repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
forflo/yodl
|
vhdlpp/vhdl_testfiles/netlist_gen_simple02.vhd
|
1
|
637
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
begin
-- sum <= A xor B xor carryIn;
sum <= '0';
carryOut <= (a and b) or
(b and carryIn) or
(a and carryIn) >
(not ('0' < '1') =
not ('1' > '0'));
fnord <= ('1' or '0') and '1';
end behv;
|
gpl-3.0
|
forflo/yodl
|
vhdlpp/vhdl_testfiles/netlist_gen_dff_complex.vhd
|
1
|
765
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
clock : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return std_logic;
begin
process(A) is
begin
if rising_edge(clock) then
case "100" is
when "000" => A <= '0';
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => B <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end if;
end process;
end behv;
|
gpl-3.0
|
forflo/yodl
|
vhdlpp/vhdl_testfiles/elsif_eliminator_nested_test.vhd
|
1
|
1045
|
-- FM. MA
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- dummy entity
entity ent is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ent;
architecture beh of ent is
signal result : std_logic_vector(n downto 0);
begin
fooProc : process is
variable baz : natural := 4711;
begin
-- with else
if (3 = 3) then
baz := 3;
-- nested :3
if (3 = 3) then
baz := 3;
elsif (4 = 4) then
baz := 4;
elsif (5 = 5) then
baz := 5;
elsif (6 = 6) then
baz := 6;
end if;
elsif (4 = 4) then
baz := 4;
elsif (5 = 5) then
baz := 5;
elsif (6 = 6) then
baz := 6;
else
baz := 100000;
end if;
end process fooProc;
end beh;
|
gpl-3.0
|
forflo/yodl
|
vhdlpp/vhdl_testfiles/parser_test_operator_symbol.vhd
|
1
|
448
|
-- parser testfile
----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dummy is
port (Cin, x, y : in std_logic;
s, Cout : out std_logic);
end dummy;
architecture a of dummy is
begin
-- of course, this makes no sense.
-- but according to p. 8.1 of VHDL-2008
-- this has to be (at least syntactically) possible
add : s <= "+" xor "*" xor "+";
end a;
|
gpl-3.0
|
alexkernphysiker/JPET-FPGA-parser
|
packet_simulation/devicefilter.vhd
|
1
|
1338
|
-- This source file was created for J-PET project in WFAIS (Jagiellonian University in Cracow)
-- License for distribution outside WFAIS UJ and J-PET project is GPL v 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity devicefilter is
port(
deviceID: in std_logic_vector(15 downto 0);
in_data: in std_logic;
clock: in std_logic;
channel_offset: out std_logic_vector(15 downto 0);
accepted: out std_logic
);
end devicefilter;
architecture Behavioral of devicefilter is
signal accept : std_logic:='0';
signal counter : integer:=0;
begin
check_device:process(in_data, clock)
begin
if rising_edge(clock) then
if in_data = '1' then
counter <= 4;
elsif accept = '1' then
accept <= '0';
elsif counter > 0 then
counter <= counter-1;
if counter = 0 then
accept <= '1';
end if;
end if;
end if;
end process check_device;
accept_device:process(accept, clock)
begin
if rising_edge(clock)then
accepted<=accept;
end if;
end process accept_device;
calculate_channel_offset:process(accept, clock)
begin
if rising_edge(clock) then
if accept='1' then
channel_offset<=deviceID;
end if;
end if;
end process calculate_channel_offset;
end Behavioral;
|
gpl-3.0
|
bruskajp/EE-316
|
Project2/Quartus_DE2Board/i2c_master_2.1.vhd
|
1
|
15693
|
--------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/1/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 Scott Larson
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 100_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC);
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL data_clk_m : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = 499) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO 124 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN 125 TO 249 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN 250 TO 324 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
-- added the following line to make sure busy = 0 in the slv_ack2 state
busy <= '0'; --continue is accepted (modified by CU)
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
-- added the following line to make sure busy = 0 in the mstr_ack state
busy <= '0'; --continue is accepted (modified by CU)
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
-- busy <= '0'; --continue is accepted (modified by CU)
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
busy <= '1'; --resume busy in the wr state (modified by CU)
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
busy <= '0'; --unflag busy (modified by CU)
sda_int <= '1'; --sets sda high impedance (modified by CU)
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
-- busy <= '0'; --continue is accepted (modified by CU)
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
busy <= '1'; --resume busy in the wr state (modified by CU)
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
busy <= '0'; --unflag busy (modified by CU)
sda_int <= '1'; --sets sda high impedance (modified by CU)
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
-- busy <= '0'; --unflag busy (modified by CU)
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
data_clk_m <= data_clk_prev and data_clk; -- Modification added at CU
WITH state SELECT
sda_ena_n <= data_clk WHEN start, --generate start condition
NOT data_clk_m WHEN stop, --generate stop condition (modification added at CU)
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
-- Following two signals will be used for tristate obuft (did not work)
-- scl <= '1' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE '0';
-- sda <= '1' WHEN sda_ena_n = '0' ELSE '0';
END logic;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Fault_Management/SHMU_prototype/version_1/TB_Package_32_bit.vhd
|
3
|
19373
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector);
procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic; signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector);
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type &
std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)));
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer;
finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector) is
-- Packet_length of 3 means it has 1 header, 1 body and 1 tail. the number of body packets are equal to Packet_length-2
-- source: id of the source node
-- destination: id of the destination node
-- packet id: packet identification number! TODO: has to be implemented!
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
variable first_time :boolean := true;
variable destination_id: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
while true loop
RTS <= '0';
if first_time = true then
for i in 0 to initial_delay loop
wait until clk'event and clk ='0';
end loop;
else
wait until clk'event and clk ='0';
end if;
--wait untill the falling edge of the clock to avoid race!
report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination);
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination) & " with length: "& integer'image(Packet_length));
writeline(VEC_FILE, LINEVARIABLE);
port_in <= Header_gen(Packet_length, source, destination, packet_id);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
for I in 0 to Packet_length-3 loop
uniform(seed1, seed2, rand);
wait until clk'event and clk ='0';
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
end loop;
wait until clk'event and clk ='0';
port_in <= Tail_gen(Packet_length, 200);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
if now > finish_time then
wait;
end if;
end loop;
end gen_packet;
procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector) is
-- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to
-- be injected. to build a true random traffic generator, we need to make a series of frames:
--
--
-- <--- Frame length-----> <--- Frame length-----> <--- Frame length----->
--
-- <-----> |<--------|///////|---->|<----|///////////|---->|<-|////|-------------->|
-- initial <-------> <----------> <------------->
-- delay frame Packet_size frame
-- initial end delay
-- delay
--
-- source: id of the source node
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
variable first_time :boolean := true;
variable id_counter : integer:= 0;
variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0;
variable destination_id: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
while true loop
-- generating the ID
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
-- generating the packet length
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
assert (3*Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure;
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
RTS <= '0';
if first_time = true then
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
-- wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
first_time := false;
else
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
end if;
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--wait untill the falling edge of the clock to avoid race!
report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id);
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " &
integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
for I in 0 to Packet_length-3 loop
uniform(seed1, seed2, rand);
wait until clk'event and clk ='0';
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
end loop;
wait until clk'event and clk ='0';
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector) is
-- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to
-- be injected. to build a true random traffic generator, we need to make a series of frames:
--
--
-- <--- Frame length-----> <--- Frame length-----> <--- Frame length----->
--
-- <-----> |<--------|///////|---->|<----|///////////|---->|<-|////|-------------->|
-- initial <-------> <----------> <------------->
-- delay frame Packet_size frame
-- initial end delay
-- delay
--
-- source: id of the source node
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
variable first_time :boolean := true;
variable id_counter : integer:= 0;
variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0;
variable destination_id: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
while true loop
-- generating the ID
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
-- generating the packet length
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)/300)*frame_length);
if (Packet_length < min_packet_size) then
Packet_length := min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length := max_packet_size;
end if;
assert (3*Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure;
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
RTS <= '0';
if first_time = true then
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
-- wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
first_time := false;
else
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
end if;
destination_id := to_integer(unsigned(not std_logic_vector(to_unsigned(source, network_size))));
if destination_id = source then
wait;
end if;
--wait untill the falling edge of the clock to avoid race!
report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id);
report " frame_size: " & integer'image(frame_length) & " packet_length: " & integer'image(Packet_length) & "starting_delay: " & integer'image(frame_starting_delay) & " ending_delay: " & integer'image(frame_ending_delay);
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " &
integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
for I in 0 to Packet_length-3 loop
uniform(seed1, seed2, rand);
wait until clk'event and clk ='0';
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
end loop;
wait until clk'event and clk ='0';
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
while true loop
counter := 0;
CTS <= '0';
wait until DRTS'event and DRTS ='1';
wait until clk'event and clk ='1';
CTS <= '1';
wait until clk'event and clk ='1';
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
P_length := to_integer(unsigned(port_in(28 downto 17)));
destination_node := to_integer(unsigned(port_in(16 downto 13)));
source_node := to_integer(unsigned(port_in(12 downto 9)));
packet_id := to_integer(unsigned(port_in(8 downto 1)));
end if;
CTS <= '0';
while (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) /= "100") loop
wait until DRTS'event and DRTS ='1';
wait until clk'event and clk ='1';
CTS <= '1';
wait until clk'event and clk ='1';
counter := counter+1;
CTS <= '0';
end loop;
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity failure;
assert (Node_ID=destination_node) report "wrong packet destination " severity failure;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length)& " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
end loop;
end get_packet;
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is
variable seed1 :positive := seed_1;
variable seed2 :positive := seed_2;
variable rand : real;
variable stuck: integer;
begin
sta_0 <= '0';
sta_1 <= '0';
while true loop
sta_0 <= '0';
sta_1 <= '0';
for I in 0 to delay loop
wait for 1 ns;
end loop;
uniform(seed1, seed2, rand);
address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5));
uniform(seed1, seed2, rand);
stuck := integer(rand*11.0);
if stuck > 5 then
sta_0 <= '1';
sta_1 <= '0';
else
sta_0 <= '0';
sta_1 <= '1';
end if;
wait for 2 ns;
end loop;
end gen_fault;
end TB_Package;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Fault_Management/SHMU_prototype/version_2/TB_Package_32_bit.vhd
|
3
|
19373
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer; finish_time: in time; signal clk: in std_logic; signal DCTS: in std_logic; signal RTS: out std_logic; signal port_in: out std_logic_vector);
procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic; signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector);
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type &
std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)));
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure gen_packet(Packet_length, source, destination, packet_id, initial_delay: in integer;
finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector) is
-- Packet_length of 3 means it has 1 header, 1 body and 1 tail. the number of body packets are equal to Packet_length-2
-- source: id of the source node
-- destination: id of the destination node
-- packet id: packet identification number! TODO: has to be implemented!
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
variable first_time :boolean := true;
variable destination_id: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
while true loop
RTS <= '0';
if first_time = true then
for i in 0 to initial_delay loop
wait until clk'event and clk ='0';
end loop;
else
wait until clk'event and clk ='0';
end if;
--wait untill the falling edge of the clock to avoid race!
report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination);
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination) & " with length: "& integer'image(Packet_length));
writeline(VEC_FILE, LINEVARIABLE);
port_in <= Header_gen(Packet_length, source, destination, packet_id);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
for I in 0 to Packet_length-3 loop
uniform(seed1, seed2, rand);
wait until clk'event and clk ='0';
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
end loop;
wait until clk'event and clk ='0';
port_in <= Tail_gen(Packet_length, 200);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
if now > finish_time then
wait;
end if;
end loop;
end gen_packet;
procedure gen_random_packet(frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector) is
-- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to
-- be injected. to build a true random traffic generator, we need to make a series of frames:
--
--
-- <--- Frame length-----> <--- Frame length-----> <--- Frame length----->
--
-- <-----> |<--------|///////|---->|<----|///////////|---->|<-|////|-------------->|
-- initial <-------> <----------> <------------->
-- delay frame Packet_size frame
-- initial end delay
-- delay
--
-- source: id of the source node
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
variable first_time :boolean := true;
variable id_counter : integer:= 0;
variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0;
variable destination_id: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
while true loop
-- generating the ID
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
-- generating the packet length
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
assert (3*Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure;
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
RTS <= '0';
if first_time = true then
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
-- wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
first_time := false;
else
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
end if;
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--wait untill the falling edge of the clock to avoid race!
report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id);
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " &
integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
for I in 0 to Packet_length-3 loop
uniform(seed1, seed2, rand);
wait until clk'event and clk ='0';
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
end loop;
wait until clk'event and clk ='0';
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(frame_length, source, initial_delay, network_size, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal DCTS: in std_logic; signal RTS: out std_logic;
signal port_in: out std_logic_vector) is
-- frame_length is inverse of PIR. with the unit of clock cycles. which means how many clock cycles per packet to
-- be injected. to build a true random traffic generator, we need to make a series of frames:
--
--
-- <--- Frame length-----> <--- Frame length-----> <--- Frame length----->
--
-- <-----> |<--------|///////|---->|<----|///////////|---->|<-|////|-------------->|
-- initial <-------> <----------> <------------->
-- delay frame Packet_size frame
-- initial end delay
-- delay
--
-- source: id of the source node
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
variable first_time :boolean := true;
variable id_counter : integer:= 0;
variable frame_starting_delay, Packet_length, frame_ending_delay: integer := 0;
variable destination_id: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
while true loop
-- generating the ID
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
-- generating the packet length
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)/300)*frame_length);
if (Packet_length < min_packet_size) then
Packet_length := min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length := max_packet_size;
end if;
assert (3*Packet_length<=frame_length) report "packet_length "& integer'image(Packet_length)&" exceeds frame size "& integer'image(frame_length) severity failure;
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
RTS <= '0';
if first_time = true then
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
-- wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
first_time := false;
else
wait until clk'event and clk ='1';
for k in 0 to frame_starting_delay-1 loop
--wait until clk'event and clk ='0';
wait for 1 ns;
end loop;
end if;
destination_id := to_integer(unsigned(not std_logic_vector(to_unsigned(source, network_size))));
if destination_id = source then
wait;
end if;
--wait untill the falling edge of the clock to avoid race!
report "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id);
report " frame_size: " & integer'image(frame_length) & " packet_length: " & integer'image(Packet_length) & "starting_delay: " & integer'image(frame_starting_delay) & " ending_delay: " & integer'image(frame_ending_delay);
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " &
integer'image(destination_id) & " with length: "& integer'image(Packet_length)& " with id: "&integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
for I in 0 to Packet_length-3 loop
uniform(seed1, seed2, rand);
wait until clk'event and clk ='0';
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
end loop;
wait until clk'event and clk ='0';
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
wait until clk'event and clk ='1';
RTS <= '1';
wait until DCTS'event and DCTS ='1';
wait until clk'event and clk ='1';
RTS <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait for 1 ns;
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal CTS: out std_logic; signal DRTS: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
while true loop
counter := 0;
CTS <= '0';
wait until DRTS'event and DRTS ='1';
wait until clk'event and clk ='1';
CTS <= '1';
wait until clk'event and clk ='1';
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
P_length := to_integer(unsigned(port_in(28 downto 17)));
destination_node := to_integer(unsigned(port_in(16 downto 13)));
source_node := to_integer(unsigned(port_in(12 downto 9)));
packet_id := to_integer(unsigned(port_in(8 downto 1)));
end if;
CTS <= '0';
while (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) /= "100") loop
wait until DRTS'event and DRTS ='1';
wait until clk'event and clk ='1';
CTS <= '1';
wait until clk'event and clk ='1';
counter := counter+1;
CTS <= '0';
end loop;
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity failure;
assert (Node_ID=destination_node) report "wrong packet destination " severity failure;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length)& " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
end loop;
end get_packet;
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is
variable seed1 :positive := seed_1;
variable seed2 :positive := seed_2;
variable rand : real;
variable stuck: integer;
begin
sta_0 <= '0';
sta_1 <= '0';
while true loop
sta_0 <= '0';
sta_1 <= '0';
for I in 0 to delay loop
wait for 1 ns;
end loop;
uniform(seed1, seed2, rand);
address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5));
uniform(seed1, seed2, rand);
stuck := integer(rand*11.0);
if stuck > 5 then
sta_0 <= '1';
sta_1 <= '0';
else
sta_0 <= '0';
sta_1 <= '1';
end if;
wait for 2 ns;
end loop;
end gen_fault;
end TB_Package;
|
gpl-3.0
|
Ana06/function-graphing-FPGA
|
trigo.vhd
|
2
|
16754
|
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 13:18:25 02/19/2014
-- Design Name:
-- Module Name: trigo - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity trigo is
Port ( valor : in STD_LOGIC_VECTOR (20 downto 0);
sen : out STD_LOGIC_VECTOR (20 downto 0);
cos : out STD_LOGIC_VECTOR (20 downto 0));
end trigo;
architecture Behavioral of trigo is
begin
with valor select
sen <= "000000000000000000000" when "111111100000000000000",
"111111111111111111111" when "111111100010000000000",
"000000000000000000000" when "111111100100000000000",
"000000000000000000000" when "111111100110000000000",
"000000000000000000000" when "111111101000000000000",
"111111111111111111111" when "111111101010000000000",
"000000000000000000000" when "111111101100000000000",
"111111111111111111111" when "111111101110000000000",
"000000000000000000000" when "111111110000000000000",
"000000000010000000000" when "111111110001000000000",
"111111111111111111111" when "111111110010000000000",
"111111111110000000000" when "111111110011000000000",
"000000000000000000000" when "111111110100000000000",
"000000000010000000000" when "111111110101000000000",
"111111111111111111111" when "111111110110000000000",
"111111111110000000000" when "111111110111000000000",
"000000000000000000000" when "111111111000000000000",
"000000000001011010100" when "111111111000100000000",
"000000000010000000000" when "111111111001000000000",
"000000000001011010100" when "111111111001100000000",
"111111111111111111111" when "111111111010000000000",
"111111111110100101011" when "111111111010100000000",
"111111111110000000000" when "111111111011000000000",
"111111111110100101011" when "111111111011100000000",
"000000000000000000000" when "111111111100000000000",
"000000000000110000111" when "111111111100010000000",
"000000000001011010100" when "111111111100100000000",
"000000000001110110010" when "111111111100110000000",
"000000000010000000000" when "111111111101000000000",
"000000000001110110010" when "111111111101010000000",
"000000000001011010100" when "111111111101100000000",
"000000000000110000111" when "111111111101110000000",
"111111111111111111111" when "111111111110000000000",
"111111111111100111000" when "111111111110001000000",
"111111111111001111000" when "111111111110010000000",
"111111111110111000111" when "111111111110011000000",
"111111111110100101011" when "111111111110100000000",
"111111111110010101100" when "111111111110101000000",
"111111111110001001101" when "111111111110110000000",
"111111111110000010011" when "111111111110111000000",
"111111111110000000000" when "111111111111000000000",
"111111111110000010011" when "111111111111001000000",
"111111111110001001101" when "111111111111010000000",
"111111111110010101100" when "111111111111011000000",
"111111111110100101011" when "111111111111100000000",
"111111111110111000111" when "111111111111101000000",
"111111111111001111000" when "111111111111110000000",
"111111111111100111000" when "111111111111111000000",
"000000000000000000000" when "000000000000000000000",
"000000000000001100100" when "000000000000000100000",
"000000000000011000111" when "000000000000001000000",
"000000000000100101001" when "000000000000001100000",
"000000000000110000111" when "000000000000010000000",
"000000000000111100010" when "000000000000010100000",
"000000000001000111000" when "000000000000011000000",
"000000000001010001001" when "000000000000011100000",
"000000000001011010100" when "000000000000100000000",
"000000000001100010111" when "000000000000100100000",
"000000000001101010011" when "000000000000101000000",
"000000000001110000111" when "000000000000101100000",
"000000000001110110010" when "000000000000110000000",
"000000000001111010011" when "000000000000110100000",
"000000000001111101100" when "000000000000111000000",
"000000000001111111011" when "000000000000111100000",
"000000000010000000000" when "000000000001000000000",
"000000000001111111011" when "000000000001000100000",
"000000000001111101100" when "000000000001001000000",
"000000000001111010011" when "000000000001001100000",
"000000000001110110010" when "000000000001010000000",
"000000000001110000111" when "000000000001010100000",
"000000000001101010011" when "000000000001011000000",
"000000000001100010111" when "000000000001011100000",
"000000000001011010100" when "000000000001100000000",
"000000000001010001001" when "000000000001100100000",
"000000000001000111000" when "000000000001101000000",
"000000000000111100010" when "000000000001101100000",
"000000000000110000111" when "000000000001110000000",
"000000000000100101001" when "000000000001110100000",
"000000000000011000111" when "000000000001111000000",
"000000000000001100100" when "000000000001111100000",
"000000000000000000000" when "000000000010000000000",
"111111111111100111000" when "000000000010001000000",
"111111111111001111000" when "000000000010010000000",
"111111111110111000111" when "000000000010011000000",
"111111111110100101011" when "000000000010100000000",
"111111111110010101100" when "000000000010101000000",
"111111111110001001101" when "000000000010110000000",
"111111111110000010011" when "000000000010111000000",
"111111111110000000000" when "000000000011000000000",
"111111111110000010011" when "000000000011001000000",
"111111111110001001101" when "000000000011010000000",
"111111111110010101100" when "000000000011011000000",
"111111111110100101011" when "000000000011100000000",
"111111111110111000111" when "000000000011101000000",
"111111111111001111000" when "000000000011110000000",
"111111111111100111000" when "000000000011111000000",
"111111111111111111111" when "000000000100000000000",
"000000000000110000111" when "000000000100010000000",
"000000000001011010100" when "000000000100100000000",
"000000000001110110010" when "000000000100110000000",
"000000000010000000000" when "000000000101000000000",
"000000000001110110010" when "000000000101010000000",
"000000000001011010100" when "000000000101100000000",
"000000000000110000111" when "000000000101110000000",
"000000000000000000000" when "000000000110000000000",
"111111111111001111000" when "000000000110010000000",
"111111111110100101011" when "000000000110100000000",
"111111111110001001101" when "000000000110110000000",
"111111111110000000000" when "000000000111000000000",
"111111111110001001101" when "000000000111010000000",
"111111111110100101011" when "000000000111100000000",
"111111111111001111000" when "000000000111110000000",
"111111111111111111111" when "000000001000000000000",
"000000000001011010100" when "000000001000100000000",
"000000000010000000000" when "000000001001000000000",
"000000000001011010100" when "000000001001100000000",
"000000000000000000000" when "000000001010000000000",
"111111111110100101011" when "000000001010100000000",
"111111111110000000000" when "000000001011000000000",
"111111111110100101011" when "000000001011100000000",
"111111111111111111111" when "000000001100000000000",
"000000000001011010100" when "000000001100100000000",
"000000000010000000000" when "000000001101000000000",
"000000000001011010100" when "000000001101100000000",
"000000000000000000000" when "000000001110000000000",
"111111111110100101011" when "000000001110100000000",
"111111111110000000000" when "000000001111000000000",
"111111111110100101011" when "000000001111100000000",
"111111111111111111111" when "000000010000000000000",
"000000000010000000000" when "000000010001000000000",
"000000000000000000000" when "000000010010000000000",
"111111111110000000000" when "000000010011000000000",
"111111111111111111111" when "000000010100000000000",
"000000000010000000000" when "000000010101000000000",
"000000000000000000000" when "000000010110000000000",
"111111111110000000000" when "000000010111000000000",
"111111111111111111111" when "000000011000000000000",
"000000000010000000000" when "000000011001000000000",
"111111111111111111111" when "000000011010000000000",
"111111111110000000000" when "000000011011000000000",
"111111111111111111111" when "000000011100000000000",
"000000000010000000000" when "000000011101000000000",
"000000000000000000000" when "000000011110000000000",
"111111111110000000000" when "000000011111000000000",
"111111111111111111111" when "000000100000000000000",
"000000000000000000000" when others;
with valor select
cos <= "000000000010000000000" when "111111100000000000000",
"111111111110000000000" when "111111100010000000000",
"000000000010000000000" when "111111100100000000000",
"111111111110000000000" when "111111100110000000000",
"000000000010000000000" when "111111101000000000000",
"111111111110000000000" when "111111101010000000000",
"000000000010000000000" when "111111101100000000000",
"111111111110000000000" when "111111101110000000000",
"000000000010000000000" when "111111110000000000000",
"111111111111111111111" when "111111110001000000000",
"111111111110000000000" when "111111110010000000000",
"111111111111111111111" when "111111110011000000000",
"000000000010000000000" when "111111110100000000000",
"111111111111111111111" when "111111110101000000000",
"111111111110000000000" when "111111110110000000000",
"000000000000000000000" when "111111110111000000000",
"000000000010000000000" when "111111111000000000000",
"000000000001011010100" when "111111111000100000000",
"111111111111111111111" when "111111111001000000000",
"111111111110100101011" when "111111111001100000000",
"111111111110000000000" when "111111111010000000000",
"111111111110100101011" when "111111111010100000000",
"000000000000000000000" when "111111111011000000000",
"000000000001011010100" when "111111111011100000000",
"000000000010000000000" when "111111111100000000000",
"000000000001110110010" when "111111111100010000000",
"000000000001011010100" when "111111111100100000000",
"000000000000110000111" when "111111111100110000000",
"111111111111111111111" when "111111111101000000000",
"111111111111001111000" when "111111111101010000000",
"111111111110100101011" when "111111111101100000000",
"111111111110001001101" when "111111111101110000000",
"111111111110000000000" when "111111111110000000000",
"111111111110000010011" when "111111111110001000000",
"111111111110001001101" when "111111111110010000000",
"111111111110010101100" when "111111111110011000000",
"111111111110100101011" when "111111111110100000000",
"111111111110111000111" when "111111111110101000000",
"111111111111001111000" when "111111111110110000000",
"111111111111100111000" when "111111111110111000000",
"000000000000000000000" when "111111111111000000000",
"000000000000011000111" when "111111111111001000000",
"000000000000110000111" when "111111111111010000000",
"000000000001000111000" when "111111111111011000000",
"000000000001011010100" when "111111111111100000000",
"000000000001101010011" when "111111111111101000000",
"000000000001110110010" when "111111111111110000000",
"000000000001111101100" when "111111111111111000000",
"000000000010000000000" when "000000000000000000000",
"000000000001111111011" when "000000000000000100000",
"000000000001111101100" when "000000000000001000000",
"000000000001111010011" when "000000000000001100000",
"000000000001110110010" when "000000000000010000000",
"000000000001110000111" when "000000000000010100000",
"000000000001101010011" when "000000000000011000000",
"000000000001100010111" when "000000000000011100000",
"000000000001011010100" when "000000000000100000000",
"000000000001010001001" when "000000000000100100000",
"000000000001000111000" when "000000000000101000000",
"000000000000111100010" when "000000000000101100000",
"000000000000110000111" when "000000000000110000000",
"000000000000100101001" when "000000000000110100000",
"000000000000011000111" when "000000000000111000000",
"000000000000001100100" when "000000000000111100000",
"000000000000000000000" when "000000000001000000000",
"111111111111110011011" when "000000000001000100000",
"111111111111100111000" when "000000000001001000000",
"111111111111011010110" when "000000000001001100000",
"111111111111001111000" when "000000000001010000000",
"111111111111000011101" when "000000000001010100000",
"111111111110111000111" when "000000000001011000000",
"111111111110101110110" when "000000000001011100000",
"111111111110100101011" when "000000000001100000000",
"111111111110011101000" when "000000000001100100000",
"111111111110010101100" when "000000000001101000000",
"111111111110001111000" when "000000000001101100000",
"111111111110001001101" when "000000000001110000000",
"111111111110000101100" when "000000000001110100000",
"111111111110000010011" when "000000000001111000000",
"111111111110000000100" when "000000000001111100000",
"111111111110000000000" when "000000000010000000000",
"111111111110000010011" when "000000000010001000000",
"111111111110001001101" when "000000000010010000000",
"111111111110010101100" when "000000000010011000000",
"111111111110100101011" when "000000000010100000000",
"111111111110111000111" when "000000000010101000000",
"111111111111001111000" when "000000000010110000000",
"111111111111100111000" when "000000000010111000000",
"111111111111111111111" when "000000000011000000000",
"000000000000011000111" when "000000000011001000000",
"000000000000110000111" when "000000000011010000000",
"000000000001000111000" when "000000000011011000000",
"000000000001011010100" when "000000000011100000000",
"000000000001101010011" when "000000000011101000000",
"000000000001110110010" when "000000000011110000000",
"000000000001111101100" when "000000000011111000000",
"000000000010000000000" when "000000000100000000000",
"000000000001110110010" when "000000000100010000000",
"000000000001011010100" when "000000000100100000000",
"000000000000110000111" when "000000000100110000000",
"000000000000000000000" when "000000000101000000000",
"111111111111001111000" when "000000000101010000000",
"111111111110100101011" when "000000000101100000000",
"111111111110001001101" when "000000000101110000000",
"111111111110000000000" when "000000000110000000000",
"111111111110001001101" when "000000000110010000000",
"111111111110100101011" when "000000000110100000000",
"111111111111001111000" when "000000000110110000000",
"111111111111111111111" when "000000000111000000000",
"000000000000110000111" when "000000000111010000000",
"000000000001011010100" when "000000000111100000000",
"000000000001110110010" when "000000000111110000000",
"000000000010000000000" when "000000001000000000000",
"000000000001011010100" when "000000001000100000000",
"000000000000000000000" when "000000001001000000000",
"111111111110100101011" when "000000001001100000000",
"111111111110000000000" when "000000001010000000000",
"111111111110100101011" when "000000001010100000000",
"111111111111111111111" when "000000001011000000000",
"000000000001011010100" when "000000001011100000000",
"000000000010000000000" when "000000001100000000000",
"000000000001011010100" when "000000001100100000000",
"111111111111111111111" when "000000001101000000000",
"111111111110100101011" when "000000001101100000000",
"111111111110000000000" when "000000001110000000000",
"111111111110100101011" when "000000001110100000000",
"111111111111111111111" when "000000001111000000000",
"000000000001011010100" when "000000001111100000000",
"000000000010000000000" when "000000010000000000000",
"111111111111111111111" when "000000010001000000000",
"111111111110000000000" when "000000010010000000000",
"111111111111111111111" when "000000010011000000000",
"000000000010000000000" when "000000010100000000000",
"111111111111111111111" when "000000010101000000000",
"111111111110000000000" when "000000010110000000000",
"111111111111111111111" when "000000010111000000000",
"000000000010000000000" when "000000011000000000000",
"111111111111111111111" when "000000011001000000000",
"111111111110000000000" when "000000011010000000000",
"111111111111111111111" when "000000011011000000000",
"000000000010000000000" when "000000011100000000000",
"111111111111111111111" when "000000011101000000000",
"111111111110000000000" when "000000011110000000000",
"111111111111111111111" when "000000011111000000000",
"000000000010000000000" when "000000100000000000000",
"000000000000000000000" when others;
end Behavioral;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Hand_Shaking/Hand_Shaking_FC/Router_32_bit_parity_with_dominant_checkers.vhd
|
1
|
70643
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
fault_out_N, fault_out_E, fault_out_W, fault_out_S, fault_out_L:out std_logic
);
end router_parity;
architecture behavior of router_parity is
COMPONENT parity_checker is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
fault_out: out std_logic
);
end COMPONENT;
COMPONENT FIFO
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
-- Signals related to Checkers
-- LBDR Checkers signals
-- North
signal N_err_header_empty_Requests_FF_Requests_in,
N_err_tail_Requests_in_all_zero,
N_err_header_tail_Requests_FF_Requests_in,
N_err_dst_addr_cur_addr_N1,
N_err_dst_addr_cur_addr_not_N1,
N_err_dst_addr_cur_addr_E1,
N_err_dst_addr_cur_addr_not_E1,
N_err_dst_addr_cur_addr_W1,
N_err_dst_addr_cur_addr_not_W1,
N_err_dst_addr_cur_addr_S1,
N_err_dst_addr_cur_addr_not_S1,
N_err_dst_addr_cur_addr_not_Req_L_in,
N_err_dst_addr_cur_addr_Req_L_in,
N_err_header_not_empty_Req_N_in,
N_err_header_not_empty_Req_E_in,
N_err_header_not_empty_Req_W_in,
N_err_header_not_empty_Req_S_in : std_logic;
-- East
signal E_err_header_empty_Requests_FF_Requests_in,
E_err_tail_Requests_in_all_zero,
E_err_header_tail_Requests_FF_Requests_in,
E_err_dst_addr_cur_addr_N1,
E_err_dst_addr_cur_addr_not_N1,
E_err_dst_addr_cur_addr_E1,
E_err_dst_addr_cur_addr_not_E1,
E_err_dst_addr_cur_addr_W1,
E_err_dst_addr_cur_addr_not_W1,
E_err_dst_addr_cur_addr_S1,
E_err_dst_addr_cur_addr_not_S1,
E_err_dst_addr_cur_addr_not_Req_L_in,
E_err_dst_addr_cur_addr_Req_L_in,
E_err_header_not_empty_Req_N_in,
E_err_header_not_empty_Req_E_in,
E_err_header_not_empty_Req_W_in,
E_err_header_not_empty_Req_S_in : std_logic;
-- West
signal W_err_header_empty_Requests_FF_Requests_in,
W_err_tail_Requests_in_all_zero,
W_err_header_tail_Requests_FF_Requests_in,
W_err_dst_addr_cur_addr_N1,
W_err_dst_addr_cur_addr_not_N1,
W_err_dst_addr_cur_addr_E1,
W_err_dst_addr_cur_addr_not_E1,
W_err_dst_addr_cur_addr_W1,
W_err_dst_addr_cur_addr_not_W1,
W_err_dst_addr_cur_addr_S1,
W_err_dst_addr_cur_addr_not_S1,
W_err_dst_addr_cur_addr_not_Req_L_in,
W_err_dst_addr_cur_addr_Req_L_in,
W_err_header_not_empty_Req_N_in,
W_err_header_not_empty_Req_E_in,
W_err_header_not_empty_Req_W_in,
W_err_header_not_empty_Req_S_in : std_logic;
-- South
signal S_err_header_empty_Requests_FF_Requests_in,
S_err_tail_Requests_in_all_zero,
S_err_header_tail_Requests_FF_Requests_in,
S_err_dst_addr_cur_addr_N1,
S_err_dst_addr_cur_addr_not_N1,
S_err_dst_addr_cur_addr_E1,
S_err_dst_addr_cur_addr_not_E1,
S_err_dst_addr_cur_addr_W1,
S_err_dst_addr_cur_addr_not_W1,
S_err_dst_addr_cur_addr_S1,
S_err_dst_addr_cur_addr_not_S1,
S_err_dst_addr_cur_addr_not_Req_L_in,
S_err_dst_addr_cur_addr_Req_L_in,
S_err_header_not_empty_Req_N_in,
S_err_header_not_empty_Req_E_in,
S_err_header_not_empty_Req_W_in,
S_err_header_not_empty_Req_S_in : std_logic;
-- Local
signal L_err_header_empty_Requests_FF_Requests_in,
L_err_tail_Requests_in_all_zero,
L_err_header_tail_Requests_FF_Requests_in,
L_err_dst_addr_cur_addr_N1,
L_err_dst_addr_cur_addr_not_N1,
L_err_dst_addr_cur_addr_E1,
L_err_dst_addr_cur_addr_not_E1,
L_err_dst_addr_cur_addr_W1,
L_err_dst_addr_cur_addr_not_W1,
L_err_dst_addr_cur_addr_S1,
L_err_dst_addr_cur_addr_not_S1,
L_err_dst_addr_cur_addr_not_Req_L_in,
L_err_dst_addr_cur_addr_Req_L_in,
L_err_header_not_empty_Req_N_in,
L_err_header_not_empty_Req_E_in,
L_err_header_not_empty_Req_W_in,
L_err_header_not_empty_Req_S_in : std_logic;
-- Arbiter Checkers signals
-- North
signal N_err_state_IDLE_xbar,
N_err_state_not_IDLE_xbar,
N_err_state_IDLE_RTS_FF_in,
N_err_state_not_IDLE_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
N_err_RTS_FF_not_DCTS_state_state_in,
N_err_not_RTS_FF_state_in_next_state,
N_err_RTS_FF_DCTS_state_in_next_state,
N_err_not_DCTS_Grants,
N_err_DCTS_not_RTS_FF_Grants,
N_err_DCTS_RTS_FF_IDLE_Grants,
N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
N_err_Requests_next_state_IDLE,
N_err_IDLE_Req_L,
N_err_Local_Req_L,
N_err_North_Req_N,
N_err_IDLE_Req_N,
N_err_Local_Req_N,
N_err_South_Req_L,
N_err_West_Req_L,
N_err_South_Req_N,
N_err_East_Req_L,
N_err_West_Req_N,
N_err_East_Req_N,
N_err_next_state_onehot,
N_err_state_in_onehot,
N_err_state_north_xbar_sel,
N_err_state_east_xbar_sel,
N_err_state_west_xbar_sel,
N_err_state_south_xbar_sel : std_logic;
-- East
signal E_err_state_IDLE_xbar,
E_err_state_not_IDLE_xbar,
E_err_state_IDLE_RTS_FF_in,
E_err_state_not_IDLE_RTS_FF_RTS_FF_in,
E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
E_err_RTS_FF_not_DCTS_state_state_in,
E_err_not_RTS_FF_state_in_next_state,
E_err_RTS_FF_DCTS_state_in_next_state,
E_err_not_DCTS_Grants,
E_err_DCTS_not_RTS_FF_Grants,
E_err_DCTS_RTS_FF_IDLE_Grants,
E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
E_err_Requests_next_state_IDLE,
E_err_IDLE_Req_L,
E_err_Local_Req_L,
E_err_North_Req_N,
E_err_IDLE_Req_N,
E_err_Local_Req_N,
E_err_South_Req_L,
E_err_West_Req_L,
E_err_South_Req_N,
E_err_East_Req_L,
E_err_West_Req_N,
E_err_East_Req_N,
E_err_next_state_onehot,
E_err_state_in_onehot,
E_err_state_north_xbar_sel,
E_err_state_east_xbar_sel,
E_err_state_west_xbar_sel,
E_err_state_south_xbar_sel : std_logic;
-- West
signal W_err_state_IDLE_xbar,
W_err_state_not_IDLE_xbar,
W_err_state_IDLE_RTS_FF_in,
W_err_state_not_IDLE_RTS_FF_RTS_FF_in,
W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
W_err_RTS_FF_not_DCTS_state_state_in,
W_err_not_RTS_FF_state_in_next_state,
W_err_RTS_FF_DCTS_state_in_next_state,
W_err_not_DCTS_Grants,
W_err_DCTS_not_RTS_FF_Grants,
W_err_DCTS_RTS_FF_IDLE_Grants,
W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
W_err_Requests_next_state_IDLE,
W_err_IDLE_Req_L,
W_err_Local_Req_L,
W_err_North_Req_N,
W_err_IDLE_Req_N,
W_err_Local_Req_N,
W_err_South_Req_L,
W_err_West_Req_L,
W_err_South_Req_N,
W_err_East_Req_L,
W_err_West_Req_N,
W_err_East_Req_N,
W_err_next_state_onehot,
W_err_state_in_onehot,
W_err_state_north_xbar_sel,
W_err_state_east_xbar_sel,
W_err_state_west_xbar_sel,
W_err_state_south_xbar_sel : std_logic;
-- South
signal S_err_state_IDLE_xbar,
S_err_state_not_IDLE_xbar,
S_err_state_IDLE_RTS_FF_in,
S_err_state_not_IDLE_RTS_FF_RTS_FF_in,
S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
S_err_RTS_FF_not_DCTS_state_state_in,
S_err_not_RTS_FF_state_in_next_state,
S_err_RTS_FF_DCTS_state_in_next_state,
S_err_not_DCTS_Grants,
S_err_DCTS_not_RTS_FF_Grants,
S_err_DCTS_RTS_FF_IDLE_Grants,
S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
S_err_Requests_next_state_IDLE,
S_err_IDLE_Req_L,
S_err_Local_Req_L,
S_err_North_Req_N,
S_err_IDLE_Req_N,
S_err_Local_Req_N,
S_err_South_Req_L,
S_err_West_Req_L,
S_err_South_Req_N,
S_err_East_Req_L,
S_err_West_Req_N,
S_err_East_Req_N,
S_err_next_state_onehot,
S_err_state_in_onehot,
S_err_state_north_xbar_sel,
S_err_state_east_xbar_sel,
S_err_state_west_xbar_sel,
S_err_state_south_xbar_sel : std_logic;
-- Local
signal L_err_state_IDLE_xbar,
L_err_state_not_IDLE_xbar,
L_err_state_IDLE_RTS_FF_in,
L_err_state_not_IDLE_RTS_FF_RTS_FF_in,
L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
L_err_RTS_FF_not_DCTS_state_state_in,
L_err_not_RTS_FF_state_in_next_state,
L_err_RTS_FF_DCTS_state_in_next_state,
L_err_not_DCTS_Grants,
L_err_DCTS_not_RTS_FF_Grants,
L_err_DCTS_RTS_FF_IDLE_Grants,
L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
L_err_Requests_next_state_IDLE,
L_err_IDLE_Req_L,
L_err_Local_Req_L,
L_err_North_Req_N,
L_err_IDLE_Req_N,
L_err_Local_Req_N,
L_err_South_Req_L,
L_err_West_Req_L,
L_err_South_Req_N,
L_err_East_Req_L,
L_err_West_Req_N,
L_err_East_Req_N,
L_err_next_state_onehot,
L_err_state_in_onehot,
L_err_state_north_xbar_sel,
L_err_state_east_xbar_sel,
L_err_state_west_xbar_sel,
L_err_state_south_xbar_sel : std_logic;
-- FIFO Control Part Checkers signals
-- North
signal N_err_write_en_write_pointer,
N_err_not_write_en_write_pointer,
N_err_read_pointer_write_pointer_not_empty,
N_err_read_pointer_write_pointer_empty,
N_err_read_pointer_write_pointer_not_full,
N_err_read_pointer_write_pointer_full,
N_err_read_pointer_increment,
N_err_read_pointer_not_increment,
N_err_write_en,
N_err_not_CTS_in,
N_err_read_en_mismatch : std_logic;
-- East
signal E_err_write_en_write_pointer,
E_err_not_write_en_write_pointer,
E_err_read_pointer_write_pointer_not_empty,
E_err_read_pointer_write_pointer_empty,
E_err_read_pointer_write_pointer_not_full,
E_err_read_pointer_write_pointer_full,
E_err_read_pointer_increment,
E_err_read_pointer_not_increment,
E_err_write_en,
E_err_not_CTS_in,
E_err_read_en_mismatch : std_logic;
-- West
signal W_err_write_en_write_pointer,
W_err_not_write_en_write_pointer,
W_err_read_pointer_write_pointer_not_empty,
W_err_read_pointer_write_pointer_empty,
W_err_read_pointer_write_pointer_not_full,
W_err_read_pointer_write_pointer_full,
W_err_read_pointer_increment,
W_err_read_pointer_not_increment,
W_err_write_en,
W_err_not_CTS_in,
W_err_read_en_mismatch : std_logic;
-- South
signal S_err_write_en_write_pointer,
S_err_not_write_en_write_pointer,
S_err_read_pointer_write_pointer_not_empty,
S_err_read_pointer_write_pointer_empty,
S_err_read_pointer_write_pointer_not_full,
S_err_read_pointer_write_pointer_full,
S_err_read_pointer_increment,
S_err_read_pointer_not_increment,
S_err_write_en,
S_err_not_CTS_in,
S_err_read_en_mismatch : std_logic;
-- Local
signal L_err_write_en_write_pointer,
L_err_not_write_en_write_pointer,
L_err_read_pointer_write_pointer_not_empty,
L_err_read_pointer_write_pointer_empty,
L_err_read_pointer_write_pointer_not_full,
L_err_read_pointer_write_pointer_full,
L_err_read_pointer_increment,
L_err_read_pointer_not_increment,
L_err_write_en,
L_err_not_CTS_in,
L_err_read_en_mismatch : std_logic;
-- Error Signals for each module (ORed combination of checker outputs)
signal N_LBDR_checkers_output,
E_LBDR_checkers_output,
W_LBDR_checkers_output,
S_LBDR_checkers_output,
L_LBDR_checkers_output: std_logic;
signal N_Arbiter_checkers_output,
E_Arbiter_checkers_output,
W_Arbiter_checkers_output,
S_Arbiter_checkers_output,
L_Arbiter_checkers_output: std_logic;
signal N_FIFO_control_part_checkers_output,
E_FIFO_control_part_checkers_output,
W_FIFO_control_part_checkers_output,
S_FIFO_control_part_checkers_output,
L_FIFO_control_part_checkers_output: std_logic;
begin
-- OR of checker outputs for each module (corresponding to each direction)
-- This is used for feeding the checker outputs to shift registers (later)
-- LBDR
N_LBDR_checkers_output <= N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_N1 or
N_err_dst_addr_cur_addr_not_N1 or
N_err_dst_addr_cur_addr_E1 or
N_err_dst_addr_cur_addr_not_E1 or
N_err_dst_addr_cur_addr_W1 or
N_err_dst_addr_cur_addr_not_W1 or
N_err_dst_addr_cur_addr_S1 or
N_err_dst_addr_cur_addr_not_S1 or
N_err_dst_addr_cur_addr_not_Req_L_in or
N_err_dst_addr_cur_addr_Req_L_in or
N_err_header_not_empty_Req_N_in or
N_err_header_not_empty_Req_E_in or
N_err_header_not_empty_Req_W_in or
N_err_header_not_empty_Req_S_in;
E_LBDR_checkers_output <= E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_N1 or
E_err_dst_addr_cur_addr_not_N1 or
E_err_dst_addr_cur_addr_E1 or
E_err_dst_addr_cur_addr_not_E1 or
E_err_dst_addr_cur_addr_W1 or
E_err_dst_addr_cur_addr_not_W1 or
E_err_dst_addr_cur_addr_S1 or
E_err_dst_addr_cur_addr_not_S1 or
E_err_dst_addr_cur_addr_not_Req_L_in or
E_err_dst_addr_cur_addr_Req_L_in or
E_err_header_not_empty_Req_N_in or
E_err_header_not_empty_Req_E_in or
E_err_header_not_empty_Req_W_in or
E_err_header_not_empty_Req_S_in;
W_LBDR_checkers_output <= W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_N1 or
W_err_dst_addr_cur_addr_not_N1 or
W_err_dst_addr_cur_addr_E1 or
W_err_dst_addr_cur_addr_not_E1 or
W_err_dst_addr_cur_addr_W1 or
W_err_dst_addr_cur_addr_not_W1 or
W_err_dst_addr_cur_addr_S1 or
W_err_dst_addr_cur_addr_not_S1 or
W_err_dst_addr_cur_addr_not_Req_L_in or
W_err_dst_addr_cur_addr_Req_L_in or
W_err_header_not_empty_Req_N_in or
W_err_header_not_empty_Req_E_in or
W_err_header_not_empty_Req_W_in or
W_err_header_not_empty_Req_S_in;
S_LBDR_checkers_output <= S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_N1 or
S_err_dst_addr_cur_addr_not_N1 or
S_err_dst_addr_cur_addr_E1 or
S_err_dst_addr_cur_addr_not_E1 or
S_err_dst_addr_cur_addr_W1 or
S_err_dst_addr_cur_addr_not_W1 or
S_err_dst_addr_cur_addr_S1 or
S_err_dst_addr_cur_addr_not_S1 or
S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_dst_addr_cur_addr_Req_L_in or
S_err_header_not_empty_Req_N_in or
S_err_header_not_empty_Req_E_in or
S_err_header_not_empty_Req_W_in or
S_err_header_not_empty_Req_S_in;
L_LBDR_checkers_output <= L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_header_tail_Requests_FF_Requests_in or
L_err_dst_addr_cur_addr_N1 or
L_err_dst_addr_cur_addr_not_N1 or
L_err_dst_addr_cur_addr_E1 or
L_err_dst_addr_cur_addr_not_E1 or
L_err_dst_addr_cur_addr_W1 or
L_err_dst_addr_cur_addr_not_W1 or
L_err_dst_addr_cur_addr_S1 or
L_err_dst_addr_cur_addr_not_S1 or
L_err_dst_addr_cur_addr_not_Req_L_in or
L_err_dst_addr_cur_addr_Req_L_in or
L_err_header_not_empty_Req_N_in or
L_err_header_not_empty_Req_E_in or
L_err_header_not_empty_Req_W_in or
L_err_header_not_empty_Req_S_in;
-- Arbiter
N_Arbiter_checkers_output <= N_err_state_IDLE_xbar or
N_err_state_not_IDLE_xbar or
N_err_state_IDLE_RTS_FF_in or
N_err_state_not_IDLE_RTS_FF_RTS_FF_in or
N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
N_err_RTS_FF_not_DCTS_state_state_in or
N_err_not_RTS_FF_state_in_next_state or
N_err_RTS_FF_DCTS_state_in_next_state or
N_err_not_DCTS_Grants or
N_err_DCTS_not_RTS_FF_Grants or
N_err_DCTS_RTS_FF_IDLE_Grants or
N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
N_err_Requests_next_state_IDLE or
N_err_IDLE_Req_L or
N_err_Local_Req_L or
N_err_North_Req_N or
N_err_IDLE_Req_N or
N_err_Local_Req_N or
N_err_South_Req_L or
N_err_West_Req_L or
N_err_South_Req_N or
N_err_East_Req_L or
N_err_West_Req_N or
N_err_East_Req_N or
N_err_next_state_onehot or
N_err_state_in_onehot or
N_err_state_north_xbar_sel or
N_err_state_east_xbar_sel or
N_err_state_west_xbar_sel or
N_err_state_south_xbar_sel;
E_Arbiter_checkers_output <= E_err_state_IDLE_xbar or
E_err_state_not_IDLE_xbar or
E_err_state_IDLE_RTS_FF_in or
E_err_state_not_IDLE_RTS_FF_RTS_FF_in or
E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
E_err_RTS_FF_not_DCTS_state_state_in or
E_err_not_RTS_FF_state_in_next_state or
E_err_RTS_FF_DCTS_state_in_next_state or
E_err_not_DCTS_Grants or
E_err_DCTS_not_RTS_FF_Grants or
E_err_DCTS_RTS_FF_IDLE_Grants or
E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
E_err_Requests_next_state_IDLE or
E_err_IDLE_Req_L or
E_err_Local_Req_L or
E_err_North_Req_N or
E_err_IDLE_Req_N or
E_err_Local_Req_N or
E_err_South_Req_L or
E_err_West_Req_L or
E_err_South_Req_N or
E_err_East_Req_L or
E_err_West_Req_N or
E_err_East_Req_N or
E_err_next_state_onehot or
E_err_state_in_onehot or
E_err_state_north_xbar_sel or
E_err_state_east_xbar_sel or
E_err_state_west_xbar_sel or
E_err_state_south_xbar_sel;
W_Arbiter_checkers_output <= W_err_state_IDLE_xbar or
W_err_state_not_IDLE_xbar or
W_err_state_IDLE_RTS_FF_in or
W_err_state_not_IDLE_RTS_FF_RTS_FF_in or
W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
W_err_RTS_FF_not_DCTS_state_state_in or
W_err_not_RTS_FF_state_in_next_state or
W_err_RTS_FF_DCTS_state_in_next_state or
W_err_not_DCTS_Grants or
W_err_DCTS_not_RTS_FF_Grants or
W_err_DCTS_RTS_FF_IDLE_Grants or
W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
W_err_Requests_next_state_IDLE or
W_err_IDLE_Req_L or
W_err_Local_Req_L or
W_err_North_Req_N or
W_err_IDLE_Req_N or
W_err_Local_Req_N or
W_err_South_Req_L or
W_err_West_Req_L or
W_err_South_Req_N or
W_err_East_Req_L or
W_err_West_Req_N or
W_err_East_Req_N or
W_err_next_state_onehot or
W_err_state_in_onehot or
W_err_state_north_xbar_sel or
W_err_state_east_xbar_sel or
W_err_state_west_xbar_sel or
W_err_state_south_xbar_sel;
S_Arbiter_checkers_output <= S_err_state_IDLE_xbar or
S_err_state_not_IDLE_xbar or
S_err_state_IDLE_RTS_FF_in or
S_err_state_not_IDLE_RTS_FF_RTS_FF_in or
S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
S_err_RTS_FF_not_DCTS_state_state_in or
S_err_not_RTS_FF_state_in_next_state or
S_err_RTS_FF_DCTS_state_in_next_state or
S_err_not_DCTS_Grants or
S_err_DCTS_not_RTS_FF_Grants or
S_err_DCTS_RTS_FF_IDLE_Grants or
S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
S_err_Requests_next_state_IDLE or
S_err_IDLE_Req_L or
S_err_Local_Req_L or
S_err_North_Req_N or
S_err_IDLE_Req_N or
S_err_Local_Req_N or
S_err_South_Req_L or
S_err_West_Req_L or
S_err_South_Req_N or
S_err_East_Req_L or
S_err_West_Req_N or
S_err_East_Req_N or
S_err_next_state_onehot or
S_err_state_in_onehot or
S_err_state_north_xbar_sel or
S_err_state_east_xbar_sel or
S_err_state_west_xbar_sel or
S_err_state_south_xbar_sel;
L_Arbiter_checkers_output <= L_err_state_IDLE_xbar or
L_err_state_not_IDLE_xbar or
L_err_state_IDLE_RTS_FF_in or
L_err_state_not_IDLE_RTS_FF_RTS_FF_in or
L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in or
L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in or
L_err_RTS_FF_not_DCTS_state_state_in or
L_err_not_RTS_FF_state_in_next_state or
L_err_RTS_FF_DCTS_state_in_next_state or
L_err_not_DCTS_Grants or
L_err_DCTS_not_RTS_FF_Grants or
L_err_DCTS_RTS_FF_IDLE_Grants or
L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot or
L_err_Requests_next_state_IDLE or
L_err_IDLE_Req_L or
L_err_Local_Req_L or
L_err_North_Req_N or
L_err_IDLE_Req_N or
L_err_Local_Req_N or
L_err_South_Req_L or
L_err_West_Req_L or
L_err_South_Req_N or
L_err_East_Req_L or
L_err_West_Req_N or
L_err_East_Req_N or
L_err_next_state_onehot or
L_err_state_in_onehot or
L_err_state_north_xbar_sel or
L_err_state_east_xbar_sel or
L_err_state_west_xbar_sel or
L_err_state_south_xbar_sel;
-- FIFO Control Part
N_FIFO_control_part_checkers_output <= N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_write_en or
N_err_not_CTS_in or
N_err_read_en_mismatch;
E_FIFO_control_part_checkers_output <= E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_write_en or
E_err_not_CTS_in or
E_err_read_en_mismatch;
W_FIFO_control_part_checkers_output <= W_err_write_en_write_pointer or
W_err_not_write_en_write_pointer or
W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or
W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or
W_err_read_pointer_increment or
W_err_read_pointer_not_increment or
W_err_write_en or
W_err_not_CTS_in or
W_err_read_en_mismatch;
S_FIFO_control_part_checkers_output <= S_err_write_en_write_pointer or
S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or
S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or
S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or
S_err_read_pointer_not_increment or
S_err_write_en or
S_err_not_CTS_in or
S_err_read_en_mismatch;
L_FIFO_control_part_checkers_output <= L_err_write_en_write_pointer or
L_err_not_write_en_write_pointer or
L_err_read_pointer_write_pointer_not_empty or
L_err_read_pointer_write_pointer_empty or
L_err_read_pointer_write_pointer_not_full or
L_err_read_pointer_write_pointer_full or
L_err_read_pointer_increment or
L_err_read_pointer_not_increment or
L_err_write_en or
L_err_not_CTS_in or
L_err_read_en_mismatch;
------------------------------------------------------------------------------------------------------------------------------
-- block diagram of one channel
--
-- .____________grant_________
-- | ▲
-- | _______ __|_______
-- | | | | |
-- | | LBDR |---req--->| Arbiter | <--handshake-->
-- | |_______| |__________| signals
-- | ▲ |
-- __▼___ | flit ___▼__
-- RX ----->| | | type | |
-- <-handshake->| FIFO |---o------------->| |-----> TX
-- signals |______| ------>| |
-- ------>| XBAR |
-- ------>| |
-- ------>| |
-- |______|
--
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the parity_checkers
PC_N: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_N, DRTS =>DRTS_N, fault_out => fault_out_N);
PC_E: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_E, DRTS =>DRTS_E, fault_out => fault_out_E);
PC_W: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_W, DRTS =>DRTS_W, fault_out => fault_out_W);
PC_S: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_S, DRTS =>DRTS_S, fault_out => fault_out_S);
PC_L: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_L, DRTS =>DRTS_L, fault_out => fault_out_L);
-- all the FIFOs
FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N,
err_write_en_write_pointer => N_err_write_en_write_pointer,
err_not_write_en_write_pointer => N_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full,
err_read_pointer_increment => N_err_read_pointer_increment,
err_read_pointer_not_increment => N_err_read_pointer_not_increment,
err_write_en => N_err_write_en,
err_not_CTS_in => N_err_not_CTS_in,
err_read_en_mismatch => N_err_read_en_mismatch
);
FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E,
err_write_en_write_pointer => E_err_write_en_write_pointer,
err_not_write_en_write_pointer => E_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full,
err_read_pointer_increment => E_err_read_pointer_increment,
err_read_pointer_not_increment => E_err_read_pointer_not_increment,
err_write_en => E_err_write_en,
err_not_CTS_in => E_err_not_CTS_in,
err_read_en_mismatch => E_err_read_en_mismatch
);
FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W,
err_write_en_write_pointer => W_err_write_en_write_pointer,
err_not_write_en_write_pointer => W_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full,
err_read_pointer_increment => W_err_read_pointer_increment,
err_read_pointer_not_increment => W_err_read_pointer_not_increment,
err_write_en => W_err_write_en,
err_not_CTS_in => W_err_not_CTS_in,
err_read_en_mismatch => W_err_read_en_mismatch
);
FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S,
err_write_en_write_pointer => S_err_write_en_write_pointer,
err_not_write_en_write_pointer => S_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full,
err_read_pointer_increment => S_err_read_pointer_increment,
err_read_pointer_not_increment => S_err_read_pointer_not_increment,
err_write_en => S_err_write_en,
err_not_CTS_in => S_err_not_CTS_in,
err_read_en_mismatch => S_err_read_en_mismatch
);
FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L,
err_write_en_write_pointer => L_err_write_en_write_pointer,
err_not_write_en_write_pointer => L_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full,
err_read_pointer_increment => L_err_read_pointer_increment,
err_read_pointer_not_increment => L_err_read_pointer_not_increment,
err_write_en => L_err_write_en,
err_not_CTS_in => L_err_not_CTS_in,
err_read_en_mismatch => L_err_read_en_mismatch
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in
);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in
);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_n_in,
err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in
);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in
);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_N: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN,
DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL,
Xbar_sel => Xbar_sel_N,
RTS => RTS_N,
err_state_IDLE_xbar => N_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => N_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => N_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => N_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => N_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => N_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => N_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => N_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => N_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => N_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => N_err_IDLE_Req_L ,
err_Local_Req_L => N_err_Local_Req_L ,
err_North_Req_N => N_err_North_Req_N ,
err_IDLE_Req_N => N_err_IDLE_Req_N ,
err_Local_Req_N => N_err_Local_Req_N ,
err_South_Req_L => N_err_South_Req_L ,
err_West_Req_L => N_err_West_Req_L ,
err_South_Req_N => N_err_South_Req_N ,
err_East_Req_L => N_err_East_Req_L ,
err_West_Req_N => N_err_West_Req_N ,
err_East_Req_N => N_err_East_Req_N ,
err_next_state_onehot => N_err_next_state_onehot ,
err_state_in_onehot => N_err_state_in_onehot ,
err_state_north_xbar_sel => N_err_state_north_xbar_sel ,
err_state_east_xbar_sel => N_err_state_east_xbar_sel ,
err_state_west_xbar_sel => N_err_state_west_xbar_sel ,
err_state_south_xbar_sel => N_err_state_south_xbar_sel
);
Arbiter_E: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE,
DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL,
Xbar_sel => Xbar_sel_E,
RTS => RTS_E,
err_state_IDLE_xbar => E_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => E_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => E_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => E_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => E_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => E_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => E_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => E_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => E_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => E_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => E_err_IDLE_Req_L ,
err_Local_Req_L => E_err_Local_Req_L ,
err_North_Req_N => E_err_North_Req_N ,
err_IDLE_Req_N => E_err_IDLE_Req_N ,
err_Local_Req_N => E_err_Local_Req_N ,
err_South_Req_L => E_err_South_Req_L ,
err_West_Req_L => E_err_West_Req_L ,
err_South_Req_N => E_err_South_Req_N ,
err_East_Req_L => E_err_East_Req_L ,
err_West_Req_N => E_err_West_Req_N ,
err_East_Req_N => E_err_East_Req_N ,
err_next_state_onehot => E_err_next_state_onehot ,
err_state_in_onehot => E_err_state_in_onehot ,
err_state_north_xbar_sel => E_err_state_north_xbar_sel ,
err_state_east_xbar_sel => E_err_state_east_xbar_sel ,
err_state_west_xbar_sel => E_err_state_west_xbar_sel ,
err_state_south_xbar_sel => E_err_state_south_xbar_sel
);
Arbiter_W: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW,
DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL,
Xbar_sel => Xbar_sel_W,
RTS => RTS_W,
err_state_IDLE_xbar => W_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => W_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => W_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => W_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => W_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => W_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => W_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => W_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => W_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => W_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => W_err_IDLE_Req_L ,
err_Local_Req_L => W_err_Local_Req_L ,
err_North_Req_N => W_err_North_Req_N ,
err_IDLE_Req_N => W_err_IDLE_Req_N ,
err_Local_Req_N => W_err_Local_Req_N ,
err_South_Req_L => W_err_South_Req_L ,
err_West_Req_L => W_err_West_Req_L ,
err_South_Req_N => W_err_South_Req_N ,
err_East_Req_L => W_err_East_Req_L ,
err_West_Req_N => W_err_West_Req_N ,
err_East_Req_N => W_err_East_Req_N ,
err_next_state_onehot => W_err_next_state_onehot ,
err_state_in_onehot => W_err_state_in_onehot ,
err_state_north_xbar_sel => W_err_state_north_xbar_sel ,
err_state_east_xbar_sel => W_err_state_east_xbar_sel ,
err_state_west_xbar_sel => W_err_state_west_xbar_sel ,
err_state_south_xbar_sel => W_err_state_south_xbar_sel
);
Arbiter_S: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS,
DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL,
Xbar_sel => Xbar_sel_S,
RTS => RTS_S,
err_state_IDLE_xbar => S_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => S_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => S_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => S_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => S_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => S_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => S_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => S_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => S_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => S_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => S_err_IDLE_Req_L ,
err_Local_Req_L => S_err_Local_Req_L ,
err_North_Req_N => S_err_North_Req_N ,
err_IDLE_Req_N => S_err_IDLE_Req_N ,
err_Local_Req_N => S_err_Local_Req_N ,
err_South_Req_L => S_err_South_Req_L ,
err_West_Req_L => S_err_West_Req_L ,
err_South_Req_N => S_err_South_Req_N ,
err_East_Req_L => S_err_East_Req_L ,
err_West_Req_N => S_err_West_Req_N ,
err_East_Req_N => S_err_East_Req_N ,
err_next_state_onehot => S_err_next_state_onehot ,
err_state_in_onehot => S_err_state_in_onehot ,
err_state_north_xbar_sel => S_err_state_north_xbar_sel ,
err_state_east_xbar_sel => S_err_state_east_xbar_sel ,
err_state_west_xbar_sel => S_err_state_west_xbar_sel ,
err_state_south_xbar_sel => S_err_state_south_xbar_sel
);
Arbiter_L: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0',
DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL,
Xbar_sel => Xbar_sel_L,
RTS => RTS_L,
err_state_IDLE_xbar => L_err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => L_err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => L_err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => L_err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => L_err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => L_err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => L_err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => L_err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => L_err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => L_err_Requests_next_state_IDLE ,
err_IDLE_Req_L => L_err_IDLE_Req_L ,
err_Local_Req_L => L_err_Local_Req_L ,
err_North_Req_N => L_err_North_Req_N ,
err_IDLE_Req_N => L_err_IDLE_Req_N ,
err_Local_Req_N => L_err_Local_Req_N ,
err_South_Req_L => L_err_South_Req_L ,
err_West_Req_L => L_err_West_Req_L ,
err_South_Req_N => L_err_South_Req_N ,
err_East_Req_L => L_err_East_Req_L ,
err_West_Req_N => L_err_West_Req_N ,
err_East_Req_N => L_err_East_Req_N ,
err_next_state_onehot => L_err_next_state_onehot ,
err_state_in_onehot => L_err_state_in_onehot ,
err_state_north_xbar_sel => L_err_state_north_xbar_sel ,
err_state_east_xbar_sel => L_err_state_east_xbar_sel ,
err_state_west_xbar_sel => L_err_state_west_xbar_sel ,
err_state_south_xbar_sel => L_err_state_south_xbar_sel
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
gpl-3.0
|
bruskajp/EE-316
|
Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/UART.vhd
|
1
|
12579
|
---- UART code taken from http://www.bealto.com/fpga-uart.html
-- -- Eric Bainville
-- -- Mar 2013
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library work;
--use work.math_real.all;
--entity basic_uart is
-- generic (
-- DIVISOR: natural := 54 -- DIVISOR = 100,000,000 / (16 x BAUD_RATE)
-- -- 2400 -> 2604
-- -- 9600 -> 651
-- -- 115200 -> 54
-- -- 1562500 -> 4
-- -- 2083333 -> 3
-- );
-- port (
-- clk: in std_logic; -- clock
-- reset: in std_logic; -- reset
-- -- Client interface
-- rx_data: out std_logic_vector(7 downto 0); -- received byte
-- rx_enable: out std_logic; -- validates received byte (1 system clock spike)
-- tx_data: in std_logic_vector(7 downto 0); -- byte to send
-- tx_enable: in std_logic; -- validates byte to send if tx_ready is '1'
-- tx_ready: out std_logic; -- if '1', we can send a new byte, otherwise we won't take it
-- -- Physical interface
-- rx: in std_logic;
-- tx: out std_logic
-- );
--end basic_uart;
--architecture Behavioral of basic_uart is
-- constant COUNTER_BITS : natural := integer(ceil(log(2,real(DIVISOR))));
-- type fsm_state_t is (idle, active); -- common to both RX and TX FSM
-- type rx_state_t is
-- record
-- fsm_state: fsm_state_t; -- FSM state
-- counter: std_logic_vector(3 downto 0); -- tick count
-- bits: std_logic_vector(7 downto 0); -- received bits
-- nbits: std_logic_vector(3 downto 0); -- number of received bits (includes start bit)
-- enable: std_logic; -- signal we received a new byte
-- end record;
-- type tx_state_t is
-- record
-- fsm_state: fsm_state_t; -- FSM state
-- counter: std_logic_vector(3 downto 0); -- tick count
-- bits: std_logic_vector(8 downto 0); -- bits to emit, includes start bit
-- nbits: std_logic_vector(3 downto 0); -- number of bits left to send
-- ready: std_logic; -- signal we are accepting a new byte
-- end record;
-- signal rx_state,rx_state_next: rx_state_t;
-- signal tx_state,tx_state_next: tx_state_t;
-- signal sample: std_logic; -- 1 clk spike at 16x baud rate
-- signal sample_counter: std_logic_vector(COUNTER_BITS-1 downto 0); -- should fit values in 0..DIVISOR-1
--begin
-- -- sample signal at 16x baud rate, 1 CLK spikes
-- sample_process: process (clk,reset) is
-- begin
-- if reset = '1' then
-- sample_counter <= (others => '0');
-- sample <= '0';
-- elsif rising_edge(clk) then
-- if sample_counter = DIVISOR-1 then
-- sample <= '1';
-- sample_counter <= (others => '0');
-- else
-- sample <= '0';
-- sample_counter <= sample_counter + 1;
-- end if;
-- end if;
-- end process;
-- -- RX, TX state registers update at each CLK, and RESET
-- reg_process: process (clk,reset) is
-- begin
-- if reset = '1' then
-- rx_state.fsm_state <= idle;
-- rx_state.bits <= (others => '0');
-- rx_state.nbits <= (others => '0');
-- rx_state.enable <= '0';
-- tx_state.fsm_state <= idle;
-- tx_state.bits <= (others => '1');
-- tx_state.nbits <= (others => '0');
-- tx_state.ready <= '1';
-- elsif rising_edge(clk) then
-- rx_state <= rx_state_next;
-- tx_state <= tx_state_next;
-- end if;
-- end process;
-- -- RX FSM
-- rx_process: process (rx_state,sample,rx) is
-- begin
-- case rx_state.fsm_state is
-- when idle =>
-- rx_state_next.counter <= (others => '0');
-- rx_state_next.bits <= (others => '0');
-- rx_state_next.nbits <= (others => '0');
-- rx_state_next.enable <= '0';
-- if rx = '0' then
-- -- start a new byte
-- rx_state_next.fsm_state <= active;
-- else
-- -- keep idle
-- rx_state_next.fsm_state <= idle;
-- end if;
-- when active =>
-- rx_state_next <= rx_state;
-- if sample = '1' then
-- if rx_state.counter = 8 then
-- -- sample next RX bit (at the middle of the counter cycle)
-- if rx_state.nbits = 9 then
-- rx_state_next.fsm_state <= idle; -- back to idle state to wait for next start bit
-- rx_state_next.enable <= rx; -- OK if stop bit is '1'
-- else
-- rx_state_next.bits <= rx & rx_state.bits(7 downto 1);
-- rx_state_next.nbits <= rx_state.nbits + 1;
-- end if;
-- end if;
-- rx_state_next.counter <= rx_state.counter + 1;
-- end if;
-- end case;
-- end process;
-- -- RX output
-- rx_output: process (rx_state) is
-- begin
-- rx_enable <= rx_state.enable;
-- rx_data <= rx_state.bits;
-- end process;
-- -- TX FSM
-- tx_process: process (tx_state,sample,tx_enable,tx_data) is
-- begin
-- case tx_state.fsm_state is
-- when idle =>
-- if tx_enable = '1' then
-- -- start a new bit
-- tx_state_next.bits <= tx_data & '0'; -- data & start
-- tx_state_next.nbits <= "0000" + 10; -- send 10 bits (includes '1' stop bit)
-- tx_state_next.counter <= (others => '0');
-- tx_state_next.fsm_state <= active;
-- tx_state_next.ready <= '0';
-- else
-- -- keep idle
-- tx_state_next.bits <= (others => '1');
-- tx_state_next.nbits <= (others => '0');
-- tx_state_next.counter <= (others => '0');
-- tx_state_next.fsm_state <= idle;
-- tx_state_next.ready <= '1';
-- end if;
-- when active =>
-- tx_state_next <= tx_state;
-- if sample = '1' then
-- if tx_state.counter = 15 then
-- -- send next bit
-- if tx_state.nbits = 0 then
-- -- turn idle
-- tx_state_next.bits <= (others => '1');
-- tx_state_next.nbits <= (others => '0');
-- tx_state_next.counter <= (others => '0');
-- tx_state_next.fsm_state <= idle;
-- tx_state_next.ready <= '1';
-- else
-- tx_state_next.bits <= '1' & tx_state.bits(8 downto 1);
-- tx_state_next.nbits <= tx_state.nbits - 1;
-- end if;
-- end if;
-- tx_state_next.counter <= tx_state.counter + 1;
-- end if;
-- end case;
-- end process;
-- -- TX output
-- tx_output: process (tx_state) is
-- begin
-- tx_ready <= tx_state.ready;
-- tx <= tx_state.bits(0);
-- end process;
--end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity uart is
port (
reset :in std_logic;
txclk :in std_logic;
ld_tx_data :in std_logic;
tx_data :in std_logic_vector (7 downto 0);
tx_enable :in std_logic;
selCheck :in std_logic_vector(1 downto 0);
tx_out :out std_logic;
tx_empty :out std_logic;
rxclk :in std_logic;
uld_rx_data :in std_logic;
rx_data :out std_logic_vector (7 downto 0);
rx_enable :in std_logic;
rx_in :in std_logic;
rx_empty :out std_logic
);
end entity;
architecture rtl of uart is
-- Internal Variables
signal tx_reg :std_logic_vector (7 downto 0);
signal tx_over_run :std_logic;
signal tx_cnt :std_logic_vector (3 downto 0);
signal rx_reg :std_logic_vector (7 downto 0);
signal rx_sample_cnt :std_logic_vector (3 downto 0);
signal rx_cnt :std_logic_vector (3 downto 0);
signal rx_frame_err :std_logic;
signal rx_over_run :std_logic;
signal rx_d1 :std_logic;
signal rx_d2 :std_logic;
signal rx_busy :std_logic;
signal rx_is_empty :std_logic;
signal tx_is_empty :std_logic;
begin
-- UART RX Logic
process (rxclk, reset,selCheck) begin
if (reset = '1') then
rx_reg <= (others=>'0');
rx_data <= (others=>'0');
rx_sample_cnt <= (others=>'0');
rx_cnt <= (others=>'0');
rx_frame_err <= '0';
rx_over_run <= '0';
rx_is_empty <= '1';
rx_d1 <= '1';
rx_d2 <= '1';
rx_busy <= '0';
elsif (rising_edge(rxclk)) then
-- Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
-- Uload the rx data
if (uld_rx_data = '1') then
rx_data <= rx_reg;
rx_is_empty <= '1';
end if;
if uld_rx_data = '1' and selCheck /= "00" and rx_is_empty = '1' then
rx_data <= "00000000";
end if;
-- Receive data only when rx is enabled
if (rx_enable = '1') then
-- Check if just received start of frame
if (rx_busy = '0' and rx_d2 = '0') then
rx_busy <= '1';
rx_sample_cnt <= X"1";
rx_cnt <= X"0";
end if;
-- Start of frame detected, Proceed with rest of data
if (rx_busy = '1') then
rx_sample_cnt <= rx_sample_cnt + 1;
-- Logic to sample at middle of data
if (rx_sample_cnt = 7) then
if ((rx_d2 = '1') and (rx_cnt = 0)) then
rx_busy <= '0';
else
rx_cnt <= rx_cnt + 1;
-- Start storing the rx data
if (rx_cnt > 0 and rx_cnt < 9) then
rx_reg(conv_integer(rx_cnt) - 1) <= rx_d2;
end if;
if (rx_cnt = 9) then
rx_busy <= '0';
-- Check if End of frame received correctly
if (rx_d2 = '0') then
rx_frame_err <= '1';
else
rx_is_empty <= '0';
rx_frame_err <= '0';
-- Check if last rx data was not unloaded,
if (rx_is_empty = '1') then
rx_over_run <= '0';
else
rx_over_run <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
if (rx_enable = '0') then
rx_busy <= '0';
end if;
end if;
end process;
rx_empty <= rx_is_empty;
-- UART TX Logic
process (txclk, reset) begin
if (reset = '1') then
tx_reg <= (others=>'0');
tx_is_empty <= '1';
tx_over_run <= '0';
tx_out <= '0';
tx_cnt <= (others=>'0');
elsif (rising_edge(txclk)) then
if (ld_tx_data = '1') then
if (tx_is_empty = '0') then
tx_over_run <= '0';
else
tx_reg <= tx_data;
tx_is_empty <= '0';
end if;
end if;
if (tx_enable = '1' and tx_is_empty = '0') then
tx_cnt <= tx_cnt + 1;
if (tx_cnt = 0) then
tx_out <= '0';
end if;
if (tx_cnt > 0 and tx_cnt < 9) then
tx_out <= tx_reg(conv_integer(tx_cnt) -1);
end if;
if (tx_cnt = 9) then
tx_out <= '1';
tx_cnt <= X"0";
tx_is_empty <= '1';
end if;
end if;
if (tx_enable = '0') then
tx_cnt <= X"0";
end if;
end if;
end process;
-- process(uld_rx_data)
-- begin
-- if uld_rx_data = '1' and selCheck /= "00" and rx_is_empty = '1' then
-- rx_data <= "00000000";
-- end if;
-- end process;
-- tx_empty <= tx_is_empty;
end architecture;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Fault_Management/SHMU_prototype/version_2/xbar.vhd
|
4
|
1004
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= North_in;
when "00010" =>
Data_out <= East_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= South_in;
when others =>
Data_out <= Local_in;
end case;
end process;
end;
|
gpl-3.0
|
JarrettR/FPGA-Cryptoparty
|
FPGA/hdl/sim_prf.vhd
|
1
|
4587
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/26/2016 11:44:06 PM
-- Design Name:
-- Module Name: sim_prf - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.sha1_pkg.all;
entity sim_prf is
end sim_prf;
architecture Behavioral of sim_prf is
component prf_main is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
load_i : in std_ulogic;
pmk_i : in w_input;
anonce_dat : in nonce_data;
cnonce_dat : in nonce_data;
amac_dat : in mac_data;
cmac_dat : in mac_data;
ptk_dat_o : out ptk_data;
ptk_valid_o : out std_ulogic
);
end component;
signal valid : std_ulogic;
signal load : std_ulogic := '0';
signal clk_i : std_ulogic := '0';
signal rst_i : std_ulogic := '0';
signal pmk : w_input;
signal anonce : nonce_data;
signal cnonce : nonce_data;
signal amac_dat : mac_data;
signal cmac_dat : mac_data;
signal ptk : ptk_data;
--pmk: 5df920b5481ed70538dd5fd02423d7e2522205feeebb974cad08a52b5613ede2
--a: 5061697277697365206b657920657870616e73696f6e
--b: 000b86c2a4850013ce5598efae12a150652e9bc22063720c5081e9eb74077fb19fffe871dc4ca1e6f448af85e8dfa16b8769957d8249a4ec68d2b7641d3782162ef0dc37b014cc48343e8dd2
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f8361
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f83611dc93e2657cecf69a3651bc4fca5880ce9081345
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f83611dc93e2657cecf69a3651bc4fca5880ce9081345c5411d489313b29e4aaf287d5231a342b777a67a
--ptk: 5e9805e89cb0e84b45e5f9e4a1a80d9d
signal i: integer range 0 to 65535;
constant clock_period : time := 1 ns;
begin
prf: prf_main port map (clk_i,rst_i,load,pmk,anonce,cnonce,amac_dat,cmac_dat,ptk,valid);
stim_proc: process
begin
rst_i <= '0';
i <= 0;
load <= '0';
--Ordinally will come from PBKDF2
--5df920b5481ed70538dd5fd02423d7e2 522205feeebb974cad08a52b5613ede2
pmk <= (X"5df920b5",X"481ed705",X"38dd5fd0",X"2423d7e2",
X"522205fe",X"eebb974c",X"ad08a52b",X"5613ede2",
others=>(X"00000000"));
--b = min(apMac, cMac) + max(apMac, cMac) + min(apNonce, cNonce) + max(apNonce, cNonce)
--We're assuming that min/max will be calculated host-side
--Comes directly from handshake on host
--000b86c2a485
amac_dat <= (X"00",X"0b",X"86",X"c2",X"a4",X"85");
--0013ce5598ef
cmac_dat <= (X"00",X"13",X"ce",X"55",X"98",X"ef");
--ae12a150652e9bc22063720c5081e9eb 74077fb19fffe871dc4ca1e6f448af85
anonce <= (X"ae",X"12",X"a1",X"50",X"65",X"2e",X"9b",X"c2",X"20",X"63",X"72",X"0c",X"50",X"81",X"e9",X"eb",
X"74",X"07",X"7f",X"b1",X"9f",X"ff",X"e8",X"71",X"dc",X"4c",X"a1",X"e6",X"f4",X"48",X"af",X"85");
--e8dfa16b8769957d8249a4ec68d2b764 1d3782162ef0dc37b014cc48343e8dd2
cnonce <= (X"e8",X"df",X"a1",X"6b",X"87",X"69",X"95",X"7d",X"82",X"49",X"a4",X"ec",X"68",X"d2",X"b7",X"64",
X"1d",X"37",X"82",X"16",X"2e",X"f0",X"dc",X"37",X"b0",X"14",X"cc",X"48",X"34",X"3e",X"8d",X"d2");
wait until rising_edge(clk_i);
rst_i <= '1';
wait until rising_edge(clk_i);
rst_i <= '0';
wait until rising_edge(clk_i);
load <= '1';
wait until rising_edge(clk_i);
load <= '0';
wait until rising_edge(clk_i);
while valid = '0' loop
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
wait;
end process;
clock_process: process
begin
clk_i <= '0';
wait for clock_period/2;
clk_i <= '1';
wait for clock_period/2;
end process;
end Behavioral;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Immortal_Chip/Router_32_bit.vhd
|
1
|
12178
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port ( reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end router;
architecture behavior of router is
COMPONENT router_channel is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS : in std_logic;
DRTS : in std_logic;
RTS : out std_logic;
CTS : out std_logic;
flit_type : in std_logic_vector(2 downto 0);
destination_address : in std_logic_vector(NoC_size-1 downto 0);
Grant_N_in , Grant_E_in , Grant_W_in , Grant_S_in , Grant_L_in : in std_logic;
Grant_N_out, Grant_E_out, Grant_W_out, Grant_S_out, Grant_L_out: out std_logic;
Req_N_in , Req_E_in , Req_W_in , Req_S_in , Req_L_in :in std_logic;
Req_N_out , Req_E_out, Req_W_out, Req_S_out, Req_L_out:out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
Xbar_sel: out std_logic_vector(4 downto 0)
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT FIFO_data_path is
generic (
DATA_WIDTH: integer := 32
);
port (
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
read_pointer, write_pointer: in std_logic_vector(3 downto 0);
write_en : in std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal write_pointer_out_N, write_pointer_out_E, write_pointer_out_W, write_pointer_out_S, write_pointer_out_L: std_logic_vector(3 downto 0);
signal read_pointer_out_N, read_pointer_out_E, read_pointer_out_W, read_pointer_out_S, read_pointer_out_L: std_logic_vector(3 downto 0);
signal write_en_out_N, write_en_out_E, write_en_out_W, write_en_out_S, write_en_out_L: std_logic;
signal Grant_N_N, Grant_N_E, Grant_N_W, Grant_N_S, Grant_N_L: std_logic;
signal Grant_E_N, Grant_E_E, Grant_E_W, Grant_E_S, Grant_E_L: std_logic;
signal Grant_W_N, Grant_W_E, Grant_W_W, Grant_W_S, Grant_W_L: std_logic;
signal Grant_S_N, Grant_S_E, Grant_S_W, Grant_S_S, Grant_S_L: std_logic;
signal Grant_L_N, Grant_L_E, Grant_L_W, Grant_L_S, Grant_L_L: std_logic;
signal Req_N_N, Req_E_N, Req_W_N, Req_S_N, Req_L_N: std_logic;
signal Req_N_E, Req_E_E, Req_W_E, Req_S_E, Req_L_E: std_logic;
signal Req_N_W, Req_E_W, Req_W_W, Req_S_W, Req_L_W: std_logic;
signal Req_N_S, Req_E_S, Req_W_S, Req_S_S, Req_L_S: std_logic;
signal Req_N_L, Req_E_L, Req_W_L, Req_S_L, Req_L_L: std_logic;
begin
Channel_N: router_channel generic map (DATA_WIDTH => DATA_WIDTH, current_address =>current_address, Rxy_rst =>Rxy_rst, Cx_rst =>Cx_rst, NoC_size => NoC_size)
port map (reset=> reset, clk => clk, DCTS => DCTS_N, DRTS => DRTS_N, RTS=>RTS_N, CTS=>CTS_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), destination_address=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19),
Grant_N_in => '0' , Grant_E_in => Grant_E_N , Grant_W_in => Grant_W_N , Grant_S_in => Grant_S_N , Grant_L_in => Grant_L_N , Grant_N_out => Grant_N_N, Grant_E_out => Grant_N_E, Grant_W_out => Grant_N_W, Grant_S_out => Grant_N_S, Grant_L_out => Grant_N_L,
Req_N_in => '0' , Req_E_in => Req_E_N , Req_W_in => Req_W_N , Req_S_in => Req_S_N , Req_L_in => Req_L_N , Req_N_out => Req_N_N , Req_E_out => Req_N_E , Req_W_out => Req_N_W , Req_S_out => Req_N_S , Req_L_out => Req_N_L ,
read_pointer_out => read_pointer_out_N, write_pointer_out => write_pointer_out_N, write_en_out=>write_en_out_N, Xbar_sel=>Xbar_sel_N);
Channel_E: router_channel generic map (DATA_WIDTH => DATA_WIDTH, current_address =>current_address, Rxy_rst =>Rxy_rst, Cx_rst =>Cx_rst, NoC_size => NoC_size)
port map (reset=> reset, clk => clk, DCTS => DCTS_E, DRTS => DRTS_E, RTS=>RTS_E, CTS=>CTS_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), destination_address=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19),
Grant_N_in => Grant_N_E , Grant_E_in => '0' , Grant_W_in => Grant_W_E , Grant_S_in => Grant_S_E , Grant_L_in => Grant_L_E , Grant_N_out => Grant_E_N, Grant_E_out => Grant_E_E, Grant_W_out => Grant_E_W, Grant_S_out => Grant_E_S, Grant_L_out => Grant_E_L,
Req_N_in => Req_N_E , Req_E_in => '0' , Req_W_in => Req_W_E , Req_S_in => Req_S_E , Req_L_in => Req_L_E , Req_N_out => Req_E_N , Req_E_out => Req_E_E , Req_W_out => Req_E_W , Req_S_out => Req_E_S , Req_L_out => Req_E_L ,
read_pointer_out => read_pointer_out_E, write_pointer_out => write_pointer_out_E, write_en_out=>write_en_out_E, Xbar_sel=>Xbar_sel_E);
Channel_W: router_channel generic map (DATA_WIDTH => DATA_WIDTH, current_address =>current_address, Rxy_rst =>Rxy_rst, Cx_rst =>Cx_rst, NoC_size => NoC_size)
port map (reset=> reset, clk => clk, DCTS => DCTS_W, DRTS => DRTS_W, RTS=>RTS_W, CTS=>CTS_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), destination_address=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19),
Grant_N_in => Grant_N_W , Grant_E_in => Grant_E_W , Grant_W_in => '0' , Grant_S_in => Grant_S_W , Grant_L_in => Grant_L_W , Grant_N_out => Grant_W_N, Grant_E_out => Grant_W_E, Grant_W_out => Grant_W_W, Grant_S_out => Grant_W_S, Grant_L_out => Grant_W_L,
Req_N_in => Req_N_W , Req_E_in => Req_E_W , Req_W_in => '0' , Req_S_in => Req_S_W , Req_L_in => Req_L_W , Req_N_out => Req_W_N , Req_E_out => Req_W_E , Req_W_out => Req_W_W , Req_S_out => Req_W_S , Req_L_out => Req_W_L ,
read_pointer_out => read_pointer_out_W, write_pointer_out => write_pointer_out_W, write_en_out=>write_en_out_W, Xbar_sel=>Xbar_sel_W);
Channel_S: router_channel generic map (DATA_WIDTH => DATA_WIDTH, current_address =>current_address, Rxy_rst =>Rxy_rst, Cx_rst =>Cx_rst, NoC_size => NoC_size)
port map (reset=> reset, clk => clk, DCTS => DCTS_S, DRTS => DRTS_S, RTS=>RTS_S, CTS=>CTS_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), destination_address=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19),
Grant_N_in => Grant_N_S , Grant_E_in => Grant_E_S , Grant_W_in => Grant_W_S , Grant_S_in => '0' , Grant_L_in => Grant_L_S , Grant_N_out => Grant_S_N, Grant_E_out => Grant_S_E, Grant_W_out => Grant_S_W, Grant_S_out => Grant_S_S, Grant_L_out => Grant_S_L,
Req_N_in => Req_N_S , Req_E_in => Req_E_S , Req_W_in => Req_W_S , Req_S_in => '0' , Req_L_in => Req_L_S , Req_N_out => Req_S_N , Req_E_out => Req_S_E , Req_W_out => Req_S_W , Req_S_out => Req_S_S , Req_L_out => Req_S_L ,
read_pointer_out => read_pointer_out_S, write_pointer_out => write_pointer_out_S, write_en_out=>write_en_out_S, Xbar_sel=>Xbar_sel_S);
Channel_L: router_channel generic map (DATA_WIDTH => DATA_WIDTH, current_address =>current_address, Rxy_rst =>Rxy_rst, Cx_rst =>Cx_rst, NoC_size => NoC_size)
port map (reset=> reset, clk => clk, DCTS => DCTS_L, DRTS => DRTS_L, RTS=>RTS_L, CTS=>CTS_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), destination_address=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19),
Grant_N_in => Grant_N_L , Grant_E_in => Grant_E_L , Grant_W_in => Grant_W_L , Grant_S_in => Grant_S_L , Grant_L_in => '0' , Grant_N_out => Grant_L_N, Grant_E_out => Grant_L_E, Grant_W_out => Grant_L_W, Grant_S_out => Grant_L_S, Grant_L_out => Grant_L_L,
Req_N_in => Req_N_L , Req_E_in => Req_E_L , Req_W_in => Req_W_L , Req_S_in => Req_S_L , Req_L_in => '0' , Req_N_out => Req_L_N , Req_E_out => Req_L_E , Req_W_out => Req_L_W , Req_S_out => Req_L_S , Req_L_out => Req_L_L ,
read_pointer_out => read_pointer_out_L, write_pointer_out => write_pointer_out_L, write_en_out=>write_en_out_L, Xbar_sel=>Xbar_sel_L);
xbar_N: XBAR generic map(DATA_WIDTH => DATA_WIDTH) port map (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in=> FIFO_D_out_W, South_in=> FIFO_D_out_S, Local_in=> FIFO_D_out_L, sel=>Xbar_sel_N, Data_out=> TX_N);
xbar_E: XBAR generic map(DATA_WIDTH => DATA_WIDTH) port map (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in=> FIFO_D_out_W, South_in=> FIFO_D_out_S, Local_in=> FIFO_D_out_L, sel=>Xbar_sel_E, Data_out=> TX_E);
xbar_W: XBAR generic map(DATA_WIDTH => DATA_WIDTH) port map (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in=> FIFO_D_out_W, South_in=> FIFO_D_out_S, Local_in=> FIFO_D_out_L, sel=>Xbar_sel_W, Data_out=> TX_W);
xbar_S: XBAR generic map(DATA_WIDTH => DATA_WIDTH) port map (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in=> FIFO_D_out_W, South_in=> FIFO_D_out_S, Local_in=> FIFO_D_out_L, sel=>Xbar_sel_S, Data_out=> TX_S);
xbar_L: XBAR generic map(DATA_WIDTH => DATA_WIDTH) port map (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in=> FIFO_D_out_W, South_in=> FIFO_D_out_S, Local_in=> FIFO_D_out_L, sel=>Xbar_sel_L, Data_out=> TX_L);
FIFO_N: FIFO_data_path generic map(DATA_WIDTH => DATA_WIDTH) port map(clk => clk, reset => reset, RX => RX_N, read_pointer => read_pointer_out_N, write_pointer => write_pointer_out_N, write_en => write_en_out_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_data_path generic map(DATA_WIDTH => DATA_WIDTH) port map(clk => clk, reset => reset, RX => RX_E, read_pointer => read_pointer_out_E, write_pointer => write_pointer_out_E, write_en => write_en_out_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_data_path generic map(DATA_WIDTH => DATA_WIDTH) port map(clk => clk, reset => reset, RX => RX_W, read_pointer => read_pointer_out_W, write_pointer => write_pointer_out_W, write_en => write_en_out_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_data_path generic map(DATA_WIDTH => DATA_WIDTH) port map(clk => clk, reset => reset, RX => RX_S, read_pointer => read_pointer_out_S, write_pointer => write_pointer_out_S, write_en => write_en_out_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_data_path generic map(DATA_WIDTH => DATA_WIDTH) port map(clk => clk, reset => reset, RX => RX_L, read_pointer => read_pointer_out_L, write_pointer => write_pointer_out_L, write_en => write_en_out_L, Data_out => FIFO_D_out_L);
end;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Credit_Based/Credit_Based_FC/FIFO_one_hot_credit_based.vhd
|
5
|
5364
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
credit_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
credit_out <= '0';
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
if read_en = '1' then
credit_out <= '1';
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in) begin
if valid_in = '1' and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
gpl-3.0
|
bruskajp/EE-316
|
Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/clk1Mhz.vhd
|
1
|
1730
|
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clk1Mhz IS
PORT (
SIGNAL samplingFreq : INOUT std_logic:= '1';
signal baudRate : INOUT std_logic:= '1';
signal rx_clk : inout std_logic:= '1';
signal tx_clk : inout std_logic:= '1';
SIGNAL iCLK : IN std_logic);
END clk1Mhz;
ARCHITECTURE Arch OF clk1Mhz IS
SIGNAL DIV : std_logic_vector (25 DOWNTO 0):="00"&X"000000";
SIGNAL DIV2 : std_logic_vector (25 DOWNTO 0):="00"&X"000000";
SIGNAL DIV3 : std_logic_vector (25 DOWNTO 0):="00"&X"000000";
SIGNAL DIV4 : std_logic_vector (25 DOWNTO 0):="00"&X"000000";
BEGIN
PROCESS(iCLK) -- 11.52 kHz clock
BEGIN
IF rising_edge(iCLK) THEN
IF DIV >= 4341 THEN
DIV <= "00"&X"000000";
baudRate <= NOT baudRate;
ELSE
DIV <= DIV + '1';
END IF;
END IF;
END PROCESS;
PROCESS(iCLK) -- 1 MHz clock
BEGIN
IF rising_edge(iCLK) THEN
IF DIV2 >= 49 THEN
DIV2 <= "00"&X"000000";
samplingFreq <= NOT samplingFreq;
ELSE
DIV2 <= DIV2 + '1';
END IF;
END IF;
END PROCESS;
PROCESS(iCLK) -- 1 MHz clock
BEGIN
IF rising_edge(iCLK) THEN -- 11.52kHz*16
IF DIV3 >= 272 THEN
DIV3 <= "00"&X"000000";
rx_clk <= NOT rx_clk;
ELSE
DIV3 <= DIV3 + '1';
END IF;
END IF;
END PROCESS;
process(iCLK)
begin
IF rising_edge(iCLK) THEN -- 115.20k*10
IF DIV4 >= 435 THEN
DIV4 <= "00"&X"000000";
tx_clk <= NOT tx_clk;
ELSE
DIV4 <= DIV4 + '1';
END IF;
END IF;
END PROCESS;
END Arch;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Hand_Shaking/Checkers/Modules_with_checkers_integrated/Dominant_checkers/Arbiter_one_hot_with_dominant_checkers/Arbiter_one_hot_with_checkers.vhd
|
2
|
16687
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end;
architecture behavior of Arbiter is
-- next
-- Arbiter router or NI
-- ------------------------------------- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- ------------------------------------- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
--CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTs _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
-- TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic;
signal Xbar_sel_sig: std_logic_vector(4 downto 0);
component Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end component;
begin
-- Arbiter checkers instantiation
ARBITERCHECKERS: Arbiter_checkers port map (
Req_N => Req_N,
Req_E => Req_E,
Req_W => Req_W,
Req_S => Req_S,
Req_L => Req_L,
DCTS => DCTS,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel=>Xbar_sel_sig,
state => state,
state_in => state_in,
next_state_out => next_state,
RTS_FF => RTS_FF,
RTS_FF_in => RTS_FF_in,
err_state_IDLE_xbar => err_state_IDLE_xbar,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE,
err_IDLE_Req_L => err_IDLE_Req_L,
err_Local_Req_L => err_Local_Req_L,
err_North_Req_N => err_North_Req_N,
err_IDLE_Req_N => err_IDLE_Req_N,
err_Local_Req_N => err_Local_Req_N,
err_South_Req_L => err_South_Req_L,
err_West_Req_L => err_West_Req_L,
err_South_Req_N => err_South_Req_N,
err_East_Req_L => err_East_Req_L,
err_West_Req_N => err_West_Req_N,
err_East_Req_N => err_East_Req_N,
err_next_state_onehot => err_next_state_onehot,
err_state_in_onehot => err_state_in_onehot,
err_state_north_xbar_sel => err_state_north_xbar_sel,
err_state_east_xbar_sel => err_state_east_xbar_sel,
err_state_west_xbar_sel => err_state_west_xbar_sel,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
-- Becuase of checkers we did this!
Grant_N <= Grant_N_sig;
Grant_E <= Grant_E_sig;
Grant_W <= Grant_W_sig;
Grant_S <= Grant_S_sig;
Grant_L <= Grant_L_sig;
Xbar_sel <= Xbar_sel_sig;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N_sig <= '0';
Grant_E_sig <= '0';
Grant_W_sig <= '0';
Grant_S_sig <= '0';
Grant_L_sig <= '0';
Xbar_sel_sig <= "00000";
case(state) is
when IDLE =>
Xbar_sel_sig <= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N_sig <= DCTS and RTS_FF ;
Xbar_sel_sig <= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Immortal_Chip/tb_network_rand_2x2.vhd
|
1
|
3363
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_0, CTS_L_0: out std_logic;
DRTS_L_0, DCTS_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_1, CTS_L_1: out std_logic;
DRTS_L_1, DCTS_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_2, CTS_L_2: out std_logic;
DRTS_L_2, DCTS_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_3, CTS_L_3: out std_logic;
DRTS_L_3, DCTS_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal RTS_L_0, DRTS_L_0, CTS_L_0, DCTS_L_0: std_logic;
--------------
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal RTS_L_1, DRTS_L_1, CTS_L_1, DCTS_L_1: std_logic;
--------------
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal RTS_L_2, DRTS_L_2, CTS_L_2, DCTS_L_2: std_logic;
--------------
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal RTS_L_3, DRTS_L_3, CTS_L_3, DCTS_L_3: std_logic;
--------------
constant clk_period : time := 1 ns;
signal reset,clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32)
PORT MAP (reset, clk,
RX_L_0, RTS_L_0, CTS_L_0, DRTS_L_0, DCTS_L_0, TX_L_0,
RX_L_1, RTS_L_1, CTS_L_1, DRTS_L_1, DCTS_L_1, TX_L_1,
RX_L_2, RTS_L_2, CTS_L_2, DRTS_L_2, DCTS_L_2, TX_L_2,
RX_L_3, RTS_L_3, CTS_L_3, DRTS_L_3, DCTS_L_3, TX_L_3);
-- connecting the packet generators
gen_random_packet(100, 0, 41, 8, 8, 10000 ns, clk, CTS_L_0, DRTS_L_0, RX_L_0);
gen_random_packet(100, 1, 9, 8, 8, 10000 ns, clk, CTS_L_1, DRTS_L_1, RX_L_1);
gen_random_packet(100, 2, 32, 8, 8, 10000 ns, clk, CTS_L_2, DRTS_L_2, RX_L_2);
gen_random_packet(100, 3, 47, 8, 8, 10000 ns, clk, CTS_L_3, DRTS_L_3, RX_L_3);
-- connecting the packet receivers
-- Arguments are:
-- data_width, inital delay, node_id, clk, DCTS, RTS, TX
get_packet(32, 5, 0, clk, DCTS_L_0, RTS_L_0, TX_L_0);
get_packet(32, 5, 1, clk, DCTS_L_1, RTS_L_1, TX_L_1);
get_packet(32, 5, 2, clk, DCTS_L_2, RTS_L_2, TX_L_2);
get_packet(32, 5, 3, clk, DCTS_L_3, RTS_L_3, TX_L_3);
end;
|
gpl-3.0
|
bruskajp/EE-316
|
Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/univ_bin_counter.vhd
|
1
|
1772
|
-- Source: http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl.html
-- Listing 4.10
-- modified: added port "clk_en", Sept 5, 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity univ_bin_counter is
generic(N: integer := 8);
port(
clk, reset : in std_logic;
syn_clr, load, en, up : in std_logic;
clk_en : in std_logic ;
d : in std_logic_vector(N-1 downto 0);
max : in unsigned(N-1 downto 0);
min : in unsigned(N-1 downto 0);
q : out std_logic_vector(N-1 downto 0)
);
end univ_bin_counter;
architecture arch of univ_bin_counter is
signal r_reg : unsigned(N-1 downto 0) := min;
signal r_next : unsigned(N-1 downto 0);
signal max_tick : std_logic;
signal min_tick : std_logic;
begin
-- register
process(clk,reset,clk_en,syn_clr,min,r_next)
begin
if (reset='1' or syn_clr = '1') then
r_reg <= min;
elsif rising_edge(clk) and clk_en = '1' then
r_reg <= r_next;
end if;
end process;
process (en,up,r_reg,min,max)
begin
if (en = '1') then
if (up = '1') then
if (r_reg = max) then
r_next <= min;
elsif (r_reg /= max) then
r_next <= r_reg +1;
end if;
elsif (up = '0') then
if (r_reg = min) then
r_next <= max;
elsif (r_reg /= min) then
r_next <= r_reg -1;
end if;
end if;
elsif (en = '0') then
r_next <= r_reg;
end if;
end process;
q <= std_logic_vector(r_reg);
end arch;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Fault_Management/Error_Detection_Correction/hamming_decoder.vhd
|
1
|
5641
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
Entity hamming_decoder is
port
(hamming_in : in std_logic_vector(38 downto 0); --d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 --d26 d27 p0 p1 p2 p3 p4 p5 p6
dataout : out std_logic_vector(31 downto 0); --d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 --d26 d27
s_err_corr : out std_logic; --diagnostic outputs
d_err_det : out std_logic; --diagnostic outputs
no_error : out std_logic); --diagnostic outputs
end hamming_decoder;
architecture beh OF hamming_decoder is
Signal syndrome : std_logic_vector (6 downto 0);
begin
syndrome(0) <= hamming_in(0) xor hamming_in(1) xor hamming_in(3) xor hamming_in(4) xor hamming_in(6) xor
hamming_in(8) xor hamming_in(10) xor hamming_in(11) xor hamming_in(13) xor hamming_in(15) xor
hamming_in(17) xor hamming_in(19) xor hamming_in(21) xor hamming_in(23) xor hamming_in(25) xor hamming_in(26) xor hamming_in(28) xor hamming_in(30) xor hamming_in(32);
syndrome(1) <= hamming_in(0) xor hamming_in(2) xor hamming_in(3) xor hamming_in(5) xor hamming_in(6) xor
hamming_in(9) xor hamming_in(10) xor hamming_in(12) xor hamming_in(13) xor hamming_in(16) xor
hamming_in(17) xor hamming_in(20) xor hamming_in(21) xor hamming_in(24) xor hamming_in(25) xor hamming_in(27) xor hamming_in(28) xor hamming_in(31) xor hamming_in(33);
syndrome(2) <= XOR_REDUCE(hamming_in(3 downto 1)) xor XOR_REDUCE(hamming_in(10 downto 7)) xor XOR_REDUCE(hamming_in(17 downto 14)) xor
XOR_REDUCE(hamming_in(25 downto 22)) xor XOR_REDUCE(hamming_in(31 downto 29)) xor hamming_in(34);
syndrome(3) <= XOR_REDUCE(hamming_in(10 downto 4)) xor XOR_REDUCE(hamming_in(25 downto 18)) xor hamming_in(35);
syndrome(4) <= XOR_REDUCE(hamming_in(25 downto 11)) xor hamming_in(36);
syndrome(5) <= XOR_REDUCE(hamming_in(31 downto 26)) xor hamming_in(37);
syndrome(6) <= XOR_REDUCE(hamming_in(38 downto 0));
PROCESS(hamming_in, syndrome)
BEGIN
if syndrome(6) = '0' then
s_err_corr <= '0';
if (syndrome = "0000000") then -------no errors
no_error <= '1';
d_err_det <= '0';
dataout <= hamming_in(31 downto 0);
else -- (syndrome(5 downto 0) /= "000000")
no_error <= '0';
d_err_det <= '1';
dataout <= (others=> '0');
end if;
else -----------------------------------------------single bit error syndrome(6) = '1'
no_error <= '0';
d_err_det <= '0';
s_err_corr <= '1';
dataout <= hamming_in(31 downto 0); -- to cover all the bits
Case syndrome(5 downto 0) is
when "000000"|"000001"|"000010"|"000100"|"001000"|"010000"|"100000" => ------ this implies the error is only in parity bits, not data.
dataout <= hamming_in(31 downto 0);
when "000011" => dataout(0) <= not hamming_in(0);
when "000101" => dataout(1) <= not hamming_in(1);
when "000110" => dataout(2) <= not hamming_in(2);
when "000111" => dataout(3) <= not hamming_in(3);
when "001001" => dataout(4) <= not hamming_in(4);
when "001010" => dataout(5) <= not hamming_in(5);
when "001011" => dataout(6) <= not hamming_in(6);
when "001100" => dataout(7) <= not hamming_in(7);
when "001101" => dataout(8) <= not hamming_in(8);
when "001110" => dataout(9) <= not hamming_in(9);
when "001111" => dataout(10) <= not hamming_in(10);
when "010001" => dataout(11) <= not hamming_in(11);
when "010010" => dataout(12) <= not hamming_in(12);
when "010011" => dataout(13) <= not hamming_in(13);
when "010100" => dataout(14) <= not hamming_in(14);
when "010101" => dataout(15) <= not hamming_in(15);
when "010110" => dataout(16) <= not hamming_in(16);
when "010111" => dataout(17) <= not hamming_in(17);
when "011000" => dataout(18) <= not hamming_in(18);
when "011001" => dataout(19) <= not hamming_in(19);
when "011010" => dataout(20) <= not hamming_in(20);
when "011011" => dataout(21) <= not hamming_in(21);
when "011100" => dataout(22) <= not hamming_in(22);
when "011101" => dataout(23) <= not hamming_in(23);
when "011110" => dataout(24) <= not hamming_in(24);
when "011111" => dataout(25) <= not hamming_in(25);
when "100001" => dataout(26) <= not hamming_in(26);
when "100010" => dataout(27) <= not hamming_in(27);
when "100011" => dataout(28) <= not hamming_in(28);
when "100100" => dataout(29) <= not hamming_in(29);
when "100101" => dataout(30) <= not hamming_in(30);
when "100110" => dataout(31) <= not hamming_in(31);
when others=> dataout <= (others=> '0');
END Case;
END if;
END process;
END beh;
|
gpl-3.0
|
bruskajp/EE-316
|
Project1/sram_controller.vhd
|
1
|
2345
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_controller is
port
(
r_w : in std_logic;
clk : in std_logic;
addr : in std_logic_vector (17 downto 0);
r_w_en : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
r_w_status : out std_logic;
sram_addr : out std_logic_vector (17 downto 0);
sram_i_o : inout std_logic_vector (15 downto 0);
sram_n_we : out std_logic;
sram_n_oe : out std_logic;
sram_n_ce : out std_logic;
sram_n_ub : out std_logic;
sram_n_lb : out std_logic
);
end sram_controller;
architecture behavior of sram_controller is
signal buf_data_in : std_logic_vector (15 downto 0);
signal buf_r_w : std_logic := '0';
signal buf_r_w_en : std_logic := '0';
signal flag_r_w_en : std_logic := '0';
type state_type is (s0, s1, s2);
signal state : state_type := s0;
begin
sram_n_ce <= '0';
sram_n_ub <= '0';
sram_n_lb <= '0';
process (clk)
begin
if rising_edge(clk) then
if buf_r_w = '1' then
sram_i_o <= buf_data_in;
else
sram_i_o <= "ZZZZZZZZZZZZZZZZ";
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
sram_addr <= addr;
buf_data_in <= data_in;
if (buf_r_w = '0') then
data_out <= sram_i_o;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
buf_r_w_en <= r_w_en;
if buf_r_w_en = '0' and r_w_en = '1' then
flag_r_w_en <= '1';
else
flag_r_w_en <= '0';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
case state is
when s0 =>
r_w_status <= '0';
buf_r_w <= r_w;
sram_n_oe <= '1';
sram_n_we <= '1';
if flag_r_w_en = '1' then
state <= s1;
else
state <= s0;
end if;
when s1 =>
r_w_status <= '1';
if (buf_r_w = '0') then
sram_n_oe <= '0';
else
sram_n_we <= '0';
end if;
state <= s2;
when s2 =>
r_w_status <= '1';
if (buf_r_w = '0') then
sram_n_oe <= '0';
else
sram_n_we <= '0';
end if;
state <= s0;
end case;
end if;
end process;
end behavior;
|
gpl-3.0
|
JarrettR/FPGA-Cryptoparty
|
FPGA/hdl/ipcore_dir/fx2_fifo/simulation/fx2_fifo_synth.vhd
|
1
|
10955
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.fx2_fifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fx2_fifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fx2_fifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fx2_fifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fx2_fifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fx2_fifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fx2_fifo_inst : fx2_fifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-3.0
|
bruskajp/EE-316
|
Project1/display_driver.vhd
|
1
|
1819
|
-- Author: Zander Blasingame
-- Class: EE 316 Spring 2017
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity display_driver is
port (
keycode : in std_logic_vector(7 downto 0);
sram_address : in std_logic_vector(7 downto 0);
sram_data : in std_logic_vector(15 downto 0);
write_address : in std_logic;
is_programming : in std_logic;
clk : in std_logic;
address : out std_logic_vector(7 downto 0);
data : out std_logic_vector(15 downto 0)
);
end display_driver;
architecture behavior of display_driver is
-- Internal Register Signals
signal data_register : std_logic_vector(15 downto 0) := x"0000";
signal address_register : std_logic_vector(7 downto 0) := x"00";
begin
-- Demux for piping input into correct register
process(write_address, keycode)
begin
if keycode(7 downto 4) /= x"F" and rising_edge(clk) then
if write_address = '1' then
address_register(3 downto 0) <= keycode(3 downto 0);
address_register(7 downto 4) <= address_register(3 downto 0);
else
data_register(3 downto 0) <= keycode(3 downto 0);
data_register(7 downto 4) <= data_register(3 downto 0);
data_register(11 downto 8) <= data_register(7 downto 4);
data_register(15 downto 12) <= data_register(11 downto 8);
end if;
end if;
-- Reset registers in op mode
if is_programming = '0' then
address_register <= x"00";
data_register <= x"0000";
end if;
end process;
-- Mux for piping selecting data output stream
process(is_programming, address_register, data_register)
begin
if is_programming = '1' then
address <= address_register;
data <= data_register;
else
address <= sram_address;
data <= sram_data;
end if;
end process;
end behavior;
|
gpl-3.0
|
bruskajp/EE-316
|
Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/reset_delay.vhd
|
1
|
624
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Reset_Delay IS
PORT (
SIGNAL iCLK : IN std_logic;
SIGNAL oRESET : OUT std_logic
);
END Reset_Delay;
ARCHITECTURE Arch OF Reset_Delay IS
SIGNAL Cont : std_logic_vector(19 DOWNTO 0):=X"00000";
BEGIN
PROCESS
BEGIN
WAIT UNTIL rising_edge (iCLK);
IF Cont /= X"FFFFF" THEN
-- IF Cont /= X"0000F" THEN
Cont <= Cont + '1';
oRESET <= '1';
ELSE
oRESET <= '0';
END IF;
END PROCESS;
END Arch;
|
gpl-3.0
|
Ana06/function-graphing-FPGA
|
logaritmo.vhd
|
2
|
11477
|
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 16:20:31 02/20/2014
-- Design Name:
-- Module Name: logaritmo - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity logaritmo is
Port ( valor : in STD_LOGIC_VECTOR (20 downto 0);
log : out STD_LOGIC_VECTOR (20 downto 0);
xlogmx : out STD_LOGIC_VECTOR (20 downto 0));
end logaritmo;
architecture Behavioral of logaritmo is
begin
with valor select
log <=
"111111111001000100011" when "000000000000000100000",
"111111111010011101000" when "000000000000001000000",
"111111111011010001000" when "000000000000001100000",
"111111111011110101110" when "000000000000010000000",
"111111111100010010011" when "000000000000010100000",
"111111111100101001101" when "000000000000011000000",
"111111111100111101011" when "000000000000011100000",
"111111111101001110100" when "000000000000100000000",
"111111111101011101101" when "000000000000100100000",
"111111111101101011000" when "000000000000101000000",
"111111111101110111010" when "000000000000101100000",
"111111111110000010011" when "000000000000110000000",
"111111111110001100101" when "000000000000110100000",
"111111111110010110001" when "000000000000111000000",
"111111111110011111000" when "000000000000111100000",
"111111111110100111010" when "000000000001000000000",
"111111111110101111000" when "000000000001000100000",
"111111111110110110010" when "000000000001001000000",
"111111111110111101010" when "000000000001001100000",
"111111111111000011110" when "000000000001010000000",
"111111111111001010000" when "000000000001010100000",
"111111111111010000000" when "000000000001011000000",
"111111111111010101101" when "000000000001011100000",
"111111111111011011001" when "000000000001100000000",
"111111111111100000011" when "000000000001100100000",
"111111111111100101011" when "000000000001101000000",
"111111111111101010010" when "000000000001101100000",
"111111111111101110111" when "000000000001110000000",
"111111111111110011011" when "000000000001110100000",
"111111111111110111101" when "000000000001111000000",
"111111111111111011111" when "000000000001111100000",
"000000000000000000000" when "000000000010000000000",
"000000000000000111110" when "000000000010001000000",
"000000000000001111000" when "000000000010010000000",
"000000000000010101111" when "000000000010011000000",
"000000000000011100100" when "000000000010100000000",
"000000000000100010110" when "000000000010101000000",
"000000000000101000110" when "000000000010110000000",
"000000000000101110011" when "000000000010111000000",
"000000000000110011111" when "000000000011000000000",
"000000000000111001000" when "000000000011001000000",
"000000000000111110001" when "000000000011010000000",
"000000000001000010111" when "000000000011011000000",
"000000000001000111101" when "000000000011100000000",
"000000000001001100000" when "000000000011101000000",
"000000000001010000011" when "000000000011110000000",
"000000000001010100101" when "000000000011111000000",
"000000000001011000101" when "000000000100000000000",
"000000000001100000011" when "000000000100010000000",
"000000000001100111110" when "000000000100100000000",
"000000000001101110101" when "000000000100110000000",
"000000000001110101010" when "000000000101000000000",
"000000000001111011100" when "000000000101010000000",
"000000000010000001011" when "000000000101100000000",
"000000000010000111001" when "000000000101110000000",
"000000000010001100100" when "000000000110000000000",
"000000000010010001110" when "000000000110010000000",
"000000000010010110110" when "000000000110100000000",
"000000000010011011101" when "000000000110110000000",
"000000000010100000010" when "000000000111000000000",
"000000000010100100110" when "000000000111010000000",
"000000000010101001001" when "000000000111100000000",
"000000000010101101011" when "000000000111110000000",
"000000000010110001011" when "000000001000000000000",
"000000000010111001001" when "000000001000100000000",
"000000000011000000100" when "000000001001000000000",
"000000000011000111011" when "000000001001100000000",
"000000000011001110000" when "000000001010000000000",
"000000000011010100010" when "000000001010100000000",
"000000000011011010001" when "000000001011000000000",
"000000000011011111111" when "000000001011100000000",
"000000000011100101010" when "000000001100000000000",
"000000000011101010100" when "000000001100100000000",
"000000000011101111100" when "000000001101000000000",
"000000000011110100011" when "000000001101100000000",
"000000000011111001000" when "000000001110000000000",
"000000000011111101100" when "000000001110100000000",
"000000000100000001111" when "000000001111000000000",
"000000000100000110000" when "000000001111100000000",
"000000000100001010001" when "000000010000000000000",
"000000000100010001111" when "000000010001000000000",
"000000000100011001001" when "000000010010000000000",
"000000000100100000001" when "000000010011000000000",
"000000000100100110101" when "000000010100000000000",
"000000000100101100111" when "000000010101000000000",
"000000000100110010111" when "000000010110000000000",
"000000000100111000100" when "000000010111000000000",
"000000000100111110000" when "000000011000000000000",
"000000000101000011010" when "000000011001000000000",
"000000000101001000010" when "000000011010000000000",
"000000000101001101001" when "000000011011000000000",
"000000000101010001110" when "000000011100000000000",
"000000000101010110010" when "000000011101000000000",
"000000000101011010101" when "000000011110000000000",
"000000000101011110110" when "000000011111000000000",
"000000000101100010111" when "000000100000000000000",
"000000000000000000000" when others;
with valor select
xlogmx <=
"111111111111101110001" when "000000000000000100000",
"111111111111100001110" when "000000000000001000000",
"111111111111010111100" when "000000000000001100000",
"111111111111001110101" when "000000000000010000000",
"111111111111000110110" when "000000000000010100000",
"111111111110111111110" when "000000000000011000000",
"111111111110111001011" when "000000000000011100000",
"111111111110110011101" when "000000000000100000000",
"111111111110101110010" when "000000000000100100000",
"111111111110101001011" when "000000000000101000000",
"111111111110100101000" when "000000000000101100000",
"111111111110100000111" when "000000000000110000000",
"111111111110011101001" when "000000000000110100000",
"111111111110011001101" when "000000000000111000000",
"111111111110010110100" when "000000000000111100000",
"111111111110010011101" when "000000000001000000000",
"111111111110010000111" when "000000000001000100000",
"111111111110001110100" when "000000000001001000000",
"111111111110001100011" when "000000000001001100000",
"111111111110001010011" when "000000000001010000000",
"111111111110001000100" when "000000000001010100000",
"111111111110000111000" when "000000000001011000000",
"111111111110000101100" when "000000000001011100000",
"111111111110000100011" when "000000000001100000000",
"111111111110000011010" when "000000000001100100000",
"111111111110000010011" when "000000000001101000000",
"111111111110000001101" when "000000000001101100000",
"111111111110000001000" when "000000000001110000000",
"111111111110000000100" when "000000000001110100000",
"111111111110000000010" when "000000000001111000000",
"111111111110000000000" when "000000000001111100000",
"111111111110000000000" when "000000000010000000000",
"111111111110000000001" when "000000000010001000000",
"111111111110000000111" when "000000000010010000000",
"111111111110000010000" when "000000000010011000000",
"111111111110000011101" when "000000000010100000000",
"111111111110000101101" when "000000000010101000000",
"111111111110001000000" when "000000000010110000000",
"111111111110001010110" when "000000000010111000000",
"111111111110001101110" when "000000000011000000000",
"111111111110010001010" when "000000000011001000000",
"111111111110010100111" when "000000000011010000000",
"111111111110011001000" when "000000000011011000000",
"111111111110011101010" when "000000000011100000000",
"111111111110100001111" when "000000000011101000000",
"111111111110100110110" when "000000000011110000000",
"111111111110101100000" when "000000000011111000000",
"111111111110110001011" when "000000000100000000000",
"111111111110111101000" when "000000000100010000000",
"111111111111001001100" when "000000000100100000000",
"111111111111010110111" when "000000000100110000000",
"111111111111100101001" when "000000000101000000000",
"111111111111110100010" when "000000000101010000000",
"000000000000000100000" when "000000000101100000000",
"000000000000010100101" when "000000000101110000000",
"000000000000100101110" when "000000000110000000000",
"000000000000110111110" when "000000000110010000000",
"000000000001001010010" when "000000000110100000000",
"000000000001011101011" when "000000000110110000000",
"000000000001110001001" when "000000000111000000000",
"000000000010000101100" when "000000000111010000000",
"000000000010011010011" when "000000000111100000000",
"000000000010101111110" when "000000000111110000000",
"000000000011000101110" when "000000001000000000000",
"000000000011110011000" when "000000001000100000000",
"000000000100100010010" when "000000001001000000000",
"000000000101010011010" when "000000001001100000000",
"000000000110000110000" when "000000001010000000000",
"000000000110111010010" when "000000001010100000000",
"000000000111110000001" when "000000001011000000000",
"000000001000100111011" when "000000001011100000000",
"000000001001100000000" when "000000001100000000000",
"000000001010011010000" when "000000001100100000000",
"000000001011010101010" when "000000001101000000000",
"000000001100010001110" when "000000001101100000000",
"000000001101001111100" when "000000001110000000000",
"000000001110001110010" when "000000001110100000000",
"000000001111001110010" when "000000001111000000000",
"000000010000001111010" when "000000001111100000000",
"000000010001010001010" when "000000010000000000000",
"000000010011011000011" when "000000010001000000000",
"000000010101100011001" when "000000010010000000000",
"000000010111110001100" when "000000010011000000000",
"000000011010000011010" when "000000010100000000000",
"000000011100011000001" when "000000010101000000000",
"000000011110110000001" when "000000010110000000000",
"000000100001001011001" when "000000010111000000000",
"000000100011101000110" when "000000011000000000000",
"000000100110001001001" when "000000011001000000000",
"000000101000101100000" when "000000011010000000000",
"000000101011010001011" when "000000011011000000000",
"000000101101111001001" when "000000011100000000000",
"000000110000100011001" when "000000011101000000000",
"000000110011001111011" when "000000011110000000000",
"000000110101111101110" when "000000011111000000000",
"000000111000101110010" when "000000100000000000000",
"000000000000000000000" when others;
end Behavioral;
|
gpl-3.0
|
Ana06/function-graphing-FPGA
|
kbdDataCtrl.vhd
|
2
|
4214
|
----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdDataCtrl
-- Target Devices:
-- Tool versions: XilINx ISE 14.4
-- Tool versions:
-- Description:
--
-- DepENDencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
ENTITY KbdDataCtrl IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
busyRx : IN STD_LOGIC;
busyTx : IN STD_LOGIC;
validDataKb : IN STD_LOGIC;
dataINIBuff : IN STD_LOGIC;
DataFromKb : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
DataFromIBuff : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Tx_en : OUT STD_LOGIC;
Rx_en : OUT STD_LOGIC;
rd_en : OUT STD_LOGIC;
wr_en : OUT STD_LOGIC;
DataTokb : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
DataToOBuff : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END KbdDataCtrl;
ARCHITECTURE Behavioral OF KbdDataCtrl IS
SIGNAL ValidDataINIbuff : std_logic;
SIGNAL GetDataIBuff : std_logic;
SIGNAL StartTransmit : std_logic;
BEGIN
PROCESS(Rst,Clk)
BEGIN
IF(rst = '1') THEN
rd_en <= '0';
wr_en <= '0';
Tx_en <= '0';
Rx_en <= '0';
ValidDataINIbuff <= '0';
startTransmit <= '0';
GetDataIBuff <= '0';
DataToOBuff <= (OTHERS => '0');
DataTokb <= (OTHERS => '0');
ELSIF(clk = '1') and (clk'event) THEN
IF(busyRx = '0') and ( busyTx = '0') THEN
IF (startTransmit = '1') THEN
Tx_en <= '1';
Rx_en <= '0';
rd_en <= '0';
wr_en <= '0';
ValidDataINIbuff <= '0';
GetDataIBuff <= '0';
startTransmit <= '0';
ELSIF (GetDataIBuff = '1') THEN
dataToKb <= dataFromIBuff;
Tx_en <= '0';
Rx_en <= '0';
rd_en <= '0';
wr_en <= '0';
ValidDataINIbuff <= '0';
GetDataIBuff <= '0';
startTransmit <= '1';
ELSIF (ValidDataINIbuff = '1') THEN
Tx_en <= '0';
Rx_en <= '0';
rd_en <= '0';
wr_en <= '0';
ValidDataINIbuff <= '0';
GetDataIBuff <= '1';
startTransmit <= '0';
ELSIF(dataINIbuff = '0') THEN
rd_en <= '1';
wr_en <= '0';
Tx_en <= '0';
Rx_en <= '0';
ValidDataINIbuff <= '1';
GetDataIBuff <= '0';
startTransmit <= '0';
ELSE
rd_en <= '0';
wr_en <= '0';
Tx_en <= '0';
Rx_en <= '1';
startTransmit <= '0';
GetDataIBuff <= '0';
ValidDataINIbuff <= '0';
END IF;
ELSIF(busyTx = '1') THEN
wr_en <= '0';
rd_en <= '0';
ValidDataINIbuff <= '0';
startTransmit <= '0';
Tx_en <= '0';
Rx_en <= '0';
ELSIF(busyRx = '1') THEN
Tx_en <= '0';
Rx_en <= '1';
rd_en <= '0';
wr_en <= '0';
IF (validDataKb = '1') THEN
dataToOBuff <= dataFromKb;
wr_en <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END Behavioral;
|
gpl-3.0
|
bruskajp/EE-316
|
Project1/lcd_driver.vhd
|
1
|
8828
|
----------------------------------------------------------------------------------
-- Institution: Clarkson Univeristy
-- Engineers: Zander Blasingame and Brandon Norris
--
-- Create Date: 11/11/2016 21:06:23
-- Design Name:
-- Module Name: lcd_driver - Behavioral
-- Project Name:
-- Target Devices: Altera DE2
-- Tool Versions:
-- Description: Created for the final of EE 365, repurposed for EE 316.
-- Display Model:
--
-- | Mode Op/Prog State Reset/Fwd/Bckwd |
-- | Enable/Disable addr data |
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lcd_driver is
Generic (
-- Input clk frequency is given as 50MHz
-- Internal clk frequency is 200Hz
-- Number picked such that T = 5 ms
constant cnt_max : integer := 83333--333
);
Port (
clk : in std_logic;
reset : in std_logic;
sys_fb : in std_logic;
sys_en : in std_logic;
sys_prog : in std_logic;
is_addr : in std_logic;
address : in std_logic_vector(7 downto 0);
data : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(7 downto 0);
enable_out : out std_logic;
mode_select_out : out std_logic
);
end lcd_driver;
architecture Behavioral of lcd_driver is
type word_mode is array (0 to 7) of std_logic_vector(7 downto 0);
-- Define signals here
signal lut_sel : integer range 0 to 47;
signal enable_sel : integer range 0 to 3;
signal clk_enable : std_logic := '1';
signal clk_cnt : integer range 0 to cnt_max;
signal sys_state_ascii : word_mode;
signal sys_mode_ascii : word_mode;
signal sys_en_ascii : word_mode;
-- Function to convert hex into ascii
function hex_to_ascii(hex_code : std_logic_vector(3 downto 0))
return std_logic_vector is
variable output : std_logic_vector(7 downto 0) := x"30";
begin
case hex_code is
when x"0" => output := x"30";
when x"1" => output := x"31";
when x"2" => output := x"32";
when x"3" => output := x"33";
when x"4" => output := x"34";
when x"5" => output := x"35";
when x"6" => output := x"36";
when x"7" => output := x"37";
when x"8" => output := x"38";
when x"9" => output := x"39";
when x"A" => output := x"41";
when x"B" => output := x"42";
when x"C" => output := x"43";
when x"D" => output := x"44";
when x"E" => output := x"45";
when x"F" => output := x"46";
when others => output := x"30";
end case;
return output;
end hex_to_ascii;
begin
-- Clock enabler
process(clk)
begin
if rising_edge(clk) then
if clk_cnt = cnt_max then
clk_cnt <= 0;
clk_enable <= '1';
else
clk_cnt <= clk_cnt + 1;
clk_enable <= '0';
end if;
end if;
end process;
-- enable_out selection clock
process(clk)
begin
if rising_edge(clk) and clk_enable = '1' then
if enable_sel = 3 then
enable_sel <= 1;
else
enable_sel <= enable_sel + 1;
end if;
end if;
end process;
-- data_out selection clock
process(clk)
begin
if rising_edge(clk) and clk_enable = '1' and enable_sel = 3 then
if lut_sel = 43 then
lut_sel <= 10;
else
lut_sel <= lut_sel + 1;
end if;
end if;
end process;
-- Mux for mode
process(sys_prog)
begin
if sys_prog = '0' then
sys_mode_ascii <= (x"4F", x"70", x"65", x"72", x"61", x"74", x"65", x"20"); -- Operate
else
sys_mode_ascii <= (x"50", x"72", x"6F", x"67", x"72", x"61", x"6D", x"20"); -- Program
end if;
end process;
-- Mux for state
process(reset, sys_fb)
begin
if reset = '1' then
sys_state_ascii <= (x"52", x"65", x"73", x"65", x"74", x"20", x"20", x"20"); -- Reset
else
if sys_fb = '1' then
sys_state_ascii <= (x"46", x"6F", x"72", x"77", x"61", x"72", x"64", x"20"); -- Forward
else
sys_state_ascii <= (x"42", x"61", x"63", x"6B", x"77", x"61", x"72", x"64"); -- Backward
end if;
end if;
end process;
-- Mux for sys enable ascii
process(sys_en, sys_prog, is_addr)
begin
if sys_prog = '0' then
if sys_en = '1' then
sys_en_ascii <= (x"45", x"6E", x"61", x"62", x"6C", x"65", x"20", x"20"); -- Enable
else
sys_en_ascii <= (x"44", x"69", x"73", x"61", x"62", x"6C", x"65", x"20"); -- Disable
end if;
else
if is_addr = '1' then
sys_en_ascii <= (x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20"); -- Address
else
sys_en_ascii <= (x"44", x"61", x"74", x"61", x"20", x"20", x"20", x"20"); -- Data
end if;
end if;
end process;
-- LUT for enable_out default 0
with enable_sel select enable_out <=
'1' when 0,
'0' when 1,
'1' when 2,
'0' when 3,
'0' when others;
-- LUT for data_out and mode_select_out default is #ff and 1 respectively
process(lut_sel)
begin
case lut_sel is
-- Initialize
when 0 => data_out <= x"38"; mode_select_out <= '0';
when 1 => data_out <= x"38"; mode_select_out <= '0';
when 2 => data_out <= x"38"; mode_select_out <= '0';
when 3 => data_out <= x"38"; mode_select_out <= '0';
when 4 => data_out <= x"38"; mode_select_out <= '0';
when 5 => data_out <= x"38"; mode_select_out <= '0';
when 6 => data_out <= x"01"; mode_select_out <= '0';
when 7 => data_out <= x"0C"; mode_select_out <= '0';
when 8 => data_out <= x"06"; mode_select_out <= '0';
when 9 => data_out <= x"80"; mode_select_out <= '0';
-- Op/Prog
when 10 => data_out <= sys_mode_ascii(0); mode_select_out <= '1';
when 11 => data_out <= sys_mode_ascii(1); mode_select_out <= '1';
when 12 => data_out <= sys_mode_ascii(2); mode_select_out <= '1';
when 13 => data_out <= sys_mode_ascii(3); mode_select_out <= '1';
when 14 => data_out <= sys_mode_ascii(4); mode_select_out <= '1';
when 15 => data_out <= sys_mode_ascii(5); mode_select_out <= '1';
when 16 => data_out <= sys_mode_ascii(6); mode_select_out <= '1';
when 17 => data_out <= sys_mode_ascii(7); mode_select_out <= '1';
-- System State
when 18 => data_out <= sys_state_ascii(0); mode_select_out <= '1';
when 19 => data_out <= sys_state_ascii(1); mode_select_out <= '1';
when 20 => data_out <= sys_state_ascii(2); mode_select_out <= '1';
when 21 => data_out <= sys_state_ascii(3); mode_select_out <= '1';
when 22 => data_out <= sys_state_ascii(4); mode_select_out <= '1';
when 23 => data_out <= sys_state_ascii(5); mode_select_out <= '1';
when 24 => data_out <= sys_state_ascii(6); mode_select_out <= '1';
when 25 => data_out <= sys_state_ascii(7); mode_select_out <= '1';
-- Newline
when 26 => data_out <= x"C0"; mode_select_out <= '0';
-- Enable / Disable
when 27 => data_out <= sys_en_ascii(0); mode_select_out <= '1';
when 28 => data_out <= sys_en_ascii(1); mode_select_out <= '1';
when 29 => data_out <= sys_en_ascii(2); mode_select_out <= '1';
when 30 => data_out <= sys_en_ascii(3); mode_select_out <= '1';
when 31 => data_out <= sys_en_ascii(4); mode_select_out <= '1';
when 32 => data_out <= sys_en_ascii(5); mode_select_out <= '1';
when 33 => data_out <= sys_en_ascii(6); mode_select_out <= '1';
when 34 => data_out <= sys_en_ascii(7); mode_select_out <= '1';
-- Address ex. x00
when 35 => data_out <= x"78"; mode_select_out <= '1';
when 36 => data_out <= hex_to_ascii(address(7 downto 4)); mode_select_out <= '1';
when 37 => data_out <= hex_to_ascii(address(3 downto 0)); mode_select_out <= '1';
-- Data ex. xA0A0
when 38 => data_out <= x"78"; mode_select_out <= '1';
when 39 => data_out <= hex_to_ascii(data(15 downto 12)); mode_select_out <= '1';
when 40 => data_out <= hex_to_ascii(data(11 downto 8)); mode_select_out <= '1';
when 41 => data_out <= hex_to_ascii(data(7 downto 4)); mode_select_out <= '1';
when 42 => data_out <= hex_to_ascii(data(3 downto 0)); mode_select_out <= '1';
-- Jump to first line
when 43 => data_out <= x"80"; mode_select_out <= '0';
-- Catch errors
when others => data_out <= x"FF"; mode_select_out <= '1';
end case;
end process;
end Behavioral;
|
gpl-3.0
|
bruskajp/EE-316
|
Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/ip/sig1dualRAM/misc/blk_mem_gen_v8_3.vhd
|
4
|
8325
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_3 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_3;
architecture xilinx of blk_mem_gen_v8_3_3 is
begin
end
architecture xilinx;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Immortal_Chip/modules_with_fault_injectors/to_be_tested/Arbiter_one_hot_with_checkers_with_FI.vhd
|
1
|
19331
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end;
architecture behavior of Arbiter is
-- TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic;
signal Xbar_sel_sig: std_logic_vector(4 downto 0);
-- New signals used for integration of FI(s) in LBDR module
signal Req_N_faulty, Req_E_faulty, Req_W_faulty, Req_S_faulty, Req_L_faulty : std_logic;
signal DCTS_faulty : std_logic;
SIGNAL state_faulty, state_in_faulty, next_state_faulty : STATE_TYPE := IDLE;
SIGNAL RTS_FF_faulty, RTS_FF_in_faulty: std_logic;
signal Grant_N_sig_faulty, Grant_E_sig_faulty, Grant_W_sig_faulty, Grant_S_sig_faulty, Grant_L_sig_faulty: std_logic;
signal Xbar_sel_sig_faulty: std_logic_vector(4 downto 0);
component Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32;
ADDRESS_WIDTH : integer := 5);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component shift_register_serial_in is
generic (
REG_WIDTH: integer := 44
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in_serial: in std_logic;
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end component;
signal FI_add_sta: std_logic_vector(43 downto 0); -- 36 bits for inputs and internal signals
-- 6 bits for fault injection location address (ceil of log2(36) = 6)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (35 downto 0);
signal faulty_signals: std_logic_vector(35 downto 0); -- 36 bits for inputs, internal and output signals (with one fault injected in one of them)
begin
non_faulty_signals <= Req_N & Req_E & Req_W & Req_S & Req_L &
DCTS &
state & state_in & next_state &
RTS_FF & RTS_FF_in &
Grant_N_sig & Grant_E_sig & Grant_W_sig & Grant_S_sig & Grant_L_sig &
Xbar_sel_sig;
FI: fault_injector generic map(DATA_WIDTH => 36, ADDRESS_WIDTH => 6)
port map (data_in=> non_faulty_signals , address=> FI_add_sta(7 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals
);
-- Extracting faulty values for input, internal and output signals
Req_N_faulty <= faulty_signals(35);
Req_E_faulty <= faulty_signals(34);
Req_W_faulty <= faulty_signals(33);
Req_S_faulty <= faulty_signals(32);
Req_L_faulty <= faulty_signals(31);
DCTS_faulty <= faulty_signals(30);
state_faulty <= faulty_signals(29 downto 24);
state_in_faulty <= faulty_signals(23 downto 18);
next_state_faulty <= faulty_signals(17 downto 12);
RTS_FF_faulty <= faulty_signals(11);
RTS_FF_in_faulty <= faulty_signals(10);
Grant_N_sig_faulty <= faulty_signals(9);
Grant_E_sig_faulty <= faulty_signals(8);
Grant_W_sig_faulty <= faulty_signals(7);
Grant_S_sig_faulty <= faulty_signals(6);
Grant_L_sig_faulty <= faulty_signals(5);
Xbar_sel_sig_faulty <= faulty_signals(4 downto 0);
SR: shift_register_serial_in generic map(REG_WIDTH => 44)
port map( clk=> fault_clk, reset=>reset, shift=> shift,data_in_serial=> data_in_serial,
data_out_parallel=> FI_add_sta, data_out_serial=> data_out_serial
);
-- Arbiter checkers instantiation
ARBITERCHECKERS: Arbiter_checkers port map (
Req_N => Req_N,
Req_E => Req_E,
Req_W => Req_W,
Req_S => Req_S,
Req_L => Req_L,
DCTS => DCTS,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel=>Xbar_sel_sig,
state => state,
state_in => state_in,
next_state_out => next_state,
RTS_FF => RTS_FF,
RTS_FF_in => RTS_FF_in,
err_state_IDLE_xbar => err_state_IDLE_xbar,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE,
err_IDLE_Req_L => err_IDLE_Req_L,
err_Local_Req_L => err_Local_Req_L,
err_North_Req_N => err_North_Req_N,
err_IDLE_Req_N => err_IDLE_Req_N,
err_Local_Req_N => err_Local_Req_N,
err_South_Req_L => err_South_Req_L,
err_West_Req_L => err_West_Req_L,
err_South_Req_N => err_South_Req_N,
err_East_Req_L => err_East_Req_L,
err_West_Req_N => err_West_Req_N,
err_East_Req_N => err_East_Req_N,
err_next_state_onehot => err_next_state_onehot,
err_state_in_onehot => err_state_in_onehot,
err_state_north_xbar_sel => err_state_north_xbar_sel,
err_state_east_xbar_sel => err_state_east_xbar_sel,
err_state_west_xbar_sel => err_state_west_xbar_sel,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in_faulty;
RTS_FF <= RTS_FF_in_faulty;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
-- Becuase of checkers we did this!
Grant_N <= Grant_N_sig;
Grant_E <= Grant_E_sig;
Grant_W <= Grant_W_sig;
Grant_S <= Grant_S_sig;
Grant_L <= Grant_L_sig;
Xbar_sel <= Xbar_sel_sig;
process(RTS_FF_faulty, DCTS_faulty, state_faulty, next_state_faulty)begin
if RTS_FF_faulty = '1' and DCTS_faulty = '0' then
state_in <= state_faulty;
else
state_in <= next_state_faulty;
end if;
end process;
process(state_faulty, RTS_FF_faulty, DCTS_faulty)begin
if state_faulty = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF_faulty = '1' and DCTS_faulty = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state_faulty, Req_N_faulty, Req_E_faulty, Req_W_faulty, Req_S_faulty, Req_L_faulty, DCTS_faulty, RTS_FF_faulty)begin
Grant_N_sig <= '0';
Grant_E_sig <= '0';
Grant_W_sig <= '0';
Grant_S_sig <= '0';
Grant_L_sig <= '0';
Xbar_sel_sig <= "00000";
case(state_faulty) is
when IDLE =>
Xbar_sel_sig <= "00000";
If Req_L_faulty = '1' then
next_state <= Local;
elsif Req_N_faulty = '1' then
next_state <= North;
elsif Req_E_faulty = '1' then
next_state <= East;
elsif Req_W_faulty = '1' then
next_state <= West;
elsif Req_S_faulty = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N_sig <= DCTS_faulty and RTS_FF_faulty ;
Xbar_sel_sig <= "00001";
If Req_N_faulty = '1' then
next_state <= North;
elsif Req_E_faulty = '1' then
next_state <= East;
elsif Req_W_faulty = '1' then
next_state <= West;
elsif Req_S_faulty = '1' then
next_state <= South;
elsif Req_L_faulty = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E_sig <= DCTS_faulty and RTS_FF_faulty;
Xbar_sel_sig <= "00010";
If Req_E_faulty = '1' then
next_state <= East;
elsif Req_W_faulty = '1' then
next_state <= West;
elsif Req_S_faulty = '1' then
next_state <= South;
elsif Req_L_faulty = '1' then
next_state <= Local;
elsif Req_N_faulty = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W_sig <= DCTS_faulty and RTS_FF_faulty;
Xbar_sel_sig <= "00100";
If Req_W_faulty = '1' then
next_state <= West;
elsif Req_S_faulty = '1' then
next_state <= South;
elsif Req_L_faulty = '1' then
next_state <= Local;
elsif Req_N_faulty = '1' then
next_state <= North;
elsif Req_E_faulty = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S_sig <= DCTS_faulty and RTS_FF_faulty;
Xbar_sel_sig <= "01000";
If Req_S_faulty = '1' then
next_state <= South;
elsif Req_L_faulty = '1' then
next_state <= Local;
elsif Req_N_faulty = '1' then
next_state <= North;
elsif Req_E_faulty = '1' then
next_state <= East;
elsif Req_W_faulty = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L_sig <= DCTS_faulty and RTS_FF_faulty;
Xbar_sel_sig <= "10000";
If Req_L_faulty = '1' then
next_state <= Local;
elsif Req_N_faulty = '1' then
next_state <= North;
elsif Req_E_faulty = '1' then
next_state <= East;
elsif Req_W_faulty = '1' then
next_state <= West;
elsif Req_S_faulty = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
|
gpl-3.0
|
SoCdesign/EHA
|
RTL/Credit_Based/Credit_Based_FC/Router_32_bit_credit_based_parity.vhd
|
1
|
16138
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic
);
end router_credit_based_parity;
architecture behavior of router_credit_based_parity is
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32
);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, valid_in =>valid_in_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, valid_in =>valid_in_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, valid_in =>valid_in_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, valid_in =>valid_in_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, valid_in =>valid_in_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
gpl-3.0
|
JarrettR/FPGA-Cryptoparty
|
FPGA/hdl/sha1_process_buffer.vhd
|
1
|
9744
|
--------------------------------------------------------------------------------
-- Final stage of SHA1 algorithm - process existing buffer and calc outputs
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha1_pkg.all;
entity sha1_process_buffer is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_full;
load_i : in std_ulogic;
new_i : in std_ulogic;
dat_w_i : in w_output;
dat_w_o : out w_output;
valid_o : out std_ulogic
);
end sha1_process_buffer;
architecture RTL of sha1_process_buffer is
signal w: w_full;
--signal w_con: w_full;
signal w_hold: w_full;
signal running: std_ulogic;
-- synthesis translate_off
signal test_word_1: std_ulogic_vector(0 to 31);
signal test_word_2: std_ulogic_vector(0 to 31);
signal test_word_3: std_ulogic_vector(0 to 31);
signal test_word_4: std_ulogic_vector(0 to 31);
signal test_word_5: std_ulogic_vector(0 to 31);
-- synthesis translate_on
signal i : integer range 0 to 79;
signal a: unsigned(0 to 31);
signal b: unsigned(0 to 31);
signal c: unsigned(0 to 31);
signal d: unsigned(0 to 31);
signal e: unsigned(0 to 31);
signal a_con: std_ulogic_vector(0 to 31);
signal b_con: std_ulogic_vector(0 to 31);
signal c_con: std_ulogic_vector(0 to 31);
signal d_con: std_ulogic_vector(0 to 31);
signal e_con: std_ulogic_vector(0 to 31);
--Algorithm variables
constant h0i : std_ulogic_vector(0 to 31) := X"67452301"; -- H0 (a)
constant h1i : std_ulogic_vector(0 to 31) := X"EFCDAB89"; -- H1 (b)
constant h2i : std_ulogic_vector(0 to 31) := X"98BADCFE"; -- H2 (c)
constant h3i : std_ulogic_vector(0 to 31) := X"10325476"; -- H3 (d)
constant h4i : std_ulogic_vector(0 to 31) := X"C3D2E1F0"; -- H4 (e)
constant k0 : std_ulogic_vector(0 to 31) := X"5A827999"; -- ( 0 <= t <= 19)
constant k1 : std_ulogic_vector(0 to 31) := X"6ED9EBA1"; -- (20 <= t <= 39)
constant k2 : std_ulogic_vector(0 to 31) := X"8F1BBCDC"; -- (40 <= t <= 59)
constant k3 : std_ulogic_vector(0 to 31) := X"CA62C1D6"; -- (60 <= t <= 79)
signal h0 : std_ulogic_vector(0 to 31) := h0i;
signal h1 : std_ulogic_vector(0 to 31) := h1i;
signal h2 : std_ulogic_vector(0 to 31) := h2i;
signal h3 : std_ulogic_vector(0 to 31) := h3i;
signal h4 : std_ulogic_vector(0 to 31) := h4i;
signal h0out : unsigned(0 to 31);
signal h1out : unsigned(0 to 31);
signal h2out : unsigned(0 to 31);
signal h3out : unsigned(0 to 31);
signal h4out : unsigned(0 to 31);
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
i <= 0;
--running <= '0';
--Todo: Reset input too, if needed
--for x in 0 to 79 loop
-- w_hold(x) <= "00000000000000000000000000000000";
--end loop;
h0 <= h0i;
h1 <= h1i;
h2 <= h2i;
h3 <= h3i;
h4 <= h4i;
else
if load_i = '1' then
if new_i = '1' then
h0 <= h0i;
h1 <= h1i;
h2 <= h2i;
h3 <= h3i;
h4 <= h4i;
a <= unsigned((h1i and h2i) or ((not h1i) and h3i)) +
rotate_left(unsigned(h0i), 5) +
unsigned(h4i) +
unsigned(dat_i(0)) +
unsigned(k0);
b <= unsigned(h0i);
c <= rotate_left(unsigned(h1i), 30);
d <= unsigned(h2i);
e <= unsigned(h3i);
else
h0 <= dat_w_i(0);
h1 <= dat_w_i(1);
h2 <= dat_w_i(2);
h3 <= dat_w_i(3);
h4 <= dat_w_i(4);
a <= unsigned((dat_w_i(1) and dat_w_i(2)) or ((not dat_w_i(1)) and dat_w_i(3))) +
rotate_left(unsigned(dat_w_i(0)), 5) +
unsigned(dat_w_i(4)) +
unsigned(dat_i(0)) +
unsigned(k0);
b <= unsigned(dat_w_i(0));
c <= rotate_left(unsigned(dat_w_i(1)), 30);
d <= unsigned(dat_w_i(2));
e <= unsigned(dat_w_i(3));
end if;
i <= 0;
else
--TEMP = S^5(A) + f(t;B,C,D) + E + W(t) + K(t);
--Alt: gotta be better way!
case i is
--f(t;B,C,D) = (B AND C) OR ((NOT B) AND D)
when 0 to 18 => a <= unsigned((b_con and c_con) or ((not b_con) and d_con)) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k0);
--f(t;B,C,D) = B XOR C XOR D
when 19 to 38 => a <= unsigned(b_con xor c_con xor d_con) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k1);
--f(t;B,C,D) = (B AND C) OR (B AND D) OR (C AND D)
when 39 to 58 => a <= unsigned((b_con and c_con) or (b_con and d_con) or (c_con and d_con)) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k2);
--f(t;B,C,D) = B XOR C XOR D
when 59 to 78 => a <= unsigned(b_con xor c_con xor d_con) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i + 1)) +
unsigned(k3);
when 79 => a <= unsigned(b_con xor c_con xor d_con) +
rotate_left(unsigned(a_con), 5) +
unsigned(e_con) +
unsigned(w(i)) +
unsigned(k3);
end case;
--E = D; D = C; C = S^30(B); B = A; A = TEMP;
e <= unsigned(d_con);
d <= unsigned(c_con);
c <= rotate_left(unsigned(b_con), 30);
b <= unsigned(a_con);
i <= i + 1;
end if;
if i = 79 then
--i <= 0;
--Todo: AND 'running' signal with i = 79 to stop incorrect 'valid_o' outputs
valid_o <= '1';
h0out <= unsigned(h0) + a;
h1out <= unsigned(h1) + b;
h2out <= unsigned(h2) + c;
h3out <= unsigned(h3) + d;
h4out <= unsigned(h4) + e;
else
valid_o <= '0';
end if;
end if;
end if;
end process;
dat_w_o(0) <= std_ulogic_vector(h0out);
dat_w_o(1) <= std_ulogic_vector(h1out);
dat_w_o(2) <= std_ulogic_vector(h2out);
dat_w_o(3) <= std_ulogic_vector(h3out);
dat_w_o(4) <= std_ulogic_vector(h4out);
w <= dat_i;
--w_con <= w;
a_con <= std_ulogic_vector(a);
b_con <= std_ulogic_vector(b);
c_con <= std_ulogic_vector(c);
d_con <= std_ulogic_vector(d);
e_con <= std_ulogic_vector(e);
-- synthesis translate_off
test_word_1 <= w(0);
test_word_2 <= w(79);
test_word_3 <= h0;
test_word_4 <= std_ulogic_vector(h0out);
test_word_5 <= std_ulogic_vector(h1out);
-- synthesis translate_on
end RTL;
|
gpl-3.0
|
freecores/usb_fpga_1_15
|
examples/usb-fpga-2.04/2.04b/lightshow/fpga/lightshow.vhd
|
17
|
3116
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led1 : out std_logic_vector(9 downto 0); -- LED1 on debug board
led2 : out std_logic_vector(19 downto 0); -- LED2 + LED3 on debug board
sw : in std_logic_vector(3 downto 0);
fxclk : in std_logic
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern1 is array(9 downto 0) of integer range 0 to 255;
type tPattern2 is array(19 downto 0) of integer range 0 to 255;
signal pattern1 : tPattern1 := (0, 10, 41, 92, 163, 255, 163, 92, 41, 10); -- pattern for LED1
signal pattern20 : tPattern2 := (0, 1, 2, 9, 16, 25, 36, 49, 64, 81, 64, 49, 36, 25, 16, 9, 2, 1, 0, 0); -- 1st pattern for LED2
signal pattern21 : tPattern2 := (0, 19, 77, 174, 77, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- 2nd pattern for LED2
signal pattern2 : tPattern2; -- pattern20 + pattern21
signal cnt1,cnt20, cnt21 : std_logic_vector(22 downto 0);
signal pwm_cnt : std_logic_vector(19 downto 0);
signal pwm_cnt8 : std_logic_vector(7 downto 0);
begin
pwm_cnt8 <= pwm_cnt(19 downto 12);
dp_fxclk: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
-- pattern for led 1
if ( cnt1 >= conv_std_logic_vector(7200000,23) ) -- 1/1.5 Hz
then
if ( sw(0) = '1' )
then
pattern1(8 downto 0) <= pattern1(9 downto 1);
pattern1(9) <= pattern1(0);
else
pattern1(9 downto 1) <= pattern1(8 downto 0);
pattern1(0) <= pattern1(9);
end if;
cnt1 <= (others => '0');
else
cnt1 <= cnt1 + 1;
end if;
-- pattern for led 2
if ( ( cnt20 >= conv_std_logic_vector(4800000,23) ) or ( (sw(2)= '1') and (cnt20 >= conv_std_logic_vector(1600000,23)) ) ) -- SW1 off: 1/3Hz, SW1 on: 1Hz
then
pattern20(18 downto 0) <= pattern20(19 downto 1);
pattern20(19) <= pattern20(0);
cnt20 <= (others => '0');
else
cnt20 <= cnt20 + 1;
end if;
if ( ( cnt21 >= conv_std_logic_vector(2000000,23) ) or ( (sw(3)= '1') and (cnt21 >= conv_std_logic_vector(500000,23)) ) )
then
if ( sw(1) = '1' )
then
pattern21(18 downto 0) <= pattern21(19 downto 1);
pattern21(19) <= pattern21(0);
else
pattern21(19 downto 1) <= pattern21(18 downto 0);
pattern21(0) <= pattern21(19);
end if;
cnt21 <= (others => '0');
else
cnt21 <= cnt21 + 1;
end if;
for i in 0 to 19 loop
pattern2(i) <= pattern20(i) + pattern21(i);
end loop;
-- pwm
if ( pwm_cnt8 = conv_std_logic_vector(255,8) )
then
pwm_cnt <= ( others => '0' );
else
pwm_cnt <= pwm_cnt + 1;
end if;
-- led1
for i in 0 to 9 loop
if ( pwm_cnt8 < pattern1(i) )
then
led1(i) <= '1';
else
led1(i) <= '0';
end if;
end loop;
for i in 0 to 19 loop
if (pwm_cnt8 < pattern2(i) )
then
led2(i) <= '1';
else
led2(i) <= '0';
end if;
end loop;
end if;
end process dp_fxclk;
end RTL;
|
gpl-3.0
|
freecores/usb_fpga_1_15
|
examples/usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.vhd
|
17
|
3116
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led1 : out std_logic_vector(9 downto 0); -- LED1 on debug board
led2 : out std_logic_vector(19 downto 0); -- LED2 + LED3 on debug board
sw : in std_logic_vector(3 downto 0);
fxclk : in std_logic
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern1 is array(9 downto 0) of integer range 0 to 255;
type tPattern2 is array(19 downto 0) of integer range 0 to 255;
signal pattern1 : tPattern1 := (0, 10, 41, 92, 163, 255, 163, 92, 41, 10); -- pattern for LED1
signal pattern20 : tPattern2 := (0, 1, 2, 9, 16, 25, 36, 49, 64, 81, 64, 49, 36, 25, 16, 9, 2, 1, 0, 0); -- 1st pattern for LED2
signal pattern21 : tPattern2 := (0, 19, 77, 174, 77, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- 2nd pattern for LED2
signal pattern2 : tPattern2; -- pattern20 + pattern21
signal cnt1,cnt20, cnt21 : std_logic_vector(22 downto 0);
signal pwm_cnt : std_logic_vector(19 downto 0);
signal pwm_cnt8 : std_logic_vector(7 downto 0);
begin
pwm_cnt8 <= pwm_cnt(19 downto 12);
dp_fxclk: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
-- pattern for led 1
if ( cnt1 >= conv_std_logic_vector(7200000,23) ) -- 1/1.5 Hz
then
if ( sw(0) = '1' )
then
pattern1(8 downto 0) <= pattern1(9 downto 1);
pattern1(9) <= pattern1(0);
else
pattern1(9 downto 1) <= pattern1(8 downto 0);
pattern1(0) <= pattern1(9);
end if;
cnt1 <= (others => '0');
else
cnt1 <= cnt1 + 1;
end if;
-- pattern for led 2
if ( ( cnt20 >= conv_std_logic_vector(4800000,23) ) or ( (sw(2)= '1') and (cnt20 >= conv_std_logic_vector(1600000,23)) ) ) -- SW1 off: 1/3Hz, SW1 on: 1Hz
then
pattern20(18 downto 0) <= pattern20(19 downto 1);
pattern20(19) <= pattern20(0);
cnt20 <= (others => '0');
else
cnt20 <= cnt20 + 1;
end if;
if ( ( cnt21 >= conv_std_logic_vector(2000000,23) ) or ( (sw(3)= '1') and (cnt21 >= conv_std_logic_vector(500000,23)) ) )
then
if ( sw(1) = '1' )
then
pattern21(18 downto 0) <= pattern21(19 downto 1);
pattern21(19) <= pattern21(0);
else
pattern21(19 downto 1) <= pattern21(18 downto 0);
pattern21(0) <= pattern21(19);
end if;
cnt21 <= (others => '0');
else
cnt21 <= cnt21 + 1;
end if;
for i in 0 to 19 loop
pattern2(i) <= pattern20(i) + pattern21(i);
end loop;
-- pwm
if ( pwm_cnt8 = conv_std_logic_vector(255,8) )
then
pwm_cnt <= ( others => '0' );
else
pwm_cnt <= pwm_cnt + 1;
end if;
-- led1
for i in 0 to 9 loop
if ( pwm_cnt8 < pattern1(i) )
then
led1(i) <= '1';
else
led1(i) <= '0';
end if;
end loop;
for i in 0 to 19 loop
if (pwm_cnt8 < pattern2(i) )
then
led2(i) <= '1';
else
led2(i) <= '0';
end if;
end loop;
end if;
end process dp_fxclk;
end RTL;
|
gpl-3.0
|
ibm2030/IBM2030
|
FMD2030_5-02A-B.vhd
|
1
|
9958
|
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-02A-B.vhd
-- Creation Date:
-- Description:
-- X6,X7 assembly, ASCII latch, X6,X7 backup (5-02A), WX reg gating (5-02B)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.1 2012-04-07
-- Enable MPX interruptions
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY X6X7 IS
port
(
SALS : IN SALS_Bus; -- 01C
DECIMAL : IN STD_LOGIC; -- 06B
CONNECT : IN STD_LOGIC; -- 06B
N_CTRL_LM : IN STD_LOGIC; -- 06B
CTRL_N : IN STD_LOGIC; -- 06B
R_REG_0_BIT : IN STD_LOGIC; -- 06C
V67_00_OR_GM_WM : IN STD_LOGIC; -- 05A
STATUS_IN_LCHD : IN STD_LOGIC; -- 06A
OPNL_IN_LCHD : IN STD_LOGIC; -- 06A
CARRY_0_LCHD : IN STD_LOGIC; -- 06A
S_REG_1_OR_R_REG_2 : IN STD_LOGIC; -- 05A
S : IN STD_LOGIC_VECTOR(0 to 7); -- 07B
G : IN STD_LOGIC_VECTOR(0 to 7); -- 05C
TIMER_UPDATE : IN STD_LOGIC; -- 04C
EXTERNAL_INT : IN STD_LOGIC; -- 04C
MPX_INTERRUPT : IN STD_LOGIC; -- 08C
SX1_INTERRUPT : IN STD_LOGIC; -- 12D
SX2_INTERRUPT : IN STD_LOGIC; -- 14D
-- HSMPX : IN STD_LOGIC; -- XXXXX
I_WRAPPED_CPU : IN STD_LOGIC; -- 03B
TIMER_UPDATE_OR_EXT_INT : IN STD_LOGIC; -- 04C
U_WRAPPED_MPX : IN STD_LOGIC; -- 03B
H_REG_6_BIT : IN STD_LOGIC; -- 04C
ADDR_IN_LCHD : IN STD_LOGIC; -- 06A
SERV_IN_LCHD : IN STD_LOGIC; -- 06A
R_REG_VAL_DEC_DIG : IN STD_LOGIC; -- 05A
N1BC_OR_R1 : IN STD_LOGIC; -- 05A
Z_BUS_0 : IN STD_LOGIC; -- 06B
G_REG_1_OR_R_REG_3 : IN STD_LOGIC; -- 05A
GT_BU_ROSAR_TO_WX_REG : IN STD_LOGIC; -- 01B
H_REG_5_PWR : IN STD_LOGIC; -- 04C
MPX_SHARE_PULSE : IN STD_LOGIC; -- 03A
SX_CHAIN_PULSE : IN STD_LOGIC; -- 03A
MACH_RST_SW : IN STD_LOGIC; -- 03D
R_REG_4_BIT : IN STD_LOGIC; -- 06C
ANY_PRIORITY_PULSE : IN STD_LOGIC; -- 03A
-- Outputs
XOR_OR_OR : OUT STD_LOGIC; -- 03A,04A
INTERRUPT : OUT STD_LOGIC; -- 01B
GT_GWX_TO_WX_REG : OUT STD_LOGIC; -- 01B
GT_FWX_TO_WX_REG : OUT STD_LOGIC; -- 01B
USE_CA_BASIC_DECODER : OUT STD_LOGIC; -- 02B,01A,03C,04C,05C,07A,07C,10C
MPX_ROS_LCH : OUT STD_LOGIC; -- 08C
X6 : OUT STD_LOGIC;
X7 : OUT STD_LOGIC;
USE_ALT_CA_DECODER : OUT STD_LOGIC; -- 07C,04C,10C,07A,11C
GT_CA_TO_W_REG : OUT STD_LOGIC; -- 01B,07A
GT_UV_TO_WX_REG : OUT STD_LOGIC; -- 01B
DIAG_LATCH_RST : OUT STD_LOGIC; -- NEW
-- Debug
DEBUG : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END X6X7;
ARCHITECTURE FMD OF X6X7 IS
signal TEST_ASCII : STD_LOGIC;
signal TEST_INTRP : STD_LOGIC;
signal TEST_WRAP : STD_LOGIC;
signal GT_ASCII_LCH : STD_LOGIC;
signal GT_MPX_LCH : STD_LOGIC; -- Output of AA3E3
signal GT_SX_LCH : STD_LOGIC; -- Output of AA3L6
signal X6_MUX,X7_MUX : STD_LOGIC;
signal CA_TO_X7_DECO : STD_LOGIC;
signal X6_BRANCH,X7_BRANCH : STD_LOGIC;
signal SX_CH_ROAR_RESTORE : STD_LOGIC;
signal MPX_CH_ROAR_RESTORE : STD_LOGIC;
signal RESTORE_0 : STD_LOGIC; -- Output of AA3K5,FL0
signal ASCII_LCH : STD_LOGIC;
signal MPX_CH_X6,MPX_CH_X7 : STD_LOGIC;
signal SX_CH_X6,SX_CH_X7 : STD_LOGIC;
signal X6_DATA,X7_DATA : STD_LOGIC;
signal STORED_X6,STORED_X7 : STD_LOGIC;
signal sXOR_OR_OR : STD_LOGIC;
signal sINTERRUPT : STD_LOGIC;
signal sGT_GWX_TO_WX_REG : STD_LOGIC;
signal sGT_FWX_TO_WX_REG : STD_LOGIC;
signal sUSE_CA_BASIC_DECODER : STD_LOGIC;
signal sMPX_ROS_LCH : STD_LOGIC;
signal REST0_LCH_Set,REST0_LCH_Reset,SXREST_LCH_Set,SXREST_LCH_Reset,
MPXROS_LCH_Reset,MPXROS_LCH_Set,MPXREST_LCH_Set,MPXREST_LCH_Reset : STD_LOGIC;
BEGIN
-- Fig 5-02A
TEST_ASCII <= '1' when SALS.SALS_CK="1001" and SALS.SALS_AK='1' else '0'; -- AB3E7
TEST_INTRP <= '1' when SALS.SALS_CK="1010" and SALS.SALS_AK='1' else '0'; -- AB3E7
TEST_WRAP <= '1' when SALS.SALS_CK="0011" and SALS.SALS_AK='1' else '0'; -- AB3E6
DIAG_LATCH_RST <= '1' when SALS.SALS_CK="0000" and SALS.SALS_AK='1' and T1='1' else '0'; -- NEW!
sXOR_OR_OR <= DECIMAL and CONNECT and N_CTRL_LM; -- AB3D2
XOR_OR_OR <= sXOR_OR_OR;
GT_ASCII_LCH <= sXOR_OR_OR and CTRL_N and T2; -- AB3D2
DEBUG <= ASCII_LCH;
-- ?? Debug remove other interrupt sources
-- sINTERRUPT <= TIMER_UPDATE or EXTERNAL_INT or MPX_INTERRUPT or SX1_INTERRUPT or SX2_INTERRUPT; -- AA3K4
sINTERRUPT <= EXTERNAL_INT or MPX_INTERRUPT;
INTERRUPT <= sINTERRUPT;
with (SALS.SALS_CH) select X6_MUX <= -- AA3G5
'1' when "0001",
R_REG_0_BIT when "0010",
V67_00_OR_GM_WM when "0011",
STATUS_IN_LCHD when "0100",
OPNL_IN_LCHD when "0101",
CARRY_0_LCHD when "0110",
S(0) when "0111",
S_REG_1_OR_R_REG_2 when "1000",
S(2) when "1001",
S(4) when "1010",
S(6) when "1011",
G(0) when "1100",
G(2) when "1101",
G(4) when "1110",
G(6) when "1111",
'0' when others; -- 0000
with (SALS.SALS_CL) select X7_MUX <= -- AA3H5
'1' when "0001",
'1' when "0010", -- CL=0010 is CA>W ?? Needed otherwise CA>W always forces X7 to 0 ??
ADDR_IN_LCHD when "0011",
SERV_IN_LCHD when "0100",
R_REG_VAL_DEC_DIG when "0101",
N1BC_OR_R1 when "0110",
Z_BUS_0 when "0111",
G(7) when "1000",
S(3) when "1001",
S(5) when "1010",
S(7) when "1011",
G_REG_1_OR_R_REG_3 when "1100",
G(3) when "1101",
G(5) when "1110",
sINTERRUPT when "1111",
'0' when others; -- 0000
X6_BRANCH <= (not ASCII_LCH or not TEST_ASCII) and -- AA3K3
(not TIMER_UPDATE_OR_EXT_INT or not TEST_INTRP) and -- AA3K3
(not SX2_INTERRUPT or SX1_INTERRUPT or not TEST_INTRP) and -- AA3K4
(not I_WRAPPED_CPU or not TEST_WRAP) and -- AA3K3
X6_MUX;
X7_BRANCH <= (not TIMER_UPDATE_OR_EXT_INT or not TEST_INTRP) and -- AA3K3
(not SX1_INTERRUPT or not TEST_INTRP) and -- AA3B7
(not TEST_WRAP or not U_WRAPPED_MPX or not H_REG_6_BIT) and -- AA3J5
X7_MUX ;
-- and CA_TO_X7_DECO; ?? Removed as it forced X7 to 0 on CA>W ??
sGT_GWX_TO_WX_REG <= GT_BU_ROSAR_TO_WX_REG and H_REG_5_PWR; -- AA3L5
GT_GWX_TO_WX_REG <= sGT_GWX_TO_WX_REG;
sGT_FWX_TO_WX_REG <= GT_BU_ROSAR_TO_WX_REG and not H_REG_5_PWR; -- AA3C2
GT_FWX_TO_WX_REG <= sGT_FWX_TO_WX_REG;
sUSE_CA_BASIC_DECODER <= not SALS.SALS_AA;
USE_CA_BASIC_DECODER <= sUSE_CA_BASIC_DECODER;
REST0_LCH_Set <= T2 and sGT_GWX_TO_WX_REG;
REST0_LCH_Reset <= MACH_RST_SW or T1;
REST0_LCH: entity work.FLL port map(REST0_LCH_Set,REST0_LCH_Reset,RESTORE_0); -- AA3K5 Bit 0
SXREST_LCH_Set <= T4 and RESTORE_0;
SXREST_LCH_Reset <= MACH_RST_SW or T3;
SXREST_LCH: entity work.FLL port map(SXREST_LCH_Set,SXREST_LCH_Reset,SX_CH_ROAR_RESTORE); -- AA3K5 Bit 1
MPXROS_LCH_Set <= T2 and sGT_FWX_TO_WX_REG;
MPXROS_LCH_Reset <= MACH_RST_SW or T1;
MPXROS_LCH: entity work.FLL port map(MPXROS_LCH_Set,MPXROS_LCH_Reset,sMPX_ROS_LCH); -- AA3L2 Bit 2
MPX_ROS_LCH <= sMPX_ROS_LCH;
MPXREST_LCH_Set <= T4 and sMPX_ROS_LCH;
MPXREST_LCH_Reset <= MACH_RST_SW or T3;
MPXREST_LCH: entity work.FLL port map(MPXREST_LCH_Set,MPXREST_LCH_Reset,MPX_CH_ROAR_RESTORE); -- AA3L2 Bit 3
X6_DATA <= X6_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6
X7_DATA <= X7_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6
GT_MPX_LCH <= (MPX_SHARE_PULSE and T1) or MACH_RST_SW; -- AA3L4,AA3E3
GT_SX_LCH <= (SX_CHAIN_PULSE and T1) or MACH_RST_SW; -- AA3F3,AA3L6
-- ASCII latch plus X6,X7 storage for
ASC_LCH: entity work.PH port map(R_REG_4_BIT,GT_ASCII_LCH,ASCII_LCH); -- AA3L3
M7_LCH: entity work.PH port map(X7_DATA,GT_MPX_LCH,MPX_CH_X7); -- AA3L3
S7_LCH: entity work.PH port map(X7_DATA,GT_SX_LCH,SX_CH_X7); -- AA3L3
M6_LCH: entity work.PH port map(X6_DATA,GT_MPX_LCH,MPX_CH_X6); -- AA3L3
S6_LCH: entity work.PH port map(X6_DATA,GT_SX_LCH,SX_CH_X6); -- AA3L3
STORED_X6 <= (SX_CH_ROAR_RESTORE and SX_CH_X6) or (MPX_CH_ROAR_RESTORE and MPX_CH_X6); -- AA3K6
STORED_X7 <= (SX_CH_ROAR_RESTORE and SX_CH_X7) or (MPX_CH_ROAR_RESTORE and MPX_CH_X7); -- AA3K6
X6 <= X6_DATA or STORED_X6; -- Wire-AND of negated signals
X7 <= X7_DATA or STORED_X7; -- Wire-AND of negated signals
-- Page 5-02B
USE_ALT_CA_DECODER <= not sUSE_CA_BASIC_DECODER and not ANY_PRIORITY_PULSE; -- AB2F7 ??
CA_TO_X7_DECO <= '0' when SALS.SALS_CL="0010" else '1'; -- AA3H5
GT_CA_TO_W_REG <= not CA_TO_X7_DECO and not ANY_PRIORITY_PULSE; -- AA3L4,AA3G4
GT_UV_TO_WX_REG <= '1' when SALS.SALS_CK="0001" and SALS.SALS_AK='1' and ANY_PRIORITY_PULSE='0' else '0'; -- AB3E6,AB3B3
END FMD;
|
gpl-3.0
|
freecores/usb_fpga_1_15
|
examples/usb-fpga-1.15/1.15d/lightshow/fpga/lightshow.vhd
|
36
|
2235
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led : out std_logic_vector(11 downto 0);
CLK : in std_logic -- 32 MHz
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern is array(11 downto 0) of integer range 0 to 15;
signal pattern1 : tPattern := (0, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1);
signal pattern2 : tPattern := (6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5);
signal pattern3 : tPattern := (0, 1, 4, 9, 4, 1, 0, 0, 0, 0, 0, 0);
type tXlatTable1 is array(0 to 12) of integer range 0 to 1023;
constant xt1 : tXlatTable1 := (0, 0, 1, 4, 13, 31, 64, 118, 202, 324, 493, 722, 1023);
type tXlatTable2 is array(0 to 9) of integer range 0 to 255;
--constant xt2 : tXlatTable2 := (0, 1, 11, 38, 90, 175, 303, 481, 718, 1023);
constant xt2 : tXlatTable2 := (0, 0, 3, 9, 22, 44, 76, 120, 179, 255);
signal cp1 : std_logic_vector(22 downto 0);
signal cp2 : std_logic_vector(22 downto 0);
signal cp3 : std_logic_vector(22 downto 0);
signal d : std_logic_vector(16 downto 0);
begin
dpCLK: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( cp1 = conv_std_logic_vector(3000000,23) )
then
pattern1(10 downto 0) <= pattern1(11 downto 1);
pattern1(11) <= pattern1(0);
cp1 <= (others => '0');
else
cp1 <= cp1 + 1;
end if;
if ( cp2 = conv_std_logic_vector(2200000,23) )
then
pattern2(10 downto 0) <= pattern2(11 downto 1);
pattern2(11) <= pattern2(0);
cp2 <= (others => '0');
else
cp2 <= cp2 + 1;
end if;
if ( cp3 = conv_std_logic_vector(1500000,23) )
then
pattern3(11 downto 1) <= pattern3(10 downto 0);
pattern3(0) <= pattern3(11);
cp3 <= (others => '0');
else
cp3 <= cp3 + 1;
end if;
if ( d = conv_std_logic_vector(1278*64-1,17) )
then
d <= (others => '0');
else
d <= d + 1;
end if;
for i in 0 to 11 loop
if ( d(16 downto 6) < conv_std_logic_vector( xt1(pattern1(i) + pattern2(i)) + xt2(pattern3(i)) ,11) )
then
led(i) <= '1';
else
led(i) <= '0';
end if;
end loop;
end if;
end process dpCLK;
end RTL;
|
gpl-3.0
|
freecores/usb_fpga_1_15
|
examples/usb-fpga-2.13/2.13c/ucecho/fpga/ucecho.vhd
|
7
|
636
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= pb_buf;
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
end if;
end process dpUCECHO;
end RTL;
|
gpl-3.0
|
ibm2030/IBM2030
|
FMD2030_5-07B2.vhd
|
1
|
6009
|
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07B2.vhd
-- Creation Date: 01/11/09
-- Description:
-- S Register
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Change GT_CS_OPT to level-triggered latch
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
-- use work.all;
ENTITY SReg IS
port
(
SA : IN STD_LOGIC; -- 01C
CS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
CD : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
N_Z_BUS : IN STD_LOGIC_VECTOR(0 to 7);
Z_BUS0, CARRY_0, Z_BUS_HI_0, Z_BUS_LO_0 : IN STD_LOGIC; -- 06B
GT_CARRY_TO_S3 : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(0 to 7);
GT_Z_BUS_TO_S : OUT STD_LOGIC;
S_REG_RST : OUT STD_LOGIC;
CTRL_REG_RST : IN STD_LOGIC; -- 01C
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
STORE_S_REG_RST : IN STD_LOGIC; -- 03D
E_SW_SEL_S : IN STD_LOGIC; -- 04C
MACH_RST_2C : IN STD_LOGIC; -- 06B
T_REQUEST : IN STD_LOGIC; -- 10BC6
FB_K_T2_PULSE : OUT STD_LOGIC;
CS_DECODE_X001 : OUT STD_LOGIC; -- 03C
BASIC_CS_0 : OUT STD_LOGIC; -- 03C
P1, T1, T2, T3, T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END SReg;
ARCHITECTURE FMD OF SReg IS
signal SETS, RESETS : STD_LOGIC_VECTOR(0 to 7);
signal CS_X000,CS_X001,CS_X010,CS_X011,CS_X100,CS_X101,CS_X110,CS_X111,CS_X01X,CS_X0X1,CS_0XXX,CS_1XXX : STD_LOGIC;
signal CD_0110 : STD_LOGIC;
signal GT_CS_OPT_DECODER, GT_CS_BASIC_DECODER : STD_LOGIC;
signal BASIC_NOT_CS_0, sBASIC_CS_0 : STD_LOGIC;
signal sGT_Z_BUS_TO_S : STD_LOGIC;
signal sS_REG_RST : STD_LOGIC;
signal GT_CS_OPT_Set,GT_CS_OPT_Reset : STD_LOGIC;
signal S_REG_Set,S_REG_Reset : STD_LOGIC_VECTOR(0 to 7);
BEGIN
-- Fig 5-07B
CS_X000 <= '1' when CS(1 to 3)="000" else '0';
CS_X001 <= '1' when CS(1 to 3)="001" else '0';
CS_DECODE_X001 <= CS_X001;
CS_X010 <= '1' when CS(1 to 3)="010" else '0';
CS_X011 <= '1' when CS(1 to 3)="011" else '0';
CS_X100 <= '1' when CS(1 to 3)="100" else '0';
CS_X101 <= '1' when CS(1 to 3)="101" else '0';
CS_X110 <= '1' when CS(1 to 3)="110" else '0';
CS_X111 <= '1' when CS(1 to 3)="111" else '0';
CS_X01X <= '1' when CS(1 to 2)="01" else '0';
CS_X0X1 <= '1' when CS(1)='0' and CS(3)='1' else '0';
CS_0XXX <= '1' when CS(0)='0' else '0';
CS_1XXX <= '1' when CS(0)='1' else '0';
GT_CS_OPT_Set <= SA and P1;
GT_CS_OPT_Reset <= CTRL_REG_RST or T1;
-- GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5
GT_CS_OPT: entity work.FLL port map(S=>GT_CS_OPT_Set, R=>GT_CS_OPT_Reset, Q=>GT_CS_OPT_DECODER); -- AB3E5
GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5
BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5 Could be" GT_CS_BASIC_DECODER and not CS(0)"
sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5 Could be "GT_CS_BASIC_DECODER and CS(0)"
BASIC_CS_0 <= sBASIC_CS_0;
FB_K_T2_PULSE <= sBASIC_CS_0 and T2 and CS_X110; -- AA3F7, AA3E3
CD_0110 <= '1' when CD="0110" else '0'; -- AA3B7, AA3J6
sGT_Z_BUS_TO_S <= (CD_0110 and T4) or (MAN_STOR_PWR and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
GT_Z_BUS_TO_S <= sGT_Z_BUS_TO_S;
sS_REG_RST <= (CD_0110 and T3) or (STORE_S_REG_RST and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
S_REG_RST <= sS_REG_RST;
SETS(0) <= CS_X111 and BASIC_NOT_CS_0; -- AA3G7
SETS(1) <= T_REQUEST and CS_X101 and BASIC_NOT_CS_0; -- AA3G7
SETS(2) <= CS_X001 and not Z_BUS0 and sBASIC_CS_0; -- AA3H7
SETS(3) <= GT_CARRY_TO_S3 and CARRY_0; -- AA3H7
SETS(4) <= BASIC_NOT_CS_0 and CS_X01X and Z_BUS_HI_0; -- AA3J7
SETS(5) <= BASIC_NOT_CS_0 and CS_X0X1 and Z_BUS_LO_0; -- AA3J7
SETS(6) <= CS_X011 and sBASIC_CS_0; -- AA3K7
SETS(7) <= CS_X101 and sBASIC_CS_0; -- AA3K7
RESETS(0) <= CS_X110 and BASIC_NOT_CS_0; -- AA3G7
RESETS(1) <= CS_X101 and not T_REQUEST and BASIC_NOT_CS_0; -- AA3G7
RESETS(2) <= CS_X000 and sBASIC_CS_0; -- AA3H7
RESETS(3) <= not CARRY_0 and GT_CARRY_TO_S3; -- AA3H7
RESETS(4) <= (BASIC_NOT_CS_0 and not Z_BUS_HI_0 and CS_X01X) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(5) <= (BASIC_NOT_CS_0 and not Z_BUS_LO_0 and CS_X0X1) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(6) <= sBASIC_CS_0 and CS_X010; -- AA3K7
RESETS(7) <= sBASIC_CS_0 and CS_X100; -- AA3K7
S_REG_Set <= mux(sGT_Z_BUS_TO_S,not N_Z_BUS) or mux(T4,SETS); -- ?? "T4 and not T1" to prevent erroneous S4 value
S_REG_Reset <= (S'range=>sS_REG_RST) or mux(T4,RESETS); -- ?? "T4 and not T1" to prevent erroneous S4 value
S_REG: FLVL port map(S_REG_Set, S_REG_Reset, S); -- AA3G7, AA3H7, AA3J7, AA3K7
END FMD;
|
gpl-3.0
|
ibm2030/IBM2030
|
FMD2030_5-10C.vhd
|
1
|
17493
|
---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10C.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console data latches and gating
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.FLL;
ENTITY n1050_DATA IS
port
(
-- Inputs
E_SW_SEL_BUS : IN E_SW_BUS_Type; -- 04CE1
USE_MANUAL_DECODER : IN STD_LOGIC; -- 03DA3
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02BA3
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02AE6
GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05CA2
XLATE_UC : IN STD_LOGIC; -- 09C
WR_LCH : IN STD_LOGIC; -- 09CD2 aka WRITE_LCH
RUN : IN STD_LOGIC; -- 09CE6
PROCEED_LCH : IN STD_LOGIC; -- 10BC3
-- TT4_POS_HOME_STT : IN STD_LOGIC; -- 10DD5
RD_OR_RD_INQ : IN STD_LOGIC; -- 09CC5
W_TIME, X_TIME, Y_TIME, Z_TIME : IN STD_LOGIC; -- 10AXX
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 08BE3
CLOCK_1 : IN STD_LOGIC; -- 10AA5
PCH_1_CLUTCH : IN STD_LOGIC; -- 10DD5
GT_1050_BUS_OUT, GT_1050_TAGS_OUT : IN STD_LOGIC; -- 04CE6
n1050_OP_IN : IN STD_LOGIC; -- 10BC5
SET_SHIFT_LCH : IN STD_LOGIC; -- 09CD6
TA_REG_SET : IN STD_LOGIC; -- 10BB2
RST_ATTACH : IN STD_LOGIC; -- 10BC2
n1050_OPER : IN STD_LOGIC; -- 10DE4
READ_INQ : IN STD_LOGIC; -- 09CE6
RD_SHARE_REQ_LCH : IN STD_LOGIC; -- 09CC6
READ : IN STD_LOGIC; -- 09CE6
WRITE_MODE : IN STD_LOGIC; -- 09CFD2
RESTORE : IN STD_LOGIC; -- 10BD2
OUTPUT_SEL_AND_READY : IN STD_LOGIC; -- 10DD4
SHARE_REQ_RST : IN STD_LOGIC; -- 10BB6
n1050_RST_LCH : IN STD_LOGIC; -- 10BA3
RDR_1_CLUTCH : IN STD_LOGIC; -- 10DD5
UC_CHARACTER, LC_CHARACTER : IN STD_LOGIC; -- 09CD2
-- Z_BUS_0, Z_BUS_3 : IN STD_LOGIC; -- 06BDX
-- TT3_POS_1050_OPER : IN STD_LOGIC; -- 10DD4
TA_REG_POS_6_ATTN_RST : IN STD_LOGIC; -- 10BE3
PCH_BITS : IN STD_LOGIC_VECTOR(0 to 6);
-- CE controls
CE_GT_TA_OR_TE : IN STD_LOGIC;
CE_DATA_ENTER_GT : IN STD_LOGIC;
CE_TE_DECODE : IN STD_LOGIC;
CE_RUN_MODE : IN STD_LOGIC; -- 10DB3
n1050_CE_MODE : IN STD_LOGIC;
CE_BITS : IN STD_LOGIC_VECTOR(0 to 7); -- 10DA1
-- Outputs
A_REG_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 07CA6
DATA_REG_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 09C
TAGS_OUT : OUT STD_LOGIC_VECTOR(0 to 7); -- 10BB1 11AA2
NPL_BITS : OUT STD_LOGIC_VECTOR(0 to 7);
PTT_BITS : OUT STD_LOGIC_VECTOR(0 to 6); -- Output to printer ("RDR")
TE_LCH : OUT STD_LOGIC;
WR_SHARE_REQ : OUT STD_LOGIC; -- 10BD5
ALLOW_STROBE : OUT STD_LOGIC; -- 09CD4 09CE1
GT_WRITE_REG : OUT STD_LOGIC; -- 10DB4
FORCE_SHIFT_CHAR : OUT STD_LOGIC; -- 10DB4
FORCE_LC_SHIFT : OUT STD_LOGIC; -- 10DB4
SET_LOWER_CASE : OUT STD_LOGIC; -- 09CD4 09CB5
n1050_INTRV_REQ : OUT STD_LOGIC; -- 10BD4 04AA4
READY_SHARE : OUT STD_LOGIC; -- 10BD4 09CB4
TT5_POS_INTRV_REQ : OUT STD_LOGIC; -- 10DC4
-- Buses
TT_BUS: INOUT STD_LOGIC_VECTOR(0 to 7);
GTD_TT3: OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC
);
END n1050_DATA;
ARCHITECTURE FMD OF n1050_DATA IS
type ConversionAtoE is array(0 to 255) of STD_LOGIC_VECTOR(0 to 7);
signal ASCII_TO_EBCDIC : ConversionAtoE :=
(
character'Pos(cr) => "00010101",
character'Pos(lf) => "00100101",
character'Pos(' ') => "01000000",
character'Pos('.') => "01001011",
character'Pos('<') => "01001100",
character'Pos('(') => "01001101",
character'Pos('+') => "01001110",
character'Pos('&') => "01010000",
character'Pos('$') => "01011011",
character'Pos(')') => "01011101",
character'Pos(';') => "01011110",
character'Pos('-') => "01100000",
character'Pos('/') => "01100001",
character'Pos(',') => "01101011",
character'Pos('%') => "01101100",
character'Pos('>') => "01101110",
character'Pos('?') => "01101111",
character'Pos(':') => "01111010",
character'Pos('#') => "01111011",
character'Pos('@') => "01111100",
character'Pos('0') => "11110000", character'Pos('1') => "11110001", character'Pos('2') => "11110010",
character'Pos('3') => "11110011", character'Pos('4') => "11110100",
character'Pos('5') => "11110101", character'Pos('6') => "11110110", character'Pos('7') => "11110111",
character'Pos('8') => "11111000", character'Pos('9') => "11111001",
character'Pos('A') => "11000001", character'Pos('B') => "11000010", character'Pos('C') => "11000011",
character'Pos('D') => "11000100", character'Pos('E') => "11000101", character'Pos('F') => "11000110",
character'Pos('G') => "11000111", character'Pos('H') => "11001000", character'Pos('I') => "11001001",
character'Pos('J') => "11010001", character'Pos('K') => "11010010", character'Pos('L') => "11010011",
character'Pos('M') => "11010100", character'Pos('N') => "11010101", character'Pos('O') => "11010110",
character'Pos('P') => "11010111", character'Pos('Q') => "11011000", character'Pos('R') => "11011001",
character'Pos('S') => "11100010", character'Pos('T') => "11100011", character'Pos('U') => "11100100",
character'Pos('V') => "11100101", character'Pos('W') => "11100110", character'Pos('X') => "11100111",
character'Pos('Y') => "11101000", character'Pos('Z') => "11101001",
character'Pos('a') => "10000001", character'Pos('b') => "10000010", character'Pos('c') => "10000011",
character'Pos('d') => "10000100", character'Pos('e') => "10000101", character'Pos('f') => "10000110",
character'Pos('g') => "10000111", character'Pos('h') => "10001000", character'Pos('i') => "10001001",
character'Pos('j') => "10010001", character'Pos('k') => "10010010", character'Pos('l') => "10010011",
character'Pos('m') => "10010100", character'Pos('n') => "10010101", character'Pos('o') => "10010110",
character'Pos('p') => "10010111", character'Pos('q') => "10011000", character'Pos('r') => "10011001",
character'Pos('s') => "10100010", character'Pos('t') => "10100011", character'Pos('u') => "10100100",
character'Pos('v') => "10100101", character'Pos('w') => "10100110", character'Pos('x') => "10100111",
character'Pos('y') => "10101000", character'Pos('z') => "10101001",
others => "01101111");
type ConversionEtoA is array(0 to 255) of character;
signal EBCDIC_TO_ASCII : ConversionEtoA :=
(
2#00010101# => cr,
2#00100101# => lf,
2#01000000# => ' ',
2#01001011# => '.',
2#01001100# => '<',
2#01001101# => '(',
2#01001110# => '+',
2#01001111# => '|',
2#01010000# => '&',
2#01011010# => '!',
2#01011011# => '$',
2#01011100# => '*',
2#01011101# => ')',
2#01011110# => ';',
2#01011111# => '~',
2#01100000# => '-',
2#01100001# => '/',
2#01101011# => ',',
2#01101100# => '%',
2#01101101# => '_',
2#01101110# => '>',
2#01101111# => '?',
2#01111010# => ':',
2#01111011# => '#',
2#01111100# => '@',
2#01111101# => ''',
2#01111110# => '=',
2#01111111# => '"',
2#11110000# => '0', 2#11110001# => '1', 2#11110010# => '2', 2#11110011# => '3', 2#11110100# => '4',
2#11110101# => '5', 2#11110110# => '6', 2#11110111# => '7', 2#11111000# => '8', 2#11111001# => '9',
2#11000001# => 'A', 2#11000010# => 'B', 2#11000011# => 'C', 2#11000100# => 'D', 2#11000101# => 'E',
2#11000110# => 'F', 2#11000111# => 'G', 2#11001000# => 'H', 2#11001001# => 'I',
2#11010001# => 'J', 2#11010010# => 'K', 2#11010011# => 'L', 2#11010100# => 'M', 2#11010101# => 'N',
2#11010110# => 'O', 2#11010111# => 'P', 2#11011000# => 'Q', 2#11011001# => 'R',
2#11100010# => 'S', 2#11100011# => 'T', 2#11100100# => 'U', 2#11100101# => 'V', 2#11100110# => 'W',
2#11100111# => 'X', 2#11101000# => 'Y', 2#11101001# => 'Z',
2#10000001# => 'a', 2#10000010# => 'b', 2#10000011# => 'c', 2#10000100# => 'd', 2#10000101# => 'e',
2#10000110# => 'f', 2#10000111# => 'g', 2#10001000# => 'h', 2#10001001# => 'i',
2#10010001# => 'j', 2#10010010# => 'k', 2#10010011# => 'l', 2#10010100# => 'm', 2#10010101# => 'n',
2#10010110# => 'o', 2#10010111# => 'p', 2#10011000# => 'q', 2#10011001# => 'r',
2#10100010# => 's', 2#10100011# => 't', 2#10100100# => 'u', 2#10100101# => 'v', 2#10100110# => 'w',
2#10100111# => 'x', 2#10101000# => 'y', 2#10101001# => 'z',
others => '?');
signal sGT_1050_BUS_OUT, sGT_1050_TAGS_OUT : STD_LOGIC;
signal sSET_LOWER_CASE : STD_LOGIC;
signal sTE_LCH : STD_LOGIC;
signal sSET_LOW_CASE : STD_LOGIC;
signal sDATA_REG : STD_LOGIC_VECTOR(0 to 7);
signal sNPL_BITS : STD_LOGIC_VECTOR(0 to 7);
signal GT_1050_BUS_TO_A, GT_1050_TAGS_TO_A : STD_LOGIC;
signal sTAGS_OUT : STD_LOGIC_VECTOR(0 to 7);
signal DATA_REG_LATCH : STD_LOGIC;
signal DATA_REG_IN : STD_LOGIC_VECTOR(0 to 7);
signal TI_P_BIT : STD_LOGIC;
signal sPTT_BITS : STD_LOGIC_VECTOR(0 to 6);
signal sGTD_TT3 : STD_LOGIC;
signal CE_TE_LCH_SET : STD_LOGIC;
signal TE_LCH_SET, TE_LCH_RESET : STD_LOGIC;
signal sGT_WRITE_REG : STD_LOGIC;
signal WR_SHARE_REQ_SET, WR_SHARE_REQ_RESET,sWR_SHARE_REQ : STD_LOGIC;
signal ALLOW_STROBE_SET, ALLOW_STROBE_RESET, sALLOW_STROBE : STD_LOGIC;
signal SHIFT_SET, SHIFT_RESET : STD_LOGIC;
signal sSHIFT : STD_LOGIC := '0';
signal INTRV_REQ_SET, INTRV_REQ_RESET, sINTRV_REQ : STD_LOGIC;
signal n1050_INTRV_REQ_RESET : STD_LOGIC;
signal NOT_OPER_RESET : STD_LOGIC;
signal NOT_OPER : STD_LOGIC := '0';
signal RDY_SHARE_SET, RDY_SHARE_RESET, sRDY_SHARE : STD_LOGIC;
signal CancelCode : STD_LOGIC;
signal NOT_n1050_OPER : STD_LOGIC;
BEGIN
-- Fig 5-10C
GT_1050_BUS_TO_A <= (E_SW_SEL_BUS.TI_SEL and USE_MANUAL_DECODER) or
(USE_ALT_CA_DECODER and not GTD_CA_BITS(0) and GTD_CA_BITS(1) and GTD_CA_BITS(2) and GTD_CA_BITS(3)); -- AB3C7 AA=1 CA=0111
GT_1050_TAGS_TO_A <= (E_SW_SEL_BUS.TT_SEL and USE_MANUAL_DECODER) or
(USE_BASIC_CA_DECO and not GTD_CA_BITS(0) and not GTD_CA_BITS(1) and not GTD_CA_BITS(2) and GTD_CA_BITS(3)); -- AA2C6 AA=0 CA=0001
A_REG_BUS <= not(((sNPL_BITS & TI_P_BIT) and (0 to 8=>GT_1050_BUS_TO_A)) or ((TT_BUS & '0') and (0 to 8=>GT_1050_TAGS_TO_A))); -- AC2E2 - Note: Inverted
DATA_REG_PH: PHV8 port map(D=>DATA_REG_IN,L=>DATA_REG_LATCH,Q=>sDATA_REG); -- AC3B2
DATA_REG_BUS <= sDATA_REG;
DATA_REG_LATCH <= (CE_DATA_ENTER_GT and CE_TE_DECODE) or (RD_OR_RD_INQ and W_TIME) or (T3 and sGT_1050_BUS_OUT) or not RUN; -- AC3P5
TAGS_OUT <= DATA_REG_IN; -- ?
sGT_1050_BUS_OUT <= GT_1050_BUS_OUT; -- AC2D6
sGT_1050_TAGS_OUT <= GT_1050_TAGS_OUT; -- AC2M4
DATA_REG_IN <= (Z_BUS(0 to 7) and (0 to 7=>(sGT_1050_BUS_OUT or sGT_1050_TAGS_OUT)))
or (CE_BITS and (0 to 7=>CE_GT_TA_OR_TE))
or (('0' & PCH_BITS) and (0 to 7=>(CLOCK_1 and PCH_1_CLUTCH))); -- AC2B4 AC2H6 AC2M6 AC2M2
sGTD_TT3 <= TT_BUS(3) and n1050_CE_MODE; -- AC2H5 AC2L4
GTD_TT3 <= sGTD_TT3;
TT_BUS(7) <= EVENPARITY(sDATA_REG(1 to 7)) and WR_LCH and RUN and not TT_BUS(0); -- AC2E4 AC2J2
-- CancelCode <= '1' when sDATA_REG(1 to 7)="1100000" else '0'; -- DATA_REG=X1100000
CancelCode <= '1' when sDATA_REG(1 to 7)="0010101" else '0'; -- DATA_REG (ASCII) = 15 = ^U
TT_BUS(0) <= CancelCode and PROCEED_LCH and TT_BUS(4); -- AL2F5 AC2D6
-- The following converts the card code CBA8421 on the DATA_REG bus to EBCDIC
-- C P P P P
-- B 0 0 1 1
-- A 0 1 0 1
-- =====================
-- 0 =40 @=7C -=60 &=50
-- 1 1=F1 /=61 j=91 a=81
-- 2 2=F2 s=A2 k=92 b=82
-- 3 3=F3 t=A3 l=93 c=83
-- 4 4=F4 u=A4 m=94 d=84
-- 5 5=F5 v=A5 n=95 e=85
-- 6 6=F6 w=A6 o=96 f=86
-- 7 7=F7 x=A7 p=97 g=87
-- 8 8=F8 y=A8 q=98 h=88
-- 9 9=F9 z=A9 r=99 i=89
-- A 0=FA CAN
-- B #=7B ,=6B $=5B .=4B
-- C
-- D CR
-- E UC EOB LC
-- F
-- For the purposes of this project, this will convert ASCII on CBA8421 into EBCDIC in MPL
-- sNPL_BITS(0) <= 0; -- AC3J2
-- sNPL_BITS(1) <= 0; -- AC3J2
-- sNPL_BITS(2) <= 0; -- AC3K2
-- sNPL_BITS(3) <= 0; -- AC3H2
-- sNPL_BITS(4) <= 0; -- AC3H2
-- sNPL_BITS(5) <= 0; -- AC3K2
-- sNPL_BITS(6) <= 0; -- AC3J2
-- sNPL_BITS(7) <= 0; -- AC3J2
sNPL_BITS <= ASCII_TO_EBCDIC(Conv_Integer(sDATA_REG));
-- sNPL_BITS <= STD_LOGIC_VECTOR(to_unsigned(Conv_Integer(sDATA_REG),8)); -- * * Temporary debug - no translation
NPL_BITS <= sNPL_BITS;
TI_P_BIT <= EVENPARITY(sNPL_BITS(0 to 7)); -- AC2G4
-- The following converts EBCDIC on the DATA_REG bus to card code CBA8421
-- For the purposes of this project, this will convert EBCDIC in DATA_REG into ASCII in PTT
-- sPTT_BIT_C <= EVEN_PARITY(...); -- C AC3G4
-- sPTT_BIT_B <= 0; -- AC3H2
-- sPTT_BIT_A <= 0; -- AC3K2
-- sPTT_BIT_8 <= 0; -- AC3G2
-- sPTT_BIT_4 <= 0; -- AC3G2
-- sPTT_BIT_2 <= 0; -- AC3G2
-- sPTT_BIT_1 <= 0; -- AC3G2
sPTT_BITS <= STD_LOGIC_VECTOR(to_unsigned(Character'Pos(EBCDIC_TO_ASCII(Conv_Integer(sDATA_REG))),7));
PTT_BITS <= sPTT_BITS;
CE_TE_LCH_SET <= (CE_DATA_ENTER_GT and CE_TE_DECODE) and n1050_OP_IN and CLOCK_1; -- AC2D7 AC2L6 ?? Ignore NOT in AC2M4
TE_LCH_SET <= CE_TE_LCH_SET or (CE_RUN_MODE and CE_TE_DECODE) or (sGT_1050_BUS_OUT and T4); -- AC2J7
sGT_WRITE_REG <= (Z_TIME and sALLOW_STROBE and not sSHIFT); -- AC2C6
GT_WRITE_REG <= sGT_WRITE_REG; -- AC2M4 AC2H6
TE_LCH_RESET <= sSET_LOWER_CASE or sGT_WRITE_REG;
TE_LCH_FL: entity FLL port map(S=>TE_LCH_SET,R=>TE_LCH_RESET,Q=>sTE_LCH); -- AC2B6
TE_LCH <= sTE_LCH;
WR_SHARE_REQ_SET <= not n1050_RST_LCH and W_TIME and WR_LCH and not sTE_LCH;
WR_SHARE_REQ_RESET <= RST_ATTACH or SHARE_REQ_RST;
WR_SHARE_REQ_FL: entity FLL port map(S=>WR_SHARE_REQ_SET,R=>WR_SHARE_REQ_RESET,Q=>sWR_SHARE_REQ); -- AC2K5 AC2D6
WR_SHARE_REQ <= sWR_SHARE_REQ;
ALLOW_STROBE_SET <= RDR_1_CLUTCH and Y_TIME and sTE_LCH;
ALLOW_STROBE_RESET <= sSET_LOWER_CASE or (Y_TIME and not RDR_1_CLUTCH) or X_TIME;
ALLOW_STROBE_FL: entity FLL port map(S=>ALLOW_STROBE_SET,R=>ALLOW_STROBE_RESET,Q=>sALLOW_STROBE); -- AC2B6
ALLOW_STROBE <= sALLOW_STROBE;
SHIFT_SET <= (n1050_CE_MODE and SET_SHIFT_LCH) or (SET_SHIFT_LCH and sTE_LCH and Y_TIME);
SHIFT_RESET <= X_TIME or sSET_LOWER_CASE;
SHIFT_FL: entity FLL port map(S=>SHIFT_SET,R=>SHIFT_RESET,Q=>sSHIFT); -- AC2B6
FORCE_SHIFT_CHAR <= (UC_CHARACTER and Z_TIME and sSHIFT) or (sSHIFT and Z_TIME and LC_CHARACTER); -- AC2C6
FORCE_LC_SHIFT <= (sSHIFT and Z_TIME and LC_CHARACTER); -- AC2D6 ?? not?
sSET_LOWER_CASE <= TA_REG_SET or RST_ATTACH; -- AC2C6 AC2D6
SET_LOWER_CASE <= sSET_LOWER_CASE;
INTRV_REQ_SET <= (not n1050_OPER and READ_INQ and not RD_SHARE_REQ_LCH)
or (not RD_SHARE_REQ_LCH and READ and (not TT_BUS(1) or not TT_BUS(3))) -- AC2G6 AC2H5
or ( WRITE_MODE
and not RESTORE
and not Z_TIME
and not TA_REG_SET
and (not TT_BUS(3) or not OUTPUT_SEL_AND_READY)
and (not CE_DATA_ENTER_GT or not n1050_CE_MODE)); -- AC2E5 AC2K7
INTRV_REQ_RESET <= SHARE_REQ_RST or RST_ATTACH; -- AC2H5 AC2H3
INTRV_REQ_FL: entity FLL port map(S=>INTRV_REQ_SET,R=>INTRV_REQ_RESET,Q=>sINTRV_REQ); -- AC2G6 AC2H3
TT5_POS_INTRV_REQ <= sINTRV_REQ;
n1050_INTRV_REQ_RESET <= n1050_CE_MODE or (Z_BUS(0) and GT_1050_TAGS_OUT) or (GT_1050_TAGS_OUT and Z_BUS(3)) or RST_ATTACH or sRDY_SHARE;
n1050_INTRV_REQ_FL: entity FLL port map(S=>sINTRV_REQ,R=>n1050_INTRV_REQ_RESET,Q=>n1050_INTRV_REQ); -- AC2K3 AC2H4
NOT_OPER_RESET <= RUN or sRDY_SHARE;
NOT_n1050_OPER <= not n1050_OPER;
NOT_OPER_FL: entity FLL port map(S=>NOT_n1050_OPER,R=>NOT_OPER_RESET,Q=>NOT_OPER); -- AC2G5 ?? Set input inverted
RDY_SHARE_SET <= not sINTRV_REQ and TT_BUS(3) and NOT_OPER; -- AC2J7
RDY_SHARE_RESET <= INTRV_REQ_RESET or RUN or TA_REG_POS_6_ATTN_RST;
RDY_SHARE_FL: entity FLL port map(S=>RDY_SHARE_SET,R=>RDY_SHARE_RESET,Q=>sRDY_SHARE); -- AC2F6 AC2E5
READY_SHARE <= sRDY_SHARE;
with DEBUG.Selection select
DEBUG.Probe <=
sDATA_REG(0) when 0,
sDATA_REG(1) when 1,
sDATA_REG(2) when 2,
sDATA_REG(3) when 3,
sDATA_REG(4) when 4,
sDATA_REG(5) when 5,
sDATA_REG(6) when 6,
sDATA_REG(7) when 7,
sNPL_BITS(0) when 8,
sNPL_BITS(1) when 9,
sNPL_BITS(2) when 10,
sNPL_BITS(3) when 11,
sNPL_BITS(4) when 12,
sNPL_BITS(5) when 13,
sNPL_BITS(6) when 14,
sNPL_BITS(7) when 15;
END FMD;
|
gpl-3.0
|
ibm2030/IBM2030
|
FMD2030_5-05D.vhd
|
1
|
9144
|
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-05D.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Read/Write Storage Clocks for 1st 32k
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Changed for 64k storage: START_1ST_32K triggered for 1st *and* 2nd 32k
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RWStgClk1st32k IS
port
(
-- Inputs
ALLOW_WRITE : IN STD_LOGIC; -- 03D
CPU_READ_PWR : IN STD_LOGIC; -- 04D
SEL_RD_CALL : IN STD_LOGIC; -- 12C
MAN_RD_CALL : IN STD_LOGIC; -- 03D
ROAR_RESTT_AND_STOR_BYPASS : IN STD_LOGIC; -- 04B
SEL_WR_CALL : IN STD_LOGIC; -- 12C
MAN_WR_CALL : IN STD_LOGIC; -- 03D
CPU_WRITE_PWR : IN STD_LOGIC; -- 04D
EARLY_LOCAL_STG : IN STD_LOGIC; -- 04D
EARLY_M_REG_0 : IN STD_LOGIC; -- 07B
M_REG_0 : IN STD_LOGIC; -- 07B
MACH_RST_SW : IN STD_LOGIC; -- 03D
-- Outputs
READ_CALL : OUT STD_LOGIC; -- 03A,03B
USE_LOCAL_MAIN_MEM : OUT STD_LOGIC; -- 06D
USE_MAIN_MEMORY : OUT STD_LOGIC; -- 06D
READ_ECHO_1, READ_ECHO_2 : OUT STD_LOGIC; -- 03D
DATA_READY_1, DATA_READY_2 : OUT STD_LOGIC; -- 03A 03B
WRITE_ECHO_1, WRITE_ECHO_2 : OUT STD_LOGIC; -- 03D
-- Debug
DEBUG1,DEBUG2,DEBUG3,DEBUG4 : OUT STD_LOGIC;
DEBUG : OUT STD_LOGIC;
DBG_TD1_1, DBG_TD1_2 : OUT STD_LOGIC_VECTOR(1 to 38);
DBG_RD_OR_WR_SET1,DBG_RD_OR_WR_RST1 : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
CLK : IN STD_LOGIC -- 50MHz / 20ns
);
END RWStgClk1st32k;
ARCHITECTURE FMD OF RWStgClk1st32k IS
signal START_RD,START_WR : STD_LOGIC;
signal START_1ST_32K, START_2ND_32K : STD_LOGIC;
signal READ_CALL_TO_MEM,WRITE_CALL_TO_MEM : STD_LOGIC;
signal sREAD_CALL : STD_LOGIC;
signal sUSE_LOCAL_MAIN_MEM : STD_LOGIC;
signal USE_LOCAL_Set,USE_LOCAL_Reset : STD_LOGIC;
signal TD1 : STD_LOGIC_VECTOR(1 to 38) := (others=>'0'); -- 20ns steps 20 to 740ns
signal RD_OR_WR_RST1, RD_OR_WR_SET1, nRD_OR_WR_SET1, CTRL_R_WIDTH1, TD1IN : STD_LOGIC;
signal TD1_80, TD1_150, TD1_200, TD1_500, TD1_560, TD1_660, TD1_680, TD1_700 : STD_LOGIC;
signal RD_OR_WR_SET1_RESET, dRD_OR_WR_SET1_RESET, CTRL_R_WIDTH1_RESET : STD_LOGIC;
signal READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_2_RESET : STD_LOGIC;
signal WRITE_ECHO_1_SET : STD_LOGIC;
signal WRITE_ECHO_1_RESET : STD_LOGIC;
signal READ_RST_SET1, READ_RST_SET2 : STD_LOGIC;
signal READ_RST_RESET1, READ_RST_RESET2 : STD_LOGIC;
signal RD_RST_CTRL1 : STD_LOGIC;
signal WRITE_RST_SET1 : STD_LOGIC;
signal WRITE_RST_RESET1 : STD_LOGIC;
signal WR_RST_CTRL1 : STD_LOGIC;
signal SET_READ_LCHS1 : STD_LOGIC;
signal DATA_READY1_SET, DATA_READY1_RESET : STD_LOGIC;
signal SET_READ_LCHS1_RESET : STD_LOGIC;
signal dT1 : STD_LOGIC;
signal sDATA_READY_1 : STD_LOGIC;
BEGIN
-- Fig 5-05D
START_RD <= not ALLOW_WRITE and CPU_READ_PWR and T1; -- AA1K4
START_WR <= ALLOW_WRITE and CPU_WRITE_PWR and T1; -- AA1K4
sREAD_CALL <= START_RD or SEL_RD_CALL or MAN_RD_CALL; -- AA1J2
READ_CALL <= sREAD_CALL;
READ_CALL_TO_MEM <= sREAD_CALL and not ROAR_RESTT_AND_STOR_BYPASS; -- AA1J3,AA1C2
WRITE_CALL_TO_MEM <= (MAN_WR_CALL or SEL_WR_CALL or START_WR) and not ROAR_RESTT_AND_STOR_BYPASS; -- AA1J2,AA1J3
USE_LOCAL_Set <= EARLY_LOCAL_STG and READ_CALL_TO_MEM;
USE_LOCAL_Reset <= not EARLY_LOCAL_STG and READ_CALL_TO_MEM;
USE_LOCAL: entity work.FLL port map(USE_LOCAL_Set,USE_LOCAL_Reset,sUSE_LOCAL_MAIN_MEM); -- CB1E2
USE_LOCAL_MAIN_MEM <= sUSE_LOCAL_MAIN_MEM;
USE_MAIN_MEMORY <= not sUSE_LOCAL_MAIN_MEM; -- CB1H2
-- START_1ST_32K <= (not EARLY_M_REG_0 and READ_CALL_TO_MEM) or (READ_CALL_TO_MEM and EARLY_LOCAL_STG) or (not M_REG_0 and WRITE_CALL_TO_MEM) or (WRITE_CALL_TO_MEM and sUSE_LOCAL_MAIN_MEM); -- CB1E2
-- START_2ND_32K <= (READ_CALL_TO_MEM and EARLY_M_REG_0 and not sUSE_LOCAL_MAIN_MEM) or (WRITE_CALL_TO_MEM and M_REG_0 and not sUSE_LOCAL_MAIN_MEM); -- CB1E2
START_1ST_32K <= READ_CALL_TO_MEM or WRITE_CALL_TO_MEM; -- CB1E2 combined 1st & 2nd 32k
-- Generate timing signals relative to START_xxx_32K
-- READ_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW)
-- WRITE_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW)
-- DATA_READY_n ON at 640ns OFF at 700ns (or MACH_RST_SW)
-- First 32K
TD1_80 <= TD1(4); -- 80ns
TD1_150 <= TD1(8); -- 160ns
TD1_200 <= TD1(10); -- 200ns
TD1_500 <= TD1(25); -- 500ns
TD1_560 <= TD1(28); -- 560ns
TD1_660 <= TD1(33); -- 660ns
TD1_680 <= TD1(34); -- 680ns
TD1_700 <= TD1(35); -- 700ns
nRD_OR_WR_SET1 <= not RD_OR_WR_SET1;
RD_OR_WR_RST1_FL: entity work.FLL port map(TD1_80, nRD_OR_WR_SET1, RD_OR_WR_RST1);
RD_OR_WR_SET1_RESET <= RD_OR_WR_RST1 or MACH_RST_SW;
-- The delay is to prevent a combinatorial loop:
Delay_RD_OR_WR_SET1_RESET: AR port map (D=>RD_OR_WR_SET1_RESET, clk=>Clk, Q=>dRD_OR_WR_SET1_RESET);
RD_OR_WR_SET1_FL: entity work.FLL port map(START_1ST_32K, dRD_OR_WR_SET1_RESET, RD_OR_WR_SET1);
TD1IN <= not RD_OR_WR_RST1 and RD_OR_WR_SET1;
-- READ CLOCK 0
READ_ECHO_1_SET <= TD1_150 and SET_READ_LCHS1;
READ_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and RD_RST_CTRL1);
READ_ECHO_1_FL: entity work.FLL port map(READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_1); -- 150 to 680ns
-- READ CLOCK 4
DATA_READY1_SET <= TD1_560 and SET_READ_LCHS1;
DATA_READY1_RESET <= MACH_RST_SW or (TD1_660 and RD_RST_CTRL1);
DATA_READY1_FL: entity work.FLL port map(DATA_READY1_SET, DATA_READY1_RESET, sDATA_READY_1); -- 560 to 660ns
DATA_READY_1 <= sDATA_READY_1;
-- READ CLOCK 5
READ_RST_SET1 <= TD1_500 and SET_READ_LCHS1;
READ_RST_RESET1 <= MACH_RST_SW or TD1_700;
READ_RST1_FL: entity work.FLL port map(READ_RST_SET1, READ_RST_RESET1, RD_RST_CTRL1); -- 500 to 700ns
-- WRITE CLOCK 0
WRITE_ECHO_1_SET <= TD1_150 and not SET_READ_LCHS1;
WRITE_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and WR_RST_CTRL1);
WRITE_ECHO_1_FL: entity work.FLL port map(WRITE_ECHO_1_SET, WRITE_ECHO_1_RESET, WRITE_ECHO_1); -- 150 to 680ns
-- WRITE CLOCK 4
SET_READ_LCHS1_RESET <= MACH_RST_SW or WRITE_CALL_TO_MEM; -- ??
SET_READ_LCHS1_FL: entity work.FLL port map(READ_CALL_TO_MEM, SET_READ_LCHS1_RESET, SET_READ_LCHS1); -- RD CALL to WR CALL
-- WRITE CLOCK 5
WRITE_RST_SET1 <= TD1_500 and not SET_READ_LCHS1;
WRITE_RST_RESET1 <= MACH_RST_SW or TD1_150; -- 150ns or 1050ns or 1500ns?
WRITE_RST1_FL: entity work.FLL port map(WRITE_RST_SET1, WRITE_RST_RESET1, WR_RST_CTRL1); -- 500 to 700ns??
-- Second 32K
READ_ECHO_2 <= '0';
DATA_READY_2 <= '0';
WRITE_ECHO_2 <= '0';
-- Debug
DEBUG <= START_RD;
DBG_TD1_1 <= TD1;
DBG_RD_OR_WR_SET1 <= RD_OR_WR_SET1;
DBG_RD_OR_WR_RST1 <= RD_OR_WR_RST1;
delayLine: process(CLK)
begin
if (rising_edge(CLK)) then
TD1 <= TD1IN & TD1(1 to TD1'right-1);
end if;
end process;
-- Debug latch
R_DEBUG: process (clk,T1,TD1IN)
begin
if rising_edge(clk) then
if T1='1' and dT1='0' then
DEBUG1 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T1)='1' then
DEBUG1 <= '1'; -- Set on any DATA_READY
end if;
end if;
if T1='1' and dT1='0' then
DEBUG2 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T2)='1' then
DEBUG2 <= '1'; -- Set on any DATA_READY
end if;
end if;
if T1='1' and dT1='0' then
DEBUG3 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T3)='1' then
DEBUG3 <= '1'; -- Set on any DATA_READY
end if;
end if;
if T1='1' and dT1='0' then
DEBUG4 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T4)='1' then
DEBUG4 <= '1'; -- Set on any DATA_READY
end if;
end if;
dT1 <= T1;
end if;
end process;
END FMD;
|
gpl-3.0
|
freecores/usb_fpga_1_15
|
examples/usb-fpga-1.11/1.11a/ucecho/fpga/ucecho.vhd
|
42
|
580
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
gpl-3.0
|
freecores/usb_fpga_1_15
|
examples/usb-fpga-2.04/2.04b/memtest/fpga/memtest.vhd
|
3
|
24037
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity memtest is
port(
FXCLK : in std_logic;
RESET_IN : in std_logic;
IFCLK : in std_logic;
-- FX2 FIFO
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic;
PA3 : in std_logic;
-- errors ...
LED1 : out std_logic_vector(9 downto 0);
-- DDR-SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end memtest;
architecture RTL of memtest is
component mem0
generic (
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_RST_ACT_LOW : integer := 0;
C3_CALIB_SOFT_IP : string := "FALSE";
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;
signal fxclk_buf : std_logic;
signal CLK : std_logic;
signal RESET0 : std_logic; -- released after dcm0 is ready
signal RESET : std_logic; -- released after MCB is ready
signal DCM0_LOCKED : std_logic;
--signal DCM0_CLK_VALID : std_logic;
----------------------------
-- test pattern generator --
----------------------------
signal GEN_CNT : std_logic_vector(29 downto 0);
signal GEN_PATTERN : std_logic_vector(29 downto 0);
signal FIFO_WORD : std_logic;
-----------------------
-- memory controller --
-----------------------
signal MEM_CLK : std_logic;
signal C3_CALIB_DONE : std_logic;
signal C3_RST0 : std_logic;
---------------
-- DRAM FIFO --
---------------
signal WR_CLK : std_logic;
signal WR_CMD_EN : std_logic_vector(2 downto 0);
type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal WR_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal WR_EN : std_logic_vector(2 downto 0);
signal WR_EN_TMP : std_logic_vector(2 downto 0);
signal WR_DATA : std_logic_vector(31 downto 0);
signal WR_EMPTY : std_logic_vector(2 downto 0);
signal WR_UNDERRUN : std_logic_vector(2 downto 0);
signal WR_ERROR : std_logic_vector(2 downto 0);
type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal WR_COUNT : WR_COUNT_ARRAY;
signal WR_PORT : std_logic_vector(1 downto 0);
signal RD_CLK : std_logic;
signal RD_CMD_EN : std_logic_vector(2 downto 0);
type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal RD_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal RD_EN : std_logic_vector(2 downto 0);
type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
signal RD_DATA : RD_DATA_ARRAY;
signal RD_EMPTY : std_logic_vector(2 downto 0);
signal RD_OVERFLOW : std_logic_vector(2 downto 0);
signal RD_ERROR : std_logic_vector(2 downto 0);
signal RD_PORT : std_logic_vector(1 downto 0);
type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal RD_COUNT : RD_COUNT_ARRAY;
signal FD_TMP : std_logic_vector(15 downto 0);
signal RD_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing read
signal RD_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing written
signal WR_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_STOP : std_logic;
begin
clkin_buf : IBUFG
port map (
O => FXCLK_BUF,
I => FXCLK
);
dcm0 : DCM_CLKGEN
generic map (
CLKFX_DIVIDE => 6,
CLKFX_MULTIPLY => 25,
CLKFXDV_DIVIDE => 4,
SPREAD_SPECTRUM => "NONE",
STARTUP_WAIT => FALSE,
CLKIN_PERIOD => 20.83333,
CLKFX_MD_MAX => 0.000
)
port map (
CLKIN => FXCLK_BUF,
CLKFX => MEM_CLK,
CLKFX180 => open,
CLKFXDV => CLK,
LOCKED => DCM0_LOCKED,
PROGDONE => open,
STATUS => open,
FREEZEDCM => '0',
PROGCLK => '0',
PROGDATA => '0',
PROGEN => '0',
RST => '0'
);
inst_mem0 : mem0 port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => mcb3_rzq,
c3_sys_clk => MEM_CLK,
c3_sys_rst_n => RESET0,
c3_clk0 => open,
c3_rst0 => C3_RST0,
c3_calib_done => C3_CALIB_DONE,
c3_p0_cmd_clk => WR_CLK,
c3_p0_cmd_en => WR_CMD_EN(0),
c3_p0_cmd_instr => "000",
c3_p0_cmd_bl => ( others => '1' ),
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
c3_p0_cmd_empty => open,
c3_p0_cmd_full => open,
c3_p0_wr_clk => WR_CLK,
c3_p0_wr_en => WR_EN(0),
c3_p0_wr_mask => ( others => '0' ),
c3_p0_wr_data => WR_DATA,
c3_p0_wr_full => open,
c3_p0_wr_empty => WR_EMPTY(0),
c3_p0_wr_count => open,
c3_p0_wr_underrun => WR_UNDERRUN(0),
c3_p0_wr_error => WR_ERROR(0),
c3_p0_rd_clk => WR_CLK,
c3_p0_rd_en => '0',
c3_p0_rd_data => open,
c3_p0_rd_full => open,
c3_p0_rd_empty => open,
c3_p0_rd_count => open,
c3_p0_rd_overflow => open,
c3_p0_rd_error => open,
c3_p2_cmd_clk => WR_CLK,
c3_p2_cmd_en => WR_CMD_EN(1),
c3_p2_cmd_instr => "000",
c3_p2_cmd_bl => ( others => '1' ),
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
c3_p2_cmd_empty => open,
c3_p2_cmd_full => open,
c3_p2_wr_clk => WR_CLK,
c3_p2_wr_en => WR_EN(1),
c3_p2_wr_mask => ( others => '0' ),
c3_p2_wr_data => WR_DATA,
c3_p2_wr_full => open,
c3_p2_wr_empty => WR_EMPTY(1),
c3_p2_wr_count => open,
c3_p2_wr_underrun => WR_UNDERRUN(1),
c3_p2_wr_error => WR_ERROR(1),
c3_p4_cmd_clk => WR_CLK,
c3_p4_cmd_en => WR_CMD_EN(2),
c3_p4_cmd_instr => "000",
c3_p4_cmd_bl => ( others => '1' ),
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
c3_p4_cmd_empty => open,
c3_p4_cmd_full => open,
c3_p4_wr_clk => WR_CLK,
c3_p4_wr_en => WR_EN(2),
c3_p4_wr_mask => ( others => '0' ),
c3_p4_wr_data => WR_DATA,
c3_p4_wr_full => open,
c3_p4_wr_empty => WR_EMPTY(2),
c3_p4_wr_count => open,
c3_p4_wr_underrun => WR_UNDERRUN(2),
c3_p4_wr_error => WR_ERROR(2),
c3_p1_cmd_clk => RD_CLK,
c3_p1_cmd_en => RD_CMD_EN(0),
c3_p1_cmd_instr => "001",
c3_p1_cmd_bl => ( others => '1' ),
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
c3_p1_cmd_empty => open,
c3_p1_cmd_full => open,
c3_p1_wr_clk => RD_CLK,
c3_p1_wr_en => '0',
c3_p1_wr_mask => ( others => '0' ),
c3_p1_wr_data => ( others => '0' ),
c3_p1_wr_full => open,
c3_p1_wr_empty => open,
c3_p1_wr_count => open,
c3_p1_wr_underrun => open,
c3_p1_wr_error => open,
c3_p1_rd_clk => RD_CLK,
c3_p1_rd_en => RD_EN(0),
c3_p1_rd_data => RD_DATA(0),
c3_p1_rd_full => open,
c3_p1_rd_empty => RD_EMPTY(0),
c3_p1_rd_count => open,
c3_p1_rd_overflow => RD_OVERFLOW(0),
c3_p1_rd_error => RD_ERROR(0),
c3_p3_cmd_clk => RD_CLK,
c3_p3_cmd_en => RD_CMD_EN(1),
c3_p3_cmd_instr => "001",
c3_p3_cmd_bl => ( others => '1' ),
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_rd_clk => RD_CLK,
c3_p3_rd_en => RD_EN(1),
c3_p3_rd_data => RD_DATA(1),
c3_p3_rd_full => open,
c3_p3_rd_empty => RD_EMPTY(1),
c3_p3_rd_count => open,
c3_p3_rd_overflow => RD_OVERFLOW(1),
c3_p3_rd_error => RD_ERROR(1),
c3_p5_cmd_clk => RD_CLK,
c3_p5_cmd_en => RD_CMD_EN(2),
c3_p5_cmd_instr => "001",
c3_p5_cmd_bl => ( others => '1' ),
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
c3_p5_cmd_empty => open,
c3_p5_cmd_full => open,
c3_p5_rd_clk => RD_CLK,
c3_p5_rd_en => RD_EN(2),
c3_p5_rd_data => RD_DATA(2),
c3_p5_rd_full => open,
c3_p5_rd_empty => RD_EMPTY(2),
c3_p5_rd_count => open,
c3_p5_rd_overflow => RD_OVERFLOW(2),
c3_p5_rd_error => RD_ERROR(2)
);
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1';
WR_CLK <= CLK;
RD_CLK <= IFCLK;
-- RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
-- RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
RESET0 <= RESET_IN or (not DCM0_LOCKED);
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
LED1(0) <= WR_UNDERRUN(0) or WR_UNDERRUN(1) or WR_UNDERRUN(2);
LED1(1) <= WR_ERROR(0) or WR_ERROR(1) or WR_ERROR(2);
LED1(2) <= RD_OVERFLOW(0) or RD_OVERFLOW(1) or RD_OVERFLOW(2);
LED1(3) <= RD_ERROR(0) or RD_ERROR(1) or RD_ERROR(2);
LED1(4) <= C3_CALIB_DONE;
LED1(5) <= C3_RST0;
LED1(6) <= RESET0;
LED1(7) <= RESET;
LED1(8) <= '0';
LED1(9) <= '1';
dpCLK: process (CLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
GEN_PATTERN <= "100101010101010101010101010101";
WR_CMD_EN <= ( others => '0' );
WR_CMD_ADDR(0) <= ( others => '0' );
WR_CMD_ADDR(1) <= ( others => '0' );
WR_CMD_ADDR(2) <= ( others => '0' );
WR_ADDR <= conv_std_logic_vector(3,18);
WR_EN <= ( others => '0' );
WR_COUNT(0) <= ( others => '0' );
WR_COUNT(1) <= ( others => '0' );
WR_COUNT(2) <= ( others => '0' );
WR_PORT <= ( others => '0' );
WR_ADDR2 <= ( others => '0' );
RD_ADDR2_BAK1 <= ( others => '0' );
RD_ADDR2_BAK2 <= ( others => '0' );
-- CLK
elsif CLK'event and CLK = '1'
then
WR_CMD_EN <= ( others => '0' );
WR_EN <= ( others => '0' );
WR_CMD_ADDR(conv_integer(WR_PORT))(25 downto 8) <= WR_ADDR;
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
then
-- FF flag = 1
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
then
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
if WR_PORT = "10"
then
WR_PORT <= "00";
else
WR_PORT <= WR_PORT + 1;
end if;
WR_ADDR <= WR_ADDR + 1;
WR_ADDR2 <= WR_ADDR2 + 1;
end if;
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
then
-- FF flag = 1
else
WR_EN(conv_integer(WR_PORT)) <= '1';
WR_DATA(31) <= '1';
WR_DATA(15) <= '0';
if PA3 = '1'
then
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
else
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
end if;
GEN_CNT <= GEN_CNT + 1;
GEN_PATTERN(29) <= GEN_PATTERN(0);
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
-- then
-- else
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
-- end if;
end if;
RD_ADDR2_BAK1 <= RD_ADDR2;
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
end if;
end process dpCLK;
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
FIFO_WORD <= '0';
SLWR <= '1';
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(0) <= ( others => '0' );
RD_CMD_ADDR(1) <= ( others => '0' );
RD_CMD_ADDR(2) <= ( others => '0' );
RD_ADDR <= conv_std_logic_vector(3,18);
RD_EN <= ( others => '0' );
RD_COUNT(0) <= conv_std_logic_vector(64,7);
RD_COUNT(1) <= conv_std_logic_vector(64,7);
RD_COUNT(2) <= conv_std_logic_vector(64,7);
RD_PORT <= ( others => '0' );
RD_ADDR2 <= ( others => '0' );
WR_ADDR2_BAK1 <= ( others => '0' );
WR_ADDR2_BAK2 <= ( others => '0' );
RD_STOP <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(conv_integer(RD_PORT))(25 downto 8) <= RD_ADDR;
RD_EN(conv_integer(RD_PORT)) <= '0';
if FLAGB = '1'
then
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
then
SLWR <= '1';
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
then
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
if RD_PORT = "10"
then
RD_PORT <= "00";
else
RD_PORT <= RD_PORT + 1;
end if;
RD_ADDR <= RD_ADDR + 1;
RD_ADDR2 <= RD_ADDR2 + 1;
end if;
else
SLWR <= '0';
if FIFO_WORD = '0'
then
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
RD_EN(conv_integer(RD_PORT)) <= '1';
else
FD(15 downto 0) <= FD_TMP;
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
end if;
WR_ADDR2_BAK1 <= WR_ADDR2;
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
then
RD_STOP <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
|
gpl-3.0
|
ibm2030/IBM2030
|
FMD2030_5-10D.vhd
|
1
|
8948
|
---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10D.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console attachment and CE section
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.all;
ENTITY n1050_ATTACH IS
port
(
-- Inputs
-- CE Cable
CE_CABLE_IN : IN CE_IN := ("00000000",'0','0','0','0','0','0','0','0','0','0');
-- CE DATA BUS From 1050 DATA section
PTT_BITS : IN STD_LOGIC_VECTOR(0 to 6);
DATA_REG : IN STD_LOGIC_VECTOR(0 to 7);
NPL_BITS : IN STD_LOGIC_VECTOR(0 to 7);
-- Other stuff
TE_LCH : IN STD_LOGIC; -- 10CB5
WRITE_UC : IN STD_LOGIC; -- 09CD6
XLATE_UC : IN STD_LOGIC; -- 09CB6
CPU_REQUEST_IN : IN STD_LOGIC; -- 10BD6
n1050_OP_IN : IN STD_LOGIC; -- 10BB5
HOME_RDR_STT_LCH : IN STD_LOGIC; -- 10BB3
RDR_ON_LCH : IN STD_LOGIC; -- 10BD3
MICRO_SHARE_LCH : IN STD_LOGIC; -- 10BC3
PROCEED_LCH : IN STD_LOGIC; -- 10BC3
TA_REG_POS_4 : IN STD_LOGIC; -- 10BE3
CR_LF : IN STD_LOGIC; -- 10BE3
TA_REG_POS_6 : IN STD_LOGIC; -- 10BE3
n1050_RST : IN STD_LOGIC; -- 10BE2
GT_WR_REG : IN STD_LOGIC; -- 10CB6
FORCE_LC_SHIFT : IN STD_LOGIC; -- 10CC6
FORCE_SHIFT_CHAR : IN STD_LOGIC; -- 10CC6
WR_STROBE : IN STD_LOGIC; -- 09CD2
PCH_1_HOME : IN STD_LOGIC; -- 09CD6
HOME_RDR_STOP : IN STD_LOGIC; -- 10BB3
TT2_POS_END : IN STD_LOGIC; -- 09CB5 - NOT IN FMD
TT5_POS_INTRV_REQ : IN STD_LOGIC; -- 10CD5
TT6_POS_ATTN : IN STD_LOGIC; -- 10BD6
CPU_LINES_ENTRY : IN CONN_1050; -- 10BE3
-- Outputs
-- CE Cable
CE_CABLE_OUT : OUT CE_OUT;
-- CE DATA BUS to 10C (1050 DATA)
CE_GT_TA_OR_TE : OUT STD_LOGIC; -- 10C
CE_DATA_ENTER_GT : OUT STD_LOGIC; -- 10BB1 10CA4 10C
CE_TE_DECODE : OUT STD_LOGIC; -- 10CA4 10C
CE_MODE_AND_TE_LCH : OUT STD_LOGIC;
n1050_CE_MODE : OUT STD_LOGIC; -- 10CB3 10BD5
-- Other stuff
CE_SEL_OUT : OUT STD_LOGIC; -- 10BD5
CE_TI_DECODE : OUT STD_LOGIC; -- 09CC5
CE_RUN_MODE : OUT STD_LOGIC; -- 09CC5
CE_TA_DECODE : OUT STD_LOGIC; -- 10BB1
CE_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 10C
EXIT_MPLX_SHARE : OUT STD_LOGIC; -- 10BB5
CE_DATA_ENTER_NC : OUT STD_LOGIC;
-- TT3_POS_1050_OPER : OUT STD_LOGIC; -- 10BE2 10BB2 10BE2 10CE5 Moved to TT_BUS(3)
-- TT4_POS_HOME_STT : OUT STD_LOGIC; -- 10CD2 Moved to TT_BUS(4)
OUTPUT_SEL_AND_RDY : OUT STD_LOGIC; -- 10CD4
n1050_OPER : OUT STD_LOGIC; -- 10CC4 10CE4
PUNCH_BITS : OUT STD_LOGIC_VECTOR(0 to 6); -- 10CE1
READ_INTLK_RST : OUT STD_LOGIC; -- 10BA1
PUNCH_1_CLUTCH : OUT STD_LOGIC; -- 10CE1 10AC1
-- PCH_1_CLUTCH_1050 : OUT STD_LOGIC; -- 09CE1 10BA1 09CD5
REQUEST_KEY : OUT STD_LOGIC; -- 10BE4
RDR_1_CLUTCH : OUT STD_LOGIC;
-- In/Out TT bus
TT_BUS : INOUT STD_LOGIC_VECTOR(0 to 7);
GTD_TT3 : IN STD_LOGIC;
-- Hardware Serial Port
serialInput : in Serial_Input_Lines;
serialOutput : out Serial_Output_Lines;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END n1050_ATTACH;
ARCHITECTURE FMD OF n1050_ATTACH IS
signal sCE_TA_DECODE, sCE_TE_DECODE : STD_LOGIC;
signal sCE_DATA_ENTER_GT : STD_LOGIC;
signal sn1050_CE_MODE : STD_LOGIC;
signal sPUNCH_1_CLUTCH : STD_LOGIC;
signal sRDR_1_CLUTCH : STD_LOGIC;
signal sOUTPUT_SEL_AND_RDY : STD_LOGIC;
signal TT1_POS_RDR_2_RDY, sTT3_POS_1050_OPER, sTT4_POS_HOME_STT : STD_LOGIC;
signal PCH_CONN_ENTRY : PCH_CONN;
signal RDR_1_CONN_EXIT : RDR_CONN;
signal CPU_LINES_EXIT : CONN_1050;
BEGIN
-- Fig 5-10D
sCE_TA_DECODE <= CE_CABLE_IN.CE_TA_DECODE;
CE_TA_DECODE <= sCE_TA_DECODE;
CE_GT_TA_OR_TE <= (CE_CABLE_IN.CE_TA_DECODE and sCE_DATA_ENTER_GT) or (sCE_TE_DECODE and sCE_DATA_ENTER_GT); -- AC2G5
sCE_DATA_ENTER_GT <= CE_CABLE_IN.CE_TI_OR_TE_RUN_MODE;
CE_DATA_ENTER_GT <= sCE_DATA_ENTER_GT;
-- CE cable entry
CE_BUS <= CE_CABLE_IN.CE_BIT; -- AC2M3
sCE_TE_DECODE <= CE_CABLE_IN.CE_TE_DECODE; -- AC2M2
CE_TE_DECODE <= sCE_TE_DECODE;
CE_SEL_OUT <= CE_CABLE_IN.CE_SEL_OUT; -- AC2M2
CE_TI_DECODE <= CE_CABLE_IN.CE_TI_DECODE; -- AC2M2
CE_RUN_MODE <= not CE_CABLE_IN.CE_MODE; -- AC2M2
CE_MODE_AND_TE_LCH <= (TE_LCH and sn1050_CE_MODE) or CE_CABLE_IN.CE_SEL_OUT; -- AC2E7
sn1050_CE_MODE <= CE_CABLE_IN.CE_MODE;
n1050_CE_MODE <= sn1050_CE_MODE;
EXIT_MPLX_SHARE <= CE_CABLE_IN.CE_EXIT_MPLX_SHARE;
CE_DATA_ENTER_NC <= CE_CABLE_IN.CE_DATA_ENTER_NC;
-- CE cable exit
CE_CABLE_OUT.PTT_BITS <= PTT_BITS;
CE_CABLE_OUT.DATA_REG <= DATA_REG;
CE_CABLE_OUT.RDR_1_CLUTCH <= sRDR_1_CLUTCH;
CE_CABLE_OUT.WRITE_UC <= WRITE_UC;
CE_CABLE_OUT.XLATE_UC <= XLATE_UC;
CE_CABLE_OUT.PUNCH_1_CLUTCH <= sPUNCH_1_CLUTCH;
CE_CABLE_OUT.NPL <= NPL_BITS;
CE_CABLE_OUT.OUTPUT_SEL_AND_RDY <= sOUTPUT_SEL_AND_RDY;
CE_CABLE_OUT.TT <= TT_BUS(0 to 2) & GTD_TT3 & TT_BUS(4 to 7);
CE_CABLE_OUT.CPU_REQUEST_IN <= CPU_REQUEST_IN;
CE_CABLE_OUT.n1050_OP_IN <= n1050_OP_IN;
CE_CABLE_OUT.HOME_RDR_STT_LCH <= HOME_RDR_STT_LCH;
CE_CABLE_OUT.RDR_ON_LCH <= RDR_ON_LCH;
CE_CABLE_OUT.MICRO_SHARE_LCH <= MICRO_SHARE_LCH;
CE_CABLE_OUT.PROCEED_LCH <= PROCEED_LCH;
CE_CABLE_OUT.TA_REG_POS_4 <= TA_REG_POS_4;
CE_CABLE_OUT.CR_LF <= CR_LF;
CE_CABLE_OUT.TA_REG_POS_6 <= TA_REG_POS_6;
CE_CABLE_OUT.n1050_RST <= n1050_RST;
-- RDR connection (output)
-- FORCE_LC_SHIFT and FORCE_SHIFT_CHAR makes 0111110 (downshift)
-- FORCE_SHIFT_CHAR makes 0001110 (upshift)
-- We remove this in favour of simple ASCII on the output
-- RDR_1_CONN_EXIT.RDR_BITS <= (PTT_BITS(0) and GT_WR_REG) -- C
-- & ((PTT_BITS(1) and GT_WR_REG) or FORCE_LC_SHIFT) -- B
-- & ((PTT_BITS(2) and GT_WR_REG) or FORCE_LC_SHIFT) -- A
-- & ((PTT_BITS(3) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 8
-- & ((PTT_BITS(4) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 4
-- & ((PTT_BITS(5) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 2
-- & (PTT_BITS(6) and GT_WR_REG); -- 1
RDR_1_CONN_EXIT.RDR_BITS <= PTT_BITS;
RDR_1_CONN_EXIT.RD_STROBE <= WR_STROBE;
CPU_LINES_EXIT <= CPU_LINES_ENTRY;
-- TT Bus
TT_BUS(1) <= TT1_POS_RDR_2_RDY;
TT_BUS(2) <= TT2_POS_END;
TT_BUS(3) <= sTT3_POS_1050_OPER;
-- TT3_POS_1050_OPER <= sTT3_POS_1050_OPER;
TT_BUS(4) <= sTT4_POS_HOME_STT;
-- TT4_POS_HOME_STT <= sTT4_POS_HOME_STT;
TT_BUS(5) <= TT5_POS_INTRV_REQ;
TT_BUS(6) <= TT6_POS_ATTN;
-- PCH connections (input)
PUNCH_BITS <= PCH_CONN_ENTRY.PCH_BITS; -- AC2L4
READ_INTLK_RST <= '1' when PCH_CONN_ENTRY.PCH_BITS="0000000" else '0'; -- AC2E3
sPUNCH_1_CLUTCH <= PCH_CONN_ENTRY.PCH_1_CLUTCH_1050; -- AC2M2 AC2J7
PUNCH_1_CLUTCH <= sPUNCH_1_CLUTCH;
-- PCH_1_CLUTCH_1050 <= sPUNCH_1_CLUTCH;
TT1_POS_RDR_2_RDY <= PCH_CONN_ENTRY.RDR_2_READY; -- AC2M5 AC2L5
sTT3_POS_1050_OPER <= PCH_CONN_ENTRY.CPU_CONNECTED; -- AC2J5
sTT4_POS_HOME_STT <= PCH_CONN_ENTRY.HOME_RDR_STT_LCH; -- AC2M5 AC2L5
-- TT4_POS_HOME_STT <= sTT4_POS_HOME_STT;
sOUTPUT_SEL_AND_RDY <= PCH_CONN_ENTRY.HOME_OUTPUT_DEV_RDY;
OUTPUT_SEL_AND_RDY <= sOUTPUT_SEL_AND_RDY;
sRDR_1_CLUTCH <= PCH_CONN_ENTRY.RDR_1_CLUTCH_1050; -- AC2M4
RDR_1_CLUTCH <= sRDR_1_CLUTCH;
n1050_OPER <= PCH_CONN_ENTRY.CPU_CONNECTED; -- FA1D4
REQUEST_KEY <=PCH_CONN_ENTRY.REQ_KEY; -- FA1D4
console : entity ibm1050 port map(
SerialIn => PCH_CONN_ENTRY,
SerialOut => RDR_1_CONN_EXIT,
SerialControl => CPU_LINES_EXIT,
serialInput => serialInput,
serialOutput => serialOutput,
clk => clk);
END FMD;
|
gpl-3.0
|
zeruniverse/pipelined_CPU
|
ISE project/ipcore_dir/data_mem.vhd
|
1
|
6674
|
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file data_mem.vhd when simulating
-- the core, data_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY data_mem IS
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(5 downto 0);
dina: in std_logic_vector(31 downto 0);
douta: out std_logic_vector(31 downto 0));
END data_mem;
ARCHITECTURE data_mem_a OF data_mem IS
-- synthesis translate_off
component wrapped_data_mem
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(5 downto 0);
dina: in std_logic_vector(31 downto 0);
douta: out std_logic_vector(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_data_mem use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 32,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 32,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "data_mem.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3",
c_write_depth_b => 64,
c_write_depth_a => 64,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 6,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 6,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 32,
c_write_width_a => 32,
c_read_depth_b => 64,
c_read_depth_a => 64,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_data_mem
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END data_mem_a;
|
gpl-3.0
|
nanomolina/MIPS
|
prueba/writeback.vhd
|
2
|
720
|
library ieee;
use ieee.std_logic_1164.all;
entity writeback is
port(
AluOutW, ReadDataW: in std_logic_vector(31 downto 0);
MemToReg: in std_logic;
ResultW: out std_logic_vector(31 downto 0));
end entity;
architecture wb_arq of writeback is
component mux2
generic (MAX : integer := 32);
port (
d0, d1: in std_logic_vector((MAX-1) downto 0);
s: in std_logic;
y: out std_logic_vector((MAX-1) downto 0));
end component;
begin
mux2_1: mux2 port map (
d0 => AluOutW,
d1 => ReadDataW,
s => MemToReg,
y => ResultW); --salida
end architecture;
|
gpl-3.0
|
zeruniverse/pipelined_CPU
|
ISE project/ipcore_dir/mem_ins.vhd
|
1
|
5714
|
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file mem_ins.vhd when simulating
-- the core, mem_ins. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY mem_ins IS
port (
a: in std_logic_vector(5 downto 0);
spo: out std_logic_vector(31 downto 0));
END mem_ins;
ARCHITECTURE mem_ins_a OF mem_ins IS
-- synthesis translate_off
component wrapped_mem_ins
port (
a: in std_logic_vector(5 downto 0);
spo: out std_logic_vector(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_mem_ins use entity XilinxCoreLib.dist_mem_gen_v5_1(behavioral)
generic map(
c_has_clk => 0,
c_has_qdpo_clk => 0,
c_has_qdpo_ce => 0,
c_parser_type => 1,
c_has_d => 0,
c_has_spo => 1,
c_read_mif => 1,
c_has_qspo => 0,
c_width => 32,
c_reg_a_d_inputs => 0,
c_has_we => 0,
c_pipeline_stages => 0,
c_has_qdpo_rst => 0,
c_reg_dpra_input => 0,
c_qualify_we => 0,
c_family => "spartan3",
c_sync_enable => 1,
c_depth => 64,
c_has_qspo_srst => 0,
c_has_qdpo_srst => 0,
c_has_dpra => 0,
c_qce_joined => 0,
c_mem_type => 0,
c_has_i_ce => 0,
c_has_dpo => 0,
c_mem_init_file => "mem_ins.mif",
c_default_data => "0",
c_has_spra => 0,
c_has_qspo_ce => 0,
c_addr_width => 6,
c_has_qspo_rst => 0,
c_has_qdpo => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mem_ins
port map (
a => a,
spo => spo);
-- synthesis translate_on
END mem_ins_a;
|
gpl-3.0
|
nanomolina/MIPS
|
PIPELINE/maindec.vhd
|
6
|
1077
|
library ieee;
use ieee.std_logic_1164.all;
entity maindec is
port (Op: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluOp: out std_logic_vector(1 downto 0));
end entity;
architecture arq_maindec of maindec is
signal parcial_result: std_logic_vector(8 downto 0);
begin
parcial_result <= ("110000010") when (Op = "000000") else
("101001000") when (Op = "100011") else
("001010000") when (Op = "101011") else
("000100001") when (Op = "000100") else
("101000000") when (Op = "001000") else
("000000100") when (Op = "000010") else
("---------");
RegWrite <= parcial_result(8);
RegDst <= parcial_result(7);
AluSrc <= parcial_result(6);
Branch <= parcial_result(5);
MemWrite <= parcial_result(4);
MemToReg <= parcial_result(3);
Jump <= parcial_result(2);
AluOp <= parcial_result(1 downto 0);
end architecture;
|
gpl-3.0
|
nanomolina/MIPS
|
prueba/maindec.vhd
|
6
|
1077
|
library ieee;
use ieee.std_logic_1164.all;
entity maindec is
port (Op: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluOp: out std_logic_vector(1 downto 0));
end entity;
architecture arq_maindec of maindec is
signal parcial_result: std_logic_vector(8 downto 0);
begin
parcial_result <= ("110000010") when (Op = "000000") else
("101001000") when (Op = "100011") else
("001010000") when (Op = "101011") else
("000100001") when (Op = "000100") else
("101000000") when (Op = "001000") else
("000000100") when (Op = "000010") else
("---------");
RegWrite <= parcial_result(8);
RegDst <= parcial_result(7);
AluSrc <= parcial_result(6);
Branch <= parcial_result(5);
MemWrite <= parcial_result(4);
MemToReg <= parcial_result(3);
Jump <= parcial_result(2);
AluOp <= parcial_result(1 downto 0);
end architecture;
|
gpl-3.0
|
nanomolina/MIPS
|
PIPELINE/fetch.vhd
|
2
|
2208
|
library ieee;
use ieee.std_logic_1164.all;
entity fetch is
port(
jumpM, PcSrcM, clk, reset: in std_logic;
PcBranchM: in std_logic_vector(31 downto 0);
InstrF, PCF, PCPlus4F: out std_logic_vector(31 downto 0));
end entity;
architecture f_arq of fetch is
component mux2
generic (MAX : integer := 32);
port (
d0, d1: in std_logic_vector((MAX-1) downto 0);
s: in std_logic;
y: out std_logic_vector((MAX-1) downto 0));
end component;
component flopr
port (
d: in std_logic_vector(31 downto 0);
rst, clk: in std_logic;
q: out std_logic_vector(31 downto 0));
end component;
component imem
port (
a: in std_logic_vector (5 downto 0);
rd: out std_logic_vector (31 downto 0));
end component;
component adder
port (
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0));
end component;
signal PCNext, PCPlus4F1, PCJump, PC1, PCF_s,
Instrf_s: std_logic_vector(31 downto 0);
signal QUATRO: std_logic_vector(31 downto 0) := x"00000004";
signal IMEMIN: std_logic_vector(5 downto 0);
begin
mux2_1: mux2 port map(
d0 => PCPlus4F1,
d1 => PcBranchM,
s => PCSrcM,
y => PCNext);
mux2_2: mux2 port map(
d0 => PCNext,
d1 => PCJump,
s => jumpM,
y => PC1);
flopr1: flopr port map(
d => PC1,
clk => clk,
rst => reset,
q => PCF_s);
adder1: adder port map(
a => PCF_s,
b => QUATRO,
y => PCPlus4F1);
imem1: imem port map(
a => IMEMIN,
rd => Instrf_s);
PCJump <= PCPlus4F1(31 downto 28) & Instrf_s(25 downto 0) & "00";
IMEMIN <= PCF_s(7 downto 2);
InstrF <= Instrf_s;
PCF <= PCF_s;
PCPlus4F <= PCPlus4F1;
end architecture;
|
gpl-3.0
|
zeruniverse/Single-cycle_CPU
|
ISE project/ipcore_dir/Ins_Mem.vhd
|
1
|
5717
|
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file Ins_Mem.vhd when simulating
-- the core, Ins_Mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY Ins_Mem IS
port (
a: in std_logic_vector(9 downto 0);
spo: out std_logic_vector(31 downto 0));
END Ins_Mem;
ARCHITECTURE Ins_Mem_a OF Ins_Mem IS
-- synthesis translate_off
component wrapped_Ins_Mem
port (
a: in std_logic_vector(9 downto 0);
spo: out std_logic_vector(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_Ins_Mem use entity XilinxCoreLib.dist_mem_gen_v5_1(behavioral)
generic map(
c_has_clk => 0,
c_has_qdpo_clk => 0,
c_has_qdpo_ce => 0,
c_parser_type => 1,
c_has_d => 0,
c_has_spo => 1,
c_read_mif => 1,
c_has_qspo => 0,
c_width => 32,
c_reg_a_d_inputs => 0,
c_has_we => 0,
c_pipeline_stages => 0,
c_has_qdpo_rst => 0,
c_reg_dpra_input => 0,
c_qualify_we => 0,
c_family => "spartan3",
c_sync_enable => 1,
c_depth => 1024,
c_has_qspo_srst => 0,
c_has_qdpo_srst => 0,
c_has_dpra => 0,
c_qce_joined => 0,
c_mem_type => 0,
c_has_i_ce => 0,
c_has_dpo => 0,
c_mem_init_file => "Ins_Mem.mif",
c_default_data => "0",
c_has_spra => 0,
c_has_qspo_ce => 0,
c_addr_width => 10,
c_has_qspo_rst => 0,
c_has_qdpo => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_Ins_Mem
port map (
a => a,
spo => spo);
-- synthesis translate_on
END Ins_Mem_a;
|
gpl-3.0
|
mzakharo/usb-de2-fpga
|
src/isp_inc.vhd
|
1
|
11513
|
-- isp_inc.vhd
-- -----------------------------------------------------------------------
-- Copyright © 2012 Mikhail Zakharov
-- -----------------------------------------------------------------------
--
-- This file is part of "ISP1362 VHDL interface for DE2"
--
-- "ISP1362 VHDL interface for DE2" is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3
--
-- "ISP1362 VHDL interface for DE2" is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with "ISP1362 VHDL interface for DE2". If not, see <http://www.gnu.org/licenses/>.
-- -----------------------------------------------------------------------
-- ISP1362 register definitions and bit field constants
-- -----------------------------------------------------------------------
-- Version : 1.0
-- Date : Sept 2012
-- Author : Mikhail Zakharov
-- Web : http://ca.linkedin.com/in/mzakharo
-- Contact : [email protected]
-- -----------------------------------------------------------------------
-- FUNCTION :
-- VHDL translation of constants, defined in ISP1362 Datasheet, Ch 15
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package isp_inc is
--=-=-=-=-=-COMMANDS-=-=-=-=-=--
constant Wr_DcEndpointConfiguration : std_logic_vector(15 downto 4) := x"002"; --20h = control out
constant Rd_DcEndpointConfiguration : std_logic_vector(15 downto 4) := x"003"; --30h = control out
constant Wr_DcAddress : std_logic_vector(15 downto 0) := x"00B6"; --B6h
constant Rd_DcAddress : std_logic_vector(15 downto 0) := x"00B7"; --B7h
constant Wr_DcMode : std_logic_vector(15 downto 0) := x"00B8"; --B8h
constant Rd_DcMode : std_logic_vector(15 downto 0) := x"00B9"; --B9h
constant Wr_DcHardwareConfiguration : std_logic_vector(15 downto 0) := x"00BA"; --BAh
constant Rd_DcHardwareConfiguration : std_logic_vector(15 downto 0) := x"00BB"; --BBh
constant Wr_DcInterruptEnable : std_logic_vector(15 downto 0) := x"00C2"; --C2h
constant Rd_DcInterruptEnable : std_logic_vector(15 downto 0) := x"00C3"; --C3h
constant Wr_DcDMAConfiguration : std_logic_vector(15 downto 0) := x"00F0"; --F0h
constant Rd_DcDMAConfiguration : std_logic_vector(15 downto 0) := x"00F1"; --F1h
constant Wr_DcDMACounter : std_logic_vector(15 downto 0) := x"00F2"; --F2h
constant Rd_DcDMACounter : std_logic_vector(15 downto 0) := x"00F3"; --F3h
constant Reset : std_logic_vector(15 downto 0) := x"00F6"; --F6h
constant Wr_Buffer : std_logic_vector(15 downto 4) := x"000"; --00h = control out (0 illegal)
constant Rd_Buffer : std_logic_vector(15 downto 4) := x"001"; --10h = control out (1 illegal)
constant Rd_ESR : std_logic_vector(15 downto 4) := x"005"; --50h = control out
constant EPSTS_STALL : std_logic_vector(15 downto 4) := x"004"; --40h = control out
constant EPSTS_UNSTALL : std_logic_vector(15 downto 4) := x"008"; --80h = control out
constant Validate : std_logic_vector(15 downto 4) := x"006"; --60h = control out (0 illegal)
constant ClearBuffer : std_logic_vector(15 downto 4) := x"007"; --70h = control out (1 illegal)
constant Rd_DcEndpointStatusImage : std_logic_vector(15 downto 4) := x"00D"; --D0h = control out
constant AcknowledgeSetup : std_logic_vector(15 downto 0) := x"00F4"; --F4h (must ack setups sec12.3.6)
constant Rd_ErrorCode : std_logic_vector(15 downto 4) := x"00A"; --A0h = control out
constant UnlockDevice : std_logic_vector(15 downto 0) := x"00B0"; --B0h
constant Wr_DcScratchRegister : std_logic_vector(15 downto 0) := x"00B2"; --B2h
constant Rd_DcScratchRegister : std_logic_vector(15 downto 0) := x"00B3"; --B3h
constant Rd_DcFrameNumber : std_logic_vector(15 downto 0) := x"00B4"; --B4h
constant Rd_DcChipID : std_logic_vector(15 downto 0) := x"00B5"; --B5h
constant Rd_DcInterrupt : std_logic_vector(15 downto 0) := x"00C0"; --C0h
--From hal.h
constant EPINDEX4EP0_CONTROL_OUT : std_logic_vector(3 downto 0) := x"0";
constant EPINDEX4EP0_CONTROL_IN : std_logic_vector(3 downto 0) := x"1";
constant EPINDEX4EP01 : std_logic_vector(3 downto 0) := x"2";
constant EPINDEX4EP02 : std_logic_vector(3 downto 0) := x"3";
constant EPINDEX4EP03 : std_logic_vector(3 downto 0) := x"4";
constant EPINDEX4EP04 : std_logic_vector(3 downto 0) := x"5";
constant EPINDEX4EP05 : std_logic_vector(3 downto 0) := x"6";
constant EPINDEX4EP06 : std_logic_vector(3 downto 0) := x"7";
constant EPINDEX4EP07 : std_logic_vector(3 downto 0) := x"8";
constant EPINDEX4EP08 : std_logic_vector(3 downto 0) := x"9";
constant EPINDEX4EP09 : std_logic_vector(3 downto 0) := x"A";
constant EPINDEX4EP0A : std_logic_vector(3 downto 0) := x"B";
constant EPINDEX4EP0B : std_logic_vector(3 downto 0) := x"C";
constant EPINDEX4EP0C : std_logic_vector(3 downto 0) := x"D";
constant EPINDEX4EP0D : std_logic_vector(3 downto 0) := x"E";
constant EPINDEX4EP0E : std_logic_vector(3 downto 0) := x"F";
constant DEVADDR_MASK : std_logic_vector(15 downto 0) := x"007F";
constant DEVADDR_EN : std_logic_vector(15 downto 0) := x"0080";
constant EP_DISABLE : std_logic_vector(15 downto 0) := "--------0-------";
constant EPCNFG_FIFO_EN : std_logic_vector(15 downto 0) := x"0080";
constant EPCNFG_IN_EN : std_logic_vector(15 downto 0) := x"0040";
constant EPCNFG_DBLBUF_EN : std_logic_vector(15 downto 0) := x"0020";
constant EPCNFG_ISO_EN : std_logic_vector(15 downto 0) := x"0010";
constant EPCNFG_ISOSZ_MASK : std_logic_vector(15 downto 0) := x"000F";
constant EPCNFG_NONISOSZ_MASK : std_logic_vector(15 downto 0) := x"0007";
constant EPCNFG_RFB_EN : std_logic_vector(15 downto 0) := x"0008";
constant EPCNFG_NONISOSZ_8 : std_logic_vector(15 downto 0) := x"0000";
constant EPCNFG_NONISOSZ_16 : std_logic_vector(15 downto 0) := x"0001";
constant EPCNFG_NONISOSZ_32 : std_logic_vector(15 downto 0) := x"0002";
constant EPCNFG_NONISOSZ_64 : std_logic_vector(15 downto 0) := x"0003";
constant EPCNFG_ISOSZ_16 : std_logic_vector(15 downto 0) := x"0000";
constant EPCNFG_ISOSZ_32 : std_logic_vector(15 downto 0) := x"0001";
constant EPCNFG_ISOSZ_48 : std_logic_vector(15 downto 0) := x"0002";
constant EPCNFG_ISOSZ_64 : std_logic_vector(15 downto 0) := x"0003";
constant EPCNFG_ISOSZ_96 : std_logic_vector(15 downto 0) := x"0004";
constant EPCNFG_ISOSZ_128 : std_logic_vector(15 downto 0) := x"0005";
constant EPCNFG_ISOSZ_160 : std_logic_vector(15 downto 0) := x"0006";
constant EPCNFG_ISOSZ_192 : std_logic_vector(15 downto 0) := x"0007";
constant EPCNFG_ISOSZ_256 : std_logic_vector(15 downto 0) := x"0008";
constant EPCNFG_ISOSZ_320 : std_logic_vector(15 downto 0) := x"0009";
constant EPCNFG_ISOSZ_384 : std_logic_vector(15 downto 0) := x"000A";
constant EPCNFG_ISOSZ_512 : std_logic_vector(15 downto 0) := x"000B";
constant EPCNFG_ISOSZ_640 : std_logic_vector(15 downto 0) := x"000C";
constant EPCNFG_ISOSZ_768 : std_logic_vector(15 downto 0) := x"000D";
constant EPCNFG_ISOSZ_896 : std_logic_vector(15 downto 0) := x"000E";
constant EPCNFG_ISOSZ_1023 : std_logic_vector(15 downto 0) := x"000F";
--constant EPSTS_STALL : std_logic_vector(15 downto 0) := x"0080";
constant EPSTS_DBF1 : std_logic_vector(15 downto 0) := x"0040";
constant EPSTS_DBF0 : std_logic_vector(15 downto 0) := x"0020";
constant EPSTS_OVWR : std_logic_vector(15 downto 0) := x"0008";
constant EPSTS_SETUP : std_logic_vector(15 downto 0) := x"0004";
constant EPSTS_DBFIDX : std_logic_vector(15 downto 0) := x"0002";
constant ERRCODE_RXTX : std_logic_vector(15 downto 0) := x"0001";
constant ERRCODE_DPID : std_logic_vector(15 downto 0) := x"0040";
constant ERRCODE_OVRLP : std_logic_vector(15 downto 0) := x"0080";
constant ERRCODE_MASK : std_logic_vector(15 downto 0) := x"001E";
constant ERRCODE_OK : std_logic_vector(15 downto 0) := x"0000";
constant ERRCODE_PIDERR : std_logic_vector(15 downto 0) := x"0002";
constant ERRCODE_PIDNEW : std_logic_vector(15 downto 0) := x"0004";
constant ERRCODE_PKTTYP : std_logic_vector(15 downto 0) := x"0006";
constant ERRCODE_TKCRC : std_logic_vector(15 downto 0) := x"0008";
constant ERRCODE_DATACRC : std_logic_vector(15 downto 0) := x"000A";
constant ERRCODE_TIMEOUT : std_logic_vector(15 downto 0) := x"000C";
constant ERRCODE_RSRV0 : std_logic_vector(15 downto 0) := x"000E";
constant ERRCODE_EOP : std_logic_vector(15 downto 0) := x"0010";
constant ERRCODE_NAK : std_logic_vector(15 downto 0) := x"0012";
constant ERRCODE_STALL : std_logic_vector(15 downto 0) := x"0014";
constant ERRCODE_OVRFL : std_logic_vector(15 downto 0) := x"0016";
constant ERRCODE_RSRV1 : std_logic_vector(15 downto 0) := x"0018";
constant ERRCODE_BITSTUFF : std_logic_vector(15 downto 0) := x"001A";
constant ERRCODE_RSRV2 : std_logic_vector(15 downto 0) := x"001C";
constant ERRCODE_DATAPID : std_logic_vector(15 downto 0) := x"001E";
constant LOCK_IOEN : std_logic_vector(15 downto 0) := x"0001";
constant MODE_SOFTCONNECT : std_logic_vector(15 downto 0) := x"0001";
constant MODE_DBG : std_logic_vector(15 downto 0) := x"0004";
constant MODE_INT_EN : std_logic_vector(15 downto 0) := x"0008";
constant MODE_SUSPND : std_logic_vector(15 downto 0) := x"0020";
constant DEVCNFG_INTPOL : std_logic_vector(15 downto 0) := x"0001";
constant DEVCNFG_INTEDGE : std_logic_vector(15 downto 0) := x"0002";
constant DEVCNFG_PWROFF : std_logic_vector(15 downto 0) := x"0004";
constant DEVCNFG_WAKEUPBY_CS : std_logic_vector(15 downto 0) := x"0008";
constant DEVCNFG_EOTPOL : std_logic_vector(15 downto 0) := x"0010";
constant DEVCNFG_DMAACKPOL : std_logic_vector(15 downto 0) := x"0020";
constant DEVCNFG_DMARQPOL : std_logic_vector(15 downto 0) := x"0040";
constant DEVCNFG_DMAACKONLY : std_logic_vector(15 downto 0) := x"0080";
constant DEVCNFG_CLOCKDIV_MASK : std_logic_vector(15 downto 0) := x"0F00";
constant DEVCNFG_CLOCKRUNNING : std_logic_vector(15 downto 0) := x"1000";
constant DEVCNFG_NOLAZYCLOCK : std_logic_vector(15 downto 0) := x"2000";
constant DEVCNFG_EXPULLUP : std_logic_vector(15 downto 0) := x"4000";
constant INTSRC_BUSRESET : std_logic_vector(15 downto 0) := x"0001";
constant INTSRC_RESUME : std_logic_vector(15 downto 0) := x"0002";
constant INTSRC_SUSPEND : std_logic_vector(15 downto 0) := x"0004";
constant INTSRC_EOT : std_logic_vector(15 downto 0) := x"0008";
constant INTSRC_SOF : std_logic_vector(15 downto 0) := x"0010";
constant INTSRC_PSEUDO_SOF : std_logic_vector(15 downto 0) := x"0020";
constant INTSRC_SHORT_PACKET : std_logic_vector(15 downto 0) := x"0040";
constant INTSRC_EP0OUT : std_logic_vector(15 downto 0) := x"0100";
constant INTSRC_EP0IN : std_logic_vector(15 downto 0) := x"0200";
constant INTSRC_EP01 : std_logic_vector(15 downto 0) := x"0400";
constant INTSRC_EP02 : std_logic_vector(15 downto 0) := x"0800";
constant INTSRC_EP03 : std_logic_vector(15 downto 0) := x"1000";
constant INTSRC_EP04 : std_logic_vector(15 downto 0) := x"2000";
constant INTSRC_EP05 : std_logic_vector(15 downto 0) := x"4000";
constant INTSRC_EP06 : std_logic_vector(15 downto 0) := x"8000";
end package;
|
gpl-3.0
|
mzakharo/usb-de2-fpga
|
sim/hal_tb.vhd
|
1
|
2867
|
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
use work.isp_hal.all;
-- Add your library and packages declaration here ...
entity hal_tb is
end hal_tb;
architecture TB_ARCHITECTURE of hal_tb is
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal d : isp_hal_in_t;
signal otg_data : STD_LOGIC_VECTOR(15 downto 0);
-- Observed signals - signals mapped to the output ports of tested entity
signal q : isp_hal_out_t;
--local signals
signal slowclk_en : bit := '1';
signal write_sense :std_logic;
signal write_end_sense : std_logic;
--------------------------------------------------------------
-- clock cycle
constant period : time := 20 ns;
--------------------------------------------------------------
begin
-- Unit Under Test port map
UUT : hal
generic map(3)
port map (
clk => clk,
reset => reset,
otg_data => otg_data,
d => d,
q => q
);
--d.int <= '1'; -- not used in this tb
----------------------------------------------------
-- clock
process
begin
clk <= '0';
wait for period/2;
clk <= '1';
wait for period/2;
end process;
--produces 25MHz clock enable for OTG
p_slowclk_en: process
begin
wait until rising_edge(clk);
slowclk_en <= not(slowclk_en);
end process;
d.slowclk_en <= slowclk_en;
----------------------------------------------------
-- resets
process
begin
reset <= '1';
wait for period;
reset <= '0';
wait;
end process;
----------------------------------------------------
-- read emulation
----------------------------------------------------
process
begin
otg_data <= (others => 'Z');
wait until falling_edge(q.rd_n);
wait for 22 ns;
otg_data <= x"BEAD";
wait until rising_edge(q.cs_n);
wait for 3 ns;
end process;
----------------------------------------------------
-- write emulation
----------------------------------------------------
write_sense <= to_stdulogic(d.drv.cmd(1));
write_end_sense <= to_stdulogic(q.drv.rdy);
process
begin
wait for period;
if (write_sense = '1') then
d.drv.data <= x"FACE";
else
d.drv.data <= x"0000";
end if;
wait until rising_edge(write_end_sense);
wait until rising_edge(clk);
d.drv.data <= x"0000";
wait for period * 4;
end process;
--choose what to do
d.drv.cmd <= otg_rd; -- otg_wr; -- otg_wr_cmd;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_hal of hal_tb is
for TB_ARCHITECTURE
for UUT : hal
use entity work.hal(handler);
end for;
end for;
end TESTBENCH_FOR_hal;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_fadd_32ns_32ns_32_5_full_dsp.vhd
|
7
|
3340
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fadd_32ns_32ns_32_5_full_dsp is
generic (
ID : integer := 0;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fadd_32ns_32ns_32_5_full_dsp is
--------------------- Component ---------------------
component ANN_ap_fadd_3_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fadd_3_full_dsp_32_u : component ANN_ap_fadd_3_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SW_standalone/hdl/design_SW_standalone_wrapper.vhd
|
1
|
6330
|
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Wed Aug 31 22:23:41 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_SW_standalone_wrapper.bd
--Design : design_SW_standalone_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SW_standalone_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 )
);
end design_SW_standalone_wrapper;
architecture STRUCTURE of design_SW_standalone_wrapper is
component design_SW_standalone is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_SW_standalone;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal leds_4bits_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
design_SW_standalone_i: component design_SW_standalone
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
leds_4bits_tri_i(3) => leds_4bits_tri_i_3(3),
leds_4bits_tri_i(2) => leds_4bits_tri_i_2(2),
leds_4bits_tri_i(1) => leds_4bits_tri_i_1(1),
leds_4bits_tri_i(0) => leds_4bits_tri_i_0(0),
leds_4bits_tri_o(3) => leds_4bits_tri_o_3(3),
leds_4bits_tri_o(2) => leds_4bits_tri_o_2(2),
leds_4bits_tri_o(1) => leds_4bits_tri_o_1(1),
leds_4bits_tri_o(0) => leds_4bits_tri_o_0(0),
leds_4bits_tri_t(3) => leds_4bits_tri_t_3(3),
leds_4bits_tri_t(2) => leds_4bits_tri_t_2(2),
leds_4bits_tri_t(1) => leds_4bits_tri_t_1(1),
leds_4bits_tri_t(0) => leds_4bits_tri_t_0(0)
);
leds_4bits_tri_iobuf_0: component IOBUF
port map (
I => leds_4bits_tri_o_0(0),
IO => leds_4bits_tri_io(0),
O => leds_4bits_tri_i_0(0),
T => leds_4bits_tri_t_0(0)
);
leds_4bits_tri_iobuf_1: component IOBUF
port map (
I => leds_4bits_tri_o_1(1),
IO => leds_4bits_tri_io(1),
O => leds_4bits_tri_i_1(1),
T => leds_4bits_tri_t_1(1)
);
leds_4bits_tri_iobuf_2: component IOBUF
port map (
I => leds_4bits_tri_o_2(2),
IO => leds_4bits_tri_io(2),
O => leds_4bits_tri_i_2(2),
T => leds_4bits_tri_t_2(2)
);
leds_4bits_tri_iobuf_3: component IOBUF
port map (
I => leds_4bits_tri_o_3(3),
IO => leds_4bits_tri_io(3),
O => leds_4bits_tri_i_3(3),
T => leds_4bits_tri_t_3(3)
);
end STRUCTURE;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_dadd_3_full_dsp_64/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
|
24
|
96728
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_feedforward_0_0/synth/design_SWandHW_standalone_feedforward_0_0.vhd
|
1
|
12310
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: UC3M:MISEA_Thesis:feedforward:1.4
-- IP Revision: 1609011434
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_SWandHW_standalone_feedforward_0_0 IS
PORT (
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
P_config_TVALID : IN STD_LOGIC;
P_config_TREADY : OUT STD_LOGIC;
P_config_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P_WandB_TVALID : IN STD_LOGIC;
P_WandB_TREADY : OUT STD_LOGIC;
P_WandB_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P_uOut_TVALID : OUT STD_LOGIC;
P_uOut_TREADY : IN STD_LOGIC;
P_uOut_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
P_netIn_TVALID : IN STD_LOGIC;
P_netIn_TREADY : OUT STD_LOGIC;
P_netIn_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P_netOut_TVALID : OUT STD_LOGIC;
P_netOut_TREADY : IN STD_LOGIC;
P_netOut_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_SWandHW_standalone_feedforward_0_0;
ARCHITECTURE design_SWandHW_standalone_feedforward_0_0_arch OF design_SWandHW_standalone_feedforward_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_feedforward_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT feedforward IS
GENERIC (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER
);
PORT (
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
P_config_TVALID : IN STD_LOGIC;
P_config_TREADY : OUT STD_LOGIC;
P_config_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P_WandB_TVALID : IN STD_LOGIC;
P_WandB_TREADY : OUT STD_LOGIC;
P_WandB_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P_uOut_TVALID : OUT STD_LOGIC;
P_uOut_TREADY : IN STD_LOGIC;
P_uOut_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
P_netIn_TVALID : IN STD_LOGIC;
P_netIn_TREADY : OUT STD_LOGIC;
P_netIn_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P_netOut_TVALID : OUT STD_LOGIC;
P_netOut_TREADY : IN STD_LOGIC;
P_netOut_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT feedforward;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_feedforward_0_0_arch: ARCHITECTURE IS "feedforward,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_feedforward_0_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_feedforward_0_0,feedforward,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF P_config_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 P_config TVALID";
ATTRIBUTE X_INTERFACE_INFO OF P_config_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 P_config TREADY";
ATTRIBUTE X_INTERFACE_INFO OF P_config_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 P_config TDATA";
ATTRIBUTE X_INTERFACE_INFO OF P_WandB_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 P_WandB TVALID";
ATTRIBUTE X_INTERFACE_INFO OF P_WandB_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 P_WandB TREADY";
ATTRIBUTE X_INTERFACE_INFO OF P_WandB_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 P_WandB TDATA";
ATTRIBUTE X_INTERFACE_INFO OF P_uOut_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 P_uOut TVALID";
ATTRIBUTE X_INTERFACE_INFO OF P_uOut_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 P_uOut TREADY";
ATTRIBUTE X_INTERFACE_INFO OF P_uOut_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 P_uOut TDATA";
ATTRIBUTE X_INTERFACE_INFO OF P_netIn_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netIn TVALID";
ATTRIBUTE X_INTERFACE_INFO OF P_netIn_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netIn TREADY";
ATTRIBUTE X_INTERFACE_INFO OF P_netIn_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netIn TDATA";
ATTRIBUTE X_INTERFACE_INFO OF P_netOut_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netOut TVALID";
ATTRIBUTE X_INTERFACE_INFO OF P_netOut_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netOut TREADY";
ATTRIBUTE X_INTERFACE_INFO OF P_netOut_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netOut TDATA";
BEGIN
U0 : feedforward
GENERIC MAP (
C_S_AXI_AXILITES_ADDR_WIDTH => 5,
C_S_AXI_AXILITES_DATA_WIDTH => 32
)
PORT MAP (
s_axi_AXILiteS_AWADDR => s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID => s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY => s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_WDATA => s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB => s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_WVALID => s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY => s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_BRESP => s_axi_AXILiteS_BRESP,
s_axi_AXILiteS_BVALID => s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY => s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_ARADDR => s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_ARVALID => s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY => s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_RDATA => s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP => s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_RVALID => s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY => s_axi_AXILiteS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
P_config_TVALID => P_config_TVALID,
P_config_TREADY => P_config_TREADY,
P_config_TDATA => P_config_TDATA,
P_WandB_TVALID => P_WandB_TVALID,
P_WandB_TREADY => P_WandB_TREADY,
P_WandB_TDATA => P_WandB_TDATA,
P_uOut_TVALID => P_uOut_TVALID,
P_uOut_TREADY => P_uOut_TREADY,
P_uOut_TDATA => P_uOut_TDATA,
P_netIn_TVALID => P_netIn_TVALID,
P_netIn_TREADY => P_netIn_TREADY,
P_netIn_TDATA => P_netIn_TDATA,
P_netOut_TVALID => P_netOut_TVALID,
P_netOut_TREADY => P_netOut_TREADY,
P_netOut_TDATA => P_netOut_TDATA
);
END design_SWandHW_standalone_feedforward_0_0_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/bd/design_TEST/hdl/design_TEST.vhd
|
1
|
194848
|
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Thu Sep 01 17:22:48 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_TEST.bd
--Design : design_TEST
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1FMN47O is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1FMN47O;
architecture STRUCTURE of m00_couplers_imp_1FMN47O is
component design_TEST_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_TEST_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= auto_pc_to_m00_couplers_ARID(0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= auto_pc_to_m00_couplers_AWID(0);
M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0);
M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wid(0) <= auto_pc_to_m00_couplers_WID(0);
M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_pc_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(0) <= m00_couplers_to_auto_pc_BID(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(0) <= m00_couplers_to_auto_pc_RID(0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_TEST_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => auto_pc_to_m00_couplers_ARID(0),
m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => auto_pc_to_m00_couplers_AWID(0),
m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0),
m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bid(0) => auto_pc_to_m00_couplers_BID(0),
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(0) => auto_pc_to_m00_couplers_RID(0),
m_axi_rlast => auto_pc_to_m00_couplers_RLAST,
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m00_couplers_WDATA(31 downto 0),
m_axi_wid(0) => auto_pc_to_m00_couplers_WID(0),
m_axi_wlast => auto_pc_to_m00_couplers_WLAST,
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(0) => m00_couplers_to_auto_pc_ARID(0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(0) => m00_couplers_to_auto_pc_AWID(0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(0) => m00_couplers_to_auto_pc_BID(0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(0) => m00_couplers_to_auto_pc_RID(0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_23E6MH is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_23E6MH;
architecture STRUCTURE of m00_couplers_imp_23E6MH is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_169O6FR is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_169O6FR;
architecture STRUCTURE of m01_couplers_imp_169O6FR is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1TCVZ15 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1TCVZ15;
architecture STRUCTURE of s00_couplers_imp_1TCVZ15 is
component design_TEST_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_TEST_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_TEST_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_NVS4CK is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_NVS4CK;
architecture STRUCTURE of s00_couplers_imp_NVS4CK is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s00_couplers_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s00_couplers_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= s00_couplers_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= s00_couplers_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rlast(0) <= s00_couplers_to_s00_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_s00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_s00_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RLAST(0) <= M_AXI_rlast(0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1JZLSPM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s01_couplers_imp_1JZLSPM;
architecture STRUCTURE of s01_couplers_imp_1JZLSPM is
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s01_couplers_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s01_couplers_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= s01_couplers_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= s01_couplers_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= s01_couplers_to_s01_couplers_AWVALID(0);
M_AXI_bready(0) <= s01_couplers_to_s01_couplers_BREADY(0);
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= s01_couplers_to_s01_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s01_couplers_to_s01_couplers_WVALID(0);
S_AXI_awready(0) <= s01_couplers_to_s01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s01_couplers_to_s01_couplers_BVALID(0);
S_AXI_wready(0) <= s01_couplers_to_s01_couplers_WREADY(0);
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_s01_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_s01_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWREADY(0) <= M_AXI_awready(0);
s01_couplers_to_s01_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_s01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s01_couplers_to_s01_couplers_BREADY(0) <= S_AXI_bready(0);
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID(0) <= M_AXI_bvalid(0);
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WLAST(0) <= S_AXI_wlast(0);
s01_couplers_to_s01_couplers_WREADY(0) <= M_AXI_wready(0);
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_TEST_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end design_TEST_axi_mem_intercon_0;
architecture STRUCTURE of design_TEST_axi_mem_intercon_0 is
component design_TEST_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_TEST_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0);
M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0);
M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
M00_AXI_wid(0) <= m00_couplers_to_axi_mem_intercon_WID(0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready(0) <= axi_mem_intercon_to_s00_couplers_ARREADY(0);
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast(0) <= axi_mem_intercon_to_s00_couplers_RLAST(0);
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= axi_mem_intercon_to_s00_couplers_RVALID(0);
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1(0) <= S01_ARESETN(0);
S01_AXI_awready(0) <= axi_mem_intercon_to_s01_couplers_AWREADY(0);
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid(0) <= axi_mem_intercon_to_s01_couplers_BVALID(0);
S01_AXI_wready(0) <= axi_mem_intercon_to_s01_couplers_WREADY(0);
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net(0) <= ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
axi_mem_intercon_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID(0) <= S01_AXI_awvalid(0);
axi_mem_intercon_to_s01_couplers_BREADY(0) <= S01_AXI_bready(0);
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST(0) <= S01_AXI_wlast(0);
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID(0) <= S01_AXI_wvalid(0);
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1FMN47O
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0),
M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0),
M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
M_AXI_wid(0) => m00_couplers_to_axi_mem_intercon_WID(0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(0) => xbar_to_m00_couplers_BID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => xbar_to_m00_couplers_RID(0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_NVS4CK
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rlast(0) => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => axi_mem_intercon_to_s00_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => axi_mem_intercon_to_s00_couplers_ARVALID(0),
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast(0) => axi_mem_intercon_to_s00_couplers_RLAST(0),
S_AXI_rready(0) => axi_mem_intercon_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_mem_intercon_to_s00_couplers_RVALID(0)
);
s01_couplers: entity work.s01_couplers_imp_1JZLSPM
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready(0) => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => s01_couplers_to_xbar_AWVALID(0),
M_AXI_bready(0) => s01_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid(0) => s01_couplers_to_xbar_BVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast(0) => s01_couplers_to_xbar_WLAST(0),
M_AXI_wready(0) => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s01_couplers_to_xbar_WVALID(0),
S_ACLK => S01_ACLK_1,
S_ARESETN(0) => S01_ARESETN_1(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => axi_mem_intercon_to_s01_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid(0) => axi_mem_intercon_to_s01_couplers_AWVALID(0),
S_AXI_bready(0) => axi_mem_intercon_to_s01_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => axi_mem_intercon_to_s01_couplers_BVALID(0),
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast(0) => axi_mem_intercon_to_s01_couplers_WLAST(0),
S_AXI_wready(0) => axi_mem_intercon_to_s01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => axi_mem_intercon_to_s01_couplers_WVALID(0)
);
xbar: component design_TEST_xbar_1
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net(0),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => xbar_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => xbar_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(0) => xbar_to_m00_couplers_BID(0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(0) => xbar_to_m00_couplers_RID(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(3 downto 2) => B"00",
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(7 downto 4) => B"0000",
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(1 downto 0) => B"00",
s_axi_arlen(15 downto 8) => B"00000000",
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(1 downto 0) => B"00",
s_axi_arprot(5 downto 3) => B"000",
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(7 downto 0) => B"00000000",
s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(5 downto 3) => B"000",
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(1) => '0',
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(1 downto 0) => B"00",
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1 downto 0) => B"00",
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(7 downto 0) => B"00000000",
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0),
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID(0),
s_axi_awvalid(0) => '0',
s_axi_bid(1 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(1 downto 0),
s_axi_bready(1) => s01_couplers_to_xbar_BREADY(0),
s_axi_bready(0) => '0',
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0),
s_axi_rdata(63 downto 32) => NLW_xbar_s_axi_rdata_UNCONNECTED(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rid(1 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(1 downto 0),
s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(1) => '0',
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST(0),
s_axi_wlast(0) => '1',
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0),
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => B"1111",
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID(0),
s_axi_wvalid(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_TEST_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_TEST_processing_system7_0_axi_periph_0;
architecture STRUCTURE of design_TEST_processing_system7_0_axi_periph_0 is
component design_TEST_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component design_TEST_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_WVALID(0);
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_23E6MH
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_169O6FR
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
s00_couplers: entity work.s00_couplers_imp_1TCVZ15
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component design_TEST_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(5 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(5 downto 0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(5 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(5 downto 0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(7 downto 0) => NLW_xbar_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_TEST is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_TEST : entity is "design_TEST,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_TEST,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=16,numReposBlks=8,numNonXlnxBlks=0,numHierBlks=8,maxHierDepth=0,da_axi4_cnt=4,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_TEST : entity is "design_TEST.hwdef";
end design_TEST;
architecture STRUCTURE of design_TEST is
component design_TEST_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_TEST_processing_system7_0_0;
component design_TEST_axi_dma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component design_TEST_axi_dma_0_0;
component design_TEST_axi_dma_1_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component design_TEST_axi_dma_1_0;
component design_TEST_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_TEST_rst_processing_system7_0_100M_0;
signal axi_dma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_dma_0_mm2s_introut_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_1_s2mm_introut_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_dma_0: component design_TEST_axi_dma_0_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_0_M_AXI_MM2S_ARREADY(0),
m_axi_mm2s_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_0_M_AXI_MM2S_RLAST(0),
m_axi_mm2s_rready => axi_dma_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_0_M_AXI_MM2S_RVALID(0),
m_axis_mm2s_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID,
mm2s_introut => NLW_axi_dma_0_mm2s_introut_UNCONNECTED,
mm2s_prmry_reset_out_n => NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_lite_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
axi_dma_1: component design_TEST_axi_dma_1_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_1_M_AXI_S2MM_AWREADY(0),
m_axi_s2mm_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_1_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_1_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_1_M_AXI_S2MM_BVALID(0),
m_axi_s2mm_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_1_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_1_M_AXI_S2MM_WREADY(0),
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_1_M_AXI_S2MM_WVALID,
s2mm_introut => NLW_axi_dma_1_s2mm_introut_UNCONNECTED,
s2mm_prmry_reset_out_n => NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_lite_bready => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
s_axis_s2mm_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
s_axis_s2mm_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
s_axis_s2mm_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
s_axis_s2mm_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID
);
axi_mem_intercon: entity work.design_TEST_axi_mem_intercon_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
M00_AXI_wid(0) => axi_mem_intercon_M00_AXI_WID(0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready(0) => axi_dma_0_M_AXI_MM2S_ARREADY(0),
S00_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid(0) => axi_dma_0_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
S00_AXI_rlast(0) => axi_dma_0_M_AXI_MM2S_RLAST(0),
S00_AXI_rready(0) => axi_dma_0_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid(0) => axi_dma_0_M_AXI_MM2S_RVALID(0),
S01_ACLK => processing_system7_0_FCLK_CLK0,
S01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S01_AXI_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
S01_AXI_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
S01_AXI_awready(0) => axi_dma_1_M_AXI_S2MM_AWREADY(0),
S01_AXI_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
S01_AXI_awvalid(0) => axi_dma_1_M_AXI_S2MM_AWVALID,
S01_AXI_bready(0) => axi_dma_1_M_AXI_S2MM_BREADY,
S01_AXI_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
S01_AXI_bvalid(0) => axi_dma_1_M_AXI_S2MM_BVALID(0),
S01_AXI_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
S01_AXI_wlast(0) => axi_dma_1_M_AXI_S2MM_WLAST,
S01_AXI_wready(0) => axi_dma_1_M_AXI_S2MM_WREADY(0),
S01_AXI_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
S01_AXI_wvalid(0) => axi_dma_1_M_AXI_S2MM_WVALID
);
processing_system7_0: component design_TEST_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(0) => '0',
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 1) => B"00000",
S_AXI_HP0_ARID(0) => axi_mem_intercon_M00_AXI_ARID(0),
S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 1) => B"00000",
S_AXI_HP0_AWID(0) => axi_mem_intercon_M00_AXI_AWID(0),
S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
S_AXI_HP0_WID(5 downto 1) => B"00000",
S_AXI_HP0_WID(0) => axi_mem_intercon_M00_AXI_WID(0),
S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.design_TEST_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready(0) => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready(0) => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wvalid(0) => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component design_TEST_rst_processing_system7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fmul_2_max_dsp_32/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd
|
24
|
10812
|
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd
|
24
|
10812
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect key_block
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`protect key_block
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`protect key_block
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`protect key_block
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`protect data_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_fifo.vhd
|
4
|
24997
|
-------------------------------------------------------------------------------
-- axi_datamover_fifo.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_afifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 )))
or
(C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 0 )
generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_datamover_v5_1_9.axi_datamover_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Ainit_Rd_clk => fifo_async_rd_reset ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ip/design_SWandHW_standalone_v2_axi_gpio_0_0/synth/design_SWandHW_standalone_v2_axi_gpio_0_0.vhd
|
1
|
9881
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_9;
USE axi_gpio_v2_0_9.axi_gpio;
ENTITY design_SWandHW_standalone_v2_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_SWandHW_standalone_v2_axi_gpio_0_0;
ARCHITECTURE design_SWandHW_standalone_v2_axi_gpio_0_0_arch OF design_SWandHW_standalone_v2_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_v2_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_v2_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_v2_axi_gpio_0_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_v2_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_v2_axi_gpio_0_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_v2_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=1,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_SWandHW_standalone_v2_axi_gpio_0_0_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fdiv_14_no_dsp_32/synth/ANN_ap_fdiv_14_no_dsp_32.vhd
|
6
|
12691
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fdiv_14_no_dsp_32;
ARCHITECTURE ANN_ap_fdiv_14_no_dsp_32_arch OF ANN_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fdiv_14_no_dsp_32_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_slice.vhd
|
19
|
4781
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/address_decoder.vhd
|
8
|
22452
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_3.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_3.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fcmp_0_no_dsp_32/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd
|
24
|
9340
|
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0.vhd
|
24
|
9340
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_1/hdl/vhdl/ANN_ST_WandB.vhd
|
7
|
3065
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ANN_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 13;
mem_size : integer := 6560
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of ANN_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity ANN_ST_WandB is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 6560;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of ANN_ST_WandB is
component ANN_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
ANN_ST_WandB_ram_U : component ANN_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/vhdl/feedforward_p_uOut.vhd
|
4
|
4111
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_p_uOut_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 8;
mem_size : integer := 140
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_p_uOut_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_p_uOut is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 140;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_p_uOut is
component feedforward_p_uOut_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sts_strm.vhd
|
4
|
38431
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_strm.vhd.vhd
-- Description: This entity is the AXI Status Stream Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_srl_fifo_v1_0_2;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_strm is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_ENABLE_SKID : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
s2mm_stop : in std_logic ; --
--
s2mm_rxlength_valid : out std_logic ; --
s2mm_rxlength_clr : in std_logic ; --
s2mm_rxlength : out std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) ; --
--
stsstrm_fifo_rden : in std_logic ; --
stsstrm_fifo_empty : out std_logic ; --
stsstrm_fifo_dout : out std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_sts_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status Stream FIFO Depth
constant STSSTRM_FIFO_DEPTH : integer := 16;
-- Status Stream FIFO Data Count Width (Unsused)
constant STSSTRM_FIFO_CNT_WIDTH : integer := clog2(STSSTRM_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_full : std_logic := '0';
signal fifo_din : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_sinit : std_logic := '0';
signal rxlength_cdc_from : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_valid_cdc_from : std_logic := '0';
signal rxlength_valid_trdy : std_logic := '0';
--signal sts_tvalid_re : std_logic := '0';-- CR565502
--signal sts_tvalid_d1 : std_logic := '0';-- CR565502
signal sts_tvalid : std_logic := '0';
signal sts_tready : std_logic := '0';
signal sts_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal sts_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sts_tlast : std_logic := '0';
signal m_tvalid : std_logic := '0';
signal m_tready : std_logic := '0';
signal m_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_tlast : std_logic := '0';
signal tag_stripped : std_logic := '0';
signal mask_tag_write : std_logic := '0';
--signal mask_tag_hold : std_logic := '0';-- CR565502
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal s2mm_stop_d1 : std_logic := '0';
signal s2mm_stop_re : std_logic := '0';
signal sts_rden : std_logic := '0';
signal follower_empty : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal fifo_out : std_logic_vector (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
begin
-- Generate Synchronous FIFO
-- I_STSSTRM_FIFO : entity lib_srl_fifo_v1_0_2.sync_fifo_fg
-- generic map (
-- C_FAMILY => C_FAMILY ,
-- C_MEMORY_TYPE => USE_LOGIC_FIFOS,
-- C_WRITE_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
-- C_WRITE_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_READ_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
-- C_READ_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_PORTS_DIFFER => 0,
-- C_HAS_DCOUNT => 1, --req for proper fifo operation
-- C_DCOUNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH,
-- C_HAS_ALMOST_FULL => 0,
-- C_HAS_RD_ACK => 0,
-- C_HAS_RD_ERR => 0,
-- C_HAS_WR_ACK => 0,
-- C_HAS_WR_ERR => 0,
-- C_RD_ACK_LOW => 0,
-- C_RD_ERR_LOW => 0,
-- C_WR_ACK_LOW => 0,
-- C_WR_ERR_LOW => 0,
-- C_PRELOAD_REGS => 1,-- 1 = first word fall through
-- C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- -- C_USE_EMBEDDED_REG => 1 -- 0 ;
-- )
-- port map (
--
-- Clk => m_axi_sg_aclk ,
-- Sinit => fifo_sinit ,
-- Din => fifo_din ,
-- Wr_en => fifo_wren ,
-- Rd_en => stsstrm_fifo_rden ,
-- Dout => stsstrm_fifo_dout ,
-- Full => fifo_full ,
-- Empty => stsstrm_fifo_empty ,
-- Almost_full => open ,
-- Data_count => open ,
-- Rd_ack => open ,
-- Rd_err => open ,
-- Wr_ack => open ,
-- Wr_err => open
--
-- );
I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map (
Clk => m_axi_sg_aclk ,
Reset => fifo_sinit ,
FIFO_Write => fifo_wren ,
Data_In => fifo_din ,
FIFO_Read => sts_rden, --sts_queue_rden ,
Data_Out => fifo_out, --sts_queue_dout ,
FIFO_Empty => fifo_empty, --sts_queue_empty ,
FIFO_Full => fifo_full ,
Addr => open
);
sts_rden <= (not fifo_empty) and follower_empty;
stsstrm_fifo_empty <= follower_empty;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (fifo_sinit = '1' or stsstrm_fifo_rden = '1') then
follower_empty <= '1';
elsif (sts_rden = '1') then
follower_empty <= '0';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (fifo_sinit = '1') then
stsstrm_fifo_dout <= (others => '0');
elsif (sts_rden = '1') then
stsstrm_fifo_dout <= fifo_out;
end if;
end if;
end process;
fifo_sinit <= not m_axi_sg_aresetn;
fifo_din <= sts_tlast & sts_tdata;
fifo_wren <= sts_tvalid and not fifo_full and not rxlength_valid_cdc_from and not mask_tag_write;
sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_cdc_from;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- -- Create register delay of status tvalid in order to create a
-- -- rising edge pulse. note xx_re signal will hold at 1 if
-- -- fifo full on rising edge of tvalid.
-- REG_TVALID : process(axi_prmry_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- sts_tvalid_d1 <= '0';
-- elsif(fifo_full = '0')then
-- sts_tvalid_d1 <= sts_tvalid;
-- end if;
-- end if;
-- end process REG_TVALID;
--
-- -- rising edge on tvalid used to gate off status tag from being
-- -- writen into fifo.
-- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1;
REG_TAG_STRIPPED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tag_stripped <= '0';
-- Reset on write of last word
elsif(fifo_wren = '1' and sts_tlast = '1')then
tag_stripped <= '0';
-- Set on beginning of new status stream
elsif(sts_tready = '1' and sts_tvalid = '1')then
tag_stripped <= '1';
end if;
end if;
end process REG_TAG_STRIPPED;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- REG_MASK_TAG : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- mask_tag_hold <= '0';
-- elsif((sts_tvalid_re = '1' and tag_stripped = '0')
-- or (fifo_wren = '1' and sts_tlast = '1'))then
-- mask_tag_hold <= '1';
-- elsif(tag_stripped = '1')then
-- mask_tag_hold <= '0';
-- end if;
-- end if;
-- end process;
--
-- -- Mask TAG if not already masked and rising edge of tvalid
-- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold);
mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid;
-- Generate logic to capture receive length when Use Receive Length is
-- enabled
GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-- Register receive length on assertion of last and valid
-- Mark rxlength as valid for higher processes
REG_RXLENGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then
rxlength_cdc_from <= (others => '0');
rxlength_valid_cdc_from <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0);
rxlength_valid_cdc_from <= '1';
end if;
end if;
end process REG_RXLENGTH;
s2mm_rxlength_valid <= rxlength_valid_cdc_from;
s2mm_rxlength <= rxlength_cdc_from;
end generate GEN_STS_APP_LENGTH;
-- Do NOT generate logic to capture receive length when option disabled
GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
end generate GEN_NO_STS_APP_LENGTH;
-- register stop to create re pulse
REG_STOP : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
s2mm_stop_d1 <= '0';
else
s2mm_stop_d1 <= s2mm_stop;
end if;
end if;
end process REG_STOP;
s2mm_stop_re <= s2mm_stop and not s2mm_stop_d1;
skid_rst <= not m_axi_sg_aresetn;
ENABLE_SKID : if C_ENABLE_SKID = 1 generate
begin
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
STS_SKID_BUF_I : entity axi_dma_v7_1_8.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => s2mm_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_sts_tvalid ,
S_READY => s_axis_s2mm_sts_tready ,
S_Data => s_axis_s2mm_sts_tdata ,
S_STRB => s_axis_s2mm_sts_tkeep ,
S_Last => s_axis_s2mm_sts_tlast ,
-- Master Side (Stream Data Output
M_VALID => sts_tvalid ,
M_READY => sts_tready ,
M_Data => sts_tdata ,
M_STRB => sts_tkeep ,
M_Last => sts_tlast
);
end generate ENABLE_SKID;
DISABLE_SKID : if C_ENABLE_SKID = 0 generate
begin
sts_tvalid <= s_axis_s2mm_sts_tvalid;
s_axis_s2mm_sts_tready <= sts_tready;
sts_tdata <= s_axis_s2mm_sts_tdata;
sts_tkeep <= s_axis_s2mm_sts_tkeep;
sts_tlast <= s_axis_s2mm_sts_tlast;
end generate DISABLE_SKID;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal s2mm_stop_reg : std_logic := '0'; -- CR605883
signal p_s2mm_stop_d1_cdc_tig : std_logic := '0';
signal p_s2mm_stop_d2 : std_logic := '0';
signal p_s2mm_stop_d3 : std_logic := '0';
signal p_s2mm_stop_re : std_logic := '0';
--ATTRIBUTE async_reg OF p_s2mm_stop_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_s2mm_stop_d2 : SIGNAL IS "true";
begin
-- Generate Asynchronous FIFO
I_STSSTRM_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1 ,
-- C_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_CNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH ,
C_DEPTH => 15 ,
C_CNT_WIDTH => 4 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_sinit ,
AFIFO_Wr_clk => axi_prmry_aclk ,
AFIFO_Wr_en => fifo_wren ,
AFIFO_Din => fifo_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => stsstrm_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => stsstrm_fifo_dout ,
AFIFO_Full => fifo_full ,
AFIFO_Empty => stsstrm_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
fifo_sinit <= not p_reset_n;
fifo_din <= sts_tlast & sts_tdata;
fifo_wren <= sts_tvalid -- valid data
and not fifo_full -- fifo has room
and not rxlength_valid_trdy --rxlength_valid_cdc_from -- not holding a valid length
and not mask_tag_write; -- not masking off tag word
sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_trdy; --rxlength_valid_cdc_from;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- -- Create register delay of status tvalid in order to create a
-- -- rising edge pulse. note xx_re signal will hold at 1 if
-- -- fifo full on rising edge of tvalid.
-- REG_TVALID : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- sts_tvalid_d1 <= '0';
-- elsif(fifo_full = '0')then
-- sts_tvalid_d1 <= sts_tvalid;
-- end if;
-- end if;
-- end process REG_TVALID;
-- -- rising edge on tvalid used to gate off status tag from being
-- -- writen into fifo.
-- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1;
REG_TAG_STRIPPED : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
tag_stripped <= '0';
-- Reset on write of last word
elsif(fifo_wren = '1' and sts_tlast = '1')then
tag_stripped <= '0';
-- Set on beginning of new status stream
elsif(sts_tready = '1' and sts_tvalid = '1')then
tag_stripped <= '1';
end if;
end if;
end process REG_TAG_STRIPPED;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- REG_MASK_TAG : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- mask_tag_hold <= '0';
-- elsif(tag_stripped = '1')then
-- mask_tag_hold <= '0';
--
-- elsif(sts_tvalid_re = '1'
-- or (fifo_wren = '1' and sts_tlast = '1'))then
-- mask_tag_hold <= '1';
-- end if;
-- end if;
-- end process;
--
-- -- Mask TAG if not already masked and rising edge of tvalid
-- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold);
mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid;
-- Generate logic to capture receive length when Use Receive Length is
-- enabled
GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
signal rxlength_clr_d1_cdc_tig : std_logic := '0';
signal rxlength_clr_d2 : std_logic := '0';
signal rxlength_d1_cdc_to : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_d2 : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_valid_d1_cdc_to : std_logic := '0';
signal rxlength_valid_d2_cdc_from : std_logic := '0';
signal rxlength_valid_d3 : std_logic := '0';
signal rxlength_valid_d4 : std_logic := '0';
signal rxlength_valid_d1_back_cdc_to, rxlength_valid_d2_back : std_logic := '0';
ATTRIBUTE async_reg : STRING;
--ATTRIBUTE async_reg OF rxlength_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d1_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d2_back : SIGNAL IS "true";
begin
-- Double register from secondary clock domain to primary
S2P_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_rxlength_clr,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => rxlength_clr_d2,
scndry_vect_out => open
);
-- S2P_CLK_CROSS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(p_reset_n = '0')then
-- rxlength_clr_d1_cdc_tig <= '0';
-- rxlength_clr_d2 <= '0';
-- else
-- rxlength_clr_d1_cdc_tig <= s2mm_rxlength_clr;
-- rxlength_clr_d2 <= rxlength_clr_d1_cdc_tig;
-- end if;
-- end if;
-- end process S2P_CLK_CROSS;
-- Register receive length on assertion of last and valid
-- Mark rxlength as valid for higher processes
TRDY_RXLENGTH : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or rxlength_clr_d2 = '1')then
rxlength_valid_trdy <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_valid_trdy <= '1';
end if;
end if;
end process TRDY_RXLENGTH;
REG_RXLENGTH : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then
rxlength_cdc_from <= (others => '0');
rxlength_valid_cdc_from <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0);
rxlength_valid_cdc_from <= '1';
elsif (rxlength_valid_d2_back = '1') then
rxlength_valid_cdc_from <= '0';
end if;
end if;
end process REG_RXLENGTH;
SYNC_RXLENGTH : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => rxlength_valid_d2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => rxlength_valid_d2_back,
scndry_vect_out => open
);
-- SYNC_RXLENGTH : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then
--
-- rxlength_valid_d1_back_cdc_to <= '0';
-- rxlength_valid_d2_back <= '0';
-- else
-- rxlength_valid_d1_back_cdc_to <= rxlength_valid_d2_cdc_from;
-- rxlength_valid_d2_back <= rxlength_valid_d1_back_cdc_to;
--
-- end if;
-- end if;
-- end process SYNC_RXLENGTH;
-- Double register from primary clock domain to secondary
P2S_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => rxlength_valid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => rxlength_valid_d2_cdc_from,
scndry_vect_out => open
);
P2S_CLK_CROSS2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_SG_LENGTH_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => rxlength_cdc_from,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => rxlength_d2
);
P2S_CLK_CROSS1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0') then -- or s2mm_rxlength_clr = '1') then
-- rxlength_d1_cdc_to <= (others => '0');
-- rxlength_d2 <= (others => '0');
-- rxlength_valid_d1_cdc_to <= '0';
-- rxlength_valid_d2_cdc_from <= '0';
rxlength_valid_d3 <= '0';
else
-- rxlength_d1_cdc_to <= rxlength_cdc_from;
-- rxlength_d2 <= rxlength_d1_cdc_to;
-- rxlength_valid_d1_cdc_to <= rxlength_valid_cdc_from;
-- rxlength_valid_d2_cdc_from <= rxlength_valid_d1_cdc_to;
rxlength_valid_d3 <= rxlength_valid_d2_cdc_from;
end if;
end if;
end process P2S_CLK_CROSS1;
process (m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then
rxlength_valid_d4 <= '0';
elsif (rxlength_valid_d3 = '1' and rxlength_valid_d2_cdc_from = '0') then
rxlength_valid_d4 <= '1';
end if;
end if;
end process;
s2mm_rxlength <= rxlength_d2;
-- s2mm_rxlength_valid <= rxlength_valid_d2;
s2mm_rxlength_valid <= rxlength_valid_d4;
end generate GEN_STS_APP_LENGTH;
-- Do NOT generate logic to capture receive length when option disabled
GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
end generate GEN_NO_STS_APP_LENGTH;
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop_reg <= '0';
else
s2mm_stop_reg <= s2mm_stop;
end if;
end if;
end process REG_STOP;
-- double register s2mm error into primary clock domain
REG_ERR2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_s2mm_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_s2mm_stop_d1_cdc_tig <= '0';
-- p_s2mm_stop_d2 <= '0';
p_s2mm_stop_d3 <= '0';
else
--p_s2mm_stop_d1_cdc_tig <= s2mm_stop; -- CR605883
-- p_s2mm_stop_d1_cdc_tig <= s2mm_stop_reg;
-- p_s2mm_stop_d2 <= p_s2mm_stop_d1_cdc_tig;
p_s2mm_stop_d3 <= p_s2mm_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY1;
p_s2mm_stop_re <= p_s2mm_stop_d2 and not p_s2mm_stop_d3;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
STS_SKID_BUF_I : entity axi_dma_v7_1_8.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_s2mm_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_sts_tvalid ,
S_READY => s_axis_s2mm_sts_tready ,
S_Data => s_axis_s2mm_sts_tdata ,
S_STRB => s_axis_s2mm_sts_tkeep ,
S_Last => s_axis_s2mm_sts_tlast ,
-- Master Side (Stream Data Output
M_VALID => sts_tvalid ,
M_READY => sts_tready ,
M_Data => sts_tdata ,
M_STRB => sts_tkeep ,
M_Last => sts_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/hdl/ip/ANN_ap_fptrunc_0_no_dsp_64.vhd
|
6
|
12165
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE ANN_ap_fptrunc_0_no_dsp_64_arch OF ANN_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "ANN_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "ANN_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fptrunc_0_no_dsp_64_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_dadd_3_full_dsp_64.vhd
|
6
|
12700
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_dadd_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_dadd_3_full_dsp_64;
ARCHITECTURE ANN_ap_dadd_3_full_dsp_64_arch OF ANN_ap_dadd_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_dadd_3_full_dsp_64_arch : ARCHITECTURE IS "ANN_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "ANN_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_dadd_3_full_dsp_64_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/ip/ANN_ap_dadd_3_full_dsp_64.vhd
|
6
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12700
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-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_dadd_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_dadd_3_full_dsp_64;
ARCHITECTURE ANN_ap_dadd_3_full_dsp_64_arch OF ANN_ap_dadd_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_dadd_3_full_dsp_64_arch : ARCHITECTURE IS "ANN_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "ANN_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_dadd_3_full_dsp_64_arch;
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gpl-3.0
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pemsac/ANN_project
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ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fmul_2_max_dsp_32/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd
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24
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10163
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fcmp_0_no_dsp_32/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd
|
24
|
10163
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5392)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_dexp_16_full_dsp_64/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd
|
24
|
10163
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5392)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/xbip_dsp48_multadd_v3_0/hdl/xbip_dsp48_multadd_v3_0.vhd
|
24
|
10163
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_dadd_3_full_dsp_64.vhd
|
6
|
12788
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_dadd_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_dadd_3_full_dsp_64;
ARCHITECTURE feedforward_ap_dadd_3_full_dsp_64_arch OF feedforward_ap_dadd_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_dadd_3_full_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_dadd_3_full_dsp_64_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/ip/feedforward_ap_dadd_3_full_dsp_64.vhd
|
6
|
12788
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_dadd_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_dadd_3_full_dsp_64;
ARCHITECTURE feedforward_ap_dadd_3_full_dsp_64_arch OF feedforward_ap_dadd_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_dadd_3_full_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_dadd_3_full_dsp_64_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_fmul_32ns_32ns_32_4_max_dsp.vhd
|
7
|
3335
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fmul_32ns_32ns_32_4_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 4;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fmul_32ns_32ns_32_4_max_dsp is
--------------------- Component ---------------------
component ANN_ap_fmul_2_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fmul_2_max_dsp_32_u : component ANN_ap_fmul_2_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/vhdl/feedforward_AXILiteS_s_axi.vhd
|
3
|
12421
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
P_mode :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity feedforward_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of P_mode
-- bit 31~0 - P_mode[31:0] (Read/Write)
-- 0x14 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of feedforward_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_P_MODE_DATA_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_CTRL : INTEGER := 16#14#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_P_mode : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_P_MODE_DATA_0 =>
rdata_data <= RESIZE(int_P_mode(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode <= STD_LOGIC_VECTOR(int_P_mode);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_DATA_0) then
int_P_mode(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_mode(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/rd_pe_ss.vhd
|
9
|
28156
|
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`protect end_protected
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/Cx_Reconf/RTL/Cx_Reconf_pseudo_with_checkers_top.vhd
|
3
|
7867
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_with_checkers_top is
port ( reconfig_cx: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Temp_Cx: in std_logic_vector(3 downto 0);
Faulty_C_N: in std_logic;
Faulty_C_E: in std_logic;
Faulty_C_W: in std_logic;
Faulty_C_S: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Cx_in_out: out std_logic_vector(3 downto 0);
reconfig_cx_in_out: out std_logic;
Temp_Cx_in_out: out std_logic_vector(3 downto 0);
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end Cx_Reconf_pseudo_with_checkers_top;
architecture behavior of Cx_Reconf_pseudo_with_checkers_top is
component Cx_Reconf_pseudo is
port ( reconfig_cx: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Temp_Cx: in std_logic_vector(3 downto 0);
Faulty_C_N: in std_logic;
Faulty_C_E: in std_logic;
Faulty_C_W: in std_logic;
Faulty_C_S: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Cx_in: out std_logic_vector(3 downto 0);
reconfig_cx_in: out std_logic;
Temp_Cx_in: out std_logic_vector(3 downto 0)
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: out std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end component;
signal Cx_in_sig: std_logic_vector (3 downto 0);
signal reconfig_cx_in_sig: std_logic;
signal Temp_Cx_in_sig: std_logic_vector(3 downto 0);
begin
Cx_in_out <= Cx_in_sig;
reconfig_cx_in_out <= reconfig_cx_in_sig;
Temp_Cx_in_out <= Temp_Cx_in_sig;
-- Cx Reconfiguration module instantiation
Cx_Reconf: Cx_Reconf_pseudo port map (
reconfig_cx => reconfig_cx,
flit_type => flit_type,
empty => empty,
grants => grants,
Temp_Cx => Temp_Cx,
Faulty_C_N => Faulty_C_N,
Faulty_C_E => Faulty_C_E,
Faulty_C_W => Faulty_C_W,
Faulty_C_S => Faulty_C_S,
Cx => Cx,
Cx_in => Cx_in_sig,
reconfig_cx_in => reconfig_cx_in_sig,
Temp_Cx_in => Temp_Cx_in_sig
);
-- Cx Reconfiguration module checkers instantiation
CHECKERS: Cx_Reconf_pseudo_checkers port map (
reconfig_cx => reconfig_cx,
flit_type => flit_type,
empty => empty,
grants => grants,
Cx_in => Cx_in_sig,
Temp_Cx => Temp_Cx,
reconfig_cx_in => reconfig_cx_in_sig,
Cx => Cx,
Faulty_C_N => Faulty_C_N,
Faulty_C_E => Faulty_C_E,
Faulty_C_W => Faulty_C_W,
Faulty_C_S => Faulty_C_S,
Temp_Cx_in => Temp_Cx_in_sig,
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal
);
end behavior;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/mlite_cpu.vhd
|
12
|
13651
|
---------------------------------------------------------------------
-- TITLE: Plasma CPU core
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_cpu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS
-- Technologies. MIPS Technologies does not endorse and is not
-- associated with this project.
-- DESCRIPTION:
-- Top level VHDL document that ties the nine other entities together.
--
-- Executes all MIPS I(tm) opcodes but exceptions and non-aligned
-- memory accesses. Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
--
-- The CPU is implemented as a two or three stage pipeline.
-- An add instruction would take the following steps (see cpu.gif):
-- Stage #0:
-- 1. The "pc_next" entity passes the program counter (PC) to the
-- "mem_ctrl" entity which fetches the opcode from memory.
-- Stage #1:
-- 2. The memory returns the opcode.
-- Stage #2:
-- 3. "Mem_ctrl" passes the opcode to the "control" entity.
-- 4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
-- and sends control signals to the other entities.
-- 5. Based on the rs_index and rt_index control signals, "reg_bank"
-- sends the 32-bit reg_source and reg_target to "bus_mux".
-- 6. Based on the a_source and b_source control signals, "bus_mux"
-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
-- Stage #3 (part of stage #2 if using two stage pipeline):
-- 7. Based on the alu_func control signals, "alu" adds the values
-- from a_bus and b_bus and places the result on c_bus.
-- 8. Based on the c_source control signals, "bus_bux" multiplexes
-- c_bus onto reg_dest.
-- 9. Based on the rd_index control signal, "reg_bank" saves
-- reg_dest into the correct register.
-- Stage #3b:
-- 10. Read or write memory if needed.
--
-- All signals are active high.
-- Here are the signals for writing a character to address 0xffff
-- when using a two stage pipeline:
--
-- Program:
-- addr value opcode
-- =============================
-- 3c: 00000000 nop
-- 40: 34040041 li $a0,0x41
-- 44: 3405ffff li $a1,0xffff
-- 48: a0a40000 sb $a0,0($a1)
-- 4c: 00000000 nop
-- 50: 00000000 nop
--
-- intr_in mem_pause
-- reset_in byte_we Stages
-- ns address data_w data_r 40 44 48 4c 50
-- 3600 0 0 00000040 00000000 34040041 0 0 1
-- 3700 0 0 00000044 00000000 3405FFFF 0 0 2 1
-- 3800 0 0 00000048 00000000 A0A40000 0 0 2 1
-- 3900 0 0 0000004C 41414141 00000000 0 0 2 1
-- 4000 0 0 0000FFFC 41414141 XXXXXX41 1 0 3 2
-- 4100 0 0 00000050 00000000 00000000 0 0 1
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been Instantiated
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
-- * A specific memory address in external ram has been blocked to be used by the NI
-- * IRQ return address register have been changed! It used to be saved in R0, now it is R26
---------------------------------------------------------------------
library ieee;
use work.mlite_pack.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mlite_cpu is
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT"; --AREA_OPTIMIZED
shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end; --entity mlite_cpu
architecture logic of mlite_cpu is
--When using a two stage pipeline "sigD <= sig".
--When using a three stage pipeline "sigD <= sig when rising_edge(clk)",
-- so sigD is delayed by one clock cycle.
signal opcode : std_logic_vector(31 downto 0);
signal rs_index : std_logic_vector(5 downto 0);
signal rt_index : std_logic_vector(5 downto 0);
signal rd_index : std_logic_vector(5 downto 0);
signal rd_indexD : std_logic_vector(5 downto 0);
signal reg_source : std_logic_vector(31 downto 0);
signal reg_target : std_logic_vector(31 downto 0);
signal reg_dest : std_logic_vector(31 downto 0);
signal reg_destD : std_logic_vector(31 downto 0);
signal a_bus : std_logic_vector(31 downto 0);
signal a_busD : std_logic_vector(31 downto 0);
signal b_bus : std_logic_vector(31 downto 0);
signal b_busD : std_logic_vector(31 downto 0);
signal c_bus : std_logic_vector(31 downto 0);
signal c_alu : std_logic_vector(31 downto 0);
signal c_shift : std_logic_vector(31 downto 0);
signal c_mult : std_logic_vector(31 downto 0);
signal c_memory : std_logic_vector(31 downto 0);
signal imm : std_logic_vector(15 downto 0);
signal pc_future : std_logic_vector(31 downto 2);
signal pc_current : std_logic_vector(31 downto 2);
signal pc_plus4 : std_logic_vector(31 downto 2);
signal alu_func : alu_function_type;
signal alu_funcD : alu_function_type;
signal shift_func : shift_function_type;
signal shift_funcD : shift_function_type;
signal mult_func : mult_function_type;
signal mult_funcD : mult_function_type;
signal branch_func : branch_function_type;
signal take_branch : std_logic;
signal a_source : a_source_type;
signal b_source : b_source_type;
signal c_source : c_source_type;
signal pc_source : pc_source_type;
signal mem_source : mem_source_type;
signal pause_mult : std_logic;
signal pause_ctrl : std_logic;
signal pause_pipeline : std_logic;
signal pause_any : std_logic;
signal pause_non_ctrl : std_logic;
signal pause_bank : std_logic;
signal nullify_op : std_logic;
signal intr_enable : std_logic;
signal intr_signal : std_logic;
signal exception_sig : std_logic;
signal reset_reg : std_logic_vector(3 downto 0);
signal reset : std_logic;
begin --architecture
pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
pause_bank <= ((mem_pause or pause_ctrl or pause_mult) and not pause_pipeline);
nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
or intr_signal = '1' or exception_sig = '1'
else '0';
c_bus <= c_alu or c_shift or c_mult;
reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
--synchronize reset and interrupt pins
intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
pc_source, pc_current, pause_any)
begin
if reset_in = '1' then
reset_reg <= "0000";
intr_signal <= '0';
elsif rising_edge(clk) then
if reset_reg /= "1111" then
reset_reg <= reset_reg + 1;
end if;
--don't try to interrupt a multi-cycle instruction
if pause_any = '0' then
if intr_in = '1' and intr_enable = '1' and pc_source = FROM_INC4 then -- pc_source = "00"
--the epc will contain pc+4
intr_signal <= '1';
else
intr_signal <= '0';
end if;
end if;
end if;
end process;
u1_pc_next: pc_next PORT MAP (
clk => clk,
reset_in => reset,
take_branch => take_branch,
pause_in => pause_any,
pc_new => c_bus(31 downto 2),
opcode25_0 => opcode(25 downto 0),
pc_source => pc_source,
pc_future => pc_future,
pc_current => pc_current,
pc_plus4 => pc_plus4);
u2_mem_ctrl: mem_ctrl
PORT MAP (
clk => clk,
reset_in => reset,
pause_in => pause_non_ctrl,
nullify_op => nullify_op,
address_pc => pc_future,
opcode_out => opcode,
address_in => c_bus,
mem_source => mem_source,
data_write => reg_target,
data_read => c_memory,
pause_out => pause_ctrl,
address_next => address_next,
byte_we_next => byte_we_next,
address => address,
byte_we => byte_we,
data_w => data_w,
data_r => data_r);
u3_control: control PORT MAP (
opcode => opcode, -- is it opcode or the whole instruction ??
intr_signal => intr_signal,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_index,
imm_out => imm,
alu_func => alu_func,
shift_func => shift_func,
mult_func => mult_func,
branch_func => branch_func,
a_source_out => a_source,
b_source_out => b_source,
c_source_out => c_source,
pc_source_out=> pc_source,
mem_source_out=> mem_source,
exception_out=> exception_sig);
u4_reg_bank: reg_bank
generic map(memory_type => memory_type)
port map (
clk => clk,
reset_in => reset,
pause => pause_bank,
interrupt_in => intr_in,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_indexD,
reg_source_out => reg_source,
reg_target_out => reg_target,
reg_dest_new => reg_destD,
intr_enable => intr_enable);
u5_bus_mux: bus_mux port map (
imm_in => imm,
reg_source => reg_source,
a_mux => a_source,
a_out => a_bus,
reg_target => reg_target,
b_mux => b_source,
b_out => b_bus,
c_bus => c_bus,
c_memory => c_memory,
c_pc => pc_current,
c_pc_plus4 => pc_plus4,
c_mux => c_source,
reg_dest_out => reg_dest,
branch_func => branch_func,
take_branch => take_branch);
u6_alu: alu
generic map (alu_type => alu_type)
port map (
a_in => a_busD,
b_in => b_busD,
alu_function => alu_funcD,
c_alu => c_alu);
u7_shifter: shifter
generic map (shifter_type => shifter_type)
port map (
value => b_busD,
shift_amount => a_busD(4 downto 0),
shift_func => shift_funcD,
c_shift => c_shift);
u8_mult: mult
generic map (mult_type => mult_type)
port map (
clk => clk,
reset_in => reset,
a => a_busD,
b => b_busD,
mult_func => mult_funcD,
c_mult => c_mult,
pause_out => pause_mult);
pipeline2: if pipeline_stages <= 2 generate
a_busD <= a_bus;
b_busD <= b_bus;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
rd_indexD <= rd_index;
reg_destD <= reg_dest;
pause_pipeline <= '0';
end generate; --pipeline2
pipeline3: if pipeline_stages > 2 generate
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
u9_pipeline: pipeline port map (
clk => clk,
reset => reset,
a_bus => a_bus,
a_busD => a_busD,
b_bus => b_bus,
b_busD => b_busD,
alu_func => alu_func,
alu_funcD => alu_funcD,
shift_func => shift_func,
shift_funcD => shift_funcD,
mult_func => mult_func,
mult_funcD => mult_funcD,
reg_dest => reg_dest,
reg_destD => reg_destD,
rd_index => rd_index,
rd_indexD => rd_indexD,
rs_index => rs_index,
rt_index => rt_index,
pc_source => pc_source,
mem_source => mem_source,
a_source => a_source,
b_source => b_source,
c_source => c_source,
c_bus => c_bus,
pause_any => pause_any,
pause_pipeline => pause_pipeline);
end generate; --pipeline3
end; --architecture logic
|
gpl-3.0
|
sunoc/vhdl-lz4-variation
|
z_old/sha1/sha1.vhd
|
1
|
13857
|
-----------------------------------------------------------------------------------
--! @file sha1.vhd
--! @brief SHA-1 Package :
--! SHA-1用各種定義パッケージ.
--! @version 0.9.1
--! @date 2012/11/27
--! @author Ichiro Kawazome <[email protected]>
-----------------------------------------------------------------------------------
--
-- Copyright (C) 2012 Ichiro Kawazome
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------------
--! @brief SHA-1用各種定義パッケージ.
-----------------------------------------------------------------------------------
package SHA1 is
-------------------------------------------------------------------------------
-- ハッシュのビット数
-------------------------------------------------------------------------------
constant HASH_BITS : integer := 160;
-------------------------------------------------------------------------------
-- １ワードのビット数
-------------------------------------------------------------------------------
constant WORD_BITS : integer := 32;
-------------------------------------------------------------------------------
-- ラウンド数
-------------------------------------------------------------------------------
constant ROUNDS : integer := 80;
-------------------------------------------------------------------------------
-- ワードの型宣言
-------------------------------------------------------------------------------
subtype WORD_TYPE is std_logic_vector(WORD_BITS-1 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
-------------------------------------------------------------------------------
-- ハッシュレジスタの初期値
-------------------------------------------------------------------------------
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"67452301"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"EFCDAB89"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"98BADCFE"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"10325476"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"C3D2E1F0"));
-------------------------------------------------------------------------------
-- K[t]の値
-------------------------------------------------------------------------------
constant K0 : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5A827999"));
constant K1 : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6ED9EBA1"));
constant K2 : WORD_TYPE := To_StdLogicVector(bit_vector'(X"8F1BBCDC"));
constant K3 : WORD_TYPE := To_StdLogicVector(bit_vector'(X"CA62C1D6"));
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
function RotL(X:WORD_TYPE;N:integer) return std_logic_vector;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
function Ch(B,C,D:WORD_TYPE) return std_logic_vector;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
function Parity(B,C,D:WORD_TYPE) return std_logic_vector;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
function Maj(B,C,D:WORD_TYPE) return std_logic_vector;
-------------------------------------------------------------------------------
-- SHA1_COREのコンポーネント宣言
-------------------------------------------------------------------------------
component SHA1_CORE
generic (
SYMBOL_BITS : --! @brief INPUT SYMBOL BITS :
--! 入力データの１シンボルのビット数を指定する.
integer := 8;
SYMBOLS : --! @brief INPUT SYMBOL SIZE :
--! 入力データのシンボル数を指定する.
integer := 4;
REVERSE : --! @brief INPUT SYMBOL REVERSE :
--! 入力データのシンボルのビット並びを逆にするかどうかを指定する.
integer := 1;
WORDS : --! @brief WORD SIZE :
--! 一度に処理するワード数を指定する.
integer := 1;
BLOCK_GAP : --! @brief BLOCK GAP CYCLE :
--! １ブロック(16word)処理する毎に挿入するギャップのサイクル
--! 数を指定する.
--! サイクル数分だけスループットが落ちるが、動作周波数が上が
--! る可能性がある.
integer := 1
);
port (
---------------------------------------------------------------------------
-- クロック&リセット信号
---------------------------------------------------------------------------
CLK : --! @brief CLOCK :
--! クロック信号
in std_logic;
RST : --! @brief ASYNCRONOUSE RESET :
--! 非同期リセット信号.アクティブハイ.
in std_logic;
CLR : --! @brief SYNCRONOUSE RESET :
--! 同期リセット信号.アクティブハイ.
in std_logic;
---------------------------------------------------------------------------
-- 入力側 I/F
---------------------------------------------------------------------------
I_DATA : --! @brief INPUT SYMBOL DATA :
in std_logic_vector(SYMBOL_BITS*SYMBOLS-1 downto 0);
I_ENA : --! @brief INPUT SYMBOL DATA ENABLE :
in std_logic_vector( SYMBOLS-1 downto 0);
I_DONE : --! @brief INPUT SYMBOL DATA DONE :
in std_logic;
I_LAST : --! @brief INPUT SYMBOL DATA LAST :
in std_logic;
I_VAL : --! @brief INPUT SYMBOL DATA VALID :
in std_logic;
I_RDY : --! @brief INPUT SYMBOL DATA READY :
out std_logic;
---------------------------------------------------------------------------
-- 出力側 I/F
---------------------------------------------------------------------------
O_DATA : --! @brief OUTPUT WORD DATA :
out std_logic_vector(HASH_BITS-1 downto 0);
O_VAL : --! @brief OUTPUT WORD VALID :
out std_logic;
O_RDY : --! @brief OUTPUT WORD READY :
in std_logic
);
end component;
-------------------------------------------------------------------------------
-- SHA_SCHEDULEのコンポーネント宣言
-------------------------------------------------------------------------------
component SHA_SCHEDULE
generic (
WORD_BITS : integer := WORD_BITS;
WORDS : integer := 1;
INPUT_NUM : integer := 16;
CALC_NUM : integer := ROUNDS;
END_NUM : integer := ROUNDS
);
port (
CLK : in std_logic;
RST : in std_logic;
CLR : in std_logic;
I_DONE : in std_logic;
I_VAL : in std_logic;
I_RDY : out std_logic;
O_INPUT : out std_logic;
O_LAST : out std_logic;
O_DONE : out std_logic;
O_NUM : out integer range 0 to END_NUM-1;
O_VAL : out std_logic;
O_RDY : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- SHA_PRE_PROCのコンポーネント宣言
-------------------------------------------------------------------------------
component SHA_PRE_PROC
generic (
WORD_BITS : integer := 32;
WORDS : integer := 1;
SYMBOL_BITS : integer := 8;
SYMBOLS : integer := 4;
REVERSE : integer := 1
);
port (
CLK : in std_logic;
RST : in std_logic;
CLR : in std_logic;
I_DATA : in std_logic_vector(SYMBOL_BITS*SYMBOLS-1 downto 0);
I_ENA : in std_logic_vector( SYMBOLS-1 downto 0);
I_DONE : in std_logic;
I_LAST : in std_logic;
I_VAL : in std_logic;
I_RDY : out std_logic;
M_DATA : out std_logic_vector(WORD_BITS*WORDS-1 downto 0);
M_DONE : out std_logic;
M_VAL : out std_logic;
M_RDY : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- SHA1_PROCのコンポーネント宣言
-------------------------------------------------------------------------------
component SHA1_PROC
generic (
WORDS : integer := 1;
PIPELINE : integer := 1;
BLOCK_GAP : integer := 0
);
port (
CLK : in std_logic;
RST : in std_logic;
CLR : in std_logic;
M_DATA : in std_logic_vector(WORD_BITS*WORDS-1 downto 0);
M_DONE : in std_logic;
M_VAL : in std_logic;
M_RDY : out std_logic;
O_DATA : out std_logic_vector(HASH_BITS-1 downto 0);
O_VAL : out std_logic;
O_RDY : in std_logic
);
end component;
end SHA1;
-----------------------------------------------------------------------------------
--! @brief SHA-1用各種プロシージャの定義.
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package body SHA1 is
-------------------------------------------------------------------------------
-- ローテート演算関数.
-------------------------------------------------------------------------------
function RotL(X:WORD_TYPE;N:integer) return std_logic_vector is
begin
return X(WORD_TYPE'high-N downto WORD_TYPE'low ) &
X(WORD_TYPE'high downto WORD_TYPE'high-N+1);
end function;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
function Ch(B,C,D:WORD_TYPE) return std_logic_vector is
begin
return D xor (B and (C xor D));
end function;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
function Parity(B,C,D:WORD_TYPE) return std_logic_vector is
begin
return B xor C xor D;
end function;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
function Maj(B,C,D:WORD_TYPE) return std_logic_vector is
begin
return (B and C) or ((B or C) and D);
end function;
end SHA1;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_status_flags_as.vhd
|
9
|
20310
|
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`protect end_protected
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_status_flags_as.vhd
|
9
|
20310
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13296)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/allocator_logic_pseudo_checkers.vhd
|
12
|
24829
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_logic_pseudo_checkers is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end allocator_logic_pseudo_checkers;
architecture behavior of allocator_logic_pseudo_checkers is
begin
-- The combionational part
-- Checkers
-- Grant_N checkers
process (grant_N_N_sig, empty_N, grant_N_N)
begin
if (grant_N_N_sig = '1' and empty_N = '0' and grant_N_N = '0') then
err_grant_N_N_sig_not_empty_N_grant_N_N <= '1';
else
err_grant_N_N_sig_not_empty_N_grant_N_N <= '0';
end if;
end process;
process (grant_N_N_sig, empty_N, grant_N_N)
begin
if ( (grant_N_N_sig = '0' or empty_N = '1') and grant_N_N = '1') then
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N <= '1';
else
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N <= '0';
end if;
end process;
process (grant_N_E_sig, empty_E, grant_N_E)
begin
if (grant_N_E_sig = '1' and empty_E = '0' and grant_N_E = '0') then
err_grant_N_E_sig_not_empty_E_grant_N_E <= '1';
else
err_grant_N_E_sig_not_empty_E_grant_N_E <= '0';
end if;
end process;
process (grant_N_E_sig, empty_E, grant_N_E)
begin
if ( (grant_N_E_sig = '0' or empty_E = '1') and grant_N_E = '1') then
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E <= '1';
else
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E <= '0';
end if;
end process;
process (grant_N_W_sig, empty_W, grant_N_W)
begin
if (grant_N_W_sig = '1' and empty_W = '0' and grant_N_W = '0') then
err_grant_N_W_sig_not_empty_W_grant_N_W <= '1';
else
err_grant_N_W_sig_not_empty_W_grant_N_W <= '0';
end if;
end process;
process (grant_N_W_sig, empty_W, grant_N_W)
begin
if ( (grant_N_W_sig = '0' or empty_W = '1') and grant_N_W = '1') then
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W <= '1';
else
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W <= '0';
end if;
end process;
process (grant_N_S_sig, empty_S, grant_N_S)
begin
if (grant_N_S_sig = '1' and empty_S = '0' and grant_N_S = '0') then
err_grant_N_S_sig_not_empty_S_grant_N_S <= '1';
else
err_grant_N_S_sig_not_empty_S_grant_N_S <= '0';
end if;
end process;
process (grant_N_S_sig, empty_S, grant_N_S)
begin
if ( (grant_N_S_sig = '0' or empty_S = '1') and grant_N_S = '1') then
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S <= '1';
else
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S <= '0';
end if;
end process;
process (grant_N_L_sig, empty_L, grant_N_L)
begin
if (grant_N_L_sig = '1' and empty_L = '0' and grant_N_L = '0') then
err_grant_N_L_sig_not_empty_L_grant_N_L <= '1';
else
err_grant_N_L_sig_not_empty_L_grant_N_L <= '0';
end if;
end process;
process (grant_N_L_sig, empty_L, grant_N_L)
begin
if ( (grant_N_L_sig = '0' or empty_L = '1') and grant_N_L = '1') then
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L <= '1';
else
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_E checkers
process (grant_E_N_sig, empty_N, grant_E_N)
begin
if (grant_E_N_sig = '1' and empty_N = '0' and grant_E_N = '0') then
err_grant_E_N_sig_not_empty_N_grant_E_N <= '1';
else
err_grant_E_N_sig_not_empty_N_grant_E_N <= '0';
end if;
end process;
process (grant_E_N_sig, empty_N, grant_E_N)
begin
if ( (grant_E_N_sig = '0' or empty_N = '1') and grant_E_N = '1') then
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N <= '1';
else
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N <= '0';
end if;
end process;
process (grant_E_E_sig, empty_E, grant_E_E)
begin
if (grant_E_E_sig = '1' and empty_E = '0' and grant_E_E = '0') then
err_grant_E_E_sig_not_empty_E_grant_E_E <= '1';
else
err_grant_E_E_sig_not_empty_E_grant_E_E <= '0';
end if;
end process;
process (grant_E_E_sig, empty_E, grant_E_E)
begin
if ( (grant_E_E_sig = '0' or empty_E = '1') and grant_E_E = '1') then
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E <= '1';
else
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E <= '0';
end if;
end process;
process (grant_E_W_sig, empty_W, grant_E_W)
begin
if (grant_E_W_sig = '1' and empty_W = '0' and grant_E_W = '0') then
err_grant_E_W_sig_not_empty_W_grant_E_W <= '1';
else
err_grant_E_W_sig_not_empty_W_grant_E_W <= '0';
end if;
end process;
process (grant_E_W_sig, empty_W, grant_E_W)
begin
if ( (grant_E_W_sig = '0' or empty_W = '1') and grant_E_W = '1') then
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W <= '1';
else
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W <= '0';
end if;
end process;
process (grant_E_S_sig, empty_S, grant_E_S)
begin
if (grant_E_S_sig = '1' and empty_S = '0' and grant_E_S = '0') then
err_grant_E_S_sig_not_empty_S_grant_E_S <= '1';
else
err_grant_E_S_sig_not_empty_S_grant_E_S <= '0';
end if;
end process;
process (grant_E_S_sig, empty_S, grant_E_S)
begin
if ( (grant_E_S_sig = '0' or empty_S = '1') and grant_E_S = '1') then
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S <= '1';
else
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S <= '0';
end if;
end process;
process (grant_E_L_sig, empty_L, grant_E_L)
begin
if (grant_E_L_sig = '1' and empty_L = '0' and grant_E_L = '0') then
err_grant_E_L_sig_not_empty_L_grant_E_L <= '1';
else
err_grant_E_L_sig_not_empty_L_grant_E_L <= '0';
end if;
end process;
process (grant_E_L_sig, empty_L, grant_E_L)
begin
if ( (grant_E_L_sig = '0' or empty_L = '1') and grant_E_L = '1') then
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L <= '1';
else
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_W checkers
process (grant_W_N_sig, empty_N, grant_W_N)
begin
if (grant_W_N_sig = '1' and empty_N = '0' and grant_W_N = '0') then
err_grant_W_N_sig_not_empty_N_grant_W_N <= '1';
else
err_grant_W_N_sig_not_empty_N_grant_W_N <= '0';
end if;
end process;
process (grant_W_N_sig, empty_N, grant_W_N)
begin
if ( (grant_W_N_sig = '0' or empty_N = '1') and grant_W_N = '1') then
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N <= '1';
else
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N <= '0';
end if;
end process;
process (grant_W_E_sig, empty_E, grant_W_E)
begin
if (grant_W_E_sig = '1' and empty_E = '0' and grant_W_E = '0') then
err_grant_W_E_sig_not_empty_E_grant_W_E <= '1';
else
err_grant_W_E_sig_not_empty_E_grant_W_E <= '0';
end if;
end process;
process (grant_W_E_sig, empty_E, grant_W_E)
begin
if ( (grant_W_E_sig = '0' or empty_E = '1') and grant_W_E = '1') then
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E <= '1';
else
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E <= '0';
end if;
end process;
process (grant_W_W_sig, empty_W, grant_W_W)
begin
if (grant_W_W_sig = '1' and empty_W = '0' and grant_W_W = '0') then
err_grant_W_W_sig_not_empty_W_grant_W_W <= '1';
else
err_grant_W_W_sig_not_empty_W_grant_W_W <= '0';
end if;
end process;
process (grant_W_W_sig, empty_W, grant_W_W)
begin
if ( (grant_W_W_sig = '0' or empty_W = '1') and grant_W_W = '1') then
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W <= '1';
else
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W <= '0';
end if;
end process;
process (grant_W_S_sig, empty_S, grant_W_S)
begin
if (grant_W_S_sig = '1' and empty_S = '0' and grant_W_S = '0') then
err_grant_W_S_sig_not_empty_S_grant_W_S <= '1';
else
err_grant_W_S_sig_not_empty_S_grant_W_S <= '0';
end if;
end process;
process (grant_W_S_sig, empty_S, grant_W_S)
begin
if ( (grant_W_S_sig = '0' or empty_S = '1') and grant_W_S = '1') then
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S <= '1';
else
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S <= '0';
end if;
end process;
process (grant_W_L_sig, empty_L, grant_W_L)
begin
if (grant_W_L_sig = '1' and empty_L = '0' and grant_W_L = '0') then
err_grant_W_L_sig_not_empty_L_grant_W_L <= '1';
else
err_grant_W_L_sig_not_empty_L_grant_W_L <= '0';
end if;
end process;
process (grant_W_L_sig, empty_L, grant_W_L)
begin
if ( (grant_W_L_sig = '0' or empty_L = '1') and grant_W_L = '1') then
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L <= '1';
else
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_S checkers
process (grant_S_N_sig, empty_N, grant_S_N)
begin
if (grant_S_N_sig = '1' and empty_N = '0' and grant_S_N = '0') then
err_grant_S_N_sig_not_empty_N_grant_S_N <= '1';
else
err_grant_S_N_sig_not_empty_N_grant_S_N <= '0';
end if;
end process;
process (grant_S_N_sig, empty_N, grant_S_N)
begin
if ( (grant_S_N_sig = '0' or empty_N = '1') and grant_S_N = '1') then
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N <= '1';
else
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N <= '0';
end if;
end process;
process (grant_S_E_sig, empty_E, grant_S_E)
begin
if (grant_S_E_sig = '1' and empty_E = '0' and grant_S_E = '0') then
err_grant_S_E_sig_not_empty_E_grant_S_E <= '1';
else
err_grant_S_E_sig_not_empty_E_grant_S_E <= '0';
end if;
end process;
process (grant_S_E_sig, empty_E, grant_S_E)
begin
if ( (grant_S_E_sig = '0' or empty_E = '1') and grant_S_E = '1') then
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E <= '1';
else
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E <= '0';
end if;
end process;
process (grant_S_W_sig, empty_W, grant_S_W)
begin
if (grant_S_W_sig = '1' and empty_W = '0' and grant_S_W = '0') then
err_grant_S_W_sig_not_empty_W_grant_S_W <= '1';
else
err_grant_S_W_sig_not_empty_W_grant_S_W <= '0';
end if;
end process;
process (grant_S_W_sig, empty_W, grant_S_W)
begin
if ( (grant_S_W_sig = '0' or empty_W = '1') and grant_S_W = '1') then
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W <= '1';
else
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W <= '0';
end if;
end process;
process (grant_S_S_sig, empty_S, grant_S_S)
begin
if (grant_S_S_sig = '1' and empty_S = '0' and grant_S_S = '0') then
err_grant_S_S_sig_not_empty_S_grant_S_S <= '1';
else
err_grant_S_S_sig_not_empty_S_grant_S_S <= '0';
end if;
end process;
process (grant_S_S_sig, empty_S, grant_S_S)
begin
if ( (grant_S_S_sig = '0' or empty_S = '1') and grant_S_S = '1') then
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S <= '1';
else
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S <= '0';
end if;
end process;
process (grant_S_L_sig, empty_L, grant_S_L)
begin
if (grant_S_L_sig = '1' and empty_L = '0' and grant_S_L = '0') then
err_grant_S_L_sig_not_empty_L_grant_S_L <= '1';
else
err_grant_S_L_sig_not_empty_L_grant_S_L <= '0';
end if;
end process;
process (grant_S_L_sig, empty_L, grant_S_L)
begin
if ( (grant_S_L_sig = '0' or empty_L = '1') and grant_S_L = '1') then
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L <= '1';
else
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_L checkers
process (grant_L_N_sig, empty_N, grant_L_N)
begin
if (grant_L_N_sig = '1' and empty_N = '0' and grant_L_N = '0') then
err_grant_L_N_sig_not_empty_N_grant_L_N <= '1';
else
err_grant_L_N_sig_not_empty_N_grant_L_N <= '0';
end if;
end process;
process (grant_L_N_sig, empty_N, grant_L_N)
begin
if ( (grant_L_N_sig = '0' or empty_N = '1') and grant_L_N = '1') then
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N <= '1';
else
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N <= '0';
end if;
end process;
process (grant_L_E_sig, empty_E, grant_L_E)
begin
if (grant_L_E_sig = '1' and empty_E = '0' and grant_L_E = '0') then
err_grant_L_E_sig_not_empty_E_grant_L_E <= '1';
else
err_grant_L_E_sig_not_empty_E_grant_L_E <= '0';
end if;
end process;
process (grant_L_E_sig, empty_E, grant_L_E)
begin
if ( (grant_L_E_sig = '0' or empty_E = '1') and grant_L_E = '1') then
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E <= '1';
else
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E <= '0';
end if;
end process;
process (grant_L_W_sig, empty_W, grant_L_W)
begin
if (grant_L_W_sig = '1' and empty_W = '0' and grant_L_W = '0') then
err_grant_L_W_sig_not_empty_W_grant_L_W <= '1';
else
err_grant_L_W_sig_not_empty_W_grant_L_W <= '0';
end if;
end process;
process (grant_L_W_sig, empty_W, grant_L_W)
begin
if ( (grant_L_W_sig = '0' or empty_W = '1') and grant_L_W = '1') then
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W <= '1';
else
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W <= '0';
end if;
end process;
process (grant_L_S_sig, empty_S, grant_L_S)
begin
if (grant_L_S_sig = '1' and empty_S = '0' and grant_L_S = '0') then
err_grant_L_S_sig_not_empty_S_grant_L_S <= '1';
else
err_grant_L_S_sig_not_empty_S_grant_L_S <= '0';
end if;
end process;
process (grant_L_S_sig, empty_S, grant_L_S)
begin
if ( (grant_L_S_sig = '0' or empty_S = '1') and grant_L_S = '1') then
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S <= '1';
else
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S <= '0';
end if;
end process;
process (grant_L_L_sig, empty_L, grant_L_L)
begin
if (grant_L_L_sig = '1' and empty_L = '0' and grant_L_L = '0') then
err_grant_L_L_sig_not_empty_L_grant_L_L <= '1';
else
err_grant_L_L_sig_not_empty_L_grant_L_L <= '0';
end if;
end process;
process (grant_L_L_sig, empty_L, grant_L_L)
begin
if ( (grant_L_L_sig = '0' or empty_L = '1') and grant_L_L = '1') then
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L <= '1';
else
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Final Grant output checkers
-- North
process (grant_N_N_sig, empty_N, grant_N_E_sig, empty_E, grant_N_W_sig, empty_W, grant_N_S_sig, empty_S, grant_N_L_sig, empty_L, grant_N)
begin
if ( ( (grant_N_N_sig = '1' and empty_N = '0' ) or (grant_N_E_sig = '1' and empty_E = '0') or (grant_N_W_sig = '1' and empty_W = '0') or
(grant_N_S_sig = '1' and empty_S = '0') or (grant_N_L_sig = '1' and empty_L = '0') ) and grant_N = '0' ) then
err_grant_signals_not_empty_grant_N <= '1';
else
err_grant_signals_not_empty_grant_N <= '0';
end if;
end process;
process (grant_N_N_sig, empty_N, grant_N_E_sig, empty_E, grant_N_W_sig, empty_W, grant_N_S_sig, empty_S, grant_N_L_sig, empty_L, grant_N)
begin
if ( ( (grant_N_N_sig = '0' or empty_N = '1' ) and (grant_N_E_sig = '0' and empty_E = '1') and (grant_N_W_sig = '0' or empty_W = '1') and
(grant_N_S_sig = '0' or empty_S = '1') and (grant_N_L_sig = '0' or empty_L = '1') ) and grant_N /= '0' ) then
err_not_grant_signals_empty_not_grant_N <= '1';
else
err_not_grant_signals_empty_not_grant_N <= '0';
end if;
end process;
-- East
process (grant_E_N_sig, empty_N, grant_E_E_sig, empty_E, grant_E_W_sig, empty_W, grant_E_S_sig, empty_S, grant_E_L_sig, empty_L, grant_E)
begin
if ( ( (grant_E_N_sig = '1' and empty_N = '0' ) or (grant_E_E_sig = '1' and empty_E = '0') or (grant_E_W_sig = '1' and empty_W = '0') or
(grant_E_S_sig = '1' and empty_S = '0') or (grant_E_L_sig = '1' and empty_L = '0') ) and grant_E = '0' ) then
err_grant_signals_not_empty_grant_E <= '1';
else
err_grant_signals_not_empty_grant_E <= '0';
end if;
end process;
process (grant_E_N_sig, empty_N, grant_E_E_sig, empty_E, grant_E_W_sig, empty_W, grant_E_S_sig, empty_S, grant_E_L_sig, empty_L, grant_E)
begin
if ( ( (grant_E_N_sig = '0' or empty_N = '1' ) and (grant_E_E_sig = '0' and empty_E = '1') and (grant_E_W_sig = '0' or empty_W = '1') and
(grant_E_S_sig = '0' or empty_S = '1') and (grant_E_L_sig = '0' or empty_L = '1') ) and grant_E /= '0' ) then
err_not_grant_signals_empty_not_grant_E <= '1';
else
err_not_grant_signals_empty_not_grant_E <= '0';
end if;
end process;
-- West
process (grant_W_N_sig, empty_N, grant_W_E_sig, empty_E, grant_W_W_sig, empty_W, grant_W_S_sig, empty_S, grant_W_L_sig, empty_L, grant_W)
begin
if ( ( (grant_W_N_sig = '1' and empty_N = '0' ) or (grant_W_E_sig = '1' and empty_E = '0') or (grant_W_W_sig = '1' and empty_W = '0') or
(grant_W_S_sig = '1' and empty_S = '0') or (grant_W_L_sig = '1' and empty_L = '0') ) and grant_W = '0' ) then
err_grant_signals_not_empty_grant_W <= '1';
else
err_grant_signals_not_empty_grant_W <= '0';
end if;
end process;
process (grant_W_N_sig, empty_N, grant_W_E_sig, empty_E, grant_W_W_sig, empty_W, grant_W_S_sig, empty_S, grant_W_L_sig, empty_L, grant_W)
begin
if ( ( (grant_W_N_sig = '0' or empty_N = '1' ) and (grant_W_E_sig = '0' and empty_E = '1') and (grant_W_W_sig = '0' or empty_W = '1') and
(grant_W_S_sig = '0' or empty_S = '1') and (grant_W_L_sig = '0' or empty_L = '1') ) and grant_W /= '0' ) then
err_not_grant_signals_empty_not_grant_W <= '1';
else
err_not_grant_signals_empty_not_grant_W <= '0';
end if;
end process;
-- South
process (grant_S_N_sig, empty_N, grant_S_E_sig, empty_E, grant_S_W_sig, empty_W, grant_S_S_sig, empty_S, grant_S_L_sig, empty_L, grant_S)
begin
if ( ( (grant_S_N_sig = '1' and empty_N = '0' ) or (grant_S_E_sig = '1' and empty_E = '0') or (grant_S_W_sig = '1' and empty_W = '0') or
(grant_S_S_sig = '1' and empty_S = '0') or (grant_S_L_sig = '1' and empty_L = '0') ) and grant_S = '0' ) then
err_grant_signals_not_empty_grant_S <= '1';
else
err_grant_signals_not_empty_grant_S <= '0';
end if;
end process;
process (grant_S_N_sig, empty_N, grant_S_E_sig, empty_E, grant_S_W_sig, empty_W, grant_S_S_sig, empty_S, grant_S_L_sig, empty_L, grant_S)
begin
if ( ( (grant_S_N_sig = '0' or empty_N = '1' ) and (grant_S_E_sig = '0' and empty_E = '1') and (grant_S_W_sig = '0' or empty_W = '1') and
(grant_S_S_sig = '0' or empty_S = '1') and (grant_S_L_sig = '0' or empty_L = '1') ) and grant_S /= '0' ) then
err_not_grant_signals_empty_not_grant_S <= '1';
else
err_not_grant_signals_empty_not_grant_S <= '0';
end if;
end process;
-- Local
process (grant_L_N_sig, empty_N, grant_L_E_sig, empty_E, grant_L_W_sig, empty_W, grant_L_S_sig, empty_S, grant_L_L_sig, empty_L, grant_L)
begin
if ( ( (grant_L_N_sig = '1' and empty_N = '0' ) or (grant_L_E_sig = '1' and empty_E = '0') or (grant_L_W_sig = '1' and empty_W = '0') or
(grant_L_S_sig = '1' and empty_S = '0') or (grant_L_L_sig = '1' and empty_L = '0') ) and grant_L = '0' ) then
err_grant_signals_not_empty_grant_L <= '1';
else
err_grant_signals_not_empty_grant_L <= '0';
end if;
end process;
process (grant_L_N_sig, empty_N, grant_L_E_sig, empty_E, grant_L_W_sig, empty_W, grant_L_S_sig, empty_S, grant_L_L_sig, empty_L, grant_L)
begin
if ( ( (grant_L_N_sig = '0' or empty_N = '1' ) and (grant_L_E_sig = '0' and empty_E = '1') and (grant_L_W_sig = '0' or empty_W = '1') and
(grant_L_S_sig = '0' or empty_S = '1') and (grant_L_L_sig = '0' or empty_L = '1') ) and grant_L /= '0' ) then
err_not_grant_signals_empty_not_grant_L <= '1';
else
err_not_grant_signals_empty_not_grant_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Valid output checkers
process (valid_N, valid_E, valid_W, valid_S, valid_L, grant_N, grant_E, grant_W, grant_S, grant_L)
begin
if (valid_N /= grant_N or valid_E /= grant_E or valid_W /= grant_W or valid_S /= grant_S or valid_L /= grant_L) then
err_grants_valid_not_match <= '1';
else
err_grants_valid_not_match <= '0';
end if;
end process;
END;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/Allocator_with_checkers/allocator_logic_pseudo_checkers.vhd
|
12
|
24829
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_logic_pseudo_checkers is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end allocator_logic_pseudo_checkers;
architecture behavior of allocator_logic_pseudo_checkers is
begin
-- The combionational part
-- Checkers
-- Grant_N checkers
process (grant_N_N_sig, empty_N, grant_N_N)
begin
if (grant_N_N_sig = '1' and empty_N = '0' and grant_N_N = '0') then
err_grant_N_N_sig_not_empty_N_grant_N_N <= '1';
else
err_grant_N_N_sig_not_empty_N_grant_N_N <= '0';
end if;
end process;
process (grant_N_N_sig, empty_N, grant_N_N)
begin
if ( (grant_N_N_sig = '0' or empty_N = '1') and grant_N_N = '1') then
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N <= '1';
else
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N <= '0';
end if;
end process;
process (grant_N_E_sig, empty_E, grant_N_E)
begin
if (grant_N_E_sig = '1' and empty_E = '0' and grant_N_E = '0') then
err_grant_N_E_sig_not_empty_E_grant_N_E <= '1';
else
err_grant_N_E_sig_not_empty_E_grant_N_E <= '0';
end if;
end process;
process (grant_N_E_sig, empty_E, grant_N_E)
begin
if ( (grant_N_E_sig = '0' or empty_E = '1') and grant_N_E = '1') then
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E <= '1';
else
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E <= '0';
end if;
end process;
process (grant_N_W_sig, empty_W, grant_N_W)
begin
if (grant_N_W_sig = '1' and empty_W = '0' and grant_N_W = '0') then
err_grant_N_W_sig_not_empty_W_grant_N_W <= '1';
else
err_grant_N_W_sig_not_empty_W_grant_N_W <= '0';
end if;
end process;
process (grant_N_W_sig, empty_W, grant_N_W)
begin
if ( (grant_N_W_sig = '0' or empty_W = '1') and grant_N_W = '1') then
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W <= '1';
else
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W <= '0';
end if;
end process;
process (grant_N_S_sig, empty_S, grant_N_S)
begin
if (grant_N_S_sig = '1' and empty_S = '0' and grant_N_S = '0') then
err_grant_N_S_sig_not_empty_S_grant_N_S <= '1';
else
err_grant_N_S_sig_not_empty_S_grant_N_S <= '0';
end if;
end process;
process (grant_N_S_sig, empty_S, grant_N_S)
begin
if ( (grant_N_S_sig = '0' or empty_S = '1') and grant_N_S = '1') then
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S <= '1';
else
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S <= '0';
end if;
end process;
process (grant_N_L_sig, empty_L, grant_N_L)
begin
if (grant_N_L_sig = '1' and empty_L = '0' and grant_N_L = '0') then
err_grant_N_L_sig_not_empty_L_grant_N_L <= '1';
else
err_grant_N_L_sig_not_empty_L_grant_N_L <= '0';
end if;
end process;
process (grant_N_L_sig, empty_L, grant_N_L)
begin
if ( (grant_N_L_sig = '0' or empty_L = '1') and grant_N_L = '1') then
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L <= '1';
else
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_E checkers
process (grant_E_N_sig, empty_N, grant_E_N)
begin
if (grant_E_N_sig = '1' and empty_N = '0' and grant_E_N = '0') then
err_grant_E_N_sig_not_empty_N_grant_E_N <= '1';
else
err_grant_E_N_sig_not_empty_N_grant_E_N <= '0';
end if;
end process;
process (grant_E_N_sig, empty_N, grant_E_N)
begin
if ( (grant_E_N_sig = '0' or empty_N = '1') and grant_E_N = '1') then
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N <= '1';
else
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N <= '0';
end if;
end process;
process (grant_E_E_sig, empty_E, grant_E_E)
begin
if (grant_E_E_sig = '1' and empty_E = '0' and grant_E_E = '0') then
err_grant_E_E_sig_not_empty_E_grant_E_E <= '1';
else
err_grant_E_E_sig_not_empty_E_grant_E_E <= '0';
end if;
end process;
process (grant_E_E_sig, empty_E, grant_E_E)
begin
if ( (grant_E_E_sig = '0' or empty_E = '1') and grant_E_E = '1') then
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E <= '1';
else
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E <= '0';
end if;
end process;
process (grant_E_W_sig, empty_W, grant_E_W)
begin
if (grant_E_W_sig = '1' and empty_W = '0' and grant_E_W = '0') then
err_grant_E_W_sig_not_empty_W_grant_E_W <= '1';
else
err_grant_E_W_sig_not_empty_W_grant_E_W <= '0';
end if;
end process;
process (grant_E_W_sig, empty_W, grant_E_W)
begin
if ( (grant_E_W_sig = '0' or empty_W = '1') and grant_E_W = '1') then
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W <= '1';
else
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W <= '0';
end if;
end process;
process (grant_E_S_sig, empty_S, grant_E_S)
begin
if (grant_E_S_sig = '1' and empty_S = '0' and grant_E_S = '0') then
err_grant_E_S_sig_not_empty_S_grant_E_S <= '1';
else
err_grant_E_S_sig_not_empty_S_grant_E_S <= '0';
end if;
end process;
process (grant_E_S_sig, empty_S, grant_E_S)
begin
if ( (grant_E_S_sig = '0' or empty_S = '1') and grant_E_S = '1') then
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S <= '1';
else
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S <= '0';
end if;
end process;
process (grant_E_L_sig, empty_L, grant_E_L)
begin
if (grant_E_L_sig = '1' and empty_L = '0' and grant_E_L = '0') then
err_grant_E_L_sig_not_empty_L_grant_E_L <= '1';
else
err_grant_E_L_sig_not_empty_L_grant_E_L <= '0';
end if;
end process;
process (grant_E_L_sig, empty_L, grant_E_L)
begin
if ( (grant_E_L_sig = '0' or empty_L = '1') and grant_E_L = '1') then
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L <= '1';
else
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_W checkers
process (grant_W_N_sig, empty_N, grant_W_N)
begin
if (grant_W_N_sig = '1' and empty_N = '0' and grant_W_N = '0') then
err_grant_W_N_sig_not_empty_N_grant_W_N <= '1';
else
err_grant_W_N_sig_not_empty_N_grant_W_N <= '0';
end if;
end process;
process (grant_W_N_sig, empty_N, grant_W_N)
begin
if ( (grant_W_N_sig = '0' or empty_N = '1') and grant_W_N = '1') then
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N <= '1';
else
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N <= '0';
end if;
end process;
process (grant_W_E_sig, empty_E, grant_W_E)
begin
if (grant_W_E_sig = '1' and empty_E = '0' and grant_W_E = '0') then
err_grant_W_E_sig_not_empty_E_grant_W_E <= '1';
else
err_grant_W_E_sig_not_empty_E_grant_W_E <= '0';
end if;
end process;
process (grant_W_E_sig, empty_E, grant_W_E)
begin
if ( (grant_W_E_sig = '0' or empty_E = '1') and grant_W_E = '1') then
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E <= '1';
else
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E <= '0';
end if;
end process;
process (grant_W_W_sig, empty_W, grant_W_W)
begin
if (grant_W_W_sig = '1' and empty_W = '0' and grant_W_W = '0') then
err_grant_W_W_sig_not_empty_W_grant_W_W <= '1';
else
err_grant_W_W_sig_not_empty_W_grant_W_W <= '0';
end if;
end process;
process (grant_W_W_sig, empty_W, grant_W_W)
begin
if ( (grant_W_W_sig = '0' or empty_W = '1') and grant_W_W = '1') then
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W <= '1';
else
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W <= '0';
end if;
end process;
process (grant_W_S_sig, empty_S, grant_W_S)
begin
if (grant_W_S_sig = '1' and empty_S = '0' and grant_W_S = '0') then
err_grant_W_S_sig_not_empty_S_grant_W_S <= '1';
else
err_grant_W_S_sig_not_empty_S_grant_W_S <= '0';
end if;
end process;
process (grant_W_S_sig, empty_S, grant_W_S)
begin
if ( (grant_W_S_sig = '0' or empty_S = '1') and grant_W_S = '1') then
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S <= '1';
else
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S <= '0';
end if;
end process;
process (grant_W_L_sig, empty_L, grant_W_L)
begin
if (grant_W_L_sig = '1' and empty_L = '0' and grant_W_L = '0') then
err_grant_W_L_sig_not_empty_L_grant_W_L <= '1';
else
err_grant_W_L_sig_not_empty_L_grant_W_L <= '0';
end if;
end process;
process (grant_W_L_sig, empty_L, grant_W_L)
begin
if ( (grant_W_L_sig = '0' or empty_L = '1') and grant_W_L = '1') then
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L <= '1';
else
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_S checkers
process (grant_S_N_sig, empty_N, grant_S_N)
begin
if (grant_S_N_sig = '1' and empty_N = '0' and grant_S_N = '0') then
err_grant_S_N_sig_not_empty_N_grant_S_N <= '1';
else
err_grant_S_N_sig_not_empty_N_grant_S_N <= '0';
end if;
end process;
process (grant_S_N_sig, empty_N, grant_S_N)
begin
if ( (grant_S_N_sig = '0' or empty_N = '1') and grant_S_N = '1') then
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N <= '1';
else
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N <= '0';
end if;
end process;
process (grant_S_E_sig, empty_E, grant_S_E)
begin
if (grant_S_E_sig = '1' and empty_E = '0' and grant_S_E = '0') then
err_grant_S_E_sig_not_empty_E_grant_S_E <= '1';
else
err_grant_S_E_sig_not_empty_E_grant_S_E <= '0';
end if;
end process;
process (grant_S_E_sig, empty_E, grant_S_E)
begin
if ( (grant_S_E_sig = '0' or empty_E = '1') and grant_S_E = '1') then
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E <= '1';
else
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E <= '0';
end if;
end process;
process (grant_S_W_sig, empty_W, grant_S_W)
begin
if (grant_S_W_sig = '1' and empty_W = '0' and grant_S_W = '0') then
err_grant_S_W_sig_not_empty_W_grant_S_W <= '1';
else
err_grant_S_W_sig_not_empty_W_grant_S_W <= '0';
end if;
end process;
process (grant_S_W_sig, empty_W, grant_S_W)
begin
if ( (grant_S_W_sig = '0' or empty_W = '1') and grant_S_W = '1') then
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W <= '1';
else
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W <= '0';
end if;
end process;
process (grant_S_S_sig, empty_S, grant_S_S)
begin
if (grant_S_S_sig = '1' and empty_S = '0' and grant_S_S = '0') then
err_grant_S_S_sig_not_empty_S_grant_S_S <= '1';
else
err_grant_S_S_sig_not_empty_S_grant_S_S <= '0';
end if;
end process;
process (grant_S_S_sig, empty_S, grant_S_S)
begin
if ( (grant_S_S_sig = '0' or empty_S = '1') and grant_S_S = '1') then
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S <= '1';
else
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S <= '0';
end if;
end process;
process (grant_S_L_sig, empty_L, grant_S_L)
begin
if (grant_S_L_sig = '1' and empty_L = '0' and grant_S_L = '0') then
err_grant_S_L_sig_not_empty_L_grant_S_L <= '1';
else
err_grant_S_L_sig_not_empty_L_grant_S_L <= '0';
end if;
end process;
process (grant_S_L_sig, empty_L, grant_S_L)
begin
if ( (grant_S_L_sig = '0' or empty_L = '1') and grant_S_L = '1') then
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L <= '1';
else
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_L checkers
process (grant_L_N_sig, empty_N, grant_L_N)
begin
if (grant_L_N_sig = '1' and empty_N = '0' and grant_L_N = '0') then
err_grant_L_N_sig_not_empty_N_grant_L_N <= '1';
else
err_grant_L_N_sig_not_empty_N_grant_L_N <= '0';
end if;
end process;
process (grant_L_N_sig, empty_N, grant_L_N)
begin
if ( (grant_L_N_sig = '0' or empty_N = '1') and grant_L_N = '1') then
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N <= '1';
else
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N <= '0';
end if;
end process;
process (grant_L_E_sig, empty_E, grant_L_E)
begin
if (grant_L_E_sig = '1' and empty_E = '0' and grant_L_E = '0') then
err_grant_L_E_sig_not_empty_E_grant_L_E <= '1';
else
err_grant_L_E_sig_not_empty_E_grant_L_E <= '0';
end if;
end process;
process (grant_L_E_sig, empty_E, grant_L_E)
begin
if ( (grant_L_E_sig = '0' or empty_E = '1') and grant_L_E = '1') then
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E <= '1';
else
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E <= '0';
end if;
end process;
process (grant_L_W_sig, empty_W, grant_L_W)
begin
if (grant_L_W_sig = '1' and empty_W = '0' and grant_L_W = '0') then
err_grant_L_W_sig_not_empty_W_grant_L_W <= '1';
else
err_grant_L_W_sig_not_empty_W_grant_L_W <= '0';
end if;
end process;
process (grant_L_W_sig, empty_W, grant_L_W)
begin
if ( (grant_L_W_sig = '0' or empty_W = '1') and grant_L_W = '1') then
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W <= '1';
else
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W <= '0';
end if;
end process;
process (grant_L_S_sig, empty_S, grant_L_S)
begin
if (grant_L_S_sig = '1' and empty_S = '0' and grant_L_S = '0') then
err_grant_L_S_sig_not_empty_S_grant_L_S <= '1';
else
err_grant_L_S_sig_not_empty_S_grant_L_S <= '0';
end if;
end process;
process (grant_L_S_sig, empty_S, grant_L_S)
begin
if ( (grant_L_S_sig = '0' or empty_S = '1') and grant_L_S = '1') then
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S <= '1';
else
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S <= '0';
end if;
end process;
process (grant_L_L_sig, empty_L, grant_L_L)
begin
if (grant_L_L_sig = '1' and empty_L = '0' and grant_L_L = '0') then
err_grant_L_L_sig_not_empty_L_grant_L_L <= '1';
else
err_grant_L_L_sig_not_empty_L_grant_L_L <= '0';
end if;
end process;
process (grant_L_L_sig, empty_L, grant_L_L)
begin
if ( (grant_L_L_sig = '0' or empty_L = '1') and grant_L_L = '1') then
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L <= '1';
else
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Final Grant output checkers
-- North
process (grant_N_N_sig, empty_N, grant_N_E_sig, empty_E, grant_N_W_sig, empty_W, grant_N_S_sig, empty_S, grant_N_L_sig, empty_L, grant_N)
begin
if ( ( (grant_N_N_sig = '1' and empty_N = '0' ) or (grant_N_E_sig = '1' and empty_E = '0') or (grant_N_W_sig = '1' and empty_W = '0') or
(grant_N_S_sig = '1' and empty_S = '0') or (grant_N_L_sig = '1' and empty_L = '0') ) and grant_N = '0' ) then
err_grant_signals_not_empty_grant_N <= '1';
else
err_grant_signals_not_empty_grant_N <= '0';
end if;
end process;
process (grant_N_N_sig, empty_N, grant_N_E_sig, empty_E, grant_N_W_sig, empty_W, grant_N_S_sig, empty_S, grant_N_L_sig, empty_L, grant_N)
begin
if ( ( (grant_N_N_sig = '0' or empty_N = '1' ) and (grant_N_E_sig = '0' and empty_E = '1') and (grant_N_W_sig = '0' or empty_W = '1') and
(grant_N_S_sig = '0' or empty_S = '1') and (grant_N_L_sig = '0' or empty_L = '1') ) and grant_N /= '0' ) then
err_not_grant_signals_empty_not_grant_N <= '1';
else
err_not_grant_signals_empty_not_grant_N <= '0';
end if;
end process;
-- East
process (grant_E_N_sig, empty_N, grant_E_E_sig, empty_E, grant_E_W_sig, empty_W, grant_E_S_sig, empty_S, grant_E_L_sig, empty_L, grant_E)
begin
if ( ( (grant_E_N_sig = '1' and empty_N = '0' ) or (grant_E_E_sig = '1' and empty_E = '0') or (grant_E_W_sig = '1' and empty_W = '0') or
(grant_E_S_sig = '1' and empty_S = '0') or (grant_E_L_sig = '1' and empty_L = '0') ) and grant_E = '0' ) then
err_grant_signals_not_empty_grant_E <= '1';
else
err_grant_signals_not_empty_grant_E <= '0';
end if;
end process;
process (grant_E_N_sig, empty_N, grant_E_E_sig, empty_E, grant_E_W_sig, empty_W, grant_E_S_sig, empty_S, grant_E_L_sig, empty_L, grant_E)
begin
if ( ( (grant_E_N_sig = '0' or empty_N = '1' ) and (grant_E_E_sig = '0' and empty_E = '1') and (grant_E_W_sig = '0' or empty_W = '1') and
(grant_E_S_sig = '0' or empty_S = '1') and (grant_E_L_sig = '0' or empty_L = '1') ) and grant_E /= '0' ) then
err_not_grant_signals_empty_not_grant_E <= '1';
else
err_not_grant_signals_empty_not_grant_E <= '0';
end if;
end process;
-- West
process (grant_W_N_sig, empty_N, grant_W_E_sig, empty_E, grant_W_W_sig, empty_W, grant_W_S_sig, empty_S, grant_W_L_sig, empty_L, grant_W)
begin
if ( ( (grant_W_N_sig = '1' and empty_N = '0' ) or (grant_W_E_sig = '1' and empty_E = '0') or (grant_W_W_sig = '1' and empty_W = '0') or
(grant_W_S_sig = '1' and empty_S = '0') or (grant_W_L_sig = '1' and empty_L = '0') ) and grant_W = '0' ) then
err_grant_signals_not_empty_grant_W <= '1';
else
err_grant_signals_not_empty_grant_W <= '0';
end if;
end process;
process (grant_W_N_sig, empty_N, grant_W_E_sig, empty_E, grant_W_W_sig, empty_W, grant_W_S_sig, empty_S, grant_W_L_sig, empty_L, grant_W)
begin
if ( ( (grant_W_N_sig = '0' or empty_N = '1' ) and (grant_W_E_sig = '0' and empty_E = '1') and (grant_W_W_sig = '0' or empty_W = '1') and
(grant_W_S_sig = '0' or empty_S = '1') and (grant_W_L_sig = '0' or empty_L = '1') ) and grant_W /= '0' ) then
err_not_grant_signals_empty_not_grant_W <= '1';
else
err_not_grant_signals_empty_not_grant_W <= '0';
end if;
end process;
-- South
process (grant_S_N_sig, empty_N, grant_S_E_sig, empty_E, grant_S_W_sig, empty_W, grant_S_S_sig, empty_S, grant_S_L_sig, empty_L, grant_S)
begin
if ( ( (grant_S_N_sig = '1' and empty_N = '0' ) or (grant_S_E_sig = '1' and empty_E = '0') or (grant_S_W_sig = '1' and empty_W = '0') or
(grant_S_S_sig = '1' and empty_S = '0') or (grant_S_L_sig = '1' and empty_L = '0') ) and grant_S = '0' ) then
err_grant_signals_not_empty_grant_S <= '1';
else
err_grant_signals_not_empty_grant_S <= '0';
end if;
end process;
process (grant_S_N_sig, empty_N, grant_S_E_sig, empty_E, grant_S_W_sig, empty_W, grant_S_S_sig, empty_S, grant_S_L_sig, empty_L, grant_S)
begin
if ( ( (grant_S_N_sig = '0' or empty_N = '1' ) and (grant_S_E_sig = '0' and empty_E = '1') and (grant_S_W_sig = '0' or empty_W = '1') and
(grant_S_S_sig = '0' or empty_S = '1') and (grant_S_L_sig = '0' or empty_L = '1') ) and grant_S /= '0' ) then
err_not_grant_signals_empty_not_grant_S <= '1';
else
err_not_grant_signals_empty_not_grant_S <= '0';
end if;
end process;
-- Local
process (grant_L_N_sig, empty_N, grant_L_E_sig, empty_E, grant_L_W_sig, empty_W, grant_L_S_sig, empty_S, grant_L_L_sig, empty_L, grant_L)
begin
if ( ( (grant_L_N_sig = '1' and empty_N = '0' ) or (grant_L_E_sig = '1' and empty_E = '0') or (grant_L_W_sig = '1' and empty_W = '0') or
(grant_L_S_sig = '1' and empty_S = '0') or (grant_L_L_sig = '1' and empty_L = '0') ) and grant_L = '0' ) then
err_grant_signals_not_empty_grant_L <= '1';
else
err_grant_signals_not_empty_grant_L <= '0';
end if;
end process;
process (grant_L_N_sig, empty_N, grant_L_E_sig, empty_E, grant_L_W_sig, empty_W, grant_L_S_sig, empty_S, grant_L_L_sig, empty_L, grant_L)
begin
if ( ( (grant_L_N_sig = '0' or empty_N = '1' ) and (grant_L_E_sig = '0' and empty_E = '1') and (grant_L_W_sig = '0' or empty_W = '1') and
(grant_L_S_sig = '0' or empty_S = '1') and (grant_L_L_sig = '0' or empty_L = '1') ) and grant_L /= '0' ) then
err_not_grant_signals_empty_not_grant_L <= '1';
else
err_not_grant_signals_empty_not_grant_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Valid output checkers
process (valid_N, valid_E, valid_W, valid_S, valid_L, grant_N, grant_E, grant_W, grant_S, grant_L)
begin
if (valid_N /= grant_N or valid_E /= grant_E or valid_W /= grant_W or valid_S /= grant_S or valid_L /= grant_L) then
err_grants_valid_not_match <= '1';
else
err_grants_valid_not_match <= '0';
end if;
end process;
END;
|
gpl-3.0
|
quicky2000/top_mandelbrot_1b
|
truncator.vhd
|
1
|
1378
|
--
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity truncator is
Port ( i : in STD_LOGIC_VECTOR (31 downto 0);
o : out STD_LOGIC_VECTOR (15 downto 0));
end truncator;
architecture Behavioral of truncator is
begin
o(15 downto 0) <= i(23 downto 8);
end Behavioral;
|
gpl-3.0
|
julioamerico/prj_crc_ip
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@addr@dec@m1/_primary.vhd
|
3
|
326
|
library verilog;
use verilog.vl_types.all;
entity AddrDecM1 is
port(
addr : in vl_logic_vector(31 downto 0);
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
addrDec : out vl_logic_vector(8 downto 0)
);
end AddrDecM1;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/network_2x2_NI_FI_packet_drop_Rand_SHMU_credit_based_tb.vhd
|
3
|
10835
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--fault injector signals
FI_Add_2_0, FI_Add_0_2: in std_logic_vector(4 downto 0);
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: in std_logic;
FI_Add_3_1, FI_Add_1_3: in std_logic_vector(4 downto 0);
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: in std_logic;
FI_Add_1_0, FI_Add_0_1: in std_logic_vector(4 downto 0);
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: in std_logic;
FI_Add_3_2, FI_Add_2_3: in std_logic_vector(4 downto 0);
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: in std_logic;
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end component;
component NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt");
port( reset : in std_logic;
clk : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end component; --component NoC_Node
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
--fault injector signals
signal FI_Add_2_0, FI_Add_0_2: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0) := (others=>'0');
signal sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: std_logic :='0';
signal FI_Add_3_1, FI_Add_1_3: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0) := (others=>'0');
signal sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: std_logic :='0';
signal FI_Add_1_0, FI_Add_0_1: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0):= (others=>'0');
signal sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: std_logic :='0';
signal FI_Add_3_2, FI_Add_2_3: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0):= (others=>'0');
signal sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: std_logic :='0';
signal link_faults_0 : std_logic_vector(4 downto 0);
signal turn_faults_0 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_0 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_0 : std_logic_vector(3 downto 0);
signal Reconfig_command_0 : std_logic;
signal link_faults_1 : std_logic_vector(4 downto 0);
signal turn_faults_1 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_1 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_1 : std_logic_vector(3 downto 0);
signal Reconfig_command_1 : std_logic;
signal link_faults_2 : std_logic_vector(4 downto 0);
signal turn_faults_2 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_2 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_2 : std_logic_vector(3 downto 0);
signal Reconfig_command_2 : std_logic;
signal link_faults_3 : std_logic_vector(4 downto 0);
signal turn_faults_3 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_3 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_3 : std_logic_vector(3 downto 0);
signal Reconfig_command_3 : std_logic;
--------------
constant clk_period : time := 1 ns;
signal reset, not_reset, clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
--fault injector signals
--FI vertical signals
FI_Add_2_0, FI_Add_0_2,
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0,
FI_Add_3_1, FI_Add_1_3,
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1,
--FI horizontal signals
FI_Add_1_0, FI_Add_0_1,
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0,
FI_Add_3_2, FI_Add_2_3,
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2,
-- should be connected to NI
link_faults_0, turn_faults_0, Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
link_faults_1, turn_faults_1, Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
link_faults_2, turn_faults_2, Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
link_faults_3, turn_faults_3, Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
not_reset <= not reset;
-- connecting the PEs
PE_0: NoC_Node
generic map( current_address => 0,
stim_file => "code_0.txt",
log_file => "output_0.txt")
port map( not_reset, clk,
credit_in => credit_out_L_0,
valid_out => valid_in_L_0,
TX => RX_L_0,
credit_out => credit_in_L_0,
valid_in => valid_out_L_0,
RX => TX_L_0,
link_faults => link_faults_0,
turn_faults => turn_faults_0,
Rxy_reconf_PE => Rxy_reconf_PE_0,
Cx_reconf_PE => Cx_reconf_PE_0,
Reconfig_command => Reconfig_command_0
);
PE_1: NoC_Node
generic map( current_address => 1,
stim_file => "code_1.txt",
log_file => "output_1.txt")
port map( not_reset, clk,
credit_in => credit_out_L_1,
valid_out => valid_in_L_1,
TX => RX_L_1,
credit_out => credit_in_L_1,
valid_in => valid_out_L_1,
RX => TX_L_1,
link_faults => link_faults_1,
turn_faults => turn_faults_1,
Rxy_reconf_PE => Rxy_reconf_PE_1,
Cx_reconf_PE => Cx_reconf_PE_1,
Reconfig_command => Reconfig_command_1
);
PE_2: NoC_Node
generic map( current_address => 2,
stim_file => "code_2.txt",
log_file => "output_2.txt")
port map( not_reset, clk,
credit_in => credit_out_L_2,
valid_out => valid_in_L_2,
TX => RX_L_2,
credit_out => credit_in_L_2,
valid_in => valid_out_L_2,
RX => TX_L_2,
link_faults => link_faults_2,
turn_faults => turn_faults_2,
Rxy_reconf_PE => Rxy_reconf_PE_2,
Cx_reconf_PE => Cx_reconf_PE_2,
Reconfig_command => Reconfig_command_2
);
PE_3: NoC_Node
generic map( current_address => 3,
stim_file => "code_3.txt",
log_file => "output_3.txt")
port map( not_reset, clk,
credit_in => credit_out_L_3,
valid_out => valid_in_L_3,
TX => RX_L_3,
credit_out => credit_in_L_3,
valid_in => valid_out_L_3,
RX => TX_L_3,
link_faults => link_faults_3,
turn_faults => turn_faults_3,
Rxy_reconf_PE => Rxy_reconf_PE_3,
Cx_reconf_PE => Cx_reconf_PE_3,
Reconfig_command => Reconfig_command_3
);
-- connecting the fault generators
gen_fault(sta0_1_0, sta1_1_0, FI_Add_1_0, 56,1138666221,1960809222);
gen_fault(sta0_0_1, sta1_0_1, FI_Add_0_1, 64,751500117,1520623220);
gen_fault(sta0_2_0, sta1_2_0, FI_Add_2_0, 70,1730004934,1255590821);
gen_fault(sta0_0_2, sta1_0_2, FI_Add_0_2, 45,332821241,1061603537);
gen_fault(sta0_3_1, sta1_3_1, FI_Add_3_1, 53,750959745,841254867);
gen_fault(sta0_1_3, sta1_1_3, FI_Add_1_3, 46,1831451386,1574401837);
gen_fault(sta0_3_2, sta1_3_2, FI_Add_3_2, 57,929911280,1401056219);
gen_fault(sta0_2_3, sta1_2_3, FI_Add_2_3, 59,322054547,1380824540);
end;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/logic_builtin.vhd
|
9
|
30405
|
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|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/ScanRegister_for_SIBFCX.vhd
|
3
|
2121
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end ScanRegister_for_SIBFCX;
architecture ScanRegister_arch of ScanRegister_for_SIBFCX is
signal and_ce, and_se, and_ue: std_logic;
signal internal_si: std_logic_vector(Size downto 0);
signal cs_reg: std_logic_vector(Size-1 downto 0);
signal u_reg: std_logic_vector(Size-1 downto 0):=ResetValue;
signal se_mux, ce_mux, ue_mux: std_logic_vector(Size-1 downto 0);
begin
-- Basic Combinational Logic
and_ce <= CE and SEL;
and_se <= SE and SEL;
and_ue <= UE and SEL;
internal_si(Size) <= SI;
-- TDR Shift Register Core
SCAN_REGISTER: for i in Size-1 downto 0 generate
-- Multiplexers
se_mux(i) <= internal_si(i+1) when and_se = '1' else cs_reg(i);
ce_mux(i) <= CaptureSource(i) when and_ce = '1' else se_mux(i);
ue_mux(i) <= cs_reg(i) when and_ue = '1' else u_reg(i);
-- Flip-Flops
cs_reg(i) <= ce_mux(i) when TCK'event and TCK = '1';
process(RST,TCK)
begin
if RST = '1' then
u_reg(i) <= ResetValue(Size-1-i);
elsif TCK'event and TCK = '0' then
u_reg(i) <= ue_mux(i);
end if;
end process;
-- Internal Connections
internal_si(i) <= cs_reg(i);
end generate;
-- Outputs
MSBLSB_SO : if BitOrder = "MSBLSB" generate
SO <= internal_si(SOSource);
end generate;
LSBMSB_SO : if BitOrder = "LSBMSB" generate
SO <= internal_si(Size-1-SOSource);
end generate;
ScanRegister_out <= u_reg;
ue_mux_out <= ue_mux;
end ScanRegister_arch;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_status_flags_sshft.vhd
|
9
|
22948
|
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`protect end_protected
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_xilinx_2.vhd
|
3
|
181455
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram_2 is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 8);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram_2 is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"8c343c00af03af270003278f0300ac008f34af0000000014008f8fafaf03af27",
INIT_05 => X"008f000c2400142480008f0010af03afaf270003278f0300ac008f3c00103000",
INIT_06 => X"008f8f0010af24af03afaf270003278f8f030000140080008f000c000080af24",
INIT_07 => X"03000004008faf24008f000c0024008f0010000c0024008f00102c008faf3000",
INIT_08 => X"0c000080af24008f0010af27000c8f008f002727afafaf03afaf270003278f8f",
INIT_09 => X"3c03af270003278f8f030000140080008fa0248faf24008f0014248024008f00",
INIT_0A => X"0000000003278f8f030000008c3c0010000c0003afaf270003278f0330008c34",
INIT_0B => X"243c000c343c243c24000c343c243c24000c243c000c243c000c243c03afaf27",
INIT_0C => X"24243c243c243caf243caf24000c24243c243c243caf243caf24000c243c000c",
INIT_0D => X"000c343c243c243c243caf243caf24000c343c243c243c243caf243caf24000c",
INIT_0E => X"243c000c000c243c000c243c000c000c243c000c243c000c000c243c000c243c",
INIT_0F => X"3c000c243c0010000c243c0014008c3c000c243c000c243c000c000c243c000c",
INIT_10 => X"af240010af24afaf03afaf270003278f8f0300000c24000c0024008c3c000c24",
INIT_11 => X"0c8f24000010008f001400008f8faf24008f0010af001400000014008f8f0010",
INIT_12 => X"24008faf240010008f8c002400008f3c000c0024008c002400008f3c000c2400",
INIT_13 => X"0c243c0010ac3c24008c3c000c243c0014248f001428008faf24008f000c24af",
INIT_14 => X"0087000c24000c8faf00008f870010a7afafafaf03afaf270003278f8f030000",
INIT_15 => X"0087a730240097af240010008f8c00008f000087000c24000c00008c00008f00",
INIT_16 => X"000c243c0010ac3c24008c3c000c243c0014248f000c8f2400000c243c001428",
INIT_17 => X"87000c24000c8faf0000008f870010a7afafafafaf03afaf270003278f8f0300",
INIT_18 => X"87a730240097af240010008f8c00008f000087000c24000c00008c00008f0000",
INIT_19 => X"008c00008f000087000c24000c8faf0000008f2400870010a7000c2400142800",
INIT_1A => X"000c240014280087a730240097af240010008f8c00008f000087000c24000c00",
INIT_1B => X"000c00008c00008f0000343c87000c24000c8faf0000000014008f870010a724",
INIT_1C => X"24000c240014280087a730240097af240010008f8c00008f0000343c87000c24",
INIT_1D => X"0c24000c00008c00008f0000343c87000c24000c8faf00000014008f870010a7",
INIT_1E => X"2400000c243c0014280087a730240097af240010008f8c00008f0000343c8700",
INIT_1F => X"af270003278f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c8f",
INIT_20 => X"0c24000c00008c002400008f3c000c24000c8faf00008f8f0010afafaf2403af",
INIT_21 => X"008f8f0010af000c24001428008faf24008faf240010008f8c002400008f3c00",
INIT_22 => X"10008f8c002400008f3c000c24000c00008c002400008f3c000c24000c8faf00",
INIT_23 => X"0010ac3c24008c3c000c243c0014248f000c243c001428008faf24008faf2400",
INIT_24 => X"8f0000008fa000278f0000008f0010afaf03afaf270003278f8f0300000c243c",
INIT_25 => X"00af008000278f0010af001428008faf24008fac008f002700008fa400270000",
INIT_26 => X"10008f8c002400008f3c000c24000c0024008c002400008f3c000c24000c8f24",
INIT_27 => X"24000c0024008c002400008f3c000c24000c8f2400af0084002700008faf2400",
INIT_28 => X"3c000c24000c8f2400af008c002700008faf240010008f8c002400008f3c000c",
INIT_29 => X"8faf24008faf240010008f8c002400008f3c000c24000c0024008c002400008f",
INIT_2A => X"8f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c243c00142800",
INIT_2B => X"000c24000c00008c3c000c24000c8faf00008f8fafaf24af2403afaf27000327",
INIT_2C => X"8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f8c3c",
INIT_2D => X"008f8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f",
INIT_2E => X"240010008f8c243c000c24000c00008c243c000c24000c8faf00008faf240010",
INIT_2F => X"008faf240010008f8c243c000c24000c00008c243c000c24000c8faf24008faf",
INIT_30 => X"0014248f000c243caf240010008f8c243c000c00008c243c000c24000c8faf24",
INIT_31 => X"28008c3caf03af27000003278f8f0300000c243c0010ac3c24008c3c000c243c",
INIT_32 => X"a324af03af270003278f0324001000ac3c24008c3cac008f0024003c8c3c0010",
INIT_33 => X"14003c8c340010240010248c3c00100083a4248fa3001000102400100094008f",
INIT_34 => X"af270003278f0324a4008fa30010ac3cac243cac3cac008c3c240018008c3c00",
INIT_35 => X"0010240010248c3c00100083a4248fa3001000102400100094008fa324afaf03",
INIT_36 => X"3cac0024003c8c248c3c001028008c3c0004008f0010008faf008c34af008c34",
INIT_37 => X"af008fafaf03af270003278f0324a4008fa30010ac243cac3cac3cac3c24008c",
INIT_38 => X"10afafafafaf03afaf270003278f038f00140080a00080af24008faf24008f00",
INIT_39 => X"8f8faf240010af240010248f0004008fa3001428008faf24008fa02400278f00",
INIT_3A => X"008f001028008faf0000000014008f8faf00000014008f8f0010af24af000000",
INIT_3B => X"1000008c008f00008f240014008fa000278f0000302430008f00100000302430",
INIT_3C => X"8f0010008c008fa02400278faf24008f0014248f0000100004008faf24008f00",
INIT_3D => X"2700248c008f0010ac008f00008f24000c8f0000008f2700100000008f248c00",
INIT_3E => X"af03af270003278f0300ac343c343cafaf03af270003278f8f0300000c8f0000",
INIT_3F => X"008fafaf03af270003278f038f0014008faf00008f24008faf302c008f0010af"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"42420200c4a0bebd00e0bdbec0004300c302c2000007624000c2c3c5c4a0bebd",
INIT_05 => X"00c20000040062024300c20000c4a0bebfbd00e0bdbec0004300c30200404200",
INIT_06 => X"00c2c30000c202c4a0bebfbd00e0bdbebfc0000040004200c20000400042c343",
INIT_07 => X"c000004100c2c24200c20000404200c200000000404200c200404200c2c24243",
INIT_08 => X"00400042c34300c20000c2c20000c440c660c2c3c6c5c4a0bebfbd00e0bdbebf",
INIT_09 => X"02a0bebd00e0bdbebfc0000040004200c24303c2c24200c2006202434200c200",
INIT_0A => X"00000000e0bdbebfc002020042020040000000a0bebfbd00e0bdbec042004242",
INIT_0B => X"44020000440245020600004402450206000044020000440200004402a0bebfbd",
INIT_0C => X"04450246024702a24202a202000004450246024702a24202a202000044020000",
INIT_0D => X"00004402450246024702a24202a20200004402450246024702a24202a2020000",
INIT_0E => X"4402000000004402000044020000000044020000440200000000440200004402",
INIT_0F => X"0200004402000000004402004000420200004402000044020000000044020000",
INIT_10 => X"c2020000c202c0c0a0bebfbd00e0bdbebfc00000000400004005004202000044",
INIT_11 => X"00c40500004000c200406200c2c3c24200c20000c000400007624000c2c30000",
INIT_12 => X"4200c2c202006200c24362420300c30200004005004262420300c30200000400",
INIT_13 => X"004402000043024300420200004402006202c300404200c2c24200c2000004c2",
INIT_14 => X"00c20000040000c4c24300c3c20000c0c0c6c5c4a0bebfbd00e0bdbebfc00000",
INIT_15 => X"00c2c2424200c2c202006200c2436200c30200c200000400004000426200c302",
INIT_16 => X"00004402000043024300420200004402006202c30000c4050000004402004042",
INIT_17 => X"c20000040000c4c2006200c2c30000c0c0c7c6c5c4a0bebfbd00e0bdbebfc000",
INIT_18 => X"c2c2424200c2c202006200c2436200c30200c200000400004000426200c30200",
INIT_19 => X"00426200c30200c20000040000c4c2006200c24300c20000c000000400404200",
INIT_1A => X"00000400404200c2c2424200c2c202006200c2436200c30200c2000004000040",
INIT_1B => X"00004000426200c302624202c30000040000c4c2000007624000c3c20000c202",
INIT_1C => X"0200000400404200c2c2424200c2c202006200c2436200c302624202c3000004",
INIT_1D => X"000400004000426200c302624202c30000040000c4c20007624000c3c20000c2",
INIT_1E => X"05000000440200404200c2c2424200c2c202006200c2436200c302624202c300",
INIT_1F => X"bfbd00e0bdbebfc00000004402000043024300420200004402006202c30000c4",
INIT_20 => X"0004000040004262420300c3020000040000c4c26200c2c30000c0c0c202a0be",
INIT_21 => X"00c2c30000c000000400404200c2c24200c2c202006200c24362420300c30200",
INIT_22 => X"6200c24362420300c302000004000040004262420300c3020000040000c4c262",
INIT_23 => X"000043024300420200004402006202c30000440200404200c2c24200c2c20200",
INIT_24 => X"c2030200c24382c4c2030200c20000c0c0a0bebfbd00e0bdbebfc00000004402",
INIT_25 => X"00c2004262c3c20000c000404200c2c24200c24300c362c30200c24382c40200",
INIT_26 => X"6200c24362420300c30200000400004005004262420300c3020000040000c405",
INIT_27 => X"0400004005004262420300c3020000040000c40500c2004262c30200c2c20200",
INIT_28 => X"020000040000c40500c2004262c30200c2c202006200c24362420300c3020000",
INIT_29 => X"c2c24200c2c202006200c24362420300c30200000400004005004262420300c3",
INIT_2A => X"bebfc00000004402000043024300420200004402006202c30000440200404200",
INIT_2B => X"0000040000400042020000040000c4c26200c2c3c0c202c202a0bebfbd00e0bd",
INIT_2C => X"434202000004000040004242020000040000c4c26200c2c3c202006200c24302",
INIT_2D => X"00c2434202000004000040004242020000040000c4c26200c2c3c202006200c2",
INIT_2E => X"02006200c2434202000004000040004242020000040000c4c20200c2c2020062",
INIT_2F => X"00c2c202006200c2434202000004000040004242020000040000c4c24200c2c2",
INIT_30 => X"006202c300004402c202006200c2434202000040004242020000040000c4c242",
INIT_31 => X"42004202c4a0bebd0000e0bdbebfc00000004402000043024300420200004402",
INIT_32 => X"c202c4a0bebd00e0bdbec0020000004302430042024300c36242030243020040",
INIT_33 => X"40620243020000020062024302004000c24303c2c000000043030040004200c2",
INIT_34 => X"bebd00e0bdbec0024000c2c00000400243030240024300630302004000420200",
INIT_35 => X"0000020062024302004000c24303c2c000000043030040004200c2c202c0c4a0",
INIT_36 => X"02438242040243024402004042004202004000c2004000c2c2004202c2004202",
INIT_37 => X"c200c2c5c4a0bebd00e0bdbec0024000c2c00000430302400240024302430042",
INIT_38 => X"00c0c7c6c5c4a0bebfbd00e0bdbec0c200400042430063c46400c3c34300c200",
INIT_39 => X"c2c3c2020000c202006202c3004100c2c000404200c2c24200c2430362c3c200",
INIT_3A => X"00c200404200c2c2000007624000c3c2c20007624000c3c20000c202c2006200",
INIT_3B => X"4062004200c26200c203004000c26283c4c3020242424200c200000202424242",
INIT_3C => X"c20040004200c2430362c3c2c24200c2006202c3000000004100c2c24200c200",
INIT_3D => X"c362034200c200004300c26200c2030000c4406200c2c30040628200c2044300",
INIT_3E => X"c4a0bebd00e0bdbec0004363034202c5c4a0bebd00e0bdbebfc0000000c44062",
INIT_3F => X"00c2c5c4a0bebd00e0bdbec0c2004000c2c26200c34200c2c2424200c20000c0"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000800ff1800350035003300b200",
INIT_01 => X"000000000000000000000000000000000000072000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000200000f000ff00000000e800000000800010100000000000000000f000ff",
INIT_05 => X"0000000000000000000000000000f00000ff00000000e8000000002000ff0000",
INIT_06 => X"0000000000000000f00000ff0000000000e80000ff0000000000002000000000",
INIT_07 => X"e80000ff000000ff000000002000000000000000200000000000000000000010",
INIT_08 => X"0020000000000000000000000007002800380000000000f00000ff0000000000",
INIT_09 => X"20f000ff0000000000e80000ff0000000000000000ff000000000000ff000000",
INIT_0A => X"0000000000000000e8161600002000ff000100f00000ff00000000e800000000",
INIT_0B => X"2a00000256922700000002561227000000002a0000002a0000002a00f00000ff",
INIT_0C => X"032800280028000028000000000200280028002800002800000000002a000000",
INIT_0D => X"0002230029002900290000290000000002430028002900290000290000000002",
INIT_0E => X"2a00000400002a0000002a00000500002a0000002a00000300002a0000002a00",
INIT_0F => X"0000002b00000000002b00000000330000002b0000002b00000200002a000000",
INIT_10 => X"0000000000000000f00000ff0000000000e8000000000001200030330000002b",
INIT_11 => X"010000300000000000ff10000000000000000000000000100000000000000000",
INIT_12 => X"0000000000000000000010241800000000012000300010241800000000000000",
INIT_13 => X"002b00000033000000330000002b000000000000ff0300000000000000000000",
INIT_14 => X"0000000000000000001000000000000000000000f00000ff0000000000e80000",
INIT_15 => X"000000ff00000000000000000000100000100000000000000020000010000010",
INIT_16 => X"00002b00000033000000330000002b0000000000000100003000002b0000ff00",
INIT_17 => X"000000000000000010000000000000000000000000f00000ff0000000000e800",
INIT_18 => X"0000ff0000000000000000000010000010000000000000002000001000001000",
INIT_19 => X"0000100000100000000000000000001000000001000000000000000000ff0000",
INIT_1A => X"00000000ff00000000ff00000000000000000000100000100000000000000020",
INIT_1B => X"00002000001000001010ff3f0000000000000000101000000000000000000000",
INIT_1C => X"0000000000ff00000000ff000000000000000000001000001010ff3f00000000",
INIT_1D => X"000000002000001000001010ff3f000000000000000010000000000000000000",
INIT_1E => X"003000002b0000ff00000000ff000000000000000000001000001010ff3f0000",
INIT_1F => X"00ff0000000000e80000002b00000033000000330000002b0000000000000100",
INIT_20 => X"000000002000001029180000000000000000000010000000000000000012f000",
INIT_21 => X"00000000000000000000ff000000000000000000000000000010291800000000",
INIT_22 => X"00000000102a180000000000000000200000102a180000000000000000000010",
INIT_23 => X"000033000000330000002b000000000000002c0000ff00000000000000000000",
INIT_24 => X"001c1c0000001000001e1e000000000000f00000ff0000000000e80000002b00",
INIT_25 => X"3000000010000000000000ff0000000000000000000010001000000010001000",
INIT_26 => X"00000000102c18000000000000000120003000102c1800000000000000010000",
INIT_27 => X"00000120003000102c1800000000000000010000300000001000100000000000",
INIT_28 => X"000000000001000030000000100010000000000000000000102c180000000000",
INIT_29 => X"000000000000000000000000102c18000000000000000120003000102c180000",
INIT_2A => X"0000e80000002b00000033000000330000002b000000000000002c0000ff0000",
INIT_2B => X"000000000020002c0000000000000000100000000000430012f00000ff000000",
INIT_2C => X"002c0000000000002000002c0000000000000000100000000000000000002c00",
INIT_2D => X"0000002c0000000000002000002c000000000000000010000000000000000000",
INIT_2E => X"0000000000002c0000000000002000002c000000000000000010000000000000",
INIT_2F => X"0000000000000000002c0000000000002000002c000000000000000000000000",
INIT_30 => X"0000000000002c00000000000000002c0000002000002c0000000000000000ff",
INIT_31 => X"0000330000f000ff000000000000e80000002b00000033000000330000002b00",
INIT_32 => X"000000f000ff00000000e8ff0000103300000033000000001035180033000000",
INIT_33 => X"0010400080000000000000320000000000000000000000000000000000000000",
INIT_34 => X"00ff00000000e8000000000000ff33003300003200000035007f000000330000",
INIT_35 => X"00000000000033000000000000000000000000000000000000000000000000f0",
INIT_36 => X"000010352000007f330000000000330000000000000000000000008000000080",
INIT_37 => X"0000000000f000ff00000000e8000000000000ff330000330032003300000033",
INIT_38 => X"000000000000f00000ff00000000e80000ff0000000000000000000000000000",
INIT_39 => X"000000ff0000000000000000000000000000ff00000000000000000010000000",
INIT_3A => X"0000000000000000101000000000000000100000000000000000000000100000",
INIT_3B => X"0010000000001800000000000000001800001616000000000000001616000000",
INIT_3C => X"00000000000000000010000000ff00000000ff0000000000ff000000ff000000",
INIT_3D => X"0010000000000000000000180000000006002810000000000010100000000000",
INIT_3E => X"00f000ff00000000e80000fc0000200000f000ff0000000000e8000006002810",
INIT_3F => X"00000000f000ff00000000e80000ff000000100000ff00000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e00ac04fd2a001800b0000000f001",
INIT_01 => X"504c4844403c3834302c2824201c18141000cc2410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"00200000082504f80008100c2500000000100012100d1b020014101410250cf0",
INIT_05 => X"001800980d00040a000018001318251014e80008080425000000080000fa0200",
INIT_06 => X"001020001e101c2025181ce00008181014250000e90000001800982500001801",
INIT_07 => X"250000e0001010fc0010009825570014000700982530001400090a0014140f06",
INIT_08 => X"9825000010010010001810140016a025a42514a8a8a4a025989c60000820181c",
INIT_09 => X"002504f80008a0989c250000e400000010000d1010ff001000080a00ff001000",
INIT_0A => X"000000000818101425030000000000fd003c00251014e8000808042501000020",
INIT_0B => X"8000008878348c0002008878340c000100ae680000ae540000ae3c0025181ce0",
INIT_0C => X"2184009c00b40010d800140200e7070c0024003c00106000140100ae680000ae",
INIT_0D => X"00e7450174008c00a40010c800140400e72105fc0014002c00105000140300e7",
INIT_0E => X"f800008b00ae680000aee000006300ae680000aec80000fe00ae680000aea800",
INIT_0F => X"0000ae5000001300ae4800000700100000ae380000ae2800001400ae680000ae",
INIT_10 => X"1403004b10031c18252024d8000820181c250000980a0005250a25100000ae5c",
INIT_11 => X"05100a250026001400eb2a00101414020014000b140004100d1a020014100011",
INIT_12 => X"0100181c0100030010002170800018000005250a250021708000180000983a00",
INIT_13 => X"ae9c00000510000100100000ae7400000d011c00b2e800101002001000982018",
INIT_14 => X"001000983a00d4181807002810002c1014302c28252024d80008282024250000",
INIT_15 => X"001010ff0100101401000300180021002c80001000982000d425000021002c80",
INIT_16 => X"00aee400000510000100100000aed800000d01140005300a2500aec40000d120",
INIT_17 => X"1000983a00d418181218002810002d101434302c28252024d800082820242500",
INIT_18 => X"1010ff0100101401000300180021002c80001000982000d425000021002c8000",
INIT_19 => X"000021003080001000983a00d4181812180028230010002f1000980a00d00600",
INIT_1A => X"00980a00ce06001010ff0100101401000300180021003080001000982000d425",
INIT_1B => X"00d42500002100348021ffff1000983a00d4181812100d1a0200281000341001",
INIT_1C => X"0100980a00c90a001010ff010010140100030018002100348021ffff10009820",
INIT_1D => X"982000d42500002100388021ffff1000983a00d41818100d1a02002810003310",
INIT_1E => X"0a2500aef00000ca0a001010ff010010140100030018002100388021ffff1000",
INIT_1F => X"24d80008282024250000aee400000510000100100000aed800000d011400053c",
INIT_20 => X"982000d425000021ec8000100000983a00d41c1c21001018002b101418342520",
INIT_21 => X"001018002b1000980a00d20a00101001001014010003001c0021ec8000100000",
INIT_22 => X"03001c0021148000100000982000d425000021148000100000983a00d41c1c23",
INIT_23 => X"000510000100100000aed800000d011400ae140000d20a001010010010140100",
INIT_24 => X"10030000100c21101003000010001f1014259094680008282024250000aee400",
INIT_25 => X"2518000c21101000871000de0a0010100100103c001021108000101c21104000",
INIT_26 => X"030018002158800010000098200005250a250021588000100000983a0005180a",
INIT_27 => X"200005250a250021588000100000983a0005180a2518001c2110400010140100",
INIT_28 => X"0000983a0005180a2518003c2110800010140100030018002158800010000098",
INIT_29 => X"10100100101401000300180021588000100000980a0005250a25002158800010",
INIT_2A => X"9094250000aee400000510000100100000aed800000d011400ae300000760a00",
INIT_2B => X"00982000d42500800000983a00d41c1c240018141018211434252024d8000898",
INIT_2C => X"04800000982000d4250004800000983a00d41c1c2500181410010003001c8000",
INIT_2D => X"001c08800000982000d4250008800000983a00d41c1c2600181410010003001c",
INIT_2E => X"010003001c0c800000982000d425000c800000983a00d41c1c27001410010003",
INIT_2F => X"001410010003001c10800000982000d4250010800000983a00d41c1c12001410",
INIT_30 => X"000d011000ae400010010003001c14800000d4250014800000983a00d41c1cee",
INIT_31 => X"0f002400082504f8000008282024250000aee400000510000100100000aed800",
INIT_32 => X"000110250cf00008080425ff0002252400010024000000082130800024000013",
INIT_33 => X"0b24000000001f01000401f0000006000000321000002a000732000600000010",
INIT_34 => X"14e80008100c25030000100000d82c00280100f00000003000fc000600240000",
INIT_35 => X"003401000401280000060000005d1800003f00075d0006000000180001041825",
INIT_36 => X"00002170800000fc200000100f00200000160008001a00040800000004000004",
INIT_37 => X"0000101410250cf00008181425030000180000c32c01002800f0002000010020",
INIT_38 => X"0a104c48444025383cc00008100c250000f20000000000140100141001001000",
INIT_39 => X"184018ff0003180100050a48000500402f00f30f001010010010102021101000",
INIT_3A => X"0010000a0a00101c12100d1b02001c4810100d1b02001c48003e140e1c121800",
INIT_3B => X"0b2a0000004c2300140f000c001c102110140300ff57ff001000080300ff30ff",
INIT_3C => X"4c000b0000004c102d21101414ff0014000aff1800000200c0001414ff001400",
INIT_3D => X"20230f00004c000c00004c2300140f00f844252100142000122a2300140f0000",
INIT_3E => X"10250cf000080804250000180360000c082504f8000840383c250000f8442521",
INIT_3F => X"00080c082504f80008100c250000f1001010240010ff001000ff010000000d00"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"00008f8faf000c8faf0000008f00008fafaf03afaf270003278f030000008f00",
INIT_01 => X"8f0000003c8fac008fac008fac008f30008fafafafafaf03af270003278f8f03",
INIT_02 => X"0010248f001428008faf24008faf00008f0030003000008f8c008f0010afac00",
INIT_03 => X"10240014008f8f001024001000008f8c008f001024001000008f8c008f001024",
INIT_04 => X"03af270003278f0300008faf03af270003278f0300001024001028008c008f00",
INIT_05 => X"343c000c243c000c343c34af24afaf03afafaf27000003278f030000343c8faf",
INIT_06 => X"240004008c340010ac24ac343c24ae000c242424000c243cac008f343caf008c",
INIT_07 => X"008fae000c242424000c24000c0024008f000c243c0014248faf000c8faf008c",
INIT_08 => X"00000000000003278f8f8f0300000c00142c008fac008f24af000c8f0010af24",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000102040912000000",
INIT_0F => X"fffffffffffffffffffffffffffffffffffffffffffffefcf9f2e4c992000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000606060606050000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000010101010101000000",
INIT_14 => X"3d3d3d3d3d3d676620740a0a747320650a000000000000000000000000000000",
INIT_15 => X"694c7363726d69546e616f6269546f6175206467730a00696920746c6c67730a",
INIT_16 => X"4e490a007420696c54004546455000454d500a6469540030617261736d657061",
INIT_17 => X"544c4c0a0a53200a4c2000454e490a0044414f4c41454e490a0044414f4c4145",
INIT_18 => X"0000000000000000000054204945540a54204d0a542043422f440a2054494920",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000102040912000000000000000000000000000000",
INIT_1F => X"fffffffffffffffffffffefcf9f2e4c992000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000606060606050000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000010101010101000000000000000000000000000000",
INIT_24 => X"7566542055000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000072756570695300736e61756369670a0a727475526e2068616e",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"6200c2c3c20000c4c2430300c30200c2c5c4a0bebfbd00e0bdbec0620200c202",
INIT_01 => X"c240026202c34000c24000c24300c24300c2c0c7c6c5c4a0bebd00e0bdbebfc0",
INIT_02 => X"006202c300404200c2c24200c2c24300c2404202424300c24300c20000c04300",
INIT_03 => X"0002006200c2c300000200404300c24300c200000200404300c24300c2000002",
INIT_04 => X"a0bebd00e0bdbec00200c2c4a0bebd00e0bdbec000000002004042004200c200",
INIT_05 => X"4202000044020000440205c202c5c4a0b0bebfbd0000e0bdbec002624202c3c4",
INIT_06 => X"0200400042020000400243630302020000040510000044024300c34202c20042",
INIT_07 => X"00c20200000405100000040000400500c200004402006202c3c20000c4c20042",
INIT_08 => X"000000000000e0bdb0bebfc000000000404200c24300c302c20000c40000c242",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"00000000000000000000000000000000010204091224489123468d1a34000000",
INIT_0F => X"fffffffffffffffffffffffffffffefcf9f2e4c99224489123468d1a34000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000003030303030300000000000000",
INIT_12 => X"02010000000000000000000000000000010101020515100b0500fb1a150f0a05",
INIT_13 => X"0000000000000000000000000000000000000000000001504f4e4d4c4b050403",
INIT_14 => X"0a3d3d3d3d3d0a747369540a656d707247000000000000000000000000000000",
INIT_15 => X"6e69736379656e65737470696e656e63622f6920740a006f762f69697420740a",
INIT_16 => X"554d0a0073746c206f00444144410053414c0a6f6e6500306e206c206220726c",
INIT_17 => X"4949540a0a45500a4546005347460a0021534e414c52554d0a0021494e414c52",
INIT_18 => X"0000000000000000000020544f52200a20544f0a2054545420450a00454f562f",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"00000000010204091224489123468d1a34000000000000000000000000000000",
INIT_1F => X"fffffefcf9f2e4c99224489123468d1a34000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000003030303030300000000000000000000000000000000000000",
INIT_22 => X"00000000010101020515100b0500fb1a150f0a05000000000000000000000000",
INIT_23 => X"0000000000000000000001504f4e4d4c4b050403020100000000000000000000",
INIT_24 => X"20203a5441000000000000000000000000000000000000000000000000000000",
INIT_25 => X"00000000000000206d74616e65007420746e6f6e690a006b2074542074696420",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"100000000000070000101f00001000000000f00000ff00000000e8101400001f",
INIT_01 => X"001814100f000000000000000000000000000000000000f000ff0000000000e8",
INIT_02 => X"0000000000ff0000000000000000100000180010001000000000000000000000",
INIT_03 => X"0000000000000000000000001000000000000000000000100000000000000000",
INIT_04 => X"f000ff00000000e817000000f000ff00000000e8100000000000000000000000",
INIT_05 => X"00200000320000007801e100000000f0000000ff0000000000e81010ff1f0000",
INIT_06 => X"7f00000000800000007f00ff0f7f00000700007f000032000000000020000000",
INIT_07 => X"000000000700007f000000000120003000000032000000000000000800000000",
INIT_08 => X"0000000000000000000000e810000100ff0000000000007f0000080000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0101010101010101010101010101010000000000000000000000000000000000",
INIT_0B => X"0202020201010101010101010101010101010101010101010101010101010101",
INIT_0C => X"0202020202020202020202020202020202020202020202020202020202020202",
INIT_0D => X"0303030303030303030303030303030303030303030303030303030303030202",
INIT_0E => X"0000000000000000010204091224489123468d1a3468d1a2458a152b56030303",
INIT_0F => X"fffffffffffffefcf9f2e4c99224489123468d1a3468d1a2458a152b56000000",
INIT_10 => X"0000000000000000000000000000000000080808080707000000000000ffffff",
INIT_11 => X"000000000000000000000000000000000101039e9b9794918e0f0c0906030000",
INIT_12 => X"46230000000000000000000095a8c0e00d50c1a1439e5b17d4914e4f0cc98643",
INIT_13 => X"1212121212000000000000000000202429303a48619123c7a4815d3a17b08d69",
INIT_14 => X"003d3d3d3d3d0069686e650073616c6165121212121212121212121212121212",
INIT_15 => X"67730a65206d67730a69657467730a7474206e616954006e69206f63696d6954",
INIT_16 => X"4d4550003a65656674002149215300542041006e6773003020746c73656e696c",
INIT_17 => X"4f43494d0044410044410054205453000a53205443204d4550000a4c20544320",
INIT_18 => X"0000000000000000000000454e414f420045524d00454f5253524100534e4920",
INIT_19 => X"00000000000000000000000000000000000000000000000000001212ed515302",
INIT_1A => X"0101010000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0101010101010101010101010101010101010101010101010101010101010101",
INIT_1C => X"0202020202020202020202020202020202020202020202020101010101010101",
INIT_1D => X"0303030303030303030303030303030303030202020202020202020202020202",
INIT_1E => X"1224489123468d1a3468d1a2458a152b56030303030303030303030303030303",
INIT_1F => X"9224489123468d1a3468d1a2458a152b56000000000000000000000001020409",
INIT_20 => X"0000000000080808080707000000000000fffffffffffffffffffefcf9f2e4c9",
INIT_21 => X"000000000101039e9b9794918e0f0c0906030000000000000000000000000000",
INIT_22 => X"95a8c0e00d50c1a1439e5b17d4914e4f0cc98643000000000000000000000000",
INIT_23 => X"0000202429303a48619123c7a4815d3a17b08d69462300000000000000000000",
INIT_24 => X"6379204552121212121212121212121212121212121212121200000000000000",
INIT_25 => X"0000000000000000622063676e000a7469696d676e4200737770205568732072",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"250014101400dc101025400020400024242025181ce000080804252500000c00",
INIT_01 => X"20250224ff1000001c000018000014ff0010041c181410250cf0000820181c25",
INIT_02 => X"0004010400ea080000000100000421000425ff2b010700000000140013000000",
INIT_03 => X"0c04000400181c00140300042a002400001c001f0200042a0024000018002a01",
INIT_04 => X"2504f80008080425420008082504f80008100c25250002050004020000002000",
INIT_05 => X"500000ae6c000080407d0010013c38252c3034c80000080804254224feff0808",
INIT_06 => X"fc002e000000003300fc00fffffc0000f90303fc00aea8000000143000140000",
INIT_07 => X"00100000f90303fc00980a0005250a251000aecc00001a011c1c009118180000",
INIT_08 => X"0b070503000008382c30342525006000ca650010000020fc20009d1800091001",
INIT_09 => X"9d97958b89837f716d6b67656159534f4947433d3b352f2b29251f1d1713110d",
INIT_0A => X"5b514b3d393733251b19150f0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a3",
INIT_0B => X"231d0b09fdf7f3ebe7dfd3cfcdc9c1bbb7b1afa5a399918d857f7b756f67615d",
INIT_0C => X"efe7e3ddd7cfc5bdb3aba5a195938d878381776b69655f5957514b413b39332d",
INIT_0D => X"d1cbc7b9b3ada9a1978f8b7773716d5f5b5955473d3b37352b291d130501f9f5",
INIT_0E => X"010204091224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78e5dfd7",
INIT_0F => X"f9f2e4c99224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78000000",
INIT_10 => X"070001020301010000000101010102030718110a03fcf5231c150e0700fffefc",
INIT_11 => X"0000010303010100010059647285a0c80b90212807e6c5a483a5846342210007",
INIT_12 => X"8a4500030103030001000100ae6472856dc80b90212807e6c5a483a584634221",
INIT_13 => X"38373635340005010300010001005d689c8b41d117a245c8833ef9b46f5914cf",
INIT_14 => X"003d3d3d3d3d006e696773007420616c6e2b2c2d2e2f30313233343d3c3b3a39",
INIT_15 => X"20740073616f2074006f722020740069727367646e65000a73646e6170756e65",
INIT_16 => X"422052002073646161000a4c00530020545300652074000a3168656d72756d20",
INIT_17 => X"4e4150550021530021490020544948000a4550495543422052000a4546495543",
INIT_18 => X"0908070605040302010000535354504900535945005352415520440054205344",
INIT_19 => X"6159534f4947433d3b352f2b29251f1d1713110d0b07050300002246cb153520",
INIT_1A => X"0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a39d97958b89837f716d6b6765",
INIT_1B => X"cdc9c1bbb7b1afa5a399918d857f7b756f67615d5b514b3d393733251b19150f",
INIT_1C => X"95938d878381776b69655f5957514b413b39332d231d0b09fdf7f3ebe7dfd3cf",
INIT_1D => X"73716d5f5b5955473d3b37352b291d130501f9f5efe7e3ddd7cfc5bdb3aba5a1",
INIT_1E => X"3468d1a2458a152b56ac59b367cf9e3c78e5dfd7d1cbc7b9b3ada9a1978f8b77",
INIT_1F => X"3468d1a2458a152b56ac59b367cf9e3c78000000010204091224489123468d1a",
INIT_20 => X"010102030718110a03fcf5231c150e0700fffefcf9f2e4c99224489123468d1a",
INIT_21 => X"7285a0c80b90212807e6c5a483a5846342210007070001020301010000000101",
INIT_22 => X"ae6472856dc80b90212807e6c5a483a584634221000001030301010001005964",
INIT_23 => X"01005d689c8b41d117a245c8833ef9b46f5914cf8a4500030103030001000100",
INIT_24 => X"616f4953542b2c2d2e2f30313233343d3c3b3a39383736353400050103000100",
INIT_25 => X"0000000100000000656e6b2064000a656f636d206e6500216f756f41652c7465",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
gpl-3.0
|
1995parham/FPGA-Homework
|
HW-4/src/p7/p7.vhd
|
1
|
810
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 05-05-2016
-- Module Name: p7.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity p7 is
end entity;
architecture rtl of p7 is
component ring_counter
generic (N : integer := 4);
port (clk, start : in std_logic;
Q : out std_logic_vector(N - 1 downto 0));
end component;
for all:ring_counter use entity work.ring_counter;
signal clk : std_logic := '0';
signal start : std_logic := '1';
signal Q : std_logic_vector(3 downto 0);
begin
clk <= not clk after 50 ns;
start <= '0' after 75 ns;
m:ring_counter port map (clk, start, Q);
end architecture;
|
gpl-3.0
|
julioamerico/prj_crc_ip
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@client_@f@m/_primary.vhd
|
3
|
868
|
library verilog;
use verilog.vl_types.all;
entity Client_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
lastCycle : in vl_logic;
DS_FM_HTRANS1 : out vl_logic;
DS_FM_HREADY : in vl_logic;
DS_FM_HRESP : in vl_logic;
addrClkEn : out vl_logic;
dataClkEn : out vl_logic;
hRegReq : in vl_logic;
hRegWrite : in vl_logic;
hFMInvalidXfer : in vl_logic;
pRegReq : in vl_logic;
pRegWrite : in vl_logic;
pFMInvalidXfer : in vl_logic;
clientReady : out vl_logic;
clientError : out vl_logic;
dataPhAck : out vl_logic
);
end Client_FM;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/compare.vhd
|
9
|
11685
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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Qw1TzRjzCw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6912)
`protect data_block
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QY9afbya/54/OxrzTRCi
`protect end_protected
|
gpl-3.0
|
julioamerico/prj_crc_ip
|
src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/mti/user_vlog/COREAHBLITE_LIB/@b@f@m_@a@h@b@s@l@a@v@e@e@x@t/_primary.vhd
|
2
|
2196
|
library verilog;
use verilog.vl_types.all;
entity BFM_AHBSLAVEEXT is
generic(
AWIDTH : integer := 10;
DEPTH : integer := 256;
EXT_SIZE : integer := 2;
INITFILE : string := " ";
ID : integer := 0;
ENFUNC : integer := 0;
ENFIFO : integer := 0;
TPD : integer := 1;
DEBUG : integer := -1
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector;
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic;
EXT_EN : in vl_logic;
EXT_WR : in vl_logic;
EXT_RD : in vl_logic;
EXT_ADDR : in vl_logic_vector;
EXT_DATA : inout vl_logic_vector(31 downto 0);
TXREADY : out vl_logic;
RXREADY : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AWIDTH : constant is 1;
attribute mti_svvh_generic_type of DEPTH : constant is 1;
attribute mti_svvh_generic_type of EXT_SIZE : constant is 1;
attribute mti_svvh_generic_type of INITFILE : constant is 1;
attribute mti_svvh_generic_type of ID : constant is 1;
attribute mti_svvh_generic_type of ENFUNC : constant is 1;
attribute mti_svvh_generic_type of ENFIFO : constant is 1;
attribute mti_svvh_generic_type of TPD : constant is 1;
attribute mti_svvh_generic_type of DEBUG : constant is 1;
end BFM_AHBSLAVEEXT;
|
gpl-3.0
|
1995parham/FPGA-Homework
|
HW-1/src/p4-1-2/p4-2.vhd
|
1
|
1843
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 04-03-2016
-- Module Name: p4-2.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity sixteen_bit_comparator is
port (a, b : in std_logic_vector(15 downto 0);
l, g, e : in std_logic;
eq, gt, lt : out std_logic);
end entity sixteen_bit_comparator;
architecture structural of sixteen_bit_comparator is
signal a0_b0_eq, a0_b0_gt, a0_b0_lt : std_logic;
signal a1_b1_eq, a1_b1_gt, a1_b1_lt : std_logic;
signal a2_b2_eq, a2_b2_gt, a2_b2_lt : std_logic;
signal a3_b3_eq, a3_b3_gt, a3_b3_lt : std_logic;
entity four_bit_comparator is
port (a, b : in std_logic_vector(3 downto 0);
l, g, e : in std_logic;
eq, gt, lt : out std_logic);
end entity four_bit_comparator;
for all:four_bit_comparator use entity work.four_bit_comparator;
begin
c0: four_bit_comparator port map (a(3 downto 0), b(3 downto 0), open, open, open,
a0_b0_eq, a0_b0_gt, a0_b0_lt);
c1: four_bit_comparator port map (a(7 downto 4), b(7 downto 4), open, open, open,
a1_b1_eq, a1_b1_gt, a1_b1_lt);
c2: four_bit_comparator port map (a(11 downto 8), b(11 downto 8), open, open, open,
a2_b2_eq, a2_b2_gt, a2_b2_lt);
c3: four_bit_comparator port map (a(15 downto 12), b(15 downto 12), open, open, open,
a3_b3_eq, a3_b3_gt, a3_b3_lt);
eq <= a3_b3_eq and a2_b2_eq and a1_b1_eq and a0_b0_eq;
gt <= a3_b3_gt or (a2_b2_gt and a3_b3_eq) or (a1_b1_gt and a2_b2_eq and a3_b3_eq)
or (a0_b0_gt and a1_b1_eq and a2_b2_eq and a3_b3_eq);
lt <= a3_b3_lt or (a2_b2_lt and a3_b3_eq) or (a1_b1_lt and a2_b2_eq and a3_b3_eq)
or (a0_b0_lt and a1_b1_eq and a2_b2_eq and a3_b3_eq);
end architecture structural;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/LBDR_packet_drop.vhd
|
3
|
5789
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end LBDR_packet_drop;
architecture behavior of LBDR_packet_drop is
signal Cx, Cx_in: std_logic_vector(3 downto 0);
signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0);
signal reconfig_cx, reconfig_cx_in: std_logic;
signal Rxy, Rxy_in: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
signal grants: std_logic;
signal packet_drop, packet_drop_in: std_logic;
signal ReConf_FF_in, ReConf_FF_out: std_logic;
begin
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Rxy <= Rxy_reconf;
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Temp_Cx <= (others => '0');
ReConf_FF_out <= '0';
reconfig_cx <= '0';
packet_drop <= '0';
elsif clk'event and clk = '1' then
Rxy <= Rxy_in;
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
ReConf_FF_out <= ReConf_FF_in;
Cx <= Cx_in;
reconfig_cx <= reconfig_cx_in;
Temp_Cx <= Temp_Cx_in;
packet_drop <= packet_drop_in;
end if;
end process;
-- The combionational part
process(Rxy_reconf, ReConf_FF_out, Rxy, Reconfig, flit_type, grants, empty)begin
if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then
Rxy_in <= Rxy_reconf;
ReConf_FF_in <= '0';
else
Rxy_in <= Rxy;
if Reconfig = '1' then
ReConf_FF_in <= '1';
else
ReConf_FF_in <= ReConf_FF_out;
end if;
end if;
end process;
process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants) begin
Temp_Cx_in <= Temp_Cx;
if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then
Cx_in <= Temp_Cx;
reconfig_cx_in <= '0';
else
Cx_in <= Cx;
if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx;
else
reconfig_cx_in <= reconfig_cx;
end if;
end if;
end process;
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop) begin
packet_drop_in <= packet_drop;
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
if dst_addr = cur_addr then
Req_L_in <= '1';
else
Req_L_in <= Req_L_FF; -- Added to remove latch possibility. Correct ??
end if;
if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or
(((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or
(((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or
(((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and dst_addr /= cur_addr then
packet_drop_in <= '1';
end if;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
if flit_type = "100" and empty = '0' then
if packet_drop = '1' then
packet_drop_in <= '0';
end if;
end if;
end process;
packet_drop_order <= packet_drop;
END;
|
gpl-3.0
|
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