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hoglet67/AtomBusMon
|
src/T6502/T65_MCode.vhd
|
4
|
45786
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.T65_Pack.all;
entity T65_MCode is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in T_Lcycle;
P : in std_logic_vector(7 downto 0);
LCycle : out T_Lcycle;
ALU_Op : out T_ALU_Op;
Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX
Set_Addr_To : out T_Set_Addr_To; -- PC Adder,S,AD,BA
Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end T65_MCode;
architecture rtl of T65_MCode is
signal Branch : std_logic;
signal ALUmore:std_logic;
begin
with IR(7 downto 5) select
Branch <= not P(Flag_N) when "000",
P(Flag_N) when "001",
not P(Flag_V) when "010",
P(Flag_V) when "011",
not P(Flag_C) when "100",
P(Flag_C) when "101",
not P(Flag_Z) when "110",
P(Flag_Z) when others;
process (IR, MCycle, P, Branch, Mode)
begin
lCycle <= Cycle_1;
Set_BusA_To <= Set_BusA_To_ABC;
Set_Addr_To <= Set_Addr_To_PBR;
Write_Data <= Write_Data_DL;
Jump <= (others => '0');
BAAdd <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
Inc_S <= '0';
Dec_S <= '0';
LDA <= '0';
LDP <= '0';
LDX <= '0';
LDY <= '0';
LDS <= '0';
LDDI <= '0';
LDALU <= '0';
LDAD <= '0';
LDBAL <= '0';
LDBAH <= '0';
SaveP <= '0';
Write <= '0';
AddY <= '0';
ALUmore <= '0';
case IR(7 downto 5) is
when "100" => -- covers $8x,$9x
case IR(1 downto 0) is
when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C
Set_BusA_To <= Set_BusA_To_Y;
if IR(4 downto 2)="111" then -- SYA ($9C)
Write_Data <= Write_Data_YB;
else
Write_Data <= Write_Data_Y;
end if;
when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
Set_BusA_To <= Set_BusA_To_X;
if IR(4 downto 2)="111" then -- SXA ($9E)
Write_Data <= Write_Data_XB;
else
Write_Data <= Write_Data_X;
end if;
when "11" => -- IR: $83,$87,$8B,$8F,$93,$97,$9B,$9F
if IR(4 downto 2)="110" then -- SHS ($9B)
Set_BusA_To <= Set_BusA_To_AAX;
LDS <= '1';
else
Set_BusA_To <= Set_BusA_To_ABC;
end if;
if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B)
Write_Data <= Write_Data_AXB;
else
Write_Data <= Write_Data_AX;
end if;
when others => -- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
Write_Data <= Write_Data_ABC;
end case;
when "101" => -- covers $Ax,$Bx
Set_BusA_To <= Set_BusA_To_DI;
case IR(1 downto 0) is
when "00" => -- IR: $A0,$A4,$A8,$AC,$B0,$B4,$B8,$BC
if IR(4) /= '1' or IR(2) /= '0' then--only for $A0,$A4,$A8,$AC or $B4,$BC
LDY <= '1';
end if;
when "01" => -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
LDA <= '1';
when "10" => -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
LDX <= '1';
when others => -- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF (undoc)
LDX <= '1';
LDA <= '1';
if IR(4 downto 2)="110" then -- LAS (BB)
Set_BusA_To <= Set_BusA_To_S;
LDS <= '1';
end if;
end case;
when "110" => -- covers $Cx,$Dx
case IR(1 downto 0) is
when "00" => -- IR: $C0,$C4,$C8,$CC,$D0,$D4,$D8,$DC
if IR(4) = '0' then--only for $Cx
LDY <= '1';
end if;
Set_BusA_To <= Set_BusA_To_Y;
when others => -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD, $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE, $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when "111" => -- covers $Ex,$Fx
case IR(1 downto 0) is
when "00" => -- IR: $E0,$E4,$E8,$EC,$F0,$F4,$F8,$FC
if IR(4) = '0' then -- only $Ex
LDX <= '1';
end if;
Set_BusA_To <= Set_BusA_To_X;
when others => -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD, $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE, $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when others =>
end case;
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers $0x-$7x, $Cx-$Fx x=2,3,6,7,A,B,E,F, for 6502 undocs
if IR=x"eb" then
Set_BusA_To <= Set_BusA_To_ABC; -- alternate SBC ($EB)
else
Set_BusA_To <= Set_BusA_To_DI;
end if;
end if;
case IR(4 downto 0) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $08,$28,$48,$68,$88,$A8,$C8,$E8
-- $0A,$2A,$4A,$6A,$8A,$AA,$CA,$EA
-- $18,$38,$58,$78,$98,$B8,$D8,$F8
-- $1A,$3A,$5A,$7A,$9A,$BA,$DA,$FA
when "00000" | "01000" | "01010" | "11000" | "11010" =>
-- Implied
case IR is
when x"00" =>
-- BRK ($00)
lCycle <= Cycle_6;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_2 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_P;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
Jump <= "10";
when others =>
end case;
when x"20" => -- JSR ($20)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"40" => -- RTI ($40)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Set_BusA_To <= Set_BusA_To_DI;
when Cycle_4 =>
LDP <= '1';
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"60" => -- RTS ($60)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_4 =>
Jump <= "10";
when Cycle_5 =>
Jump <= "01";
when others =>
end case;
when x"08" | x"48" | x"5a" | x"da" => -- PHP, PHA, PHY*, PHX* ($08,$48,$5A,$DA)
lCycle <= Cycle_2;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case MCycle is
when Cycle_1 =>
if mode/="00" or IR(1)='0' then --wrong on 6502
Write <= '1';
case IR(7 downto 4) is
when "0000" =>
Write_Data <= Write_Data_P;
when "0100" =>
Write_Data <= Write_Data_ABC;
when "0101" =>
if Mode /= "00" then
Write_Data <= Write_Data_Y;
else
Write <= '0';
end if;
when "1101" =>
if Mode /= "00" then
Write_Data <= Write_Data_X;
else
Write <= '0';
end if;
when others =>
end case;
Set_Addr_To <= Set_Addr_To_SP;
end if;
when Cycle_2 =>
Dec_S <= '1';
when others =>
end case;
when x"28" | x"68" | x"7a" | x"fa" => -- PLP, PLA, PLY*, PLX* ($28,$68,$7A,$FA)
lCycle <= Cycle_3;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case IR(7 downto 4) is
when "0010" =>--plp
LDP <= '1';
when "0110" =>--pla
LDA <= '1';
when "0111" =>--ply not for 6502
if Mode /= "00" then
LDY <= '1';
end if;
when "1111" =>--plx not for 6502
if Mode /= "00" then
LDX <= '1';
end if;
when others =>
end case;
case MCycle is
when Cycle_sync =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
SaveP <= '1';
end if;
when Cycle_1 =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
end if;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_DI;
when others =>
end case;
when x"a0" | x"c0" | x"e0" => -- LDY, CPY, CPX ($A0,$C0,$E0)
-- Immediate
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when x"88" => -- DEY ($88)
LDY <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_Y;
when others =>
end case;
when x"ca" => -- DEX ($CA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_X;
when others =>
end case;
when x"1a" | x"3a" => -- INC*, DEC* ($1A,$3A)
if Mode /= "00" then
LDA <= '1'; -- A
else
lCycle <= Cycle_1;--undoc 2 cycle nop
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"0a" | x"2a" | x"4a" | x"6a" => -- ASL, ROL, LSR, ROR ($0A,$2A,$4A,$6A)
LDA <= '1'; -- A
Set_BusA_To <= Set_BusA_To_ABC;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"8a" | x"98" => -- TYA, TXA ($8A,$98)
LDA <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"aa" | x"a8" => -- TAX, TAY ($AA,$A8)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
when x"9a" => -- TXS ($9A)
LDS <= '1'; -- will be set only in Cycle_sync
when x"ba" => -- TSX ($BA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"80" => -- undoc: NOP imm2 ($80)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when others => -- others ($0A,$EA, $18,$38,$58,$78,$B8,$C8,$D8,$E8,$F8)
case MCycle is
when Cycle_sync =>
when others =>
end case;
end case;
-- IR: $01,$21,$41,$61,$81,$A1,$C1,$E1
-- $03,$23,$43,$63,$83,$A3,$C3,$E3
when "00001" | "00011" =>
-- Zero Page Indexed Indirect (d,x)
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($01,$21,$41,$61,$C1,$E1,$03,$23,$43,$63,$C3,$E3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
BAAdd <= "01";
LDBAL <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5=>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
Write <= '1';
LDDI<='1';
end if;
when Cycle_6=>
Write <= '1';
LDALU<='1';
SaveP<='1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $09,$29,$49,$69,$89,$A9,$C9,$E9
when "01001" =>
-- Immediate
if IR(7 downto 5)/="100" then -- all except undoc. NOP imm2 (not $89)
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
-- IR: $0B,$2B,$4B,$6B,$8B,$AB,$CB,$EB
when "01011" =>
if Mode="00" then
-- Immediate undoc for 6500
case IR(7 downto 5) is
when "010"|"011"|"000"|"001" =>--ALR,ARR
Set_BusA_To<=Set_BusA_To_DA;
LDA <= '1';
when "100" =>--XAA
Set_BusA_To<=Set_BusA_To_DAX;
LDA <= '1';
when "110" =>--SAX (SBX)
Set_BusA_To<=Set_BusA_To_AAX;
LDX <= '1';
when "101" =>--OAL
Set_BusA_To<=Set_BusA_To_DAO;
LDA <= '1';
when others=>
LDA <= '1';
end case;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
end if;
-- IR: $02,$22,$42,$62,$82,$A2,$C2,$E2
-- $12,$32,$52,$72,$92,$B2,$D2,$F2
when "00010" | "10010" =>
-- Immediate, SKB, KIL
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
if IR = "10100010" then
-- LDX ($A2)
Jump <= "01";
LDX <= '1'; -- Moved, Lorenz test showed X changing on SKB (NOPx)
elsif IR(7 downto 4)="1000" or IR(7 downto 4)="1100" or IR(7 downto 4)="1110" then
-- undoc: NOP imm2
Jump <= "01";
else
-- KIL !!!
end if;
when others =>
end case;
-- IR: $04,$24,$44,$64,$84,$A4,$C4,$E4
when "00100" =>
-- Zero Page
lCycle <= Cycle_2;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--24=BIT zpg
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then--84=sty zpg (the only write in this group)
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
-- IR: $05,$25,$45,$65,$85,$A5,$C5,$E5
-- $06,$26,$46,$66,$86,$A6,$C6,$E6
-- $07,$27,$47,$67,$87,$A7,$C7,$E7
when "00101" | "00110" | "00111" =>
-- Zero Page
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
lCycle <= Cycle_4;
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
if Mode="00" and IR(0)='1' then
Set_BusA_To<=Set_BusA_To_ABC;
ALUmore <= '1'; -- For undoc DCP/DCM support
LDDI <= '1'; -- requires DIN to reflect DOUT!
end if;
when others =>
end case;
else
lCycle <= Cycle_2;
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
end if;
-- IR: $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "01100" =>
-- Absolute
if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then -- JMP ($4C,$6C)
if IR(5) = '0' then
lCycle <= Cycle_2;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
when Cycle_2 =>
Jump <= "10";
when others =>
end case;
else
lCycle <= Cycle_4;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
LDBAL <= '1';
when Cycle_2 =>
LDBAH <= '1';
if Mode /= "00" then
Jump <= "10";
end if;
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
end if;
when Cycle_3 =>
LDDI <= '1';
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
BAAdd <= "01"; -- DB Inc
else
Jump <= "01";
end if;
when Cycle_4 =>
Jump <= "10";
when others =>
end case;
end if;
else
lCycle <= Cycle_3;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--2c-BIT
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--80, sty, the only write in this group
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $0D,$2D,$4D,$6D,$8D,$AD,$CD,$ED
-- $0E,$2E,$4E,$6E,$8E,$AE,$CE,$EE
-- $0F,$2F,$4F,$6F,$8F,$AF,$CF,$EF
when "01101" | "01110" | "01111" =>
-- Absolute
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then -- ($0E,$2E,$4E,$6E,$CE,$EE, $0F,$2F,$4F,$6F,$CF,$EF)
-- Read-Modify-Write
lCycle <= Cycle_5;
if Mode="00" and IR(0) = '1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
Write <= '1';
LDALU <= '1';
SaveP <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" then -- all but $8D, $8E, $8F, $AD, $AE, $AF ($AD does set LDA in an earlier case statement)
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--8d
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
when "10000" =>
-- Relative
-- This circuit dictates when the last
-- microcycle occurs for the branch depending on
-- whether or not the branch is taken and if a page
-- is crossed...
if (Branch = '1') then
lCycle <= Cycle_3; -- We're done @ T3 if branching...upper
-- level logic will stop at T2 if no page cross
-- (See the Break signal)
else
lCycle <= Cycle_1;
end if;
-- This decodes the current microcycle and takes the
-- proper course of action...
case MCycle is
-- On the T1 microcycle, increment the program counter
-- and instruct the upper level logic to fetch the offset
-- from the Din bus and store it in the data latches. This
-- will be the last microcycle if the branch isn't taken.
when Cycle_1 =>
Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-- from microcycle T0.
LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route
-- the Din bus to the memory data latch (DL)
-- so that the branch offset is fetched.
-- In microcycle T2, tell the logic in the top level to
-- add the offset. If the most significant byte of the
-- program counter (i.e. the current "page") does not need
-- updating, we are done here...the Break signal at the
-- T65.vhd level takes care of that...
when Cycle_2 =>
Jump <= "11"; -- Tell the PC Jump logic to use relative mode.
PCAdd <= '1'; -- This tells the PC adder to update itself with
-- the current offset recently fetched from
-- memory.
-- The following is microcycle T3 :
-- The program counter should be completely updated
-- on this cycle after the page cross is detected.
-- We don't need to do anything here...
when Cycle_3 =>
when others => null; -- Do nothing.
end case;
-- IR: $11,$31,$51,$71,$91,$B1,$D1,$F1
-- $13,$33,$53,$73,$93,$B3,$D3,$F3
when "10001" | "10011" =>
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($11,$31,$51,$71,$D1,$F1,$13,$33,$53,$73,$D3,$F3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDBAL <= '1';
BAAdd <= "01"; -- DB Inc
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" then
Write <= '1';
elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_6 =>
LDALU<='1';
SaveP<='1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To<=Set_BusA_To_ABC;
when others =>
end case;
-- IR: $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $15,$35,$55,$75,$95,$B5,$D5,$F5
-- $16,$36,$56,$76,$96,$B6,$D6,$F6
-- $17,$37,$57,$77,$97,$B7,$D7,$F7
when "10100" | "10101" | "10110" | "10111" =>
-- Zero Page, X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($16,$36,$56,$76,$D6,$F6, $17,$37,$57,$77,$D7,$F7)
-- Read-Modify-Write
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then -- The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
if Mode="00" and IR(0)='1' then
LDDI<='1';
end if;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" and IR(0)='1' then -- dont LDA on undoc skip
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
-- Added this check for Y reg. use, added undocs
if (IR(3 downto 1) = "011") then -- ($16,$36,$56,$76,$96,$B6,$D6,$F6,$17,$37,$57,$77,$97,$B7,$D7,$F7)
AddY <= '1';
end if;
if IR(7 downto 5) = "100" then -- ($14,$34,$15,$35,$16,$36,$17,$37) the only write instruction
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 => null;
when others =>
end case;
end if;
-- IR: $19,$39,$59,$79,$99,$B9,$D9,$F9
-- $1B,$3B,$5B,$7B,$9B,$BB,$DB,$FB
when "11001" | "11011" =>
-- Absolute Y
lCycle <= Cycle_4;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_6;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then--99/9b
Write <= '1';
elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 => -- just for undoc
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_5 =>
Write <= '1';
LDALU<='1';
Set_Addr_To <= Set_Addr_To_BA;
SaveP<='1';
when Cycle_6 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
-- $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD
-- $1E,$3E,$5E,$7E,$9E,$BE,$DE,$FE
-- $1F,$3F,$5F,$7F,$9F,$BF,$DF,$FF
when "11100" | "11101" | "11110" | "11111" =>
-- Absolute X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($1E,$3E,$5E,$7E,$DE,$FE, $1F,$3F,$5F,$7F,$DF,$FF)
-- Read-Modify-Write
lCycle <= Cycle_6;
if Mode="00" and IR(0)='1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_X;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
end if;
when others =>
end case;
else -- ($1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC, $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD, $9E,$BE,$9F,$BF)
lCycle <= Cycle_4;--Or 3 if not page crossing
if IR(7 downto 6) /= "10" then
if Mode/="00" or IR(4)='0' or IR(1 downto 0)/="00" then
LDA <= '1';
end if;
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
-- special case $BE which uses Y reg as index!!
if(IR(7 downto 6)="10" and IR(4 downto 1)="1111") then
Set_BusA_To <= Set_BusA_To_Y;
else
Set_BusA_To <= Set_BusA_To_X;
end if;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then -- ($9E,$9F)
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
when others =>
end case;
end if;
when others =>
end case;
end process;
process (IR, MCycle, Mode,ALUmore)
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
case IR(1 downto 0) is
when "00" =>
case IR(4 downto 2) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $04,$24,$44,$64,$84,$A4,$C4,$E4
-- $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "000" | "001" | "011" =>
case IR(7 downto 5) is
when "110" | "111" => -- CP ($C0,$C4,$CC,$E0,$E4,$EC)
ALU_Op <= ALU_OP_CMP;
when "101" => -- LD ($A0,$A4,$AC)
ALU_Op <= ALU_OP_EQ2;
when "001" => -- BIT ($20,$24,$2C - $20 is ignored, as its a jmp)
ALU_Op <= ALU_OP_BIT;
when others => -- other, NOP/ST ($x0,$x4,$xC)
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $08,$28,$48,$68,$88,$A8,$C8,$E8
when "010" =>
case IR(7 downto 5) is
when "111" | "110" => -- IN ($C8,$E8)
ALU_Op <= ALU_OP_INC;
when "100" => -- DEY ($88)
ALU_Op <= ALU_OP_DEC;
when others => -- LD
ALU_Op <= ALU_OP_EQ2;
end case;
-- IR: $18,$38,$58,$78,$98,$B8,$D8,$F8
when "110" =>
case IR(7 downto 5) is
when "100" => -- TYA ($98)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
-- $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
when others =>
case IR(7 downto 5) is
when "101" => -- LD ($B0,$B4,$BC)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
end case;
when "01" => -- OR
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $01,$05,$09,$0D,$11,$15,$19,$1D
ALU_Op<=ALU_OP_OR;
when 1=> -- IR: $21,$25,$29,$2D,$31,$35,$39,$3D
ALU_Op<=ALU_OP_AND;
when 2=> -- IR: $41,$45,$49,$4D,$51,$55,$59,$5D
ALU_Op<=ALU_OP_EOR;
when 3=> -- IR: $61,$65,$69,$6D,$71,$75,$79,$7D
ALU_Op<=ALU_OP_ADC;
when 4=>-- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=> -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=> -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD
ALU_Op<=ALU_OP_CMP;
when others=> -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD
ALU_Op<=ALU_OP_SBC;
end case;
when "10" =>
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $02,$06,$0A,$0E,$12,$16,$1A,$1E
ALU_Op<=ALU_OP_ASL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00011010,$1A -> INC acc, not on 6502
ALU_Op <= ALU_OP_INC;
end if;
when 1=> -- IR: $22,$26,$2A,$2E,$32,$36,$3A,$3E
ALU_Op<=ALU_OP_ROL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00111010,$3A -> DEC acc, not on 6502
ALU_Op <= ALU_OP_DEC;
end if;
when 2=> -- IR: $42,$46,$4A,$4E,$52,$56,$5A,$5E
ALU_Op<=ALU_OP_LSR;
when 3=> -- IR: $62,$66,$6A,$6E,$72,$76,$7A,$7E
ALU_Op<=ALU_OP_ROR;
when 4=> -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
ALU_Op<=ALU_OP_BIT;
if IR(4 downto 2) = "010" then -- 10001010, $8A -> TXA
ALU_Op <= ALU_OP_EQ2;
else -- 100xxx10, $82,$86,$8E,$92,$96,$9A,$9E
ALU_Op <= ALU_OP_EQ1;
end if;
when 5=> -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=> -- IR: $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE
ALU_Op<=ALU_OP_DEC;
when others=> -- IR: $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE
ALU_Op<=ALU_OP_INC;
end case;
when others => -- "11" undoc double alu ops
case(to_integer(unsigned(IR(7 downto 5)))) is
-- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF
when 5 =>
if IR=x"bb" then--LAS
ALU_Op <= ALU_OP_AND;
else
ALU_Op <= ALU_OP_EQ2;
end if;
-- IR: $03,$07,$0B,$0F,$13,$17,$1B,$1F
-- $23,$27,$2B,$2F,$33,$37,$3B,$3F
-- $43,$47,$4B,$4F,$53,$57,$5B,$5F
-- $63,$67,$6B,$6F,$73,$77,$7B,$7F
-- $83,$87,$8B,$8F,$93,$97,$9B,$9F
-- $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
-- $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
when others =>
if IR=x"6b" then -- ARR
ALU_Op<=ALU_OP_ARR;
elsif IR=x"8b" then -- ARR
ALU_Op<=ALU_OP_XAA; -- we can't use the bit operation as we don't set all flags...
elsif IR=x"0b" or IR=x"2b" then -- ANC
ALU_Op<=ALU_OP_ANC;
elsif IR=x"eb" then -- alternate SBC
ALU_Op<=ALU_OP_SBC;
elsif ALUmore='1' then
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_OR;
when 1=>
ALU_Op<=ALU_OP_AND;
when 2=>
ALU_Op<=ALU_OP_EOR;
when 3=>
ALU_Op<=ALU_OP_ADC;
when 4=>
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=>
ALU_Op<=ALU_OP_CMP;
when others=>
ALU_Op<=ALU_OP_SBC;
end case;
else
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_ASL;
when 1=>
ALU_Op<=ALU_OP_ROL;
when 2=>
ALU_Op<=ALU_OP_LSR;
when 3=>
ALU_Op<=ALU_OP_ROR;
when 4=>
ALU_Op<=ALU_OP_BIT;
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=>
ALU_Op<=ALU_OP_DEC;
if IR(4 downto 2)="010" then -- $6B
ALU_Op<=ALU_OP_SAX; -- special SAX (SBX) case
end if;
when others=>
ALU_Op<=ALU_OP_INC;
end case;
end if;
end case;
end case;
end process;
end;
|
gpl-3.0
|
fbelavenuto/msx1fpga
|
src/audio/vm2413/slotcounter.vhd
|
2
|
2460
|
--
-- SlotCounter.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
--
-- modified by t.hara
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SlotCounter is
generic (
delay : integer
);
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : out std_logic_vector( 4 downto 0 );
stage : out std_logic_vector( 1 downto 0 )
);
end entity;
architecture rtl of SlotCounter is
signal ff_count : std_logic_vector( 6 downto 0 );
begin
process (reset, clk)
begin
if reset = '1' then
ff_count <= "1000111" - delay;
elsif rising_edge(clk) then
if clkena ='1' then
if ff_count = "1000111" then -- 71
ff_count <= (others => '0');
else
ff_count <= ff_count + 1;
end if;
end if;
end if;
end process;
stage <= ff_count(1 downto 0); -- 0`3 ÅzÂ
slot <= ff_count(6 downto 2); -- 0`17 ÅzÂ
end architecture;
|
gpl-3.0
|
hoglet67/AtomBusMon
|
src/AlanD/R65Cx2.vhd
|
1
|
70463
|
-- -----------------------------------------------------------------------
--
-- This is a table driven 65Cx2 core by A.Daly
-- This is a derivative of the excellent FPGA64 core see below
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity R65C02 is
port (
reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
nwe : out std_logic;
sync : out std_logic;
sync_irq : out std_logic;
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0)
);
end R65C02;
-- Store Zp (3) => fetch, cycle2, cycleEnd
-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (3) => fetch, cycle2, cycleJump
-- Jmp (ind) (6) => fetch, cycle2, cycle3, cycleRead, cycleRead2, cycleJump
-- Jmp (ind,x) (6) => fetch, cycle2, cycle3, cycleRead, cycleRead2, cycleJump
-- Brk (7) => fetch, cycle2, stack2, stack3, stack4, cycleRead2, cycleJump
-- -----------------------------------------------------------------------
architecture Behavioral of R65C02 is
-- Statemachine
type cpuCycles is (
opcodeFetch, -- New opcode is read and registers updated
cycle2,
cycle3,
cyclePreIndirect,
cycleIndirect,
cycleBranchTaken,
cycleBranchPage,
cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
cycleRead, -- Read cycle
cycleRead2, -- Second read cycle after page-boundary crossing.
cycleRmw, -- Calculate ALU output for read-modify-write instr.
cyclePreWrite, -- Cycle before write when doing indexed addressing.
cycleWrite, -- Write cycle for zeropage or absolute addressing.
cycleStack1,
cycleStack2,
cycleStack3,
cycleStack4,
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd
);
signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean;
signal processIrq : std_logic;
signal nmiReg : std_logic;
signal nmiEdge : std_logic;
signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
signal soReg : std_logic; -- SO pin edge detection
-- Opcode decoding
constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2;
constant opcUpdateS : integer := 3;
constant opcUpdateN : integer := 4;
constant opcUpdateV : integer := 5;
constant opcUpdateD : integer := 6;
constant opcUpdateI : integer := 7;
constant opcUpdateZ : integer := 8;
constant opcUpdateC : integer := 9;
constant opcSecondByte : integer := 10;
constant opcAbsolute : integer := 11;
constant opcZeroPage : integer := 12;
constant opcIndirect : integer := 13;
constant opcStackAddr : integer := 14; -- Push/Pop address
constant opcStackData : integer := 15; -- Push/Pop status/data
constant opcJump : integer := 16;
constant opcBranch : integer := 17;
constant indexX : integer := 18;
constant indexY : integer := 19;
constant opcStackUp : integer := 20;
constant opcWrite : integer := 21;
constant opcRmw : integer := 22;
constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
constant opcRti : integer := 24;
constant opcIRQ : integer := 25;
constant opcInA : integer := 26;
constant opcInBrk : integer := 27;
constant opcInX : integer := 28;
constant opcInY : integer := 29;
constant opcInS : integer := 30;
constant opcInT : integer := 31;
constant opcInH : integer := 32;
constant opcInClear : integer := 33;
constant aluMode1From : integer := 34;
--
constant aluMode1To : integer := 37;
constant aluMode2From : integer := 38;
--
constant aluMode2To : integer := 40;
constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43;
subtype addrDef is unsigned(0 to 15);
--
-- is Interrupt -----------------+
-- instruction is RTI ----------------+|
-- PC++ on last cycle (RTS) ---------------+||
-- RMW --------------+|||
-- Write -------------+||||
-- Pop/Stack up -------------+|||||
-- Branch ---------+ ||||||
-- Jump ----------+| ||||||
-- Push or Pop data -------+|| ||||||
-- Push or Pop addr ------+||| ||||||
-- Indirect -----+|||| ||||||
-- ZeroPage ----+||||| ||||||
-- Absolute ---+|||||| ||||||
-- PC++ on cycle2 --+||||||| ||||||
-- |AZI||JBXY|WM|||
constant immediate : addrDef := "1000000000000000";
constant implied : addrDef := "0000000000000000";
-- Zero page
constant readZp : addrDef := "1010000000000000";
constant writeZp : addrDef := "1010000000010000";
constant rmwZp : addrDef := "1010000000001000";
-- Zero page indexed
constant readZpX : addrDef := "1010000010000000";
constant writeZpX : addrDef := "1010000010010000";
constant rmwZpX : addrDef := "1010000010001000";
constant readZpY : addrDef := "1010000001000000";
constant writeZpY : addrDef := "1010000001010000";
constant rmwZpY : addrDef := "1010000001001000";
-- Zero page indirect
constant readIndX : addrDef := "1001000010000000";
constant writeIndX : addrDef := "1001000010010000";
constant rmwIndX : addrDef := "1001000010001000";
constant readIndY : addrDef := "1001000001000000";
constant writeIndY : addrDef := "1001000001010000";
constant rmwIndY : addrDef := "1001000001001000";
constant rmwInd : addrDef := "1001000000001000";
constant readInd : addrDef := "1001000000000000";
constant writeInd : addrDef := "1001000000010000";
-- |AZI||JBXY|WM||
-- Absolute
constant readAbs : addrDef := "1100000000000000";
constant writeAbs : addrDef := "1100000000010000";
constant rmwAbs : addrDef := "1100000000001000";
constant readAbsX : addrDef := "1100000010000000";
constant writeAbsX : addrDef := "1100000010010000";
constant rmwAbsX : addrDef := "1100000010001000";
constant readAbsY : addrDef := "1100000001000000";
constant writeAbsY : addrDef := "1100000001010000";
constant rmwAbsY : addrDef := "1100000001001000";
-- PHA PHP
constant push : addrDef := "0000010000000000";
-- PLA PLP
constant pop : addrDef := "0000010000100000";
-- Jumps
constant jsr : addrDef := "1000101000000000";
constant jumpAbs : addrDef := "1000001000000000";
constant jumpInd : addrDef := "1100001000000000";
constant jumpIndX : addrDef := "1100001010000000";
constant relative : addrDef := "1000000100000000";
-- Specials
constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001";
constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu
-- X = index X
-- Y = index Y
-- S = Stack pointer
-- H = indexH
--
-- AEXYSTHc
constant aluInA : unsigned(0 to 7) := "10000000";
constant aluInBrk : unsigned(0 to 7) := "01000000";
constant aluInX : unsigned(0 to 7) := "00100000";
constant aluInY : unsigned(0 to 7) := "00010000";
constant aluInS : unsigned(0 to 7) := "00001000";
constant aluInT : unsigned(0 to 7) := "00000100";
constant aluInClr : unsigned(0 to 7) := "00000001";
constant aluInSet : unsigned(0 to 7) := "00000000";
constant aluInXXX : unsigned(0 to 7) := "--------";
-- Most of the aluModes are just like the opcodes.
-- aluModeInp -> input is output. calculate N and Z
-- aluModeCmp -> Compare for CMP, CPX, CPY
-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
-- aluModeInc -> for INC but also INX, INY
-- aluModeDec -> for DEC but also DEX, DEY
subtype aluMode1 is unsigned(0 to 3);
subtype aluMode2 is unsigned(0 to 2);
subtype aluMode is unsigned(0 to 9);
-- Logic/Shift ALU
constant aluModeInp : aluMode1 := "0000";
constant aluModeP : aluMode1 := "0001";
constant aluModeInc : aluMode1 := "0010";
constant aluModeDec : aluMode1 := "0011";
constant aluModeFlg : aluMode1 := "0100";
constant aluModeBit : aluMode1 := "0101";
-- 0110
-- 0111
constant aluModeLsr : aluMode1 := "1000";
constant aluModeRor : aluMode1 := "1001";
constant aluModeAsl : aluMode1 := "1010";
constant aluModeRol : aluMode1 := "1011";
constant aluModeTSB : aluMode1 := "1100";
constant aluModeTRB : aluMode1 := "1101";
-- 1110
-- 1111;
-- Arithmetic ALU
constant aluModePss : aluMode2 := "000";
constant aluModeCmp : aluMode2 := "001";
constant aluModeAdc : aluMode2 := "010";
constant aluModeSbc : aluMode2 := "011";
constant aluModeAnd : aluMode2 := "100";
constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110";
constant aluModeNoF : aluMode2 := "111";
constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---";
constant aluDec : aluMode := aluModeDec & aluModePss & "---";
constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
constant aluRor : aluMode := aluModeRor & aluModePss & "---";
constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
constant aluRol : aluMode := aluModeRol & aluModePss & "---";
constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
constant aluTSB : aluMode := aluModeTSB & aluModePss & "---";
constant aluTRB : aluMode := aluModeTRB & aluModePss & "---";
constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A
-- |+------ Update register X
-- ||+----- Update register Y
-- |||+---- Update register S
-- |||| +-- Update Flags
-- |||| |
-- |||| _|__
-- |||| / \
-- AXYS NVDIZC addressing aluInput aluMode
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "001100" & brk & aluInBrk & aluP, -- 00 BRK
"1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 02 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 03 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTSB, -- 04 TSB zp ----------- 65C02
"1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
"0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 07 NOP ------- 65C02
"0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
"1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
"1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTSB, -- 0C TSB abs ---------- 65C02
"1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
"0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
"1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
"1000" & "100010" & readInd & aluInT & aluOra, -- 12 ORA (zp) --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 13 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTRB, -- 14 TRB zp ~---------- 65C02
"1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
"0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 17 NOP ------- 65C02
"0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
"1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
"1000" & "100010" & implied & aluInA & aluInc, -- 1A INC accu --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTRB, -- 1C TRB abs ~----- --- 65C02
"1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
"1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 22 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 23 NOP ------- 65C02
"0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
"1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
"0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 27 NOP ------- 65C02
"0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
"1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
"1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2B NOP ------- 65C02
"0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
"1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
"0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
"1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
"1000" & "100010" & readInd & aluInT & aluAnd, -- 32 AND (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 33 NOP ------- 65C02
"0000" & "110010" & readZpX & aluInT & aluBit, -- 34 BIT zp,x -------- 65C02
"1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 37 NOP ------- 65C02
"0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
"1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
"1000" & "100010" & implied & aluInA & aluDec, -- 3A DEC accu -------- 65C12
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3B NOP ------- 65C02
"0000" & "110010" & readAbsX & aluInT & aluBit, -- 3C BIT abs,x ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
"1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 42 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 43 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 44 NOP ------- 65C02
"1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
"0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 47 NOP ------- 65C02
"0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
"1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
"1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4B NOP ------- 65C02
"0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
"1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
"0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
"1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
"1000" & "100010" & readInd & aluInT & aluEor, -- 52 EOR (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 53 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 54 NOP ------- 65C02
"1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
"0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 57 NOP ------- 65C02
"0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
"1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
"0000" & "000000" & push & aluInY & aluInp, -- 5A PHY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5B NOP ------- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 5C NOP ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
"1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 62 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 63 NOP ------- 65C02
"0000" & "000000" & writeZp & aluInClr & aluInp, -- 64 STZ zp ---------- 65C02
"1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
"0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 67 NOP ------- 65C02
"1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
"1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
"1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6B NOP ------ 65C02
"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
"0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6F NOP ------ 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
"1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
"1000" & "110011" & readInd & aluInT & aluAdc, -- 72 ADC (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 73 NOP ------ 65C02
"0000" & "000000" & writeZpX & aluInClr & aluInp, -- 74 STZ zp,x -------- 65C02
"1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 77 NOP ----- 65C02
"0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
"1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
"0010" & "100010" & pop & aluInT & aluInp, -- 7A PLY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7B NOP ----- 65C02
"0000" & "000000" & jumpIndX & aluInXXX & aluXXX, -- 7C JMP indirect,x -- 65C02
--"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 80 BRA ----------- 65C02
"0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 83 NOP ----- 65C02
"0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
"0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
"0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 87 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
"0000" & "000010" & immediate & aluInT & aluBit, -- 89 BIT imm ------- 65C02
"1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs ------- 65C02
"0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
"0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8F NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
"0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
"0000" & "000000" & writeInd & aluInA & aluInp, -- 92 STA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 93 NOP ----- 65C02
"0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
"0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
"0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 97 NOP ----- 65C02
"1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
"0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
"0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInClr & aluInp, -- 9C STZ Abs ------- 65C02
"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
"0000" & "000000" & writeAbsX & aluInClr & aluInp, -- 9C STZ Abs,x ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
"0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A3 NOP ----- 65C02
"0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
"1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
"0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A7 NOP ----- 65C02
"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AB NOP ----- 65C02
"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
"1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
"1000" & "100010" & readInd & aluInT & aluInp, -- B2 LDA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B3 NOP ----- 65C02
"0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
"1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
"0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B7 NOP ----- 65C02
"0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
"1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
"0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BB NOP ----- 65C02
"0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
"1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
"0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
"0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
"0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
"0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C7 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
"0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
"0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
"0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
"0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
"0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
"0000" & "100011" & readInd & aluInT & aluCmp, -- D2 CMP (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- D4 NOP ----- 65C02
"0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
"0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D7 NOP ----- 65C02
"0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
"0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
"0000" & "000000" & push & aluInX & aluInp, -- DA PHX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- DC NOP ----- 65C02
"0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
"1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
"1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
"0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E7 NOP ----- 65C02
"0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
"1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
"1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
"0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
"1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
"1000" & "110011" & readInd & aluInT & aluSbc, -- F2 SBC (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- F4 NOP ----- 65C02
"1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
"0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F7 NOP ---- 65C02
"0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
"1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
"0100" & "100010" & pop & aluInT & aluInp, -- FA PLX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- FB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- FC NOP ----- 65C02
"1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX -- FF NOP ----- 65C02
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
-- Program counter
signal PC : unsigned(15 downto 0); -- Program counter
-- Address generation
type nextAddrDef is (
nextAddrHold,
nextAddrIncr,
nextAddrIncrL, -- Increment low bits only (zeropage accesses)
nextAddrIncrH, -- Increment high bits only (page-boundary)
nextAddrDecrH, -- Decrement high bits (branch backwards)
nextAddrPc,
nextAddrIrq,
nextAddrReset,
nextAddrAbs,
nextAddrAbsIndexed,
nextAddrZeroPage,
nextAddrZPIndexed,
nextAddrStack,
nextAddrRelative
);
signal nextAddr : nextAddrDef;
signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0);
signal myAddrIncrH : unsigned(7 downto 0);
signal myAddrDecrH : unsigned(7 downto 0);
signal theWe : std_logic;
signal irqActive : std_logic;
-- Output register
signal doReg : unsigned(7 downto 0);
-- Buffer register
signal T : unsigned(7 downto 0);
-- General registers
signal A : unsigned(7 downto 0); -- Accumulator
signal X : unsigned(7 downto 0); -- Index X
signal Y : unsigned(7 downto 0); -- Index Y
signal S : unsigned(7 downto 0); -- stack pointer
-- Status register
signal C : std_logic; -- Carry
signal Z : std_logic; -- Zero flag
signal I : std_logic; -- Interrupt flag
signal D : std_logic; -- Decimal mode
signal B : std_logic; -- Break software interrupt
signal R : std_logic; -- always 1
signal V : std_logic; -- Overflow
signal N : std_logic; -- Negative
-- ALU
-- ALU input
signal aluInput : unsigned(7 downto 0);
signal aluCmpInput : unsigned(7 downto 0);
-- ALU output
signal aluRegisterOut : unsigned(7 downto 0);
signal aluRmwOut : unsigned(7 downto 0);
signal aluC : std_logic;
signal aluZ : std_logic;
signal aluV : std_logic;
signal aluN : std_logic;
-- Indexing
signal indexOut : unsigned(8 downto 0);
begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInA) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInX) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInY) = '1' then
temp := temp and Y;
end if;
if opcInfo(opcInS) = '1' then
temp := temp and S;
end if;
if opcInfo(opcInT) = '1' then
temp := temp and T;
end if;
if opcInfo(opcInBrk) = '1' then
temp := temp and "11100111"; -- also DMB clear D (bit 3)
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');
end if;
aluInput <= temp;
end process;
processCmpInput: process(clk, opcInfo, A, X, Y)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInCmp) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInCpx) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInCpy) = '1' then
temp := temp and Y;
end if;
aluCmpInput <= temp;
end process;
-- ALU consists of two parts
-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
-- Some instructions are both RMW and accumulator so for most
-- instructions the rmw results are routed through accu alu too.
-- The B flag
------------
--No actual "B" flag exists inside the 6502's processor status register. The B
--flag only exists in the status flag byte pushed to the stack. Naturally,
--when the flags are restored (via PLP or RTI), the B bit is discarded.
--
--Depending on the means, the B status flag will be pushed to the stack as
--either 0 or 1.
--
--software instructions BRK & PHP will push the B flag as being 1.
--hardware interrupts IRQ & NMI will push the B flag as being 0.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C, R)
variable lowBits : unsigned(5 downto 0);
variable nineBits : unsigned(8 downto 0);
variable rmwBits : unsigned(8 downto 0);
variable tsxBits : unsigned(8 downto 0);
variable varC : std_logic;
variable varZ : std_logic;
variable varV : std_logic;
variable varN : std_logic;
begin
lowBits := (others => '-');
nineBits := (others => '-');
rmwBits := (others => '-');
tsxBits := (others => '-');
R <= '1';
B <= '0';
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp => rmwBits := C & aluInput;
when aluModeP => rmwBits := C & N & V & R & (not irqActive) & D & I & Z & C; -- irqActive
when aluModeInc => rmwBits := C & (aluInput + 1);
when aluModeDec => rmwBits := C & (aluInput - 1);
when aluModeAsl => rmwBits := aluInput & "0";
when aluModeTSB => rmwBits := "0" & (aluInput(7 downto 0) or A); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeTRB => rmwBits := "0" & (aluInput(7 downto 0) and (not A)); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeFlg => rmwBits := aluInput(0) & aluInput;
when aluModeLsr => rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
when aluModeRol => rmwBits := aluInput & C;
when aluModeRoR => rmwBits := aluInput(0) & C & aluInput(7 downto 1);
when others => rmwBits := C & aluInput;
end case;
-- ALU
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
when aluModeSbc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
when aluModeCmp => ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
when aluModeAnd => ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
when aluModeEor => ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
when aluModeOra => ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
when aluModeNoF => ninebits := "000110000";
when others => ninebits := rmwBits;
end case;
varV := aluInput(6); -- Default for BIT / PLP / RTI
if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varZ := rmwBits(1);
elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then
if tsxBits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
elsif ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varN := rmwBits(7);
else
varN := nineBits(7);
end if;
varC := ninebits(8);
case opcInfo(aluMode2From to aluMode2To) is
-- Flags Affected: n v — — — — z c
-- n Set if most significant bit of result is set; else cleared.
-- v Set if signed overflow; cleared if valid signed result.
-- z Set if result is zero; else cleared.
-- c Set if unsigned overflow; cleared if valid unsigned result
when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag.
if D = '1' then
if lowBits(5 downto 1) > 9 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
if lowBits(5) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
end if;
end if;
end if;
when others =>
null;
end case;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode high bits correction, is done after setting Z and N flags
varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
if D = '1' then
if ninebits(8 downto 4) > 9 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
end if;
end if;
when aluModeSbc =>
varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
if D = '1' then
-- Check for borrow (lower 4 bits)
if lowBits(5) = '0' then
ninebits(7 downto 0) := ninebits(7 downto 0) - 6;
end if;
-- Check for borrow (upper 4 bits)
if ninebits(8) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if;
end if;
when others =>
null;
end case;
-- fix n and z flag for 65c02 adc sbc instructions in decimal mode
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when aluModeSbc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when others =>
null;
end case;
-- DMB Remove Pipelining
-- if rising_edge(clk) then
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
-- end if;
end process;
calcInterrupt: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = cycleStack4 or reset = '0' then
nmiReg <= '1';
end if;
if nextCpuCycle /= cycleBranchTaken and nextCpuCycle /= opcodeFetch then
irqReg <= irq_n;
nmiEdge <= nmi_n;
if (nmiEdge = '1') and (nmi_n = '0') then
nmiReg <= '0';
end if;
end if;
-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
end if;
end if;
end process;
--pipeirq: process(clk)
-- begin
-- if rising_edge(clk) then
-- if enable = '1' then
-- if (reset = '0') or (theCpuCycle = opcodeFetch) then
-- -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- -- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
-- processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
-- end if;
-- end if;
-- end if;
-- end process;
calcNextOpcode: process(clk, di, reset, processIrq)
variable myNextOpcode : unsigned(7 downto 0);
begin
-- Next opcode is read from input unless a reset or IRQ is pending.
myNextOpcode := di;
if reset = '0' then
myNextOpcode := X"4C";
elsif processIrq = '1' then
myNextOpcode := X"00";
end if;
nextOpcode <= myNextOpcode;
end process;
nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if (reset = '0') or (theCpuCycle = opcodeFetch) then
opcInfo <= nextOpcInfo;
end if;
end if;
end if;
end process;
calcTheOpcode: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = opcodeFetch then
irqActive <= '0';
if processIrq = '1' then
irqActive <= '1';
end if;
-- Fetch opcode
theOpcode <= nextOpcode;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(enable, theCpuCycle, opcInfo)
begin
updateRegisters <= false;
if enable = '1' then
if opcInfo(opcRti) = '1' then
if theCpuCycle = cycleRead then
updateRegisters <= true;
end if;
elsif theCpuCycle = opcodeFetch then
updateRegisters <= true;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theCpuCycle <= nextCpuCycle;
end if;
if reset = '0' then
theCpuCycle <= cycle2;
end if;
end if;
end process;
-- Determine the next cpu cycle. After the last cycle we always
-- go to opcodeFetch to get the next opcode.
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut, T, N, V, C, Z)
begin
nextCpuCycle <= opcodeFetch;
case theCpuCycle is
when opcodeFetch =>
-- DMB: Implement single cycle NOPs (columns 3,7,B,F) by
-- looking ahead at opcode (bypassing the normal decoding)
if nextOpcode(1 downto 0) = "11" then
nextCpuCycle <= opcodeFetch;
else
nextCpuCycle <= cycle2;
end if;
when cycle2 =>
if opcInfo(opcBranch) = '1' then
if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11")
or (theOpcode(7 downto 0) = x"80") then -- Branch condition is true
nextCpuCycle <= cycleBranchTaken;
end if;
elsif (opcInfo(opcStackUp) = '1') then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackAddr) = '1' and opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleStack2;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleWrite;
elsif opcInfo(opcAbsolute) = '1' then
nextCpuCycle <= cycle3;
elsif opcInfo(opcIndirect) = '1' then
if opcInfo(indexX) = '1' then
nextCpuCycle <= cyclePreIndirect;
else
nextCpuCycle <= cycleIndirect;
end if;
elsif opcInfo(opcZeroPage) = '1' then
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
else
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreRead;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycle3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
end if;
if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
if opcInfo(opcWrite) = '1' then
nextCpuCycle <= cycleWrite;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect =>
nextCpuCycle <= cycleIndirect;
when cycleIndirect =>
nextCpuCycle <= cycle3;
when cycleBranchTaken =>
if indexOut(8) /= T(7) then
nextCpuCycle <= cycleBranchPage;
end if;
when cyclePreRead =>
if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2;
end if;
when cycleRead =>
if opcInfo(opcJump) = '1' or indexOut(8) = '1' then
nextCpuCycle <= cycleRead2;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
if opcInfo(indexX) = '1' or opcInfo(indexY) = '1' then
nextCpuCycle <= cycleRead2;
end if;
end if;
when cycleRead2 =>
if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
end if;
when cycleRmw =>
nextCpuCycle <= cycleWrite;
when cyclePreWrite =>
nextCpuCycle <= cycleWrite;
when cycleStack1 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2;
end if;
when cycleStack2 =>
nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead;
end if;
if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycleStack3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4;
end if;
when cycleStack4 =>
nextCpuCycle <= cycleRead2;
when cycleJump =>
if opcInfo(opcIncrAfter) = '1' then
nextCpuCycle <= cycleEnd;
end if;
when others =>
null;
end case;
end process;
-- -----------------------------------------------------------------------
-- T register
-- -----------------------------------------------------------------------
calcT: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when cycle2 =>
T <= di;
when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then
if theOpcode = x"28" or theOpcode = x"40" then -- plp or rti pulling the flags off the stack
T <= (di or "00110000"); -- Read from stack
else
T <= di;
end if;
end if;
when cycleIndirect | cycleRead | cycleRead2 =>
T <= di;
when others =>
null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- A register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateA) = '1' then
A <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- X register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateX) = '1' then
X <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Y register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateY) = '1' then
Y <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- C flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateC) = '1' then
C <= aluC;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Z flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateZ) = '1' then
Z <= aluZ;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- I flag interupt flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
I <= '1';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateI) = '1' then
I <= aluInput(2);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- D flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
D <= '0';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateD) = '1' then
D <= aluInput(3);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- V flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateV) = '1' then
V <= aluV;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- N flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateN) = '1' then
N <= aluN;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Stack pointer
-- -----------------------------------------------------------------------
process(clk)
variable sIncDec : unsigned(7 downto 0);
variable updateFlag : boolean;
begin
if rising_edge(clk) then
if opcInfo(opcStackUp) = '1' then
sIncDec := S + 1;
else
sIncDec := S - 1;
end if;
if enable = '1' then
updateFlag := false;
case nextCpuCycle is
when cycleStack1 =>
if (opcInfo(opcStackUp) = '1') or (opcInfo(opcStackData) = '1') then
updateFlag := true;
end if;
when cycleStack2 =>
updateFlag := true;
when cycleStack3 =>
updateFlag := true;
when cycleStack4 =>
updateFlag := true;
when cycleRead =>
if opcInfo(opcRti) = '1' then
updateFlag := true;
end if;
when cycleWrite =>
if opcInfo(opcStackData) = '1' then
updateFlag := true;
end if;
when others =>
null;
end case;
if updateFlag then
S <= sIncDec;
end if;
end if;
if updateRegisters then
if opcInfo(opcUpdateS) = '1' then
S <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Data out
-- -----------------------------------------------------------------------
calcDo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
doReg <= aluRmwOut;
case nextCpuCycle is
when cycleStack2 =>
if opcInfo(opcIRQ) = '1' and irqActive = '0' then
doReg <= myAddrIncr(15 downto 8);
else
doReg <= PC(15 downto 8);
end if;
when cycleStack3 =>
doReg <= PC(7 downto 0);
when cycleRmw =>
doReg <= di; -- Read-modify-write write old value first.
when others =>
null;
end case;
end if;
end if;
end process;
do <= doReg;
-- -----------------------------------------------------------------------
-- Write enable
-- -----------------------------------------------------------------------
calcWe: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theWe <= '1';
case nextCpuCycle is
when cycleStack1 =>
if opcInfo(opcStackUp) = '0' and ((opcInfo(opcStackAddr) = '0') or (opcInfo(opcStackData) = '1')) then
theWe <= '0';
end if;
when cycleStack2 | cycleStack3 | cycleStack4 =>
if opcInfo(opcStackUp) = '0' then
theWe <= '0';
end if;
when cycleRmw =>
theWe <= '0';
when cycleWrite =>
theWe <= '0';
when others =>
null;
end case;
end if;
end if;
--nwe <= theWe;
end process;
nwe <= theWe;
-- -----------------------------------------------------------------------
-- Program counter
-- -----------------------------------------------------------------------
calcPC: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when opcodeFetch =>
PC <= myAddr;
when cycle2 =>
if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr;
else
PC <= myAddr;
end if;
end if;
when cycle3 =>
if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Address generation
-- -----------------------------------------------------------------------
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
begin
nextAddr <= nextAddrIncr;
case theCpuCycle is
when cycle2 =>
if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcIndirect) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcSecondByte) = '1' then
nextAddr <= nextAddrIncr;
else
nextAddr <= nextAddrHold;
end if;
when cycle3 =>
if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs;
else
nextAddr <= nextAddrAbsIndexed;
end if;
when cyclePreIndirect =>
nextAddr <= nextAddrZPIndexed;
when cycleIndirect =>
nextAddr <= nextAddrIncrL;
when cycleBranchTaken =>
nextAddr <= nextAddrRelative;
when cycleBranchPage =>
if T(7) = '0' then
nextAddr <= nextAddrIncrH;
else
nextAddr <= nextAddrDecrH;
end if;
when cyclePreRead =>
nextAddr <= nextAddrZPIndexed;
when cycleRead =>
nextAddr <= nextAddrPc;
if indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' or opcInfo(opcJump) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRead2 =>
nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRmw =>
nextAddr <= nextAddrHold;
when cyclePreWrite =>
nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
end if;
when cycleWrite =>
nextAddr <= nextAddrPc;
when cycleStack1 =>
nextAddr <= nextAddrStack;
when cycleStack2 =>
nextAddr <= nextAddrStack;
when cycleStack3 =>
nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc;
end if;
when cycleStack4 =>
nextAddr <= nextAddrIrq;
when cycleJump =>
nextAddr <= nextAddrAbs;
when others =>
null;
end case;
if reset = '0' then
nextAddr <= nextAddrReset;
end if;
end process;
indexAlu: process(opcInfo, myAddr, T, X, Y)
begin
if opcInfo(indexX) = '1' then
indexOut <= (B"0" & T) + (B"0" & X);
elsif opcInfo(indexY) = '1' then
indexOut <= (B"0" & T) + (B"0" & Y);
elsif opcInfo(opcBranch) = '1' then
indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
else
indexOut <= B"0" & T;
end if;
end process;
calcAddr: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case nextAddr is
when nextAddrIncr =>
myAddr <= myAddrIncr;
when nextAddrIncrL =>
myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
when nextAddrIncrH =>
myAddr(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH =>
myAddr(15 downto 8) <= myAddrDecrH;
when nextAddrPc =>
myAddr <= PC;
when nextAddrIrq =>
myAddr <= X"FFFE";
if nmiReg = '0' then
myAddr <= X"FFFA";
end if;
when nextAddrReset =>
myAddr <= X"FFFC";
when nextAddrAbs =>
myAddr <= di & T;
when nextAddrAbsIndexed =>
myAddr <= di & indexOut(7 downto 0);
when nextAddrZeroPage =>
myAddr <= "00000000" & di;
when nextAddrZPIndexed =>
myAddr <= "00000000" & indexOut(7 downto 0);
when nextAddrStack =>
myAddr <= "00000001" & S;
when nextAddrRelative =>
myAddr(7 downto 0) <= indexOut(7 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
myAddrIncr <= myAddr + 1;
myAddrIncrH <= myAddr(15 downto 8) + 1;
myAddrDecrH <= myAddr(15 downto 8) - 1;
addr <= myAddr;
-- DMB This looked plain broken and inferred a latch
--
-- calcsync: process(clk)
-- begin
-- if enable = '1' then
-- case theCpuCycle is
-- when opcodeFetch =>
-- sync <= '1';
-- when others =>
-- sync <= '0';
-- end case;
-- end if;
-- end process;
sync <= '1' when theCpuCycle = opcodeFetch else '0';
sync_irq <= irqActive;
Regs <= std_logic_vector(myAddr) &
"00000001" & std_logic_vector(S)&
N & V & R & B & D & I & Z & C &
std_logic_vector(Y) &
std_logic_vector(X) &
std_logic_vector(A);
end architecture;
|
gpl-3.0
|
fbelavenuto/msx1fpga
|
src/syn-multicore2/multicore2_top.vhd
|
1
|
23635
|
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- TOP created by Victor Trucco (c) 2018
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.msx_pack.all;
entity multicore2_top is
port (
-- Clocks
clock_50_i : in std_logic;
-- Buttons
btn_n_i : in std_logic_vector(4 downto 1);
-- SRAM (AS7C34096)
sram_addr_o : out std_logic_vector(18 downto 0) := (others => '0');
sram_data_io : inout std_logic_vector( 7 downto 0) := (others => 'Z');
sram_we_n_o : out std_logic := '1';
sram_oe_n_o : out std_logic := '1';
-- SDRAM (H57V256 = 16Mx16 = 32MB)
sdram_clk_o : out std_logic := '0';
sdram_cke_o : out std_logic := '0';
sdram_ad_o : out std_logic_vector(12 downto 0) := (others => '0');
sdram_da_io : inout std_logic_vector(15 downto 0) := (others => 'Z');
sdram_ba_o : out std_logic_vector( 1 downto 0) := (others => '0');
sdram_dqm_o : out std_logic_vector( 1 downto 0) := (others => '1');
sdram_ras_o : out std_logic := '1';
sdram_cas_o : out std_logic := '1';
sdram_cs_o : out std_logic := '1';
sdram_we_o : out std_logic := '1';
-- PS2
ps2_clk_io : inout std_logic := 'Z';
ps2_data_io : inout std_logic := 'Z';
ps2_mouse_clk_io : inout std_logic := 'Z';
ps2_mouse_data_io : inout std_logic := 'Z';
-- SD Card
sd_cs_n_o : out std_logic := '1';
sd_sclk_o : out std_logic := '0';
sd_mosi_o : out std_logic := '0';
sd_miso_i : in std_logic;
-- Joysticks
joy1_up_i : in std_logic;
joy1_down_i : in std_logic;
joy1_left_i : in std_logic;
joy1_right_i : in std_logic;
joy1_p6_i : in std_logic;
joy1_p9_i : in std_logic;
joy2_up_i : in std_logic;
joy2_down_i : in std_logic;
joy2_left_i : in std_logic;
joy2_right_i : in std_logic;
joy2_p6_i : in std_logic;
joy2_p9_i : in std_logic;
joyX_p7_o : out std_logic := '1';
-- Audio
dac_l_o : out std_logic := '0';
dac_r_o : out std_logic := '0';
ear_i : in std_logic;
mic_o : out std_logic := '0';
-- VGA
vga_r_o : out std_logic_vector(4 downto 0) := (others => '0');
vga_g_o : out std_logic_vector(4 downto 0) := (others => '0');
vga_b_o : out std_logic_vector(4 downto 0) := (others => '0');
vga_hsync_n_o : out std_logic := '1';
vga_vsync_n_o : out std_logic := '1';
-- HDMI
tmds_o : out std_logic_vector(7 downto 0) := (others => '0');
--STM32
stm_rx_o : out std_logic := 'Z'; -- stm RX pin, so, is OUT on the slave
stm_tx_i : in std_logic := 'Z'; -- stm TX pin, so, is IN on the slave
stm_rst_o : out std_logic := '0'; -- '0' to hold the microcontroller reset line, to free the SD card
stm_a15_io : inout std_logic;
stm_b8_io : inout std_logic := 'Z';
stm_b9_io : inout std_logic := 'Z';
stm_b12_io : inout std_logic := 'Z';
stm_b13_io : inout std_logic := 'Z';
stm_b14_io : inout std_logic := 'Z';
stm_b15_io : inout std_logic := 'Z'
);
end entity;
architecture behavior of multicore2_top is
-- Buttons
signal btn_por_n_s : std_logic;
signal btn_reset_n_s : std_logic;
signal btn_scan_s : std_logic;
-- Resets
signal pll_locked_s : std_logic;
signal por_s : std_logic;
signal reset_s : std_logic;
signal soft_reset_k_s : std_logic;
signal soft_reset_s_s : std_logic;
signal soft_por_s : std_logic;
signal soft_rst_cnt_s : unsigned(7 downto 0) := X"FF";
-- Clocks
signal clock_sdram_s : std_logic;
signal clock_master_s : std_logic;
signal clock_vdp_s : std_logic;
signal clock_cpu_s : std_logic;
signal clock_psg_en_s : std_logic;
signal clock_3m_s : std_logic;
signal turbo_on_s : std_logic;
signal clock_vga_s : std_logic;
signal clock_dvi_s : std_logic;
signal clock_vga2x_s : std_logic;
-- RAM
signal ram_addr_s : std_logic_vector(22 downto 0); -- 8MB
signal ram_data_from_s : std_logic_vector( 7 downto 0);
signal ram_data_to_s : std_logic_vector( 7 downto 0);
signal ram_ce_s : std_logic;
signal ram_oe_s : std_logic;
signal ram_we_s : std_logic;
-- VRAM memory
signal vram_addr_s : std_logic_vector(13 downto 0); -- 16K
signal vram_do_s : std_logic_vector( 7 downto 0);
signal vram_di_s : std_logic_vector( 7 downto 0);
-- signal vram_ce_s : std_logic;
-- signal vram_oe_s : std_logic;
signal vram_we_s : std_logic;
-- Audio
signal audio_scc_s : signed(14 downto 0);
signal audio_psg_s : unsigned( 7 downto 0);
signal beep_s : std_logic;
signal audio_l_s : unsigned(15 downto 0);
signal audio_r_s : unsigned(15 downto 0);
signal audio_l_amp_s : unsigned(15 downto 0);
signal audio_r_amp_s : unsigned(15 downto 0);
signal volumes_s : volumes_t;
-- Video
signal rgb_col_s : std_logic_vector( 3 downto 0);
-- signal rgb_hsync_n_s : std_logic;
-- signal rgb_vsync_n_s : std_logic;
signal cnt_hor_s : std_logic_vector( 8 downto 0);
signal cnt_ver_s : std_logic_vector( 7 downto 0);
signal vga_hsync_n_s : std_logic;
signal vga_vsync_n_s : std_logic;
signal vga_blank_s : std_logic;
signal vga_col_s : std_logic_vector( 3 downto 0);
signal vga_r_s : std_logic_vector( 3 downto 0);
signal vga_g_s : std_logic_vector( 3 downto 0);
signal vga_b_s : std_logic_vector( 3 downto 0);
signal scanlines_en_s : std_logic;
signal odd_line_s : std_logic;
signal sound_hdmi_l_s : std_logic_vector(15 downto 0);
signal sound_hdmi_r_s : std_logic_vector(15 downto 0);
signal tdms_r_s : std_logic_vector( 9 downto 0);
signal tdms_g_s : std_logic_vector( 9 downto 0);
signal tdms_b_s : std_logic_vector( 9 downto 0);
signal tdms_p_s : std_logic_vector( 3 downto 0);
signal tdms_n_s : std_logic_vector( 3 downto 0);
-- Keyboard
signal rows_s : std_logic_vector( 3 downto 0);
signal cols_s : std_logic_vector( 7 downto 0);
signal caps_en_s : std_logic;
signal extra_keys_s : std_logic_vector( 3 downto 0);
signal keyb_valid_s : std_logic;
signal keyb_data_s : std_logic_vector( 7 downto 0);
signal keymap_addr_s : std_logic_vector( 8 downto 0);
signal keymap_data_s : std_logic_vector( 7 downto 0);
signal keymap_we_s : std_logic;
-- Joystick
signal joy1_out_s : std_logic;
signal joy2_out_s : std_logic;
-- Bus
signal bus_addr_s : std_logic_vector(15 downto 0);
signal bus_data_from_s : std_logic_vector( 7 downto 0) := (others => '1');
signal bus_data_to_s : std_logic_vector( 7 downto 0);
signal bus_rd_n_s : std_logic;
signal bus_wr_n_s : std_logic;
signal bus_m1_n_s : std_logic;
signal bus_iorq_n_s : std_logic;
signal bus_mreq_n_s : std_logic;
signal bus_sltsl1_n_s : std_logic;
signal bus_sltsl2_n_s : std_logic;
signal bus_int_n_s : std_logic;
signal bus_wait_n_s : std_logic;
-- JT51
signal jt51_cs_n_s : std_logic;
signal jt51_data_from_s : std_logic_vector( 7 downto 0) := (others => '1');
signal jt51_hd_s : std_logic := '0';
signal jt51_left_s : signed(15 downto 0) := (others => '0');
signal jt51_right_s : signed(15 downto 0) := (others => '0');
-- OPLL
signal opll_cs_n_s : std_logic := '1';
signal opll_mo_s : signed(12 downto 0) := (others => '0');
signal opll_ro_s : signed(12 downto 0) := (others => '0');
begin
-- PLL1
pll: entity work.pll1
port map (
inclk0 => clock_50_i,
c0 => clock_master_s, -- 21.477 MHz [21.484]
c1 => clock_sdram_s, -- 85.908 MHz (4x master) [85.937]
c2 => sdram_clk_o, -- 85.908 MHz -90°
locked => pll_locked_s
);
-- PLL2
pll2: entity work.pll2
port map (
inclk0 => clock_50_i,
c0 => clock_vga_s, -- 25.200
c1 => clock_dvi_s -- 126.000
);
-- Clocks
clks: entity work.clocks
port map (
clock_i => clock_master_s,
por_i => not pll_locked_s,
turbo_on_i => turbo_on_s,
clock_vdp_o => clock_vdp_s,
clock_5m_en_o => open,
clock_cpu_o => clock_cpu_s,
clock_psg_en_o => clock_psg_en_s,
clock_3m_o => clock_3m_s
);
-- The MSX1
the_msx: entity work.msx
generic map (
hw_id_g => 8,
hw_txt_g => "Multicore2 Board",
hw_version_g => actual_version,
video_opt_g => 3, -- No dblscan and external palette (Color in rgb_r_o)
ramsize_g => 8192,
hw_hashwds_g => '0'
)
port map (
-- Clocks
clock_i => clock_master_s,
clock_vdp_i => clock_vdp_s,
clock_cpu_i => clock_cpu_s,
clock_psg_en_i => clock_psg_en_s,
-- Turbo
turbo_on_k_i => extra_keys_s(3), -- F11
turbo_on_o => turbo_on_s,
-- Resets
reset_i => reset_s,
por_i => por_s,
softreset_o => soft_reset_s_s,
-- Options
opt_nextor_i => '1',
opt_mr_type_i => "00",
opt_vga_on_i => '1',
-- RAM
ram_addr_o => ram_addr_s,
ram_data_i => ram_data_from_s,
ram_data_o => ram_data_to_s,
ram_ce_o => ram_ce_s,
ram_we_o => ram_we_s,
ram_oe_o => ram_oe_s,
-- ROM
rom_addr_o => open,
rom_data_i => ram_data_from_s,
rom_ce_o => open,
rom_oe_o => open,
-- External bus
bus_addr_o => bus_addr_s,
bus_data_i => bus_data_from_s,
bus_data_o => bus_data_to_s,
bus_rd_n_o => bus_rd_n_s,
bus_wr_n_o => bus_wr_n_s,
bus_m1_n_o => bus_m1_n_s,
bus_iorq_n_o => bus_iorq_n_s,
bus_mreq_n_o => bus_mreq_n_s,
bus_sltsl1_n_o => bus_sltsl1_n_s,
bus_sltsl2_n_o => bus_sltsl2_n_s,
bus_wait_n_i => bus_wait_n_s,
bus_nmi_n_i => '1',
bus_int_n_i => bus_int_n_s,
-- VDP RAM
vram_addr_o => vram_addr_s,
vram_data_i => vram_do_s,
vram_data_o => vram_di_s,
vram_ce_o => open,--vram_ce_s,
vram_oe_o => open,--vram_oe_s,
vram_we_o => vram_we_s,
-- Keyboard
rows_o => rows_s,
cols_i => cols_s,
caps_en_o => caps_en_s,
keyb_valid_i => keyb_valid_s,
keyb_data_i => keyb_data_s,
keymap_addr_o => keymap_addr_s,
keymap_data_o => keymap_data_s,
keymap_we_o => keymap_we_s,
-- Audio
audio_scc_o => audio_scc_s,
audio_psg_o => audio_psg_s,
beep_o => beep_s,
volumes_o => volumes_s,
-- K7
k7_motor_o => open,
k7_audio_o => mic_o,
k7_audio_i => ear_i,
-- Joystick
joy1_up_i => joy1_up_i,
joy1_down_i => joy1_down_i,
joy1_left_i => joy1_left_i,
joy1_right_i => joy1_right_i,
joy1_btn1_i => joy1_p6_i,
joy1_btn1_o => open,
joy1_btn2_i => joy1_p9_i,
joy1_btn2_o => open,
joy1_out_o => joy1_out_s,
joy2_up_i => joy2_up_i,
joy2_down_i => joy2_down_i,
joy2_left_i => joy2_left_i,
joy2_right_i => joy2_right_i,
joy2_btn1_i => joy2_p6_i,
joy2_btn1_o => open,
joy2_btn2_i => joy2_p9_i,
joy2_btn2_o => open,
joy2_out_o => joy2_out_s,
-- Video
cnt_hor_o => cnt_hor_s,
cnt_ver_o => cnt_ver_s,
rgb_r_o => rgb_col_s,
rgb_g_o => open,
rgb_b_o => open,
hsync_n_o => open,
vsync_n_o => open,
ntsc_pal_o => open,
vga_on_k_i => '0',
scanline_on_k_i=> '0',
vga_en_o => open,
-- SPI/SD
spi_cs_n_o => sd_cs_n_o,
spi_sclk_o => sd_sclk_o,
spi_mosi_o => sd_mosi_o,
spi_miso_i => sd_miso_i,
sd_pres_n_i => '0',
sd_wp_i => '0',
-- DEBUG
D_wait_o => open,
D_slots_o => open,
D_ipl_en_o => open
);
joyX_p7_o <= not joy1_out_s; -- for Sega Genesis joypad
--joy2_p7_o <= not joy2_out_s; -- for Sega Genesis joypad
-- RAM
ram: entity work.ssdram256Mb
generic map (
freq_g => 85
)
port map (
clock_i => clock_sdram_s,
reset_i => reset_s,
refresh_i => '1',
-- Static RAM bus
addr_i => "00" & ram_addr_s,
data_i => ram_data_to_s,
data_o => ram_data_from_s,
cs_i => ram_ce_s,
oe_i => ram_oe_s,
we_i => ram_we_s,
-- SD-RAM ports
mem_cke_o => sdram_cke_o,
mem_cs_n_o => sdram_cs_o,
mem_ras_n_o => sdram_ras_o,
mem_cas_n_o => sdram_cas_o,
mem_we_n_o => sdram_we_o,
mem_udq_o => sdram_dqm_o(1),
mem_ldq_o => sdram_dqm_o(0),
mem_ba_o => sdram_ba_o,
mem_addr_o => sdram_ad_o,
mem_data_io => sdram_da_io
);
-- VRAM
vram: entity work.spram
generic map (
addr_width_g => 14,
data_width_g => 8
)
port map (
clk_i => clock_master_s,
we_i => vram_we_s,
addr_i => vram_addr_s,
data_i => vram_di_s,
data_o => vram_do_s
);
-- Keyboard PS/2
keyb: entity work.keyboard
port map (
clock_i => clock_3m_s,
reset_i => reset_s,
-- MSX
rows_coded_i => rows_s,
cols_o => cols_s,
keymap_addr_i => keymap_addr_s,
keymap_data_i => keymap_data_s,
keymap_we_i => keymap_we_s,
-- LEDs
led_caps_i => caps_en_s,
-- PS/2 interface
ps2_clk_io => ps2_clk_io,
ps2_data_io => ps2_data_io,
-- Direct Access
keyb_valid_o => keyb_valid_s,
keyb_data_o => keyb_data_s,
--
reset_o => soft_reset_k_s,
por_o => soft_por_s,
reload_core_o => open,
extra_keys_o => extra_keys_s
);
-- Audio
mixer: entity work.mixeru
port map (
clock_i => clock_master_s,
reset_i => reset_s,
volumes_i => volumes_s,
beep_i => beep_s,
ear_i => ear_i,
audio_scc_i => audio_scc_s,
audio_psg_i => audio_psg_s,
jt51_left_i => jt51_left_s,
jt51_right_i => jt51_right_s,
opll_mo_i => opll_mo_s,
opll_ro_i => opll_ro_s,
audio_mix_l_o => audio_l_s,
audio_mix_r_o => audio_r_s
);
audio_l_amp_s <= audio_l_s(15) & audio_l_s(13 downto 0) & "0";
audio_r_amp_s <= audio_r_s(15) & audio_r_s(13 downto 0) & "0";
-- Left Channel
audiol : entity work.dac
generic map (
nbits_g => 16
)
port map (
reset_i => reset_s,
clock_i => clock_3m_s,
dac_i => audio_l_amp_s,
dac_o => dac_l_o
);
-- Right Channel
audior : entity work.dac
generic map (
nbits_g => 16
)
port map (
reset_i => reset_s,
clock_i => clock_3m_s,
dac_i => audio_r_amp_s,
dac_o => dac_r_o
);
-- Glue logic
-- Resets
btn_por_n_s <= btn_n_i(2) or btn_n_i(4);
btn_reset_n_s <= btn_n_i(3) or btn_n_i(4);
por_s <= '1' when pll_locked_s = '0' or soft_por_s = '1' or btn_por_n_s = '0' else '0';
reset_s <= '1' when soft_rst_cnt_s = X"01" or btn_reset_n_s = '0' else '0';
process(reset_s, clock_master_s)
begin
if reset_s = '1' then
soft_rst_cnt_s <= X"00";
elsif rising_edge(clock_master_s) then
if (soft_reset_k_s = '1' or soft_reset_s_s = '1' or por_s = '1') and soft_rst_cnt_s = X"00" then
soft_rst_cnt_s <= X"FF";
elsif soft_rst_cnt_s /= X"00" then
soft_rst_cnt_s <= soft_rst_cnt_s - 1;
end if;
end if;
end process;
---------------------------------
-- scanlines
btnscl: entity work.debounce
generic map (
counter_size_g => 16
)
port map (
clk_i => clock_master_s,
button_i => btn_n_i(1) or btn_n_i(2),
result_o => btn_scan_s
);
process (por_s, btn_scan_s)
begin
if por_s = '1' then
scanlines_en_s <= '0';
elsif falling_edge(btn_scan_s) then
scanlines_en_s <= not scanlines_en_s;
end if;
end process;
-- VGA framebuffer
vga: entity work.vga
port map (
I_CLK => clock_master_s,
I_CLK_VGA => clock_vga_s,
I_COLOR => rgb_col_s,
I_HCNT => cnt_hor_s,
I_VCNT => cnt_ver_s,
O_HSYNC => vga_hsync_n_s,
O_VSYNC => vga_vsync_n_s,
O_COLOR => vga_col_s,
O_HCNT => open,
O_VCNT => open,
O_H => open,
O_BLANK => vga_blank_s
);
-- Scanlines
process(vga_hsync_n_s,vga_vsync_n_s)
begin
if vga_vsync_n_s = '0' then
odd_line_s <= '0';
elsif rising_edge(vga_hsync_n_s) then
odd_line_s <= not odd_line_s;
end if;
end process;
-- Index => RGB
process (clock_vga_s)
variable vga_col_v : integer range 0 to 15;
variable vga_rgb_v : std_logic_vector(15 downto 0);
variable vga_r_v : std_logic_vector( 3 downto 0);
variable vga_g_v : std_logic_vector( 3 downto 0);
variable vga_b_v : std_logic_vector( 3 downto 0);
type ram_t is array (natural range 0 to 15) of std_logic_vector(15 downto 0);
constant rgb_c : ram_t := (
-- RB0G
0 => X"0000",
1 => X"0000",
2 => X"240C",
3 => X"570D",
4 => X"5E05",
5 => X"7F07",
6 => X"D405",
7 => X"4F0E",
8 => X"F505",
9 => X"F707",
10 => X"D50C",
11 => X"E80C",
12 => X"230B",
13 => X"CB09",
14 => X"CC0C",
15 => X"FF0F"
);
begin
if rising_edge(clock_vga_s) then
vga_col_v := to_integer(unsigned(vga_col_s));
vga_rgb_v := rgb_c(vga_col_v);
if scanlines_en_s = '1' then
--
if vga_rgb_v(15 downto 12) > 1 and odd_line_s = '1' then
vga_r_s <= vga_rgb_v(15 downto 12) - 2;
else
vga_r_s <= vga_rgb_v(15 downto 12);
end if;
--
if vga_rgb_v(11 downto 8) > 1 and odd_line_s = '1' then
vga_b_s <= vga_rgb_v(11 downto 8) - 2;
else
vga_b_s <= vga_rgb_v(11 downto 8);
end if;
--
if vga_rgb_v(3 downto 0) > 1 and odd_line_s = '1' then
vga_g_s <= vga_rgb_v(3 downto 0) - 2;
else
vga_g_s <= vga_rgb_v(3 downto 0);
end if;
else
vga_r_s <= vga_rgb_v(15 downto 12);
vga_b_s <= vga_rgb_v(11 downto 8);
vga_g_s <= vga_rgb_v( 3 downto 0);
end if;
end if;
end process;
sound_hdmi_l_s <= '0' & std_logic_vector(audio_l_amp_s(15 downto 1));
sound_hdmi_r_s <= '0' & std_logic_vector(audio_r_amp_s(15 downto 1));
-- HDMI
hdmi: entity work.hdmi
generic map (
FREQ => 25200000, -- pixel clock frequency
FS => 48000, -- audio sample rate - should be 32000, 41000 or 48000 = 48KHz
CTS => 25200, -- CTS = Freq(pixclk) * N / (128 * Fs)
N => 6144 -- N = 128 * Fs /1000, 128 * Fs /1500 <= N <= 128 * Fs /300 (Check HDMI spec 7.2 for details)
)
port map (
I_CLK_PIXEL => clock_vga_s,
I_R => vga_r_s & vga_r_s,
I_G => vga_g_s & vga_g_s,
I_B => vga_b_s & vga_b_s,
I_BLANK => vga_blank_s,
I_HSYNC => vga_hsync_n_s,
I_VSYNC => vga_vsync_n_s,
-- PCM audio
I_AUDIO_ENABLE => '1',
I_AUDIO_PCM_L => sound_hdmi_l_s,
I_AUDIO_PCM_R => sound_hdmi_r_s,
-- TMDS parallel pixel synchronous outputs (serialize LSB first)
O_RED => tdms_r_s,
O_GREEN => tdms_g_s,
O_BLUE => tdms_b_s
);
hdmio: entity work.hdmi_out_altera
port map (
clock_pixel_i => clock_vga_s,
clock_tdms_i => clock_dvi_s,
red_i => tdms_r_s,
green_i => tdms_g_s,
blue_i => tdms_b_s,
tmds_out_p => tdms_p_s,
tmds_out_n => tdms_n_s
);
tmds_o(7) <= tdms_p_s(2); -- 2+
tmds_o(6) <= tdms_n_s(2); -- 2-
tmds_o(5) <= tdms_p_s(1); -- 1+
tmds_o(4) <= tdms_n_s(1); -- 1-
tmds_o(3) <= tdms_p_s(0); -- 0+
tmds_o(2) <= tdms_n_s(0); -- 0-
tmds_o(1) <= tdms_p_s(3); -- CLK+
tmds_o(0) <= tdms_n_s(3); -- CLK-
vga_r_o <= vga_r_s & '0';
vga_g_o <= vga_g_s & '0';
vga_b_o <= vga_b_s & '0';
vga_hsync_n_o <= vga_hsync_n_s;
vga_vsync_n_o <= vga_vsync_n_s;
-- Peripheral BUS control
bus_data_from_s <= jt51_data_from_s when jt51_hd_s = '1' else
-- midi_data_from_s when midi_hd_s = '1' else
(others => '1');
bus_wait_n_s <= '1';--midi_wait_n_s;
bus_int_n_s <= '1';--midi_int_n_s;
-- JT51
jt51_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0010000" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '1'; -- 0x20 - 0x21
jt51: entity work.jt51_wrapper
port map (
clock_i => clock_3m_s,
reset_i => reset_s,
addr_i => bus_addr_s(0),
cs_n_i => jt51_cs_n_s,
wr_n_i => bus_wr_n_s,
rd_n_i => bus_rd_n_s,
data_i => bus_data_to_s,
data_o => jt51_data_from_s,
has_data_o => jt51_hd_s,
ct1_o => open,
ct2_o => open,
irq_n_o => open,
p1_o => open,
-- Low resolution output (same as real chip)
sample_o => open,
left_o => open,
right_o => open,
-- Full resolution output
xleft_o => jt51_left_s,
xright_o => jt51_right_s,
-- unsigned outputs for sigma delta converters, full resolution
dacleft_o => open,
dacright_o => open
);
-- OPLL
opll_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0111110" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '1'; -- 0x7C - 0x7D
opll1 : entity work.opll
port map (
clock_i => clock_master_s,
clock_en_i => clock_psg_en_s,
reset_i => reset_s,
data_i => bus_data_to_s,
addr_i => bus_addr_s(0),
cs_n => opll_cs_n_s,
we_n => bus_wr_n_s,
melody_o => opll_mo_s,
rythm_o => opll_ro_s
);
-- MIDI
-- midi_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0111111" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '1'; -- 0x7E - 0x7F
-- MIDI interface
-- midi: entity work.midiIntf
-- port map (
-- clock_i => clock_8m_s,
-- reset_i => reset_s,
-- addr_i => bus_addr_s(0),
-- cs_n_i => midi_cs_n_s,
-- wr_n_i => bus_wr_n_s,
-- rd_n_i => bus_rd_n_s,
-- data_i => bus_data_to_s,
-- data_o => midi_data_from_s,
-- has_data_o => midi_hd_s,
-- -- Outs
-- int_n_o => midi_int_n_s,
-- wait_n_o => midi_wait_n_s,
-- tx_o => uart_tx_o
-- );
-- DEBUG
-- leds_n_o(0) <= not turbo_on_s;
-- leds_n_o(1) <= not caps_en_s;
-- leds_n_o(2) <= not soft_reset_k_s;
-- leds_n_o(3) <= not soft_por_s;
end architecture;
|
gpl-3.0
|
sittner/lcnc-mdsio
|
vhdl/source/mdsio/dac_mod.vhd
|
1
|
6734
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DAC_MOD is
generic (
-- IO-REQ: 3 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000011";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
OUT_EN: in std_logic;
SCLK_EDGE: in std_logic;
SCLK_STATE: in std_logic;
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_DATA_IN: in std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
WB_STB_WR: in std_logic;
SV : inout std_logic_vector(10 downto 3)
);
end;
architecture rtl of DAC_MOD is
constant CMD_WriteA: std_logic_vector(7 downto 0) := "00000000";
constant CMD_WriteB_LoadAB: std_logic_vector(7 downto 0) := "00110100";
signal wb_data_mux : std_logic_vector(31 downto 0);
signal shift_cnt: std_logic_vector(4 downto 0);
signal bitcnt_sync: std_logic;
signal bitcnt_top: std_logic;
signal dac1_data: std_logic_vector(15 downto 0);
signal dac2_data: std_logic_vector(15 downto 0);
signal dac2_reg: std_logic_vector(15 downto 0);
signal dac3_data: std_logic_vector(15 downto 0);
signal dac4_data: std_logic_vector(15 downto 0);
signal dac4_reg: std_logic_vector(15 downto 0);
signal dac5_data: std_logic_vector(15 downto 0);
signal dac6_data: std_logic_vector(15 downto 0);
signal dac6_reg: std_logic_vector(15 downto 0);
signal ssync: std_logic;
signal sclk: std_logic;
signal select_ab: std_logic;
signal dac12_shift: std_logic_vector(23 downto 0);
signal dac34_shift: std_logic_vector(23 downto 0);
signal dac56_shift: std_logic_vector(23 downto 0);
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR)
begin
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
wb_data_mux(15 downto 0) <= dac1_data;
wb_data_mux(31 downto 16) <= dac2_data;
when WB_ADDR_OFFSET + 1 =>
wb_data_mux(15 downto 0) <= dac3_data;
wb_data_mux(31 downto 16) <= dac4_data;
when WB_ADDR_OFFSET + 2 =>
wb_data_mux(15 downto 0) <= dac5_data;
wb_data_mux(31 downto 16) <= dac6_data;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
P_PE_REG_WR : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
dac1_data <= (others => '0');
dac2_data <= (others => '0');
dac3_data <= (others => '0');
dac4_data <= (others => '0');
dac5_data <= (others => '0');
dac6_data <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_WR = '1' then
case WB_ADDR is
when WB_ADDR_OFFSET =>
dac1_data <= WB_DATA_IN(15 downto 0);
dac2_data <= WB_DATA_IN(31 downto 16);
when WB_ADDR_OFFSET + 1 =>
dac3_data <= WB_DATA_IN(15 downto 0);
dac4_data <= WB_DATA_IN(31 downto 16);
when WB_ADDR_OFFSET + 2 =>
dac5_data <= WB_DATA_IN(15 downto 0);
dac6_data <= WB_DATA_IN(31 downto 16);
when others =>
end case;
end if;
end if;
end process;
----------------------------------------------------------
--- serial clock
----------------------------------------------------------
p_sclk: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
ssync <= '0';
sclk <= '0';
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' then
ssync <= '0';
sclk <= '0';
if SCLK_STATE = '0' then
if bitcnt_sync = '1' then
ssync <= '1';
else
sclk <= '1';
end if;
end if;
end if;
end if;
end process;
----------------------------------------------------------
--- shift counter
----------------------------------------------------------
p_bitcnt_cnt: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
shift_cnt <= (others => '0');
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '1' then
if bitcnt_top = '1' then
shift_cnt <= (others => '0');
else
shift_cnt <= shift_cnt + 1;
end if;
end if;
end if;
end process;
bitcnt_sync <= '1' when shift_cnt = 23 else '0';
bitcnt_top <= '1' when shift_cnt = 24 else '0';
----------------------------------------------------------
--- output shift
----------------------------------------------------------
p_so_out_shift: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
dac12_shift <= (others => '0');
dac34_shift <= (others => '0');
dac56_shift <= (others => '0');
dac2_reg <= (others => '0');
dac4_reg <= (others => '0');
dac6_reg <= (others => '0');
select_ab <= '0';
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if bitcnt_top = '1' then
if select_ab = '0' then
dac12_shift <= CMD_WriteA & dac1_data;
dac34_shift <= CMD_WriteA & dac3_data;
dac56_shift <= CMD_WriteA & dac5_data;
dac2_reg <= dac2_data;
dac4_reg <= dac4_data;
dac6_reg <= dac6_data;
else
dac12_shift <= CMD_WriteB_LoadAB & dac2_reg;
dac34_shift <= CMD_WriteB_LoadAB & dac4_reg;
dac56_shift <= CMD_WriteB_LoadAB & dac6_reg;
end if;
select_ab <= not select_ab;
else
dac12_shift <= dac12_shift(22 downto 0) & "1";
dac34_shift <= dac34_shift(22 downto 0) & "1";
dac56_shift <= dac56_shift(22 downto 0) & "1";
end if;
end if;
end if;
end process;
----------------------------------------------------------
--- output mapping
----------------------------------------------------------
SV(3) <= '0';
SV(4) <= '0';
SV(5) <= not ssync;
SV(6) <= not sclk;
SV(7) <= not dac56_shift(23);
SV(8) <= not dac34_shift(23);
SV(9) <= not dac12_shift(23);
SV(10) <= OUT_EN;
end;
|
gpl-3.0
|
freecores/usb_fpga_1_2
|
examples/usb-fpga-1.11/1.11c/memtest/fpga/memtest.vhd
|
16
|
23751
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity memtest is
port(
FXCLK : in std_logic;
RESET_IN : in std_logic;
IFCLK : in std_logic;
-- FX2 FIFO
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic;
PA3 : in std_logic;
-- errors ...
PC : out std_logic_vector(7 downto 0);
-- DDR-SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end memtest;
architecture RTL of memtest is
component dcm0
port (
-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic;
CLK_VALID : out std_logic
);
end component;
component mem0
generic (
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_RST_ACT_LOW : integer := 0;
C3_CALIB_SOFT_IP : string := "FALSE";
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;
signal CLK : std_logic;
signal RESET0 : std_logic; -- released after dcm0 is ready
signal RESET : std_logic; -- released after MCB is ready
signal DCM0_LOCKED : std_logic;
signal DCM0_CLK_VALID : std_logic;
----------------------------
-- test pattern generator --
----------------------------
signal GEN_CNT : std_logic_vector(29 downto 0);
signal GEN_PATTERN : std_logic_vector(29 downto 0);
signal FIFO_WORD : std_logic;
-----------------------
-- memory controller --
-----------------------
signal MEM_CLK : std_logic;
signal C3_CALIB_DONE : std_logic;
signal C3_RST0 : std_logic;
---------------
-- DRAM FIFO --
---------------
signal WR_CLK : std_logic;
signal WR_CMD_EN : std_logic_vector(2 downto 0);
type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal WR_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal WR_EN : std_logic_vector(2 downto 0);
signal WR_EN_TMP : std_logic_vector(2 downto 0);
signal WR_DATA : std_logic_vector(31 downto 0);
signal WR_EMPTY : std_logic_vector(2 downto 0);
signal WR_UNDERRUN : std_logic_vector(2 downto 0);
signal WR_ERROR : std_logic_vector(2 downto 0);
type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal WR_COUNT : WR_COUNT_ARRAY;
signal WR_PORT : std_logic_vector(1 downto 0);
signal RD_CLK : std_logic;
signal RD_CMD_EN : std_logic_vector(2 downto 0);
type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal RD_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal RD_EN : std_logic_vector(2 downto 0);
type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
signal RD_DATA : RD_DATA_ARRAY;
signal RD_EMPTY : std_logic_vector(2 downto 0);
signal RD_OVERFLOW : std_logic_vector(2 downto 0);
signal RD_ERROR : std_logic_vector(2 downto 0);
signal RD_PORT : std_logic_vector(1 downto 0);
type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal RD_COUNT : RD_COUNT_ARRAY;
signal FD_TMP : std_logic_vector(15 downto 0);
signal RD_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing read
signal RD_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing written
signal WR_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_STOP : std_logic;
begin
inst_dcm0 : dcm0 port map(
-- Clock in ports
CLK_IN1 => FXCLK,
-- Clock out ports
CLK_OUT1 => MEM_CLK,
CLK_OUT2 => CLK,
-- Status and control signals
RESET => RESET_IN,
LOCKED => DCM0_LOCKED,
CLK_VALID => DCM0_CLK_VALID
);
inst_mem0 : mem0 port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => mcb3_rzq,
c3_sys_clk => MEM_CLK,
c3_sys_rst_n => RESET0,
c3_clk0 => open,
c3_rst0 => C3_RST0,
c3_calib_done => C3_CALIB_DONE,
c3_p0_cmd_clk => WR_CLK,
c3_p0_cmd_en => WR_CMD_EN(0),
c3_p0_cmd_instr => "000",
c3_p0_cmd_bl => ( others => '1' ),
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
c3_p0_cmd_empty => open,
c3_p0_cmd_full => open,
c3_p0_wr_clk => WR_CLK,
c3_p0_wr_en => WR_EN(0),
c3_p0_wr_mask => ( others => '0' ),
c3_p0_wr_data => WR_DATA,
c3_p0_wr_full => open,
c3_p0_wr_empty => WR_EMPTY(0),
c3_p0_wr_count => open,
c3_p0_wr_underrun => WR_UNDERRUN(0),
c3_p0_wr_error => WR_ERROR(0),
c3_p0_rd_clk => WR_CLK,
c3_p0_rd_en => '0',
c3_p0_rd_data => open,
c3_p0_rd_full => open,
c3_p0_rd_empty => open,
c3_p0_rd_count => open,
c3_p0_rd_overflow => open,
c3_p0_rd_error => open,
c3_p2_cmd_clk => WR_CLK,
c3_p2_cmd_en => WR_CMD_EN(1),
c3_p2_cmd_instr => "000",
c3_p2_cmd_bl => ( others => '1' ),
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
c3_p2_cmd_empty => open,
c3_p2_cmd_full => open,
c3_p2_wr_clk => WR_CLK,
c3_p2_wr_en => WR_EN(1),
c3_p2_wr_mask => ( others => '0' ),
c3_p2_wr_data => WR_DATA,
c3_p2_wr_full => open,
c3_p2_wr_empty => WR_EMPTY(1),
c3_p2_wr_count => open,
c3_p2_wr_underrun => WR_UNDERRUN(1),
c3_p2_wr_error => WR_ERROR(1),
c3_p4_cmd_clk => WR_CLK,
c3_p4_cmd_en => WR_CMD_EN(2),
c3_p4_cmd_instr => "000",
c3_p4_cmd_bl => ( others => '1' ),
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
c3_p4_cmd_empty => open,
c3_p4_cmd_full => open,
c3_p4_wr_clk => WR_CLK,
c3_p4_wr_en => WR_EN(2),
c3_p4_wr_mask => ( others => '0' ),
c3_p4_wr_data => WR_DATA,
c3_p4_wr_full => open,
c3_p4_wr_empty => WR_EMPTY(2),
c3_p4_wr_count => open,
c3_p4_wr_underrun => WR_UNDERRUN(2),
c3_p4_wr_error => WR_ERROR(2),
c3_p1_cmd_clk => RD_CLK,
c3_p1_cmd_en => RD_CMD_EN(0),
c3_p1_cmd_instr => "001",
c3_p1_cmd_bl => ( others => '1' ),
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
c3_p1_cmd_empty => open,
c3_p1_cmd_full => open,
c3_p1_wr_clk => RD_CLK,
c3_p1_wr_en => '0',
c3_p1_wr_mask => ( others => '0' ),
c3_p1_wr_data => ( others => '0' ),
c3_p1_wr_full => open,
c3_p1_wr_empty => open,
c3_p1_wr_count => open,
c3_p1_wr_underrun => open,
c3_p1_wr_error => open,
c3_p1_rd_clk => RD_CLK,
c3_p1_rd_en => RD_EN(0),
c3_p1_rd_data => RD_DATA(0),
c3_p1_rd_full => open,
c3_p1_rd_empty => RD_EMPTY(0),
c3_p1_rd_count => open,
c3_p1_rd_overflow => RD_OVERFLOW(0),
c3_p1_rd_error => RD_ERROR(0),
c3_p3_cmd_clk => RD_CLK,
c3_p3_cmd_en => RD_CMD_EN(1),
c3_p3_cmd_instr => "001",
c3_p3_cmd_bl => ( others => '1' ),
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_rd_clk => RD_CLK,
c3_p3_rd_en => RD_EN(1),
c3_p3_rd_data => RD_DATA(1),
c3_p3_rd_full => open,
c3_p3_rd_empty => RD_EMPTY(1),
c3_p3_rd_count => open,
c3_p3_rd_overflow => RD_OVERFLOW(1),
c3_p3_rd_error => RD_ERROR(1),
c3_p5_cmd_clk => RD_CLK,
c3_p5_cmd_en => RD_CMD_EN(2),
c3_p5_cmd_instr => "001",
c3_p5_cmd_bl => ( others => '1' ),
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
c3_p5_cmd_empty => open,
c3_p5_cmd_full => open,
c3_p5_rd_clk => RD_CLK,
c3_p5_rd_en => RD_EN(2),
c3_p5_rd_data => RD_DATA(2),
c3_p5_rd_full => open,
c3_p5_rd_empty => RD_EMPTY(2),
c3_p5_rd_count => open,
c3_p5_rd_overflow => RD_OVERFLOW(2),
c3_p5_rd_error => RD_ERROR(2)
);
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1';
WR_CLK <= CLK;
RD_CLK <= IFCLK;
RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
PC(0) <= WR_UNDERRUN(0) or WR_UNDERRUN(1) or WR_UNDERRUN(2);
PC(1) <= WR_ERROR(0) or WR_ERROR(1) or WR_ERROR(2);
PC(2) <= RD_OVERFLOW(0) or RD_OVERFLOW(1) or RD_OVERFLOW(2);
PC(3) <= RD_ERROR(0) or RD_ERROR(1) or RD_ERROR(2);
PC(4) <= C3_CALIB_DONE;
PC(5) <= C3_RST0;
PC(6) <= RESET0;
PC(7) <= RESET;
dpCLK: process (CLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
GEN_PATTERN <= "100101010101010101010101010101";
WR_CMD_EN <= ( others => '0' );
WR_CMD_ADDR(0) <= ( others => '0' );
WR_CMD_ADDR(1) <= ( others => '0' );
WR_CMD_ADDR(2) <= ( others => '0' );
WR_ADDR <= conv_std_logic_vector(3,18);
WR_EN <= ( others => '0' );
WR_COUNT(0) <= ( others => '0' );
WR_COUNT(1) <= ( others => '0' );
WR_COUNT(2) <= ( others => '0' );
WR_PORT <= ( others => '0' );
WR_ADDR2 <= ( others => '0' );
RD_ADDR2_BAK1 <= ( others => '0' );
RD_ADDR2_BAK2 <= ( others => '0' );
-- CLK
elsif CLK'event and CLK = '1'
then
WR_CMD_EN <= ( others => '0' );
WR_EN <= ( others => '0' );
WR_CMD_ADDR(conv_integer(WR_PORT))(25 downto 8) <= WR_ADDR;
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
then
-- FF flag = 1
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
then
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
if WR_PORT = "10"
then
WR_PORT <= "00";
else
WR_PORT <= WR_PORT + 1;
end if;
WR_ADDR <= WR_ADDR + 1;
WR_ADDR2 <= WR_ADDR2 + 1;
end if;
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
then
-- FF flag = 1
else
WR_EN(conv_integer(WR_PORT)) <= '1';
WR_DATA(31) <= '1';
WR_DATA(15) <= '0';
if PA3 = '1'
then
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
else
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
end if;
GEN_CNT <= GEN_CNT + 1;
GEN_PATTERN(29) <= GEN_PATTERN(0);
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
-- then
-- else
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
-- end if;
end if;
RD_ADDR2_BAK1 <= RD_ADDR2;
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
end if;
end process dpCLK;
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
FIFO_WORD <= '0';
SLWR <= '1';
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(0) <= ( others => '0' );
RD_CMD_ADDR(1) <= ( others => '0' );
RD_CMD_ADDR(2) <= ( others => '0' );
RD_ADDR <= conv_std_logic_vector(3,18);
RD_EN <= ( others => '0' );
RD_COUNT(0) <= conv_std_logic_vector(64,7);
RD_COUNT(1) <= conv_std_logic_vector(64,7);
RD_COUNT(2) <= conv_std_logic_vector(64,7);
RD_PORT <= ( others => '0' );
RD_ADDR2 <= ( others => '0' );
WR_ADDR2_BAK1 <= ( others => '0' );
WR_ADDR2_BAK2 <= ( others => '0' );
RD_STOP <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(conv_integer(RD_PORT))(25 downto 8) <= RD_ADDR;
RD_EN(conv_integer(RD_PORT)) <= '0';
if FLAGB = '1'
then
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
then
SLWR <= '1';
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
then
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
if RD_PORT = "10"
then
RD_PORT <= "00";
else
RD_PORT <= RD_PORT + 1;
end if;
RD_ADDR <= RD_ADDR + 1;
RD_ADDR2 <= RD_ADDR2 + 1;
end if;
else
SLWR <= '0';
if FIFO_WORD = '0'
then
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
RD_EN(conv_integer(RD_PORT)) <= '1';
else
FD(15 downto 0) <= FD_TMP;
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
end if;
WR_ADDR2_BAK1 <= WR_ADDR2;
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
then
RD_STOP <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
|
gpl-3.0
|
asicguy/gplgpu
|
hdl/sim_lib/hardcopyiv_pcie_hip_components.vhd
|
1
|
71800
|
-- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package HARDCOPYIV_PCIE_HIP_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function alpha_tolower (given_string : string) return string;
-- GENERIC utility functions END
--
-- hardcopyiv_pciehip_pciexp_dcfiforam
--
COMPONENT hardcopyiv_pciehip_pciexp_dcfiforam
GENERIC (
addr_width : INTEGER := 4;
data_width : INTEGER := 32
);
PORT (
data : IN STD_LOGIC_VECTOR((data_width - 1) DOWNTO 0);
wren : IN STD_LOGIC;
wraddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
wrclock : IN STD_LOGIC;
rdclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyiv_hssi_pcie_hip
--
COMPONENT hardcopyiv_hssi_pcie_hip
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bistenrcv0 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrcv1 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrpl : VitalDelayType01 := DefpropDelay01;
tipd_bistscanen : VitalDelayType01 := DefpropDelay01;
tipd_bistscanin : VitalDelayType01 := DefpropDelay01;
tipd_bisttesten : VitalDelayType01 := DefpropDelay01;
tipd_coreclkin : VitalDelayType01 := DefpropDelay01;
tipd_corecrst : VitalDelayType01 := DefpropDelay01;
tipd_corepor : VitalDelayType01 := DefpropDelay01;
tipd_corerst : VitalDelayType01 := DefpropDelay01;
tipd_coresrst : VitalDelayType01 := DefpropDelay01;
tipd_cplerr : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cplpending : VitalDelayType01 := DefpropDelay01;
tipd_dbgpipex1rx : VitalDelayArrayType01(15 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlaspmcr0 : VitalDelayType01 := DefpropDelay01;
tipd_dlcomclkreg : VitalDelayType01 := DefpropDelay01;
tipd_dlctrllink2 : VitalDelayArrayType01(13 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dldataupfc : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlhdrupfc : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlinhdllp : VitalDelayType01 := DefpropDelay01;
tipd_dlmaxploaddcr : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphycfg : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphypm : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlrequpfc : VitalDelayType01 := DefpropDelay01;
tipd_dlreqwake : VitalDelayType01 := DefpropDelay01;
tipd_dlrxecrcchk : VitalDelayType01 := DefpropDelay01;
tipd_dlsndupfc : VitalDelayType01 := DefpropDelay01;
tipd_dltxcfgextsy : VitalDelayType01 := DefpropDelay01;
tipd_dltxreqpm : VitalDelayType01 := DefpropDelay01;
tipd_dltxtyppm : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dltypupfc : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcctrl : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidmap : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidupfc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_extrain : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmiaddr : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmidin : VitalDelayArrayType01(32 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmirden : VitalDelayType01 := DefpropDelay01;
tipd_lmiwren : VitalDelayType01 := DefpropDelay01;
tipd_mode : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_mramhiptestenable : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanen : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanin : VitalDelayType01 := DefpropDelay01;
tipd_pclkcentral : VitalDelayType01 := DefpropDelay01;
tipd_pclkch0 : VitalDelayType01 := DefpropDelay01;
tipd_phyrst : VitalDelayType01 := DefpropDelay01;
tipd_physrst : VitalDelayType01 := DefpropDelay01;
tipd_phystatus : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pldclk : VitalDelayType01 := DefpropDelay01;
tipd_pldrst : VitalDelayType01 := DefpropDelay01;
tipd_pldsrst : VitalDelayType01 := DefpropDelay01;
tipd_pllfixedclk : VitalDelayType01 := DefpropDelay01;
tipd_rxdata : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatak : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidle : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxmaskvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxmaskvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxstatus : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxvalid : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanen : VitalDelayType01 := DefpropDelay01;
tipd_scanmoden : VitalDelayType01 := DefpropDelay01;
tipd_swdnin : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_swupin : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_testin : VitalDelayArrayType01(40 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlaermsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappintasts : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappmsireq : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsitc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlhpgctrler : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpexmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmauxpwr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmdata : VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmetocr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmevent : VitalDelayType01 := DefpropDelay01;
tipd_tlslotclkcfg : VitalDelayType01 := DefpropDelay01;
tipd_txdatavc00 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc01 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc10 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc11 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txeopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc1 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc1 : VitalDelayType01 := DefpropDelay01;
tpd_pldclk_clrrxpath_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackphypm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackrequpfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlacksndupfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentdeemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentspeed_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dldllreq_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrdll_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrphy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkautobdwstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkbdwmngstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlltssm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrpbufemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrstentercompbit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrsttxmarginfield_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxtyppm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxvalpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dltxackpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlupexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlvcstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev128ns_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev1us_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_extraclkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_hotrstexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_intstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_l2exit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_laneact_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_linkup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmidout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_resetstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_r2cerr0ext_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_serrout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_successspeednegoint_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swdnwake_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swuphotrst_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappintaack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappmsiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlpmetosr_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dataenablen_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriostate_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_type : STRING := "hardcopyiv_hssi_pcie_hip";
advanced_errors : STRING := "false";
allow_rx_valid_empty : STRING := "false"; -- july3,2008
bar0_64bit_mem_space : STRING := "true";
bar0_io_space : STRING := "false";
bar0_prefetchable : STRING := "true";
bar0_size_mask : INTEGER := 32;
bar1_64bit_mem_space : STRING := "false";
bar1_io_space : STRING := "false";
bar1_prefetchable : STRING := "false";
bar1_size_mask : INTEGER := 4;
bar2_64bit_mem_space : STRING := "false";
bar2_io_space : STRING := "false";
bar2_prefetchable : STRING := "false";
bar2_size_mask : INTEGER := 4;
bar3_64bit_mem_space : STRING := "false";
bar3_io_space : STRING := "false";
bar3_prefetchable : STRING := "false";
bar3_size_mask : INTEGER := 4;
bar4_64bit_mem_space : STRING := "false";
bar4_io_space : STRING := "false";
bar4_prefetchable : STRING := "false";
bar4_size_mask : INTEGER := 4;
bar5_64bit_mem_space : STRING := "false";
bar5_io_space : STRING := "false";
bar5_prefetchable : STRING := "false";
bar5_size_mask : INTEGER := 4;
bar_io_window_size : STRING := "NONE";
bar_prefetchable : INTEGER := 0;
base_address : INTEGER := 0;
bridge_port_ssid_support : STRING := "false";
bridge_port_vga_enable : STRING := "false";
bypass_cdc : STRING := "false";
bypass_tl : STRING := "false";
class_code : INTEGER := 16711680;
completion_timeout : STRING := "ABCD";
core_clk_divider : INTEGER := 1;
core_clk_source : STRING := "PLL_FIXED_CLK";
credit_buffer_allocation_aux : STRING := "BALANCED";
deemphasis_enable : STRING := "false";
device_address : INTEGER := 0;
device_id : INTEGER := 1;
device_number : INTEGER := 0;
diffclock_nfts_count : INTEGER := 128;
disable_async_l2_logic : STRING := "false"; -- july2,2008
disable_cdc_clk_ppm : STRING := "true";
disable_device_number_mismatch : STRING := "false";
disable_link_x2_support : STRING := "false";
disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
dll_active_report_support : STRING := "false";
ei_delay_powerdown_count : INTEGER := 10;
eie_before_nfts_count : INTEGER := 4;
enable_adapter_half_rate_mode : STRING := "false";
enable_ch0_pclk_out : STRING := "false";
enable_completion_timeout_disable : STRING := "true";
enable_coreclk_out_half_rate : STRING := "false";
enable_d1pm_support : STRING := "false";
enable_d2pm_support : STRING := "false";
enable_ecrc_check : STRING := "false";
enable_ecrc_gen : STRING := "false";
enable_function_msi_support : STRING := "true";
enable_function_msix_support : STRING := "false";
enable_gen2_core : STRING := "true";
enable_hip_x1_loopback : STRING := "false";
enable_l1_aspm : STRING := "false";
enable_msi_64bit_addressing : STRING := "true";
enable_msi_masking : STRING := "false";
enable_rcv0buf_a_we : STRING := "true";
enable_rcv0buf_b_re : STRING := "true";
enable_rcv0buf_output_regs : STRING := "false";
enable_rcv1buf_a_we : STRING := "true";
enable_rcv1buf_b_re : STRING := "true";
enable_rcv1buf_output_regs : STRING := "false";
enable_retrybuf_a_we : STRING := "true";
enable_retrybuf_b_re : STRING := "true";
enable_retrybuf_ecc : STRING := "false"; -- ww12
enable_retrybuf_output_regs : STRING := "false";
enable_retrybuf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx0buf_ecc : STRING := "false"; -- ww12
enable_rx0buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx1buf_ecc : STRING := "false"; -- ww12
enable_rx1buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx_buffer_checking : STRING := "false";
enable_rx_ei_l0s_exit_refined : STRING := "false";
enable_rx_reordering : STRING := "true";
enable_slot_register : STRING := "false";
endpoint_l0_latency : INTEGER := 0;
endpoint_l1_latency : INTEGER := 0;
expansion_base_address_register : INTEGER := 0;
extend_tag_field : STRING := "false";
fc_init_timer : INTEGER := 1024;
flow_control_timeout_count : INTEGER := 200;
flow_control_update_count : INTEGER := 30;
gen2_diffclock_nfts_count : INTEGER := 255;
gen2_lane_rate_mode : STRING := "false";
gen2_sameclock_nfts_count : INTEGER := 255;
hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
iei_logic : STRING := "IEI_IIIS";
indicator : INTEGER := 7;
l01_entry_latency : INTEGER := 31;
l0_exit_latency_diffclock : INTEGER := 6;
l0_exit_latency_sameclock : INTEGER := 6;
l1_exit_latency_diffclock : INTEGER := 0;
l1_exit_latency_sameclock : INTEGER := 0;
lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000";
low_priority_vc : INTEGER := 0;
max_link_width : INTEGER := 4;
max_payload_size : INTEGER := 2;
maximum_current : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
millisecond_cycle_count : INTEGER := 0;
mram_bist_settings : STRING := "";
msi_function_count : INTEGER := 2;
msix_pba_bir : INTEGER := 0;
msix_pba_offset : INTEGER := 0;
msix_table_bir : INTEGER := 0;
msix_table_offset : INTEGER := 0;
msix_table_size : INTEGER := 0;
no_command_completed : STRING := "true";
no_soft_reset : STRING := "false";
pcie_mode : STRING := "SHARED_MODE";
pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
port_link_number : INTEGER := 1;
port_address : INTEGER := 0;
register_pipe_signals : STRING := "false";
retry_buffer_last_active_address : INTEGER := 2047;
retry_buffer_memory_settings : INTEGER := 0;
revision_id : INTEGER := 1;
rx0_adap_fifo_full_value : INTEGER := 9;
rx1_adap_fifo_full_value : INTEGER := 9;
rx_cdc_full_value : INTEGER := 12;
rx_idl_os_count : INTEGER := 0;
rx_ptr0_nonposted_dpram_max : INTEGER := 0;
rx_ptr0_nonposted_dpram_min : INTEGER := 0;
rx_ptr0_posted_dpram_max : INTEGER := 0;
rx_ptr0_posted_dpram_min : INTEGER := 0;
rx_ptr1_nonposted_dpram_max : INTEGER := 0;
rx_ptr1_nonposted_dpram_min : INTEGER := 0;
rx_ptr1_posted_dpram_max : INTEGER := 0;
rx_ptr1_posted_dpram_min : INTEGER := 0;
sameclock_nfts_count : INTEGER := 128;
single_rx_detect : INTEGER := 0;
skp_os_schedule_count : INTEGER := 0;
slot_number : INTEGER := 0;
slot_power_limit : INTEGER := 0;
slot_power_scale : INTEGER := 0;
ssid : INTEGER := 0;
ssvid : INTEGER := 0;
subsystem_device_id : INTEGER := 1;
subsystem_vendor_id : INTEGER := 4466;
surprise_down_error_support : STRING := "false";
tx0_adap_fifo_full_value : INTEGER := 11;
tx1_adap_fifo_full_value : INTEGER := 11;
tx_cdc_full_value : INTEGER := 12;
tx_cdc_stop_dummy_full_value : INTEGER := 11;
use_crc_forwarding : STRING := "false";
vc0_clk_enable : STRING := "true";
vc0_rx_buffer_memory_settings : INTEGER := 0;
vc0_rx_flow_ctrl_compl_data : INTEGER := 448;
vc0_rx_flow_ctrl_compl_header : INTEGER := 112;
vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc0_rx_flow_ctrl_posted_data : INTEGER := 360;
vc0_rx_flow_ctrl_posted_header : INTEGER := 50;
vc1_clk_enable : STRING := "false";
vc1_rx_buffer_memory_settings : INTEGER := 0;
vc1_rx_flow_ctrl_compl_data : INTEGER := 448;
vc1_rx_flow_ctrl_compl_header : INTEGER := 112;
vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc1_rx_flow_ctrl_posted_data : INTEGER := 360;
vc1_rx_flow_ctrl_posted_header : INTEGER := 50;
vc_arbitration : INTEGER := 1;
vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
vendor_id : INTEGER := 4466
);
PORT (
bistenrcv0 : IN STD_LOGIC := '0';
bistenrcv1 : IN STD_LOGIC := '0';
bistenrpl : IN STD_LOGIC := '0';
bistscanen : IN STD_LOGIC := '0';
bistscanin : IN STD_LOGIC := '0';
bisttesten : IN STD_LOGIC := '0';
coreclkin : IN STD_LOGIC := '0';
corecrst : IN STD_LOGIC := '0';
corepor : IN STD_LOGIC := '0';
corerst : IN STD_LOGIC := '0';
coresrst : IN STD_LOGIC := '0';
cplerr : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
cplpending : IN STD_LOGIC := '0';
dbgpipex1rx : IN STD_LOGIC_VECTOR(15 - 1 DOWNTO 0) := (others => '0');
dlaspmcr0 : IN STD_LOGIC := '0';
dlcomclkreg : IN STD_LOGIC := '0';
dlctrllink2 : IN STD_LOGIC_VECTOR(13 - 1 DOWNTO 0) := (others => '0');
dldataupfc : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
dlhdrupfc : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlinhdllp : IN STD_LOGIC := '1';
dlmaxploaddcr : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dlreqphycfg : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlreqphypm : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlrequpfc : IN STD_LOGIC := '0';
dlreqwake : IN STD_LOGIC := '0';
dlrxecrcchk : IN STD_LOGIC := '0';
dlsndupfc : IN STD_LOGIC := '0';
dltxcfgextsy : IN STD_LOGIC := '0';
dltxreqpm : IN STD_LOGIC := '0';
dltxtyppm : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dltypupfc : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
dlvcctrl : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlvcidmap : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
dlvcidupfc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extrain : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmiaddr : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmidin : IN STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (others => '0');
lmirden : IN STD_LOGIC := '0';
lmiwren : IN STD_LOGIC := '0';
mode : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
mramhiptestenable : IN STD_LOGIC := '0';
mramregscanen : IN STD_LOGIC := '0';
mramregscanin : IN STD_LOGIC := '0';
pclkcentral : IN STD_LOGIC := '0';
pclkch0 : IN STD_LOGIC := '0';
phyrst : IN STD_LOGIC := '0';
physrst : IN STD_LOGIC := '0';
phystatus : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
pldclk : IN STD_LOGIC := '0';
pldrst : IN STD_LOGIC := '0';
pldsrst : IN STD_LOGIC := '0';
pllfixedclk : IN STD_LOGIC := '0';
rxdata : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
rxdatak : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxelecidle : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxmaskvc0 : IN STD_LOGIC := '0';
rxmaskvc1 : IN STD_LOGIC := '0';
rxreadyvc0 : IN STD_LOGIC := '0';
rxreadyvc1 : IN STD_LOGIC := '0';
rxstatus : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
rxvalid : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
scanen : IN STD_LOGIC := '0';
scanmoden : IN STD_LOGIC := '0';
swdnin : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
swupin : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(40 - 1 DOWNTO 0) := (others => '0');
tlaermsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappintasts : IN STD_LOGIC := '0';
tlappmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappmsireq : IN STD_LOGIC := '0';
tlappmsitc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
tlhpgctrler : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpexmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpmauxpwr : IN STD_LOGIC := '0';
tlpmdata : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
tlpmetocr : IN STD_LOGIC := '0';
tlpmevent : IN STD_LOGIC := '0';
tlslotclkcfg : IN STD_LOGIC := '0';
txdatavc00 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc01 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc10 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc11 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txeopvc00 : IN STD_LOGIC := '0';
txeopvc01 : IN STD_LOGIC := '0';
txeopvc10 : IN STD_LOGIC := '0';
txeopvc11 : IN STD_LOGIC := '0';
txerrvc0 : IN STD_LOGIC := '0';
txerrvc1 : IN STD_LOGIC := '0';
txsopvc00 : IN STD_LOGIC := '0';
txsopvc01 : IN STD_LOGIC := '0';
txsopvc10 : IN STD_LOGIC := '0';
txsopvc11 : IN STD_LOGIC := '0';
txvalidvc0 : IN STD_LOGIC := '0';
txvalidvc1 : IN STD_LOGIC := '0';
bistdonearcv0 : OUT STD_LOGIC;
bistdonearcv1 : OUT STD_LOGIC;
bistdonearpl : OUT STD_LOGIC;
bistdonebrcv0 : OUT STD_LOGIC;
bistdonebrcv1 : OUT STD_LOGIC;
bistdonebrpl : OUT STD_LOGIC;
bistpassrcv0 : OUT STD_LOGIC;
bistpassrcv1 : OUT STD_LOGIC;
bistpassrpl : OUT STD_LOGIC;
bistscanoutrcv0 : OUT STD_LOGIC;
bistscanoutrcv1 : OUT STD_LOGIC;
bistscanoutrpl : OUT STD_LOGIC;
clrrxpath : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataenablen : OUT STD_LOGIC;
derrcorextrcv0 : OUT STD_LOGIC;
derrcorextrcv1 : OUT STD_LOGIC;
derrcorextrpl : OUT STD_LOGIC;
derrrpl : OUT STD_LOGIC;
dlackphypm : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dlackrequpfc : OUT STD_LOGIC;
dlacksndupfc : OUT STD_LOGIC;
dlcurrentdeemp : OUT STD_LOGIC;
dlcurrentspeed : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dldllreq : OUT STD_LOGIC;
dlerrdll : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlerrphy : OUT STD_LOGIC;
dllinkautobdwstatus : OUT STD_LOGIC;
dllinkbdwmngstatus : OUT STD_LOGIC;
dlltssm : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlrpbufemp : OUT STD_LOGIC;
dlrstentercompbit : OUT STD_LOGIC;
dlrsttxmarginfield : OUT STD_LOGIC;
dlrxtyppm : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
dlrxvalpm : OUT STD_LOGIC;
dltxackpm : OUT STD_LOGIC;
dlup : OUT STD_LOGIC;
dlupexit : OUT STD_LOGIC;
dlvcstatus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC;
dpriostate : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
eidleinfersel : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
ev128ns : OUT STD_LOGIC;
ev1us : OUT STD_LOGIC;
extraclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
extraout : OUT STD_LOGIC_VECTOR(15 - 1 DOWNTO 0);
gen2rate : OUT STD_LOGIC;
gen2rategnd : OUT STD_LOGIC;
hotrstexit : OUT STD_LOGIC;
intstatus : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
l2exit : OUT STD_LOGIC;
laneact : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
linkup : OUT STD_LOGIC;
lmiack : OUT STD_LOGIC;
lmidout : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
ltssml0state : OUT STD_LOGIC;
mramregscanout : OUT STD_LOGIC;
powerdown : OUT STD_LOGIC_VECTOR(16 - 1 DOWNTO 0);
resetstatus : OUT STD_LOGIC;
rxbardecvc0 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbardecvc1 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc00 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc01 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc10 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc11 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxdatavc00 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc01 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc10 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc11 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxeopvc00 : OUT STD_LOGIC;
rxeopvc01 : OUT STD_LOGIC;
rxeopvc10 : OUT STD_LOGIC;
rxeopvc11 : OUT STD_LOGIC;
rxerrvc0 : OUT STD_LOGIC;
rxerrvc1 : OUT STD_LOGIC;
rxfifoemptyvc0 : OUT STD_LOGIC;
rxfifoemptyvc1 : OUT STD_LOGIC;
rxfifofullvc0 : OUT STD_LOGIC;
rxfifofullvc1 : OUT STD_LOGIC;
rxfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxpolarity : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxsopvc00 : OUT STD_LOGIC;
rxsopvc01 : OUT STD_LOGIC;
rxsopvc10 : OUT STD_LOGIC;
rxsopvc11 : OUT STD_LOGIC;
rxvalidvc0 : OUT STD_LOGIC;
rxvalidvc1 : OUT STD_LOGIC;
r2cerr0ext : OUT STD_LOGIC;
serrout : OUT STD_LOGIC;
successspeednegoint : OUT STD_LOGIC;
swdnwake : OUT STD_LOGIC;
swuphotrst : OUT STD_LOGIC;
testout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
tlappintaack : OUT STD_LOGIC;
tlappmsiack : OUT STD_LOGIC;
tlcfgadd : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
tlcfgctl : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
tlcfgctlwr : OUT STD_LOGIC;
tlcfgsts : OUT STD_LOGIC_VECTOR(53 - 1 DOWNTO 0);
tlcfgstswr : OUT STD_LOGIC;
tlpmetosr : OUT STD_LOGIC;
txcompl : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txcredvc0 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txcredvc1 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txdata : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
txdatak : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdeemph : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdetectrx : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txelecidle : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txfifoemptyvc0 : OUT STD_LOGIC;
txfifoemptyvc1 : OUT STD_LOGIC;
txfifofullvc0 : OUT STD_LOGIC;
txfifofullvc1 : OUT STD_LOGIC;
txfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txmargin : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
txreadyvc0 : OUT STD_LOGIC;
txreadyvc1 : OUT STD_LOGIC;
wakeoen : OUT STD_LOGIC
);
END COMPONENT;
end hardcopyiv_pcie_hip_components;
package body HARDCOPYIV_PCIE_HIP_COMPONENTS is
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(len -1 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
end HARDCOPYIV_PCIE_HIP_COMPONENTS;
|
gpl-3.0
|
sukinull/vivado_zed_pieces
|
axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/38e122e0/hdl/blk_mem_gen_v8_2.vhd
|
24
|
19921
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
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`protect end_protected
|
gpl-3.0
|
sukinull/vivado_zed_pieces
|
axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/7820e39a/hdl/src/vhdl/lpf.vhd
|
23
|
17838
|
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0;
--use lib_cdc_v1_0.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/process/harris/hdl/pipliner_7x7.vhd
|
1
|
8678
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
library std;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.harris_package_components.all;
--use work.harris_package_variables.all;
entity pipliner_7x7 is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
HALF_WINDOW_WIDTH: integer -- The total window's width is :(HALF_WINDOW_WIDTH*2+1) : Should be an odd number
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
pixel_table_7_7 : out pixel_matrix
);
end pipliner_7x7;
architecture rtl of pipliner_7x7 is
type pixel_mask is array (0 to 2,0 to 2) of signed((PIX_WIDTH) downto 0);
type pix_out_signal is array (0 to 5) of std_logic_vector((PIX_WIDTH-1) downto 0);
--type pixel_matrix is array (0 to 6,0 to 6) of std_logic_vector((PIX_WIDTH-1) downto 0);
--type filter_matrix is array (0 to 6,0 to 6) of std_logic_vector(RESULT_LENGTH downto 0);
constant RESULT_LENGHT : integer := 64;
constant FIFO_LENGHT : integer := LINE_WIDTH_MAX-7;
constant FIFO_LENGHT_WIDTH : integer := integer(ceil(log2(real(FIFO_LENGHT))));
constant Ix_sobel_mask:pixel_mask:=((to_signed(-1,9),to_signed(0,9),to_signed(1,9)),(to_signed(-1,9),to_signed(0,9),to_signed(1,9)),(to_signed(-1,9),to_signed(0,9),to_signed(1,9)));
constant Iy_sobel_mask:pixel_mask:=((to_signed(-1,9),to_signed(-1,9),to_signed(-1,9)),(to_signed(0,9),to_signed(0,9),to_signed(0,9)),(to_signed(1,9),to_signed(1,9),to_signed(1,9)));
signal fv_signal,out_clk_dv:std_logic;
signal widthimg_temp : std_logic_vector(15 downto 0):=widthimg_i;
signal sig_wrreq:std_logic:='1';
signal sig_rdreq:std_logic:='0';
signal line_pix_out:pix_out_signal;
shared variable R:std_logic_vector((RESULT_LENGHT-1) downto 0);
shared variable Prev_R_max:std_logic_vector((RESULT_LENGHT-1) downto 0):=x"00000001DCD65000";
shared variable R_max:std_logic_vector((RESULT_LENGHT-1) downto 0):=x"00000001DCD65000";
shared variable conv_value_x,conv_value_y:signed(17 downto 0):=to_signed(0,18);
shared variable conv_value:integer:=0;
shared variable param_changing_reset:std_logic:='0';
shared variable Ixx,Ixy,Iyy:signed(31 downto 0):=to_signed(0,32);
shared variable cast_36_bits:std_logic_vector(35 downto 0);
shared variable aclr:std_logic:='0';
shared variable Ixx_vec,Iyy_vec:std_logic_vector(31 downto 0);
shared variable mult_a,mult_b,mult_2_a,mult_2_b,mult_3_a,mult_3_b:std_logic_vector(31 downto 0);
shared variable mult_s,mult_2_s,mult_3_s,comp_a,comp_a_2,comp_b,comp_b_2,add_a_1,add_b_1,add_b_2,add_s_inter,add_s :std_logic_vector(63 downto 0);
shared variable comp_s,comp_s_2:std_logic:='1';
shared variable pixel_matrix_kernel:pixel_matrix;
component scfifo
generic
( LPM_WIDTH: POSITIVE;
LPM_WIDTHU: POSITIVE;
LPM_NUMWORDS: POSITIVE;
LPM_SHOWAHEAD: STRING := "OFF";
ALLOW_RWCYCLE_WHEN_FULL: STRING := "OFF";
OVERFLOW_CHECKING: STRING:= "ON";
UNDERFLOW_CHECKING: STRING:= "ON"
);
port
(
data: in std_logic_vector(LPM_WIDTH-1 downto 0);
clock, wrreq, rdreq, aclr: in std_logic;
full, empty, almost_full, almost_empty: out std_logic;
q: out std_logic_vector(LPM_WIDTH-1 downto 0);
usedw: out std_logic_vector(LPM_WIDTHU-1 downto 0)
);
end component;
begin
sig_wrreq<='1';
G_1 : for i in 0 to 5 generate
line_fifo : scfifo
generic map (
LPM_WIDTH =>PIX_WIDTH,
LPM_WIDTHU =>FIFO_LENGHT_WIDTH,
LPM_NUMWORDS =>FIFO_LENGHT
)
port map(
data => pixel_matrix_kernel(i+1,0),
clock => clk_proc,
wrreq => in_dv,
q => line_pix_out(i),
rdreq => sig_rdreq and in_dv,
aclr =>param_changing_reset or(not(reset_n))
);
end generate;
process (clk_proc, reset_n)
variable x_pos,y_pos : unsigned(15 downto 0);
variable counter:integer:=0;
begin
fv_signal<=in_fv;
if(reset_n='0') then
x_pos := to_unsigned(0, 16);
y_pos := to_unsigned(0, 16);
out_clk_dv<='0';
elsif(rising_edge(clk_proc)) then
fv_signal<=in_fv;
out_clk_dv<='0';
if(in_fv='0') then
x_pos := to_unsigned(0, 16);y_pos := to_unsigned(0, 16);
out_clk_dv<='0';
------------------------------------------------------------------------------------------------------
elsif(in_dv='1') then
counter:=counter+1;
if(counter=(unsigned(widthimg_i)-8)) then
sig_rdreq<='1';
end if;
out_clk_dv<='1';
for o in 0 to 6 loop
for p in 0 to 5 loop
pixel_matrix_kernel(o,p):=pixel_matrix_kernel(o,p+1);
end loop;
if (o<6) then
pixel_matrix_kernel(o,6):=line_pix_out(o);
end if;
end loop;
pixel_matrix_kernel(6,6):=in_data;
----------- end of line ----------------
if(x_pos=unsigned(widthimg_i)) then
y_pos := y_pos+1;
x_pos := to_unsigned (1, 16);
else
x_pos := x_pos+1;
end if;
-----------------------------------------
----------------------- bloquage et débloquage de l'horloge -----------------------------------------------------
if (y_pos<=to_unsigned (HALF_WINDOW_WIDTH-1, 16)) then
out_clk_dv<='0';
end if;
----------------------- blocage de bords spéciale pour les deux premiers élements de bords ----------------------
if (x_pos<=to_unsigned (HALF_WINDOW_WIDTH, 16)) then
if (y_pos=to_unsigned (3, 16)) then
out_clk_dv<='0';
end if;
end if;
-----------------------------------------------------------------------------------------------------------------
else
end if;
-------------- changing widthimg_i parameter---------------------------------------------------------------------
if (unsigned(widthimg_i)=unsigned(widthimg_temp)) then
param_changing_reset:='0';
else
param_changing_reset:='1';
counter:=0;
sig_rdreq<='0';
end if;
widthimg_temp<=widthimg_i;
-----------------------------------------------------------------------------
else
end if;
end process;
out_data<= std_logic_vector(to_unsigned(conv_value, 8));
out_dv <= out_clk_dv;
out_fv <= fv_signal;
pixel_table_7_7<=pixel_matrix_kernel;
end rtl;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/component/gp_com/flow_to_com/flow_to_com.vhd
|
1
|
7785
|
-- **************************************************************************
-- FLOW IN
-- **************************************************************************
-- This component is connected to USB Driver and generate FV/DV/data as outputs
-- 26/11/2014 - creation - C.Bourrasset
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComFlow_pkg.all;
entity flow_to_com is
generic (
FLOW_SIZE : POSITIVE := 8;
DATA_HAL_SIZE : POSITIVE := 16;
FIFO_DEPTH : INTEGER := 1024;
FLOW_ID : INTEGER := 1;
PACKET_SIZE : INTEGER := 256;
FLAGS_CODES : my_array_t := InitFlagCodes
);
port (
clk_proc : in std_logic;
clk_hal : in std_logic;
rst_n : in std_logic;
in_data : in std_logic_vector(FLOW_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
enable_flow_i : in std_logic;
enable_global_i : in std_logic;
-- to arbitrer
rdreq_i : in std_logic;
data_o : out std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_o : out std_logic;
f_empty_o : out std_logic;
size_packet_o : out std_logic_vector(15 downto 0)
);
end flow_to_com;
architecture rtl of flow_to_com is
---------------------------------------------------------
-- COMPONENT DECLARATION
---------------------------------------------------------
component fv_signal_synchroniser
port (
clk : in std_logic;
rst_n : in std_logic;
fv_i : in std_logic;
signal_i : in std_logic;
signal_o : out std_logic
);
end component;
component flowto16
generic (
INPUT_SIZE : INTEGER;
FIFO_DEPTH : INTEGER := 32
);
port (
rst_n : in std_logic;
clk : in std_logic;
in_data : in std_logic_vector(FLOW_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector(15 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component com_flow_fifo_tx
generic (
FIFO_DEPTH : INTEGER := 1024;
FLOW_ID : INTEGER := 1;
PACKET_SIZE : INTEGER := 256;
HAL_WIDTH : INTEGER := 16;
FLAGS_CODES : my_array_t := InitFlagCodes
);
port (
clk_proc : in std_logic;
clk_hal : in std_logic;
rst_n : in std_logic;
data_wr_i : in std_logic;
data_i : in std_logic_vector(15 downto 0);
rdreq_i : in std_logic;
flag_wr_i : in std_logic;
flag_i : in std_logic_vector(7 downto 0);
-- fifo pkt inputs
fifo_pkt_wr_i : in std_logic;
fifo_pkt_data_i : in std_logic_vector(15 downto 0);
-- to arbitrer
data_o : out std_logic_vector(HAL_WIDTH-1 downto 0);
flow_rdy_o : out std_logic;
f_empty_o : out std_logic;
fifos_f_o : out std_logic;
size_packet_o : out std_logic_vector(15 downto 0)
);
end component;
component write_flow is
generic (
PACKET_SIZE : INTEGER := 256;
FLAGS_CODES : my_array_t := InitFlagCodes
);
port (
clk : in std_logic;
rst_n : in std_logic;
in_data : in std_logic_vector(15 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
enable_i : in std_logic;
fifo_f_i : in std_logic;
data_wr_o : out std_logic;
data_o : out std_logic_vector(15 downto 0);
flag_wr_o : out std_logic;
flag_o : out std_logic_vector(7 downto 0);
fifo_pkt_wr_o : out std_logic;
fifo_pkt_data_o : out std_logic_vector(15 downto 0)
);
end component;
---------------------------------------------------------
-- SIGNALS FOR INTERCONNECT
---------------------------------------------------------
signal fifo_f_s : std_logic := '0';
signal data_wr_s : std_logic := '0';
signal data_s : std_logic_vector(15 downto 0) := (others=>'0');
signal in_data_s : std_logic_vector(15 downto 0);
signal in_fv_s : std_logic;
signal in_dv_s : std_logic;
signal enable_flow_sync : std_logic;
signal enable_global_sync : std_logic;
signal enable_s : std_logic;
signal fifo_pkt_wr_s : std_logic;
signal fifo_pkt_data_s : std_logic_vector(15 downto 0);
-- may add CDC component for flag
signal flag_s : std_logic_vector(7 downto 0) := (others=>'0');
signal flag_wr_s : std_logic := '0';
begin
-- Adapt input flow size to 16 bits
flowto16_inst : component flowto16
generic map (
INPUT_SIZE => FLOW_SIZE,
FIFO_DEPTH => 128
)
port map (
clk => clk_proc,
rst_n => rst_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => in_data_s,
out_fv => in_fv_s,
out_dv => in_dv_s
);
ENABLE_FLOW_INST : component fv_signal_synchroniser
port map (
clk => clk_proc,
rst_n => rst_n,
fv_i => in_fv_s,
signal_i => enable_flow_i,
signal_o => enable_flow_sync
);
ENABLE_GLOBAL_INST : component fv_signal_synchroniser
port map (
clk => clk_proc,
rst_n => rst_n,
fv_i => in_fv_s,
signal_i => enable_global_i,
signal_o => enable_global_sync
);
-- port map
WRFLOW_process : component write_flow
generic map (
PACKET_SIZE => PACKET_SIZE,
FLAGS_CODES => FLAGS_CODES
)
port map (
clk => clk_proc,
rst_n => rst_n,
in_data => in_data_s,
in_fv => in_fv_s,
in_dv => in_dv_s,
enable_i => enable_s,
fifo_f_i => fifo_f_s,
data_wr_o => data_wr_s,
data_o => data_s,
flag_wr_o => flag_wr_s ,
flag_o => flag_s,
fifo_pkt_wr_o => fifo_pkt_wr_s,
fifo_pkt_data_o => fifo_pkt_data_s
);
ComFlowFifoTX_inst : component com_flow_fifo_tx
generic map (
FIFO_DEPTH => FIFO_DEPTH,
FLOW_ID => FLOW_ID,
PACKET_SIZE => PACKET_SIZE,
FLAGS_CODES => FLAGS_CODES,
HAL_WIDTH => DATA_HAL_SIZE
)
port map (
clk_proc => clk_proc,
clk_hal => clk_hal,
rst_n => rst_n and enable_s,
data_wr_i => data_wr_s,
data_i => data_s,
rdreq_i => rdreq_i,
flag_wr_i => flag_wr_s,
flag_i => flag_s,
fifo_pkt_wr_i => fifo_pkt_wr_s,
fifo_pkt_data_i => fifo_pkt_data_s,
data_o => data_o,
flow_rdy_o => flow_rdy_o,
f_empty_o => f_empty_o,
fifos_f_o => fifo_f_s,
size_packet_o => size_packet_o
);
enable_s <= enable_flow_sync and enable_global_sync;
end rtl;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/component/gp_fifo/hdl/tb/tb_gp_fifo.vhd
|
1
|
3389
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library ALTERA_MF;
use ALTERA_MF.all;
entity tb_fifo is
end tb_fifo;
architecture sim of tb_fifo is
---------------------------------------------------------
-- CONSTANTS
---------------------------------------------------------
constant FIFO_DEPTH_CONST : positive:=4;
constant DATA_WIDTH_CONST : positive:=8;
---------------------------------------------------------
-- SIGNALS
---------------------------------------------------------
signal clk_s : std_logic;
signal reset_n_s : std_logic;
signal data_wr_s : std_logic;
signal data_in_s : std_logic_vector(DATA_WIDTH_CONST-1 downto 0);
signal full_s : std_logic;
signal data_rd_s : std_logic;
signal data_ou_s : std_logic_vector(DATA_WIDTH_CONST-1 downto 0);
signal empty_s : std_logic;
---------------------------------------------------------
-- C.U.T
---------------------------------------------------------
component gp_fifo
generic (
DATA_WIDTH : positive;
FIFO_DEPTH : positive
);
port (
clk : in std_logic;
reset_n : in std_logic;
data_wr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
full : out std_logic;
data_rd : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
empty : out std_logic
);
end component;
begin
---------------------------------------------------------
-- C.U.T INSTANSTATION
---------------------------------------------------------
gp_fifo_inst : gp_fifo
generic map(
DATA_WIDTH => DATA_WIDTH_CONST,
FIFO_DEPTH => FIFO_DEPTH_CONST
)
port map(
clk => clk_s,
reset_n => reset_n_s,
data_wr => data_wr_s,
data_in => data_in_s,
full => full_s,
data_rd => data_rd_s,
data_out => data_ou_s,
empty => empty_s
);
---------------------------------------------------------
-- STIMULUS
---------------------------------------------------------
-- Clock
clk_stim : process
begin
clk_s <= '1';
wait for 20 ns;
clk_s <= '0';
wait for 20 ns;
end process;
-- Initial Reset
init_reset : process
begin
reset_n_s <= '0' ;
wait for 50 ns ;
reset_n_s <= '1' ;
wait for 340 ns;
end process;
-- Write in FIFO stimulus
dw_stim : process
begin
data_wr_s <= '0';
wait for 60 ns;
data_wr_s <= '1';
wait for 40 ns;
data_wr_s <= '0';
wait for 20 ns;
data_wr_s <= '1';
wait for 60 ns;
data_wr_s <= '0';
wait for 20 ns;
data_wr_s <= '1';
wait for 40 ns;
data_wr_s <= '0';
wait for 60 ns;
end process;
-- Read From FIFO simulus
rd_stim : process
begin
data_rd_s <= '0';
wait for 160 ns;
data_rd_s <= '1';
wait for 40 ns;
data_rd_s <= '0';
wait for 20 ns;
data_rd_s <= '1';
wait for 60 ns;
data_rd_s <= '0';
wait for 20 ns;
data_rd_s <= '1';
wait for 40 ns;
end process;
-- In data stimulus
data_stim : process
variable i : integer := 0;
begin
for i in 1 to 100 loop
data_in_s <= std_logic_vector(to_unsigned(i,DATA_WIDTH_CONST));
wait for 20 ns;
end loop;
end process;
end architecture;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/toolchain/caph/hdl/caph_lib/caph.vhd
|
1
|
13658
|
-----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package core is
function cond(e1: boolean; e2: signed; e3: signed) return signed;
function cond(e1: boolean; e2: unsigned; e3: unsigned) return unsigned;
function cond(e1: boolean; e2: std_logic_vector; e3: std_logic_vector) return std_logic_vector;
function eq(e1: signed; e2: signed) return unsigned;
function eq(e1: unsigned; e2: unsigned) return unsigned;
function mul(e1: signed; e2: signed) return signed;
function mul(e1: unsigned; e2: unsigned) return unsigned;
function to_std_logic_vector(e: unsigned; s: natural) return std_logic_vector;
function to_std_logic_vector(e: signed; s: natural) return std_logic_vector;
function to_std_logic_vector(e: boolean; s: natural) return std_logic_vector;
function from_std_logic_vector(e: std_logic_vector; s: natural) return unsigned;
function from_std_logic_vector(e: std_logic_vector; s: natural) return signed;
function from_std_logic_vector(e: std_logic_vector; s: natural) return boolean;
function from_std_logic_vector(e: std_logic_vector; s: natural) return std_logic_vector;
function to_bool(e: unsigned) return boolean;
function to_bool(e: signed) return boolean;
function to_bool(e: std_logic_vector) return boolean;
function conv_unsigned(e: unsigned; s: natural) return unsigned;
function conv_unsigned(e: signed; s: natural) return unsigned;
function conv_unsigned(e: boolean; s: natural) return unsigned;
function conv_unsigned(e: integer; s: natural) return unsigned;
function conv_signed(e: signed; s: natural) return signed;
function conv_signed(e: unsigned; s: natural) return signed;
function conv_signed(e: boolean; s: natural) return signed;
function conv_signed(e: integer; s: natural) return signed;
function to_integer(e: integer) return integer;
function to_string(v : std_logic_vector) return string; -- for debug only
procedure dump_slv(name: string; v: std_logic_vector); -- for debug only
component stream_in is
generic ( filename: string := "input.bin"; size: integer := 10; period: integer := 2; blanking: boolean := false );
port ( full : in std_logic;
dout : out std_logic_vector(size-1 downto 0);
wr : out std_logic; -- write (push) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end component;
component stream_out is
generic ( filename: string := "vhdl_result.dat"; size: integer := 10);
port ( empty : in std_logic;
din : in std_logic_vector(size-1 downto 0);
rd : out std_logic; -- read (pop) signal
clk : in std_logic;
rst : in std_logic
);
end component;
component port_in is
generic ( filename: string := ""; size: integer := 10; ival: bit_vector);
port ( full : in std_logic;
dout : out std_logic_vector(size-1 downto 0);
wr : out std_logic; -- write (push) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end component;
component port_out is
generic ( filename: string := "result.bin"; size: integer := 10 );
port ( empty : in std_logic;
din : in std_logic_vector(size-1 downto 0);
rd : out std_logic; -- read (pop) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end component;
--~
--~ component split2 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split3 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split4 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic;
--~ d4_f : in std_logic;
--~ d4 : out std_logic_vector(size-1 downto 0);
--~ d4_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split5 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic;
--~ d4_f : in std_logic;
--~ d4 : out std_logic_vector(size-1 downto 0);
--~ d4_wr : out std_logic;
--~ d5_f : in std_logic;
--~ d5 : out std_logic_vector(size-1 downto 0);
--~ d5_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split6 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic;
--~ d4_f : in std_logic;
--~ d4 : out std_logic_vector(size-1 downto 0);
--~ d4_wr : out std_logic;
--~ d5_f : in std_logic;
--~ d5 : out std_logic_vector(size-1 downto 0);
--~ d5_wr : out std_logic;
--~ d6_f : in std_logic;
--~ d6 : out std_logic_vector(size-1 downto 0);
--~ d6_wr : out std_logic
--~ );
--~ end component;
--component decoder is
-- generic ( size: integer := 8 )
-- port (
-- sel: in integer;
-- outp: std_logic_vector ( size-1 downto 0)
-- );
--end component;
end core;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- use STD.textio.all; -- FOR DEBUG ONLY
package body core is
function cond(e1: boolean; e2: signed; e3: signed) return signed is
begin
if e1 then return e2; else return e3; end if;
end;
function cond(e1: boolean; e2: unsigned; e3: unsigned) return unsigned is
begin
if e1 then return e2; else return e3; end if;
end;
function cond(e1: boolean; e2: std_logic_vector; e3: std_logic_vector) return std_logic_vector is
begin
if e1 then return e2; else return e3; end if;
end;
function eq(e1: signed; e2: signed) return unsigned is
begin
if ( e1 = e2 ) then
return "1";
else
return "0";
end if;
end;
function eq(e1: unsigned; e2: unsigned) return unsigned is
begin
if ( e1 = e2 ) then
return "1";
else
return "0";
end if;
end;
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function mul (e1: signed; e2: signed) return signed is
constant length: INTEGER := maximum(e1'length, e2'length);
begin
return resize(e1*e2, length);
end;
function mul (e1: unsigned; e2: unsigned) return unsigned is
constant length: INTEGER := maximum(e1'length, e2'length);
begin
return resize(e1*e2, length);
end;
function to_std_logic_vector(e: unsigned; s:natural) return std_logic_vector is
begin
return STD_LOGIC_VECTOR(resize(e,s));
end;
function to_std_logic_vector(e: signed; s:natural) return std_logic_vector is
begin
return STD_LOGIC_VECTOR(resize(e,s));
end;
function to_std_logic_vector(e: boolean; s:natural) return std_logic_vector is
begin
if e then
return STD_LOGIC_VECTOR(TO_UNSIGNED(0,s-1)) & "1";
else
return STD_LOGIC_VECTOR(TO_UNSIGNED(0,s-1)) & "0";
end if;
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return unsigned is
begin
-- return UNSIGNED(e(s-1 downto 0));
-- return UNSIGNED(e(e'high downto e'high-s+1));
return UNSIGNED(e(s-1 downto 0)); -- Changed in v2.6.2: in variants, fields are RIGHT justified
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return signed is
begin
-- return SIGNED(e(s-1 downto 0));
-- return SIGNED(e(e'high downto e'high-s+1));
return SIGNED(e(s-1 downto 0)); -- Changed in v2.6.2: in variants, fields are RIGHT justified
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return boolean is
begin
-- if e(e'high downto e'high) = "1" then
if e(0 downto 0) = "1" then -- Changed in v2.6.2: in variants, fields are RIGHT justified
return true;
else
return false;
end if;
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return std_logic_vector is
begin
return (e(s-1 downto 0)); -- Changed in v2.6.2: in variants, fields are RIGHT justified
-- return e(e'high downto e'high-s+1);
end;
function to_bool(e: unsigned) return boolean is
begin
if e = (e'range=>'0') then return false; else return true; end if;
end;
function to_bool(e: signed) return boolean is
begin
if e = (e'range=>'0') then return false; else return true; end if;
end;
function to_bool(e: std_logic_vector) return boolean is
begin
if e = (e'range=>'0') then return false; else return true; end if;
end;
function conv_unsigned(e: unsigned; s: natural) return unsigned is
begin
return resize(e, s);
end;
function conv_unsigned(e: signed; s: natural) return unsigned is
begin
return resize(unsigned(e), s);
end;
function conv_unsigned(e: boolean; s: natural) return unsigned is
begin
if ( e ) then return to_unsigned(1,s); else return to_unsigned(0,s); end if;
end;
function conv_unsigned(e: integer; s: natural) return unsigned is
begin
return to_unsigned(e,s);
end;
function conv_signed(e: signed; s: natural) return signed is
begin
return resize(e, s);
end;
function conv_signed(e: unsigned; s: natural) return signed is
begin
return resize(signed('0' & e), s);
end;
function conv_signed(e: boolean; s: natural) return signed is
begin
if ( e ) then return to_signed(1,s); else return to_signed(0,s); end if;
end;
function conv_signed(e: integer; s: natural) return signed is
begin
return to_signed(e,s);
end;
function to_integer(e: integer) return integer is
begin
return e;
end;
-- Debug aux fns
function to_string(v : std_logic_vector) return string is
variable s : string(1 to v'length) := (others => 'x');
variable c : string(1 to 3);
variable j : integer := 1;
begin
for i in v'high downto v'low loop
c := std_logic'image(v(i));
s(j to j) := c(2 to 2); -- c is a 3 character string (with quotes) !
j := j+1;
end loop;
return s;
end to_string;
procedure dump_slv(name: string; v: std_logic_vector) is
begin
report name & "[" & integer'image(v'high) & ":" & integer'image(v'low) & "]=" & to_string(v);
end;
end package body core;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd
|
4
|
10499
|
--**********************************************************************************************
-- JTAG "Flash" programmer for AVR Core(cp2 Clock Domain)
-- Version 0.5
-- Modified 20.06.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.JTAGPack.all;
use WORK.AVRuCPackage.all;
entity OCDProgcp2 is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- From/To TCK clock domain("Flash" programmer)
FlEEPrgAdr : in std_logic_vector(15 downto 0);
FlPrgRdData : out std_logic_vector(15 downto 0);
EEPrgRdData : out std_logic_vector(7 downto 0);
FlEEPrgWrData : in std_logic_vector(15 downto 0);
ChipEraseStart : in std_logic;
ChipEraseDone : out std_logic;
ProgEnable : in std_logic;
FlWrMStart : in std_logic; -- Multiple
FlWrSStart : in std_logic; -- Single
FlRdMStart : in std_logic; -- Multiple
FlRdSStart : in std_logic; -- Single
EEWrStart : in std_logic;
EERdStart : in std_logic;
TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic
);
end OCDProgcp2;
architecture RTL of OCDProgcp2 is
-- **********************************************************************************
-- *************************** Programmer part *********************************************
-- **********************************************************************************
-- Edge detectors
signal TAPCtrlTLRDel : std_logic; -- TAP Run-Test/Idle
-- Chip Erase Start edge detector
signal ChipEraseStartDel : std_logic;
-- Flash Write Start(using Virtual Flash Page Load Register) edge detector
signal FlWrMStartDel : std_logic;
-- Flash Write Start(using Load Data Low(2d)/Load Data High(2e)) edge detector
signal FlWrSStartDel : std_logic;
-- Flash Read Start(using Virtual Flash Page Read Register) edge detector
signal FlRdMStartDel : std_logic;
-- Flash Read Start(using Load Data Low and High Byte(3d)) edge detector
signal FlRdSStartDel : std_logic;
-- "Flash" programmer state machines
signal FlWrCnt : std_logic_vector(1 downto 0) ; -- Write
signal FlRdCnt : std_logic_vector(1 downto 0) ; -- Read (Low andHigh bytes)
signal FlRd_St : std_logic; -- "Flash" read(Latch data)
-- "Flash" address and data registers
signal FlashPrgAdrRg : std_logic_vector(15 downto 0); -- Address(Write/Read)
signal FlashPrgDataRg : std_logic_vector(15 downto 0); -- Data(for Write)
-- Output copies
signal pm_h_we_Int : std_logic;
signal pm_l_we_Int : std_logic;
-- Chip erase
signal ChipErase_St : std_logic;
-- "EEPROM" support
-- Edge detectors
signal EEWrStartDel : std_logic;
signal EERdStartDel : std_logic;
-- EEPROM address and data registers
signal EEPrgAdrRg : std_logic_vector(EEAdr'range); -- Address(Write/Read)
signal EEPrgDataRg : std_logic_vector(EEWrData'range); -- Data(for Write)
signal EEWr_Int : std_logic;
-- EEPROM programmer state machines
signal EEWrCnt : std_logic_vector(1 downto 0) ; -- Write
signal EERdCnt : std_logic_vector(1 downto 0) ; -- Read
signal EERd_St : std_logic;
begin
-- ***************************** Programmer part ********************************
FlashWriteCntAndCtrl:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge)
-- Edge detectors
TAPCtrlTLRDel <= TAPCtrlTLR;
FlWrMStartDel <= FlWrMStart;
FlWrSStartDel <= FlWrSStart;
-- Delay counter
if(TAPCtrlTLR='1') then -- Reset counter
FlWrCnt <= (others => '0');
elsif((FlWrMStart='0' and FlWrMStartDel='1')or
(FlWrSStart='0' and FlWrSStartDel='1')) then
FlWrCnt <= "01";
elsif(FlWrCnt/="00") then
FlWrCnt <= FlWrCnt + 1;
end if;
-- Control
if(TAPCtrlTLR='1') then -- Reset control signals
pm_h_we_Int <= '0';
pm_l_we_Int <= '0';
else
case pm_h_we_Int is
when '0' =>
if((ChipEraseStart='1' and ChipEraseStartDel='0') or FlWrCnt="11") then
pm_h_we_Int <= '1';
end if;
when '1' =>
if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then
pm_h_we_Int <= '0';
end if;
when others => null;
end case;
case pm_l_we_Int is
when '0' =>
if((ChipEraseStart='1' and ChipEraseStartDel='0') or FlWrCnt="11") then
pm_l_we_Int <= '1';
end if;
when '1' =>
if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then
pm_l_we_Int <= '0';
end if;
when others => null;
end case;
end if;
-- Address (for Erase,Write and Read!!!)
if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase -> Clear address counter
FlashPrgAdrRg <= (others => '0');
elsif(ChipErase_St='1') then -- Chip erase -> increment aaddress
FlashPrgAdrRg <= FlashPrgAdrRg + 1;
elsif(FlWrCnt="11" or FlRdCnt="11") then -- Normal mode
FlashPrgAdrRg <= FlEEPrgAdr;
end if;
-- Data
if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase
FlashPrgDataRg <= (others => '1');
elsif(FlWrCnt="11") then -- Write to flash
FlashPrgDataRg <= FlEEPrgWrData;
end if;
-- EEPROM Address (for Erase,Write and Read!!!)
if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase -> Clear address counter
EEPrgAdrRg <= (others => '0');
elsif(ChipErase_St='1') then -- Chip erase -> increment aaddress
EEPrgAdrRg <= EEPrgAdrRg + 1;
elsif(EEWrCnt="11" or EERdCnt="11") then -- Normal mode
EEPrgAdrRg <= FlEEPrgAdr(EEPrgAdrRg'range);
end if;
-- EEPROM Data
if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase
EEPrgDataRg <= (others => '1');
elsif(EEWrCnt="11") then -- Write to EEPROM
EEPrgDataRg <= FlEEPrgWrData(EEPrgDataRg'range);
end if;
-- EEPROM Write
case EEWr_Int is
when '0' =>
if((ChipEraseStart='1' and ChipEraseStartDel='0') or EEWrCnt="11") then
EEWr_Int <= '1';
end if;
when '1' =>
if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then
EEWr_Int <= '0';
end if;
when others => EEWr_Int <= '0';
end case;
-- EEPROM Read state
if(EERdCnt="11") then
EERd_St <= '1';
else
EERd_St <= '0';
end if;
end if;
end process;
-- "Flash" write enables
pm_l_we <= pm_l_we_Int;
pm_h_we <= pm_h_we_Int;
-- "Flash" data inputs
pm_din <= FlashPrgDataRg;
-- EEPROM
EEAdr <= EEPrgAdrRg;
EEWrData <= EEPrgDataRg;
EEWr <= EEWr_Int;
EEPrgSel <= ProgEnable; -- !!!TBD!!! (Add EESAVE)
-- Flash read
FlashReadCntAndCtrl:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge)
-- Edge detectors
FlRdMStartDel <= FlRdMStart;
FlRdSStartDel <= FlRdSStart;
-- EEPROM edge detectors
EEWrStartDel <= EEWrStart;
EERdStartDel <= EERdStart;
-- Delay counter (for read)
if(TAPCtrlTLR='1') then -- Reset counter
FlRdCnt <= (others => '0');
elsif((FlRdMStart='0' and FlRdMStartDel='1')or
(FlRdSStart='0' and FlRdSStartDel='1')) then
FlRdCnt <= "01";
elsif(FlRdCnt/="00") then
FlRdCnt <= FlRdCnt + 1;
end if;
if(FlRdCnt="11") then
FlRd_St <= '1';
else
FlRd_St <= '0';
end if;
if(FlRd_St='1') then -- Latch read data
FlPrgRdData <= pm_dout;
end if;
-- EEPROM Read delay counter
if(TAPCtrlTLR='1') then -- Reset counter
EERdCnt <= (others => '0');
elsif(EERdStart='0' and EERdStartDel='1') then -- Falling edge
EERdCnt <= "01";
elsif(EERdCnt/="00") then
EERdCnt <= EERdCnt + 1;
end if;
-- EEPROM Write delay counter
if(TAPCtrlTLR='1') then -- Reset counter
EEWrCnt <= (others => '0');
elsif(EEWrStart='0' and EEWrStartDel='1') then -- Falling edge
EEWrCnt <= "01";
elsif(EEWrCnt/="00") then
EEWrCnt <= EEWrCnt + 1;
end if;
-- EEPROM Read latch
if(EERd_St='1') then
EEPrgRdData <= EERdData;
end if;
end if;
end process;
-- Chip Erase
ChipEraseState:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge)
ChipEraseStartDel <= ChipEraseStart; -- Edge detector
if (TAPCtrlTLR='1') then -- Reset
ChipErase_St <= '0';
else
case ChipErase_St is
when '0' =>
if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase
ChipErase_St <= '1';
end if;
when '1' =>
if (FlashPrgAdrRg=C_MaxEraseAdr) then
ChipErase_St <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- !!!TBD!!!
ChipEraseDone <= not ChipErase_St;
-- *************************** End of programmer part *******************************
pm_adr <= FlashPrgAdrRg when (ProgEnable='1') else -- Programming Mode
PC; -- Normal Operations
end RTL;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/io/eth_marvell_88e1111/hdl/ICMP/ff_icmp.vhd
|
1
|
7359
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: ff_icmp.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ff_icmp IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
END ff_icmp;
ARCHITECTURE SYN OF ff_icmp IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(7 DOWNTO 0);
rdempty <= sub_wire2;
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 256,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 8,
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "256"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ff_icmp.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ff_icmp.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ff_icmp.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ff_icmp.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ff_icmp_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-3.0
|
DreamIP/GPStudio
|
support/component/neighExtractor/cnn_types.vhd
|
1
|
239
|
library ieee;
use ieee.std_logic_1164.all;
package cnn_types is
constant PIXEL_CONST : integer := 8;
type pixel_array is array ( integer range <> ) of std_logic_vector (PIXEL_CONST-1 downto 0);
end cnn_types;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/T80/T80_Reg.vhd
|
2
|
5074
|
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0);
DOR : out std_logic_vector(127 downto 0);
DIRSet : in std_logic;
DIR : in std_logic_vector(127 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if rising_edge(Clk) then
if DIRSet = '1' then
RegsL(0) <= DIR( 7 downto 0);
RegsH(0) <= DIR( 15 downto 8);
RegsL(1) <= DIR( 23 downto 16);
RegsH(1) <= DIR( 31 downto 24);
RegsL(2) <= DIR( 39 downto 32);
RegsH(2) <= DIR( 47 downto 40);
RegsL(3) <= DIR( 55 downto 48);
RegsH(3) <= DIR( 63 downto 56);
RegsL(4) <= DIR( 71 downto 64);
RegsH(4) <= DIR( 79 downto 72);
RegsL(5) <= DIR( 87 downto 80);
RegsH(5) <= DIR( 95 downto 88);
RegsL(6) <= DIR(103 downto 96);
RegsH(6) <= DIR(111 downto 104);
RegsL(7) <= DIR(119 downto 112);
RegsH(7) <= DIR(127 downto 120);
elsif CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
DOR <= RegsH(7) & RegsL(7) & RegsH(6) & RegsL(6) & RegsH(5) & RegsL(5) & RegsH(4) & RegsL(4) & RegsH(3) & RegsL(3) & RegsH(2) & RegsL(2) & RegsH(1) & RegsL(1) & RegsH(0) & RegsL(0);
end;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/process/dynroiBinMask/hdl/dynroiBinMask.vhd
|
1
|
4352
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynroiBinMask is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dynroiBinMask;
architecture rtl of dynroiBinMask is
component dynroiBinMask_process
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
status_reg_bypass_bit : in std_logic;
in_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component dynroiBinMask_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
status_reg_bypass_bit : out std_logic;
in_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal status_reg_bypass_bit : std_logic;
signal in_size_reg_in_w_reg : std_logic_vector (11 downto 0);
signal in_size_reg_in_h_reg : std_logic_vector (11 downto 0);
begin
dynroiBinMask_process_inst : dynroiBinMask_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
status_reg_bypass_bit => status_reg_bypass_bit,
in_size_reg_in_w_reg => in_size_reg_in_w_reg,
in_size_reg_in_h_reg => in_size_reg_in_h_reg,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
dynroiBinMask_slave_inst : dynroiBinMask_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
status_reg_bypass_bit => status_reg_bypass_bit,
in_size_reg_in_w_reg => in_size_reg_in_w_reg,
in_size_reg_in_h_reg => in_size_reg_in_h_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/process/conv/hdl/conv.vhd
|
1
|
6528
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity conv is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end conv;
architecture rtl of conv is
component conv_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
w00_reg_m00 : in std_logic_vector(7 downto 0);
w01_reg_m01 : in std_logic_vector(7 downto 0);
w02_reg_m02 : in std_logic_vector(7 downto 0);
w10_reg_m10 : in std_logic_vector(7 downto 0);
w11_reg_m11 : in std_logic_vector(7 downto 0);
w12_reg_m12 : in std_logic_vector(7 downto 0);
w20_reg_m20 : in std_logic_vector(7 downto 0);
w21_reg_m21 : in std_logic_vector(7 downto 0);
w22_reg_m22 : in std_logic_vector(7 downto 0);
norm_reg_norm : in std_logic_vector(3 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component conv_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
w00_reg_m00 : out std_logic_vector(7 downto 0);
w01_reg_m01 : out std_logic_vector(7 downto 0);
w02_reg_m02 : out std_logic_vector(7 downto 0);
w10_reg_m10 : out std_logic_vector(7 downto 0);
w11_reg_m11 : out std_logic_vector(7 downto 0);
w12_reg_m12 : out std_logic_vector(7 downto 0);
w20_reg_m20 : out std_logic_vector(7 downto 0);
w21_reg_m21 : out std_logic_vector(7 downto 0);
w22_reg_m22 : out std_logic_vector(7 downto 0);
norm_reg_norm : out std_logic_vector(3 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_width : std_logic_vector (15 downto 0);
signal w00_reg_m00 : std_logic_vector (7 downto 0);
signal w01_reg_m01 : std_logic_vector (7 downto 0);
signal w02_reg_m02 : std_logic_vector (7 downto 0);
signal w10_reg_m10 : std_logic_vector (7 downto 0);
signal w11_reg_m11 : std_logic_vector (7 downto 0);
signal w12_reg_m12 : std_logic_vector (7 downto 0);
signal w20_reg_m20 : std_logic_vector (7 downto 0);
signal w21_reg_m21 : std_logic_vector (7 downto 0);
signal w22_reg_m22 : std_logic_vector (7 downto 0);
signal norm_reg_norm : std_logic_vector (3 downto 0);
begin
conv_process_inst : conv_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
w00_reg_m00 => w00_reg_m00,
w01_reg_m01 => w01_reg_m01,
w02_reg_m02 => w02_reg_m02,
w10_reg_m10 => w10_reg_m10,
w11_reg_m11 => w11_reg_m11,
w12_reg_m12 => w12_reg_m12,
w20_reg_m20 => w20_reg_m20,
w21_reg_m21 => w21_reg_m21,
w22_reg_m22 => w22_reg_m22,
norm_reg_norm => norm_reg_norm,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
conv_slave_inst : conv_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
w00_reg_m00 => w00_reg_m00,
w01_reg_m01 => w01_reg_m01,
w02_reg_m02 => w02_reg_m02,
w10_reg_m10 => w10_reg_m10,
w11_reg_m11 => w11_reg_m11,
w12_reg_m12 => w12_reg_m12,
w20_reg_m20 => w20_reg_m20,
w21_reg_m21 => w21_reg_m21,
w22_reg_m22 => w22_reg_m22,
norm_reg_norm => norm_reg_norm,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_generator_v12_0/hdl/ramfifo/wr_handshaking_flags.vhd
|
6
|
12657
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7632)
`protect data_block
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|
gpl-3.0
|
JuanMarcosRamirez/WeightedMedianDisenoLogico
|
misc/FPGA/otros/auditoría_imagen_16x16/window_3x3_x.vhd
|
1
|
10204
|
--------------------------------------------------------------------------
--
-- Autor: Jorge Márquez
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity window_3x3 is
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w11 : out std_logic_vector(vwidth -1 downto 0);
w12 : out std_logic_vector(vwidth -1 downto 0);
w13 : out std_logic_vector(vwidth -1 downto 0);
w21 : out std_logic_vector(vwidth -1 downto 0);
w22 : out std_logic_vector(vwidth -1 downto 0);
w23 : out std_logic_vector(vwidth -1 downto 0);
w31 : out std_logic_vector(vwidth -1 downto 0);
w32 : out std_logic_vector(vwidth -1 downto 0);
w33 : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic:='0'
);
end window_3x3;
architecture window_3x3 of window_3x3 is
component fifo_16x8x
port (
din : IN std_logic_VECTOR(7 downto 0);
wr_en : IN std_logic;
wr_clk : IN std_logic;
rd_en : IN std_logic;
rd_clk : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic_VECTOR(7 downto 0);
full : OUT std_logic;
empty : OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(3 downto 0));
end component;
signal a00 : std_logic_vector(vwidth-1 downto 0);
signal a11 : std_logic_vector(vwidth-1 downto 0);
signal a12 : std_logic_vector(vwidth-1 downto 0);
signal a13 : std_logic_vector(vwidth-1 downto 0);
signal a21 : std_logic_vector(vwidth-1 downto 0);
signal a22 : std_logic_vector(vwidth-1 downto 0);
signal a23 : std_logic_vector(vwidth-1 downto 0);
signal a31 : std_logic_vector(vwidth-1 downto 0);
signal a32 : std_logic_vector(vwidth-1 downto 0);
signal a33 : std_logic_vector(vwidth-1 downto 0);
--fifoa signals
signal clear : std_logic;
signal wrreqa : std_logic:='1';
signal rdreqa : std_logic:='0';
signal ofulla : std_logic;
signal oemptya : std_logic;
signal ofifoa : std_logic_vector(vwidth-1 downto 0);
signal ousedwa : std_logic_VECTOR(3 downto 0);
--fifob signals
signal wrreqb : std_logic:='0';
signal rdreqb : std_logic:='0';
signal ofullb : std_logic;
signal oemptyb : std_logic;
signal ofifob : std_logic_vector(vwidth-1 downto 0);
signal ousedwb : std_logic_VECTOR(3 downto 0);
signal dwrreqb: std_logic:='0';
-- signals for DV coordination
signal dddddddddDV: std_logic:='0';--:='0'; --9ds
signal ddddddddDV: std_logic:='0'; --8ds -- Señales
signal dddddddDV: std_logic :='0'; --04/06/08 7 ds funciona al pelo! -- Señales
signal ddddddDV: std_logic:='0';
signal dddddDV: std_logic:='0';
signal ddddDV: std_logic:='0';
signal dddDV: std_logic:='0';
signal ddDV: std_logic:='0';
signal dDV: std_logic:='0';
signal ousedwa_temp: integer:=0;
signal ousedwb_temp: integer:=0;
begin
fifoa: fifo_16x8x
port map (
din => a13,
wr_en => wrreqa,
wr_clk => Clk,
rd_en => rdreqa,
rd_clk => Clk,
rst => clear,
dout => ofifoa,
full => ofulla,
empty => oemptya,
wr_data_count => ousedwa
);
fifob: fifo_16x8x
port map (
din => a23,
wr_en => wrreqb,
wr_clk => Clk,
rd_en => rdreqb,
rd_clk => Clk,
rst => clear,
dout => ofifob,
full => ofullb,
empty => oemptyb,
wr_data_count => ousedwb
);
clear <= not(RSTn);
clock: process(Clk,RSTn)
begin
if RSTn = '0' then
a11 <= (others=>'0');
a12 <= (others=>'0');
a13 <= (others=>'0');
a21 <= (others=>'0');
a22 <= (others=>'0');
a23 <= (others=>'0');
a31 <= (others=>'0');
a32 <= (others=>'0');
a33 <= (others=>'0');
w11 <= (others=>'0');
w12 <= (others=>'0');
w13 <= (others=>'0');
w21 <= (others=>'0');
w22 <= (others=>'0');
w23 <= (others=>'0');
w31 <= (others=>'0');
w32 <= (others=>'0');
w33 <= (others=>'0');
wrreqa <= '0';
wrreqb <= '0';
-- dddddddddDV <= '0'; --9 ds
-- ddddddddDV <= '0'; -- 8 ds
-- dddddddDV <= '0'; -- 7 ds
ddddddDV <= '0';
dddddDV <= '0';
ddddDV <= '0';
dddDV <= '0';
ddDV <= '0';
dDV <= '0';
DV <= '0';
elsif rising_edge(Clk) then
a00 <= D;
a11 <= a00;
w11 <= a00;
w12 <= a11;
a12 <= a11;
w13 <= a12;
a13 <= a12;
w21 <= ofifoa;
a21 <= ofifoa;
w22 <= a21;
a22 <= a21;
w23 <= a22;
a23 <= a22;
w31 <= ofifob;
a31 <= ofifob;
w32 <= a31;
a32 <= a31;
w33 <= a32;
a33 <= a32;
wrreqa <= '1';
wrreqb <= dwrreqb;
ddddddDV <= dddddddDV; --04/06/08
dddddDV <= ddddddDV;
ddddDV <= dddddDV;
dddDV <= ddddDV;
ddDV <= dddDV;
dDV <= ddDV;
DV <= dDV;
end if;
end process;
req: process(Clk)
begin
if rising_edge(Clk) then
if ousedwa = "1010" then
rdreqa <= '1';
dwrreqb <= '1';
end if;
if ousedwb = "1010" then
rdreqb <= '1';
dddddddDV <= '1'; --04/06/08 ds
end if;
end if;
end process;
end window_3x3;
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/builtin/fifo_generator_v12_0_comps_builtin.vhd
|
6
|
32006
|
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x32/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_defaults.vhd
|
8
|
32589
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22384)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/builtin/builtin_prim_v6.vhd
|
6
|
37128
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25744)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/ramfifo/rd_pe_sshft.vhd
|
6
|
17676
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11344)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/axi_bram_ctrl_16b/blk_mem_gen_v8_2/hdl/blk_mem_input_block.vhd
|
8
|
45404
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 31872)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/blk_mem_gen_v8_2/hdl/blk_mem_input_block.vhd
|
8
|
45404
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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aU3uU6qaXWsFaGyQrek=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 31872)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/builtin/delay.vhd
|
6
|
10088
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5728)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_pkg.vhd
|
8
|
127668
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 92768)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
dskntIndustry/Hardware
|
hdl_library/CommonFunctions/MathHelpers.vhd
|
1
|
3248
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package MathHelpers is
function log2(A : integer) return integer;
function isPow2(A : integer) return boolean;
function max(A, B : integer) return integer;
function max(A, B : std_logic_vector) return std_logic_vector;
function min(A, B : integer) return integer;
function min(A, B : std_logic_vector) return std_logic_vector;
function abs_std_logic_vector(arg: std_logic_vector) return std_logic_vector;
end package MathHelpers;
package body MathHelpers is
function log2(A : integer) return integer is
begin
for I in 1 to 30 loop
if (2**I >= A) then
return(I);
end if;
end loop;
return(30);
end function log2;
-------------------------------------------------------------------------------
-- return true if an integer nuber is a power of 2
function isPow2(x : integer) return boolean is
begin
-- Works for up to 32 bit integers
if
x = 1 or x = 2 or x = 4 or x = 8 or x = 16 or x = 32 or
x = 64 or x = 128 or x = 256 or x = 512 or x = 1024 or
x = 2048 or x = 4096 or x = 8192 or x = 16384 or
x = 32768 or x = 65536 or x = 131072 or x = 262144 or
x = 524288 or x = 1048576 or x = 2097152 or
x = 4194304 or x = 8388608 or x = 16777216 or
x = 33554432 or x = 67108864 or x = 134217728 or
x = 268435456 or x = 536870912 or x = 1073741824
then
report "Argument is a power of 2" severity NOTE;
return true;
else
report "Argument is not a power of 2" severity NOTE;
return false;
end if;
end function isPow2;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function max(A, B : integer) return integer is
begin
if B > A then
return B;
end if;
return A;
end function max;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function max(A, B : std_logic_vector) return std_logic_vector is
begin
if B > A then
return B;
end if;
return A;
end function max;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function min(A, B : integer) return integer is
begin
if B > A then
return A;
end if;
return B;
end function min;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function min(A, B : std_logic_vector) return std_logic_vector is
begin
if B > A then
return A;
end if;
return B;
end function min;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function abs_std_logic_vector(arg: std_logic_vector) return std_logic_vector is
variable Result: signed(arg'length-1 downto 0);
begin
Result := signed(arg);
if Result(Result'left) = '1' then
Result := -Result;
end if;
return std_logic_vector(Result);
end function;
end package body MathHelpers;
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x32/synth/fifo_async_103x32.vhd
|
1
|
38595
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_async_103x32 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(102 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(102 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END fifo_async_103x32;
ARCHITECTURE fifo_async_103x32_arch OF fifo_async_103x32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_async_103x32_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(102 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(102 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_async_103x32_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.3.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_async_103x32_arch : ARCHITECTURE IS "fifo_async_103x32,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_async_103x32_arch: ARCHITECTURE IS "fifo_async_103x32,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=5,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=103,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=103,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=16,C_PROG_FULL_THRESH_NEGATE_VAL=15,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=5,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=5,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 5,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 103,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 103,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 16,
C_PROG_FULL_THRESH_NEGATE_VAL => 15,
C_PROG_FULL_TYPE => 1,
C_RD_DATA_COUNT_WIDTH => 5,
C_RD_DEPTH => 32,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 5,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 5,
C_WR_DEPTH => 32,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 5,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
prog_full => prog_full,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_async_103x32_arch;
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/common/synchronizer_ff.vhd
|
6
|
8637
|
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|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_generator_v12_0/hdl/common/synchronizer_ff.vhd
|
6
|
8637
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4656)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/builtin/builtin_extdepth_v6.vhd
|
6
|
50137
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35376)
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_wrapper.vhd
|
8
|
57813
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41056)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/common/output_blk.vhd
|
6
|
27163
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18368)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/ramfifo/wr_status_flags_sshft.vhd
|
6
|
23122
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15376)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_generator_v12_0/hdl/builtin/reset_builtin.vhd
|
6
|
19078
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/ramfifo/wr_dc_fwft_ext_as.vhd
|
6
|
13630
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8352)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
dskntIndustry/Hardware
|
hdl_library/SPI/SPI_Master.vhd
|
1
|
1570
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.CommonFunctions.all;
library hdl_library_ClockGenerator;
use hdl_library_ClockGenerator.ClockGenerator.all;
entity SPI_Master is
generic
(
G_CLOCK_FREQUENCY : integer;
G_SPI_FREQUENCY : integer;
G_SPI_TRANSACTION_SIZE : integer
);
port
(
clock : in std_logic;
enable : in std_logic;
SCLK : out std_logic;
MISO : out std_logic;
MOSI : in std_logic;
SS_n : in std_logic;
tx_data : out std_logic_vector(G_SPI_TRANSACTION_SIZE - 1 downto 0);
rx_data : in std_logic_vector(G_SPI_TRANSACTION_SIZE - 1 downto 0);
data_valid : in std_logic;
ready : out std_logic
);
end entity; --SPI_Master
architecture arch of SPI_Master is
signal SCLK_n : std_logic := '0';
begin
enable <= data_valid;
SerializeDataToSPI:process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
MOSI <= rx_data(rx_data'high);
rx_data <= rx_data(rx_data'high - 1 downto 0) & '0';
end if;
end if;
end process SerializeDataToSPI; -- SerializeDataToSPI
dut : entity hdl_library_ClockGenerator.ClockGenerator
generic map
(
G_CLOCK_FREQUENCY => G_CLOCK_FREQUENCY,
G_CLOCK_DIVIDER => G_CLOCK_DIVIDER
)
port map
(
clock => clock,
enable => enable,
clock_output => SCLK,
clock_output_n => SCLK_n
);
end architecture; -- arch
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_generator_v12_0/hdl/builtin/builtin_top.vhd
|
6
|
77480
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55616)
`protect data_block
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|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/builtin/bin_cntr.vhd
|
6
|
8597
|
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`protect end_protected
|
gpl-3.0
|
Yarr/Yarr-fw
|
rtl/kintex7/rx-core/gearbox32to66.vhd
|
1
|
2153
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX channel
-- # Aurora style rx code
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gearbox32to66 is
port (
-- Sys connect
rst_i : in std_logic;
clk_i : in std_logic;
-- Input
data32_i : in std_logic_vector(31 downto 0);
data32_valid_i : in std_logic;
slip_i : in std_logic;
-- Outoput
data66_o : out std_logic_vector(65 downto 0);
data66_valid_o : out std_logic
);
end gearbox32to66;
architecture rtl of gearbox32to66 is
signal gearbox_cnt : unsigned(7 downto 0);
signal shift_cnt : std_logic;
signal buffer128 : std_logic_vector(127 downto 0);
signal slip_cnt : std_logic;
begin
shift_proc: process(clk_i, rst_i)
begin
if (rst_i = '1') then
buffer128 <= (others => '0');
gearbox_cnt <= (others => '0');
data66_valid_o <= '0';
data66_o <= (others => '0');
shift_cnt <= '0';
slip_cnt <= '0';
elsif rising_edge(clk_i) then
data66_valid_o <= '0';
if (data32_valid_i = '1') then
shift_cnt <= not shift_cnt;
buffer128(127 downto 0) <= buffer128(95 downto 0) & data32_i;
data66_o <= buffer128(128-(to_integer(gearbox_cnt(4 downto 0))*2)-1 downto 62-(to_integer(gearbox_cnt(4 downto 0))*2));
if (shift_cnt = '1') then
if (slip_i = '1') then
gearbox_cnt <= gearbox_cnt;
data66_valid_o <= '1';
elsif (gearbox_cnt = 32) then
gearbox_cnt <= (others => '0');
data66_valid_o <= '0';
else
gearbox_cnt <= gearbox_cnt + 1;
data66_valid_o <= '1';
end if;
end if;
end if;
end if;
end process shift_proc;
end rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/conditional_expressions/rule_100_test_input.vhd
|
2
|
397
|
architecture rtl of fifo is
begin
process
begin
var1 := '0'when rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0'when rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0'when rd_en = '1' else '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/process/rule_008_test_input.fixed_upper.vhd
|
1
|
151
|
architecture RTL of FIFO is
begin
process
begin
END process;
-- Violations below
process
begin
END process;
end architecture RTL;
|
gpl-3.0
|
Yarr/Yarr-fw
|
rtl/spartan6/gn4124-core/dma_controller.vhd
|
2
|
19703
|
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: DMA controller (dma_controller.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 31-08-2010
--
-- version: 0.2
--
-- description: Manages the DMA transfers.
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 30-09-2010 (mcattin) Add status, error and abort
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
entity dma_controller is
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- Interrupt request
dma_ctrl_irq_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
dma_ctrl_carrier_addr_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_o : out std_logic_vector(31 downto 0);
dma_ctrl_len_o : out std_logic_vector(31 downto 0);
dma_ctrl_start_l2p_o : out std_logic; -- To the L2P DMA master
dma_ctrl_start_p2l_o : out std_logic; -- To the P2L DMA master
dma_ctrl_start_next_o : out std_logic; -- To the P2L DMA master
dma_ctrl_byte_swap_o : out std_logic_vector(1 downto 0);
dma_ctrl_abort_o : out std_logic;
dma_ctrl_done_i : in std_logic;
dma_ctrl_error_i : in std_logic;
---------------------------------------------------------
-- From P2L DMA master
next_item_carrier_addr_i : in std_logic_vector(31 downto 0);
next_item_host_addr_h_i : in std_logic_vector(31 downto 0);
next_item_host_addr_l_i : in std_logic_vector(31 downto 0);
next_item_len_i : in std_logic_vector(31 downto 0);
next_item_next_l_i : in std_logic_vector(31 downto 0);
next_item_next_h_i : in std_logic_vector(31 downto 0);
next_item_attrib_i : in std_logic_vector(31 downto 0);
next_item_valid_i : in std_logic;
---------------------------------------------------------
-- Wishbone slave interface
wb_clk_i : in std_logic; -- Bus clock
wb_adr_i : in std_logic_vector(3 downto 0); -- Adress
wb_dat_o : out std_logic_vector(31 downto 0); -- Data in
wb_dat_i : in std_logic_vector(31 downto 0); -- Data out
wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wb_cyc_i : in std_logic; -- Read or write cycle
wb_stb_i : in std_logic; -- Read or write strobe
wb_we_i : in std_logic; -- Write
wb_ack_o : out std_logic -- Acknowledge
);
end dma_controller;
architecture behaviour of dma_controller is
------------------------------------------------------------------------------
-- Wishbone slave component declaration
------------------------------------------------------------------------------
component dma_controller_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
clk_i : in std_logic;
-- Port for std_logic_vector field: 'DMA engine control' in reg: 'DMACTRLR'
dma_ctrl_o : out std_logic_vector(31 downto 0);
dma_ctrl_i : in std_logic_vector(31 downto 0);
dma_ctrl_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA engine status' in reg: 'DMASTATR'
dma_stat_o : out std_logic_vector(31 downto 0);
dma_stat_i : in std_logic_vector(31 downto 0);
dma_stat_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA start address in the carrier' in reg: 'DMACSTARTR'
dma_cstart_o : out std_logic_vector(31 downto 0);
dma_cstart_i : in std_logic_vector(31 downto 0);
dma_cstart_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA start address (low) in the host' in reg: 'DMAHSTARTLR'
dma_hstartl_o : out std_logic_vector(31 downto 0);
dma_hstartl_i : in std_logic_vector(31 downto 0);
dma_hstartl_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA start address (high) in the host' in reg: 'DMAHSTARTHR'
dma_hstarth_o : out std_logic_vector(31 downto 0);
dma_hstarth_i : in std_logic_vector(31 downto 0);
dma_hstarth_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA read length in bytes' in reg: 'DMALENR'
dma_len_o : out std_logic_vector(31 downto 0);
dma_len_i : in std_logic_vector(31 downto 0);
dma_len_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pointer (low) to next item in list' in reg: 'DMANEXTLR'
dma_nextl_o : out std_logic_vector(31 downto 0);
dma_nextl_i : in std_logic_vector(31 downto 0);
dma_nextl_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pointer (high) to next item in list' in reg: 'DMANEXTHR'
dma_nexth_o : out std_logic_vector(31 downto 0);
dma_nexth_i : in std_logic_vector(31 downto 0);
dma_nexth_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA chain control' in reg: 'DMAATTRIBR'
dma_attrib_o : out std_logic_vector(31 downto 0);
dma_attrib_i : in std_logic_vector(31 downto 0);
dma_attrib_load_o : out std_logic
);
end component dma_controller_wb_slave;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_IDLE : std_logic_vector(2 downto 0) := "000";
constant c_DONE : std_logic_vector(2 downto 0) := "001";
constant c_BUSY : std_logic_vector(2 downto 0) := "010";
constant c_ERROR : std_logic_vector(2 downto 0) := "011";
constant c_ABORT : std_logic_vector(2 downto 0) := "100";
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- DMA controller registers
signal dma_ctrl : std_logic_vector(31 downto 0);
signal dma_stat : std_logic_vector(31 downto 0);
signal dma_cstart : std_logic_vector(31 downto 0);
signal dma_hstartl : std_logic_vector(31 downto 0);
signal dma_hstarth : std_logic_vector(31 downto 0);
signal dma_len : std_logic_vector(31 downto 0);
signal dma_nextl : std_logic_vector(31 downto 0);
signal dma_nexth : std_logic_vector(31 downto 0);
signal dma_attrib : std_logic_vector(31 downto 0);
signal dma_ctrl_load : std_logic;
signal dma_stat_load : std_logic;
signal dma_cstart_load : std_logic;
signal dma_hstartl_load : std_logic;
signal dma_hstarth_load : std_logic;
signal dma_len_load : std_logic;
signal dma_nextl_load : std_logic;
signal dma_nexth_load : std_logic;
signal dma_attrib_load : std_logic;
signal dma_ctrl_reg : std_logic_vector(31 downto 0);
signal dma_stat_reg : std_logic_vector(31 downto 0);
signal dma_cstart_reg : std_logic_vector(31 downto 0);
signal dma_hstartl_reg : std_logic_vector(31 downto 0);
signal dma_hstarth_reg : std_logic_vector(31 downto 0);
signal dma_len_reg : std_logic_vector(31 downto 0);
signal dma_nextl_reg : std_logic_vector(31 downto 0);
signal dma_nexth_reg : std_logic_vector(31 downto 0);
signal dma_attrib_reg : std_logic_vector(31 downto 0);
-- DMA controller FSM
type dma_ctrl_state_type is (DMA_IDLE, DMA_START_TRANSFER, DMA_TRANSFER,
DMA_START_CHAIN, DMA_CHAIN,
DMA_ERROR, DMA_ABORT);
signal dma_ctrl_current_state : dma_ctrl_state_type;
-- status signals
signal dma_status : std_logic_vector(2 downto 0);
signal dma_error_irq : std_logic;
signal dma_done_irq : std_logic;
begin
------------------------------------------------------------------------------
-- Wishbone slave instanciation
------------------------------------------------------------------------------
dma_controller_wb_slave_0 : dma_controller_wb_slave port map (
rst_n_i => rst_n_i,
wb_clk_i => wb_clk_i,
wb_addr_i => wb_adr_i,
wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
clk_i => clk_i,
dma_ctrl_o => dma_ctrl,
dma_ctrl_i => dma_ctrl_reg,
dma_ctrl_load_o => dma_ctrl_load,
dma_stat_o => open,
dma_stat_i => dma_stat_reg,
dma_stat_load_o => open,
dma_cstart_o => dma_cstart,
dma_cstart_i => dma_cstart_reg,
dma_cstart_load_o => dma_cstart_load,
dma_hstartl_o => dma_hstartl,
dma_hstartl_i => dma_hstartl_reg,
dma_hstartl_load_o => dma_hstartl_load,
dma_hstarth_o => dma_hstarth,
dma_hstarth_i => dma_hstarth_reg,
dma_hstarth_load_o => dma_hstarth_load,
dma_len_o => dma_len,
dma_len_i => dma_len_reg,
dma_len_load_o => dma_len_load,
dma_nextl_o => dma_nextl,
dma_nextl_i => dma_nextl_reg,
dma_nextl_load_o => dma_nextl_load,
dma_nexth_o => dma_nexth,
dma_nexth_i => dma_nexth_reg,
dma_nexth_load_o => dma_nexth_load,
dma_attrib_o => dma_attrib,
dma_attrib_i => dma_attrib_reg,
dma_attrib_load_o => dma_attrib_load
);
------------------------------------------------------------------------------
-- DMA controller registers
------------------------------------------------------------------------------
p_regs : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
dma_ctrl_reg <= (others => '0');
dma_stat_reg <= (others => '0');
dma_cstart_reg <= (others => '0');
dma_hstartl_reg <= (others => '0');
dma_hstarth_reg <= (others => '0');
dma_len_reg <= (others => '0');
dma_nextl_reg <= (others => '0');
dma_nexth_reg <= (others => '0');
dma_attrib_reg <= (others => '0');
elsif rising_edge(clk_i) then
-- Control register
if (dma_ctrl_load = '1') then
dma_ctrl_reg <= dma_ctrl;
end if;
-- Status register
dma_stat_reg(2 downto 0) <= dma_status;
dma_stat_reg(31 downto 3) <= (others => '0');
-- Target start address
if (dma_cstart_load = '1') then
dma_cstart_reg <= dma_cstart;
end if;
-- Host start address lowest 32-bit
if (dma_hstartl_load = '1') then
dma_hstartl_reg <= dma_hstartl;
end if;
-- Host start address highest 32-bit
if (dma_hstarth_load = '1') then
dma_hstarth_reg <= dma_hstarth;
end if;
-- DMA transfer length in byte
if (dma_len_load = '1') then
dma_len_reg <= dma_len;
end if;
-- next item address lowest 32-bit
if (dma_nextl_load = '1') then
dma_nextl_reg <= dma_nextl;
end if;
-- next item address highest 32-bit
if (dma_nexth_load = '1') then
dma_nexth_reg <= dma_nexth;
end if;
-- Chained DMA control
if (dma_attrib_load = '1') then
dma_attrib_reg <= dma_attrib;
end if;
-- next item received => start a new transfer
if (next_item_valid_i = '1') then
dma_ctrl_reg(0) <= '1';
dma_cstart_reg <= next_item_carrier_addr_i;
dma_hstartl_reg <= next_item_host_addr_l_i;
dma_hstarth_reg <= next_item_host_addr_h_i;
dma_len_reg <= next_item_len_i;
dma_nextl_reg <= next_item_next_l_i;
dma_nexth_reg <= next_item_next_h_i;
dma_attrib_reg <= next_item_attrib_i;
end if;
-- Start DMA, 1 tick pulse
if (dma_ctrl_reg(0) = '1') then
dma_ctrl_reg(0) <= '0';
end if;
end if;
end process p_regs;
dma_ctrl_byte_swap_o <= dma_ctrl_reg(3 downto 2);
------------------------------------------------------------------------------
-- IRQ output assignement
------------------------------------------------------------------------------
dma_ctrl_irq_o <= dma_error_irq & dma_done_irq;
------------------------------------------------------------------------------
-- DMA controller FSM
------------------------------------------------------------------------------
p_fsm : process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
dma_ctrl_current_state <= DMA_IDLE;
dma_ctrl_carrier_addr_o <= (others => '0');
dma_ctrl_host_addr_h_o <= (others => '0');
dma_ctrl_host_addr_l_o <= (others => '0');
dma_ctrl_len_o <= (others => '0');
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
dma_ctrl_start_next_o <= '0';
dma_status <= c_IDLE;
dma_error_irq <= '0';
dma_done_irq <= '0';
dma_ctrl_abort_o <= '0';
elsif rising_edge(clk_i) then
case dma_ctrl_current_state is
when DMA_IDLE =>
-- Clear done irq to make it 1 tick pulse
dma_done_irq <= '0';
if(dma_ctrl_reg(0) = '1') then
-- Starts a new transfer
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when DMA_START_TRANSFER =>
-- Clear abort signal
dma_ctrl_abort_o <= '0';
if (unsigned(dma_len_reg(31 downto 2)) = 0) then
-- Requesting a DMA of 0 word length gives a error
dma_error_irq <= '1';
dma_ctrl_current_state <= DMA_ERROR;
else
-- Start the DMA if the length is not 0
if (dma_attrib_reg(1) = '0') then
-- L2P transfer (from target to PCIe)
dma_ctrl_start_l2p_o <= '1';
elsif (dma_attrib_reg(1) = '1') then
-- P2L transfer (from PCIe to target)
dma_ctrl_start_p2l_o <= '1';
end if;
dma_ctrl_current_state <= DMA_TRANSFER;
dma_ctrl_carrier_addr_o <= dma_cstart_reg;
dma_ctrl_host_addr_h_o <= dma_hstarth_reg;
dma_ctrl_host_addr_l_o <= dma_hstartl_reg;
dma_ctrl_len_o <= dma_len_reg;
dma_status <= c_BUSY;
end if;
when DMA_TRANSFER =>
-- Clear start signals, to make them 1 tick pulses
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
if (dma_ctrl_reg(1) = '1') then
-- Transfer aborted
dma_ctrl_current_state <= DMA_ABORT;
elsif(dma_ctrl_error_i = '1') then
-- An error occurs !
dma_error_irq <= '1';
dma_ctrl_current_state <= DMA_ERROR;
elsif(dma_ctrl_done_i = '1') then
-- End of DMA transfer
if(dma_attrib_reg(0) = '1') then
-- More transfer in chained DMA
dma_ctrl_current_state <= DMA_START_CHAIN;
else
-- Was the last transfer
dma_status <= c_DONE;
dma_done_irq <= '1';
dma_ctrl_current_state <= DMA_IDLE;
end if;
end if;
when DMA_START_CHAIN =>
-- Catch the next item in host memory
dma_ctrl_current_state <= DMA_CHAIN;
dma_ctrl_host_addr_h_o <= dma_nexth_reg;
dma_ctrl_host_addr_l_o <= dma_nextl_reg;
dma_ctrl_len_o <= X"0000001C";
dma_ctrl_start_next_o <= '1';
when DMA_CHAIN =>
-- Clear start next signal, to make it 1 tick pulse
dma_ctrl_start_next_o <= '0';
if (dma_ctrl_reg(1) = '1') then
-- Transfer aborted
dma_ctrl_current_state <= DMA_ABORT;
elsif(dma_ctrl_error_i = '1') then
-- An error occurs !
dma_error_irq <= '1';
dma_ctrl_current_state <= DMA_ERROR;
elsif (next_item_valid_i = '1') then
-- next item received
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when DMA_ERROR =>
dma_status <= c_ERROR;
-- Clear error irq to make it 1 tick pulse
dma_error_irq <= '0';
if(dma_ctrl_reg(0) = '1') then
-- Starts a new transfer
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when DMA_ABORT =>
dma_status <= c_ABORT;
dma_ctrl_abort_o <= '1';
if(dma_ctrl_reg(0) = '1') then
-- Starts a new transfer
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when others =>
dma_ctrl_current_state <= DMA_IDLE;
dma_ctrl_carrier_addr_o <= (others => '0');
dma_ctrl_host_addr_h_o <= (others => '0');
dma_ctrl_host_addr_l_o <= (others => '0');
dma_ctrl_len_o <= (others => '0');
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
dma_ctrl_start_next_o <= '0';
dma_status <= (others => '0');
dma_error_irq <= '0';
dma_done_irq <= '0';
dma_ctrl_abort_o <= '0';
end case;
end if;
end process p_fsm;
end behaviour;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/generic_map/rule_004_test_input.vhd
|
1
|
583
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map (
G_GEN_1 => 1,
G_GEN_2 => 2,
G_GEN_3 => 3);
end architecture ARCH;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/if_statement/rule_009_test_input.fixed.vhd
|
1
|
850
|
architecture RTL of FIFO is
begin
process
begin
if (a = '1' or b = '0' and
c = '1' xor d = '1' and
g = x) then
b <= '0';
elsif (a = '1' or b = '0' and
c = '1' xor d = '1' and
g = x) then
b <= '1';
else
b <= '1';
end if;
-- Violations below
if (a = '1' or b = '0' and
c = '1' xor d = '1' and
g = x) then
b <= '0';
elsif (a = '1' or b = '0' and
c = '1' xor d = '1' and
g = x) then
b <= '1';
else
b <= '1';
end if;
if a = 1 then
b <= 1;
elsif
b = 1 then
c <= 2;
end if;
end process;
-- Check comments in if statements
process begin
if (a = 1 and
-- Comment
b = 0) then
b <= '1';
end if;
end process;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/context/rule_009_test_input.fixed.vhd
|
1
|
413
|
--This should pass
context c1 is
end context c1;
--These should fail
context c1 is
end context
c1;
context
c1
is
end context
-- Some comment
c1;
context c1 is
end context -- Some comment
-- Some other comment
c1;
context c1 -- Yet another commet
-- Some comment
is
end context
-- Comment again
c1;
-- Test with missing end context keyword
context c1 is
end;
context c2 is
end context c2;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/conditional_waveforms/rule_100_test_input.fixed.vhd
|
1
|
398
|
architecture rtl of fifo is
begin
process
begin
var1 := '0'when rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0'when rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' else '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
|
gpl-3.0
|
lvd2/zxevo
|
unsupported/solegstar/fpga/current/sim_models/T80_Pack.vhd
|
7
|
8485
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/signal/rule_014_test_input.vhd
|
1
|
1217
|
architecture RTL of ENTITY1 is
signal sig1, sig2 : std_logic;
signal sig9 : std_logic;
signal sig3 : std_logic;
signal sig4 : std_logic;
signal sig5 : std_logic;
signal sig6 : std_logic;
signal sig7 : std_logic;
component COMP1 is
port (
SIG1 : in std_logic;
SIG2 : out std_logic;
SIG3 : in std_logic
);
end component COMP1;
begin
PROC_NAME : process (siG2) is
begin
siG1 <= '0';
if (SIG2 = '0') then
sIg1 <= '1';
elsif (SiG2 = '1') then
SIg1 <= '0';
end if;
end process PROC_NAME;
-- This is a component that is brought in by a component declaration in the same file
U_COMP1 : COMP1
port map (
SIG1 => Sig1,
SIG2 => SIg2,
SIG3 => sig3
);
-- This is a component that is brought in by a package
U_COMP2 : COMP2
port map (
SIG3 => Sig3,
SIG4 => sig4,
SIG5 => siG5
);
-- This is a component that is directly instantiated
U_COMP3 : entity library.COMP3
port map (
SIG6 => siG6,
SIG7 => sig7
);
Sig1 <= '0';
sig1 <= sig2 and sig3;
sig1 <= Sig2 and sig3;
sig1 <= sig2 and
Sig3;
SIG1 <= SIG2 and SIG3;
SIG1 <= SIG1 or SIG1;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/styles/code_examples/library_statements.vhd
|
1
|
158
|
library work;
use work.tb_utilities.all;
use work.tb_wait_clock_package.all;
use work.random_pkg.all;
use work.dsd_types.all;
--use work.channel_types.all;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/report_statement/rule_500_test_input.vhd
|
1
|
134
|
architecture rtl of fifo is
begin
process begin
REPORT "hello";
report "hello";
end process;
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/interface_signal_declaration/classification_test_input.vhd
|
1
|
496
|
entity FIFO is
port (
port1 : in std_logic;
port1 : out std_logic;
port1 : inout std_logic bus;
port1 : buffer std_logic bus := "asdf";
port1 : linkage std_logic := "asdf";
port1 : std_logic
);
end entity FIFO;
entity FIFO is
port (
signal port1 : in std_logic;
signal port1 : out std_logic;
signal port1 : inout std_logic;
signal port1 : buffer std_logic;
signal port1 : linkage std_logic;
signal port1 : std_logic
);
end entity FIFO;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/after/rule_001_test_input.vhd
|
1
|
2507
|
architecture ARCH of ENTITY is
begin
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (falling_edge(clk)) then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (rising_edge(clk)) then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This checks detection of after outside clock processes
a <= b after 10 ns;
-- Violations below -----------------------------------
-- This process checks for missing after statements
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c;
c <= d;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (falling_edge(clk)) then
a <= b;
b <= c after 1 ns;
c <= d;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (rising_edge(clk)) then
a <= b;
b <= c;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d;
d <= e;
end if;
end process CLK_PROC;
end architecture ARCH;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/comment/rule_011_test_input.fixed.vhd
|
1
|
963
|
-- This should be okay
architecture rtl of fifo is
-- Comment
signal a : std_logic;
-- Okay comment
signal b : std_logic_vector;
begin
-- Comment 1
a <= b;
-- Comment 2
c <= d;
-- Comment 3
e <= f;
-- BQ1/M3S1
rx_tdata_remapped <= rx_tdata(119 downto 112) & rx_tdata(127 downto 120) &
-- BI1/M2S1
rx_tdata(87 downto 80) & rx_tdata(95 downto 88) &
-- BQ0/M3S0
rx_tdata(103 downto 96) & rx_tdata(111 downto 104) &
-- BQ0/M2S0
rx_tdata(71 downto 64) & rx_tdata(79 downto 72) &
-- AQ1/M1S1
rx_tdata(55 downto 48) & rx_tdata(63 downto 56) &
-- AI1/M0S1
rx_tdata(23 downto 16) & rx_tdata(31 downto 24) &
-- AQ0/M1S0
rx_tdata(39 downto 32) & rx_tdata(47 downto 40) &
-- AI0/M0S0
rx_tdata(7 downto 0) & rx_tdata(15 downto 8);
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/port_clause/classification_test_input.vhd
|
1
|
130
|
entity FIFO is
port ( );
end entity FIFO;
entity FIFO is
port (
);
end entity FIFO;
entity FIFO is
port
(
)
;
end entity FIFO;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/record_type_definition/rule_301_test_input.fixed.vhd
|
1
|
392
|
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record a : std_logic; b : std_logic; end record;
begin
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/component/rule_012_test_input.fixed_upper.vhd
|
1
|
212
|
architecture RTl of FIFO is
component fifo is
end component FIFO;
-- Failures below
component fifo is
end component FIFO;
component fifo is
end component FIFO;
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/architecture/rule_020_test_input.fixed_lower.vhd
|
3
|
221
|
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ent is
begin
end rtl;
architecture RTL of Ent is
begin
end Rtl;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end architecture;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/context_ref/rule_003_test_input.vhd
|
1
|
39
|
context c1;
CONTEXT c2;
Context c2;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/type_definition/rule_005_test_input.vhd
|
1
|
308
|
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
type state_machine is (idle,
write,
read, done);
type state_machine is (idle,
write, read, done);
type state_machine is (idle,
write,
read,
done);
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/block/rule_505_test_input.vhd
|
7
|
169
|
architecture RTL of FIFO is
begin
block_label : block is begin end block block_label;
BLOCK_LABEL : BLOCK IS BEGIN END BLOCK BLOCK_LABEL;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/alias_declaration/rule_102_test_input.vhd
|
1
|
164
|
architecture rtl of fifo is
alias designator : subtype_indication is name;
alias designator : subtype_indication is name;
begin
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/package/rule_018_test_input.fixed_upper.vhd
|
1
|
71
|
package fifo_pkg is
end PACKAGE;
package fifo_pkg is
end PACKAGE;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/architecture/rule_017_test_input.vhd
|
1
|
307
|
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
-- This should not fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/conditional_waveforms/rule_103_test_input.vhd
|
2
|
409
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when (rd_en = '1') else'1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when (rd_en = '1') else'1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when (rd_en = '1') else'1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/attribute_specification/rule_503_test_input.fixed_upper.vhd
|
1
|
183
|
architecture RTL of FIFO is
attribute coordinate of comp_1:component IS (0.0, 17.5);
ATTRIBUTE COORDINATE OF comp_1:component IS (0.0, 17.5);
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/generic/rule_013_test_input.vhd
|
1
|
259
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
end entity FIFO;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/comment/rule_100_test_input.fixed.vhd
|
1
|
254
|
--
-- This should pass
--| This should pass
----------This should pass
--==================
-- This should fail
--| This should fail
----------This should pass
--
--==================
--¨
-- pragmas should be ignored
--vhdl_comp_off
--vhdl_comp_on
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/wait/rule_001_test_input.vhd
|
1
|
764
|
entity ENTITY1 is
generic (
wait_generic : std_logic := '0'
);
port (
wait_port : std_logic := '1'
);
end entity ENTITY1;
architecture ARCH of ENTITY1 is
signal wait_for_something : std_logic;
component ENTITY2 is
generic (
wait_generic : std_logic := '0'
);
port (
wait_port : std_logic := '1'
);
end component ENTITY2;
begin
PROC1 : process (wait_for_something) is
-- wait <-- this should not be classified as a wait
variable wait_for_other_thing : std_logic;
begin
wait for 10ns;
wait on a,b;
wait until a = '0';
end process PROC1;
U_ENTITY2 : ENTITY2
generic map (
wait_generic => '0'
)
port map (
wait_port => '1'
);
end architecture ARCH;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/entity/rule_014_test_input.fixed_lower.vhd
|
1
|
103
|
entity FIFO is
end entity fifo;
entity FIFO is
end entity FIFO;
entity FIFO is
end entity FIFO;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/generic_map/rule_003_test_input.vhd
|
1
|
694
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map(
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map
(
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/element_association/rule_100_test_input.vhd
|
1
|
343
|
architecture rtl of fifo is
begin
a <= (others => (others => '0'));
process begin
a <= (others => (others => '0'));
end process;
end architecture;
architecture rtl of fifo is
begin
a <= (others=> (others => '0'));
process begin
a <= (others => (others=> '0'));
end process;
end architecture;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/vsg/read_configuration_files/package_2.vhd
|
12226531
|
0
|
gpl-3.0
|
|
michaelmiehling/A25_VME_TB
|
Testbench/M25P32/memory_access.vhd
|
1
|
9527
|
-------------------------------------------------------
-- Author: Hugues CREUSY
--February 2004
-- VHDL model
-- project: M25P32 50 MHz,
-- release: 1.0
-----------------------------------------------------
-- Unit : Memory Access
-----------------------------------------------------
-------------------------------------------------------------
-- These VHDL models are provided "as is" without warranty
-- of any kind, included but not limited to, implied warranty
-- of merchantability and fitness for a particular purpose.
-------------------------------------------------------------
-----------------------------------------------------------
--
-- MEMORY ACCESS
--
-----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY STD;
USE STD.textio.ALL;
LIBRARY work;
USE WORK.mem_util_pkg.ALL;
-----------------------------------------------------------
-- Entity
-----------------------------------------------------------
-- This entity modelizes the access to the memory array
-----------------------------------------------------------
ENTITY Memory_Access IS
GENERIC( init_file: string;
SIZE : positive;
Plength : positive;
SSIZE : positive;
NB_BIT_DATA: positive;
NB_BIT_ADD: positive;
NB_BIT_ADD_MEM: positive
);
PORT( add_mem: IN std_logic_vector(NB_BIT_ADD_MEM-1 downto 0);
BE_enable,SE_enable,add_pp_enable,PP_enable,read_enable,data_request: IN boolean;
p_prog: IN page (0 TO (Plength-1));
data_to_read: OUT std_logic_vector (NB_BIT_DATA-1 downto 0)
);
END Memory_Access;
-----------------------------------------------------------------
-- Architecture
-----------------------------------------------------------------
-- The architecture contains one process which executes
-- read and write instructions
-- on the content. This content is initialized and further
-- saved by two procedures
-- (write_to_file and read_from_file) in the convenient text file
-----------------------------------------------------------------
ARCHITECTURE Static_Alloc OF Memory_Access IS
CONSTANT bit_to_code_mem:natural:=TO_bit_code(size/NB_BIT_DATA);
CONSTANT top_mem:positive:=size/NB_BIT_DATA-1;
TYPE memoire IS array (0 TO top_mem) OF std_logic_vector(7 downto 0);
--------------------------- PROCEDURES ------------------------
------------------------- READ FROM FILE ----------------------
PROCEDURE read_from_file ( file_name:string;
memory: out memoire) IS
file data_file : text open read_mode is file_name;
VARIABLE L: line;
VARIABLE LSB,MSB:std_logic_vector(3 downto 0);
VARIABLE dr: string (1 to 2*Plength);
VARIABLE index_m: natural:=0;
BEGIN
WHILE NOT endfile(data_file) LOOP
readline(data_file,L);
READ(L,dr);
deallocate(L);
FOR i IN 1 TO Plength LOOP
CASE dr(2*(i-1)+1) IS
WHEN '0'=> MSB := "0000";
WHEN '1'=> MSB := "0001";
WHEN '2'=> MSB := "0010";
WHEN '3'=> MSB := "0011";
WHEN '4'=> MSB := "0100";
WHEN '5'=> MSB := "0101";
WHEN '6'=> MSB := "0110";
WHEN '7'=> MSB := "0111";
WHEN '8'=> MSB := "1000";
WHEN '9'=> MSB := "1001";
WHEN 'A'=> MSB := "1010";
WHEN 'B'=> MSB := "1011";
WHEN 'C'=> MSB := "1100";
WHEN 'D'=> MSB := "1101";
WHEN 'E'=> MSB := "1110";
WHEN 'F'=> MSB := "1111";
WHEN 'a'=> MSB := "1010";
WHEN 'b'=> MSB := "1011";
WHEN 'c'=> MSB := "1100";
WHEN 'd'=> MSB := "1101";
WHEN 'e'=> MSB := "1110";
WHEN 'f'=> MSB := "1111";
WHEN OTHERS => null;
END CASE;
CASE dr(2*(i-1)+2) IS
WHEN '0'=> LSB := "0000";
WHEN '1'=> LSB := "0001";
WHEN '2'=> LSB := "0010";
WHEN '3'=> LSB := "0011";
WHEN '4'=> LSB := "0100";
WHEN '5'=> LSB := "0101";
WHEN '6'=> LSB := "0110";
WHEN '7'=> LSB := "0111";
WHEN '8'=> LSB := "1000";
WHEN '9'=> LSB := "1001";
WHEN 'A'=> LSB := "1010";
WHEN 'B'=> LSB := "1011";
WHEN 'C'=> LSB := "1100";
WHEN 'D'=> LSB := "1101";
WHEN 'E'=> LSB := "1110";
WHEN 'F'=> LSB := "1111";
WHEN 'a'=> MSB := "1010";
WHEN 'b'=> MSB := "1011";
WHEN 'c'=> MSB := "1100";
WHEN 'd'=> MSB := "1101";
WHEN 'e'=> MSB := "1110";
WHEN 'f'=> MSB := "1111";
WHEN OTHERS => null;
END CASE;
memory(index_m):=(MSB(3),MSB(2),MSB(1),MSB(0),LSB(3),LSB(2),LSB(1),LSB(0));
index_m:=index_m+1;
END LOOP;
END LOOP;
END read_from_file;
----------------------------------------------------------
---------------- WRITE TO FILE --------------------
PROCEDURE write_to_file ( file_name:string;
memory:IN memoire) IS
file data_file : text open write_mode is file_name;
VARIABLE L: line;
VARIABLE LSB,MSB:std_logic_vector(3 downto 0);
VARIABLE dr: string (1 to 2*Plength);
VARIABLE index_m:natural:=0;
BEGIN
WHILE (index_m<TOP_MEM) LOOP
FOR i IN 1 TO Plength LOOP
FOR j IN 0 TO 3 LOOP
LSB(j):= memory(index_m)(j);
MSB(j):= memory(index_m)(j+4);
END LOOP;
index_m:=index_m+1;
CASE MSB IS
WHEN "0000" => dr(2*(i-1)+1):='0';
WHEN "0001" => dr(2*(i-1)+1):='1';
WHEN "0010" => dr(2*(i-1)+1):='2';
WHEN "0011" => dr(2*(i-1)+1):='3';
WHEN "0100" => dr(2*(i-1)+1):='4';
WHEN "0101" => dr(2*(i-1)+1):='5';
WHEN "0110" => dr(2*(i-1)+1):='6';
WHEN "0111" => dr(2*(i-1)+1):='7';
WHEN "1000" => dr(2*(i-1)+1):='8';
WHEN "1001" => dr(2*(i-1)+1):='9';
WHEN "1010" => dr(2*(i-1)+1):='A';
WHEN "1011" => dr(2*(i-1)+1):='B';
WHEN "1100" => dr(2*(i-1)+1):='C';
WHEN "1101" => dr(2*(i-1)+1):='D';
WHEN "1110" => dr(2*(i-1)+1):='E';
WHEN "1111" => dr(2*(i-1)+1):='F';
WHEN OTHERS => null;
END CASE;
CASE LSB IS
WHEN "0000" => dr(2*(i-1)+2):='0';
WHEN "0001" => dr(2*(i-1)+2):='1';
WHEN "0010" => dr(2*(i-1)+2):='2';
WHEN "0011" => dr(2*(i-1)+2):='3';
WHEN "0100" => dr(2*(i-1)+2):='4';
WHEN "0101" => dr(2*(i-1)+2):='5';
WHEN "0110" => dr(2*(i-1)+2):='6';
WHEN "0111" => dr(2*(i-1)+2):='7';
WHEN "1000" => dr(2*(i-1)+2):='8';
WHEN "1001" => dr(2*(i-1)+2):='9';
WHEN "1010" => dr(2*(i-1)+2):='A';
WHEN "1011" => dr(2*(i-1)+2):='B';
WHEN "1100" => dr(2*(i-1)+2):='C';
WHEN "1101" => dr(2*(i-1)+2):='D';
WHEN "1110" => dr(2*(i-1)+2):='E';
WHEN "1111" => dr(2*(i-1)+2):='F';
WHEN OTHERS => null;
END CASE;
END LOOP;
WRITE(L,dr);
writeline(data_file,L);
END LOOP;
END write_to_file;
----------------------------------------------------
BEGIN -- architecture body begins here
----------------------------------------------------
-- PROCESS MEMORY
----------------------------------------------------
memory: PROCESS
VARIABLE content:memoire;
VARIABLE deb_zone, int_add:natural:=0;
VARIABLE cut_add:std_logic_vector(bit_to_code_mem-1 downto 0);
VARIABLE int_add_mem:natural:=to_bit_code(size/NB_BIT_DATA);
VARIABLE first_run:boolean:=true;
VARIABLE message, my_file: LINE;
BEGIN
---------------------------------
-- initialisation of memory array
---------------------------------
IF (first_run) THEN
WRITE (message,string'("Trying to load "));
WRITE (message, init_file);
writeline(output, message);
read_from_file(init_file,content);
first_run:=false;
END IF;
WAIT ON add_pp_enable,pp_enable, be_enable, se_enable, data_request,read_enable;
-----------------------------------------------------------
-- To ignore don't care MSB of the address
-----------------------------------------------------------
IF ( (se_enable'event AND se_enable)
OR (add_pp_enable'event AND add_pp_enable)
OR (read_enable'event AND read_enable) ) THEN
FOR i IN 0 TO bit_to_code_mem-1 LOOP
cut_add(i):=add_mem(i);
END LOOP;
END IF;
-----------------------------------------------------------
-- Read instruction
-----------------------------------------------------------
IF (data_request'event AND data_request AND read_enable) THEN
int_add:=to_natural(cut_add);
IF (int_add>top_mem) THEN
FOR i IN 0 TO bit_to_code_mem-1 LOOP
cut_add(i):='0';
END LOOP;
int_add:=0;
END IF;
data_to_read<=content(int_add);
cut_add:=add_inc(cut_add); -- to increase the adress
END IF;
IF (READ_enable'event AND (NOT read_enable)) THEN
FOR i IN 0 TO NB_BIT_DATA-1 LOOP
data_to_read(i)<='0';
END LOOP;
END IF;
----------------------------------------------------------
-- Page program instruction
-- To find the first adress of the memory to be programmed
----------------------------------------------------------
IF (add_pp_enable'event AND add_pp_enable) THEN
int_add_mem:=to_natural(cut_add);
int_add:=top_mem+1;
WHILE int_add>int_add_mem LOOP
int_add:=int_add-Plength;
END LOOP;
END IF;
------------------------------------------------------
-- Sector erase instruction
-- To find the first adress of the sector to be erased
------------------------------------------------------
IF (se_enable'event AND se_enable) THEN
int_add:=add_sector(cut_add,SIZE/NB_BIT_DATA,SSIZE/NB_BIT_DATA);
END IF;
------------------------------------------------------
-- Write or erase cycle execution
------------------------------------------------------
IF (pp_enable'event AND (pp_enable)) THEN
FOR i IN 0 TO (Plength-1) LOOP
content (int_add+i):=p_prog(i) AND content(int_add+i);
END LOOP;
-- write_to_file(init_file,content);
END IF;
IF (be_enable'event AND (NOT be_enable)) THEN
FOR i IN 0 TO top_mem LOOP
content(i):="11111111";
END LOOP;
-- write_to_file(init_file,content);
END IF;
IF (se_enable'event AND (NOT se_enable)) THEN
FOR i IN int_add TO (int_add+SSIZE/NB_BIT_DATA-1) LOOP
content(i):="11111111";
END LOOP;
-- write_to_file(init_file,content);
END IF;
END PROCESS memory;
END static_alloc;
|
gpl-3.0
|
bobxiv/DispositivosLogicosProgramables-FICH
|
Proyecto 1 DLP TP Calculadora/Src/ArithmeticTest.vhd
|
1
|
4123
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:03:50 10/08/2011
-- Design Name:
-- Module Name: C:/Users/BOB/Calculadora/Source/ArithmeticTest.vhd
-- Project Name: Calculadora
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ArithmeticModule
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ArithmeticTest IS
END ArithmeticTest;
ARCHITECTURE behavior OF ArithmeticTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ArithmeticModule
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
Op : IN std_logic_vector(1 downto 0);
Res : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal Op : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal Res : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ArithmeticModule PORT MAP (
A => A,
B => B,
Op => Op,
Res => Res
);
-- Clock process definitions
--<clock>_process :process
--begin
--<clock> <= '0';
--wait for <clock>_period/2;
--<clock> <= '1';
--wait for <clock>_period/2;
--end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
--wait for <clock>_period*10;
-- Estimulos:
-- ----------
--Prueba de la operacion de suma
--Prueba 1 Comienza a 100ns
A <= "00000001";--1
B <= "00001000";--8
OP <= "00";--Suma
--Res deberia tener 9, osea 00001001b
wait for 100 ns;
--Prueba 2 Comienza a 200ns
A <= "00000001";--1
B <= "00000001";--1
OP <= "00";--Suma
--Res deberia tener 2, osea 00000010b
wait for 100 ns;
--Prueba 3 Comienza a 300ns
A <= "00000101";--5
B <= "00000011";--3
OP <= "00";--Suma
--Res deberia tener 8, osea 00001000b
wait for 100 ns;
--Prueba de la operacion de resta
--Prueba 1 Comienza a 400ns
A <= "00001000";--8
B <= "00000001";--1
OP <= "01";--Resta
--Res deberia tener 7, osea 00000111b
wait for 100 ns;
--Prueba 2 Comienza a 500ns
A <= "00000001";--1
B <= "00000001";--1
OP <= "01";--Resta
--Res deberia tener 0, osea 00000000b
wait for 100 ns;
--Prueba 3 Comienza a 600ns
A <= "00000101";--5
B <= "00000011";--3
OP <= "01";--Resta
--Res deberia tener 2, osea 00000010b
wait for 100 ns;
--Prueba de la operacion de multiplicacion
--Prueba 1 Comienza a 700ns
A <= "00001000";--8
B <= "00000001";--1
OP <= "10";--Multiplicacion
--Res deberia tener 8, osea 00001000b
wait for 100 ns;
--Prueba 2 Comienza a 800ns
A <= "00000011";--3
B <= "00000111";--7
OP <= "10";--Multiplicacion
--Res deberia tener 21, osea 00010101b
wait for 100 ns;
--Prueba 3 Comienza a 900ns
A <= "00000101";--5
B <= "00000011";--3
OP <= "10";--Multiplicacion
--Res deberia tener 15, osea 00001111b
wait for 100 ns;
wait;
end process;
END;
|
gpl-3.0
|
michaelmiehling/A25_VME_TB
|
Testbench/M25P32/mem_util_pkg.vhd
|
1
|
5403
|
-------------------------------------------------------
-- Author: Hugues CREUSY
--February 2004
-- VHDL model
-- project: M25P32 50 MHz,
-- release: 1.0
-----------------------------------------------------
-- Unit : Package mem_util_pkg
-----------------------------------------------------
-------------------------------------------------------------
-- These VHDL models are provided "as is" without warranty
-- of any kind, included but not limited to, implied warranty
-- of merchantability and fitness for a particular purpose.
-------------------------------------------------------------
-------------------------------------------------------------------------
-- Memory utilization package
-------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-------------------------------------------------------------------------
-- PACKAGE
-------------------------------------------------------------------------
PACKAGE mem_util_pkg IS
TYPE PAGE is ARRAY (natural range <>) of std_logic_vector(7 downto 0);
--------------------------------------------------------------------
-- To convert a standard logic vector (ie a binary word) into
-- a natural
---------------------------------------------------------------------
FUNCTION TO_natural(vecteur_bit : std_logic_vector ) RETURN natural ;
---------------------------------------------------------------------
---------------------------------------------------------------------------
-- To increase the adress pointing vector
---------------------------------------------------------------------------
FUNCTION add_inc(vecteur_bit : std_logic_vector ) RETURN std_logic_vector ;
---------------------------------------------------------------------------
--------------------------------------------------------------------
-- To get the number of bits used to code the memory
-- which size (number of bytes) is a parameter
--------------------------------------------------------------------
FUNCTION TO_bit_code(nb_octets: positive) RETURN natural ;
--------------------------------------------------------------------
------------------------------------------------------------------------
-- To get the first adress of the sector pointed by anyone of its bytes.
------------------------------------------------------------------------
FUNCTION add_sector(vecteur_bit: std_logic_vector;
NB_byte_mem,NB_byte_sect: positive) RETURN natural;
------------------------------------------------------------------------
--------------------------------------------------------------------------
-- To convert an integer (ARG) into a standard logic vector with its size.
--------------------------------------------------------------------------
FUNCTION TO_std_logic_vector(ARG: INTEGER; SIZE: INTEGER)
RETURN STD_LOGIC_VECTOR;
--------------------------------------------------------------------------
END mem_util_pkg;
---------------------------------------------------------------
-- Package body
---------------------------------------------------------------
PACKAGE BODY mem_util_pkg IS
----------------------------------------------------------------
FUNCTION TO_natural(vecteur_bit : std_logic_vector ) RETURN natural IS
VARIABLE val_vecteur: natural := 0;
BEGIN
FOR J IN vecteur_bit'RANGE LOOP
val_vecteur := val_vecteur * 2;
val_vecteur := val_vecteur + std_logic'pos(vecteur_bit(J)) - 2;
END LOOP;
RETURN val_vecteur;
END TO_natural;
---------------------------------------------------------------
FUNCTION add_inc(vecteur_bit : std_logic_vector ) RETURN std_logic_vector IS
VARIABLE val_vecteur: std_logic_vector(vecteur_bit'RANGE);
BEGIN
val_vecteur := vecteur_bit;
FOR J IN vecteur_bit'REVERSE_RANGE LOOP
val_vecteur(J) := "XOR"( vecteur_bit(J), '1' );
IF (val_vecteur(J) = '1') THEN
EXIT;
END IF;
END LOOP;
RETURN val_vecteur;
END add_inc;
-----------------------------------------------------------------
FUNCTION TO_bit_code(nb_octets: positive) RETURN natural IS
VARIABLE val_add, add_bit_code: natural ;
BEGIN
val_add := nb_octets;
add_bit_code := 0;
IF ((val_add rem 2)/=0) THEN
val_add := val_add - 1 ;
add_bit_code := add_bit_code + 1 ;
END IF;
WHILE ( val_add > 1 ) LOOP
val_add := (val_add/2);
add_bit_code := add_bit_code + 1;
END LOOP;
RETURN add_bit_code;
END TO_bit_code;
---------------------------------------------------------------
FUNCTION TO_std_logic_vector(ARG: INTEGER; SIZE: INTEGER)
RETURN STD_LOGIC_VECTOR IS
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
begin
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2;
end if;
end loop;
return result;
END TO_std_logic_vector;
------------------------------------------------------------
FUNCTION add_sector(vecteur_bit:std_logic_vector;NB_byte_mem,NB_byte_sect:positive)
RETURN natural IS
VARIABLE addr_sector,deb_sect: natural := 0;
BEGIN
addr_sector := TO_natural(vecteur_bit);
FOR i IN 1 TO (NB_byte_mem/NB_byte_sect) LOOP
IF ((i-1)*NB_byte_sect<=addr_sector AND addr_sector < i*NB_byte_sect) THEN
deb_sect:=(i-1)*NB_byte_sect;
END IF;
END LOOP;
RETURN deb_sect;
END add_sector;
--------------------------------------------------------------
END mem_util_pkg;
|
gpl-3.0
|
bobxiv/DispositivosLogicosProgramables-FICH
|
Practica/testseg.vhd
|
1
|
3167
|
--------------------------------------------------------------------------------
-- Company: Universidad de Valencia
-- Engineer: Alfredo Rosado
--
-- Create Date: 10:58:12 10/16/2006
-- Design Name: segmentos
-- Module Name: C:/Xilinx/prac1/prac1b/testseg.vhd
-- Project Name: prac1b
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: segmentos
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY testseg_vhd IS
END testseg_vhd;
ARCHITECTURE behavior OF testseg_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT segmentos
PORT(
Reloj : IN std_logic;
Reset : IN std_logic;
interruptor : IN std_logic_vector(3 downto 0);
abcdefgdp : OUT std_logic_vector(7 downto 0);
anodos : BUFFER std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL Reloj : std_logic := '0';
SIGNAL Reset : std_logic := '0';
SIGNAL interruptor : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL abcdefgdp : std_logic_vector(7 downto 0);
SIGNAL anodos : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: segmentos PORT MAP(
Reloj => Reloj,
Reset => Reset,
interruptor => interruptor,
abcdefgdp => abcdefgdp,
anodos => anodos
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
Reset <= '1';
wait for 15 ns;
reset <= '0';
wait; -- will wait forever
END PROCESS;
tb2 : PROCESS
BEGIN
Reloj <= '1';
wait for 10 ns;
Reloj <= '0';
wait for 10 ns;
END PROCESS;
tb3 : PROCESS
BEGIN
interruptor <= "0000";
wait for 1000 ns;
interruptor(0) <= '1';
wait for 1000 ns;
interruptor(0) <= '0';
interruptor(1) <= '1';
wait for 1000 ns;
interruptor(1) <= '0';
interruptor(2) <= '1';
wait for 1000 ns;
interruptor(2) <= '0';
interruptor(3) <= '1';
wait for 1000 ns;
interruptor(3) <= '0';
interruptor(0) <= '1';
wait for 1000 ns;
interruptor(0) <= '0';
interruptor(1) <= '1';
wait for 1000 ns;
interruptor(1) <= '0';
interruptor(2) <= '1';
wait for 1000 ns;
interruptor(2) <= '0';
interruptor(3) <= '1';
wait for 1000 ns;
interruptor(3) <= '0';
interruptor(0) <= '1';
wait for 1000 ns;
interruptor(0) <= '0';
interruptor(1) <= '1';
wait for 1000 ns;
interruptor(1) <= '0';
interruptor(2) <= '1';
wait for 1000 ns;
interruptor(2) <= '0';
interruptor(3) <= '1';
wait for 1000 ns;
interruptor(3) <= '0';
interruptor(0) <= '1';
wait;
END PROCESS;
END;
|
gpl-3.0
|
lelongdunet/dspunit
|
sim/rompkg.vhd
|
2
|
2115
|
-------------------------------------------------------------------------------
-- Le langage VHDL : du langage au circuit, du circuit au langage.
-- Copyright (C) Jacques Weber, Sébastien Moutault et Maurice Meaudre, 2006.
--
-- Ce programme est libre, vous pouvez le redistribuer et/ou le modifier selon
-- les termes de la Licence Publique Générale GNU publiée par la Free Software
-- Foundation (version 2 ou bien toute autre version ultérieure choisie par
-- vous).
--
-- Ce programme est distribué car potentiellement utile, mais SANS AUCUNE
-- GARANTIE, ni explicite ni implicite, y compris les garanties de
-- commercialisation ou d'adaptation dans un but spécifique. Reportez-vous à
-- la Licence Publique Générale GNU pour plus de détails.
--
-- Vous devez avoir reçu une copie de la Licence Publique Générale GNU en même
-- temps que ce programme ; si ce n'est pas le cas, écrivez à la Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307,
-- États-Unis.
--
-- [email protected]
-- [email protected]
-------------------------------------------------------------------------------
-- Projet :
-- Design :
-- Fichier : rompkg.vhd
-- Module : PACKAGE rompkg
-- Descript. :
-- Auteur : J.Weber
-- Date : 03/03/07
-- Version : 1.0
-- Depend. :
-- Simulation : ModelSim 6.0d
-- Synthèse :
-- Remarques :
--
--
-------------------------------------------------------------------------------
-- Date | Rév | Description
-- 01/08/06 | 1.0 | Première version stable utilisée pour le livre.
-- 03/03/07 | | Pas de modifications du design.
-- | | Preparation pour la mise en ligne.
-- | |
-- | |
-------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
PACKAGE rompkg IS
CONSTANT ad_nb_bits : INTEGER := 3 ; -- e
CONSTANT size: INTEGER := 2**ad_nb_bits ; -- 8 bytes
SUBTYPE byte IS STD_LOGIC_VECTOR(7 DOWNTO 0) ;
TYPE rom_tbl IS ARRAY(NATURAL RANGE <>) OF byte ;
END PACKAGE rompkg ;
|
gpl-3.0
|
michaelfivez/ascon_hardware_implementation
|
ascon12864_iterated/Kernel/DiffusionLayer.vhd
|
1
|
1684
|
-------------------------------------------------------------------------------
--! @project Iterated hardware implementation of Asconv12864
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DiffusionLayer is
generic( SHIFT1 : integer range 0 to 63;
SHIFT2 : integer range 0 to 63);
port( Input : in std_logic_vector(63 downto 0);
Output : out std_logic_vector(63 downto 0));
end entity DiffusionLayer;
architecture structural of DiffusionLayer is
begin
DiffLayer: process(Input) is
variable Temp0,Temp1 : std_logic_vector(63 downto 0);
begin
Temp0(63 downto 64-SHIFT1) := Input(SHIFT1-1 downto 0);
Temp0(63-SHIFT1 downto 0) := Input(63 downto SHIFT1);
Temp1(63 downto 64-SHIFT2) := Input(SHIFT2-1 downto 0);
Temp1(63-SHIFT2 downto 0) := Input(63 downto SHIFT2);
Output <= Temp0 xor Temp1 xor Input;
end process DiffLayer;
end architecture structural;
|
gpl-3.0
|
hsnuonly/PikachuVolleyFPGA
|
VGA.srcs/sources_1/ip/select1/synth/select1.vhd
|
1
|
14297
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY select1 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END select1;
ARCHITECTURE select1_arch OF select1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF select1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF select1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF select1_arch : ARCHITECTURE IS "select1,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF select1_arch: ARCHITECTURE IS "select1,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=select1.mif" &
",C_INIT_FILE=select1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=2071,C_READ_DEPTH_A=2071,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B" &
"=2071,C_READ_DEPTH_B=2071,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN" &
"_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.822999 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "select1.mif",
C_INIT_FILE => "select1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 2071,
C_READ_DEPTH_A => 2071,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 2071,
C_READ_DEPTH_B => 2071,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.822999 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END select1_arch;
|
gpl-3.0
|
hsnuonly/PikachuVolleyFPGA
|
VGA.ip_user_files/ip/bg_pole/bg_pole_stub.vhdl
|
2
|
1364
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:47 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_pole/bg_pole_stub.vhdl
-- Design : bg_pole
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bg_pole is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end bg_pole;
architecture stub of bg_pole is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[6:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
gpl-3.0
|
bsmerbeckuri/SHA512Optimization
|
CPU_System/Rhody_CPU_pipelinev7.vhd
|
1
|
38937
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev7 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev7 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant WPAD2 : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
signal rcount: integer := 0;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD or Opcode2=WPAD2) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
elsif (Opcode2 = WLOAD) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = WPAD) then
if (rcount < 80) then
wout <= std_logic_vector(mvect(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))));
end if;
elsif (Opcode2 = WPAD2) then
if (rcount < 80) then
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2 = WPAD) then
if (rcount < 80) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
elsif (Opcode2 = WPAD2) then
if (rcount < 80) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (rcount < 80) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= rcount + 1;
end if;
elsif(Opcode3 = WPAD2) then
if (rcount < 80) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= rcount + 1;
end if;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif (Opcode3 = WPAD2) then
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
|
gpl-3.0
|
hsnuonly/PikachuVolleyFPGA
|
VGA.ip_user_files/ip/select1/select1_stub.vhdl
|
2
|
1366
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:49 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/select1/select1_stub.vhdl
-- Design : select1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity select1 is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end select1;
architecture stub of select1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[11:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
gpl-3.0
|
hsnuonly/PikachuVolleyFPGA
|
VGA.srcs/sources_1/ip/title3/synth/title3.vhd
|
1
|
14282
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY title3 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END title3;
ARCHITECTURE title3_arch OF title3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF title3_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF title3_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF title3_arch : ARCHITECTURE IS "title3,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF title3_arch: ARCHITECTURE IS "title3,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=title3.mif,C" &
"_INIT_FILE=title3.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=3725,C_READ_DEPTH_A=3725,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=37" &
"25,C_READ_DEPTH_B=3725,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BH" &
"V_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.822999 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "title3.mif",
C_INIT_FILE => "title3.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 3725,
C_READ_DEPTH_A => 3725,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 3725,
C_READ_DEPTH_B => 3725,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.822999 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END title3_arch;
|
gpl-3.0
|
hsnuonly/PikachuVolleyFPGA
|
VGA.srcs/sources_1/ip/title2_1/synth/title2.vhd
|
1
|
14290
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY title2 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END title2;
ARCHITECTURE title2_arch OF title2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF title2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF title2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF title2_arch : ARCHITECTURE IS "title2,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF title2_arch: ARCHITECTURE IS "title2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=title2.mif,C" &
"_INIT_FILE=title2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=10404,C_READ_DEPTH_A=10404,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=" &
"10404,C_READ_DEPTH_B=10404,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WAR" &
"N_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.227751 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "title2.mif",
C_INIT_FILE => "title2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 10404,
C_READ_DEPTH_A => 10404,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 10404,
C_READ_DEPTH_B => 10404,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.227751 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END title2_arch;
|
gpl-3.0
|
bsmerbeckuri/SHA512Optimization
|
CPU_System/Rhody_CPU_pipelinev42.vhd
|
2
|
29774
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev42 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev42 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RX4 : std_logic_vector(2 downto 0) is IR4(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RY3 : std_logic_vector(2 downto 0) is IR3(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
signal tmpxx: std_logic_vector(19 downto 0);
signal tmpyy: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
--constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant LDMD2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
--constant LDIX : std_logic_vector(5 downto 0) := "000110";
--constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
--constant T11 : std_logic_vector(5 downto 0) := "101110";
--constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant STMD : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant LDMD : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal rcount : std_logic_vector(31 downto 0);
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal dvect : WORD_VECTOR(0 to 7);
signal wout: std_logic_vector(63 downto 0);
signal lcount: std_logic_vector(31 downto 0);
signal scount: std_logic_vector(31 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2=LDMD) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when ((Opcode3=RETI or Opcode3=LDMD) and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3 = STMD) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when ((Opcode4=SYS or Opcode4=STMD) and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2=STM or Opcode2=STR or Opcode2=WPAD or Opcode2 = LDMD or Opcode2 = STMD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI or Opcode3=LDMD or Opcode3 = STMD or Opcode3 = WPAD) else
true when(Opcode4=SYS or Opcode4=RETI or Opcode4 = STMD) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
rcount <= x"00000000";
lcount <= x"00000000";
scount <= x"00000000";
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
t1_val <= X"0000000000000000";
t2_val <= X"0000000000000000";
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM or Opcode2 = LDMD) then
MAR <= x"000" & M2;
tmpxx <= std_logic_vector((unsigned(M2) + 1));
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STMD) then
dvect(0) <= std_logic_vector(unsigned(wva) + unsigned(h0));
dvect(1) <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dvect(2) <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dvect(3) <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dvect(4) <= std_logic_vector(unsigned(wve) + unsigned(h4));
dvect(5) <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dvect(6) <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dvect(7) <= std_logic_vector(unsigned(wvh) + unsigned(h7));
MAR <= x"000" & M2;
MDR_out <= dvect(to_integer(unsigned(scount)))(63 downto 32);
tmpyy <= x"000" & std_logic_vector(unsigned(M2) + 1);
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2 = WPAD) then
if (to_integer(unsigned(rcount)) < 1) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
end if;
if (to_integer(unsigned(rcount)) < 16) then
wout <= std_logic_vector(mvect(to_integer(unsigned(rcount))));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2 = LDMD) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR) then
null;
elsif(Opcode2=STMD) then
register_file(to_integer(unsigned(RX3))) <= MAR;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = WPAD) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(rcount)))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=LDMD) then
mvect(to_integer(unsigned(lcount)))(63 downto 32) <= MDR_in;
MAR <= x"000" & tmpxx;
register_file(to_integer(unsigned(RX3))) <= std_logic_vector(lcount);
elsif (Opcode3=STM or Opcode3=STR) then
null;
elsif (Opcode3 = STMD) then
register_file(to_integer(unsigned(RY3))) <= tmpyy;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (to_integer(unsigned(rcount)) < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= std_logic_vector((unsigned(rcount)+1));
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= std_logic_vector((unsigned(rcount)+1));
end if;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif(Opcode3 = LDMD) then
MDR_in <= MEM_in;
elsif(Opcode3 = STMD) then
MAR <= tmpyy;
MDR_out <= dvect(to_integer(unsigned(scount)))(31 downto 0);
elsif (Opcode3 = WPAD) then
if (to_integer(unsigned(rcount)) < 1) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
end if;
if (to_integer(unsigned(rcount)) < 16) then
wout <= std_logic_vector(mvect(to_integer(unsigned(rcount))));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
elsif (Opcode4 = LDMD) then
mvect(to_integer(unsigned(lcount)))(31 downto 0) <= MDR_in;
elsif (Opcode4 = STMD) then
null;
elsif (Opcode4 = WPAD) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(rcount)))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
if (Opcode4 = LDMD) then
lcount <= std_logic_vector(unsigned(lcount)+1);
elsif (Opcode4 = STMD) then
if (to_integer(unsigned(scount)) = 7) then
scount <= x"00000000";
else
scount <= std_logic_vector(unsigned(scount) + 1);
end if;
elsif(Opcode4 = WPAD) then
if (to_integer(unsigned(rcount)) < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= std_logic_vector((unsigned(rcount)+1));
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= std_logic_vector((unsigned(rcount)+1));
end if;
end if;
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
|
gpl-3.0
|
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/crc_calc.vhd
|
1
|
7094
|
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fvk $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2010-04-14 14:16:04 +0200 (Wed, 14 Apr 2010) $
-- Revision : $Revision: 189 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------
-- LIBRARY --
-------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
-- CRC Tool by Easics
library work;
use work.all;
use work.PCK_CRC10_D10.all;
use work.PCK_CRC8_D8.all;
--use work.app_pack.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity crc_calc is
generic (
DATAWIDTH : integer ;
POLYNOMIAL : std_logic_vector := "11001001111";
USE_CRC_TOOL : boolean := TRUE
);
port ( -- System
-- APP_CFG_REG : in AppCfgRegTp;
INITVALUE : in std_logic;
CLOCK : in std_logic;
RESET : in std_logic;
-- Data input
INIT : in std_logic;
DATA_IN : in std_logic_vector(DATAWIDTH-1 downto 0);
CRC_OUT : out std_logic_vector(DATAWIDTH-1 downto 0)
);
end;
---------------------------
-- BEHAVIOUR DESCRIPTION --
---------------------------
architecture rtl of crc_calc is
----------------------------
-- COMPONENTS DEFINITIONS --
----------------------------
-- Xilinx components
-- none
-- user components
-- none
-------------------------------
-- TYPE & SIGNAL DEFINITIONS --
-------------------------------
type temptp is array (DATAWIDTH downto 0) of std_logic_vector(DATAWIDTH downto 0);
signal CRC_own : std_logic_vector(DATAWIDTH-1 downto 0);
signal CRC_tool : unsigned(DATAWIDTH-1 downto 0);
signal tmparray : temptp;
--------------------
-- MAIN BEHAVIOUR --
--------------------
begin
CRC_OUT <= std_logic_vector(CRC_tool(DATAWIDTH-1 downto 0)) when (USE_CRC_TOOL = TRUE) else CRC_own;
CRCModule:process(CLOCK, RESET)
variable CRC_own_i : std_logic_vector(DATAWIDTH downto 0);
variable temp : std_logic_vector(DATAWIDTH downto 0);
begin
if (RESET ='1') then
CRC_own_i := (others => '1');
CRC_tool <= (others => '1');
CRC_own <= (others => '1');
--
elsif (CLOCK'event and CLOCK = '1') then
--DATA_IN_delay1 <= DATA_IN;
--DATA_IN_delay2 <= DATA_IN_delay1;
-- if (INIT='1' and APP_CFG_REG.sysmode(7) = '0') then
if (INIT='1' and INITVALUE = '0') then
CRC_tool <= (others => '1'); --CRC tool by easics
CRC_own <= (others => '1'); --own implementation
CRC_own_i := (others => '1');
-- elsif ( INIT='1' and APP_CFG_REG.sysmode(7) = '1') then
elsif ( INIT='1' and INITVALUE = '1') then
CRC_tool <= (others => '0'); --CRC tool by easics
CRC_own <= (others => '0'); --own implementation
CRC_own_i := (others => '0');
else
CRC_own_i(DATAWIDTH-1 downto 0) := DATA_IN xor CRC_own_i(DATAWIDTH downto 1);
CRC_own_i(DATAWIDTH) := '0';
for i in (DATAWIDTH) downto 0 loop
if (CRC_own_i(CRC_own_i'high) = '1') then
temp := (CRC_own_i xor POLYNOMIAL);
CRC_own_i := (temp(DATAWIDTH-1 downto 0) & '0');
tmparray(DATAWIDTH-i) <= temp;
else
CRC_own_i := (CRC_own_i(DATAWIDTH-1 downto 0) & '0');
end if;
end loop;
if (DATAWIDTH = 10) then
CRC_tool <= nextCRC10_D10(unsigned(DATA_IN),unsigned(CRC_tool)); --CRC tool by easics
else
CRC_tool <= nextCRC8_D8(unsigned(DATA_IN),unsigned(CRC_tool)); --CRC tool by easics
end if;
CRC_own <= CRC_own_i(DATAWIDTH downto 1); --own implementation
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl.vhd
|
2
|
15657
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-3.0
|
CprE488/Final
|
repository/ProcessorIPLib/pcores/axi_tpg_v2_00_a/hdl/vhdl/user_logic.vhd
|
1
|
20629
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Oct 22 10:34:41 2007 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 8;
C_FAMILY : string := "virtex5";
C_Chroma_Format : integer := 0 -- 0 = RGB444; 1 = YCbCr422
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
clk : in STD_LOGIC;
rst : in STD_LOGIC;
vsync_in : in std_logic;
hsync_in : in std_logic;
vblank_in : in std_logic;
hblank_in : in std_logic;
de_in : in std_logic;
red_in : in std_logic_vector(7 downto 0);
green_in : in std_logic_vector(7 downto 0);
blue_in : in std_logic_vector(7 downto 0);
vsync_out : out std_logic;
hsync_out : out std_logic;
vblank_out : out std_logic;
hblank_out : out std_logic;
de_out : out std_logic;
red_out : out std_logic_vector(7 downto 0);
green_out : out std_logic_vector(7 downto 0);
blue_out : out std_logic_vector(7 downto 0);
ZP_debug : out std_logic_vector(57 downto 0);
TPG_debug : out std_logic_vector(38 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
signal Control_reg : std_logic_vector(31 downto 0);
signal Motion_reg : std_logic_vector(31 downto 0);
signal XHairs_reg : std_logic_vector(31 downto 0);
signal FrameSize_reg : std_logic_vector(31 downto 0);
signal ZPlateHDelta_reg : std_logic_vector(31 downto 0);
signal ZPlateVDelta_reg : std_logic_vector(31 downto 0);
signal BoxSize_reg : std_logic_vector(31 downto 0);
signal BoxColour_reg : std_logic_vector(31 downto 0);
signal not_tpg_hsync_out : std_logic;
signal not_tpg_vsync_out : std_logic;
------------------------------------------
signal slv_reg_write_sel : std_logic_vector(0 to (C_NUM_REG-1));
signal slv_reg_read_sel : std_logic_vector(0 to (C_NUM_REG-1));
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
type slv_array1 is array (natural range <>) of std_logic_vector(C_SLV_DWIDTH-1 downto 0);
type slv_array2 is array (natural range <>) of std_logic_vector(C_SLV_DWIDTH-1 downto 0);
type slv_array_ce is array (natural range <>) of std_logic_vector(0 to C_NUM_REG-1);
type slv_array_be is array (natural range <>) of std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
constant slv_mask : slv_array2(0 to C_NUM_REG-1) := (
x"00000fff", --00 0
x"000001ff", --04 1
x"0fff0fff", --08 2
x"0fff0fff", --0c 3
x"ffffffff", --10 4
x"ffffffff", --14 5
x"00000fff", --18 6
x"00ffffff" --1c 7
);
signal slv_reg : slv_array2((C_NUM_REG-1) downto 0);
signal le_slv_reg : slv_array1(C_NUM_REG-1 downto 0);
signal slv_reg_stat : slv_array2(C_NUM_REG-1 downto 0);
signal le_slv_reg_stat : slv_array1(C_NUM_REG-1 downto 0);
signal Bus2IP_Data_sync : slv_array2(1 downto 0);
signal slv_ip2bus_data_sync : slv_array2(1 downto 0);
signal Bus2IP_WrCE_sync : slv_array_ce(1 downto 0);
signal Bus2IP_RdCE_sync : slv_array_ce(1 downto 0);
signal Bus2IP_BE_sync : slv_array_be(1 downto 0);
signal Bus2IP_Reset_sync : std_logic_vector(1 downto 0);
signal reset_core : std_logic;
signal slv_write_ack_sync : std_logic_vector(1 downto 0);
signal slv_read_ack_sync : std_logic_vector(1 downto 0);
constant read_only_reg : std_logic_vector((C_NUM_REG-1) downto 0) := "00000000";
-- JLH: Signals used to created single beat acknowledge
signal rdack_d : std_logic := '0';
signal slv_read_ack_end : std_logic;
signal wrack_d : std_logic := '0';
signal slv_write_ack_end : std_logic;
signal RdCE_or : std_logic_vector(C_NUM_REG downto 0);
signal WrCE_or : std_logic_vector(C_NUM_REG downto 0);
attribute SYN_PRESERVE : boolean;
attribute KEEP : boolean;
attribute SYN_KEEP : boolean;
-- CW
attribute SYN_PRESERVE of Bus2IP_Data_sync : signal is TRUE;
attribute KEEP of Bus2IP_Data_sync : signal is TRUE;
attribute SYN_KEEP of Bus2IP_Data_sync : signal is TRUE;
attribute SYN_PRESERVE of slv_ip2bus_data_sync : signal is TRUE;
attribute KEEP of slv_ip2bus_data_sync : signal is TRUE;
attribute SYN_KEEP of slv_ip2bus_data_sync : signal is TRUE;
attribute SYN_PRESERVE of Bus2IP_WrCE_sync: signal is TRUE;
attribute KEEP of Bus2IP_WrCE_sync: signal is TRUE;
attribute SYN_KEEP of Bus2IP_WrCE_sync: signal is TRUE;
attribute SYN_PRESERVE of Bus2IP_RdCE_sync : signal is TRUE;
attribute KEEP of Bus2IP_RdCE_sync : signal is TRUE;
attribute SYN_KEEP of Bus2IP_RdCE_sync : signal is TRUE;
attribute SYN_PRESERVE of Bus2IP_BE_sync : signal is TRUE;
attribute KEEP of Bus2IP_BE_sync : signal is TRUE;
attribute SYN_KEEP of Bus2IP_BE_sync : signal is TRUE;
attribute SYN_PRESERVE of slv_write_ack_sync : signal is TRUE;
attribute KEEP of slv_write_ack_sync : signal is TRUE;
attribute SYN_KEEP of slv_write_ack_sync : signal is TRUE;
attribute SYN_PRESERVE of slv_read_ack_sync : signal is TRUE;
attribute KEEP of slv_read_ack_sync : signal is TRUE;
attribute SYN_KEEP of slv_read_ack_sync : signal is TRUE;
attribute SYN_PRESERVE of Bus2IP_Reset_sync : signal is TRUE;
attribute KEEP of Bus2IP_Reset_sync : signal is TRUE;
attribute SYN_KEEP of Bus2IP_Reset_sync : signal is TRUE;
attribute KEEP of slv_reg_read_sel : signal is TRUE;
attribute KEEP of slv_reg_write_sel : signal is TRUE;
attribute KEEP of Bus2IP_RdCE : signal is TRUE;
attribute KEEP of Bus2IP_WrCE : signal is TRUE;
-- end CW
begin
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
--- slv_reg_write_sel <= Bus2IP_WrCE(0 to 7);
--- slv_reg_read_sel <= Bus2IP_RdCE(0 to 7);
--- slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7);
--- slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
-- JLH: Variable input OR gates for ack end generation
RdCE_or(0)<='0';
WrCE_or(0)<='0';
GEN_OR: for i in 0 to C_NUM_REG-1 generate
RdCE_or(i+1)<=Bus2IP_RdCE(i) or RdCE_or(i);
WrCE_or(i+1)<=Bus2IP_WrCE(i) or WrCE_or(i);
end generate;
slv_read_ack_end <= RdCE_or(C_NUM_REG);
slv_write_ack_end <= WrCE_or(C_NUM_REG);
---- Including sync registers
slv_reg_write_sel <= Bus2IP_WrCE_sync(Bus2IP_WrCE_sync'high);
slv_write_ack <= '0' when(Bus2IP_WrCE_sync(Bus2IP_WrCE_sync'high) = 0) else '1';
slv_reg_read_sel <= Bus2IP_RdCE_sync(Bus2IP_RdCE_sync'high);
slv_read_ack <= '0' when(Bus2IP_RdCE_sync(Bus2IP_RdCE_sync'high) = 0) else '1';
reset_core <= Bus2IP_Reset_sync(Bus2IP_Reset_sync'high);
-- signal synchronization to clk domain
process(clk) is
begin
if (clk'event) and (clk = '1') then
Bus2IP_Data_sync <= Bus2IP_Data_sync(Bus2IP_Data_sync'high-1 downto 0) & Bus2IP_Data;
Bus2IP_WrCE_sync <= Bus2IP_WrCE_sync(Bus2IP_WrCE_sync'high-1 downto 0) & Bus2IP_WrCE;
Bus2IP_RdCE_sync <= Bus2IP_RdCE_sync(Bus2IP_RdCE_sync'high-1 downto 0) & Bus2IP_RdCE;
Bus2IP_BE_sync <= Bus2IP_BE_sync(Bus2IP_BE_sync'high-1 downto 0) & Bus2IP_BE;
Bus2IP_Reset_sync <= Bus2IP_Reset_sync(Bus2IP_Reset_sync'high-1 downto 0) & Bus2IP_Reset;
end if;
end process;
-- signal synchronization to Bus2IP_Clk domain
process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
slv_ip2bus_data_sync <= slv_ip2bus_data_sync(slv_ip2bus_data_sync'high-1 downto 0) & slv_ip2bus_data;
slv_write_ack_sync <= slv_write_ack_sync(slv_write_ack_sync'high-1 downto 0) & slv_write_ack;
slv_read_ack_sync <= slv_read_ack_sync(slv_read_ack_sync'high-1 downto 0) & slv_read_ack;
if Bus2IP_Reset = '1' then -- remove and set attribute to not use SRL16
rdack_d <= '0';
wrack_d <= '0';
else
-- JLH: Create single beat read acknowledge.
if (rdack_d = '1') then
rdack_d <= '0';
elsif (slv_read_ack_end = '1') then
rdack_d <= slv_read_ack_sync(slv_read_ack_sync'high);
end if;
-- JLH: Create single beat write acknowledge.
if (wrack_d = '1') then
wrack_d <= '0';
elsif (slv_write_ack_end = '1') then
wrack_d <= slv_write_ack_sync(slv_write_ack_sync'high);
end if;
end if;
end if;
end process;
SLAVE_REG_WRITE_PROC2 : process(clk) is
begin
if clk'event and clk = '1' then
if reset_core = '1' then
for i in 0 to C_NUM_REG-1 loop
if (read_only_reg(i) = '0') then
slv_reg(i) <= (others => '0');
end if;
end loop;
else
for i in 0 to C_NUM_REG-1 loop
if(slv_reg_write_sel(i) = '1') then
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE_sync(Bus2IP_BE_sync'high)(byte_index) = '1' ) then
if (read_only_reg(i) = '0') then
-- slv_reg(i)(byte_index*8 to byte_index*8+7) <= Bus2IP_Data_sync(Bus2IP_Data_sync'high)(byte_index*8 to byte_index*8+7);
slv_reg(i)(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data_sync(Bus2IP_Data_sync'high)(byte_index*8+7 downto byte_index*8);
end if;
end if;
end loop;
end if;
end loop;
end if;
end if;
end process SLAVE_REG_WRITE_PROC2;
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg) is
begin
slv_ip2bus_data <= (others => '0');
for i in 0 to C_NUM_REG-1 loop
if(slv_reg_read_sel(i) = '1') then
for j in 0 to C_SLV_DWIDTH-1 loop
if (slv_mask(i)(j) = '1') then
slv_ip2bus_data(j) <= slv_reg(i)(j);
else
slv_ip2bus_data(j) <= slv_reg_stat(i)(j);
end if;
end loop;
end if;
end loop;
end process SLAVE_REG_READ_PROC;
GEN_REGS: for i in 0 to C_NUM_REG-1 generate
le_slv_reg(i) <= slv_reg(i);
slv_reg_stat(i) <= le_slv_reg_stat(i);
end generate GEN_REGS;
tpg_u1 : entity work.tpg_core
generic map
(
C_FAMILY => C_FAMILY,
C_Chroma_Format => C_Chroma_Format
)
port map
(
clk => clk,
rst => rst,
vsync_in => vsync_in,
hsync_in => hsync_in,
vblank_in => vblank_in,
hblank_in => hblank_in,
CbCrPolarity => le_slv_reg(0)(5),
VSyncPolarity => le_slv_reg(0)(10),
HSyncPolarity => le_slv_reg(0)(11),
VBlankPolarity => le_slv_reg(0)(12),
HBlankPolarity => le_slv_reg(0)(13),
de_in => de_in,
red_in => red_in,
green_in => green_in,
blue_in => blue_in,
PatternSel => le_slv_reg(0)(3 downto 0),
Motion => le_slv_reg(1)(0),
Motion_speed => le_slv_reg(1)(8 downto 1),
EnableXHairs => le_slv_reg(0)(4),
ComponentMask => le_slv_reg(0)(8 downto 6),
EnableBox => le_slv_reg(0)(9),
XHairsV => le_slv_reg(2)(11 downto 0),
XHairsH => le_slv_reg(2)(27 downto 16),
active_line_length => le_slv_reg(3)(11 downto 0),
active_frame_height => le_slv_reg(3)(27 downto 16),
ZPlateHDeltaStart => le_slv_reg(4)(31 downto 16),
ZPlateHDelta2 => le_slv_reg(4)(15 downto 0),
ZPlateVDeltaStart => le_slv_reg(5)(31 downto 16),
ZPlateVDelta2 => le_slv_reg(5)(15 downto 0),
BoxSize => le_slv_reg(6)(11 downto 0),
BoxColour => le_slv_reg(7)(23 downto 0),
vsync_out => vsync_out,
hsync_out => hsync_out,
vblank_out => vblank_out,
hblank_out => hblank_out,
de_out => de_out,
red_out => red_out,
green_out => green_out,
blue_out => blue_out,
ZP_debug => ZP_debug,
TPG_debug => TPG_debug
);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
-- IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
-- IP2Bus_WrAck <= slv_write_ack;
-- IP2Bus_RdAck <= slv_read_ack;
-- IP2Bus_Error <= '0';
---- Including sync registers
-- JLH: Modified to use single beat ack signals wrack_d, rdack_d
IP2Bus_Data <= slv_ip2bus_data_sync(slv_ip2bus_data_sync'high);
IP2Bus_WrAck <= wrack_d;--slv_write_ack_sync(slv_write_ack_sync'high);
IP2Bus_RdAck <= rdack_d; -- slv_read_ack_sync(slv_read_ack_sync'high);
IP2Bus_Error <= '0';
end IMP;
|
gpl-3.0
|
CprE488/Final
|
system/hdl/system_v_tc_vid_out_0_wrapper.vhd
|
1
|
10199
|
-------------------------------------------------------------------------------
-- system_v_tc_vid_out_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library v_tc_v5_01_a;
use v_tc_v5_01_a.all;
entity system_v_tc_vid_out_0_wrapper is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector(8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_v_tc_vid_out_0_wrapper : entity is "v_tc_v5_01_a";
end system_v_tc_vid_out_0_wrapper;
architecture STRUCTURE of system_v_tc_vid_out_0_wrapper is
component v_tc is
generic (
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_GEN_AUTO_SWITCH : integer;
C_MAX_PIXELS : integer;
C_MAX_LINES : integer;
C_NUM_FSYNCS : integer;
C_DETECT_EN : integer;
C_GENERATE_EN : integer;
C_DET_HSYNC_EN : integer;
C_DET_VSYNC_EN : integer;
C_DET_HBLANK_EN : integer;
C_DET_VBLANK_EN : integer;
C_DET_AVIDEO_EN : integer;
C_DET_ACHROMA_EN : integer;
C_GEN_HSYNC_EN : integer;
C_GEN_VSYNC_EN : integer;
C_GEN_HBLANK_EN : integer;
C_GEN_VBLANK_EN : integer;
C_GEN_AVIDEO_EN : integer;
C_GEN_ACHROMA_EN : integer;
C_GEN_VIDEO_FORMAT : INTEGER;
C_GEN_CPARITY : integer;
C_SYNC_EN : integer;
C_GEN_VBLANK_POLARITY : integer;
C_GEN_HBLANK_POLARITY : integer;
C_GEN_VSYNC_POLARITY : integer;
C_GEN_HSYNC_POLARITY : integer;
C_GEN_AVIDEO_POLARITY : integer;
C_GEN_ACHROMA_POLARITY : integer;
C_GEN_VACTIVE_SIZE : integer;
C_GEN_HACTIVE_SIZE : integer;
C_GEN_HFRAME_SIZE : integer;
C_GEN_F0_VFRAME_SIZE : integer;
C_GEN_HSYNC_START : integer;
C_GEN_HSYNC_END : integer;
C_GEN_F0_VBLANK_HSTART : integer;
C_GEN_F0_VBLANK_HEND : integer;
C_GEN_F0_VSYNC_VSTART : integer;
C_GEN_F0_VSYNC_VEND : integer;
C_GEN_F0_VSYNC_HSTART : integer;
C_GEN_F0_VSYNC_HEND : integer;
C_FSYNC_HSTART0 : integer;
C_FSYNC_VSTART0 : integer;
C_FSYNC_HSTART1 : integer;
C_FSYNC_VSTART1 : integer;
C_FSYNC_HSTART2 : integer;
C_FSYNC_VSTART2 : integer;
C_FSYNC_HSTART3 : integer;
C_FSYNC_VSTART3 : integer;
C_FSYNC_HSTART4 : integer;
C_FSYNC_VSTART4 : integer;
C_FSYNC_HSTART5 : integer;
C_FSYNC_VSTART5 : integer;
C_FSYNC_HSTART6 : integer;
C_FSYNC_VSTART6 : integer;
C_FSYNC_HSTART7 : integer;
C_FSYNC_VSTART7 : integer;
C_FSYNC_HSTART8 : integer;
C_FSYNC_VSTART8 : integer;
C_FSYNC_HSTART9 : integer;
C_FSYNC_VSTART9 : integer;
C_FSYNC_HSTART10 : integer;
C_FSYNC_VSTART10 : integer;
C_FSYNC_HSTART11 : integer;
C_FSYNC_VSTART11 : integer;
C_FSYNC_HSTART12 : integer;
C_FSYNC_VSTART12 : integer;
C_FSYNC_HSTART13 : integer;
C_FSYNC_VSTART13 : integer;
C_FSYNC_HSTART14 : integer;
C_FSYNC_VSTART14 : integer;
C_FSYNC_HSTART15 : integer;
C_FSYNC_VSTART15 : integer;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_FAMILY : STRING
);
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(C_NUM_FSYNCS-1 to 0)
);
end component;
begin
v_tc_vid_out_0 : v_tc
generic map (
C_HAS_AXI4_LITE => 1,
C_HAS_INTC_IF => 0,
C_GEN_AUTO_SWITCH => 1,
C_MAX_PIXELS => 4096,
C_MAX_LINES => 4096,
C_NUM_FSYNCS => 1,
C_DETECT_EN => 0,
C_GENERATE_EN => 1,
C_DET_HSYNC_EN => 1,
C_DET_VSYNC_EN => 1,
C_DET_HBLANK_EN => 1,
C_DET_VBLANK_EN => 1,
C_DET_AVIDEO_EN => 1,
C_DET_ACHROMA_EN => 0,
C_GEN_HSYNC_EN => 1,
C_GEN_VSYNC_EN => 1,
C_GEN_HBLANK_EN => 1,
C_GEN_VBLANK_EN => 1,
C_GEN_AVIDEO_EN => 1,
C_GEN_ACHROMA_EN => 0,
C_GEN_VIDEO_FORMAT => 0,
C_GEN_CPARITY => 0,
C_SYNC_EN => 1,
C_GEN_VBLANK_POLARITY => 1,
C_GEN_HBLANK_POLARITY => 1,
C_GEN_VSYNC_POLARITY => 1,
C_GEN_HSYNC_POLARITY => 1,
C_GEN_AVIDEO_POLARITY => 1,
C_GEN_ACHROMA_POLARITY => 1,
C_GEN_VACTIVE_SIZE => 720,
C_GEN_HACTIVE_SIZE => 1280,
C_GEN_HFRAME_SIZE => 1650,
C_GEN_F0_VFRAME_SIZE => 750,
C_GEN_HSYNC_START => 1390,
C_GEN_HSYNC_END => 1430,
C_GEN_F0_VBLANK_HSTART => 1280,
C_GEN_F0_VBLANK_HEND => 1280,
C_GEN_F0_VSYNC_VSTART => 724,
C_GEN_F0_VSYNC_VEND => 729,
C_GEN_F0_VSYNC_HSTART => 1280,
C_GEN_F0_VSYNC_HEND => 1280,
C_FSYNC_HSTART0 => 0,
C_FSYNC_VSTART0 => 0,
C_FSYNC_HSTART1 => 0,
C_FSYNC_VSTART1 => 0,
C_FSYNC_HSTART2 => 0,
C_FSYNC_VSTART2 => 0,
C_FSYNC_HSTART3 => 0,
C_FSYNC_VSTART3 => 0,
C_FSYNC_HSTART4 => 0,
C_FSYNC_VSTART4 => 0,
C_FSYNC_HSTART5 => 0,
C_FSYNC_VSTART5 => 0,
C_FSYNC_HSTART6 => 0,
C_FSYNC_VSTART6 => 0,
C_FSYNC_HSTART7 => 0,
C_FSYNC_VSTART7 => 0,
C_FSYNC_HSTART8 => 0,
C_FSYNC_VSTART8 => 0,
C_FSYNC_HSTART9 => 0,
C_FSYNC_VSTART9 => 0,
C_FSYNC_HSTART10 => 0,
C_FSYNC_VSTART10 => 0,
C_FSYNC_HSTART11 => 0,
C_FSYNC_VSTART11 => 0,
C_FSYNC_HSTART12 => 0,
C_FSYNC_VSTART12 => 0,
C_FSYNC_HSTART13 => 0,
C_FSYNC_VSTART13 => 0,
C_FSYNC_HSTART14 => 0,
C_FSYNC_VSTART14 => 0,
C_FSYNC_HSTART15 => 0,
C_FSYNC_VSTART15 => 0,
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_FAMILY => "zynq"
)
port map (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aclken => s_axi_aclken,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
irq => irq,
intc_if => intc_if,
clk => clk,
resetn => resetn,
clken => clken,
det_clken => det_clken,
gen_clken => gen_clken,
fsync_in => fsync_in,
vblank_in => vblank_in,
vsync_in => vsync_in,
hblank_in => hblank_in,
hsync_in => hsync_in,
active_video_in => active_video_in,
active_chroma_in => active_chroma_in,
vblank_out => vblank_out,
vsync_out => vsync_out,
hblank_out => hblank_out,
hsync_out => hsync_out,
active_video_out => active_video_out,
active_chroma_out => active_chroma_out,
fsync_out => fsync_out
);
end architecture STRUCTURE;
|
gpl-3.0
|
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/pulse_regen_k7/simulation/fg_tb_pkg.vhd
|
1
|
11733
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pulse_regen_k7_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-3.0
|
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth.vhd
|
1
|
11115
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 100 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 74,
C_DOUT_WIDTH => 74,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-3.0
|
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/pulse_regen.vhd
|
1
|
4151
|
library ieee;
use ieee.std_logic_1164.all;
entity pulse_regen is
generic
(
C_FAMILY : string := "kintex7"
);
port
(
rst : IN std_logic;
clk1 : IN std_logic;
pulse1 : IN std_logic;
clk2 : IN std_logic;
pulse2 : OUT std_logic
);
end entity pulse_regen;
architecture rtl of pulse_regen is
--
-- Device specific FIFOs
--
component pulse_regen_s6
port (
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(0 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(0 downto 0);
valid : OUT std_logic;
empty : OUT std_logic;
full : OUT std_logic
);
end component;
component pulse_regen_v6
port (
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(0 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(0 downto 0);
valid : OUT std_logic;
empty : OUT std_logic;
full : OUT std_logic
);
end component;
component pulse_regen_k7
port (
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(0 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(0 downto 0);
valid : OUT std_logic;
empty : OUT std_logic;
full : OUT std_logic
);
end component;
begin
S6_GEN : if (C_FAMILY = "spartan6") generate
pulse_regen_s6_l : pulse_regen_s6
port map (
rst => rst,
wr_clk => clk1,
wr_en => pulse1,
din => (others => '0'),
full => open,
rd_clk => clk2,
rd_en => '1',
dout => open,
valid => pulse2,
empty => open
);
end generate S6_GEN;
V6_GEN : if (C_FAMILY = "virtex6") generate
pulse_regen_v6_l : pulse_regen_v6
port map (
rst => rst,
wr_clk => clk1,
wr_en => pulse1,
din => (others => '0'),
full => open,
rd_clk => clk2,
rd_en => '1',
dout => open,
valid => pulse2,
empty => open
);
end generate V6_GEN;
K7_GEN : if (C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
pulse_regen_k7_l : pulse_regen_k7
port map (
rst => rst,
wr_clk => clk1,
wr_en => pulse1,
din => (others => '0'),
full => open,
rd_clk => clk2,
rd_en => '1',
dout => open,
valid => pulse2,
empty => open
);
end generate K7_GEN;
end rtl;
|
gpl-3.0
|
victor1994y/BipedRobot_byFPGA
|
Project_BipedRobot.srcs/sources_1/ip/vio_0/vio_0_stub.vhdl
|
1
|
1425
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Thu Jul 20 11:47:27 2017
-- Host : ACER-BLUES running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- d:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/vio_0/vio_0_stub.vhdl
-- Design : vio_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vio_0 is
Port (
clk : in STD_LOGIC;
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end vio_0;
architecture stub of vio_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2015.4";
begin
end;
|
gpl-3.0
|
gau-veldt/InsideTheBox
|
Progress_2017_12_21/vic_ii.vhd
|
1
|
33498
|
----------------------------------------------------------------------------------
--
-- VIC II simulator
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vic_ii is
port (
-- register access
rga : in std_logic_vector(5 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
-- video access
va : out std_logic_vector(13 downto 0);
vd : in std_logic_vector(7 downto 0);
cd : in std_logic_vector(3 downto 0);
-- bus mastering
cpu_clk : out std_logic; -- 4 MHz CPU clock
cpu_ben : out std_logic; -- 1=CPU on buses
vic_ben : out std_logic; -- 1=VIC on buses
bus_ph0 : out std_logic; -- master PH0 clock
bus_ph1 : out std_logic; -- master PH1 clock
bus_ph2 : out std_logic; -- master PH2 clock
res0 : in std_logic; -- reset (low)
-- external signals
clk20_ph1 : in std_logic;
clk20_ph2 : in std_logic;
vhs : out std_logic;
vvs : out std_logic;
vr : out std_logic_vector(4 downto 0);
vg : out std_logic_vector(5 downto 0);
vb : out std_logic_vector(4 downto 0)
);
end vic_ii;
architecture vic_ii_impl of vic_ii is
attribute ram_style : string;
attribute gated_clock : string;
attribute fsm_encoding : string;
--attribute gated_clock of clk20_ph1 : signal is "true";
--attribute gated_clock of clk20_ph2 : signal is "true";
subtype sl is std_logic;
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv6 is std_logic_vector(5 downto 0);
subtype u6 is unsigned(5 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype u9 is unsigned(8 downto 0);
subtype slv9 is std_logic_vector(8 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype cgptr is std_logic_vector(11 downto 0);
subtype dword is std_logic_vector(31 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype long is unsigned(31 downto 0);
subtype v_addr is std_logic_vector(13 downto 0);
subtype c_addr is std_logic_vector(9 downto 0);
subtype r_addr is std_logic_vector(5 downto 0);
type vregs is array(46 downto 0) of byte;
signal vic_regs : vregs := (
others => x"00"
);
attribute ram_style of vic_regs : signal is "registers";
alias vic_M0X : byte is vic_regs( 0);
alias vic_M0X8 : sl is vic_regs(16)(0);
alias vic_M1X : byte is vic_regs( 1);
alias vic_M1X8 : sl is vic_regs(16)(1);
alias vic_M2X : byte is vic_regs( 2);
alias vic_M2X8 : sl is vic_regs(16)(2);
alias vic_M3X : byte is vic_regs( 3);
alias vic_M3X8 : sl is vic_regs(16)(3);
alias vic_M4X : byte is vic_regs( 4);
alias vic_M4X8 : sl is vic_regs(16)(4);
alias vic_M5X : byte is vic_regs( 5);
alias vic_M5X8 : sl is vic_regs(16)(5);
alias vic_M6X : byte is vic_regs( 6);
alias vic_M6X8 : sl is vic_regs(16)(6);
alias vic_M7X : byte is vic_regs( 7);
alias vic_M7X8 : sl is vic_regs(16)(7);
alias vic_M0Y : byte is vic_regs( 8);
alias vic_M1Y : byte is vic_regs( 9);
alias vic_M2Y : byte is vic_regs(10);
alias vic_M3Y : byte is vic_regs(11);
alias vic_M4Y : byte is vic_regs(12);
alias vic_M5Y : byte is vic_regs(13);
alias vic_M6Y : byte is vic_regs(14);
alias vic_M7Y : byte is vic_regs(15);
alias vic_YSCROLL : slv3 is vic_regs(17)(2 downto 0);
alias vic_RSEL : sl is vic_regs(17)(3);
alias vic_DEN : sl is vic_regs(17)(4);
alias vic_BMM : sl is vic_regs(17)(5);
alias vic_ECM : sl is vic_regs(17)(6);
alias vic_RST8 : sl is vic_regs(17)(7);
alias vic_RASTER : byte is vic_regs(18);
alias vic_LPX : byte is vic_regs(19);
alias vic_LPY : byte is vic_regs(20);
alias vic_M0E : sl is vic_regs(21)(0);
alias vic_M1E : sl is vic_regs(21)(1);
alias vic_M2E : sl is vic_regs(21)(2);
alias vic_M3E : sl is vic_regs(21)(3);
alias vic_M4E : sl is vic_regs(21)(4);
alias vic_M5E : sl is vic_regs(21)(5);
alias vic_M6E : sl is vic_regs(21)(6);
alias vic_M7E : sl is vic_regs(21)(7);
alias vic_XSCROLL : slv3 is vic_regs(22)(2 downto 0);
alias vic_CSEL : sl is vic_regs(22)(3);
alias vic_MCM : sl is vic_regs(22)(4);
alias vic_RES : sl is vic_regs(22)(5);
alias vic_M0YE : sl is vic_regs(23)(0);
alias vic_M1YE : sl is vic_regs(23)(1);
alias vic_M2YE : sl is vic_regs(23)(2);
alias vic_M3YE : sl is vic_regs(23)(3);
alias vic_M4YE : sl is vic_regs(23)(4);
alias vic_M5YE : sl is vic_regs(23)(5);
alias vic_M6YE : sl is vic_regs(23)(6);
alias vic_M7YE : sl is vic_regs(23)(7);
alias vic_CB : slv3 is vic_regs(24)(3 downto 1);
alias vic_VM : nybble is vic_regs(24)(7 downto 4);
alias vic_IRQ : sl is vic_regs(25)(7);
alias vic_ILP : sl is vic_regs(25)(3);
alias vic_IMMC : sl is vic_regs(25)(2);
alias vic_IMBC : sl is vic_regs(25)(1);
alias vic_IRST : sl is vic_regs(25)(0);
alias vic_ELP : sl is vic_regs(26)(3);
alias vic_EMMC : sl is vic_regs(26)(2);
alias vic_EMBC : sl is vic_regs(26)(1);
alias vic_ERST : sl is vic_regs(26)(0);
alias vic_M0DP : sl is vic_regs(27)(0);
alias vic_M1DP : sl is vic_regs(27)(1);
alias vic_M2DP : sl is vic_regs(27)(2);
alias vic_M3DP : sl is vic_regs(27)(3);
alias vic_M4DP : sl is vic_regs(27)(4);
alias vic_M5DP : sl is vic_regs(27)(5);
alias vic_M6DP : sl is vic_regs(27)(6);
alias vic_M7DP : sl is vic_regs(27)(7);
alias vic_M0MC : sl is vic_regs(28)(0);
alias vic_M1MC : sl is vic_regs(28)(1);
alias vic_M2MC : sl is vic_regs(28)(2);
alias vic_M3MC : sl is vic_regs(28)(3);
alias vic_M4MC : sl is vic_regs(28)(4);
alias vic_M5MC : sl is vic_regs(28)(5);
alias vic_M6MC : sl is vic_regs(28)(6);
alias vic_M7MC : sl is vic_regs(28)(7);
alias vic_M0XE : sl is vic_regs(29)(0);
alias vic_M1XE : sl is vic_regs(29)(1);
alias vic_M2XE : sl is vic_regs(29)(2);
alias vic_M3XE : sl is vic_regs(29)(3);
alias vic_M4XE : sl is vic_regs(29)(4);
alias vic_M5XE : sl is vic_regs(29)(5);
alias vic_M6XE : sl is vic_regs(29)(6);
alias vic_M7XE : sl is vic_regs(29)(7);
alias vic_M0M : sl is vic_regs(30)(0);
alias vic_M1M : sl is vic_regs(30)(1);
alias vic_M2M : sl is vic_regs(30)(2);
alias vic_M3M : sl is vic_regs(30)(3);
alias vic_M4M : sl is vic_regs(30)(4);
alias vic_M5M : sl is vic_regs(30)(5);
alias vic_M6M : sl is vic_regs(30)(6);
alias vic_M7M : sl is vic_regs(30)(7);
alias vic_M0D : sl is vic_regs(31)(0);
alias vic_M1D : sl is vic_regs(31)(1);
alias vic_M2D : sl is vic_regs(31)(2);
alias vic_M3D : sl is vic_regs(31)(3);
alias vic_M4D : sl is vic_regs(31)(4);
alias vic_M5D : sl is vic_regs(31)(5);
alias vic_M6D : sl is vic_regs(31)(6);
alias vic_M7D : sl is vic_regs(31)(7);
alias vic_EC : nybble is vic_regs(32)(3 downto 0);
alias vic_B0C : nybble is vic_regs(33)(3 downto 0);
alias vic_B1C : nybble is vic_regs(34)(3 downto 0);
alias vic_B2C : nybble is vic_regs(35)(3 downto 0);
alias vic_B3C : nybble is vic_regs(36)(3 downto 0);
alias vic_MM0 : nybble is vic_regs(37)(3 downto 0);
alias vic_MM1 : nybble is vic_regs(38)(3 downto 0);
alias vic_M0C : nybble is vic_regs(39)(3 downto 0);
alias vic_M1C : nybble is vic_regs(40)(3 downto 0);
alias vic_M2C : nybble is vic_regs(41)(3 downto 0);
alias vic_M3C : nybble is vic_regs(42)(3 downto 0);
alias vic_M4C : nybble is vic_regs(43)(3 downto 0);
alias vic_M5C : nybble is vic_regs(44)(3 downto 0);
alias vic_M6C : nybble is vic_regs(45)(3 downto 0);
alias vic_M7C : nybble is vic_regs(46)(3 downto 0);
type clist is array(15 downto 0) of byte;
constant vc_red : clist := (
0=>x"00", 1=>x"FF", 2=>x"a1", 3=>x"6a", 4=>x"a2", 5=>x"5c", 6=>x"50", 7=>x"cb",
8=>x"a3", 9=>x"6e", 10=>x"cc", 11=>x"63", 12=>x"8b", 13=>x"9b", 14=>x"8a", 15=>x"af"
);
constant vc_green : clist := (
0=>x"00", 1=>x"FF", 2=>x"4d", 3=>x"c1", 4=>x"57", 5=>x"ad", 6=>x"44", 7=>x"d6",
8=>x"68", 9=>x"53", 10=>x"7f", 11=>x"63", 12=>x"8b", 13=>x"e3", 14=>x"7f", 15=>x"af"
);
constant vc_blue : clist := (
0=>x"00", 1=>x"FF", 2=>x"43", 3=>x"c8", 4=>x"a5", 5=>x"5f", 6=>x"9c", 7=>x"89",
8=>x"3a", 9=>x"0b", 10=>x"76", 11=>x"63", 12=>x"8b", 13=>x"9d", 14=>x"cd", 15=>x"af"
);
function vcolor_r(color : nybble) return byte is
begin return vc_red(to_integer(unsigned(color))); end vcolor_r;
function vcolor_g(color : nybble) return byte is
begin return vc_green(to_integer(unsigned(color))); end vcolor_g;
function vcolor_b(color : nybble) return byte is
begin return vc_blue(to_integer(unsigned(color))); end vcolor_b;
function count3(org: slv3) return slv3 is
begin
case org is
when "000" => return "001";
when "001" => return "010";
when "010" => return "011";
when "011" => return "100";
when "100" => return "101";
when "101" => return "110";
when "110" => return "111";
when "111" => return "000";
when others => return "000";
end case;
end count3;
function clk20ph_count(org: u6) return u6 is
begin
case org is
when "000000" => return "000001";
when "000001" => return "000010";
when "000010" => return "000011";
when "000011" => return "000100";
when "000100" => return "000101";
when "000101" => return "000110";
when "000110" => return "000111";
when "000111" => return "001000";
when "001000" => return "001001";
when "001001" => return "010000";
when "010000" => return "010001";
when "010001" => return "010010";
when "010010" => return "010011";
when "010011" => return "010100";
when "010100" => return "010101";
when "010101" => return "010110";
when "010110" => return "010111";
when "010111" => return "011000";
when "011000" => return "011001";
when "011001" => return "100000";
when "100000" => return "100001";
when "100001" => return "100010";
when "100010" => return "100011";
when "100011" => return "100100";
when "100100" => return "100101";
when "100101" => return "100110";
when "100110" => return "100111";
when "100111" => return "101000";
when "101000" => return "101001";
when "101001" => return "110000";
when "110000" => return "110001";
when "110001" => return "110010";
when "110010" => return "110011";
when "110011" => return "110100";
when "110100" => return "110101";
when "110101" => return "110110";
when "110110" => return "110111";
when "110111" => return "111000";
when "111000" => return "111001";
when "111001" => return "000000";
when others => return "000000";
end case;
end clk20ph_count;
signal clk20_12 : std_logic;
signal clk20ph : u6 := "001001";
attribute fsm_encoding of clk20ph : signal is "sequential";
signal clk20stg : pair;
signal clk20tik : nybble := "0000";
signal cpuclk : std_logic;
signal ph0 : std_logic;
signal ph1 : std_logic;
signal ph2 : std_logic;
signal cpu_slice : std_logic;
signal vic_slice : std_logic;
signal rapos_V : u16 := "0000000000000000";
signal rapos_H : u16 := "0000000000000000";
signal vis_V : u16;
signal vis_H : u16;
signal win_V : u16;
signal win_H : u16;
signal regras_v : u9;
signal vbdr : std_logic;
signal hbdr : std_logic;
signal bdr : std_logic;
signal en_V : std_logic;
signal en_H : std_logic;
signal en : std_logic;
signal cell_h : ubyte;
signal cell_v : ubyte;
signal cell_ph : ubyte;
signal cell_pv : ubyte;
signal rg_o : byte;
signal rg_i : byte;
function d_to_slv(arg : long) return dword is
begin
return dword(arg);
end d_to_slv;
-- line pixel/color registers
subtype slin is std_logic_vector(23 downto 0);
subtype sptr_t is std_logic_vector(13 downto 0);
type cline is array(39 downto 0) of nybble;
type bline is array(39 downto 0) of byte;
type sptr is array(7 downto 0) of sptr_t;
type sdata is array(7 downto 0) of slin;
signal line_pix : std_logic_vector(319 downto 0) := (others => '0'); -- pixels
signal line_c : cline := (others => x"f"); -- color
signal line_b : bline := (others => x"ff"); -- block (character)
signal line_sprs : sdata := (others => x"000000"); -- sprites
signal spr_ptr : sptr := (others => "00000000000000");
function u8toi(src: ubyte) return integer is
begin
return to_integer(unsigned(src));
end u8toi;
function ratoi(src: slv6) return integer is
begin
return to_integer(unsigned(src));
end ratoi;
function pxtoi(src: slv9) return integer is
begin
return to_integer(unsigned(src));
end pxtoi;
function inc6(src: slv6) return slv6 is
variable conv : unsigned(5 downto 0);
begin
conv := unsigned(src) + 1;
return slv6(conv);
end inc6;
function cpu_read(cbus,cr1w0 : std_logic) return boolean is
begin
case cbus and cr1w0 is
when '1' => return true;
when others => return false;
end case;
end;
function cpu_write(cbus,cr1w0 : std_logic) return boolean is
begin
case cbus and (not cr1w0) is
when '1' => return true;
when others => return false;
end case;
end;
function reg_in_range(rega: slv6) return boolean is
begin
case rega is
when "000000" => return true;
when "000001" => return true;
when "000010" => return true;
when "000011" => return true;
when "000100" => return true;
when "000101" => return true;
when "000110" => return true;
when "000111" => return true;
when "001000" => return true;
when "001001" => return true;
when "001010" => return true;
when "001011" => return true;
when "001100" => return true;
when "001101" => return true;
when "001110" => return true;
when "001111" => return true;
when "010000" => return true;
when "010001" => return true;
when "010010" => return true;
when "010011" => return true;
when "010100" => return true;
when "010101" => return true;
when "010110" => return true;
when "010111" => return true;
when "011000" => return true;
when "011001" => return true;
when "011010" => return true;
when "011011" => return true;
when "011100" => return true;
when "011101" => return true;
when "011110" => return true;
when "011111" => return true;
when "100000" => return true;
when "100001" => return true;
when "100010" => return true;
when "100011" => return true;
when "100100" => return true;
when "100101" => return true;
when "100110" => return true;
when "100111" => return true;
when "101000" => return true;
when "101001" => return true;
when "101010" => return true;
when "101011" => return true;
when "101100" => return true;
when "101101" => return true;
when "101110" => return true;
when others => return false;
end case;
end reg_in_range;
type fstg_t is (
get_idle,
get_m_ptrs,
get_m_data,
get_c_ptrs,
get_c_data
);
signal fetch_stg : fstg_t := get_idle;
signal fetch_m : slv3 := "000";
signal fetch_n : slv6 := "000000";
signal fetch_p : u16;
--
-- "unused vic register bits yield 1 on reading"
--
impure function vic_regs_masked(reg: integer) return byte is
variable tbyt : byte;
begin
case reg is
when 0 => tbyt:= ( vic_regs( 0));
when 1 => tbyt:= ( vic_regs( 1));
when 2 => tbyt:= ( vic_regs( 2));
when 3 => tbyt:= ( vic_regs( 3));
when 4 => tbyt:= ( vic_regs( 4));
when 5 => tbyt:= ( vic_regs( 5));
when 6 => tbyt:= ( vic_regs( 6));
when 7 => tbyt:= ( vic_regs( 7));
when 8 => tbyt:= ( vic_regs( 8));
when 9 => tbyt:= ( vic_regs( 9));
when 10 => tbyt:= ( vic_regs(10));
when 11 => tbyt:= ( vic_regs(11));
when 12 => tbyt:= ( vic_regs(12));
when 13 => tbyt:= ( vic_regs(13));
when 14 => tbyt:= ( vic_regs(14));
when 15 => tbyt:= ( vic_regs(15));
when 16 => tbyt:= ( vic_regs(16));
when 17 => tbyt:= ( regras_v( 8) & vic_regs(17)(6 downto 0));
when 18 => tbyt:= ( byte(regras_v(7 downto 0)));
when 19 => tbyt:= ( vic_regs(19));
when 20 => tbyt:= ( vic_regs(20));
when 21 => tbyt:= ( vic_regs(21));
when 22 => tbyt:= ("11" & vic_regs(22)(5 downto 0));
when 23 => tbyt:= ( vic_regs(23));
when 24 => tbyt:= ( vic_regs(24)(7 downto 1) & '1');
when 25 => tbyt:= ( vic_regs(25)(7) & "111" & vic_regs(25)(3 downto 0));
when 26 => tbyt:= ("1111" & vic_regs(26)(3 downto 0));
when 27 => tbyt:= ( vic_regs(27));
when 28 => tbyt:= ( vic_regs(28));
when 29 => tbyt:= ( vic_regs(29));
when 30 => tbyt:= ( vic_regs(30));
when 31 => tbyt:= ( vic_regs(31));
when 32 => tbyt:= ("1111" & vic_regs(32)(3 downto 0));
when 33 => tbyt:= ("1111" & vic_regs(33)(3 downto 0));
when 34 => tbyt:= ("1111" & vic_regs(34)(3 downto 0));
when 35 => tbyt:= ("1111" & vic_regs(35)(3 downto 0));
when 36 => tbyt:= ("1111" & vic_regs(36)(3 downto 0));
when 37 => tbyt:= ("1111" & vic_regs(37)(3 downto 0));
when 38 => tbyt:= ("1111" & vic_regs(38)(3 downto 0));
when 39 => tbyt:= ("1111" & vic_regs(39)(3 downto 0));
when 40 => tbyt:= ("1111" & vic_regs(40)(3 downto 0));
when 41 => tbyt:= ("1111" & vic_regs(41)(3 downto 0));
when 42 => tbyt:= ("1111" & vic_regs(42)(3 downto 0));
when 43 => tbyt:= ("1111" & vic_regs(43)(3 downto 0));
when 44 => tbyt:= ("1111" & vic_regs(44)(3 downto 0));
when 45 => tbyt:= ("1111" & vic_regs(45)(3 downto 0));
when 46 => tbyt:= ("1111" & vic_regs(46)(3 downto 0));
when others => tbyt:= "11111111";
end case;
return tbyt;
end vic_regs_masked;
function valid_cell_x(xc : slv6) return boolean is
begin
case xc is
when "101000" => return false;
when "101001" => return false;
when "101010" => return false;
when "101011" => return false;
when "101100" => return false;
when "101101" => return false;
when "101110" => return false;
when "101111" => return false;
when "110000" => return false;
when "110001" => return false;
when "110010" => return false;
when "110011" => return false;
when "110100" => return false;
when "110101" => return false;
when "110110" => return false;
when "110111" => return false;
when "111000" => return false;
when "111001" => return false;
when "111010" => return false;
when "111011" => return false;
when "111100" => return false;
when "111101" => return false;
when "111110" => return false;
when "111111" => return false;
when others => return true;
end case;
end valid_cell_x;
begin
clock20ph: process(clk20_ph1,clk20_ph2,clk20ph,rapos_V,rapos_H,res0) is
variable raV : u16;
variable raH : u16;
begin
raV := rapos_V;
raH := rapos_H;
if (res0 = '0') then
--clk20ph <= "001001";
rapos_V <= "0000000000000000";
rapos_H <= "0000000000000000";
else
if (falling_edge(clk20_ph2)) then
--if (rising_edge(clk20_ph2)) then
--clk20ph <= clk20ph_count(clk20ph);
raV := rapos_V;
raH := raH + 1;
if (raH >= 528) then
raH := "0000000000000000";
raV := raV + 1;
if (raV >= 628) then
raV := "0000000000000000";
end if;
end if;
rapos_V <= raV;
rapos_H <= raH;
end if;
--if (falling_edge(clk20_ph1)) then
--if (rising_edge(clk20_ph1)) then
--clk20ph <= clk20ph_count(clk20ph);
--end if;
end if;
end process clock20ph;
clk20_12 <= clk20_ph1 or clk20_ph2;
cpu_clkcnt: process(clk20_12,clk20ph) is
begin
if (res0 = '0') then
clk20ph <= "001001";
elsif (falling_edge(clk20_12)) then
clk20ph <= clk20ph_count(clk20ph);
end if;
end process cpu_clkcnt;
cpu_clocks: process(clk20_ph1,clk20_ph2,clk20ph) is
variable sigs : nybble;
begin
case clk20ph is
when "110001" => sigs := "1110";
when "110010" => sigs := "1000";
when "110011" => sigs := "1100";
when "110100" => sigs := "1000";
when "110101" => sigs := "0101";
when "110110" => sigs := "0000";
when "110111" => sigs := "0100";
when "111000" => sigs := "0000";
when others => sigs := "0000";
end case;
if (rising_edge(clk20_ph1) or rising_edge(clk20_ph2)) then
ph0 <= sigs(3);
cpuclk <= sigs(2);
ph1 <= sigs(1);
ph2 <= sigs(0);
--case clk20ph is
-- when "110001" => cpuclk <= '1';
-- when "110011" => cpuclk <= '1';
-- when "110101" => cpuclk <= '1';
-- when "110111" => cpuclk <= '1';
-- when others => cpuclk <= '0';
--end case;
--case clk20ph is
-- when "110001" => ph0 <= '1';
-- when "110010" => ph0 <= '1';
-- when "110011" => ph0 <= '1';
-- when "110100" => ph0 <= '1';
-- when others => ph0 <= '0';
--end case;
--case clk20ph is
-- when "110001" => ph1 <= '1';
-- when others => ph1 <= '0';
--end case;
--case clk20ph is
-- when "110101" => ph2 <= '1';
-- when others => ph2 <= '0';
--end case;
end if;
end process cpu_clocks;
cpu_clk <= cpuclk;
bus_ph0 <= ph0;
bus_ph1 <= ph1;
bus_ph2 <= ph2;
clk20stg <= pair(clk20ph(5 downto 4));
cpu_slice <= clk20stg(1) and clk20stg(0); -- when 1 it's CPU's turn on bus
vic_slice <= clk20stg(1) nand clk20stg(0); -- when 1 it's VIC's turn on bus
cpu_ben <= cpu_slice;
vic_ben <= vic_slice;
poscalc: process(clk20_ph2, rapos_V, rapos_H) is
begin
vis_V <= rapos_V - 5;
--win_V <= rapos_V - 105;
case vic_YSCROLL is
when "000" => win_V <= rapos_V - 99;
when "001" => win_V <= rapos_V - 101;
when "010" => win_V <= rapos_V - 103;
when "011" => win_V <= rapos_V - 105;
when "100" => win_V <= rapos_V - 107;
when "101" => win_V <= rapos_V - 109;
when "110" => win_V <= rapos_V - 111;
when others => win_V <= rapos_V - 113;
end case;
vis_H <= rapos_H - 84;
--win_H <= rapos_H - 124;
case vic_XSCROLL is
when "000" => win_H <= rapos_H - 125;
when "001" => win_H <= rapos_H - 126;
when "010" => win_H <= rapos_H - 127;
when "011" => win_H <= rapos_H - 128;
when "100" => win_H <= rapos_H - 129;
when "101" => win_H <= rapos_H - 130;
when "110" => win_H <= rapos_H - 131;
when others => win_H <= rapos_H - 132;
end case;
end process poscalc;
calc_rg_raster: process(clk20_ph1,clk20_ph2,vis_V) is
-- calculate the raster for the system to read
begin
if rising_edge(clk20_ph1) or rising_edge(clk20_ph2) then
if (vis_V <= x"03ff") then
regras_v <= vis_v(9 downto 1);
end if;
end if;
end process calc_rg_raster;
cell_H <= ubyte(win_H(10 downto 3));
cell_V <= ubyte(win_V(11 downto 4)); -- ignoring bit 0 (so odd lines repeat the even lines)
cell_PH <= ubyte("00000" & win_H(2 downto 0));
cell_PV <= ubyte("00000" & win_V(3 downto 1)); -- ignoring bit 0 (so odd lines repeat the even lines)
hb_calc: process(clk20_ph2, rapos_H, vic_CSEL) is
begin
if (falling_edge(clk20_ph2)) then
if (vic_CSEL='1' and ((rapos_H < 124) or (rapos_H > 443))) then
hbdr <= '1';
elsif (vic_CSEL='0' and ((rapos_H < 131) or (rapos_H > 434))) then
hbdr <= '1';
else
hbdr <= '0';
end if;
end if;
end process hb_calc;
vb_calc: process(clk20_ph2, rapos_V, vic_RSEL) is
begin
if (falling_edge(clk20_ph2)) then
if (vic_RSEL='1' and ((rapos_V < 105) or (rapos_V > 504))) then
vbdr <= '1';
elsif (vic_RSEL='0' and ((rapos_V < 113) or (rapos_V > 496))) then
vbdr <= '1';
else
vbdr <= '0';
end if;
end if;
end process vb_calc;
eh_calc: process(clk20_ph2, rapos_H) is
begin
if (falling_edge(clk20_ph2)) then
if ((rapos_H < 84) or (rapos_H > 483)) then
en_H <= '0';
else
en_H <= '1';
end if;
end if;
end process eh_calc;
ev_calc: process(clk20_ph2, rapos_V) is
begin
if (falling_edge(clk20_ph2)) then
if ((rapos_V < 5) or (rapos_V > 604)) then
en_V <= '0';
else
en_V <= '1';
end if;
end if;
end process ev_calc;
bdr <= vbdr or hbdr;
en <= en_V and en_H;
hsync: process(rapos_H) is
begin
if (rapos_H < 64) then
vhs <= '1';
else
vhs <= '0';
end if;
end process hsync;
vsync: process(rapos_V) is
begin
if (rapos_V < 4) then
vvs <= '1';
else
vvs <= '0';
end if;
end process vsync;
rgdo <= rg_o;
rg_i <= rgdi;
vreg_rd: process(ph2,cpu_slice,rga,vic_regs,r1w0) is
begin
if (rising_edge(ph2)) then
if (cpu_read(cpu_slice,r1w0)) then
-- reading register
if (reg_in_range(rga)) then
--rg_o <= vic_regs(ratoi(rga));
rg_o <= vic_regs_masked(ratoi(rga));
else
rg_o <= x"FF";
end if;
end if;
end if;
end process vreg_rd;
vreg_wr: process(ph2,cpu_slice,rga,r1w0,rg_i) is
begin
if (falling_edge(ph2)) then
if (cpu_write(cpu_slice,r1w0) and reg_in_range(rga)) then
-- writing register
vic_regs(ratoi(rga)) <= rg_i;
end if;
end if;
end process vreg_wr;
fetching: process(clk20_ph1,clk20_ph2,vic_slice,fetch_stg,fetch_m,cell_PV,cd,vd,
win_v,res0,rapos_H,fetch_n,fetch_p,vic_VM,vic_CB,line_c,line_b) is
variable cur_stg : fstg_t;
variable cur_n : slv6;
begin
if (res0 = '0') then
fetch_stg <= get_idle;
else
if (vic_slice='1') then
if (rising_edge(clk20_ph1)) then
case fetch_stg is
when get_idle =>
va <= "11111111111111";
when get_m_ptrs =>
va <= vic_VM & c_addr(fetch_p(9 downto 0));
when get_m_data =>
va <= vic_CB & line_b(ratoi(fetch_n)) & slv3(cell_PV(2 downto 0));
when others =>
null;
end case;
end if;
if (falling_edge(clk20_ph2)) then
cur_stg := fetch_stg;
cur_n := fetch_n;
case cur_stg is
when get_idle =>
if (rapos_H < x"0018" and win_V < x"8000") then
if (win_V(3 downto 0) = "0000") then
fetch_stg <= get_m_ptrs;
fetch_m <= "000";
fetch_n <= "000000";
fetch_p <= (cell_V*40);
else
fetch_stg <= get_m_data;
fetch_m <= "000";
fetch_n <= "000000";
end if;
end if;
when get_m_ptrs =>
line_c(ratoi(cur_n)) <= cd;
line_b(ratoi(cur_n)) <= vd;
if (cur_n < "100111") then
fetch_n <= inc6(cur_n);
fetch_p <= fetch_p + 1;
else
fetch_n <= "000000";
fetch_stg <= get_m_data;
end if;
when get_m_data =>
line_pix(pxtoi(fetch_n & "000")) <= vd(0);
line_pix(pxtoi(fetch_n & "001")) <= vd(1);
line_pix(pxtoi(fetch_n & "010")) <= vd(2);
line_pix(pxtoi(fetch_n & "011")) <= vd(3);
line_pix(pxtoi(fetch_n & "100")) <= vd(4);
line_pix(pxtoi(fetch_n & "101")) <= vd(5);
line_pix(pxtoi(fetch_n & "110")) <= vd(6);
line_pix(pxtoi(fetch_n & "111")) <= vd(7);
if (fetch_n < "100111") then
fetch_n <= inc6(fetch_n);
else
fetch_n <= "000000";
fetch_stg <= get_idle;
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process fetching;
pixgen: process(en,bdr,vic_EC,win_H,cell_H,vic_B0C,clk20_ph1) is
variable cur_px_pos : slv9;
variable cur_cell_x : slv6;
begin
cur_px_pos := "000000000";
cur_cell_x := slv6(win_H(8 downto 3));
if (rising_edge(clk20_ph1)) then
if (en = '1') then
if (bdr = '1') then
vr <= vcolor_r(vic_EC)(7 downto 3);
vg <= vcolor_g(vic_EC)(7 downto 2);
vb <= vcolor_b(vic_EC)(7 downto 3);
else
cur_px_pos(8 downto 3) := cur_cell_x;
cur_px_pos(2 downto 0) := "111" xor slv3(win_H(2 downto 0));
if (not valid_cell_x(cur_cell_x)) then
vr <= vcolor_r(vic_B0C)(7 downto 3);
vg <= vcolor_g(vic_B0C)(7 downto 2);
vb <= vcolor_b(vic_B0C)(7 downto 3);
--vr <= vcolor_r(x"2")(7 downto 3); -- debug to catch out-of-range columns
--vg <= vcolor_g(x"2")(7 downto 2);
--vb <= vcolor_b(x"2")(7 downto 3);
elsif (line_pix(to_integer(unsigned(cur_px_pos))) = '1') then
vr <= vcolor_r(line_c(u8toi(cell_H)))(7 downto 3);
vg <= vcolor_g(line_c(u8toi(cell_H)))(7 downto 2);
vb <= vcolor_b(line_c(u8toi(cell_H)))(7 downto 3);
else
vr <= vcolor_r(vic_B0C)(7 downto 3);
vg <= vcolor_g(vic_B0C)(7 downto 2);
vb <= vcolor_b(vic_B0C)(7 downto 3);
end if;
end if;
else
vr <= "00000";
vg <= "000000";
vb <= "00000";
end if;
end if;
end process pixgen;
end vic_ii_impl;
|
gpl-3.0
|
gau-veldt/InsideTheBox
|
Progress_2017_12_08/vic_ii.vhd
|
2
|
28875
|
----------------------------------------------------------------------------------
--
-- VIC II simulator
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vic_ii is
port (
-- register access
rga : in std_logic_vector(5 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
-- video access
va : out std_logic_vector(13 downto 0);
vd : in std_logic_vector(7 downto 0);
cd : in std_logic_vector(3 downto 0);
-- bus mastering
cpu_clk : out std_logic; -- 4 MHz CPU clock
cpu_ben : out std_logic; -- 1=CPU on buses
vic_ben : out std_logic; -- 1=VIC on buses
bus_ph0 : out std_logic; -- master PH0 clock
bus_ph1 : out std_logic; -- master PH1 clock
bus_ph2 : out std_logic; -- master PH2 clock
res0 : in std_logic; -- reset (low)
-- external signals
clk20_ph1 : in std_logic;
clk20_ph2 : in std_logic;
vhs : out std_logic;
vvs : out std_logic;
vr : out std_logic_vector(4 downto 0);
vg : out std_logic_vector(5 downto 0);
vb : out std_logic_vector(4 downto 0)
);
end vic_ii;
architecture vic_ii_impl of vic_ii is
attribute ram_style : string;
attribute gated_clock : string;
--attribute gated_clock of clk20_ph1 : signal is "true";
--attribute gated_clock of clk20_ph2 : signal is "true";
subtype sl is std_logic;
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv6 is std_logic_vector(5 downto 0);
subtype u6 is unsigned(5 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype slv9 is std_logic_vector(8 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype cgptr is std_logic_vector(11 downto 0);
subtype dword is std_logic_vector(31 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype long is unsigned(31 downto 0);
subtype v_addr is std_logic_vector(13 downto 0);
subtype c_addr is std_logic_vector(9 downto 0);
subtype r_addr is std_logic_vector(5 downto 0);
type vregs is array(46 downto 0) of byte;
signal vic_regs : vregs;
attribute ram_style of vic_regs : signal is "registers";
alias vic_M0X : byte is vic_regs( 0);
alias vic_M0X8 : sl is vic_regs(16)(0);
alias vic_M1X : byte is vic_regs( 1);
alias vic_M1X8 : sl is vic_regs(16)(1);
alias vic_M2X : byte is vic_regs( 2);
alias vic_M2X8 : sl is vic_regs(16)(2);
alias vic_M3X : byte is vic_regs( 3);
alias vic_M3X8 : sl is vic_regs(16)(3);
alias vic_M4X : byte is vic_regs( 4);
alias vic_M4X8 : sl is vic_regs(16)(4);
alias vic_M5X : byte is vic_regs( 5);
alias vic_M5X8 : sl is vic_regs(16)(5);
alias vic_M6X : byte is vic_regs( 6);
alias vic_M6X8 : sl is vic_regs(16)(6);
alias vic_M7X : byte is vic_regs( 7);
alias vic_M7X8 : sl is vic_regs(16)(7);
alias vic_M0Y : byte is vic_regs( 8);
alias vic_M1Y : byte is vic_regs( 9);
alias vic_M2Y : byte is vic_regs(10);
alias vic_M3Y : byte is vic_regs(11);
alias vic_M4Y : byte is vic_regs(12);
alias vic_M5Y : byte is vic_regs(13);
alias vic_M6Y : byte is vic_regs(14);
alias vic_M7Y : byte is vic_regs(15);
alias vic_YSCROLL : slv3 is vic_regs(17)(2 downto 0);
alias vic_RSEL : sl is vic_regs(17)(3);
alias vic_DEN : sl is vic_regs(17)(4);
alias vic_BMM : sl is vic_regs(17)(5);
alias vic_ECM : sl is vic_regs(17)(6);
alias vic_RST8 : sl is vic_regs(17)(7);
alias vic_RASTER : byte is vic_regs(18);
alias vic_LPX : byte is vic_regs(19);
alias vic_LPY : byte is vic_regs(20);
alias vic_M0E : sl is vic_regs(21)(0);
alias vic_M1E : sl is vic_regs(21)(1);
alias vic_M2E : sl is vic_regs(21)(2);
alias vic_M3E : sl is vic_regs(21)(3);
alias vic_M4E : sl is vic_regs(21)(4);
alias vic_M5E : sl is vic_regs(21)(5);
alias vic_M6E : sl is vic_regs(21)(6);
alias vic_M7E : sl is vic_regs(21)(7);
alias vic_XSCROLL : slv3 is vic_regs(22)(2 downto 0);
alias vic_CSEL : sl is vic_regs(22)(3);
alias vic_MCM : sl is vic_regs(22)(4);
alias vic_RES : sl is vic_regs(22)(5);
alias vic_M0YE : sl is vic_regs(23)(0);
alias vic_M1YE : sl is vic_regs(23)(1);
alias vic_M2YE : sl is vic_regs(23)(2);
alias vic_M3YE : sl is vic_regs(23)(3);
alias vic_M4YE : sl is vic_regs(23)(4);
alias vic_M5YE : sl is vic_regs(23)(5);
alias vic_M6YE : sl is vic_regs(23)(6);
alias vic_M7YE : sl is vic_regs(23)(7);
alias vic_CB : slv3 is vic_regs(24)(3 downto 1);
alias vic_VM : nybble is vic_regs(24)(7 downto 4);
alias vic_IRQ : sl is vic_regs(25)(7);
alias vic_ILP : sl is vic_regs(25)(3);
alias vic_IMMC : sl is vic_regs(25)(2);
alias vic_IMBC : sl is vic_regs(25)(1);
alias vic_IRST : sl is vic_regs(25)(0);
alias vic_ELP : sl is vic_regs(26)(3);
alias vic_EMMC : sl is vic_regs(26)(2);
alias vic_EMBC : sl is vic_regs(26)(1);
alias vic_ERST : sl is vic_regs(26)(0);
alias vic_M0DP : sl is vic_regs(27)(0);
alias vic_M1DP : sl is vic_regs(27)(1);
alias vic_M2DP : sl is vic_regs(27)(2);
alias vic_M3DP : sl is vic_regs(27)(3);
alias vic_M4DP : sl is vic_regs(27)(4);
alias vic_M5DP : sl is vic_regs(27)(5);
alias vic_M6DP : sl is vic_regs(27)(6);
alias vic_M7DP : sl is vic_regs(27)(7);
alias vic_M0MC : sl is vic_regs(28)(0);
alias vic_M1MC : sl is vic_regs(28)(1);
alias vic_M2MC : sl is vic_regs(28)(2);
alias vic_M3MC : sl is vic_regs(28)(3);
alias vic_M4MC : sl is vic_regs(28)(4);
alias vic_M5MC : sl is vic_regs(28)(5);
alias vic_M6MC : sl is vic_regs(28)(6);
alias vic_M7MC : sl is vic_regs(28)(7);
alias vic_M0XE : sl is vic_regs(29)(0);
alias vic_M1XE : sl is vic_regs(29)(1);
alias vic_M2XE : sl is vic_regs(29)(2);
alias vic_M3XE : sl is vic_regs(29)(3);
alias vic_M4XE : sl is vic_regs(29)(4);
alias vic_M5XE : sl is vic_regs(29)(5);
alias vic_M6XE : sl is vic_regs(29)(6);
alias vic_M7XE : sl is vic_regs(29)(7);
alias vic_M0M : sl is vic_regs(30)(0);
alias vic_M1M : sl is vic_regs(30)(1);
alias vic_M2M : sl is vic_regs(30)(2);
alias vic_M3M : sl is vic_regs(30)(3);
alias vic_M4M : sl is vic_regs(30)(4);
alias vic_M5M : sl is vic_regs(30)(5);
alias vic_M6M : sl is vic_regs(30)(6);
alias vic_M7M : sl is vic_regs(30)(7);
alias vic_M0D : sl is vic_regs(31)(0);
alias vic_M1D : sl is vic_regs(31)(1);
alias vic_M2D : sl is vic_regs(31)(2);
alias vic_M3D : sl is vic_regs(31)(3);
alias vic_M4D : sl is vic_regs(31)(4);
alias vic_M5D : sl is vic_regs(31)(5);
alias vic_M6D : sl is vic_regs(31)(6);
alias vic_M7D : sl is vic_regs(31)(7);
alias vic_EC : nybble is vic_regs(32)(3 downto 0);
alias vic_B0C : nybble is vic_regs(33)(3 downto 0);
alias vic_B1C : nybble is vic_regs(34)(3 downto 0);
alias vic_B2C : nybble is vic_regs(35)(3 downto 0);
alias vic_B3C : nybble is vic_regs(36)(3 downto 0);
alias vic_MM0 : nybble is vic_regs(37)(3 downto 0);
alias vic_MM1 : nybble is vic_regs(38)(3 downto 0);
alias vic_M0C : nybble is vic_regs(39)(3 downto 0);
alias vic_M1C : nybble is vic_regs(40)(3 downto 0);
alias vic_M2C : nybble is vic_regs(41)(3 downto 0);
alias vic_M3C : nybble is vic_regs(42)(3 downto 0);
alias vic_M4C : nybble is vic_regs(43)(3 downto 0);
alias vic_M5C : nybble is vic_regs(44)(3 downto 0);
alias vic_M6C : nybble is vic_regs(45)(3 downto 0);
alias vic_M7C : nybble is vic_regs(46)(3 downto 0);
type clist is array(15 downto 0) of byte;
constant vc_red : clist := (
0=>x"00", 1=>x"FF", 2=>x"a1", 3=>x"6a", 4=>x"a2", 5=>x"5c", 6=>x"50", 7=>x"cb",
8=>x"a3", 9=>x"6e", 10=>x"cc", 11=>x"63", 12=>x"8b", 13=>x"9b", 14=>x"8a", 15=>x"af"
);
constant vc_green : clist := (
0=>x"00", 1=>x"FF", 2=>x"4d", 3=>x"c1", 4=>x"57", 5=>x"ad", 6=>x"44", 7=>x"d6",
8=>x"68", 9=>x"53", 10=>x"7f", 11=>x"63", 12=>x"8b", 13=>x"e3", 14=>x"7f", 15=>x"af"
);
constant vc_blue : clist := (
0=>x"00", 1=>x"FF", 2=>x"43", 3=>x"c8", 4=>x"a5", 5=>x"5f", 6=>x"9c", 7=>x"89",
8=>x"3a", 9=>x"0b", 10=>x"76", 11=>x"63", 12=>x"8b", 13=>x"9d", 14=>x"cd", 15=>x"af"
);
function vcolor_r(color : nybble) return byte is
begin return vc_red(to_integer(unsigned(color))); end vcolor_r;
function vcolor_g(color : nybble) return byte is
begin return vc_green(to_integer(unsigned(color))); end vcolor_g;
function vcolor_b(color : nybble) return byte is
begin return vc_blue(to_integer(unsigned(color))); end vcolor_b;
function count3(org: slv3) return slv3 is
begin
case org is
when "000" => return "001";
when "001" => return "010";
when "010" => return "011";
when "011" => return "100";
when "100" => return "101";
when "101" => return "110";
when "110" => return "111";
when "111" => return "000";
when others => return "000";
end case;
end count3;
function clk20ph_count(org: u6) return u6 is
begin
case org is
when "000000" => return "000001";
when "000001" => return "000010";
when "000010" => return "000011";
when "000011" => return "000100";
when "000100" => return "000101";
when "000101" => return "000110";
when "000110" => return "000111";
when "000111" => return "001000";
when "001000" => return "001001";
when "001001" => return "010000";
when "010000" => return "010001";
when "010001" => return "010010";
when "010010" => return "010011";
when "010011" => return "010100";
when "010100" => return "010101";
when "010101" => return "010110";
when "010110" => return "010111";
when "010111" => return "011000";
when "011000" => return "011001";
when "011001" => return "100000";
when "100000" => return "100001";
when "100001" => return "100010";
when "100010" => return "100011";
when "100011" => return "100100";
when "100100" => return "100101";
when "100101" => return "100110";
when "100110" => return "100111";
when "100111" => return "101000";
when "101000" => return "101001";
when "101001" => return "110000";
when "110000" => return "110001";
when "110001" => return "110010";
when "110010" => return "110011";
when "110011" => return "110100";
when "110100" => return "110101";
when "110101" => return "110110";
when "110110" => return "110111";
when "110111" => return "111000";
when "111000" => return "111001";
when "111001" => return "000000";
when others => return "000000";
end case;
end clk20ph_count;
signal clk20ph : u6 := "001001";
signal clk20stg : pair;
signal clk20tik : nybble := "0000";
signal cpuclk : std_logic;
signal ph0 : std_logic;
signal ph1 : std_logic;
signal ph2 : std_logic;
signal cpu_slice : std_logic;
signal vic_slice : std_logic;
signal rapos_V : u16 := "0000000000000000";
signal rapos_H : u16 := "0000000000000000";
signal vis_V : u16;
signal vis_H : u16;
signal win_V : u16;
signal win_H : u16;
signal vbdr : std_logic;
signal hbdr : std_logic;
signal bdr : std_logic;
signal en_V : std_logic;
signal en_H : std_logic;
signal en : std_logic;
signal cell_h : ubyte;
signal cell_v : ubyte;
signal cell_ph : ubyte;
signal cell_pv : ubyte;
signal rg_o : byte;
signal rg_i : byte;
function d_to_slv(arg : long) return dword is
begin
return dword(arg);
end d_to_slv;
-- line pixel/color registers
subtype slin is std_logic_vector(23 downto 0);
subtype sptr_t is std_logic_vector(13 downto 0);
type cline is array(39 downto 0) of nybble;
type bline is array(39 downto 0) of byte;
type sptr is array(7 downto 0) of sptr_t;
type sdata is array(7 downto 0) of slin;
signal line_pix : std_logic_vector(319 downto 0) := (others => '0'); -- pixels
signal line_c : cline := (others => x"f"); -- color
signal line_b : bline := (others => x"ff"); -- block (character)
signal line_sprs : sdata := (others => x"000000"); -- sprites
signal spr_ptr : sptr := (others => "00000000000000");
function u8toi(src: ubyte) return integer is
begin
return to_integer(unsigned(src));
end u8toi;
function ratoi(src: slv6) return integer is
begin
return to_integer(unsigned(src));
end ratoi;
function pxtoi(src: slv9) return integer is
begin
return to_integer(unsigned(src));
end pxtoi;
function inc6(src: slv6) return slv6 is
variable conv : unsigned(5 downto 0);
begin
conv := unsigned(src) + 1;
return slv6(conv);
end inc6;
function cpu_read(cbus,cr1w0 : std_logic) return boolean is
begin
case cbus and cr1w0 is
when '1' => return true;
when others => return false;
end case;
end;
function cpu_write(cbus,cr1w0 : std_logic) return boolean is
begin
case cbus and (not cr1w0) is
when '1' => return true;
when others => return false;
end case;
end;
function reg_in_range(rega: slv6) return boolean is
begin
case rega is
when "000000" => return true;
when "000001" => return true;
when "000010" => return true;
when "000011" => return true;
when "000100" => return true;
when "000101" => return true;
when "000110" => return true;
when "000111" => return true;
when "001000" => return true;
when "001001" => return true;
when "001010" => return true;
when "001011" => return true;
when "001100" => return true;
when "001101" => return true;
when "001110" => return true;
when "001111" => return true;
when "010000" => return true;
when "010001" => return true;
when "010010" => return true;
when "010011" => return true;
when "010100" => return true;
when "010101" => return true;
when "010110" => return true;
when "010111" => return true;
when "011000" => return true;
when "011001" => return true;
when "011010" => return true;
when "011011" => return true;
when "011100" => return true;
when "011101" => return true;
when "011110" => return true;
when "011111" => return true;
when "100000" => return true;
when "100001" => return true;
when "100010" => return true;
when "100011" => return true;
when "100100" => return true;
when "100101" => return true;
when "100110" => return true;
when "100111" => return true;
when "101000" => return true;
when "101001" => return true;
when "101010" => return true;
when "101011" => return true;
when "101100" => return true;
when "101101" => return true;
when "101110" => return true;
when others => return false;
end case;
end reg_in_range;
type fstg_t is (
get_idle,
get_m_ptrs,
get_m_data,
get_c_ptrs,
get_c_data
);
signal fetch_stg : fstg_t := get_idle;
signal fetch_m : slv3 := "000";
signal fetch_n : slv6 := "000000";
signal fetch_p : u16;
--
-- "unused vic register bits yield 1 on reading"
--
impure function vic_regs_masked(reg: integer) return byte is
begin
case reg is
when 22 => return ("11" & vic_regs(reg)(5 downto 0));
when 24 => return (vic_regs(reg)(7 downto 1) & '1');
when 25 => return (vic_regs(reg)(7) & "111" & vic_regs(reg)(3 downto 0));
when 26 => return ("1111" & vic_regs(reg)(3 downto 0));
when 32 => return ("1111" & vic_regs(reg)(3 downto 0));
when 33 => return ("1111" & vic_regs(reg)(3 downto 0));
when 34 => return ("1111" & vic_regs(reg)(3 downto 0));
when 35 => return ("1111" & vic_regs(reg)(3 downto 0));
when 36 => return ("1111" & vic_regs(reg)(3 downto 0));
when 37 => return ("1111" & vic_regs(reg)(3 downto 0));
when 38 => return ("1111" & vic_regs(reg)(3 downto 0));
when 39 => return ("1111" & vic_regs(reg)(3 downto 0));
when 40 => return ("1111" & vic_regs(reg)(3 downto 0));
when 41 => return ("1111" & vic_regs(reg)(3 downto 0));
when 42 => return ("1111" & vic_regs(reg)(3 downto 0));
when 43 => return ("1111" & vic_regs(reg)(3 downto 0));
when 44 => return ("1111" & vic_regs(reg)(3 downto 0));
when 45 => return ("1111" & vic_regs(reg)(3 downto 0));
when 46 => return ("1111" & vic_regs(reg)(3 downto 0));
when others => return vic_regs(reg);
end case;
end vic_regs_masked;
begin
clock20ph: process(clk20_ph1,clk20_ph2,clk20ph,rapos_V,rapos_H,res0) is
variable raV : u16;
variable raH : u16;
begin
raV := rapos_V;
raH := rapos_H;
if (res0 = '0') then
clk20ph <= "001001";
rapos_V <= "0000000000000000";
rapos_H <= "0000000000000000";
else
if (falling_edge(clk20_ph2)) then
--if (rising_edge(clk20_ph2)) then
clk20ph <= clk20ph_count(clk20ph);
raV := rapos_V;
raH := raH + 1;
if (raH >= 528) then
raH := "0000000000000000";
raV := raV + 1;
if (raV >= 628) then
raV := "0000000000000000";
end if;
end if;
rapos_V <= raV;
rapos_H <= raH;
end if;
if (falling_edge(clk20_ph1)) then
--if (rising_edge(clk20_ph1)) then
clk20ph <= clk20ph_count(clk20ph);
end if;
end if;
end process clock20ph;
cpu_clocks: process(clk20_ph1,clk20_ph2,clk20ph) is
begin
if (rising_edge(clk20_ph1) or rising_edge(clk20_ph2)) then
case clk20ph is
when "110001" => cpuclk <= '1';
when "110011" => cpuclk <= '1';
when "110101" => cpuclk <= '1';
when "110111" => cpuclk <= '1';
when others => cpuclk <= '0';
end case;
case clk20ph is
when "110001" => ph0 <= '1';
when "110010" => ph0 <= '1';
when "110011" => ph0 <= '1';
when "110100" => ph0 <= '1';
when others => ph0 <= '0';
end case;
case clk20ph is
when "110001" => ph1 <= '1';
when others => ph1 <= '0';
end case;
case clk20ph is
when "110101" => ph2 <= '1';
when others => ph2 <= '0';
end case;
end if;
end process cpu_clocks;
cpu_clk <= cpuclk;
bus_ph0 <= ph0;
bus_ph1 <= ph1;
bus_ph2 <= ph2;
clk20stg <= pair(clk20ph(5 downto 4));
cpu_slice <= clk20stg(1) and clk20stg(0); -- when 1 it's CPU's turn on bus
vic_slice <= clk20stg(1) nand clk20stg(0); -- when 1 it's VIC's turn on bus
cpu_ben <= cpu_slice;
vic_ben <= vic_slice;
poscalc: process(clk20_ph2, rapos_V, rapos_H) is
begin
vis_V <= rapos_V - 5;
--win_V <= rapos_V - 105;
case vic_YSCROLL is
when "000" => win_V <= rapos_V - 99;
when "001" => win_V <= rapos_V - 101;
when "010" => win_V <= rapos_V - 103;
when "011" => win_V <= rapos_V - 105;
when "100" => win_V <= rapos_V - 107;
when "101" => win_V <= rapos_V - 109;
when "110" => win_V <= rapos_V - 111;
when others => win_V <= rapos_V - 113;
end case;
vis_H <= rapos_H - 84;
--win_H <= rapos_H - 124;
case vic_XSCROLL is
when "000" => win_H <= rapos_H - 125;
when "001" => win_H <= rapos_H - 126;
when "010" => win_H <= rapos_H - 127;
when "011" => win_H <= rapos_H - 128;
when "100" => win_H <= rapos_H - 129;
when "101" => win_H <= rapos_H - 130;
when "110" => win_H <= rapos_H - 131;
when others => win_H <= rapos_H - 132;
end case;
end process poscalc;
cell_H <= ubyte(win_H(10 downto 3));
cell_V <= ubyte(win_V(11 downto 4)); -- ignoring bit 0 (so odd lines repeat the even lines)
cell_PH <= ubyte("00000" & win_H(2 downto 0));
cell_PV <= ubyte("00000" & win_V(3 downto 1)); -- ignoring bit 0 (so odd lines repeat the even lines)
hb_calc: process(clk20_ph2, rapos_H, vic_CSEL) is
begin
if (falling_edge(clk20_ph2)) then
if (vic_CSEL='1' and ((rapos_H < 124) or (rapos_H > 443))) then
hbdr <= '1';
elsif (vic_CSEL='0' and ((rapos_H < 131) or (rapos_H > 434))) then
hbdr <= '1';
else
hbdr <= '0';
end if;
end if;
end process hb_calc;
vb_calc: process(clk20_ph2, rapos_V, vic_RSEL) is
begin
if (falling_edge(clk20_ph2)) then
if (vic_RSEL='1' and ((rapos_V < 105) or (rapos_V > 504))) then
vbdr <= '1';
elsif (vic_RSEL='0' and ((rapos_V < 113) or (rapos_V > 496))) then
vbdr <= '1';
else
vbdr <= '0';
end if;
end if;
end process vb_calc;
eh_calc: process(clk20_ph2, rapos_H) is
begin
if (falling_edge(clk20_ph2)) then
if ((rapos_H < 84) or (rapos_H > 483)) then
en_H <= '0';
else
en_H <= '1';
end if;
end if;
end process eh_calc;
ev_calc: process(clk20_ph2, rapos_V) is
begin
if (falling_edge(clk20_ph2)) then
if ((rapos_V < 5) or (rapos_V > 604)) then
en_V <= '0';
else
en_V <= '1';
end if;
end if;
end process ev_calc;
bdr <= vbdr or hbdr;
en <= en_V and en_H;
hsync: process(rapos_H) is
begin
if (rapos_H < 64) then
vhs <= '1';
else
vhs <= '0';
end if;
end process hsync;
vsync: process(rapos_V) is
begin
if (rapos_V < 4) then
vvs <= '1';
else
vvs <= '0';
end if;
end process vsync;
rgdo <= rg_o;
rg_i <= rgdi;
vreg_rd: process(ph2,cpu_slice,rga,vic_regs,r1w0) is
begin
if (rising_edge(ph2)) then
if (cpu_read(cpu_slice,r1w0)) then
-- reading register
if (reg_in_range(rga)) then
--rg_o <= vic_regs(ratoi(rga));
rg_o <= vic_regs_masked(ratoi(rga));
else
rg_o <= x"FF";
end if;
end if;
end if;
end process vreg_rd;
vreg_wr: process(ph2,cpu_slice,rga,r1w0,rg_i) is
begin
if (falling_edge(ph2)) then
if (cpu_write(cpu_slice,r1w0) and reg_in_range(rga)) then
-- writing register
vic_regs(ratoi(rga)) <= rg_i;
end if;
end if;
end process vreg_wr;
fetching: process(clk20_ph1,clk20_ph2,vic_slice,fetch_stg,fetch_m,cell_PV,cd,vd,
win_v,res0,rapos_H,fetch_n,fetch_p,vic_VM,vic_CB,line_c,line_b) is
variable cur_stg : fstg_t;
variable cur_n : slv6;
begin
if (res0 = '0') then
fetch_stg <= get_idle;
else
if (vic_slice='1') then
if (rising_edge(clk20_ph1)) then
case fetch_stg is
when get_idle =>
va <= "11111111111111";
when get_m_ptrs =>
va <= vic_VM & c_addr(fetch_p(9 downto 0));
when get_m_data =>
va <= vic_CB & line_b(ratoi(fetch_n)) & slv3(cell_PV(2 downto 0));
when others =>
null;
end case;
end if;
if (falling_edge(clk20_ph2)) then
cur_stg := fetch_stg;
cur_n := fetch_n;
case cur_stg is
when get_idle =>
if (rapos_H < x"0018" and win_V < x"8000") then
if (win_V(3 downto 0) = "0000") then
fetch_stg <= get_m_ptrs;
fetch_m <= "000";
fetch_n <= "000000";
fetch_p <= (cell_V*40);
else
fetch_stg <= get_m_data;
fetch_m <= "000";
fetch_n <= "000000";
end if;
end if;
when get_m_ptrs =>
line_c(ratoi(cur_n)) <= cd;
line_b(ratoi(cur_n)) <= vd;
if (cur_n < "100111") then
fetch_n <= inc6(cur_n);
fetch_p <= fetch_p + 1;
else
fetch_n <= "000000";
fetch_stg <= get_m_data;
end if;
when get_m_data =>
line_pix(pxtoi(fetch_n & "000")) <= vd(0);
line_pix(pxtoi(fetch_n & "001")) <= vd(1);
line_pix(pxtoi(fetch_n & "010")) <= vd(2);
line_pix(pxtoi(fetch_n & "011")) <= vd(3);
line_pix(pxtoi(fetch_n & "100")) <= vd(4);
line_pix(pxtoi(fetch_n & "101")) <= vd(5);
line_pix(pxtoi(fetch_n & "110")) <= vd(6);
line_pix(pxtoi(fetch_n & "111")) <= vd(7);
if (fetch_n < "100111") then
fetch_n <= inc6(fetch_n);
else
fetch_n <= "000000";
fetch_stg <= get_idle;
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process fetching;
pixgen: process(en,bdr,vic_EC,win_H,cell_H,vic_B0C,clk20_ph1) is
variable cur_px_pos : slv9;
begin
cur_px_pos := "000000000";
if (rising_edge(clk20_ph1)) then
if (en = '1') then
if (bdr = '1') then
vr <= vcolor_r(vic_EC)(7 downto 3);
vg <= vcolor_g(vic_EC)(7 downto 2);
vb <= vcolor_b(vic_EC)(7 downto 3);
else
cur_px_pos(8 downto 3) := slv6(win_H(8 downto 3));
cur_px_pos(2 downto 0) := "111" xor slv3(win_H(2 downto 0));
if (line_pix(to_integer(unsigned(cur_px_pos))) = '1') then
vr <= vcolor_r(line_c(u8toi(cell_H)))(7 downto 3);
vg <= vcolor_g(line_c(u8toi(cell_H)))(7 downto 2);
vb <= vcolor_b(line_c(u8toi(cell_H)))(7 downto 3);
else
vr <= vcolor_r(vic_B0C)(7 downto 3);
vg <= vcolor_g(vic_B0C)(7 downto 2);
vb <= vcolor_b(vic_B0C)(7 downto 3);
end if;
end if;
else
vr <= "00000";
vg <= "000000";
vb <= "00000";
end if;
end if;
end process pixgen;
end vic_ii_impl;
|
gpl-3.0
|
forflo/yodl
|
vhdlpp/vhdl_testfiles/netlist_candidate_01.vhd
|
1
|
3624
|
-- this vhdl source resembles following verilog code
-- module ripplemod(a, b, cin, sum, cout);
-- input [7:0] a;
-- input [7:0] b;
-- input cin;
-- output [7:0]sum;
-- output cout;
-- wire[6:0] c;
--
-- fulladd a1(a[0],b[0],cin,sum[0],c[0]);
-- fulladd a2(a[1],b[1],c[0],sum[1],c[1]);
-- fulladd a3(a[2],b[2],c[1],sum[2],c[2]);
-- fulladd a4(a[3],b[3],c[2],sum[3],c[3]);
-- fulladd a5(a[4],b[4],c[3],sum[4],c[4]);
-- fulladd a6(a[5],b[5],c[4],sum[5],c[5]);
-- fulladd a7(a[6],b[6],c[5],sum[6],c[6]);
-- fulladd a8(a[7],b[7],c[6],sum[7],cout);
-- endmodule
--
-- module fulladd(a, b, cin, sum, cout);
-- input a; input b; input cin;
-- output sum; output cout;
--
-- assign sum=(a^b^cin);
-- assign cout=((a&b)|(b&cin)|(a&cin));
-- endmodule
--
-- which expands to:
--
-- sum(0) <= a(0) xor b(0) xor cin
-- c(0) <= (a(0) and b(0)) or (b(0) and cin) or (a(0) and cin);
--
-- sum(1) <= a(1) xor b(1) xor c(0)
-- c(1) <= (a(1) and b(1)) or (b(1) and c(0)) or (a(1) and c(0));
--
-- sum(2) <= a(2) xor b(2) xor c(1)
-- c(2) <= (a(2) and b(2)) or (b(2) and c(1)) or (a(2) and c(1));
--
-- sum(3) <= a(3) xor b(3) xor c(2)
-- c(3) <= (a(3) and b(3)) or (b(3) and c(2)) or (a(3) and c(2));
--
-- sum(4) <= a(4) xor b(4) xor c(3)
-- c(4) <= (a(4) and b(4)) or (b(4) and c(3)) or (a(4) and c(3));
--
-- sum(5) <= a(5) xor b(5) xor c(4)
-- c(5) <= (a(5) and b(5)) or (b(5) and c(4)) or (a(5) and c(4));
--
-- sum(6) <= a(6) xor b(6) xor c(5)
-- c(6) <= (a(6) and b(6)) or (b(6) and c(5)) or (a(6) and c(5));
--
-- sum(7) <= a(7) xor b(7) xor c(6)
-- cout <= (a(7) and b(7)) or (b(7) and c(6)) or (a(7) and c(6));
----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector(7 downto 0));
end adder;
architecture behv of adder is
signal wire : std_logic_vector(8 downto 0);
begin
wire(0) <= cin;
cout <= wire(8);
rippleCarry : for pos in 0 to 7 generate
sum(pos) <= a(pos) xor b(pos) xor wire(pos);
wire(pos + 1) <=
(a(pos) and b(pos)) or
(b(pos) and wire(pos)) or
(a(pos) and wire(pos));
end generate rippleCarry;
end behv;
----
-- for n = 1 this expands to:
----------------
-- library ieee;
-- use ieee.std_logic_1164.all;
-- use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
--
-- entity adder is
-- port(A : in std_logic_vector(1 downto 0);
-- B : in std_logic_vector(1 downto 0);
-- cin : in std_logic;
-- cout : out std_logic;
-- sum : out std_logic_vector(1 downto 0));
-- end adder;
--
-- architecture behv of adder is
-- signal wire : std_logic_vector(2 downto 0);
-- begin
-- wire(0) <= cin;
-- cout <= wire(2);
--
-- rippleCarry : for pos in 0 to 1 generate
-- sum(pos) <= a(pos) xor b(pos) xor wire(pos);
-- wire(pos + 1) <=
-- (a(pos) and b(pos)) or
-- (b(pos) and wire(pos)) or
-- (a(pos) and wire(pos));
-- end generate rippleCarry;
--
-- -- which in turn expands to:
-- sum(0) <= a(0) xor b(0) xor wire(0);
-- wire(1) <= (a(0) and b(0)) or
-- (b(0) and wire(0)) or
-- (a(0) and wire(0));
--
-- sum(1) <= a(1) xor b(1) xor wire(1);
-- wire(2) <= (a(1) and b(1)) or
-- (b(1) and wire(1)) or
-- (a(1) and wire(1));
--
-- end behv;
----
|
gpl-3.0
|
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