repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
FlatTargetInk/UMD_RISC-16G5
|
Lab04/Lab04/ipcore_dir/VGA_BUFFER_RAM/simulation/addr_gen.vhd
|
30
|
4526
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/Poject_Lab01/Project1/ipcore_dir/blk_mem_gen_v7_3/simulation/addr_gen.vhd
|
30
|
4526
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/Poject_Lab01/Project1/ProjLab01.vhd
|
1
|
13101
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Rob Mushrall
-- Timothy Doucette Jr
-- Christopher Parks
--
-- Create Date: 15:43:26 03/25/2016
-- Design Name:
-- Module Name: ProjLab01 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity ProjLab01 is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
--instruction : in STD_LOGIC_VECTOR (15 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (15 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
DEBUG_OUT : out STD_LOGIC_VECTOR (15 downto 0));
end ProjLab01;
architecture Structural of ProjLab01 is
signal OP1, OP2, OP3, OP4 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RA1, RA2, RA3 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RA4 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '1');
signal RB1, RB2, RB3, RB4 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal PC0, PC1, PC2, PC3, PC4 : STD_LOGIC_VECTOR (4 downto 0) := (OTHERS => '0');
signal IMM1, IMM2, IMM3 : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal GLOBAL_EN : STD_LOGIC := '1'; -- Determines whether things are enabled (allowed to operate)
signal IMM_SEL : STD_LOGIC := '0'; -- Determines selection between immediate data and RB
signal PC_EN, PC_INC : STD_LOGIC := '1'; -- Program counter enable
signal PC_RST : STD_LOGIC := '0';
signal INST_EN : STD_LOGIC := '1'; -- Enables instruction memory
signal RD_EN, WR_EN : STD_LOGIC := '0'; -- Enables the register bank to read, write
signal OPR1, OPR2, OPRB :STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- From reg bank to RA and RB data registers
signal OPIN : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RAIN : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RBIN : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal IMMIN : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal IMSEL : STD_LOGIC := '0';
signal OP1_SEL, OP2_SEL : STD_LOGIC_VECTOR (1 downto 0):= (OTHERS => '0'); -- Selector for data contention
signal ALU_RESULT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- Latched Result of ALU
signal ALU_VAL : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- Result direct from ALU
signal ALU_OUT_FLAGS : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); -- flags output from ALU
signal ALU_FLAGS : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); -- latched flags from ALU
signal RA_IN, RB_IN : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- Values to go to DC Muxes
signal RA_OUT, RB_OUT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- Values from DC muxes to ALU
signal ALU_DC1, ALU_DC2: STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- Data contention ALU values
signal RA_DC1, RA_DC2: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '1'); -- Data contention RA values
signal RB_DC1, RB_DC2: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '1'); -- Data contention RB values
signal DATARD_EN, DATAWR_EN: STD_LOGIC := '0'; -- Enable reading or writing to/from Data Memory
begin
ALU_OUT <= ALU_RESULT;
CCR <= ALU_FLAGS;
DST_ADR <= "00000000000" & PC4;
DEBUG_OUT <= OPIN & RAIN & IMMIN;
-------- Debugging I/O --------
---------------------------------
--ALU_OUT <= "000" & RA4 & RB4 & PC4; --ALU_RESULT;
--STORE_DATA <= "000" & IMSEL & OP4 & IMM3;
--OPIN <= instruction(15 downto 12);
--RAIN <= instruction(11 downto 8);
--RBIN <= instruction(7 downto 4);
--IMMIN <= instruction (7 downto 0);
-------- ALU --------
-----------------------
ALU_UNIT : entity work.ALU_Toplevel
port map(RA => RA_OUT,
RB => RB_OUT,
OP => OP3,
CLK => CLK,
ALU_OUT => ALU_VAL,
SREG => ALU_OUT_FLAGS,
LDST_DAT => STORE_DATA);
--LDST_ADR => DST_ADR);
-------- Fetch --------
-------------------------
Fetch_UNIT : entity work.Instruction_Memory_TL
port map( CLK => CLK,
RST => RST,
RA => RAIN,
RB => RBIN,
OP => OPIN,
IMM => IMMIN);
-------- Control Units --------
---------------------------------
-- DISPTCH : entity work.Dispatch port map(CLK => CLK, -- (in)
-- OPC => OP2, -- (in)
-- RA => RA2, -- (in)
-- RB => RB2, -- (in)
-- RA4 => RA4, -- (in)
-- IMM_SEL => IMM_SEL, -- (out)
-- DC1 => DC2_1, -- (out)
-- DC2 => DC2_2); -- Dispatch control unit (out)
-- FETCH : entity work.Fetch_CTL port map(CLK => CLK, -- (in)
-- EN => GLOBAL_EN, -- (in)
-- RST => PC_RST, -- (out)
-- INC => PC_INC, -- (out)
-- PC_EN => PC_EN, -- (out)
-- INST_EN => INST_EN); -- Fetch control unit (out)
REGCTL : entity work.REG_CTL port map(CLK => CLK, -- (in)
OPC => OP1, -- (in)
OPC4 => OP4, -- (in)
RD_EN => RD_EN, -- (out)
WR_EN => WR_EN); -- Register control unit (out)
DCCTL : entity work.DC_CTL port map(CLK => CLK, -- (in)
RA => RA3, -- (in)
RB => RB3,
RA0 => RA4,
-- RB0 => RB4,
RA1 => RA_DC1,
RA2 => RA_DC2,
-- RB1 => RB_DC1,
-- RB2 => RB_DC2,
OPC => OP3, -- (in)
OP1_SEL => OP1_SEL, -- (out)
OP2_SEL => OP2_SEL); -- Data contention (out)
DATA_CTL : entity work.DATA_CTL
port map(CLK => CLK,
EN => GLOBAL_EN,
OP => OP3,
RD_EN => DATARD_EN,
WR_EN => DATAWR_EN);
IMSELECT : entity work.IMSEL
port map(OP => OP2,
SEL_IM => IMSEL);
-------- Pipeline Registers --------
--------------------------------------
----> Stage One <----
OP1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OPIN,
Dout => OP1);
RA1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RAIN,
Dout => RA1);
RB1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RBIN,
Dout => RB1);
IMM1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 8)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => IMMIN,
Dout => IMM1);
PC1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 5)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => PC0,
Dout => PC1);
----> Stage Two <----
OP2_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OP1,
Dout => OP2);
RA2ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RA1,
Dout => RA2);
RB2ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RB1,
Dout => RB2);
OPR0_Reg: entity work.PipelineRegisters
generic map( dataWidth => 8)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => IMM1,
Dout => IMM2);
-- OPR1_Reg: entity work.PipelineRegisters
-- generic map( dataWidth => 16)
-- port map( Clk => CLK,
-- Ena => GLOBAL_EN,
-- Rst => RST,
-- Din => F2OPR1,
-- Dout => S3OPR1);
-- OPR2_Reg: entity work.PipelineRegisters
-- generic map( dataWidth => 16)
-- port map( Clk => CLK,
-- Ena => GLOBAL_EN,
-- Rst => RST,
-- Din => F2OPR2,
-- Dout => S3OPR2);
PC2_Reg: entity work.PipelineRegisters
generic map( dataWidth => 5)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => PC1,
Dout => PC2);
----> Stage Three <----
RA3ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RA2,
Dout => RA3);
RB3ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RB2,
Dout => RB3);
PC3_Reg: entity work.PipelineRegisters
generic map( dataWidth => 5)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => PC2,
Dout => PC3);
OP3_Reg: entity work.PipelineRegisters
generic map( datawidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OP2,
Dout => OP3);
RA_DATA: entity work.PipelineRegisters
generic map( datawidth => 16)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OPR1,
Dout => RA_IN);
RB_DATA: entity work.PipelineRegisters
generic map( datawidth => 16)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OPRB,
Dout => RB_IN);
----> Stage Four <----
RA4ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RA3,
Dout => RA4);
RB4ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RB3,
Dout => RB4);
PC4_Reg: entity work.PipelineRegisters
generic map( dataWidth => 5)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => PC3,
Dout => PC4);
ALU_OUT_Reg: entity work.PipelineRegisters
generic map( dataWidth => 16)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => ALU_VAL,
Dout => ALU_RESULT);
ALU_FLAGS_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => ALU_OUT_FLAGS,
Dout => ALU_FLAGS);
OP4_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OP3,
Dout => OP4);
----> DC Stage 1 <----
ALU_OUT1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 16)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => ALU_RESULT,
Dout => ALU_DC1);
RA_DC1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RA4,
Dout => RA_DC1);
RB_DC1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RB4,
Dout => RB_DC1);
----> DC Stage 2 <----
ALU_OUT2_Reg: entity work.PipelineRegisters
generic map( dataWidth => 16)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => ALU_DC1,
Dout => ALU_DC2);
RA_DC2_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RA_DC1,
Dout => RA_DC2);
RB_DC2_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RB_DC1,
Dout => RB_DC2);
-------- Immediate Select Mux --------
----------------------------------------
with IMSEL select OPRB <=
x"00" & IMM2 when '1',
OPR2 when OTHERS;
-------- Memory Entities --------
-----------------------------------
ProgCounter: entity work.programCounter
generic map(PCWIDTH => 5)
port map( CLK => CLK,
EN => PC_EN,
RST => RST,
INSADR => PC0);
RegisterBank_Unit: entity work.RegisterBank
port map( RST => RST,
RAddr => RA1,
RBddr => RB1,
RWddr => RA4,
DATAIN => ALU_RESULT,
clk => CLK,
R => RD_EN,
W => WR_EN,
RAout => OPR1,
RBout => OPR2);
-------- Data Contention Handler --------
-------------------------------------------
with OP1_SEL select RA_OUT <=
ALU_RESULT when "01",
ALU_DC1 when "10",
ALU_DC2 when "11",
RA_IN when OTHERS;
with OP2_SEL select RB_OUT <=
ALU_RESUlt when "01",
ALU_DC1 when "10",
ALU_DC2 when "11",
RB_IN when OTHERS;
end Structural;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/ipcore_dir/EXTERNAL_MEMORY/example_design/EXTERNAL_MEMORY_prod.vhd
|
2
|
10143
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: EXTERNAL_MEMORY_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 16384
-- C_READ_DEPTH_A : 16384
-- C_ADDRA_WIDTH : 14
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 16384
-- C_READ_DEPTH_B : 16384
-- C_ADDRB_WIDTH : 14
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY EXTERNAL_MEMORY_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END EXTERNAL_MEMORY_prod;
ARCHITECTURE xilinx OF EXTERNAL_MEMORY_prod IS
COMPONENT EXTERNAL_MEMORY_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : EXTERNAL_MEMORY_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/vga_controller_tb.vhd
|
7
|
6285
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: VGA_COLOR Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY VGA_TOPLEVEL_tb_vhd IS
END VGA_TOPLEVEL_tb_vhd;
ARCHITECTURE behavior OF VGA_TOPLEVEL_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT VGA_TOPLEVEL
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
--SW : in STD_LOGIC_VECTOR (7 downto 0);
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
VGARED : out STD_LOGIC_VECTOR (2 downto 0);
VGAGRN : out STD_LOGIC_VECTOR (2 downto 0);
VGABLU : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '0';
SIGNAL PS2_CLK : STD_LOGIC := '1';
SIGNAL PS2_DATA: STD_LOGIC := '1';
SIGNAL HSYNC : STD_LOGIC := '0';
SIGNAL VSYNC : STD_LOGIC := '0';
SIGNAL VGARED : STD_LOGIC_VECTOR(2 downto 0) := (others=>'0');
SIGNAL VGAGRN : STD_LOGIC_VECTOR(2 downto 0) := (others=>'0');
SIGNAL VGABLU : STD_LOGIC_VECTOR(1 downto 0) := (others=>'0');
--SIGNAL SW : STD_LOGIC_VECTOR(7 downto 0);
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: VGA_TOPLEVEL PORT MAP( CLK => CLK,
RST => RST,
--SW => SW,
PS2_CLK => PS2_CLK,
PS2_DATA=> PS2_DATA,
HSYNC => HSYNC,
VSYNC => VSYNC,
VGARED => VGARED,
VGAGRN => VGAGRN,
VGABLU => VGABLU);
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Start VGA_Controller Test Bench" severity NOTE;
--Simulate Pressing A
--Sending the Break Code X"F0"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
--Sending the Key Code X"1C"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '0';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
wait; -- will wait forever
END PROCESS;
END;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/logical_unit.vhd
|
8
|
1684
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:37:34 03/28/2016
-- Design Name:
-- Module Name: logical_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logical_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
LOG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end logical_unit;
architecture Combinational of logical_unit is
signal result : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal zro : STD_LOGIC := '0';
begin
with OP select
result <=
RA or RB when "011", -- OR
RA and RB when "010", -- AND
RA and RB when "110", -- ANDI
RB when "100", -- MOV
RA or RB when OTHERS; -- SAFE (I guess)
zro <= '1' when result(15 downto 0) = x"00000000" else '0'; -- Zero
LOG_OUT <= result;
SREG_OUT <= '0' & zro & "00";
end Combinational;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/Instr_Mem1.vhd
|
2
|
5613
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file Instr_Mem1.vhd when simulating
-- the core, Instr_Mem1. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY Instr_Mem1 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END Instr_Mem1;
ARCHITECTURE Instr_Mem1_a OF Instr_Mem1 IS
-- synthesis translate_off
COMPONENT wrapped_Instr_Mem1
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_Instr_Mem1 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "Instr_Mem1.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_Instr_Mem1
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END Instr_Mem1_a;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/word_unit.vhd
|
4
|
2155
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 14:45:47 03/31/2016
-- Design Name:
-- Module Name: word_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity word_unit is
Port ( DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
IMMAddr : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR(3 downto 0); -- Pass OP(2) to this (OP=0=Load, OP=1=Write)
RESULT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (7 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0));
end word_unit;
architecture Combinational of word_unit is
signal WREN : STD_LOGIC_VECTOR(0 downto 0) := "0";
begin
DST_ADR <= IMMAddr;
STORE_DATA <= DATAIN;
WREN <= "0" when OP = x"9" else -- x"9" is load word
"1" when OP = x"A"; -- x"A" is store word
DATAMEMORY : entity work.DATAMEM port map(ADDRA => IMMAddr,
DINA => DATAIN,
WEA => WREN, -- Write enable
CLKA => CLK,
DOUTA => RESULT);
-- When OP = 1 then WRITE is enabled, IMMAddr gives us the address to write to, DATAIN gives us the data to write. RESULT will soon show data written if untouched
-- When OP = 0 then WRITE is disabled, DATAIN is ignored, IMMAddr gives us the address to read from, and RESULT is set to the RESULT.
end Combinational;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/programCounter.vhd
|
7
|
1104
|
-- Company: Team 5
-- Engineer:
--
-- Create Date: 15:15:57 03/11/2016
-- Design Name:
-- Module Name: programCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity programCounter is
generic(PCWIDTH:integer:=16);
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
RST : in STD_LOGIC;
INSADR : out STD_LOGIC_VECTOR (PCWIDTH-1 downto 0));
end programCounter;
architecture Behavioral of programCounter is
signal COUNTER : std_logic_vector(PCWIDTH-1 downto 0) := (OTHERS => '0');
begin
INSADR <= COUNTER;
process(CLK, RST)
begin
if(RST = '1')then
COUNTER <= (OTHERS => '0');
elsif(CLK'event and CLK = '0')then
if(EN = '1')then
COUNTER <= unsigned(COUNTER) + 1;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/Lab04/ipcore_dir/DEBUG_RAM/simulation/DEBUG_RAM_synth.vhd
|
5
|
9210
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: DEBUG_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY DEBUG_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE DEBUG_RAM_synth_ARCH OF DEBUG_RAM_synth IS
COMPONENT DEBUG_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 4 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: DEBUG_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/Intruction_Memory/Instruction_Memory/simulation/Instruction_Memory_tb.vhd
|
1
|
4516
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Instruction_Memory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Instruction_Memory_tb IS
END ENTITY;
ARCHITECTURE Instruction_Memory_tb_ARCH OF Instruction_Memory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Instruction_Memory_synth_inst:ENTITY work.Instruction_Memory_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/vga_driver.vhd
|
10
|
3053
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: VGA Toplevel
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Toplevel of the VGA Unit
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity VGA_Driver is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
--Data INPUT
DATA_CLK : in STD_LOGIC;
DATA_WE : in STD_LOGIC;
DATA_ADR : in STD_LOGIC_VECTOR (11 downto 0);
DATA : in STD_LOGIC_VECTOR (7 downto 0);
--VGA OUTPUT
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
VGARED : out STD_LOGIC_VECTOR (2 downto 0);
VGAGRN : out STD_LOGIC_VECTOR (2 downto 0);
VGABLU : out STD_LOGIC_VECTOR (1 downto 0));
end VGA_Driver;
architecture Structural of VGA_Driver is
signal PCLK : STD_LOGIC;
signal vcount : STD_LOGIC_VECTOR(9 downto 0):= (OTHERS => '0');
signal hcount : STD_LOGIC_VECTOR(9 downto 0):= (OTHERS => '0');
signal blank : STD_LOGIC := '0';
signal MUX8to1_OUT : STD_LOGIC := '0';
signal BUF_ADR : STD_LOGIC_VECTOR(11 downto 0):= (OTHERS => '0');
signal BUF_OUT : STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0');
signal FR_ADR : STD_LOGIC_VECTOR(10 downto 0):= (OTHERS => '0');
signal FR_DATA: STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0');
signal VGA_ADR : STD_LOGIC_VECTOR(12 downto 0):= (OTHERS => '0');
begin
VGA_ADR <= vcount(8 downto 4)*X"50" + hcount(9 downto 3);
BUF_ADR <= VGA_ADR(11 downto 0);
FR_ADR <= BUF_OUT(6 downto 0) & vcount(3 downto 0);
U1: entity work.CLK_25MHZ
port map( CLK_IN => CLK,
CLK_OUT => PCLK);
U2: entity work.vga_controller
port map( RST => RST,
PIXEL_CLK => PCLK,
HS => HSYNC,
VS => VSYNC,
HCOUNT => hcount,
VCOUNT => vcount,
BLANK => blank);
U3: entity work.RGB
port map( VALUE => MUX8to1_OUT,
BLANK => blank,
RED => VGARED,
GRN => VGAGRN,
BLU => VGABLU);
U4: entity work.MUX8to1
port map( SEL => hcount(2 downto 0),
DATA => FR_DATA,
OUTPUT => MUX8to1_OUT);
U5: entity work.FONT_ROM
port map( CLK => CLK,
ADDR => FR_ADR,
DATA => FR_DATA);
U6: entity work.VGA_BUFFER_RAM
port map( CLKA => DATA_CLK,
WEA(0)=> DATA_WE,
ADDRA => DATA_ADR,
DINA => DATA,
CLKB => CLK,
ADDRB => BUF_ADR,
DOUTB => BUF_OUT);
end Structural;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/Lab04/vga_driver.vhd
|
10
|
3053
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: VGA Toplevel
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Toplevel of the VGA Unit
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity VGA_Driver is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
--Data INPUT
DATA_CLK : in STD_LOGIC;
DATA_WE : in STD_LOGIC;
DATA_ADR : in STD_LOGIC_VECTOR (11 downto 0);
DATA : in STD_LOGIC_VECTOR (7 downto 0);
--VGA OUTPUT
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
VGARED : out STD_LOGIC_VECTOR (2 downto 0);
VGAGRN : out STD_LOGIC_VECTOR (2 downto 0);
VGABLU : out STD_LOGIC_VECTOR (1 downto 0));
end VGA_Driver;
architecture Structural of VGA_Driver is
signal PCLK : STD_LOGIC;
signal vcount : STD_LOGIC_VECTOR(9 downto 0):= (OTHERS => '0');
signal hcount : STD_LOGIC_VECTOR(9 downto 0):= (OTHERS => '0');
signal blank : STD_LOGIC := '0';
signal MUX8to1_OUT : STD_LOGIC := '0';
signal BUF_ADR : STD_LOGIC_VECTOR(11 downto 0):= (OTHERS => '0');
signal BUF_OUT : STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0');
signal FR_ADR : STD_LOGIC_VECTOR(10 downto 0):= (OTHERS => '0');
signal FR_DATA: STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0');
signal VGA_ADR : STD_LOGIC_VECTOR(12 downto 0):= (OTHERS => '0');
begin
VGA_ADR <= vcount(8 downto 4)*X"50" + hcount(9 downto 3);
BUF_ADR <= VGA_ADR(11 downto 0);
FR_ADR <= BUF_OUT(6 downto 0) & vcount(3 downto 0);
U1: entity work.CLK_25MHZ
port map( CLK_IN => CLK,
CLK_OUT => PCLK);
U2: entity work.vga_controller
port map( RST => RST,
PIXEL_CLK => PCLK,
HS => HSYNC,
VS => VSYNC,
HCOUNT => hcount,
VCOUNT => vcount,
BLANK => blank);
U3: entity work.RGB
port map( VALUE => MUX8to1_OUT,
BLANK => blank,
RED => VGARED,
GRN => VGAGRN,
BLU => VGABLU);
U4: entity work.MUX8to1
port map( SEL => hcount(2 downto 0),
DATA => FR_DATA,
OUTPUT => MUX8to1_OUT);
U5: entity work.FONT_ROM
port map( CLK => CLK,
ADDR => FR_ADR,
DATA => FR_DATA);
U6: entity work.VGA_BUFFER_RAM
port map( CLKA => DATA_CLK,
WEA(0)=> DATA_WE,
ADDRA => DATA_ADR,
DINA => DATA,
CLKB => CLK,
ADDRB => BUF_ADR,
DOUTB => BUF_OUT);
end Structural;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab04/alu_shift_unit.vhd
|
12
|
1229
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Shift_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Shift Unit
-- Operations - Shift Left, Shift Right
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Shift_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
COUNT : in STD_LOGIC_VECTOR (2 downto 0);
OP : in STD_LOGIC;
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU_Shift_Unit;
architecture Combinational of ALU_Shift_Unit is
signal shift_left, shift_right : std_logic_vector (7 downto 0) := (OTHERS => '0');
begin
shift_left <= to_stdlogicvector(to_bitvector(A) sll conv_integer(COUNT));
shift_right <= to_stdlogicvector(to_bitvector(A) srl conv_integer(COUNT));
RESULT <= shift_left when OP='0' else shift_right;
end Combinational;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab04/rgb.vhd
|
12
|
1005
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: RGB
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Enable for RGB
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RGB is
Port ( VALUE : in STD_LOGIC;
BLANK : in std_logic;
RED : out STD_LOGIC_VECTOR(2 downto 0);
GRN : out STD_LOGIC_VECTOR(2 downto 0);
BLU : out STD_LOGIC_VECTOR(1 downto 0));
end RGB;
architecture Behavioral of RGB is
signal enb : std_logic;
begin
RED<="000" when BLANK='1' else VALUE & VALUE & VALUE;
GRN<="000" when BLANK='1' else VALUE & VALUE & VALUE;
BLU<="00" when BLANK='1' else VALUE & VALUE;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/rgb.vhd
|
12
|
1005
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: RGB
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Enable for RGB
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RGB is
Port ( VALUE : in STD_LOGIC;
BLANK : in std_logic;
RED : out STD_LOGIC_VECTOR(2 downto 0);
GRN : out STD_LOGIC_VECTOR(2 downto 0);
BLU : out STD_LOGIC_VECTOR(1 downto 0));
end RGB;
architecture Behavioral of RGB is
signal enb : std_logic;
begin
RED<="000" when BLANK='1' else VALUE & VALUE & VALUE;
GRN<="000" when BLANK='1' else VALUE & VALUE & VALUE;
BLU<="00" when BLANK='1' else VALUE & VALUE;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
JumpUnit/ECE368_Project_Lab1_Team5/ipcore_dir/Instr_Mem/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/ipcore_dir/DEBUG_RAM/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/ipcore_dir/EXTERNAL_MEMORY/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ALU/ALU/arith_unit.vhd
|
1
|
1885
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:20:02 03/28/2016
-- Design Name:
-- Module Name: arith_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity arith_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
AR_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end arith_unit;
architecture Combinational of arith_unit is
signal a,b : STD_LOGIC_VECTOR (16 downto 0) := (OTHERS => '0');
signal RESULT : STD_LOGIC_VECTOR (16 downto 0) := (OTHERS => '0');
signal SREG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
a <= '0' & RA;
b <= '0' & RB;
with OP select
RESULT <=
a + b when "000", -- ADD
a - b when "001", -- SUB
a + b when "101", -- ADDI
'0' & X"0000" when OTHERS;
SREG(3) <= RESULT(15); -- Negative with signed logic
SREG(2) <= '1' when RESULT(15 downto 0) = x"00000000" else '1'; -- Zero
SREG(1) <= RESULT(16) xor RESULT(15); -- Overflow with signed logic
SREG(0) <= RESULT(16); -- Carry
SREG_OUT <= SREG;
AR_OUT <= RESULT(15 downto 0);
end Combinational;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_exdes.vhd
|
5
|
4822
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END blk_mem_gen_v7_3_exdes;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_v7_3 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : blk_mem_gen_v7_3
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab4/VGADebug/VGADebug/keyboard_controller_tb.vhd
|
4
|
5823
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: KEYBOARD_CONTROLLER Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY KEYBOARD_CONTROLLER_tb_vhd IS
END KEYBOARD_CONTROLLER_tb_vhd;
ARCHITECTURE behavior OF KEYBOARD_CONTROLLER_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT KEYBOARD_CONTROLLER
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
ASCII_OUT: out STD_LOGIC_VECTOR (7 downto 0);
ASCII_RD : out STD_LOGIC;
ASCII_WE : out STD_LOGIC);
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '0';
SIGNAL PS2_CLK : STD_LOGIC := '1';
SIGNAL PS2_DATA: STD_LOGIC := '1';
SIGNAL ASCII_OUT : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL ASCII_RD: STD_LOGIC := '0';
SIGNAL ASCII_WE: STD_LOGIC := '0';
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: KEYBOARD_CONTROLLER PORT MAP( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA=> PS2_DATA,
ASCII_OUT => ASCII_OUT,
ASCII_RD=> ASCII_RD,
ASCII_WE=> ASCII_WE);
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 us;
report "Start VGA_Controller Test Bench" severity NOTE;
--Simulate Pressing A
--Sending the Break Code X"F0"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
--Sending the Key Code X"1C"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '0';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
wait; -- will wait forever
END PROCESS;
END;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab3/KeyboardProject/Keyboard/keyboard_controller_tb.vhd
|
4
|
5823
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: KEYBOARD_CONTROLLER Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY KEYBOARD_CONTROLLER_tb_vhd IS
END KEYBOARD_CONTROLLER_tb_vhd;
ARCHITECTURE behavior OF KEYBOARD_CONTROLLER_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT KEYBOARD_CONTROLLER
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
ASCII_OUT: out STD_LOGIC_VECTOR (7 downto 0);
ASCII_RD : out STD_LOGIC;
ASCII_WE : out STD_LOGIC);
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '0';
SIGNAL PS2_CLK : STD_LOGIC := '1';
SIGNAL PS2_DATA: STD_LOGIC := '1';
SIGNAL ASCII_OUT : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL ASCII_RD: STD_LOGIC := '0';
SIGNAL ASCII_WE: STD_LOGIC := '0';
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: KEYBOARD_CONTROLLER PORT MAP( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA=> PS2_DATA,
ASCII_OUT => ASCII_OUT,
ASCII_RD=> ASCII_RD,
ASCII_WE=> ASCII_WE);
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 us;
report "Start VGA_Controller Test Bench" severity NOTE;
--Simulate Pressing A
--Sending the Break Code X"F0"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
--Sending the Key Code X"1C"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '0';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
wait; -- will wait forever
END PROCESS;
END;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Shadow_Register/Lab04/ipcore_dir/DEBUG_RAM/simulation/DEBUG_RAM_synth.vhd
|
2
|
8888
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: DEBUG_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY DEBUG_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE DEBUG_RAM_synth_ARCH OF DEBUG_RAM_synth IS
COMPONENT DEBUG_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 64,
READ_WIDTH => 4 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: DEBUG_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/Intruction_Memory/Instruction_Memory/example_design/Instruction_Memory_exdes.vhd
|
1
|
4834
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instruction_Memory_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Instruction_Memory_exdes;
ARCHITECTURE xilinx OF Instruction_Memory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Instruction_Memory IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Instruction_Memory
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/Poject_Lab01[old]/ProjLab1/ProjLab01.vhd
|
1
|
3445
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Rob Mushrall
-- Timothy Doucette Jr
-- Chris Parks
--
-- Create Date: 15:43:26 03/25/2016
-- Design Name:
-- Module Name: ProjLab01 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ProjLab01 is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (15 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0));
end ProjLab01;
architecture Structural of ProjLab01 is
signal GLOBAL_EN : STD_LOGIC := '1'; -- Determines whether things are enabled and allowed to do the thing
signal OP1, OP2, OP3, OP4 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RA1, RA2, RA3, RA4 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RB1, RB2, RB3, RB4 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal IM1, IM2, IM3 : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal IMM_SEL : STD_LOGIC := '0'; -- Determines selection between immediate data and RB
signal DC2_1, DC2_2 : STD_LOGIC := '0'; --
signal PC_EN, PC_RST, PC_INC : STD_LOGIC := '0'; -- Program counter enable
signal INST_EN : STD_LOGIC := '1'; -- Enables instruction memory
signal RD_EN, WR_EN : STD_LOGIC := '0'; -- Enables the register bank to read, write
signal OP1_SEL, OP2_SEL : STD_LOGIC := '0'; -- Used for data contention ctrl (DC_CTL) to drive select lines on two muxes
begin
DISPTCH : entity work.Dispatch port map(CLK => CLK, -- (in)
OPC => OP2, -- (in)
RA => RA2, -- (in)
RB => RB2, -- (in)
RA4 => RA4, -- (in)
IMM_SEL => IMM_SEL, -- (out)
DC1 => DC2_1, -- (out)
DC2 => DC2_2); -- Dispatch control unit (out)
FETCH : entity work.Fetch_CTL port map( CLK => CLK, -- (in)
EN => GLOBAL_EN, -- (in)
RST => PC_RST, -- (out)
INC => PC_INC, -- (out)
PC_EN => PC_EN, -- (out)
INST_EN => INST_EN); -- Fetch control unit (out)
REGCTL : entity work.REG_CTL port map(CLK => CLK, -- (in)
OPC => OP1, -- (in)
OPC4 => OP4, -- (in)
RD_EN => RD_EN, -- (out)
WR_EN => WR_EN); -- Register control unit (out)
DCCTL : entity work.DC_CTL port map(CLK => CLK, -- (in)
RA => RA1, -- (in)
RB => RB1, -- (in)
OPC => OP1, -- (in)
RA4 => RA4, -- (in)
OP1_SEL => OP1_SEL, -- (out)
OP2_SEL => OP2_SEL); -- Data contention (out)
end Structural;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/ProgramCounter/ProgramCounter/ipcore_dir/Instr_Mem/simulation/addr_gen.vhd
|
101
|
4409
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab04/font_rom_ascii.vhd
|
12
|
53139
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab3/XTerm/XTerm/font_rom_ascii.vhd
|
12
|
53139
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/Lab04/ipcore_dir/DEBUG_RAM/simulation/bmg_stim_gen.vhd
|
5
|
12711
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((4 <= 7),WR_RD_DEEP_COUNT,
((4/32)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((7 <= 4),WR_RD_DEEP_COUNT,
((32/4)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(3 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(6 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 128 ,
RST_INC => 8 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32 ,
DATA_PART_CNT => 0,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/ipcore_dir/blk_mem_gen_v7_3/simulation/bmg_tb_pkg.vhd
|
30
|
6206
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/Poject_Lab01/RegisterBank2/RegisterBank.vhd
|
1
|
5441
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: SYNCHRONOUS REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Revision 0.02 - (3/31/16) Comments added, verified address selection worked as Dan's compiler expected.
--
-- Additional Comments: Signals in this module are used as data storage registers,
-- going from R0 up to R15. Faulty addresses are handled by
-- not handling them. This means that when a faulty address
-- is given, the old data is left on the output value.
-- EXAMPLE: RAout assigned 12 previously. New RAddr is faulty.
-- RAout remains as assigned 12.
--
-- The register bank is synchronous, meaning it will read data
-- into a register on the rising edge and then output data on
-- the RAout/RBout lines on the falling edge of clk.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); -- Address for register to put out to RAout
RBddr : in STD_LOGIC_VECTOR (3 downto 0); -- Address for register to put out to RBout
RWddr : in STD_LOGIC_VECTOR (3 downto 0); -- Address for register to write to
DATAIN : in STD_LOGIC_VECTOR (15 downto 0); -- Data to write to register
clk : in STD_LOGIC; -- Clock. Register bank is synchronous. Read on rising edge, Write on falling edge.
R : in STD_LOGIC; -- Read enable (Enables register bank to put out data)
W : in STD_LOGIC; -- Write enable (Enables register bank to take in data)
RAout : out STD_LOGIC_VECTOR (15 downto 0); -- Puts out data based on register selection using RAddr
RBout : out STD_LOGIC_VECTOR (15 downto 0)); -- Puts out data based on register selection using RBddr
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := x"0000";
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is -- Address selection for RA
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS. THIS CAUSES THE PREVIOUS DATA TO REMAIN FOR A FAULTY ADDRESS!
end case; -- (3/31/16): Verified RegisterBank address selection matched up with what Dan Noyes' compiler expects.
case RBddr is -- Address selection for RB
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS. THIS CAUSES THE PREVIOUS DATA TO REMAIN FOR A FAULTY ADDRESS!
end case; -- (3/31/16): Verified RegisterBank address selection matched up with what Dan Noyes' compiler expects.
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS. THIS CAUSES THE PREVIOUS DATA TO REMAIN FOR FAULTY ADDRESS!
end case; -- (3/31/16): Verified RegisterBank address selection matched up with what Dan Noyes' compiler expects.
end if;
end process;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/ipcore_dir/Instr_Mem/simulation/checker.vhd
|
69
|
5607
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/ipcore_dir/DEBUG_RAM/simulation/checker.vhd
|
69
|
5607
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/ipcore_dir/blk_mem_gen_v7_3/simulation/checker.vhd
|
26
|
5768
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/ipcore_dir/VGA_BUFFER_RAM/simulation/checker.vhd
|
26
|
5768
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/Poject_Lab01/Project1/DC_CTL.vhd
|
6
|
2306
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1, OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if (RA = RA0) then
OP1 <= "01";
-- OP1_SEL <= OP1;
elsif (RA = RA1) then
OP1 <= "10";
-- OP1_SEL <= OP1;
elsif (RA = RA2) then
OP1 <= "11";
-- OP1_SEL <= OP1;
else
OP1 <= "00";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0) then
OP2 <= "01";
elsif (RB = RA1) then
OP2 <= "10";
elsif (RB = RA2) then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
"00" when OTHERS;
end Mixed;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/ipcore_dir/instruction_memory/simulation/data_gen.vhd
|
69
|
5024
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/ipcore_dir/DEBUG_RAM/simulation/data_gen.vhd
|
69
|
5024
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab3/XTerm/XTerm/ipcore_dir/VGA_BUFFER_RAM/simulation/data_gen.vhd
|
69
|
5024
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/Lab04/ipcore_dir/VGA_BUFFER_RAM/simulation/VGA_BUFFER_RAM_tb.vhd
|
8
|
4695
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: VGA_BUFFER_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY VGA_BUFFER_RAM_tb IS
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_tb_ARCH OF VGA_BUFFER_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
VGA_BUFFER_RAM_synth_inst:ENTITY work.VGA_BUFFER_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/Poject_Lab01[old]/RegisterBank2 (3-25-16)/RegisterBank2/RegisterBank_tb.vhd
|
2
|
3781
|
--------------------------------------------------------------------------------
-- Company: UMASS DARTMOUTH
-- Engineer: Christopher Parks
--
-- Create Date: 13:20:29 03/25/2016
-- Design Name:
-- Module Name: Z:/Xilinx/RegisterBank2/RegisterBank_tb.vhd
-- Project Name: RegisterBank
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RegisterBank
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY RegisterBank_tb IS
END RegisterBank_tb;
ARCHITECTURE behavior OF RegisterBank_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RegisterBank
PORT(
RAddr : IN std_logic_vector(3 downto 0);
RBddr : IN std_logic_vector(3 downto 0);
RWddr : IN std_logic_vector(3 downto 0);
DATAIN : IN std_logic_vector(15 downto 0);
clk : IN std_logic;
R : IN std_logic;
W : IN std_logic;
RAout : OUT std_logic_vector(15 downto 0);
RBout : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal RAddr : std_logic_vector(3 downto 0) := (others => '0');
signal RBddr : std_logic_vector(3 downto 0) := (others => '0');
signal RWddr : std_logic_vector(3 downto 0) := (others => '0');
signal DATAIN : std_logic_vector(15 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal R : std_logic := '0';
signal W : std_logic := '0';
--Outputs
signal RAout : std_logic_vector(15 downto 0);
signal RBout : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RegisterBank PORT MAP (
RAddr => RAddr,
RBddr => RBddr,
RWddr => RWddr,
DATAIN => DATAIN,
clk => clk,
R => R,
W => W,
RAout => RAout,
RBout => RBout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
W <= '1'; -- Enable write
wait for clk_period;
for i in 0 to 15 loop
RWddr <= std_logic_vector(to_unsigned(i, RWddr'length));
wait for clk_period;
DATAIN <= std_logic_vector(to_unsigned(i,DATAIN'length));
wait for clk_period;
end loop;
W <= '0';
R <= '1';
wait for clk_period;
for i in 0 to 14 loop
RAddr <= std_logic_vector(to_unsigned(i,RAddr'length));
RBddr <= std_logic_vector(to_unsigned(i+1,RBddr'length));
wait for clk_period;
assert (RAout(3 downto 0) = RAddr) report "wrong value" severity error;
assert (RBout(3 downto 0) = RBddr) report "wrong value" severity error;
end loop;
wait;
end process;
END;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Shadow_Register/Lab04/Lab04/vga_controller.vhd
|
12
|
4006
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA Controller
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Driver a VGA display
-- Display out an resolution of 640x480@60Hz
-- Notes:
-- For more information on a VGA display:
-- https://eewiki.net/pages/viewpage.action?pageId=15925278
-- http://digilentinc.com/Data/Documents/Reference%20Designs/VGA%20RefComp.zip
-- Always read the spec sheets
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_controller is
Port ( RST : in std_logic;
PIXEL_CLK : inout std_logic;
HS : out std_logic;
VS : out std_logic;
HCOUNT : out std_logic_vector(9 downto 0);
VCOUNT : out std_logic_vector(9 downto 0);
BLANK : out std_logic);
end vga_controller;
architecture Behavioral of vga_controller is
-- maximum value - horizontal pixel counter
constant HMAX : std_logic_vector(9 downto 0) := "1100100000"; -- 800
-- maximum value - vertical pixel counter
constant VMAX : std_logic_vector(9 downto 0) := "1000001101"; -- 525
-- total visible columns
constant HLINES: std_logic_vector(9 downto 0) := "1010000000"; -- 640
-- horizontal counter - front porch ends
constant HFP : std_logic_vector(9 downto 0) := "1010001000"; -- 648
-- horizontal counter - synch pulse ends
constant HSP : std_logic_vector(9 downto 0) := "1011101000"; -- 744
-- total visible lines
constant VLINES: std_logic_vector(9 downto 0) := "0111100000"; -- 480
-- vertical counter - front porch ends
constant VFP : std_logic_vector(9 downto 0) := "0111100010"; -- 482
-- vertical counter - synch pulse ends
constant VSP : std_logic_vector(9 downto 0) := "0111100100"; -- 484
-- polarity of the horizontal and vertical synch pulse
constant SPP : std_logic := '0';
signal hcounter : std_logic_vector(9 downto 0) := (others => '0');
signal vcounter : std_logic_vector(9 downto 0) := (others => '0');
signal video_enable: std_logic;
begin
hcount <= hcounter;
vcount <= vcounter;
blank <= not video_enable when rising_edge(PIXEL_CLK);
video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
-- horizontal counter
h_count: process(PIXEL_CLK)
begin
if(rising_edge(PIXEL_CLK)) then
if(rst = '1') then
hcounter <= (others => '0');
elsif(hcounter = HMAX) then
hcounter <= (others => '0');
else
hcounter <= hcounter + 1;
end if;
end if;
end process h_count;
-- vertical counter
v_count: process(PIXEL_CLK)
begin
if(rising_edge(PIXEL_CLK)) then
if(rst = '1') then
vcounter <= (others => '0');
elsif(hcounter = HMAX) then
if(vcounter = VMAX) then
vcounter <= (others => '0');
else
vcounter <= vcounter + 1;
end if;
end if;
end if;
end process v_count;
-- horizontal synch pulse
do_hs: process(PIXEL_CLK)
begin
if(rising_edge(PIXEL_CLK)) then
if(hcounter >= HFP and hcounter < HSP) then
HS <= SPP;
else
HS <= not SPP;
end if;
end if;
end process do_hs;
-- generate vertical synch pulse
do_vs: process(PIXEL_CLK)
begin
if(rising_edge(PIXEL_CLK)) then
if(vcounter >= VFP and vcounter < VSP) then
VS <= SPP;
else
VS <= not SPP;
end if;
end if;
end process do_vs;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/ipcore_dir/blk_mem_gen_v7_3/simulation/data_gen.vhd
|
26
|
5164
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/Lab04/ipcore_dir/DEBUG_RAM/simulation/data_gen.vhd
|
26
|
5164
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/Combined_tb.vhd
|
1
|
3441
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:24:50 04/20/2016
-- Design Name:
-- Module Name: /home/tj/Desktop/UMD_RISC-16G5/ProjectLab2/Combined/Combined_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ProjLab01
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Combined_tb IS
END Combined_tb;
ARCHITECTURE behavior OF Combined_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ProjLab01
PORT(
CLK : IN std_logic;
RST : IN std_logic;
ALU_OUT : OUT std_logic_vector(15 downto 0);
DST_ADR : OUT std_logic_vector(15 downto 0);
STORE_DATA : OUT std_logic_vector(15 downto 0);
CCR : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal ALU_OUT : std_logic_vector(15 downto 0);
signal DST_ADR : std_logic_vector(15 downto 0);
signal STORE_DATA : std_logic_vector(15 downto 0);
signal CCR : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_period : time := 1 ms;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ProjLab01 PORT MAP (
CLK => CLK,
RST => RST,
ALU_OUT => ALU_OUT,
DST_ADR => DST_ADR,
STORE_DATA => STORE_DATA,
CCR => CCR
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
RST <= '1';
wait for CLK_period*2;
wait for CLK_period/2;
RST <= '0';
wait for CLK_period*10;
-- instruction <= X"5002";
--
-- wait for CLK_period;
--
-- instruction <= X"5101";
--
-- wait for CLK_period;
--
-- instruction <= X"A10F";
--
-- wait for CLK_period;
--
-- instruction <= X"950F";
--
-- wait for CLK_period;
--
-- instruction <= X"0050";
--
-- wait for CLK_period;
--
-- instruction <= X"2010";
--
-- wait for CLK_period;
--
-- instruction <= X"3010";
--
-- wait for CLK_period;
--
-- instruction <= X"0010";
--
-- wait for CLK_period;
--
-- instruction <= X"4A10";
--
-- wait for CLK_period;
--
-- instruction <= X"7A03";
--
-- wait for CLK_period;
--
-- instruction <= X"B201";
--
-- wait for CLK_period;
--
-- instruction <= X"C212";
wait for CLK_period;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab04/ipcore_dir/VGA_BUFFER_RAM/simulation/bmg_stim_gen.vhd
|
8
|
12716
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((12 <= 12),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((12 <= 12),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(11 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(11 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 4096,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/ipcore_dir/VGA_BUFFER_RAM/simulation/bmg_stim_gen.vhd
|
8
|
12716
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((12 <= 12),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((12 <= 12),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(11 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(11 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 4096,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/Lab04/ipcore_dir/VGA_BUFFER_RAM/simulation/bmg_stim_gen.vhd
|
8
|
12716
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((12 <= 12),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((12 <= 12),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(11 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(11 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 4096,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/ProgramCounter/ProgramCounter/PC_OFFSET.vhd
|
3
|
1207
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:04:12 04/22/2016
-- Design Name:
-- Module Name: PC_OFFSET - Combinational
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PC_OFFSET is
generic(PCWIDTH:integer:=16);
Port (CUR_ADR : in STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
OFFSET : in STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
NEW_ADR : out STD_LOGIC_VECTOR(PCWIDTH-1 downto 0));
end PC_OFFSET;
architecture Combinational of PC_OFFSET is
begin
NEW_ADR <= CUR_ADR + OFFSET;
end Combinational;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab04/ipcore_dir/DEBUG_RAM.vhd
|
5
|
5933
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file DEBUG_RAM.vhd when simulating
-- the core, DEBUG_RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY DEBUG_RAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END DEBUG_RAM;
ARCHITECTURE DEBUG_RAM_a OF DEBUG_RAM IS
-- synthesis translate_off
COMPONENT wrapped_DEBUG_RAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_DEBUG_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 4,
c_addrb_width => 7,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "20",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16,
c_read_depth_b => 128,
c_read_width_a => 32,
c_read_width_b => 4,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16,
c_write_depth_b => 128,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 32,
c_write_width_b => 4,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_DEBUG_RAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END DEBUG_RAM_a;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab3/VGADisplay/VGAColor/rgb.vhd
|
3
|
1020
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: RGB
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Enable for RGB
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RGB is
Port ( VALUE : in STD_LOGIC_VECTOR(7 downto 0);
BLANK : in std_logic;
RED : out STD_LOGIC_VECTOR(2 downto 0);
GRN : out STD_LOGIC_VECTOR(2 downto 0);
BLU : out STD_LOGIC_VECTOR(1 downto 0));
end RGB;
architecture Behavioral of RGB is
signal enb : std_logic;
begin
RED<="000" when BLANK='1' else VALUE(7 downto 5);
GRN<="000" when BLANK='1' else VALUE(4 downto 2);
BLU<="00" when BLANK='1' else VALUE(1 downto 0);
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ALU/ALU/alu_toplevel.vhd
|
1
|
2789
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_Toplevel is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG : out STD_LOGIC_VECTOR (3 downto 0);
LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Toplevel;
architecture Structural of ALU_Toplevel is
signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
begin
arith_unit: entity work.arith_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
AR_OUT => ARITH);
logical_unit: entity work.logical_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
LOG_OUT => LOGIC,
SREG_OUT => SREG_LG);
shift_unit: entity work.shift_unit
port map( RA => RA,
SHIFT => RB(7 downto 0),
OP => OP(3),
SHIFT_OUT => SHIFT,
SREG_OUT => SREG_SH);
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD (ARITHMETIC)
ARITH when "0001", -- SUB (ARITHMETIC)
LOGIC when "0010", -- AND (LOGICAL)
LOGIC when "0011", -- OR (LOGICAL)
LOGIC when "0100", -- MOV (LOGICAL)
ARITH when "0101", -- ADDI (ARITHMETIC)
LOGIC when "0110",--, -- ANDI (LOGICAL)
SHIFT when "0111", -- SL (SHIFT)
SHIFT when "1000",--, -- SR (SHIFT)
--"" when "1001", -- LW (WORD)
--"" when "1010"; -- SW (WORD)
RA when OTHERS;
end Structural;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ALU/ALU/ALU_tb.vhd
|
1
|
4571
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:48:55 04/01/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ALU/ALU/ALU_tb.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU_Toplevel
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU_Toplevel
PORT(
RA : IN std_logic_vector(15 downto 0);
RB : IN std_logic_vector(15 downto 0);
OP : IN std_logic_vector(3 downto 0);
ALU_OUT : OUT std_logic_vector(15 downto 0);
SREG : OUT std_logic_vector(3 downto 0);
LDST_DAT : OUT std_logic_vector(15 downto 0);
LDST_ADR : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal RA : std_logic_vector(15 downto 0) := (others => '0');
signal RB : std_logic_vector(15 downto 0) := (others => '0');
signal OP : std_logic_vector(3 downto 0) := (others => '0');
signal CLK : std_logic := '0';
--Outputs
signal ALU_OUT : std_logic_vector(15 downto 0);
signal SREG : std_logic_vector(3 downto 0);
signal LDST_DAT : std_logic_vector(15 downto 0);
signal LDST_ADR : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace CLK below with
-- appropriate port name
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU_Toplevel PORT MAP (
RA => RA,
RB => RB,
OP => OP,
ALU_OUT => ALU_OUT,
SREG => SREG,
LDST_DAT => LDST_DAT,
LDST_ADR => LDST_ADR
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
RA <= X"0002";
RB <= X"0001";
OP <= "0000";
wait for CLK_period;
assert (ALU_OUT = X"0003") report "Incorrect Result" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
OP <= "0001";
wait for CLK_period;
assert (ALU_OUT = X"0001") report "Incorrect Result" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
OP <= "0010";
wait for CLK_period;
assert (ALU_OUT = X"0000") report "Incorrect Result" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
OP <= "0011";
wait for CLK_period;
assert (ALU_OUT = X"0003") report "Incorrect Result" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
OP <= "0100";
wait for CLK_period;
assert (ALU_OUT = X"0001") report "Incorrect Result" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
OP <= "0101";
wait for CLK_period;
assert (ALU_OUT = X"0003") report "Incorrect Result" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
OP <= "0110";
wait for CLK_period;
assert (ALU_OUT = X"0000") report "Incorrect Result" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
OP <= "0111";
wait for CLK_period;
assert (ALU_OUT = X"0004") report "Incorrect Result" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
OP <= "1000";
wait for CLK_period;
assert (ALU_OUT = X"0001") report "Incorrect Result" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
-- for i in 0 to 15 loop
-- OP <= to_stdlogicvector(i);
-- wait for CLK_period;
-- end loop;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/ipcore_dir/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_synth.vhd
|
5
|
8218
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/NewCombined/Dispatch.vhd
|
9
|
2146
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:23:05 03/25/2016
-- Design Name:
-- Module Name: Dispatch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Dispatch is
Port ( CLK : in STD_LOGIC;
OPC : in STD_LOGIC_VECTOR (3 downto 0);
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA4 : in STD_LOGIC_VECTOR (3 downto 0);
IMM_SEL : out STD_LOGIC;
DC1 : out STD_LOGIC;
DC2 : out STD_LOGIC);
end Dispatch;
architecture Behavioral of Dispatch is
begin
process(CLK)
begin
if(rising_edge(CLK)) then
case OPC is
when "0000" => IMM_SEL <= '0';
when "0001" => IMM_SEL <= '0';
when "0010" => IMM_SEL <= '0';
when "0011" => IMM_SEL <= '0';
when "0100" => IMM_SEL <= '0';
when "0101" => IMM_SEL <= '1';
when "0110" => IMM_SEL <= '1';
when "0111" => IMM_SEL <= '1';
when "1000" => IMM_SEL <= '1';
when "1001" => IMM_SEL <= '1';
when "1010" => IMM_SEL <= '1';
when others => IMM_SEL <= '0';
end case;
-- case RA is
-- when RA4 => DC1 <= '1';
-- when others => DC1 <= '0';
-- end case;
--
-- case RB is
-- when RA4 => DC2 <= '1';
-- when others => DC2 <= '0';
-- end case;
if(RA = RA4) then
DC1 <= '1';
else
DC1 <= '0';
end if;
if(RB = RA4) then
DC2 <= '1';
else
DC2 <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/Dispatch.vhd
|
9
|
2146
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:23:05 03/25/2016
-- Design Name:
-- Module Name: Dispatch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Dispatch is
Port ( CLK : in STD_LOGIC;
OPC : in STD_LOGIC_VECTOR (3 downto 0);
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA4 : in STD_LOGIC_VECTOR (3 downto 0);
IMM_SEL : out STD_LOGIC;
DC1 : out STD_LOGIC;
DC2 : out STD_LOGIC);
end Dispatch;
architecture Behavioral of Dispatch is
begin
process(CLK)
begin
if(rising_edge(CLK)) then
case OPC is
when "0000" => IMM_SEL <= '0';
when "0001" => IMM_SEL <= '0';
when "0010" => IMM_SEL <= '0';
when "0011" => IMM_SEL <= '0';
when "0100" => IMM_SEL <= '0';
when "0101" => IMM_SEL <= '1';
when "0110" => IMM_SEL <= '1';
when "0111" => IMM_SEL <= '1';
when "1000" => IMM_SEL <= '1';
when "1001" => IMM_SEL <= '1';
when "1010" => IMM_SEL <= '1';
when others => IMM_SEL <= '0';
end case;
-- case RA is
-- when RA4 => DC1 <= '1';
-- when others => DC1 <= '0';
-- end case;
--
-- case RB is
-- when RA4 => DC2 <= '1';
-- when others => DC2 <= '0';
-- end case;
if(RA = RA4) then
DC1 <= '1';
else
DC1 <= '0';
end if;
if(RB = RA4) then
DC2 <= '1';
else
DC2 <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/ipcore_dir/blk_mem_gen_v7_3.vhd
|
5
|
5822
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v7_3.vhd when simulating
-- the core, blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v7_3 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END blk_mem_gen_v7_3;
ARCHITECTURE blk_mem_gen_v7_3_a OF blk_mem_gen_v7_3 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_gen_v7_3
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_gen_v7_3 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "blk_mem_gen_v7_3.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v7_3
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END blk_mem_gen_v7_3_a;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/Poject_Lab01/Project1/ipcore_dir/Instr_Mem/example_design/Instr_Mem_prod.vhd
|
5
|
10082
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: Instr_Mem_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : Instr_Mem.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 32
-- C_READ_DEPTH_A : 32
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 32
-- C_READ_DEPTH_B : 32
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instr_Mem_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END Instr_Mem_prod;
ARCHITECTURE xilinx OF Instr_Mem_prod IS
COMPONENT Instr_Mem_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : Instr_Mem_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/Poject_Lab01/Project1/ipcore_dir/Instruction_Memory.vhd
|
6
|
5701
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file instruction_memory.vhd when simulating
-- the core, instruction_memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY instruction_memory IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END instruction_memory;
ARCHITECTURE instruction_memory_a OF instruction_memory IS
-- synthesis translate_off
COMPONENT wrapped_instruction_memory
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_instruction_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "instruction_memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 20,
c_read_depth_b => 20,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 20,
c_write_depth_b => 20,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_instruction_memory
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END instruction_memory_a;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/ipcore_dir/Instruction_Memory.vhd
|
6
|
5701
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file instruction_memory.vhd when simulating
-- the core, instruction_memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY instruction_memory IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END instruction_memory;
ARCHITECTURE instruction_memory_a OF instruction_memory IS
-- synthesis translate_off
COMPONENT wrapped_instruction_memory
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_instruction_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "instruction_memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 20,
c_read_depth_b => 20,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 20,
c_write_depth_b => 20,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_instruction_memory
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END instruction_memory_a;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/Lab04/alu_toplevel.vhd
|
7
|
2688
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab04/Lab04/alu_toplevel.vhd
|
7
|
2688
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/Instr_Mem1/simulation/Instr_Mem1_synth.vhd
|
2
|
7895
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instr_Mem1_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY Instr_Mem1_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE Instr_Mem1_synth_ARCH OF Instr_Mem1_synth IS
COMPONENT Instr_Mem1_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: Instr_Mem1_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/ipcore_dir/instruction_memory/example_design/instruction_memory_exdes.vhd
|
5
|
4671
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instruction_memory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instruction_memory_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END instruction_memory_exdes;
ARCHITECTURE xilinx OF instruction_memory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT instruction_memory IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : instruction_memory
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab04/button_controller.vhd
|
10
|
1450
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: Button Controller
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Button Controller
-- Four input debouncer
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
entity buttoncontrol is
Port ( CLK : in STD_LOGIC;
INPUT : in STD_LOGIC_VECTOR (3 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (3 downto 0));
end buttoncontrol;
architecture Structural of buttoncontrol is
signal EN : STD_LOGIC := '1';
begin
BTN_0: entity work.debounce
port map( CLK => CLK,
EN => EN,
INPUT => INPUT(0),
OUTPUT => OUTPUT(0));
BTN_1: entity work.debounce
port map( CLK => CLK,
EN => EN,
INPUT => INPUT(1),
OUTPUT => OUTPUT(1));
BTN_2: entity work.debounce
port map( CLK => CLK,
EN => EN,
INPUT => INPUT(2),
OUTPUT => OUTPUT(2));
BTN_3: entity work.debounce
port map( CLK => CLK,
EN => EN,
INPUT => INPUT(3),
OUTPUT => OUTPUT(3));
end Structural;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/RegisterBank.vhd
|
7
|
3891
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/RegisterBank.vhd
|
7
|
3891
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
Separius/CordicWrapper
|
corwrapcontrol.vhd
|
1
|
3336
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity corwrapcontrol is
port(clk: in std_logic;
slave: in std_logic;
grant: in std_logic;
done_in: in std_logic;
rst: in std_logic;
done_out: out std_logic;
store: out std_logic;
en: out std_logic;
start: out std_logic;
readMem : out std_logic;
writeMem:out std_logic;
req:out std_logic;
data_out_select: out std_logic_vector(1 downto 0));
end entity corwrapcontrol;
-------------------------------------------------------------------------------
architecture arch of corwrapcontrol is
type cordic_states is (ready,saving,requested,granted,waiting,waitingtwo,starting,writeaddress,writeaddresstwo,writein);
signal state, next_state: cordic_states;
begin -- architecture arch
process (clk, rst)
begin
if(rst='1') then
state <= ready;
elsif (clk='1' and clk'Event) then
state <= next_state;
end if;
end process;
process (state, slave, grant, done_in)
begin
case state is
when ready => if slave='1' then
next_state <= saving;
else
next_state <= ready;
end if;
when saving => next_state <= requested;
when requested => if(grant='1') then
next_state <= granted;
else
next_state <= requested;
end if;
when granted => next_state <= waiting;
when waiting => next_state <= waitingtwo;
when waitingtwo => next_state <= starting;
--when starting => next_state <= startingtwo;
when starting => if(done_in = '1')then
next_state <= writeaddress;
else
next_state <= starting;
end if;
when writeaddress => next_state <= writeaddresstwo;
when writeaddresstwo => next_state <= writein;
when writein => next_state <= ready;
end case;
end process;
process (state)
begin
case state is
when ready => done_out<='1';store<='0';en<='0';start<='0';readMem<='0';writeMem<='0';req<='0';data_out_select<="11";
when saving => done_out<='0';store<='0';en<='1';start<='0';readMem<='0';writeMem<='0';req<='0';data_out_select<="11";
when requested => done_out<='0';store<='0';en<='0';start<='0';readMem<='0';writeMem<='0';req<='1';data_out_select<="11";
when granted => done_out<='0';store<='0';en<='0';start<='0';readMem<='1';writeMem<='0';req<='0';data_out_select<="10";
when waiting => done_out<='0';store<='0';en<='0';start<='0';readMem<='0';writeMem<='0';req<='0';data_out_select<="10";
when waitingtwo => done_out<='0';store<='0';en<='0';start<='1';readMem<='0';writeMem<='0';req<='0';data_out_select<="10";
when starting => done_out<='0';store<='0';en<='0';start<='1';readMem<='0';writeMem<='0';req<='0';data_out_select<="11";
--when startingtwo => done_out<='0';store<='0';en<='0';start<='1';readMem<='0';writeMem<='0';req<='0';data_out_select<="11";
when writeaddress => done_out<='0';store<='1';en<='0';start<='0';readMem<='0';writeMem<='1';req<='0';data_out_select<="01";
when writeaddresstwo => done_out<='0';store<='0';en<='0';start<='0';readMem<='0';writeMem<='0';req<='0';data_out_select<="01";
when writein => done_out<='0';store<='0';en<='0';start<='0';readMem<='0';writeMem<='0';req<='0';data_out_select<="00";
end case;
end process;
end architecture arch;
-------------------------------------------------------------------------------
|
gpl-3.0
|
Separius/CordicWrapper
|
sregExtended.vhd
|
1
|
728
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sregExtended is
generic(width: integer:= 16);
port(data_i: in signed(width-1 downto 0);
en_i: in std_logic;
clk: in std_logic;
result: out signed(width-1 downto 0));
end entity sregExtended;
-------------------------------------------------------------------------------
architecture arch of sregExtended is
signal internal: signed(width-1 downto 0);
begin -- architecture arch
process(clk)
begin
if(clk'event and clk='1') then
if(en_i = '1') then
internal <= data_i;
end if;
end if;
end process;
result <= internal;
end architecture arch;
-------------------------------------------------------------------------------
|
gpl-3.0
|
Separius/CordicWrapper
|
sregstd.vhd
|
1
|
742
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sregstd is
generic(width: integer:= 5);
port(data_i: in std_logic_vector(width-1 downto 0);
en_i: in std_logic;
clk: in std_logic;
result: out std_logic_vector(width-1 downto 0));
end entity sregstd;
-------------------------------------------------------------------------------
architecture arch of sregstd is
signal internal: std_logic_vector(width-1 downto 0);
begin -- architecture arch
process(clk)
begin
if(clk'event and clk='1') then
if(en_i = '1') then
internal <= data_i;
end if;
end if;
end process;
result <= internal;
end architecture arch;
-------------------------------------------------------------------------------
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/pro000014.vhd
|
1
|
3943
|
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes.
use work.std_logic_1164_for_tst.all;
entity ENT00011_Test_Bench is
end ENT00011_Test_Bench;
architecture ARCH00011_Test_Bench of ENT00011_Test_Bench is
type std_array_array is array (0 to 3, 1 to 4) of std_ulogic;
signal I_saa : std_array_array := (others => x"B");
subtype byte is bit_vector(7 downto 0);
subtype byte2 is bit_vector(0 to 7);
signal b1 : byte := x"00";
signal b2 : byte2 := x"00";
type bit_array_array is array (0 to 3, 4 downto 1) of bit;
signal I_baa : bit_array_array := (others => x"A");
type NatArray is array (natural range <>) of natural;
type std_array is array (0 to 7) of std_logic;
signal I_sa : std_array := "10101010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type enum_array is array (integer range <>) of enum;
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
f4 : enum;
f5 : enum_array(0 to 3);
f6 : NatArray(7 downto 0);
f7 : bit_vector(7 downto 0);
end record;
type rec_array is array (integer range <>) of rec;
signal e : enum := a_v;
signal ea : enum_array(0 to 3) := (others => a_v);
signal r : rec := (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
);
signal ra : rec_array(0 to 3) := (others => (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
)
);
signal bv : bit_vector(15 downto 0) := x"CCCC";
signal clk : std_ulogic := '0';
signal clk2 : std_ulogic := '0';
type BoolVector is array (integer range <>) of boolean;
signal bool : BoolVector(1 to 60);
begin
bool(37) <= bv'Active;
bool(38) <= ra'Active;
bool(39) <= r'Active;
bool(40) <= ea'Active;
bool(41) <= e'Active;
bool(42) <= I_sa'Active;
bool(43) <= I_baa'Active;
bool(44) <= I_saa'Active;
bool(45) <= b1'Active;
bool(46) <= b2'Active;
bool(47) <= clk'Active;
bool(48) <= clk2'Active;
clk <= not clk after 1 us;
clk2 <= not clk2 after 3 us;
process (clk)
begin
if clk'event and clk = '1' then
b1 <= b1(6 downto 0) & not b1(7);
case e is
when a_v => e <= b_v;
when b_v => e <= c_v;
when c_v => e <= d_v;
when d_v => e <= e_v;
when e_v => e <= f_v;
when f_v => e <= a_v;
end case;
ea(0) <= e;
ea_loop: for i in 1 to ea'length-1 loop
ea(i) <= ea(i-1);
end loop ea_loop;
elsif falling_edge(clk) then
bv <= bv(bv'left-1 downto bv'low) & bv(bv'high);
r.f1 <= r.f1 + 1;
r.f2 <= not r.f2;
r.f3 <= not r.f3;
r.f4 <= e;
r.f5 <= ea;
r_f6_loop: for i in r.f6'low to r.f6'high loop
r.f6(i) <= r.f6(i) + 1;
end loop r_f6_loop;
r.f7 <= r.f7(6 downto 0) & r.f7(7);
ra(ra'high) <= r;
ra_loop: for i in ra'high-1 downto 0 loop
ra(i) <= ra(i+1);
end loop;
end if;
end process;
process (clk2)
begin
if rising_edge(clk2) then
I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2);
elsif clk2'event and clk2 = '0' then
I_saa_loop_1: for i in 0 to 3 loop
I_saa_loop_2: for j in 1 to 4 loop
I_saa(i,j) <= I_sa(i+j);
end loop I_saa_loop_2;
end loop I_saa_loop_1;
I_baa_loop_1: for i in 0 to 3 loop
I_baa_loop_2: for j in 1 to 4 loop
I_baa(i,j) <= bv(i*j);
end loop I_baa_loop_2;
end loop I_baa_loop_1;
end if;
end process;
end ARCH00011_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00032.vhd
|
1
|
7969
|
-- NEED RESULT: ARCH00032.P1: Target of a variable assignment may be a indexed name passed
-- NEED RESULT: ARCH00032.P2: Target of a variable assignment may be a indexed name passed
-- NEED RESULT: ARCH00032.P3: Target of a variable assignment may be a indexed name passed
-- NEED RESULT: ARCH00032.P4: Target of a variable assignment may be a indexed name passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00032
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00032)
-- ENT00032_Test_Bench(ARCH00032_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00032 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
begin
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
--
correct := correct and
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
test_report ( "ARCH00032.P1" ,
"Target of a variable assignment may be a " &
"indexed name" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3 : st_arr3 :=
c_st_arr3_1 ;
--
begin
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
--
correct := correct and
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00032.P2" ,
"Target of a variable assignment may be a " &
"indexed name" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
--
end Proc1 ;
begin
Proc1 ;
correct := correct and
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
test_report ( "ARCH00032.P3" ,
"Target of a variable assignment may be a " &
"indexed name" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_st_rec3 : inout st_rec3
; v_st_arr1 : inout st_arr1
; v_st_arr2 : inout st_arr2
; v_st_arr3 : inout st_arr3
)
is
begin
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
--
end Proc1 ;
begin
Proc1 (
v_st_rec3
, v_st_arr1
, v_st_arr2
, v_st_arr3
) ;
correct := correct and
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr1(st_arr1'Left) =
c_st_int1_2 ;
correct := correct and
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
correct := correct and
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
test_report ( "ARCH00032.P4" ,
"Target of a variable assignment may be a " &
"indexed name" ,
correct) ;
end process P4 ;
--
end ARCH00032 ;
--
entity ENT00032_Test_Bench is
end ENT00032_Test_Bench ;
--
architecture ARCH00032_Test_Bench of ENT00032_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00032 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00032_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_input_block.vhd
|
9
|
44196
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Sa/X2fuUPFBgWNweidBHti1Zxl0+dnCXbqQGfecXx8FI17ZoWd7iE0xOtcmFB6U6z3tUyQkhFOxR
EHXegHMx4g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lmF9yNNj2XYcQ9hhoCl3f8rXeTtSGgIr1qdJbiSB0SlzCSD8WBXutfiivo57XGJhu1U0wD91NxCb
PzIl/zTNse1B5uGgh18rDSJ9fMtA4UpMnx+zMBI0fI09dVnaCH1f8xOp3LaoIJV7rBGQBk3KEySL
Nf+oDAOICOwP6un8zOQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
B5jvUryWP9fNwzOEe1EQz4yDxapUWxmoA/3Z0UGGAo/HSICL78qjy6KanqtXsjXZbGtiFPZk/Q6g
ZDVeNOAdIpLy3+1YT4R6EYQEFzv1VzA5tKhouaqjalzyVAXUQYJD3OqXEzBjjGbQKd+vSi5PL6sP
UTTfPOf6rsMe/Utn6vNBjxDjwmje4sAFmxj8RCp0T7Mab+7I3p4PFx86s65Ah4yQFyUF7hVyORPf
6+B4ZvNqBI+sK4evlgpufY/j3PhvHX8HGoagDffHqpr5mDS7Z/fPyKHh72mKcd/F/dhN1HEqNLdN
87OS3Zi9l2lvPR26pT3SSuHBy/I1h2lDiJvO4w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bTInUywiEuEN8l/R5pd03y9OWcM3AfJRXCyFmSNTCXG1FbnEtyFC9ZmkLaWG/HzvD8iv8mLTDcQ+
7Vd5lA2adNj3+v6vPXArGIbCAq4YlpZOyNJoCVsq6lE2HSNYcsKD0hQBkquOvwEGKSf34EA+EE6i
sf6GFCuzL128uVm5wag=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
og53ELaxsAv9yq+YTzEqUM4u5Dno+yoI1fBgG/O8FF0m/201+yQXAwEHL3fAqtw7ebxmwgXE2T3A
9UuXt2dF5DYqdRz03jPbv5cL5NEk2HKIOqhiLxvid++AQDa9YvrV7M+gxhGXBMrb4eF35Pu+tyTC
3UAr73a2V95NSOAJ/bAVyG9pIPMI8G67pbtbRMV0MuQWjHMjJg5Tu2/eHC6NeCfpoqzjgnBQata7
C9XBTTvswizJfwE5j3QYkj4+cLKEc/zczoOXPFmOyofUjlhTkB+TteT5P30UxfwjcdoDG1O5CI4B
F45cHCYR0uRof06XqR8+1V6E14d7EsptQxCkYQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30976)
`protect data_block
R0Qk2oqwflI9GpY3m5joyseliRr4673dtp0lb1zDjkaaSufNRzDMCc6KCowR99QdiV3je5ItWJZK
PYxTs4SmTjjkdQ0tl2SE4l30zmLlsSJwwzKxnBjAYz2Tpyjx+PNqYJWKLBtu1Mo6/NmnPRW9ZUJ5
v+BbQEvER29PcVmOcpcU26f6rdxDGEutkjVbwiC4bNKvTYoVcOAJylzwaNCeu00I8wdeAxyuMI2V
7gnv/8UIU3q8dsfika1drxzPOHbICw7KgkfbiC6HWbxcLRF5JZGCrdUIN6b3OFKFjd4Iu8THIt0y
hlQk6MoS5vNOlipkwh2PYzGL7siVmCh44OvFhErNUeu11ET0HHiKSdC/x4c67/BGFGJRYAR6D+Un
EQAGE7ZuLwPUp4b37jSwrWmXZzGz4qp7ijyXLLriiZg1wCmxBQTg4utJ9hwuXbb6tvDp+MtJgqEP
eXaYjCrdu24m8rl52Xfh2il4DvgXjCeF9Xxpvhtf0K93pmbeyNBSSQaQvfrEYZxd/XIByCcMub2G
/eliy4qrlXsG2t5G/M8K1wD/fWjT+x2tniBOmXcHrrMf5M1uclvkUpco9tukW2emHWJUgYwg2+JP
VcXJybqc0TiZ+zmMXwg7PSkGTsIrJOR+bXxITnWZlLzEh1NKya7idNMVzHvhG/pL5on8kiCquT6C
paYY93z4Q+rCTrcpSgJ0vu0Sbbdb0pOztC1/qNSXzW0OUF0RbJ4W0X5jLAPwhnTpZYhSSOYxrVVU
Bn6T5C7+stZysHLHSo5XfzbDT4totQOb7anKifxqRNPPkpJqBpR+4m/gm78/qp30KN7VMUhDrTF6
NMdhJ50uFhRrH0FkxJTrM7unnZIoqJIx8pJCZCoQJ7yB/9H96asPUyfrCrRv09k2qPndzED7hL8i
VlJTUWK1yvb4/xkycV9OZfDPAe7gTDKW9L71mL0snI3Cz1+2nZddEzdXija45VV8iT2irY7aIEU1
cbSG0Sdi6NQNKdje6lrL8aE7Hq90o72klnlgKjjXsnfZveYha5CaqOQ42E1B1R6XkwaCyFSZlKrp
tFLDGmzQz4asWWyz4jN01zMm9LQqoEthX32790gSNKSslIcZBXGtODOXiwofEHEExM0w99zAniE4
bWTP0PaI8gPwTlW/lc/TIQf5DndvN5hR5T1Lp2hZZsIt6uFxBG5YO7y+h1IiwrDhU3WWtMLcooS9
27ClR0Z8IcX4LgD9lPytGItemoIe+KRiS4UOLlNVSB89TNSrdBhgpXbOizjGkd/HbqeWwiNZqnGA
8zj+3kAC/3MFACdpN6VMA5gAs5fPr+M1uvlrh7R8cNJ1EoFQmt0wB60/a58qbd9WvlzKMFhIyHav
VWM9Z4mT0eI/xMFGpQZIz5SFJwVWLDfcYKPvf/q6lVfpOSZmAOw4eka48Xu56rBBDPnPD61X+qZn
1oTIJzc1oU3pQ37YknezVOFONYgED1A1jIbxh/euCWEJRPORf390woSbSth25anOK/N6CbyXAWn1
2TciwzvudbsJ4hjKmLex/+QIHz9LC6R0YDPShvdSe03kovD6Izgg+mka7xg5YF3W562XAG8Xy8ux
jQ3OguS2myOzZ2Wn2Qdfn3R5NHehfd3KI2NOe2/YpY/zWcKBEXvQvqsIdDgL35n2xOCOnzHZ/eQW
/PLxNgnuDBxd+NYSZNkFp2CZNUj+AP4q8oV8Un1Ncyarenn7xp3V+NdPilDvhwGXqXqfJeCi4oHX
6y3pfov2mgYRhlWJOmhZe5OXV4ys5CrDco3QluFqFyBFok3F9UsP3aZ4ZgTU1y11oUpHh/t//+/5
7nb1V2yR9tt+JWyUUzMRZ3JpYmkRSlqnPBThQbdkQPDEGBqjDjJfFzbJcKQ2CiedYthko+rGFrxU
TrUqIxEMl6402jeb477XKU6V+geyt4xJF8sm5Pl/s0hmXT7G0tAy38XUoKRXFShm2Ap+tUPtJLbP
SsgFgiWybM9vbEZFr6HRZ8qIrCzWn48x1Cc/ldh3vfGasvfcJhirNot8nBaFu9b2JD8Fh9Ur8Uqe
aU+xenxn4d/5ysebVTuQ/fOiT9PdrDytlp/JlGSDGo72i5aDH7cbkMw+lIoOmPaGK8PcjstKsQUx
WvM3+Vg3cjFq/+P1sfMY38NOiOMHqxYpZUdVThVgojqYarOJlF5lPmyab5JRfgBEaj7oBUKy5QAG
hQXXxikb8zh0nWbMj2dtzp6WzyuTdYY9yppoNGpvRgPbXUBGIwUodkswVtVKazY14bkHlNvWVzVG
1CmDDlGqT1AaNucQBsC+4qCT9Xsymdc2O40uZO1Ke6VzyEWp+aIOiocRDkHz0CaxQ+1pOJV/6qi0
8Ug/T8Ch4jqOPMSUM5Jwino02VNmamKbZnuLFkXGINdxz2tp50LQPVPIVz3TPmX1eWdS32t5if70
blJbSOUUu3xP6pwM8S1BffUMAIP6IsBVdbkYWzbGl5eEiI7QooIVX3HA9xndRfL1dQSim8U+ca2q
LKtG+BL5V3wQAImSuoA4MA0Wh5TQBKAe340YSWGP3DxbMszc55vfpGs2cT3ZD1LHBs1TU2ibHMXc
/Esbt6dXdFUTxW3CJ9FixwXTnE9B1pp1e5HVKBTcxNQ0mjV59MYcxRTq4qRpBa7ssnFDp/FU2ryr
B7EgpcXbgeiGtgPabPX7R3BllEQH0jNNtwofWEJLsXwrfE/iUha3IR9wqOODIN1smRN/a9TM+kLT
TY1QBNvYowFnKLVQBHgUWA1RbO/tQVlkuiZDzqXcxdtbBgnkYZEjAYgZU0qkBsZJ79NvmVj4WDiI
bkJPPvzmKlPm6vVA+/TLRYJA4p7E+w6AcJDcGKVfpmmePDjR+XBs4mWNHp2m6bNjfKiuZ3meqOv/
ZCHpjt9df+jP+JFfkqtu9H78FeM5IZtTDQ7GxPaZSgH0GCDtOz36Z1s/qp7fk5EiiNOeZ/qU6KPa
0Ud5idnEwXgUTlbonrMuyS9Eo0MQYCCydQvdMGs/bp2CWwGAq2GEiAIQZi263DMV1dTM9QV8l0ov
BPj/Ol+xMcQAeTLWGHF0rnamAlxCx7jgS+T5JYzHUD/yXNYV9tWL0KpnqLGruFXxZ6b3qdVMRySc
5PmoqBwxaSph8tMwmORPRDKebqFEfEKt+RVBT8bIlvW/f7rr+pDoLsJM2MjvF8tWXqNgU3ENJqT3
mt0vUcznMyTGK9CC5OgADks305wAg1JwwlXgvYAdwfUD+MTA7tYAI/dnR1Y0ezR92EbDgKNHP63S
KXQaTU1Hwyf/Ag/vFeeB0SdXjPVOt+eWsq7z9W/zIA0SpeRhM7CfWwtsrO1HluU4qc9PolNO68wD
30d2991uHPWjN+s+VfyBqGVht/VhsrNJ11XQMWJul8AUOysI9fPxX3HIy97MEBXBDzqZgSdT5nIk
bYGB0kmY6LebsqFpkT5r3w6dZUokAY1Itnivu9eNYsK11v2u/aeVOltJJ5jFJK0lYUyZuZYFXoSs
YrDUnNycUvqtRruWXKB8gHV1PleaCrvFsW2YzkXcG+jwhFFbJslKjizeNfCA8ExZlqd4Zy38xfE4
H3LdP4Vrpd+AzME7+J+AZc/B2P+uqUMm49RCSmN0OeXvj9OHc5t8HkJ7w2lvrQNsxFePf0fIlPmE
acIB/qIKPewIQV6N/9oSjGLgUDyJdcen8PZNQSeOuDzdOLF5O//ARByz1Wrw3tXiUxYf6pqYJK3N
FPenNfl244p5J5P0Srexj5WY1m6j2hz3TQjPt+GxFSbil3h0J6cd1u9wW8jcFcImoAUpjRVYZ06N
WGAAU9/++cfolOTBdtEVjtLUQT6/zoHvfBom9SHx5EeKI4rH11VEUznbsvr24oxJdOXA8FvJcVU8
5AncgPNTL2EIAXcwm0LcnlqwtTF/YeDbJr6JPD1HXctHLHFnLe/7pV1BLCmY5LBDLkOdqz89tpnT
/UrkbE5MJlLQbobj/4gwrDQZvN7vfTBTJFwQTvdGCXb7/AceR50Tw42PtdgngB4UH2iGjD/qSed6
jcZ8ZxA10b6JJEdxmEoQV/tVlKxb//80jtZS8fxrWGxHqsuIRDUekVvQbTbqFLhghhCT36g2p0s1
9GfipZ1QxfOpGbSxjl9opxuckqugO/bD1IrLlwDsqePMcnXboktTtEcK0UwOEB35SH7J9glohS5r
nH9vPVGqQJt1NSFtGX9KIax2ujVD216GwCJ/SJZEPqdktT/s+DqZx6Nx8NeAyMcTlKVDIygxlnK/
fiDSSlzGYlXB+/h2wYWn0fy4wphMr0lStAnQjRuaFXmtaD/sUu7nN3serVoHoXqbfREmEg0PXIqN
geLV5MJbdjztqf+vCPJsnk7mnIa7ZzB6ynvSI5jWBbuB01ZYwovWxd5gc+DMMA2JmSt8zwhnUrnf
49kXLhw0jU8hS//7kSwAjCLxyqOkAx7KIGqAW3MPmmQbThxpUxCr4k50EYTpCVEu1iWjLPJ+flqr
RFkUUE+DmeoNNuG0ajyq7yHQHjLcXwRpgtfou9Mu0fCtM0Gn24fAioEP2KHbnI4GodZ1zezMyMVd
kmiy4ykD4OMQquAtcrkLtk6TTCS/cukjw2awELZQZz+7L1OuR3E4cwXd8tLSJukfIkuiZHCS6Xzi
H26Y8XS5ENGDGquHqcpK2Yp2Tp86Xup2yVcmNvH5HS5OtNcUSKodPtYvk9zSxM2BSWjskZh1+fEQ
LSp2hY1YHrTGPLx/vDMIZ3+lDjbmI2wiHh7zkoutuXpS2GewG81gP/rauotS9KxSwAeBKYySJh6p
VGUWTjU634D6DBLg/ePVhog+ekyxsuaaOYj2uOO4ZdpHl8NdZWEvabEgFRxVQJL7nCpue7XEDVEo
bySYxxcU14RCksUsONoupv8xPI5MfcRbuI/5hlTRAoeva8B8kaYB84tSxjOHkG/IQrKRThVibqaW
QpwJAJXaOnybnTkp8ofwp+UPhbceSxtyMaBvaARuadxlVbFFYle7CMj7Kbt8XMdhCl7n8AYuhEmG
++Y0RHKGaMQX0Swt3+x2K2Oj1NlFmHDHYAc7aPpgjFvcHWhAaqI4HPkqT+AK4p7o8+/ZA5AI+3gy
e+vcWnyE9IboyHhtoxtawJRqtIoSFpaV+ZpJEBkMkViMVO0xmmKmU9KztY6EAgGGd6On7/W9HH5K
tfwFOBz64fRcsLDLpK1vVgxFmv8Uj4ORvaq+MjAPPMT4X0xpf2dVIhLiZJrvL74UrUX2oe6tqYgD
FXMDrVV6c8OniO8kkLBAmJbmXpjBn7CYvSZoolX9taRuOnwiYgJIREWBLb6nZfvZ2ZSDGqic2pe5
+87K3DHEUVlVpUfmd1ZzPxGN9gS4h9y/FGzQftJHKvDh79FhuVwGNcNIvjZhyPArdMjuNiceHxNI
YePMIvPT2h91eD2EKQmQkIBNq4F6x/VSUnpxWqPYLkpXAF+pZkZU/+vyUy58TUG4G7+LzUHYHyuj
rFGGD5+vvuFklA0vrf96O/P7MD6vhCCkE7169Nq+8bAWhC8w0qF85qnqkenEgDCGTkzVhzSV0o9W
F9UX+Lfqt/ufJbiKfmFCHGuhNsnEPAoVIF7LOO2rVh0/SCbo/dzxZHkvKvoSdpXOf7kh0IcxDHSN
vwrsFaDkvyTUFrLgcV8iHZxHuPQTz9JT1pAIE9fc0bz648eoltsuxoIUAoTmtP25O/lUpEHZL0kp
vqbhl30/hhvKCRXni20y7ceTMQkieNcdGT+G6qSnD3ccJ7t/qtt+5yFcIY8Lam1AqifIbOCxY7g9
YgB/7JUN+sCkO2h1i6MiCAl15EDN48stQzcag+9MB/ujebdOx6HAoF2wmlpDVToHzFwSu7pw32ua
N0IWEgr8kKErh5vQHdSp/Gw2xQcSQ5KLf7Z4ebKOEwmFqVOaBJuk3+rEibK+s/PODSLkva+KcKkD
tBjVdGnFaHWSOxZqSaKP+zp/uLDZ7bQGCKZTn+Q8CdJ1HPZnkSXTpcRoD58PKivpeg7ZNkAutJjn
YRp4B/JhhYIhm43ex6B0jvk52v91qM9k28Eh5hHaCA96wi73UA7pluuYB+xKpSWwUs0u1p6/SvwD
wtdxqgLb4rhXSzwsceDEC4ZV+qvUU8Lqqz3ZKBOoNTrri5/Vkx0V2d834QBLoEDdUMgC33rEpAo/
nBGxhwPOIgekmSg9iN5/SkroJ/47we84NcNhfdX55zOPsnpUnDxffyCavCq8/AznbVducoXPJF7N
wSXx90G2O659asmnX6TahdphdbsUkiFAdySU3134uGquka1Fuf4+0gBUqblDw7splt/SGWQHdRpN
4Yt4KLthcmsRcL9w4Ptt+l7Tdv2kC5T7ggaNFS9a0dd45qg/GR+OdxLSeBebLD98cqRJyMZn1bBo
+UYWuO0wvGWX7+sx5urxtPiyw6WAsF+EaTBh7jyuNFIpeJzfqGID5oHq2RnTjcQnWGKLZreRtWFC
rDlqOZMNaCBus+D9MC5fUD7lQFyIFYupqUL3O1+zblBO4HOI6eXJ35P5CZnyrkxpSZE35GOL7BQo
WIa115ZXCmBPZ1vsGz3cW/VRxXjellA0chZh5yWi3prfjOCJm4iA0qkU9obHDAUgWASWIbE7nfFx
UmcRDQNS/JMD4lHXkmwIehem5joxDWZXgn4loUym+IO/7ZqQ36z6gRuJic+GpLXjonQa8OJP4dqZ
EhCMvClj6+KPnNUdAeyECBaxHgYagi73N1il3bnMPQmBq9Xwy4ErhwGvoG2/agvEisLE8/5T8Eq2
ifNKrbICVtqYkjWj4WVQVVDDNITxOqKzisXeohSipHd0cHBL81zCykpwhOkZEmKCrfMJPO67qSfG
2/fBhE8V5nd8NC9Wz2QSexB5ElEhpFH6ziOWSTP4+Ve2XHeeweMX6X9K7bJEHOfYcgmVhAJcVFnu
naUeRItVJT78mQ6gem53UWk0iPj67erN5ol/NRWWG2rpe/oReRZBh591bw3tEwGPCUG3EVf42Gi/
Ab7WKMcRQ0FKWGa810191ELmQXZAR1V/N8PVUqNqk8PX3OOrJ8frJie8Y6w1abA1ztBhoxzo8DNE
j1pRBxQs+QJ5LRF5Ai6pmdnxTLboM/f7kwr5aC59WtpurQ46831AT6pulbGuQPoZ5OS+Inq7xeqx
8opbbCKbbB5xbCFCXVpkYFr4pPHsUTvJY//RT1zEASe6iMhJnYqOM+MJxRvXZQ4LSvR83ByiJEBK
NGv64SuJzmfAcM9VlKLhuiqFky9ts1g+mweYuM5w0MxErMkxFIoyGpiQiYgVFtwOvB7m9uxhQBJp
oVSBJCWKH8lmCi8jGLbtmUhIPxyiO7K0vqUUKNdeNGowyaL1NXB6WSd/Wh51QI9aSVeho1k3vIsJ
Ysb6N0fpH58APLSYnF3wP0KCjqFHUs+6YzFLhoCKMhnDbbFFkaVyofa1hhfLiiTXWHdtIClcnLu+
vBE44aKDO6bovu5bYK6vs8/q9jldLyAJUwfUpi8PxcpyVWBh7eIAJjd3u/SHCwLDYKpdJsNYfi2s
Aee7lYNiiO/crpiSVeyuUOG7/g8xeXoojo+asaAvVklvrpm/5+x83dGJzwkEcTnQ4kmFMHB09usN
MOvv6RtvrrHt3HdPYNCSexmKslvRu3/ds3TEdfg3CfNbGTwqn8fAUNZLQeZu9V0/0yG/AKNrXA00
iiZWBfkqVUeoM25v8Tz7rEoFwinTFIaqFwJpYHwzrugsAsoJzvtve+HdcIH8C4s1QtzCFlz7b5wj
sqR8GDiAd1d1FKNzomO+nd4RVJIjtppiY+1Z+T+1OmxJppJBv3W55CDfVkll58KAgX+sOnJmvMWT
S/RvdtssSL6EhvVtO7aAIhqZie0Urb4UO8Irm+ICQce6mRmTXkTQ8DtXZfF7yBLqDgRqLWpavCCM
Sxxkk9EzHeNUo7lGGfsKqDU4T6KoNwn2dlYOiiENNNMxr+DPsxPfYCcGXz5GBbhQB/ME1Gvjz25L
aNvO3/STWDV9Aa6k5Ds0QCFhZ/i2RATDtxE9z26InhrmDsQSsaxFbML8TLHYLlNQRM4LxMxiV3mI
xNNhEwliVZhCX7T/W5rWP5EvgFSMgDMwVSrqBuT5ODRIHD55RRunI7CJ2mnn5JqkYc3gYL/ovdFy
88oMLqMA3E2tA232qgVLNSnnvcBjVw1CEYovqqHIfGI2tMpfFvC7iOxd1lgdJQ7egY34klDPy8rL
p30QprKJKxum3mzgEhG4d6sF2t06mq/aBpI/uhGYhD/uWhArsvBpnFWmA8KF6Y5uA80wqYUlFzbo
SFRcU2pCHudUfgrJCUgMac73fHqrfB93vkPhVlgYPx/PNNcBxB5wpp1rAiWNVhGVQMXGvGVUD6QY
ekBlyeXyU5rEeoCNrXbpDGo7ppGAqHeke8m4txXgYkQ6cI0fohnjTnjAMB+DtASSXwdr9SHujHlT
1B4TeILyWocV2Q5DHiPK/Ap0VfrSDmdJ8kDuMenTkqliE4LkEdYPjs6ZTve90QWkCkjQeMrrMBGs
YhV28UR0o7tLnXNhLz48h+CR8jj0xuh1+LktsNQbVk0a2fGLw6U/rp7K7Ek6k7mSbIq3KIzDS7XJ
LAYSnLc1RGGmtESauJIQ/YhbtdvVeoUkDfzTATV2fSy4bzeiiJyYkYNZes3ybXm1EqplcUT4XYe7
39dGeHB+gC36tjaJePE3MUGNYr1SFV0FCjPgKdAdTN5lqK5ECWdaX/luDlZYZdtZEb7Fi6NXlY68
BZeNdPJiYa78CUKNVT0Dc0+7yAkUOAvkO4E6Qoh6SN7XvfrxkybuO2B27koWyVkUvOCR4zK6oWxI
5lgiUo9Hm3J41uPPHL/JnA+e37IgIH3oTx8Wrboon6KzFA/TUubh8tLlcJblLFX+LkTdiAi1MQ6n
DJkYjAgfv7T8wBxmmb+lqj+WIAmufuL8LoE3caYc72D8M0Y89UjbwOkStZXv6BVPMpKxC/xv48Oi
z12aMiQDLnFS60FN2jsSpCX3Q3725x/8JpOUF3YoexR/R6YWg1mo/5CqtKQ/34Fhaply3PvZsmRR
R0/SmYbBqW0ALZrdKh8Qmif4II8srhX8jFzK9381zZImGrbKHVdISvozq3Bq87PrD8pr3HEvyAQP
5eYHrauv1llHg93PqR26Jcwed5bYVV+q1Gx34cg0Yn0/PhBxrdU3wuDGkSf/QqxFkRQZ7NhkCzoQ
l0yNTnEReqXmAEf+pYuYcFXe+lQ0OdP0hLlr8816d26TlPRELCecVghSu43S3OG2q+Ut/Hl5Esfi
byqm/XNglNkbWuXL09ruSiNXQM9s5jLCbpMuKgG6NrxefWvsOmYCpPrR1vgDXjT8hErcNxCEY3Jm
MDLbHPjL3Ryso5sox1hKUOZC4DtUWDfYcLkNWvF01MBqL/plfv6yqsJkrUyfmjdFugNGXpX98Rrl
KfrhO4hFY8KknQ+eNRIGAV7jTDwulrPg3bq93fih/avDwYItub21+3EyFcaraPOSwxDuohg09Qti
StgNiP8Okwb/45YJtrYr8uQMkxxtbd7c+n4ZNh0GWE3ecgJxKQUs3H6faZoZ5uLeQmql/KhdYA83
j7V6tyyiwpgAZQKr5/PjMKbCWQMJXMudB4I4OeThZV83bo3Q+CXjUsnWPGfkb+6/73i3/cZG4sBj
vfUD7Yz1tMqW3dY9BXt99LE4u1G48G0Bns/KdVj1gtCt6+Di+YjaWDWAdOKTvxcmy33XAD/HF6IJ
1n24wgCVAF7NX+vQJ8IbX2MfOV0w+fHJkf0EQzNsdJnHfFY6tlvsHuPLGJyhIm21qy2o0xOkFkDt
kgZoIgsTsMH3hrcia3xJTGfowDhkAieOialiBb979THrSIYaoIINxRoLkCvQhG6aUcjtkQ/Yclv5
VtPw8tNz/YaQi28r1lFE063UrzMrNRX7UtE1is3jePMopFyRkLP7ydrkdsW0D5oTYNDAcpUiHApT
sFIyHYWwXMbZ1AMNDkHBXUla0aYD9Nu3GbfonDBjn/SZFRRVwwqBiWglGs95RFB8eQUMDcYBHxBS
fKZ7OVZVUxXSonHR6FpA/f7APXhR+j8hm/bTfKqvk4fWgMe12alpOnOWAoKR0fe7vV37abYg4YuO
rlkVdilLVFyIMg5y+J/oegIPSnwlFSAOcv6wrh3HGyW3aLkzFhCqsKjPZRY8tly7d2LjmVtXvht2
/Q7PU+Ao0ZjXvCDlUGjqlvdzSrbLBPFFKmgZGIsVVpPXm7CJYR7/d4582C+73bSoVv310+HC7S7M
VGEf56AcO/UaT5/pDurRP2jJVEIoyRRc36NyWu1m2pceqzeBOxCy5sJMYQXpGJQC6aRWxfhFSaCa
m8S0+MF6OeUUbGVPjSiWGC9g/3VX/zA/z1tZVuEZHOVc2LPUJvrlJiJ6G129DhLcrS8Pob9chy7a
LjYAEoo+bwQrqGkEWe0ehA+7WugIasK3p8tA+hH8L1SmSP7qbve8ndae64oOG/Zc6YB/4bMS74U4
JUzWPu3CfDr66hutMWzonn1IlZZy2r5l5Y05KZ7J86J0gx52AbwdmZY4oB8gOf0PWtoLWinrJ7p6
iEwzyhPYnYELXzOcO5X+imQHn2wYEeR4WoIGN2mn8jZhOC6BTWTm5PXPtN7CLJ186BiWHrfQPdZT
noC1PDm2OIdsNr3zA5eXb7fg/WdH27/xdC6TAVNsPkZkW+NOrKEVpvoL/Z0weGg6qMamBHjjNzuE
ejqQgm7WSeXnenk37WjHZbNkyz01J5eJ9ixKgkTbLG+FFoO70fRx0cDVo5ki/Tmr0fWGMLNyohTT
tmie8E1d9IZU0FoEUCV6MGWBqDiQU7QXof+6jcFtRsMVWfVZlmzT/yrYaH97f8l/R0gCuTdEF4ss
td4ejWmb4Va6RSZdODa/R/Jd+Oajh5G2wPIzW2j+ShrKjWJrFwbzWv6BXeF/5pV12HVttvDuDDbg
iUWOwnuFg9SrwOHAVZFDIjXaldkUBlmbKlB9C9dT45dNE/v+vCYVXeWh/vyQlx4cYSG2/ZQsBE/y
PUxKhFfuXve54ohA4YJY77a5W+8qHorEgMRmhgqqiP/n2fQ0uuVEGpGjis9dVYIuy6FhNHlUePs2
I8/YeYdy0vWhgukxUAqC77tSe+vwTYyq16fthjREbZtAe7WpCyZwB6hxq4HG3of7OYxY2k7Iy44e
aoFeMUgafN6rt4DMXSEtoA8WSYpqYzVJbTdihowk6OyKxkl7jY6YuICyknIEi+Q/CAe5CLaRv9C2
GRrPOb2sQ+xbzJk1MBWF3OZaFPlnog/Bwvrgbjz+/9BKpvUpxbW1Pj+6mYKD3XTm81tnA+zVrn6y
XN/Swll4k9QvoUk2VQQTL4fK1dlJSZVnG+tPjaHZ3OOZ46z6T1Ny76P53+Gp42iTx4UeurPGhp1Q
/p3lasXul0O37RlkQ9h3Lc72UtLdXFwmcYlDDtP9bqqAMcb7BLfBC5OfCAUXJxfdBPXN5wPt6TBI
WBPkUknqhy+RbgZInQlBVZf1+9WyUQKa11a2xwOvFLtAkblNJkeW7KTyCPnSeAed8b1RiX65k5YA
sZD0xC9v32BBYzfvOnuINVKXQ/zAzVjNADY5GIY0K+AKv1LUe8SElscvYiX2O5wlPC2HyHJkKEwc
xxWkFnTdFLeoMWNMOQKClzqqWFJdOSfPWV89oYifPHJ5jTaqVsGjAnoji9rTFuCb3Zoek/8NYOZh
KT2v7cT5t4u9ms86MekU2bzwZjbsLdMrKznL0+9jno/pcdJixll4l3OS7kyl3XAPpltBKhnY+JrR
PLqQoJMiB88d2lqH6eCUXCgM3KlEU/Y2MsyR1vT3OvFdBu7H2XpXHCvhXvc9QIUOtfeILl2o8mIf
bOWSP0eJWzDntN/fMyyRO5LSCnYUwEvFdnLekKFuoV141wrRl0Hj5QLWeWA5P604+HOVC+fdVMJ9
Mty3oGh/pJeizotdOhnavn+NSy3UZvZ9xFnqn/5K/FpTtGYuEhKSM8Jy8a810IcuX144/7FMzVsG
PHcGVJXNlNxmyCG5McW4tI1bAVhWRh5zroEu5ikTZWLTbYojUS/n1XCRiVdGPfwmEPlSzEjHgUZf
opKE0jJRyBRMx8WhK3RGdsN+hagfYoCRJUM4N7tQcDokXvbPexbVEtlPqzrC/lB5le6ipLz3Jrig
rAOupRw92ZzP7HDp6X6ZopAH2mp99y658+y0z3JNkCcfMkM7nK+8JOq282J5tBzjkdZP8AAZRZUc
ridmxQcEb4O4NECJ+awPdr+FJzBWFUGkONB7gY6rHKAwM2GM+9Hmhk2JxN5z1JTswG1tcYcYg6G/
3/hOCCkg92TD2QW51uQxKmnZ91H1SY71nfPO16VfoYB5UUJGs2R2H1MtNBKLOeUZsar/6Fo4Lrck
A0529+rW52YnKYlhqDFYVwrLMWScmdxUo3ra5El7E2K+YqMZG60QzaADD8nSzaQp0+sj1/y4xNDQ
tFvaTbkMUhqo7X8tiSO6c+3PO4OFQ3nBNVu5ySAys7GPfcSjgApwAHxAgkaM7SqIT9nvO4Atyxjx
DzncOTKxxsrTdh1jNd6bu92CYjndL3iEEdSsckiyhUGTtrm7XkV3ehpWLoayt0xBsZgm7hr5LQi9
x1FcYad7KA4/ZyiiH+okb+c11SnV3rQrRmhZGu8LKkTjnZXC0Rpovzy+TjBHxIgEFTTdz+Z6ElXu
j7b3aSSPR5aaAMaD0qluVa5TmJvqpi+qPJj6QxWc45A6TT+Y1LG/7ianPPohZ0/FImhzrifQwUPm
vcAryWhqH8eiFydLpObNP9iNOs5nawFYKVoxm06rfA0gjDUwuSCirLXueghmv/1wHfGMqnYMPhyw
MaL9SFAEMw6hrI5xKSrfx6sI67CRHFAnTXao7Si4UsnsL5BwykDlZdbCAacQthPktgCTVi6MzLBu
Wt89hKHmDK3qGmxL+pOx48OFlgqHWGgcxyWINknohKpHZ0HGcEV51BKSQIL5Beu1OyJzlSjAeUvJ
N0L4ZqBaftV8hHzkqqVQ+74srXq+SN6oGoCuqaO7ospHgynr+uZychqcJ8AeiifZJhD/n8ZMlpVl
NbGo9ZBTHdnkkO0v/2sk9rHBwE9X8cJuW5maXEJuY/VzNlAOn0jG1/uje2PzjLRQYuX3ORDklfT1
pfy9VvWyk3ka7GjUcm44LcSjoV/wfUYOfJadcn7+YdhRMop3pqqadYSVbJnzqTxIjMdPnCHgS9VH
oSZZJIO4pDvc8A0SqXqDdc4Z+utneEv43tKqKsC+w/uxeDOHBmNoqcGIARi66Qv9curD0ZgD5aJ7
90xOVs141QqQhL/d2BzO3KSFZAgw4qfj1CvunIcanttXGzD13/pa05lNzQCajsq8hsz0lWPpwq3W
MfKP5sGpHOaRYYCRcU5Y2UpI7N712Tq+NGmmkm+8LFWcqJK4dEt5bYlW09gEAX8SBkaeCO8sLPLr
XdwkqyslXjKdJ5gVcGrwqGr9o0W5NwOAzFzi/rVaMc6zWI4Atc8caQT9162OtUrclD1BvQq27kmK
TeAtrhZbtQpoPThYZytCBKQIZiTnN82rCcffEQftXH/NhgtobzSAsArelJq5kanD3S3rwmZOc3tD
hft6lh2BzgFN6SG4HrquqKbjimWDYh+UpOn2fqhm3MPE6bNr+TFsxtv21On+lfEgqHZ4J1h+iyZQ
sFXsK9XNR/oPFLY3Wt9Plt8NT/+3yjp+ksMi3KV2gZ+x36uwFHyyCQP4tLTiqrcF/22qcDoVS6t9
DjjoZgSDjSJf3w8Dnl2ANW0JU/es26DEQUJPQEgpr+SnZtL002MpxF7p7lWhJmkIr1iZJ0FrX3Ik
Lt5/Jo8uTQqDlCCdaOkwLAXXcE0oMcFQw4CEJfyzUpYTVrTZb9a1BPeRBPZD5P12XV5IBYbZ+Clh
Vv+oKiS2cylMjqP5ls38H+NGq+apDPcCe95EVaNYved6sr4YDYQA3QbVKbgxKS5i9AvFd+dxxEsr
StGUF/Q3WfW9K5oKZqgkGrACsquzA1fDEZRDq78w9IdOoTl4KeTac7Ap/lSRIAVbvbnQ5dxLHUH8
exzMOTTA7ZLP3V/aSi05BbO/bGjiarmtvRcpLVrN2HfZCldh1PwA203zXEwubNhe+eS8XDaKT/yi
YIZgLpPMMaQZocKkUWxgN/GY384oeWPHdTlG2rmcdGouc4kSveMsUMwVX5aRJ5whQyIWYTugbenY
6gPHTIhQsUmmYjbT9vXD8W/TtBnEvFb51GU6gy4oq1tyIUt+idZWRqAhlXXYIKfEQgphOYH9XCBV
OChTHKr3MxvJiqyWOg1opXJGmqalkwWcij7ShzIVI5iXK3Rr6ygLtrjRCc63H1ly/h2rD0VNtc08
ZTme3T0OSBq+hpck8eHno/alJfBVmZb44HRy2PJ8bGVOcaOO9Ihy/O5RWh7VtfanzM+qdplOtWmn
tIWGYZWYBT4xtiH7wsfrrYvg+yxpZt2ne4zzkfqWevvR8jJCRTW4Qak/QJ92OOWtRRTfIO0pqtFL
SHOdKTI6TaMVZJPs55OEC5gaqdludqlk8rysAT3UxmTB82ofDVd1QLhgFhCmNUAnSz9J6HYxuILp
PZzOesC24csHwgt16yQb8eyLSVkYzw7HeXbYqOtM9x3MZHFqvYo3iq3jXI6Xpi97sTa38l4OSE9P
cAhcLd12Nazf7T+MvsostPGFuOM0XKBT6aRWFGIk/VC3BCDQLJbT7+T/tMCjZfw4Tj+HrApoCinH
JSDG2QTQAcWTxyNnJff//oiwkp+90JxFT/lNn4z6HbbeJazskTXz8J6ox6vIlgSVIL0/HCgB5sEa
xEmo/hdLDkpBxWlDwQ+oj2iQ0h8EOWANgOqKwKksds9IdYmI55E15Q/UhjJzKWb43rIL4VHI99fz
hYkSzihMbN+JOrSgI4y6vWvgUY5SgVyCnfpKDdid7Q/ESQjJ7CX75uQIL0EfBsmejulZR7lawF0m
eU4K5OhRc6FI5+NB7qm36A8a5gU/l0Jzr663Cr/2ymNItBL+LElwPZBznUM3okbZDRetZMUW/NgV
ikvkcH1yirw+3t9CHz+GqYAP8j0bhdoQTllls/6aAeC+bkUWGN6ATT2meL4J2qUZPrz7U1AcdiUM
2t4pRPVLUbFIrGp+UhTHa7lPms6/f4bZ6jh/rO0gRZbOQiMQeFGbbyuIzE9X/tOQPkHHuHse24qB
Q1dC7OsgO5P2ngQ2WImR/4Xe/B+m/j3mRFbL6SGpvqAvsLceShTM53NJ2Vb5cPPuxhKTn87rBPXn
DInQxasWpr+NvAQbIR/l9oP3YoJcDD7ifuvo9fI2FhuW3Ch5nxKpFTvqf6JBspIsujb+zvIxU1Xm
NBJMcY9mfHzsabe34o7qQiGU1/ON7kA5bCPAa/Isl2mXoqoEX/4WsjcsvR7kKBub9Y0uA+bYUsKI
Ykk3O4iYHCxA/nYRUlpJ9EhjZe2CoWVpVupKLOfnRBu3NNviZXwi3TqIb7Jnkmk7b2APHsIk6p+g
X+kTTlnioESDfuWdo0tUPyEqUNeppTjcGFk3Y53aDC7vuSMmXxGXtvr5qx4Jtv3wmEY+OqFq9CJc
BOl/72d39XuRFTCvYbNadQIW8BHYDXcN+tO5unKgOUbmz/7Sn+om74HBOYc5j0HAX2r2ajEeXpxt
O/8tVDVmOMPOoW1wNJD8NvIFzQvO3zvxz5FuN0jH/bP2xPy7IJ2kkSuhPxpdTaLi5TuWKgUHihh2
ersMCVtKURunSXH6ZeT/XbDd2Z5kcc304zBn2Sv/teP3k9uAG9OMgHfkA7qtdVujWtK4avckhfpP
hSX3Vx4PnRvdV4cIry3H9mwvzu/fpyWIpTlSSxvJBh8u3olzesWoiYGAiDJvp5DfVLMKtbbEtWyx
E4GncytDVuluNwW7gwLe2gzWFhdVjiHgewZecEC5gJwY1UgxVd47LLhSyA7EguGT8v5QBXqurSfD
kmditvyW7aoV6Z5GzQtuMi+iyd4HKBVlvz2dbJIEbj3b9CvYbOE+Z6EN6JR2unTkVxYbZABJMrnV
NPP6DI5tAMnLHM7fNEA/fysqRsLsJFHSKTm8+2NTprxtzEtBhaEt9SMGBbAsQ5MH3p0Y5UHUVHk0
SibhE/cmzu3N5CIEzR29SGZ6tuSwcQsqNMjsJRvfiuk0Vsi3M2OCvyFGJQIwlMqePJogMBG1fAW0
HGYRfAxAjCh1wheLlxCZiyMawigvtvmyRuB6VuqVqFaA8i8AnDQpXj4wR6ItbnY0G20p/U5AkC5x
CAnF2N91G4UiSBoBYGqcI4h1OMPceKquonlbuQEn6lB54N3BnebhrpzlU4r7C/F9vCzF/XkveKCv
dpRqxc8Vr+ufx9Cya8OHrafM6VDfDNqdO7n1KjRYMIFrJ3/oDCVDel8OB2DVNsa4sDGLwCQWSYwL
vH4aYHCmrP1nkKuVx6q8OvtkR4sLHQNoSjs+BUJSqjZL5EZRrq3kIlcnAV2itbKIs+1eFHX0kteF
9SaTvssQPfFvgc/88gIR2KFtGtVxYf2+yjoOtsQT8FWap2jp8LZoeoR1YtHE/yorPcP5oRpRI3TT
AVtL5Sbqr5RdwUWHhndWPnKvCDEtxXZTusyeFXvAJyO4aEhRgxrSBnH9wE72UT6OkvNBgWybGCvu
lcTyuytI3ELhYXyt9/4EvaTL+6CJSwddG9r1Ik2o7epNzoChIXVuzRVYyycPXAl1lxz39twSHNph
RiPZd/WedAqzACHdNZj7eTprD4VNOCxxQ9wqDuy3/m/icLIb/51yHtEIECo+/ELL6VPTDxNIoyG9
zQo7kLD5XmthbcgwWifTpYWvYQoLMDC6blJCQhugjaDRGeV7tsHSh3lur6HkXZ7QLxhWsn/VxV7r
16gSg3sZEoozA+HTJaWvNOASzjCsLkNtWtWAwjSartn5LraOj4YFsXuVKLeEzX4XNrz2fsEW2fWs
6kctRbK/r2rghfOpH0My80CfkNwpGA/PCsifzpvRqM/gD86BHqUYYOlPs+5e/zYcT00MHFsqvp8v
teEnWM2pkrskYjsfwvnOQIokT5oVfzsWBBbeOGqVnez+CufObe1LBlRJOE7/QhMgaGEGzDVhEBsn
qn/yw/idIWZVT0tgevi4K0xH4Jp7SKQMUub8uUBMtzJhHMflrOt6tNExLRVoFQNeTylmdrTW/5RS
4v8ADHWwPmchAMI9tm2BEAWcHlmHNQ6F9GTUdS6G5j4dIQtvuBs5ibl1FZ0dU+wKHiK20JNE1nV9
Z8mVn8brpOYf+BSeXqwBtVPXKAuPlXcZ352VIwOnCT7PIsnDDlPzw1CzmR9itM+xHe69LaQ0BJCu
hrOf8EESiZkXKR+13RFfgSEqKs+aiO9VjlMMGZ5DF8zlzk6FMZQW/SYd99pqSPWNTguq2ozUP67b
K3XVNZL15Wsdx1+Pc5aLE8UDk9dNpV5rFrKlbWqkxogUTKRX4eE//jThE0z+x7TdmFmDonLG284U
gB2z14XeH2rLLJKwM/hvpSPuMAIts5M+wmTc7yclD73hE/8Mpr0GNDr/r02xAwCmRD8TaZuZnnn1
T8nOc7yM2YHHTg4YM8LgHy/igt/pEHW2cr9GytKba56tlELW1cwEgmaEz9aKok7TJ04nrTnjR1ns
uEY6GZrHhGaPsAgKoLvQ9GX+hg5p00QK2xPXPK5+quXgcC1z3Rt+TCnMypdOXBqNpBxDdvQfOkYr
Zvz3KULVhVTTIOEreTzjmHDpP88fGWH+okZCRrxYFSV/17mNHuaVuNDsFiyVMbkvsM2G68rUSpKw
a8fuLI9c3CoT8P6FcAQNGKqcgPee/Rt6glo+Gy98Pa4r9OJ6AeK1a6CUBvb3w6G3kyBIXQp/0vrA
rkQj2a4ADT9g8m9jg2YnWg+kBrHAAczow18MT3Pix6b6PxtWNxPdkCwqra3Q71FI9qzxCvwvJpxj
Bicr9+ugGde+kIsnBTeai80AKiz8P8hy2KUeTAMYTxtpwv5ZG/17Ye+RS1ElJP+WRhHUm+ehDy18
P+opFM6FGWGPE4mhU+gAb7AK5CgTW0Y6Ho/c2sCBBUiLwS2v97HBYaAo6TL6R9+8T2zX1QDwGWf2
U3qmzrMrIFY+eKk4nBh7GS0IDwxIZl/yKiK3mW8HhGlU3Pcj2yi7X1/ecSyISKZZ49hHmkz+7bx9
R6pnz+Ot7CS7r8tkMQPyul+l4M9daewLDLvZLTJa3GKV4ebA15FORdv7USsw4nqZpbzDGVfy7Bcx
On1luUcRONOWmu68eKuSVA/7XPk+63xuB0jq44r9pJVjttq1IVMqyV8r/NGT1reu3Xk69vn3Maf/
/Goxg7UKcov2GnH27l7rPuBrQyh125AnkbPJuwUWv1TxOKftN7/kVYeCwZ6kHEzPDdVTO/najHrP
Tl9Jmajvq1q9wUueA8rjjFPkYOoBz9JbkCLJ3qRE5VO3iZFM0+zHzgrxzwEKOYyDcWHF8+1Dhmrj
jkMEDNx+5R6exuhxNG1Fz2E1WAF27Pn3GKkOESk3bPmJV8vJQwVLFNV6bndmLqEGOhm8JtD5FjKB
C4oSOjPyDjXBjRF6wtoBPX0/WOMnCku05tgIVVMWZr54O9McrLTcwEsXiJHZPrl62CLFMOySXCyw
zaD3e9BIkseYTLM3gJlh6pKAQUOLMAEWtAzZPpudoqLZK5wItoJgKZq9XeaRV/bDUsV2m4qdJseQ
dZnYdnsDNrb1RbKgP/OEeXNS10adYMTY2urBZXiK/6SFrlepHpgaBgyaueaXec1GY3t7zOUbvYby
hpixCG8Qtv9v/uWduK1ORy3p88ozwGYa8PK7sHLHSAgKDzHRqvTXRQadSgFAR9Ifp6YSLid8wJES
yvHHZXHvz3ehrp2lcrJOVGcpNjFMtyRuaAzaC+OUbhkLnuQ1M7hD+vLylPKpmlqjQoQQM65pflZS
01mlVzVskU5BPvxk6Tykf2rk6YmasrrZ4SPRiC3G/EjHFqCIr+l8rvdp3BM+CSgMSEitzq6JhPxs
jW3zR1GADZGEsopVuu0WE/PdL4+oDUWqIfAMc+Ex1KgxTpQONEwnoPSeiZP/kPECeyAp5U0ksrmA
0RqRGLkiQXqAStgW1iAv8ocSv1oPk8adxkTE9IzjDlRPuPiXwhlq03ceEnAmKucNLIhllhaNCp38
Uj2V1XiFuumzzREMFhR8wYD6mWdo17aDjmC2A2RnxjjGYaSqIOPeY8VtmIaaXXCWQQjwgf/+Yvx8
Ly029Nmr9SDuuPWtrCgophApSTEkqgi36p7oQrGCvrrdN8sGF+Mfns58BS0hfkDLC0iJEeBMqBUd
Snd514NyVp9r+jDga7cxTKNsw69bbURST0SGuRtZxpc9n0aTCmBaKeRlV+1fqp21znvCkl7LEd9U
4HYR+vXHRZ46lymuwAHC5zWxibv8Bs9n22F040jKsoQnlogw/wk/vMMVJqVWbJoltnWKFkNBsF/6
9eKktnAP31W+BICwuCgMMb08HEF5o8IEpD9v3w8BUDfvfjTliAUpH9pihsES5vGE1VQ0loAOvcep
pu0UhNeBtwm/FUf7PZHOHYCdJD8iWg0ziihtuH7W2V35xijsb6Yv0kuc/nrfUNLVo5KiScNDrhFp
3Fr5eploXd0N1w3GcMvz9aZ+2gkLpVVAr2A53h1PhkCbCuCMCO6lCTmWIUs+WxhLhWGSglwnImmg
r6j+BFZaFyfeY903m139ILKoOzAEJIcgS2MVlbla5rxFNu/8+CTeln2Sx3SpRUHRkjLc+SD33Msx
sdF0UaJjXp63safch/dG23DQus6T78F215hMbhXcLa7oExKh7SSNfWdXjBAgIWGoyztloz1pI9zB
ipusYUYu3iJyoC7nnZtTKV5Os8FIvnjvxf5uc4MpSt4wiA22Qospp9v+nk5XGpEL8RiB/lEsgQRb
lmIsIdvCGWacocviSdfi5kMGTeG1XU5nebu+Bbdi3Bzj9g6fDkUZCbxykZ0KzldZrTVuJVPCedA8
/c4PPccRbe6V6z05ojgULWoTd/XohvxFb8tFivGbJmHsdIuDKIxcqxy6vXaGZbOgmGrR8rMep10/
iD5p8IMsCQzEjfKHyJS63ZTmE9WAhUrdw51iFxCzbFcOfZEf+NLPG+sHZIYeStMJCG4pGAsgw9OR
E7ucyig+/RtZZbsKhHd8IpSwr9o41Xtme5k49apMbH3J141JU+e0OxbBZlpC6/rySrUMfxhJ612U
rRsO3DYaaQHRhzknsviW09Wm7XNIk6xvHESFCGw5Efd3itvTCO2LtZF23DG+XETS0YEa9tmidEbL
xD0O3r/KOolLTKN553PGbZGbj53U5yzxr7JbYTmHIx1CS7lW295JLfCKNkBqLUTZjkaMzZbE/rcJ
1CPNf/9iWwSjfE7b46U8Qvj1+YPI2stym+0dnCf2OKs3LwpyICOIwU1eLMot3sNN/9XtrW9BoDRj
kCYcxyBKA9vkOiHI/upFbCuiF/ZrtSot63+rSytSYIk1i3k8Z3F4JKQN8MJ5z65GLjmrBecHl7pt
+IlzsSgYoyrazQ9M72X3bD0D2BrP1NwqUHhe6kDD4q1fh1byGi1/MqyAGnO/IVcOWoMnsd1uk5Ov
f1BenQ68lwwEMCtlN7kjw5uNT8OEKHnpyQmQStfAE7LbCHAjDe+oG7kO4GO59+E2Vl8Lg4J2eCa4
NupV3KuEtjjOZhJ0V+7AVUMstG3kosFXtmHFpNF0kbGjOfxu3CakbtFt3tbMV+3FwqzrCeDmb1fc
6XZBmpJkkXEf53iexyM8E71Urd+Rf4v+ZScGeUcesFmY7YGAWFdZHVf8yYhwuFnYOhw4Q5lPDXeX
22VYPCJ9gOLcxAFwsPVQjD4jczA6n25FYfFdMSA5B3TrPSwJ7LdlXzm/Dc1LKpilnxYzy/fNYP/v
fRp/1vWFZfYvZAM1G47PX43ulAqp8GsmJ+1WGgfCxbutYB51HDwtCztsPSVjLlm/jcIevtLNPApk
WvS71nYgteEyH53uShFV2njuELIwPzbmzzDZBEMZYwrY6+9L/hsLvO36cbCfHZXrGPGGgKotQZ23
+1U1/NSNtmpWDndmccCoGnFEZFD7kUThSXm7+xGKxYECisI14vi21N2oDCzVyhUVCU2O7FIFYYF0
z7j1ViuKb+b1wb6fkUB8n0KFOoyhHFl7zIO6XBXUweO+Ji2VVonw7A8vOUpEtPp6vQeB1FUH1Rva
9LB0uuqjzFRJ2wUFqdSSgXrSKu5sYytjZWRRWZbRQQWuuk2h6UTEU0sFqDiTtryEiBZx48pYiXIw
EDC3Nr/+utBVpfACwi5hV2YtEMqluYmoyDKEyZKtFXYs8TjZhZPPiw0gT952Xx0rfGFHzmI6FjTq
LYfEQM1eDgFUkUQZCYAEZ/WB2qc4APWohfsU3GF83QUywqQC6x//r4zD+g19QAn/FybFtlkd38xW
UDfHcQjInknxHXyxcTT3OtK6LnRXeodRl2J5rSKlsWT/c0WdjyNd+jYk9U/P9gtNq1Y5G8zCnhHH
yUJYUFd3CDKm59wRqE8dT1QjERh8I4KzZRJMl42fusloiu9fEbICfkr65kZiI0en0O/gIihvJzWR
8fd8n6QDB7agikUEizvN+9w40gzbxBFBaqt1epxyN/gtBS9lkinvTkdYEjmoDg9X47JoOd5CJobr
riTNo4d014IcTw92d1nnjWKVEI0SFgzij3Rl16YMSpwqrdodF88c4mpH13LP+7dIBXnGZf9yPQAr
9fi4JcPTsJUht3OP1TpufTf/jSkK2oRc6q9AV/2Gtjvh2jHG/oPEUtFsqEmPQVORcdzGkOopZ8xM
NqJ32iEQnGR7O8i0pUAXBZ1zX82d4CcFTbXFJCIThFAFkcEoYhDVP+belH9MeMa7IhRARKg8LL6w
/F1BwVmUXogfCWRLC1TQWN41w3rvvKLn86Q+cxk/uvAolFzeh0ZR7HTIwJBtd+axCPQYx89jxvlg
MttWQGno1wLVP0JyDMPWMrfP6HryKj9VCcjvXFicK/ymgB0t4HC+kxvSh2orv8dsMsyxLU/PuSQA
awMbSffhrYB/UeEoVuUkPN8azGLLq0KZdCvu1jiIhZ9hHobncQCY0NhaYMfYpSDmH9wpZFDbwlKc
dIPKAQdLlIqk8g6qfbY9ZI54ru13NJKjdgqLaCVudn3zOhtX6OUlgJMCR16pfy0E4DRK4BlG7o2Q
8Mhl66u8bPj7DUZueC/TBJHHXa21Yehl+QYtYwP5oaMccsWzq0tWS0uiNv9KHgQMePGIZ1LjwFVZ
xJ2J7G/1F4l1zlWkrvdUciKGxdn3WbkThqp5C+h3iksXo24ar02H+HeJR6G5uW48+CkOp5Q8Pukf
VJPmncuLpXRWweG4rZF5DKuNkCSoUHpcwd1aL2LPTP43Mhp2O71xf6HAPuoMVDpac4aN8uISrOfp
0k/HnRTtMpoNCDomLAkMwiF+K2oFrrdfbytI8zwnAzwY+U1JFhnUjiF+DPxSTZslvGuu3Ddns1CA
mq7z/HEHgNRfu4x7UL3HEHR9WLEpNTkTSOuguhkEoKDzgJsG/1MHHqObvJHqloa/AsLu/h2o35B7
TRFrQK+BJ7vmcKYBBWUmw88Bzgf3HFHaLNzUdSaK1v/eoob5HBiJrMn7kOqbSa68siRsq9cwbd4p
CihutpZh21X5435lFwZVpZn2/TzS2N9qeS9o9UVuOZwELWPw4R8uylspDFOx563B+YULDzHQ//N2
07wznMoP5qcg9YCM273Jcmjqj69skV72niMASpDbLYh7YNJYeR/RjKMdwaN0IxYJouw7u0+brEXd
pWdw262p5PgW2kN+59HBm86fZpBvp8MHqlstYLOaWTK/FE6BpZ8LZhjvbR15bB5mfwz9PMOY+8zH
WR++cWf8kHipkB4Yy2wTO4Cqlub4unKZe1xIvw/Xmi0s6PgwSIQbFaYPgo02/Lc3EcYphlaTrbfq
wkxSFk7RiuGXvfwlhYuUZVIfDXyqAiAuEOq/HrWnLbHbu7AqfbX8/NI4jxyQkoh44+IZs/ALX4/b
dRzTu2GbP9m21+C7gCh3S18NPO4cHmy91pd9Jfd/5wHvF8LoOlHy8MdYIrTp6gQb+aIX4cuY5L6U
/5I4eD3zTpkNFaSPbFhDps3n11KANo/FxUrkHggdPasUTgOw6LgELxFJyq+eyGbW1iqbuWAfcqqh
d5CdzU9WFmFDyek6TrX+raC1Sk4GRdZ2dkVwblTnHxne0EgDh3nctSnyxra7uIk8I2AXua9p+csg
pSVFwL0TH6NOZIJH/bGtQHsBJO5dpNvSpdgh+LmdgKn1lCA6mWM5ulpoqz85jM3b6w8XYYIJ4euk
t7UB8RfhFQDY39CAhEqLcEYQ3QTgnQJ6OJzy7lpqTUK6++gedU1psVQxoWG+GdMIYy7i03epGdMl
gstC00Cev1YBVVR7uPt0U8nALXvSoDlLurN178Cu31/BRtcXPk6cQcCihOfvc2yBW1I9tgcgJlj3
Oaxr6tCCSHVGqGANzwcX63CbtrO7xX4ghSwp2a8aHQJawUJVrjgdYjX6hTlqhgmtUtF/+b+DFaiV
WtPN7Kw8n0C8HxfEN8bGbMHFbcJg1/vs7v/VOn5oO1LYCSf2BcW/+qDdOZooItA5W4lbox1mqGme
oYzDdiph3UUjsTGXoAtOncSXT5PWiEt/8tsuKjWK0MzWfCXk7Cm/tmltrx0kwgg9l57C6FACmuIE
b914cvBZ4WojDEcmCOyZjMWEPrd+RIDgtPaiPOGxC+vQ1D3u/efvRnmLzQESF6G76eB5BVm3NSL6
GtBD6JgpcB2GAiQoypXd5A/Ce9bketc3eVdDAZEWYcGOwLQ5++0VwQXv9AxaJElPP7BsIZUzA4kD
IiqQiT+71dzKlboaKBNL9IVv4yxmow6FF8u0cAud7C7Gb3n0tLIptRVWcn4jmCBg3RUKgLp7xxmQ
naU1hZJv9ig2BItLkeV05mbHraoNR4I0q4bsJ1mwj1A4bghIuKSTzdFNHbTpV21FxoWvRTiWNos/
lx+RbNsKwDJEwpo9+wbsdgRL8w3LwEX2QRsVrgIzjqU82gUJYdSc1m/T7zJwf3AlGv2WOo5YCkVe
S4Sdy1245mg5e4RRFn3ZXEqQEQZbNmxKcwpCNbMm6voaGg6rTsbl1bUjDKi0/EN9AZnx9m9+tVQC
2/p80ymdbCtisbUwgxHa+nOgyOjwgnKrzF7mqZ/tm1u0xbdwv0M1X2tugDYpSSYL2EosIugpp+E1
CIa3uwx0EsBx8QNpar8JG3qn711mxHEdJDNN2BZmX0J8VD0Jp+n+mxR1sLQ8PadwekJjeEkWrGFh
OeS0L+yLx7fzRl7I0smg9R4tKpH5GbkENtjyPUQPhm3Fo5QheoN49t1F8YDz3crnHoObyxXJYamo
MO8RFXGT1O0StLcqDSluTuQb9gp093suXLFSMniL9XVakiOD3tA+nVRdptv2dtRETSm2hhIRnmYx
9LM5fF4zXNYm2Sgq2A4q3+XCTZqFmIzNcF0v8SyM3dALsje7Vya1Y+rSBPjigIGbF4k+4u4cAwip
3+BWNScEBIscVrltD01U2IQgCLTcCmnbPmZF+++9fsTuYxPctLk4eDEL3V304KCOtSWNf3WpXKpw
YmCxzVTs/dryEYwHVZl60zZSFdUQeuwTewCUJ2lqqE6H+6JQ5iMRPdBJRvOlGiHkkCZ4DRDz2gfI
3GCthfBiRNyzf7dZzpevr6sETq6E4UmU9vrn/ByZ3juRYBAJQFrH48kKWn/TOFrgstb/JwlTXfF9
q0girJynI4J8r5a+PbJ6HX0hVOjVWIfe5J+RqV+dFga5DNWqK1t191dEEQo+4c55+A7M1FhPKr7b
wuFLAdA1jz4AsHGZISqKYET83b1H9KFjtXZ2e3IISxyzeLeNoHKvLBixN5XA8+UMhp5FKWfoaJ4s
sBEFL+ABmb5rx2blgs60keS5lJ67EXjnEqVeftSgJWMqRL80hOqZE67Mm02X7+39Ov7GNXkXWzN4
YNhSAoO7cnk63PdK0qdzRdSFtRZDRS+w5HGed8sftK0WeupaggDwucE7mzlZMVit8Ov7zRmYOc+Q
+EVvZm4rRwE2/9V1W0Maqc9kFFCOEquZEBgXqxKg599LvSM1PWu3cYf1o8fhoXe0o5eZRtb8PlM7
sfut0gdhx/GndOFL3KCXSNpe1mlV4Lqj+nmSiiFnp8XQsR+sA9wSmrBYQLBJzQGyiVAzBtATVUSc
su+12BAmPNyFDNvREspSdQoWaJWuT5+B2QUQ/ZSqWaKGE5SDvGJG1eFlxLarXKGwK9Qja9BgUwi1
KYQ9tlVwOpzbRNdYBb+q4Cw3Ojy7psmM2hK8sj2HgPnmOUGCA/X29UrrfmQSFalf6YNfkqUFzZXS
D1AKXsUdSe1i7qnQhJT/3xsl5r8vLfiwug+9iIClvbyexE3caOHtguWnNs4GP6HlVlJHIFZDvyY4
rTXhutVHbZvmEBTNfsHZQyHQYbsCZilWuIiztczk4h3nRnrJkEBT7IZxPO3Z3qSGxvSLKTPNM7u1
AHKOA1StKte5bImmyP+szjc60AgAi2yVUeRWQb6sB+XK2U/JBWqiVWPby1F74P/1LY0DfH+bXx7y
eFPYHM0tHnlkeeptt/D2aiCQorMztImI9hgpNYbRjFOIIAPawuqv8V7jar167GYFKK9tumj+2nX9
Y2S4BIa/nI58kDSPOEzMNxG/p0qV/Pg7Zmu/O19vHYF0unO+g+boIJl7LPdSHqyDXPSRSXIlj3h+
NmSbWGUZIvhrVHAsQK4//I+g6X9P7ueEJO5Lr0sFXcT8Q+lRf7PwAUTAqgFE9MWBx93dhO7VO96w
VgbuPm2YNW0g3FcI6gPP1rhicHbRFzYdmqFBYD0ngAwrUIXmwPfZqDEpmfc2ReOGpWVk9WOU09xi
80sL+VuAmF12VQ0pqPGRfEoqmiVy4LU7cPZCEbqeKv1bS9xAJD4p1+DQ1M6mavs8T47UqtuXVKx8
r0dfEg722cxTSYypVHQENTBOYJQ8KvRkIDoH5WsymdYmtdpPLame4qM96n9KukQHyHNiTwa4qQ22
FSD/uoO8pZSdfkVvvwfomogeCNd/s54vMbFl4NxX8YFDbaDPNXlDD298bDVG9WBEK3YxC4D0AyU8
XNphG0siE0kRSDjAJshLBjDRZymWsFSZoDVGqvfVY/6AHHzxtzegq40a5wOF1NvXULXm68OKKAPV
UtpLCCEXqiAf7FzDbjaLUvwNww3J1eO/r/fyLyg7EK4m8AgaoPjqPMv6H4uX/rJt2VucahJTxTVj
TDNsSjmW5xP7KuPQvkHjP/JmJS4OStY/wFx02Y9E+jHrASoDTbnN2fNeAEdLj7THp/NFabXqmqAC
tIL6btkXvNF6TzVQeMEgfp97oDaH9FKPwH7WrlSmyNOCJq7lq5uHBpcQELPAuwAp4OQhMeuDeL6K
XBx6F/qaN1RGTCv4MtxZEsOstW7WaFpYnNmgU9qCUke3MM+cFclbqPQGuWa8vkrX6XjO3CLzZgVJ
wJLetDlwc6jJNvOlcV//dZnR/7UrNkVYao1fmZ27E/dpFBWtqGF9F4jPj3oNBeRUH9XTkp4dqftY
ArWvH3pbGtRe4CZHQXmmaX74Rywt2v92WofqeTUIGQztkX6Iz5krFwDKvTjHVwq0XBBUuOgTAY7X
pZZadrShUPudrwUgBgZz+qPypuO4D3zgvsjssl9VH5lausbBe/HZOWjL9HCoC5nuS5AiKU9kCHTP
sUxBk/Zuv2RiKJUpcC0MWL5KwVyrqFbheV4AVq8EDYmO24rXr1UtKyExQq6L50e3YjyZTS3c77uE
zT5vD/nAUY1EqgXnVJwIpXGnWayFOPeKz6I8mrj/2KoIkiD+folMhoxD9rsdgpYZ1BLF6skxej07
PX5LB5cd1jKLsGSG4TnuL+RwBhDCsvY1HdUXuzm3hj7DkDPdDWUisYbpfrlc15m4AVni2wU+pqxs
KkUndbhxjjVQj/lgxekAgrj1QJqTTDH82h3M74DGFomCs200gCvn9alv9M1Jnbt5LSK9mG+vQ/Ba
57u/DAgfBSyJttkEk42LvN35k69r2xRISmr+gmvApVolhSFAA/NNuHvIyM9tpa5ndUEzzpnpgMe9
cI/a+3ULlxJ2S+XaoZGYEcJYp6Sn4+Qr+nneS319sCnTLa1kE3uxjDJa6Wv9NQMNtGbEyn0higXE
TdjtqnByuIYM2ZheuKEK7dgqankcU0smNna1drchyf4bz3SrNnr24zsWP/iVUWhKJYxx2YxGC6Bl
BQZuMoLZq2bzDPLbq2rcJOQ4cNlcxcgUD1kpXUPBsGCSyypNzHxZeV2Wjnqc4Q6O/kGYfFfXPWM3
z9k+A+v5mesdaC8N7i+8zuWWQ9ba0Mvf5+9XoMkCvRfIf2tA+Evz31NfAjhD7dqKTMk+Ms0XUgu1
yqjI3SnPagd7joEB2n4jAmgOOEukf1sqLg9ZG4/U0BcWrGbaI4AjkabhQtheE8LeqweBkZe+akmc
Qa5dJWApNWOqnrh2KolWoNfVCjp3/Kd6eOrXrRDgU2d6ziDFERn2vjQa9txzJhChIFPTE91rKEyw
NWZNLGTrtdbwHCqAADWITZQE5PDywNoZc6Tnghh8rXqQd7gBZKaieI8kau42N/WxVxIh+T1CjvrX
Ntoc/URQUXrihmZc9MNK2NjUtGhQZIqYWpH+HS647wyTLzXatIcIEw6rIds/bg3YK6DhH81++QhZ
bojSRF4MjT+3kJ2ULmvwYUfMsIzByqIfpMCdkRQeCx7zIDN4U1NTrDay1dN3I4PB2OFXCy3rLNwn
4sAbTBHfJO8QsSuX6G94P9KYUKV8mFNGdldcQsrJYgvzTtxCHSRWOu6pFRKcFyAJhQq6n4bxo5dJ
OmcV6bhzANzGSFpil1dyC+83568Ep/owHiKDMaGQwEhu09PJEdhPGSBMhlAM+CcxMdKgJqP332ns
Y8dJwe5h7F8y8D3NUHoc7BhF+sB6pcdcDkxcNz2u7nKCbYZXRN03J7cV55aOo7Gj/UvrKR/Rk83m
O4nvfDGo2/rnV5NCJjWGq+eACEgZxvUOC8biiFijd9hT6ppSy3IAwaah8YMYK0c2piKk0TgmA7D5
lPJpI08ATBIE7UTXjG7zMGpUz3QmPgIdXtM5SJtMGxXzcKgWGiIJ5yMkqXvC0bfURvoulL+pK/Lh
q8I1bRrhuypHFJxm8QMvR4FZ3q93OczTyn5bi6IJoWZ+K58Wzb3dCBOBNY1iwV2CjJQ6ktNRBI7r
wfaSvgNRSECwWOAH1hszf7gToG14vdshnmaQkGOEPtY4QrVNOhcG0/18gKu1/o4A3D21P4hFbVaN
ZRfTQfWckuacBEk2idFKNXSePY/vtFhgUCSk+c3B6ws3vzur9qvt4ABoZI7xv93rqjhpLC0q9Hw/
+aHPBGIep2gQURXlZzFBMiP1ey4CKkJdDU6YDeRwFBLVR+/LKvtwpspzJZ6XBytWiNG3OHaOfZVc
dm4Zz3KzTDkDwxE+CZNuVU/1uIN6PfUffCqRrAUG8YqgdrurHNlHF+/W4kvYCEWIAZrOowVZ6OUP
ZfY0M12IRLuc2EGLfTqrP3m24qhP82FzlUt4ijZSu14ulm2f6/EBEO4xgMIhJEtmLTl2fn9nbUYa
X3deZ3RcHFgVafTu8popuCPJYXBISfPVjU3WOnQI2cXgCyTDojkh1XhcBWszOPjq6xruff9X0b13
/fEo9tLVSDHx6SWRF6XWMF+46tfZXrw/PSLu7hl8a3ybF6+a3XeLTkrcFhWCnMQLszXw05kiBR+5
c8XsPePviNRlQyUj2QtB14PuWeanW+ZXCizHsMU8x6hOUG+5ck1mwPL9mbVhEYtpT2FKNdjljSyX
+QfvdHYk0/RmfBBinmzIydc60VBXR4C8I6WybC/9RQjCqQmPkVdOKsgfD398/KR6Ktl2j+wH7Q6Q
r8oXOnLuhmL1ap5U7g9ZVjq+a316IAzXrr8umjHkwE6JxnXwoB1bwOqQ7Hg2NSG/M9a8MDibhYxx
1HG5FXJZ6fMhYNjfZoOHS1bPNKj4e9eX1VvJWiSA11DtZn1aYKkvkZ5JpWVKSqqC5QGVDcuTNEqt
qItl+gCQpdCb4mDDPH4e80t07NKtxEpnJPdQnHr/4LvHul8g1NfbfIjb2UfBLW+NorkhEkKjVSqd
cLV49E2uLvCev2PWUU3GSJ1gy5coiQsvfbe6g7sJTrotOjRuJsiFILFb/NxCke9ccpvWh29hqS0s
t0XdkR/KCYghXRByYs/Ao7luWWVxGIKKqQ+M5dNr7agDpHdqigjkP6Q4aO6cV9Yn4pqrTBHOb9so
xvIQUdSukeJ8god6GC82hH0YjQmsfiEAvJKxdfp8dex0mjRB4G/xQxhhXqujTYbmhUQ1jOlIKOBg
ZqWLLThgnOFvSDL/FY47opOy0LSF6ZxR//1cPU3qu6o66qfpNVylvbOHLz1aMDWS2oyqUaQ02C7z
slyf1R8BZ9VSyEawk1J5kfF8q1wGN3tl0q2GEFPnVPJSWAvldVcovV1tUpwiTQ9kIPRiTDjl+sj9
0ajLmDTTctRJUdn+eWptrkmSW1n0TWnxVBPm15LYpKNHOfDxVFLs/wJw4w8NCVRBT/92FNg85fL4
d862v5P24f3lLImB4z9MWYOaku11tb9TYmy3JhTfHp9LhsWv3w6HzC0jdidDym8RF92QLQKuhEA2
NLpNqWgg7iBYLziIyUxaVv0mqUtWklAJy3N8udA9D7R9NjHJeXKw1LNHSVCqz04F++UZ1LCh7Xro
g8G33srKaJVt0X3yAqTh2Ux+4w4/BDT2ts+ns3U99guG/LUOukcvLjacwgE3WVkK/9I8FGbSge0E
FEOYRh2WXrK2TBLtHhcCd03PJ8yXBMH4RlNNu7Rzk8vFkrhbq/C+NYhViW2+nwdYePFE2Q8J8ptu
z3oTrimlV5xiX9/FUsvKPM71QhJr2CeAmvNyGOhyhrrnZgVvcdCJ4aI3KUayvcdEqBHeBXFMuM6t
DcL13uioTlVJ5Ui19PiI7j+8Bg/nrmCgHyjv7Wd6oE0XhvoEIkXMio+PUzEjkfVFawM04KMO1eMm
oigr2pMtS/2joFilwxxYAhD4kjVz0TDImAnYQ9PkHJCDdQFNdkyFyfCxHbz2OUFzYrb8kTyLnJVb
TN0bteKJPlbA2ZzIKWV3f5NsztvSI/4JHoUPy3sYzNqKh3ZRKftLTi33gnyJkru2YjDdBSMciRbP
RDLdPG8is6EsXNP4Zcpf29c3eDs4dQuQvf0PqdTMOciH/hdWCH8BPxqkrRVM+lR6yNtwlIvqMTLZ
FDvktU4sN6OdScIn/ZAhismk3TXsfvDcGvT9y28fdeH4IMU5wFE8oc91gEvWmLD1VX0PMd59CIL7
01K9jiz1/01mmB5+eBs3h/raInGLWYjzhPOC1MEwIg/4o4kTtjtFnNBG0Qo0gleEc6J7WX/HOixx
7FN6XPO39Z9sQOVekqGPbPLKgF8QOEJqiEUDvLGE7aTniM6PGjB/N8Z1u7wNec0Pq7gsuU4Lf5AT
V0QRd2aBgfK9Ysbwac9YsYAltGZGPxJn9ijPfUjJDE53BYSM1szZEPDBMNUpSGgweAY+yKJhg82u
QP+1aXYaZA6xvSjBLdKIOTFWoThtybZb4eqZYPbXp+DS8Iv8yXVkX7Ug2wCQOOO1nYpfpvzmUTYB
wMCGeRIqLkZTBkEAs/oCghXTBGscWvkfDg+nIQdBR0rfwmlI9NvoEsw93RH9AaI0E5sUkb5fsES9
kH8iYKWf47Ur+qNomaPWGAM1UilRUiwMbGFfQ0Z8T7JtQQEgds4PzeUHu5Bd6ywgaA4odv9hDPn2
3sZOLdnQlE2M6o1yOxV05dCiwmyJXC7sVn/u9F4RGQftnAnyHRgfBHlfG1yGoBuvc5KVGeiM8qgC
jqCOkIomUCeNFS0Kh2SpIyqkKkEX53+dEizTDnjZTej16RV54h+zPD6yc3CxnrHqFnHPcaLjNq10
2j27NlshFTFP7XylREVQwV13wsJDFi2jnCC6K63MQzAkhzTwKrjqqkb0zV0hYijyi0pVtQNr8jXV
0cZzCktZRTaKSg0agSa8zWOu+YtEYZrfrae6ZxW1j19LH894QPSZJznT1q46RBfgHEAnJhrOzHJp
LbPmFC0gxNbbJPS87tRUTn0GgCOVDKQQUWKfgkp8qKY4y1CcBRAXhIWysnrAgRrpoTUW37r2go/n
c821vhbAa5/fJDCvEuTQWBjsKYPnMSy1pjvY+zxOae+03RVFKEu/Wc7rtnPTwzO1f0AskPca0dy1
yEkrt/tO7WWiy3p1DbE4s+L+JUh/dwek+WOETn0R/1AHTh6IL8Gf0AoDNn7KMZacIL99ibdeUrwb
+mcxtUo/McQP0NWtQ7E1ApZwFdmntR3UmvO/KY7yzRBJGlN9B+ghfMNw5DCNVycxXpXGu2wngp1s
u3W/Rmztkpkfg18NfK6Ej98NSFhaGT+pvCDKaf0Fe+UuKpfMXwcvLmzJ8tfU2cCtmz1bTqHF15Y2
G0KIRO6KHWHg9GCc/G3rmDWaqfc6ukG4xbZs8WEOfSkU+hxzWC3ajmBWi1fqlbKo3BCXegYzaV0D
Av70Lftbtf0yy/4ROl19A9XAWu7l1XTbr/o6PInsKKAAr6ODsNeBjPZuTB6ZH5uBSgROB2BzfAMs
/xie/EbtWwh124qP0YBR/YwzpQPAasdtScrD5tr71B9qTH62r5uJTIowMG5mC7NLn69vDeoX+EkP
OjQCdYbYwi7QqJOMhA4HI5qmrC7U7+XjLgOheu0V55yl+8f1AHt5hgxg5FeuG3e288vtkvhxKwyI
mknTJUbdb1iXuGZQrKxCLaPC62gio8JK5+jGMHh6lN/nyvw9jLmeMEmHfEbycpwLjRBlR0ep3mse
ojlk8eLOJxLUxQmB9uDwbNPX2mKJUNPu01afpU3M31TaAUxmu/36J77BIIfkX1WMjJzl5NQSEjPN
hftEJhIHb7LJpP0Wrx48E7F3uvHnoUssNJveudKWpt13PX/0ycsWRQrudwNJEYxyR+jnf9ruy4gG
D9olg9wJhtERKs18PxJUsXQ8DLoVO3kB3kxlFdq+rfgJEC2al446eRd7S2mR1grBf+a5q3c7opoL
ER18vOjqradxDDNiP4N4FKb1FJumroc52wSc+ntqzSPM4yHLYjbVBgEHpmeV3DSQiZH6fo0ue0iP
p1TUdaPTBwSaxkVAI6ZwhVMucx8Ho1qrz2LCBoq2oeSNx/wYIODP1Bz9UlalQceFSL0rkwQsk510
JPb7K8lAJ2Z38e3b8dD9Uu8QcQTJ3OfqFSDTFGfzHPRMEbWAhYhBbf+ZPmf513AS0DakXeEuqE1T
wM7qXRljmP78EYv5yY5hlxr1tDFsjMrxAVnikYZrLz9XhS0mqgIR1pewF/syeH5bo9qJWZC6hHpw
W5JtAvvEdIlxCtnaNiBtBjVgYINu/iRuU9DGRwB1cStJqXDgw+fGopjLi4665jPpCUJIit3ocaQ8
rudC5pnhRITw71kjDDQGFugce4+WyUgarQF/yMWkSNw1G+H18BTIPRakXxosfsOV9QvKjaNZe9AN
PEDgy+TuG1ljpgODLlCuDBMK2g50SHEEr0pcxx7lWbGJyv+E3P4V6Sjjwfn0psmBLuwnBd2evw3c
ofdDEH2uzmgMiHpYibAbf2eGJR2L+7LVDBdVk+GbEDJidy7uMLH4imUD7wvVZcDsBfMfs9yoU6vK
KMhGQZyZ8zQGMYy4NEdtq7+7XQ+oRN7NHGDLu7IFglXmsveiddPvN8Fo9/rG+4t4+h9VOomVvWFa
3GwT190U+YWUc9hJZQCXe5186GcV145WbUrlvx8eRTzjQ3uEfNA2T1TE15i5i7AKDyD7CWXp1IpO
MNRMYtVBxazK5FAMZkOXkc10NUm5UWhXgS8mgitzDhOyyF5j7brW1RscDmQTdlRuVP5e1CBtqEjM
Ky4S2+Sx+txDjL43zQDvs39/WMQU6oymDKjeknDgpmMRCQ36WQrOVKycxV2buFteqeqifeUYJMhq
6dON3FpVNGs/fR2ECCd56SjQRaNJ7jDgkdFe8EjuPr2OE+1zk0LwLhj0+aM+b4nzkhfZDYfAnpXV
H+HbiYUGb/+X60DYzc7ME4vryRzgRk1rpO8C/7c/KYXtEEKIxPonu1hAIMyNVCRvBc5aADUD2810
gVEfmWz2bwqAWNWVbKlCtR2tDDGohFBya8vyE5Q1L/ZAuAnA4dtKLkJQdrRR3MnebvBXm6HJYS1i
dS39pAn7OdQHQXOFTf1fSvr35h1FXRnIONN5N/DTGjyCIp9lntHqOumthCOKKj8FvHHF/wvQN7Ip
ns4mKp5kJSlbWDbCRJspKVrvzY6gHnARKfsvQN91T6X1WzS2hJpNUw2ZwqBCQbuW5IlSAWUnoGJW
Saf8dhwDU5VS06bHA8s1ujwqt5zJWxXdQf+ERy2S7Fmg3R9UVXmcp/fHr9+hnjypG84Jl3tENaqZ
DOJs9SbY4LqGE3tD6gIbFFyrZfu+OEq2pCzVdGlsNFRrEJ94uL7J3Er2EbVE9kNteKO3yxa/UGNk
gr4dk5zNexZ7jwQLVcI8cWv+8kvKNyAxwF9gJ0PxltAl3EI+4FvuzPOxsvLWh89Emr26jwNFaczO
XFwOx+wXGzYVbyVvcjZy3q8xnzxxnGrhK1vumnkUMrlfU8Zro+ZjKByOJ7m8PvEKtSV2cuD8dNhf
G0FE5gBhfrKJm0OkwtbJcJYhWRFM0AZNccZqtlz0S2xJYoHzabQ0/OL+3hPX3TmLQ7OfLvtB9PvW
rIuwmonEsoe3xYFx3g2SaoEFDJC2ybUkgBWpCQB2Fi52zXtvZAF7zAfSl/a3+oP/LqbWLen73WwW
V2m/9qYmPeOqHdIF6eiHqL4en3MqSQ83Mtzb6vFIaXX27mDGnSqvxlXMXsHsedQIpBieapRIf5Xz
z3cepB/hxdmvVJPnKfv3g81ymc0j2fzLuMpuscCxpvQjODA8b4d/HmN4cTPTFr8BxoWvIWiCuslh
UXM3ANQ23V/Fm6FeYPbA9Qa4P9xO1IyXScjQcGkHQj/Vr0fVDfw9iwl1k6XRqJyuRPaP29kdhp4o
u1OTcexJCO7SqZzyRjuH2ZniXqmjZ2lkfrAFGVMKdh+0sPaitoDAC5JxjDKPXWI93y2BLLbvConB
inREl5Tm4ccg7tF+ZYFSnh1G5V6dumq/eBoOVi/9FrkT+Sx3PKw5pBlBFsNTyE8fpcFJZE8muIdq
eOZXhB2TEaT+DoNSHHIRB7V00mgqrPLzJ1jsVF57csqorwUSUviLVODRq9kci7OTzoJDKHbH1kft
mjWaCehYE2+teUXT8c4Pp1AvmWZqsAtl6bSlat/0mnzArO4vaVef18EXL1qe8WzMyVmhRl3Hhtks
AZmKtNeQ0mCa4GsiNuW5jHZLDvNUippG8pxrRBa9YKZT0m5jeagcVrYjX0+gKlayZXQWHl6HeR3B
9lESFGGw0REakkPoEt+V++FAfxQkvxfrzDr4l+qPG1H7e3J43k9HyRSKhZRmPL124lKM9kTaBdkl
rOrPxy7MOj8+6Y8Rlq/1jNjA4ddUJW1fWKNUCMao7H144+Cfy6aKImKQV+62yQRgdyzEGZ9GhQ32
JJshWue1hgR3geJEDLHodFwWz7r/Du0AX09xqp+73otZ0BTNBnZt3ZWWlNASQmiOuPUuJCTtMQCH
tF5IwsC4vXB8gL7Fohks+ubfwGrfx7aoz3q0qNU7H+nvpDOT2umDBFsnY9lRgrTLNQTFJPAW2p/R
I/fc29MAYdKh1wo0bJfrDNnBUbAInsZS+SOakEu6r+mKozMTtBKIaRZQI9JJTw7BCWMjhw03Duzv
/vU4xnGsz9EARl5l3TrjPI5toxRHQ5htxyH8Yfaqhj5Sx73UuGbBLMKOmqJkwqJZ5KzVseodVs3U
wejYtjcGMNsIFvgLtF6Of7RVbvpgPx0f+2adFij137koptji3QCohPXdf3Tx0rkMyCyaZTJCbPti
K6DnmXH+QuFs/mOL7ax2pBDT4Z1qqMIwKOUN5Y3vS9Wgsu8IAUSfNlw4KHrzO7QAdnuAw32xeNbN
IVr+wYo5EIjBKEdVRW488rErpcEDptN5Ven5HsJXGk/xPgFlcjKIJ10kfV6cFj0gIGGLp/kAtvae
RLfzHVj+OoQIuAmLkzGQbdGrblQWS4UBbxnQQp1AYaP2KFZUTfWkFbNts6/ji+S3shzT0wvE2fvl
AzxlrRVOmxj6MIc5qgaiwHpN3dDEwWzgJp7M0fWHuiMGLrCedbF3JUfStNeXJhcD7nO4Q3RN2cp9
XxujmpGTVBcTSybFy1s7n+LZp7c8KIK3C2BLtKuYBKBqt7ABGntFKj+WoCkRNISsgWVTppItb2a9
aIhz/Mz3sdxkPqYLJYqCe3d4AdyxijJIrq9KM1xnYNn65Ycw/5Y4OEnwi5HDTQ0uaiS15g/EhaB3
1P0O1FA+NtveZZIG+JcU1AHObP4ei6eRKu4YRtb63Y3QEsKZZFuWURbY2IJZFafCSJmtTHiNlT1P
JnKD3QjXmqCB+ZiAwrOGnl3dv5GMWs+299SI6RwXiLhZZmvfFyzBav+akgp71lG7fu0Q/yLx36uN
Zyfay7o3VarbLvG4jHIMRqvSDYCp70vpow1DUdZifo4ezC6er00+dvEdZzABwgvV0oSUAKPiDRLe
G9mkkyzgF057AOWZJkjVUdkiFtbAF79bvLWuj1UKe2C72a5TRdC6MInzrIo7dYAGOD+c5Q5TCbf+
wVKWmRJtIt7VSs4ixv5c7cF3ao95Cbo5BJ0geTBaQiVhnZeFzhRwrUCKs7sxHymN//RmkL/U6D4c
1dTtkE50wjVygXvrUZZVjnxU6IoXqxls6Thk4gmAYpNt98P5AcoF6LB0gdu6deQf4TZ9gdBPl2Wo
zAl4k5C/rRjCzqSFeZZKZn+nhIDttBMVNN6uzv5dD0ONgUNQrIKWbpQSMPoH8VaeBWUtB3Ux2DLC
3KjHmBtIf0KN6U40bVX41cwqfZuNkuhhz1ZmWOGeTKkEsQOVRe/rzLdUJBt3I/T3fWssZrD9b8RS
EUuJyIPKXepvavvsPBngO1ONg5DHyt+Pd8cV5l1Gou5vQoEcMtr1kpYCTodIdYUf2eC8rlut0lpc
KUKBKY7mLq/Th9OQJNPhP6ZbgmnT12zK1C+rUNH2lJdpaB0eloNhT+pxZz3nTh+hGwD0ghfQKugw
UFtq2BGf8Uofa2Y1fSML7BuXZ9nirqYBuFz6BvAJoPgPWcvNi5ml+291cN6JTE9t/coeHur+VvS6
36tJ9U2UJNF7Fl7l3OnILSTfxzZBkdk7P8nW4+B8z+vRcpwQnSVXseUWKlPpyo6n1WkjfcjE4XW1
dLCbs6MY0qew8A2IbD14BYLg4bJ65Xx0IHc24P/y9oDrPDGM+yTFpO9gK6eqpcrJ36EssUPUxD4G
U4JpY3YbqMpyeOmqYDgava+C8GtrqNSGOW+45OJJFE1uBhiR7w/tagQFA2LBu28cbaOI2W9c3F0T
ybLh9uiuFppCHrB86sRiiyqqoAH7fKBoi2DoZrakf8jeO2xy2QKH/o9/OX2cvb6z12ImOjwAzd7o
RnxyXY3/6ntEcDw6Ky+1TuKlaWSErrAvvis6FAroPXQ/l0r9XJThTcIJJ2KgHv8otf869i0bIAHH
M+EgBncsITJwpOM7/ibLc7FtzW6pcGCAy5KPwbXAKwrj9Vg5jbXDWs1TH27e4yRd7jiNQclVCmxE
sGDWGqUajTMkxoqAf/SYXEbWgpmtz5BVVc7+L8aqcDUynO/f67/ICSAqIkaZFTVIeRBgRRMLrvLr
M5PYbM8Q2c7mrQmzX0uhR7EegRynEkFCp4RNw0abYcKuoVs0ZZz8LxpyUkJFU5JOkela6+tM/1Gn
0rmy1AE5e6awi1iS4BxsUbRcDIRLMDBV14QCrfnBV6KwtX8/JPcOOflalueRzV6jW2yylmS4jmgn
iyMOVOJhq/k+N8ykMdTOhjytolpReUsx4Bwt4G/mqQMQFhNU0pykIkgSqhhDUnkMs35Aoe10+SwT
g1gJfUlxkfxylmGnf20ITjNrhNnE098BiB47EIjqlcrV1tQTUV0EbP4Y5WzCeDSXD/VG6qKGnMQ7
UWbMrJLf8C3p2u4lhf3QJ8xaQYp8Zke6WmfZVsRGkp8SmiPVEPMvlLoYebO7EzW3mL5jrsN93Rp3
s7wyJt5esB2vkAwygdnj+I9U1HNXnxGdKFIXyhiVuBsYl1Y8H1a618SLoLkyncfuFTu45lh8Mgyl
X/G6hgIerD7WPA6zBZMCd2doz3+ybb0Y9OO89BUzQd+yFeodatWB0JiliO6ZD6AZnQtqgHCycjMv
LDsZJ+EWboymlDH1hJWrmTjUfX5+cTmHLX/gadDgT2JwD8bXl4s24Y96YhOYB5BB+fJhE2BIy4Bv
e2BVx1YD/PrT3PrfBzn1i5oAeStwJpqNfQD1n3Wu/WciYW/bacKwehZcL7WQ+VKlRmpaQbpBUOPH
demyWVg1h89LFaHn39d9bqvFPUpp+G7nrSfyoNf7IaS/0BxDVLYHvMHGbkU5VaUqlUpu2+RfRGo/
uFIQWjRIDXZxGrrkMBLtaWHxqguEDpA/RwYyYqEs9S/n49vuVeUJG0wx/okRwgpuwl+tZ9Ad2vFe
U2ScMrT+uwmlEhRfKP1ZlKgsfsdXjoKhn/8uRuWmCUSZOyWP/Fj4mHn+T2BJ8xK8t4Mqjfikliwo
KqoKogHWJU4HY1FJump5Rzu8UZYPSPegEo6py07InQK/XvKwngaap5Vy21B7vd+SJE55o0tgFC4X
Z4Kcp4uMU9/GTOTijfgzJR7r5Tot0nQnfRNZo8qui5Vu4lcH95jIDFwgIri1inaPHt7+Zb0ZdmZO
BWbqBeob3XRGtktzZcgvcy1LIyWdM5C7X0js6YI3kt9xfEzFBYRht9z2ur0UWAmxDps0zUtdGA1X
ZNAzD5dcv/Vy7zqUxJwgC1P/k9MJWT29b/l2sT8s5vRumMfxUyDaHQgM0IUued7BPoo+YN4luMSI
TYdOe0Jl0e/uTrM8iJrNHc5EjaSl9tJg011/x740VXu4IdnnmQ4vf3teNG0d4Lh8iKAgZx4AsSkv
4Ah5AXBuzkIiFWmdnoX3VWheamWe4c4rk0Nr7Dhbcq0lHI1bugT0LKvayHUlbDdNe6wrNVRty5oa
Fdk4A5IbAAq5XZO8cOMNgfhd09PS0s36+vM2wQjzFEySSPLmmOPh0J7L/+y9wjInPaaclUa8EOaq
gXCDhc9wQaGqAKVfQJ7Uiiqdo4T+OwDMltvxyhY6PHC6l3+r+G8wCojizddH1aKptBw3xO8BxH0B
elIbNmFSHiJBdcMqhQngA/B75DvC+qE+9nC8BxSJmZVn/tW6M/ziz0BdFmRxWTa1S5o1te7u4VTb
Y7uh8I4w+p4ojywcNFbkZ9bCynIc+gCPzAkwqUNiDMpm3YypApwnNmHJQ3d89rz4uGnLpZDMVMfv
H5/oBVVaz6tAdSJ/d0hQ2iLphVjj37UXM9IC6Em1K34QePSPZ8PxnqYi37IbnZw/oLTjLz0qbJ8q
GAtN9zSpCaCtyxWcJglOlNUZzKI2Abj3/mYcYsE38UUAvKE0H2O1Tgb0JZBVnNxmeAKmEYijmsWG
HR25GS/xbFcKtRgjU6tUPC7GZKgQc6u6CjV/tBy4pK2TVgEuSI0uk5tct13u9pQtoPS4ggg0Rldj
7BaUCZLcbgTVSvynqT9KK5pUQiDPVUjZoKkc4+bNhEAm/88GVHJdBF4Vs+Gb3RvOkRIVXfP2WLCL
mod0YTf/1hXzxsoHgTxAKug0NQL+t/ErEO8Z79naWjN6xANbZ7o/tZ2EjWjgbdAokowfsp3Ajd/C
8VQ/OZOwCcQTwo76wE5eWRP8a2O3iWZgkW1x9X1G+K0oTk2tManaFogYCihNcxAk+y0nmT9efdzX
toODdEatzbLJRT1RStrq6YuRCWZAEAPOL2fTuZO4vN4tTKq8SYZ9vhWpRRIRltZOCjA+leHHpZ0P
cnnlaJpNEyizDRGI1F9aoMlVIfJL7oTmPF7hXoFpcjVkzWxQM9FEKoEDMm6fZIiImZohnycDahMG
eaoze8fgeN48UUz6cN8TbRxAMI/WWdX/hCprtbeVn5gGY3sdQRzm8AJCBsFQHPF8XsPsj0EdYA98
YAu2F+89JsRDFFT7bZNLxYjWO6l70h6NqwzwjcsorGU0ku4vAl907yarLhZ6MgTrsVf/ta8CXI/V
YzEftGSJFDmx/FBaUBmHtV9W+NPbDHw66ejUwcfXvpRpfBQlFccV8izejGC9T9x7dY89JvT03N5o
lv+IhL1R0fbAvWpKZ5i6F3Tc3+h1d3kG1twC1inwFZQ5dYjq8YvrCGknfNPoonQRtFlRYyZEB01L
weFxGw+XSxbqJLHgg+rdPBy4gLNpY2xvoYSrQ7C5VAkM/OydnSC8P16+mhPcXvkVKZmvnCx6AlLU
yBbwiOCuHwRWaKThWajXe6gmEKDwifjSOkkB0jKpMf2BNAs0PEtoJKb1YAb9k6+QlClYvpXg6i+Q
+VTnjZ2Mt6xGKbvSor5zKDy7ajKZ/JoeljFl6JXnIYBnri1n8fyOZdQquLcbFBOqFykUOwQ9Biyg
20SiHvRVqEKg02boLyJOiv52GP/cJnK4tQRZn9oaMVJNtygBcIVOj/2/HNeT54WdFRIovTEw2wQC
3sKPPubs7jQ9hPHbRX5yc4rX0jipVxZRVcRAsnaeuKMhMQL6UdVouAbeZ6F9zpQHxYkDrCANgqz+
Yqheo29RD4M0k6YPpG851cbVv4QcmgvJeJwN59F+arivXP3IoaXS6bk97yIr8TIj1b877zpcxybv
sRfESX0F/3cJEvFeE3vyMrOC74ZuWP7WoMj2CQp5KYITroh0TeRm6c22SZnGspTcfgJ1ujSF/k+R
oUwE5/MzEsTm1g5fsdFgbrcfkbFd3ro9FLbTnZ8zRPekNq/x6F9hh4QXj8nz6O4448E1hG7Ic0fn
YbWpTUzSLKnletvSC9fbMgfn/v0PaZA7/VlxqjOk3sj9CbdPX2Dm1+U4A21l6Ie1il0gkp/xppY4
7q/2+4P/wCnyPzQgF2pzWD8IHzap2NyDI14wUIYrS+FIZZikOZ/mjUBewzf+ZjKi1LAaNMtD0eDC
3IEmQU0yYvyElzU28GQFXgk+kjrOfptar1/c0cn3FVY6wAwC7Ny9S7D+94NjyaPxE3l3LOXkNSBH
6BCN/JzRuGXHwlNQfErdCQ+B4k7C9GCzplQqsqvexcl4ydSuT2Jh/a75gq7LhcXydjGPPhuTvanL
o/NlDGpuit2rsuo5wi64U+qA5OuNkJG31SblDjcxcEqIXBHUyPivqauO0G+62tzFw31/zTxK+b3t
4zcgQEEYEyrzY2uzYEBUEpFhYuKc/+eCZywbOPyZT6P2S9ZgjmjTXWqEjGFWhAx1MbAUIMKRQHSG
IXT3xAN495aqO8CTQIaNFnYMqOqVE+BI+gaHdR7uycdF+fglr6oTEIlb6GZGtFm8PZA1+6682amf
UekajtLWvA7dhHyfqM/uoTRFeSZQabc8mes5vT6VD7ApS9sQEiO5mJENmq/5jHPEJE79PSFmkcbK
K2dz6q0dsVFvfXx/Y05sj5wZybqmueJPDfLrwtFXo9k0Ji+pe/vI+S0Ynd/Q//qufI7TLxKDK2lB
cjLX2zq58iMu/csNW4JBT8SVfk8Lhfg7enrp/4g9f2s8tNJqo864iM8bN8edBX7SdTvNsa05h+6W
5O0lpNGZ9JOGA1NL0m9cS4lUG1LIf3fKcIMR3/0fNgro4IobrXtPMpS9Zc/QTNWyr/TXKjIMveVK
4BFHlUf8kjSUKlF2b2wZCjkW1Mb7uf6QK8oJEWiCidD45ayy70LcrFLzPerjpNt7Pr3KW1Eh2icj
40R7AfBaV0Hn0gPTj6w2xfANjmHz+7O1Agdwupkv3bv9/o7pM4/RkC4REyI879dFw8Oy4xqi/O4H
SoYr/IVk23yvDABxCgBnlwq5LR3xT6Wjldv4HaqFZnfYgU6JMpZ5LQX0PmUH3GkLB7A93VViLi7m
0SCjL4Zy6e5uLfK3DovF2d0gflj+At0MMPV7x1h+mvq5gzvHe72w/ApsXdXtnGxjVGCLCZRJDDBE
1gwlVNmWCnHVuAW+d63BsLLih79GY5hbSucHdMGUfbHy1py/fWV4I1SRIFBWyDYEKC6OUQFQTCCh
ZU46wMNeX+79dZVndieYl9t56eMipa2Ukg==
`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00231.vhd
|
1
|
10055
|
-- NEED RESULT: ENT00231.P00231: Associated scalar out ports with static subtypes passed
-- NEED RESULT: ENT00231: Associated scalar out ports with static subtypes passed
-- NEED RESULT: ENT00231.P00231: Associated scalar out ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00231
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00231(ARCH00231)
-- ENT00231_Test_Bench(ARCH00231_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00231 is
port (
toggle : out switch := down;
i_boolean_1, i_boolean_2 : out boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : out bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : out severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : out character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : out t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : out st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : out integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : out t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : out st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : out time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : out t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : out st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : out real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : out t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : out st_real1
:= c_st_real1_1
) ;
begin
end ENT00231 ;
--
architecture ARCH00231 of ENT00231 is
begin
process
variable correct : boolean := true ;
begin
test_report ( "ENT00231" ,
"Associated scalar out ports with static subtypes" ,
correct) ;
--
toggle <= up ;
i_boolean_1 <= c_boolean_2 ;
i_boolean_2 <= c_boolean_2 ;
i_bit_1 <= c_bit_2 ;
i_bit_2 <= c_bit_2 ;
i_severity_level_1 <= c_severity_level_2 ;
i_severity_level_2 <= c_severity_level_2 ;
i_character_1 <= c_character_2 ;
i_character_2 <= c_character_2 ;
i_t_enum1_1 <= c_t_enum1_2 ;
i_t_enum1_2 <= c_t_enum1_2 ;
i_st_enum1_1 <= c_st_enum1_2 ;
i_st_enum1_2 <= c_st_enum1_2 ;
i_integer_1 <= c_integer_2 ;
i_integer_2 <= c_integer_2 ;
i_t_int1_1 <= c_t_int1_2 ;
i_t_int1_2 <= c_t_int1_2 ;
i_st_int1_1 <= c_st_int1_2 ;
i_st_int1_2 <= c_st_int1_2 ;
i_time_1 <= c_time_2 ;
i_time_2 <= c_time_2 ;
i_t_phys1_1 <= c_t_phys1_2 ;
i_t_phys1_2 <= c_t_phys1_2 ;
i_st_phys1_1 <= c_st_phys1_2 ;
i_st_phys1_2 <= c_st_phys1_2 ;
i_real_1 <= c_real_2 ;
i_real_2 <= c_real_2 ;
i_t_real1_1 <= c_t_real1_2 ;
i_t_real1_2 <= c_t_real1_2 ;
i_st_real1_1 <= c_st_real1_2 ;
i_st_real1_2 <= c_st_real1_2 ;
wait ;
end process ;
end ARCH00231 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00231_Test_Bench is
end ENT00231_Test_Bench ;
--
architecture ARCH00231_Test_Bench of ENT00231_Test_Bench is
begin
L1:
block
signal i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
signal i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
signal i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal i_character_1, i_character_2 : character
:= c_character_1 ;
signal i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
signal i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
signal i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
signal i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal i_time_1, i_time_2 : time
:= c_time_1 ;
signal i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
signal i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal i_real_1, i_real_2 : real
:= c_real_1 ;
signal i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
signal i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1 ;
--
component UUT
port (
toggle : out switch ;
i_boolean_1, i_boolean_2 : out boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : out bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : out severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : out character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : out t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : out st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : out integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : out t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : out st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : out time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : out t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : out st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : out real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : out t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : out st_real1
:= c_st_real1_1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00231 ( ARCH00231 ) ;
--
begin
CIS1 : UUT
port map (
toggle ,
i_boolean_1, i_boolean_2,
i_bit_1, i_bit_2,
i_severity_level_1, i_severity_level_2,
i_character_1, i_character_2,
i_t_enum1_1, i_t_enum1_2,
i_st_enum1_1, i_st_enum1_2,
i_integer_1, i_integer_2,
i_t_int1_1, i_t_int1_2,
i_st_int1_1, i_st_int1_2,
i_time_1, i_time_2,
i_t_phys1_1, i_t_phys1_2,
i_st_phys1_1, i_st_phys1_2,
i_real_1, i_real_2,
i_t_real1_1, i_t_real1_2,
i_st_real1_1, i_st_real1_2
) ;
P00231 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_boolean_1 = c_boolean_2
and i_boolean_2 = c_boolean_2 ;
correct := correct and i_bit_1 = c_bit_2
and i_bit_2 = c_bit_2 ;
correct := correct and i_severity_level_1 = c_severity_level_2
and i_severity_level_2 = c_severity_level_2 ;
correct := correct and i_character_1 = c_character_2
and i_character_2 = c_character_2 ;
correct := correct and i_t_enum1_1 = c_t_enum1_2
and i_t_enum1_2 = c_t_enum1_2 ;
correct := correct and i_st_enum1_1 = c_st_enum1_2
and i_st_enum1_2 = c_st_enum1_2 ;
correct := correct and i_integer_1 = c_integer_2
and i_integer_2 = c_integer_2 ;
correct := correct and i_t_int1_1 = c_t_int1_2
and i_t_int1_2 = c_t_int1_2 ;
correct := correct and i_st_int1_1 = c_st_int1_2
and i_st_int1_2 = c_st_int1_2 ;
correct := correct and i_time_1 = c_time_2
and i_time_2 = c_time_2 ;
correct := correct and i_t_phys1_1 = c_t_phys1_2
and i_t_phys1_2 = c_t_phys1_2 ;
correct := correct and i_st_phys1_1 = c_st_phys1_2
and i_st_phys1_2 = c_st_phys1_2 ;
correct := correct and i_real_1 = c_real_2
and i_real_2 = c_real_2 ;
correct := correct and i_t_real1_1 = c_t_real1_2
and i_t_real1_2 = c_t_real1_2 ;
correct := correct and i_st_real1_1 = c_st_real1_2
and i_st_real1_2 = c_st_real1_2 ;
end if ;
--
test_report ( "ENT00231.P00231" ,
"Associated scalar out ports with static subtypes",
correct) ;
end process P00231 ;
end block L1 ;
end ARCH00231_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl/STD/standard_orig.vhd
|
1
|
2611
|
-- This is Package STANDARD as defined in the VHDL 1992 Language Reference Manual.
package standard is
type boolean is (false,true);
type bit is ('0', '1');
type character is (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del,
c128, c129, c130, c131, c132, c133, c134, c135,
c136, c137, c138, c139, c140, c141, c142, c143,
c144, c145, c146, c147, c148, c149, c150, c151,
c152, c153, c154, c155, c156, c157, c158, c159,
-- the character code for 160 is there (NBSP),
-- but prints as no char
' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
'¨', '©', 'ª', '«', '¬', '', '®', '¯',
'°', '±', '²', '³', '´', 'µ', '¶', '·',
'¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ' );
type severity_level is (note, warning, error, failure);
type integer is range -2147483647 to 2147483647;
type real is range -1.0E308 to 1.0E308;
type time is range -2147483647 to 2147483647
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
subtype delay_length is time range 0 fs to time'high;
impure function now return delay_length;
subtype natural is integer range 0 to integer'high;
subtype positive is integer range 1 to integer'high;
type string is array (positive range <>) of character;
type bit_vector is array (natural range <>) of bit;
type file_open_kind is (
read_mode,
write_mode,
append_mode);
type file_open_status is (
open_ok,
status_error,
name_error,
mode_error);
attribute foreign : string;
end standard;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00259.vhd
|
1
|
2050
|
-- NEED RESULT: ENT00259(ARCH00259): Different architecture bodies with different entities may have same name passed
-- NEED RESULT: ENT00259_1(ARCH00259): Different architecture bodies with different entities may have same name passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00259
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00259(ARCH00259)
-- ENT00259_1(ARCH00259)
-- ENT00259_Test_Bench(ARCH00259_Test_Bench)
--
-- REVISION HISTORY:
--
-- 16-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00259 is
begin
end ENT00259 ;
architecture ARCH00259 of ENT00259 is
begin
p :
process
begin
test_report ( "ENT00259(ARCH00259)" ,
"Different architecture bodies with different entities" &
" may have same name" ,
true ) ;
wait ;
end process p ;
end ARCH00259 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00259_1 is
begin
end ENT00259_1 ;
architecture ARCH00259 of ENT00259_1 is
begin
p :
process
begin
test_report ( "ENT00259_1(ARCH00259)" ,
"Different architecture bodies with different entities" &
" may have same name" ,
true ) ;
wait ;
end process p ;
end ARCH00259 ;
entity ENT00259_Test_Bench is
end ENT00259_Test_Bench ;
architecture ARCH00259_Test_Bench of ENT00259_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00259 ( ARCH00259 ) ;
for CIS2 : UUT use entity WORK.ENT00259_1 ( ARCH00259 ) ;
begin
CIS1 : UUT ;
CIS2 : UUT ;
end block L1 ;
end ARCH00259_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00366.vhd
|
1
|
14635
|
-- NEED RESULT: ARCH00366.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00366.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00366.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00366: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00366: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00366: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00366: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00366: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00366: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00366
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00366(ARCH00366)
-- ENT00366_Test_Bench(ARCH00366_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00366 is
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
end ENT00366 ;
--
--
architecture ARCH00366 of ENT00366 is
subtype chk_time_type is Time ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec2_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_rec2_vector_select : select_type := 1 ;
signal st_rec3_vector_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_st_rec1_vector )
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(lowb).f2 <= transport
-- c_st_rec1_vector_2(lowb).f2 after 10 ns,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00366.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(lowb).f2 <= transport
-- c_st_rec1_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec1_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(lowb).f2 <= transport
-- c_st_rec1_vector_1(lowb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00366" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(lowb).f2 after 10 ns,
c_st_rec1_vector_1(lowb).f2 after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(lowb).f2 after 10 ns ,
c_st_rec1_vector_1(lowb).f2 after 20 ns ,
c_st_rec1_vector_2(lowb).f2 after 30 ns ,
c_st_rec1_vector_1(lowb).f2 after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(lowb).f2 after 5 ns ;
--
CHG2 :
process ( s_st_rec2_vector )
variable correct : boolean ;
begin
case s_st_rec2_vector_cnt is
when 0
=> null ;
-- s_st_rec2_vector(lowb).f2 <= transport
-- c_st_rec2_vector_2(lowb).f2 after 10 ns,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00366.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_vector_select <= transport 2 ;
-- s_st_rec2_vector(lowb).f2 <= transport
-- c_st_rec2_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec2_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec2_vector_select <= transport 3 ;
-- s_st_rec2_vector(lowb).f2 <= transport
-- c_st_rec2_vector_1(lowb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00366" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec2_vector_savt <= transport Std.Standard.Now ;
chk_st_rec2_vector <= transport s_st_rec2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_vector_cnt <= transport s_st_rec2_vector_cnt + 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(lowb).f2 after 10 ns,
c_st_rec2_vector_1(lowb).f2 after 20 ns
when st_rec2_vector_select = 1 else
--
c_st_rec2_vector_2(lowb).f2 after 10 ns ,
c_st_rec2_vector_1(lowb).f2 after 20 ns ,
c_st_rec2_vector_2(lowb).f2 after 30 ns ,
c_st_rec2_vector_1(lowb).f2 after 40 ns
when st_rec2_vector_select = 2 else
--
c_st_rec2_vector_1(lowb).f2 after 5 ns ;
--
CHG3 :
process ( s_st_rec3_vector )
variable correct : boolean ;
begin
case s_st_rec3_vector_cnt is
when 0
=> null ;
-- s_st_rec3_vector(highb).f3 <= transport
-- c_st_rec3_vector_2(highb).f3 after 10 ns,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00366.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_vector_select <= transport 2 ;
-- s_st_rec3_vector(highb).f3 <= transport
-- c_st_rec3_vector_2(highb).f3 after 10 ns ,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ,
-- c_st_rec3_vector_2(highb).f3 after 30 ns ,
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec3_vector_select <= transport 3 ;
-- s_st_rec3_vector(highb).f3 <= transport
-- c_st_rec3_vector_1(highb).f3 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00366" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_vector_savt <= transport Std.Standard.Now ;
chk_st_rec3_vector <= transport s_st_rec3_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_vector_cnt <= transport s_st_rec3_vector_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_rec3_vector(highb).f3 <= transport
c_st_rec3_vector_2(highb).f3 after 10 ns,
c_st_rec3_vector_1(highb).f3 after 20 ns
when st_rec3_vector_select = 1 else
--
c_st_rec3_vector_2(highb).f3 after 10 ns ,
c_st_rec3_vector_1(highb).f3 after 20 ns ,
c_st_rec3_vector_2(highb).f3 after 30 ns ,
c_st_rec3_vector_1(highb).f3 after 40 ns
when st_rec3_vector_select = 2 else
--
c_st_rec3_vector_1(highb).f3 after 5 ns ;
--
end ARCH00366 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00366_Test_Bench is
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
end ENT00366_Test_Bench ;
--
--
architecture ARCH00366_Test_Bench of ENT00366_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00366 ( ARCH00366 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
)
;
end block L1 ;
end ARCH00366_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00635.vhd
|
1
|
129785
|
-- NEED RESULT: ARCH00635.P1: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P2: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P3: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P4: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P5: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P6: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P7: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P8: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P9: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P10: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P11: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P12: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P13: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P14: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P15: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P16: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P17: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed passed
-- NEED RESULT: P16: Inertial transactions entirely completed passed
-- NEED RESULT: P15: Inertial transactions entirely completed passed
-- NEED RESULT: P14: Inertial transactions entirely completed passed
-- NEED RESULT: P13: Inertial transactions entirely completed passed
-- NEED RESULT: P12: Inertial transactions entirely completed passed
-- NEED RESULT: P11: Inertial transactions entirely completed passed
-- NEED RESULT: P10: Inertial transactions entirely completed passed
-- NEED RESULT: P9: Inertial transactions entirely completed passed
-- NEED RESULT: P8: Inertial transactions entirely completed passed
-- NEED RESULT: P7: Inertial transactions entirely completed passed
-- NEED RESULT: P6: Inertial transactions entirely completed passed
-- NEED RESULT: P5: Inertial transactions entirely completed passed
-- NEED RESULT: P4: Inertial transactions entirely completed passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00635
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (6)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00635)
-- ENT00635_Test_Bench(ARCH00635_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00635 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
signal s_boolean_1 : boolean
:= c_boolean_1 ;
signal s_bit_1 : bit
:= c_bit_1 ;
signal s_severity_level_1 : severity_level
:= c_severity_level_1 ;
signal s_character_1 : character
:= c_character_1 ;
signal s_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_1 : integer
:= c_integer_1 ;
signal s_st_int1_1 : st_int1
:= c_st_int1_1 ;
signal s_time_1 : time
:= c_time_1 ;
signal s_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
signal s_real_1 : real
:= c_real_1 ;
signal s_st_real1_1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
--
signal s_boolean_2 : boolean
:= c_boolean_1 ;
signal s_bit_2 : bit
:= c_bit_1 ;
signal s_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal s_character_2 : character
:= c_character_1 ;
signal s_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_2 : integer
:= c_integer_1 ;
signal s_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal s_time_2 : time
:= c_time_1 ;
signal s_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal s_real_2 : real
:= c_real_1 ;
signal s_st_real1_2 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
signal s_boolean_3 : boolean
:= c_boolean_1 ;
signal s_bit_3 : bit
:= c_bit_1 ;
signal s_severity_level_3 : severity_level
:= c_severity_level_1 ;
signal s_character_3 : character
:= c_character_1 ;
signal s_st_enum1_3 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_3 : integer
:= c_integer_1 ;
signal s_st_int1_3 : st_int1
:= c_st_int1_1 ;
signal s_time_3 : time
:= c_time_1 ;
signal s_st_phys1_3 : st_phys1
:= c_st_phys1_1 ;
signal s_real_3 : real
:= c_real_1 ;
signal s_st_real1_3 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_3 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_3 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_3 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_3 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_3 : st_arr3
:= c_st_arr3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 10 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 20 ns ;
--
when 1
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 10 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 20 ns ,
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 30 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 40 ns ;
--
when 3
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <= transport
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 100 ns ;
--
when 5
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 10 ns ,
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 20 ns ,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 30 ns ,
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 40 ns ;
--
when 6
=> correct :=
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 40 ns ;
--
when 7
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_boolean_1'ACTIVE and
s_boolean_2'ACTIVE and
s_boolean_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 10 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 20 ns ;
--
when 1
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 10 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 20 ns ,
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 30 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 40 ns ;
--
when 3
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_bit_1,
s_bit_2,
s_bit_3) <= transport
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 100 ns ;
--
when 5
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 10 ns ,
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 20 ns ,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 30 ns ,
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 40 ns ;
--
when 6
=> correct :=
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 40 ns ;
--
when 7
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_bit_1'ACTIVE and
s_bit_2'ACTIVE and
s_bit_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 10 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 20 ns ;
--
when 1
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 10 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 20 ns ,
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 30 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 40 ns ;
--
when 3
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <= transport
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 100 ns ;
--
when 5
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 10 ns ,
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 20 ns ,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 30 ns ,
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 40 ns ;
--
when 6
=> correct :=
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 40 ns ;
--
when 7
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_severity_level_1'ACTIVE and
s_severity_level_2'ACTIVE and
s_severity_level_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 10 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 20 ns ;
--
when 1
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 10 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 20 ns ,
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 30 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 40 ns ;
--
when 3
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_character_1,
s_character_2,
s_character_3) <= transport
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 100 ns ;
--
when 5
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 10 ns ,
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 20 ns ,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 30 ns ,
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 40 ns ;
--
when 6
=> correct :=
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 40 ns ;
--
when 7
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_character_1'ACTIVE and
s_character_2'ACTIVE and
s_character_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 10 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 10 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 20 ns ,
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 30 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <= transport
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 10 ns ,
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 20 ns ,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 30 ns ,
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_enum1_1'ACTIVE and
s_st_enum1_2'ACTIVE and
s_st_enum1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 10 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 20 ns ;
--
when 1
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 10 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 20 ns ,
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 30 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 40 ns ;
--
when 3
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_integer_1,
s_integer_2,
s_integer_3) <= transport
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 100 ns ;
--
when 5
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 10 ns ,
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 20 ns ,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 30 ns ,
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 40 ns ;
--
when 6
=> correct :=
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 40 ns ;
--
when 7
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_integer_1'ACTIVE and
s_integer_2'ACTIVE and
s_integer_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 10 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 10 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 20 ns ,
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 30 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <= transport
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 10 ns ,
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 20 ns ,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 30 ns ,
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_int1_1'ACTIVE and
s_st_int1_2'ACTIVE and
s_st_int1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 10 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 20 ns ;
--
when 1
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 10 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 20 ns ,
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 30 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 40 ns ;
--
when 3
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_time_1,
s_time_2,
s_time_3) <= transport
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 100 ns ;
--
when 5
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 10 ns ,
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 20 ns ,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 30 ns ,
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 40 ns ;
--
when 6
=> correct :=
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 40 ns ;
--
when 7
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_time_1'ACTIVE and
s_time_2'ACTIVE and
s_time_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 10 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 10 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 20 ns ,
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 30 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <= transport
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 10 ns ,
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 20 ns ,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 30 ns ,
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_phys1_1'ACTIVE and
s_st_phys1_2'ACTIVE and
s_st_phys1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 10 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 20 ns ;
--
when 1
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 10 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 20 ns ,
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 30 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 40 ns ;
--
when 3
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_real_1,
s_real_2,
s_real_3) <= transport
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 100 ns ;
--
when 5
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 10 ns ,
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 20 ns ,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 30 ns ,
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 40 ns ;
--
when 6
=> correct :=
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 40 ns ;
--
when 7
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_real_1'ACTIVE and
s_real_2'ACTIVE and
s_real_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 10 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 10 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 20 ns ,
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 30 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <= transport
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 10 ns ,
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 20 ns ,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 30 ns ,
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_real1_1'ACTIVE and
s_st_real1_2'ACTIVE and
s_st_real1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 10 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 10 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 20 ns ,
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 30 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <= transport
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 10 ns ,
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 20 ns ,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 30 ns ,
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_rec1_1'ACTIVE and
s_st_rec1_2'ACTIVE and
s_st_rec1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 10 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 10 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 20 ns ,
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 30 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <= transport
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 10 ns ,
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 20 ns ,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 30 ns ,
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_rec2_1'ACTIVE and
s_st_rec2_2'ACTIVE and
s_st_rec2_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 10 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 10 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 20 ns ,
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 30 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <= transport
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 10 ns ,
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 20 ns ,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 30 ns ,
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_rec3_1'ACTIVE and
s_st_rec3_2'ACTIVE and
s_st_rec3_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 10 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 10 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 20 ns ,
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 30 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <= transport
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 10 ns ,
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 20 ns ,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 30 ns ,
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_arr1_1'ACTIVE and
s_st_arr1_2'ACTIVE and
s_st_arr1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 10 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 10 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 20 ns ,
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 30 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <= transport
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 10 ns ,
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 20 ns ,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 30 ns ,
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_arr2_1'ACTIVE and
s_st_arr2_2'ACTIVE and
s_st_arr2_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 10 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 10 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 20 ns ,
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 30 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <= transport
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 10 ns ,
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 20 ns ,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 30 ns ,
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_arr3_1'ACTIVE and
s_st_arr3_2'ACTIVE and
s_st_arr3_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00635 ;
--
entity ENT00635_Test_Bench is
end ENT00635_Test_Bench ;
--
architecture ARCH00635_Test_Bench of ENT00635_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00635 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00635_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl/IEEE/synopsys/std_logic_misc.vhdl
|
1
|
33614
|
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--library SYNOPSYS;
--use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
--attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00071.vhd
|
1
|
51479
|
-- NEED RESULT: ARCH00071.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P3: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P4: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P5: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P6: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P7: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P8: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P9: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P10: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P11: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P12: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P13: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P14: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P15: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P16: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P17: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00071
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00071)
-- ENT00071_Test_Bench(ARCH00071_Test_Bench)
--
-- REVISION HISTORY:
--
-- 06-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00071 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_boolean = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_boolean )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_boolean <= transport
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P1" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= transport
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_boolean <= transport c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_bit = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_bit )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_bit <= transport
c_bit_2 after 10 ns,
c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P2" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= transport
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_bit <= transport c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_severity_level = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_severity_level )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_severity_level <= transport
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P3" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= transport
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_severity_level <= transport c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_character = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_character )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_character <= transport
c_character_2 after 10 ns,
c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P4" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= transport
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_character <= transport c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1 = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_enum1 <= transport
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P5" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= transport
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1 <= transport c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_integer = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_integer )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_integer <= transport
c_integer_2 after 10 ns,
c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P6" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= transport
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_integer <= transport c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1 = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_int1 <= transport
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P7" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= transport
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1 <= transport c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_time = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_time )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_time <= transport
c_time_2 after 10 ns,
c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P8" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= transport
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_time <= transport c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1 = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_phys1 <= transport
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P9" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= transport
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1 <= transport c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_real = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_real )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_real <= transport
c_real_2 after 10 ns,
c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P10" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= transport
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_real <= transport c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1 = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real1 <= transport
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P11" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= transport
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1 <= transport c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1 <= transport
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P12" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= transport
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1 <= transport c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2 <= transport
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P13" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= transport
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2 <= transport c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3 <= transport
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P14" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= transport
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3 <= transport c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr1 <= transport
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P15" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= transport
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 <= transport c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr2 <= transport
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P16" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= transport
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 <= transport c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr3 <= transport
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00071.P17" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= transport
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 <= transport c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00071" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00071" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P17 ;
--
--
end ARCH00071 ;
--
entity ENT00071_Test_Bench is
end ENT00071_Test_Bench ;
--
architecture ARCH00071_Test_Bench of ENT00071_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00071 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00071_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_output_block.vhd
|
9
|
17048
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZDbLXMCW/rFA4qQp7M4XtRAVOMy7+62OqdKd3dOe4Jvb/C2JADukHaa3oslAf5TtlaTLr3ozEohl
VKGhLio1ig==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Y/syMaBfRSQ9MD98NKAleGixPcntMfRl9i4DpBCi/l65gO8EpoXWOhQZbbZ/maNd7yin7yuO19Yn
GGuE9YDWOl8XBpG3phkcKzJdSu0mKYd+0AQJj9q1lFv6qrGMoUttsl/IpN2yMUpz5fUapnIBd6rb
mRz2FHrHicaebKc88GU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FF+Cl3PgjNR7xzwHRMbIHqn9oRbNDNLj8DIaO1Hlm+2QX1CI/VCFdTgjthL/wOzU50VEXfI4vdA+
5GN341oMmZ0O5YACNPw0jsmb5K/Axml5iblkv1aO205Ys1mBMBZkaFGlBcZsIV0uEzUDpOvPfeVc
ABQXYw6KbTA1+NUfxZFROZrc/rjF2mQh4nDUCfFYZPrriJZjjyEjlSX+cy4KzCuZbbpJBCFd6XxQ
koLohsN3xKemISIPZsKR/aiic3+A4CLGXARU2+NNZ8Y9zw6ZjLQLvFiy4Fb1QeehEhg6MMEY/h+t
IjJP8sZ2k68e+ilMbQE8db8f77x7eXxc0dya2Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WftP1jT77k0S0KW6WZKPHR28tgdkvbiMqDTC2VCWXKRGglkNUJl3J5a6mxg7KN6NyWhnYj6a5QQx
8Hz0va2ePEpBUyQNGP6NCbGXeaRe8pCPsXgRKTVJmrMqDjyhAZagmIXcKOaLXzSspWEBEQiSDaSF
bOXSgmj7JNe+zDKqwGQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RqlUBtgum9dv43EmKmtzWIjfHZGaDUNQ3TN8Yu3IeXyJKi5cWCoW72Oqm8t5IbLFWHnY2SKPDquO
q9pnAH1xYve2UU/ki12sb1zBNCPYJNGoVMVoYZ+WBiTxkJRS6r3QcID+4PLSLBrCx6FOaNYxyz+N
HNXn1tfTA8+dazSGeer4nW4ht7uWxXKe8ZcSvezFDU3/Z+p+x33qF8Pn4hTSjcYP4oZL0Zy9vG3Q
RhJw+4Hx1YmXbpfrBWVqQOuYui18fd1gpad/b4yH9e+H5xWbSO//cFWXzEE/cO+APY0/xbSvI9qd
ejSJhSc7iuIlnvzmNk5U33IYSygGzh0yfq6Rzw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10880)
`protect data_block
RnRPKi9jEml7Lu5FUKT7enOKOvnc34gbCzO7zvUDeHtG+GUynXRcFA+rsSsRPbZpqCjxxTzp5Qun
6WLhdv9L8FEaS9Q1jhKlkGFB55l3+p4qQKTbx5MVd+YUJ7Zu/kMglcFpSUa+KoqO0Z5hy73i0hJN
4NWbm8nVqK+W+TFXMYBWUUv8aiJpbk5rUX8c6NP6epVkFpLlR9+peyLunYEUenGU2yYjoi+w4gtO
OAZyJQPBi9ZX8ALBo4pje3GMW8fT+0WHbsQkbKnYPch58C5QTU8YIT2U0NIcMcjLTsDD+GLUXDQU
aP3GFY0KrHDO38Ke6b0TZ8R6ZgY4JLkL71PDr2vR6Od+oeWjcrlbRoZ31NGIPlUw/vRIHffn0MhN
n6Oe1LnKgVQEoM0cMX2+Y8CNaQziX0WvHey9nc+tDwS6a8IM+cdehwfaq+v9e1w4nHGXFHvMrv7J
XgLd+PPj396aHL6S2ZYlNiHfhXRYUx3DE5auKfrIjltk3Bc5PmZdzU1DuM+PehEMoY+41BzATXuO
M0rimqNeckoKlFFfyzpEKA/YyHms8EilZ9c1PQBQEet4iiy01BfHig40wlrTze26i5PhsCcghh6g
kxThOdU4t2aU3UQaMQuWIxnuWt4Ms5Ob5sqoAX2hHVEKvP2U8s+LrZqG+dELEpbkIhAgyCMBNgj0
Inhi82+4rU62Zsus9Hlq/pKchL9ztrRYBH9hrpcl8bIqvnNh3vlWmZdcwrpfjG0deANc0vHZstJt
Bux6IBdaMBCwPHADTTlvQeXcyZO9VTy/D93ncxXeaJ/FuzjaBl7UQo1T4y9eRYCni3N8HqoqDfcO
EtYJmnRFzVlQyk7tTpWXKhu1JRkOd86AUtW6n2bth+0bZsX0trG36iSx4BZaMZeiEAejxtWZ8kJu
1KgWqEPL+pbgmjoeYfma2EPnJ/UAM9rTbFS0Bai51DLaBlNC1U6SfXm6VPLkwFVyqn7+GhVh4kRs
Q9BWCrDMXyJGW+kaZ/EuSavt/v5hXOLwrq6LVA5rtiETpgT7mqQL99fPqpqX/qYf0mMtJyfCwJTC
bvOM/L6wHzNAcMQK2E3h8hiWJxwMZyl33SuiaHuH4bxd6Bf58uN80KkwCsMsOT/5hd3U5yWRnrPp
BwD7Z6zUtVxmvJT6eVMnzfy5dkJyk6aBT79JiWZz7ITFWyFn8k/SBtzeQTL0Pb8oHDBmNOkk3qXB
g6fhSUJAvTp0Rjf5K440RObNehIbuCZ3uMvp/PhUB/KhfzQdCgduJxkmcOT0UuzyxRdMgK5LE/6x
9CLyhKqHxOY7Y9yjPF62alcETmAnXFqdyUnVCutzYUwo+VON3IKhy/pdq/PjXa6yRrCygAmVw92B
cre0eVZLOE5ew0k0fS31pORFlo4LuowaC0yJZm3TYYCQSTFYxkJlM6jeK4BWmSoPmfBRBwMjDpTR
8v0r4pThYzeSWt1CBCmEYq94F5gKOo3cQ/lchV5zKIrdIA11jYExInchOGFvdWSuhHyKWEmiouKI
Adt+ttvJEqRlSdVZwdnUI6+oqIhBrZIdBKMXRNA+0lWs4MzFdl5odIpqRfoRG+Ck2LWdfUoygEHK
WAdLmxQyhHkmjqoq/Mg3uujQLFrby/gMbq4A2udy2d+4oh2tAjWSLd+4qvxuiUMIlSEl/RPqFFpz
Kl69jJkW6MHYQS4WG93Ui+ANIRpFYz7pGGPEbEu3p/pUVI2uI6ImNLV75vl4f9VNDkwCrFZ2wzUI
H+eTezozAHiLmLHJZOOuBrXbBEeiPomOHeqQ9RIXe4w4bfFfarpyIsGLSkxVZbiPYVz/2uzZngqy
+1n/FVO+S46DODztVlVVGMI7Ty8An0jFsKZS1Rw8Om7udaY5sFOdmp8NTCzeOMRiKU993LbyGf08
QXeD3OUratg46nyrMATDQu0xOAur/bdd1dxJUbWiY8emyKA0A/OFYQv98Dw5A/5fV2ffZnRvFYn9
p819ZVFdaGG25z83D53gM72aw58WtvDBThrfhPYiOmGCnsNwzevdhYuxXzVVoRm3XiSkkFlVkzYW
kAPtY9cl4YqdkJicSys+5Lo/n2NqItSj9TJ/yVO4Hbf3/hwuomKyNZ+0uYjetwhGFomSuDrdTKLs
wnudxVbD4U5ceP0Xuob56QwE4ovuR17hOy8fw6ZA3pXf1hd5WDA/tQCEriKruwJ2x3dfatTREspE
ZiCXueZWz4iUCRgFtDZAWD37FVVb8aJ7Utj/KuPDyIqujW1uTHXPC8YC4rFOiLsp02Fk/HRTXrUu
6a+RIG2x7cfYFP06joczzSRGLcg+MZlpwv2H9AlteR3Dmom0B6+h5/EwV2DEU/rht43L5kOaDmDK
sPtA3cL5+CJnnclUki9sq2W//NhWAxAsrF8Z1FRtq7f6gmeNRtP7D81NRihHJmAp6mPdepYnW+1G
bfxFWRqiirXLzXGWRENU9VGJ5mRxZRloFknCJb1tEf4FKsBy3XVr2dybjeijp4AHBTSmlMgHP7m1
yC/y+OaBc3fPnOsr8eQ+iwpFGWfLuQxpm2ozCW0uGT0sxh+dXO5lPCHXAAs28ygSLeq6EDi4ObD4
uNm7vEG0yewGgcyBcaKmjDmtoECVUsMVnDc0VuFR9xgTnJ1BTodWR+9nA5ENs1prEHe2fYQE0gsx
MycdXoYIxZekXPbVkgxLDnEgYg4X8ElIwCpsMdEnbkOZC1dlZZOO8h2P+BvjynE/3DGBzbkHVtRP
dOqMLVImqDhmrk1JrbeIlbg/Qrbts70QVTCmAfw081DhqzFHvGnmcPqJXkt809gPqe1joZ1+K+0R
qDDqTzPQL2tA569sWN7UiPX+yqzfqibwJxFXNJ4Li1F99xxyluiX2cmkGboac81yO7OqziAoSspJ
YyjrtwRIy4Rjuf1BAOd6bhQVSXaXDVJbr1ZGk1Afyp4ddLZWQc04NYriBsCgFw4iSl5TuK4OTvOv
871+VmklUyogTiJegUQX2M+L7T1Yq6pAYKsufo3an6zUSmbMN/9kY2dPJdKKIC03G/4/OpxlLo/a
WLhxMkWVjPemmHVQhibRl1IlVIrLClpSvhE7n/na5EaM1xej/J4CKwNZFwhG40xfvUXSWxSjIpG7
zVvTgB3+eVKFS2t2/JUvHsTPN9Cjad2EiWY1lanZ/pkkYYTbIxAqHj0rS+l66aXqb1BmatdcZIOd
sjTpGPK7fRvwYlOZUJKqVM1epE8Fm1jMdL9cY4gfCNrFu50rIT9VvnCVduuuA7lDtxauMVWR1qKz
0ecD4kMWpK9pcX8eRgoNvJnqrP6wzQdAzAl78qCaYyqF/YQePBbHO7M8ixvaBI6rA+XUWK9gV8U8
QySkkBt+OByPVsZ56m5hCAE/3NVLKlBev9vPGuVVMiXLOyXYIwTRQroN4YLxNWqtJM10XHeKADoG
7OmWKpCjh7AGxzAYcaeEdONW5GvVQ/5M47evphkKxMpaXlMeMMgQSICjN18dm75lpXNjvurvdZrN
GDDhJb73T8yct1yQGomqbth82tcKeWQXGdTuj94yvDRwb7TU7wXa/84cbmHzXJqXRST7j6mc3SB/
43Rqa04OHWf03U1mP/aVAr9OSaOr08Do/MA/6iayrCBmFGlOjmh5csfUK2cKhl/yPWHe9uW9Wl4p
mlg6UyeEWR8hrdr6tvIN1VwfsiVoYVfQi7uwvM4dsT07KlfxE1x8Vi249sy9KyTCa9RWBu7SOQcn
MIFvnlVDY5wSCht5TP1hxXQct2F4k351/xGqvqB1Ouikn8SCmfbtTgOdL3CeEnjtVLKdCN33ryrk
dSxgdpwEUrxKyNVr8OvJY/RVrC0HoTdSoh72Imw7Waj+M+vpqDk5GwkNRxNQyR+CkxFCpzn87980
dJL3nEuy8zMqqDue154EpRiz6SajQF+dKz9iTJWLedGtczEkBuCL9MP8gd0K/umt6vQTiWTLy/As
XPVo/2ISYwdcU4vQS+5jjzp1OSwu8CyaeXq+F4zm6B4fY7Jhhn/0QQSuxGy0sxLayuZvJ/XUqf0F
uJubjPFq4paAz66mB6ZiYHCubiX65Yv2DOyF1jVObZE4WcCNhc69RTgeQ8s6JVqVztWpRSZBMGLq
hj7ZcZQn1SUU1L//bXTN3Zf5qPi4iuhk5TDjfqTYnwAs/dHQzuBsaClL6fLkHgHbiR1nAJ99Ga0j
qrRFBq7kk6i2MAO/7WtPfwnuV4VtFJsFuASGp7pgv4TLlG+lJwE3Bx/X8AK3+hd9zkrESZPZfzJh
YyVI/SjId9fwoyEgrOGBZFe5cB5GRetIxHVWvEWdR+BNv30GM7puwMkSDgQfULraG6j+BufnYfGo
qxnlc8pmmySIBYd2XDvCZWdt+LLTXCGpu4tRcpkL2utiRXkUpoaCqO8ZI55X1lSigYQg9PzgmpZb
CYkITKloliol+rhHMBx9X8sOJubHfkkkgscxcMoWC9Q1dQSAONR+dg7XHdadzg3YZSWzshF64TI1
hHgdhKNCQvBr3E3jXN8wQLmy311a74zy4USwRB9lwvSEFyVjx083i/3L/98ymRlhnlO9rfvWeE4T
vnGn+qyJEoZmjY1zhjMc9zHisj4Vzpd60I8g1dxsxlSoPEwBbzz4BscQYyrpJKIRkS8hrGunPBLl
0H2lC4CZLO6P4+VZ/oiK8CahZ6ZiYCvpiVvfa+y2PJs5sBqldgwLdtFBGFh6+dsSkD5SXOUAc4Rd
Mqp8QFAOKZzOdtJegswk67ch/0DxGdDLVm6awQ2VsM+yk8YbPW1S2C0yEtO4FgNHt1WUC+BWARHb
a2gr6kcCfaMKpw/H44709wtU83Rys6T2Fbdw+1KpqPOnAs1xv1ae5TO7qFP2JNbAeZQns6dJHskq
CPmgQ6S83j8Cx3hJBmynvOErv5hPVphlfl33ITpwumxR17lBCC5qD8WvLmgRhKHL/nL1VJITTVBO
jJ8Mc2aecViN1F9bQZOqau2aZyUMVNFmBrPhM9xUDcBiga9qXwX3rwGLtI+yfhSH8wA7c2SWwN+F
08AW/edx29X2cqRXhJBNI+CndbcECfZ92QE+YldnTPwYnlXciv8hcKRUCzxhrLrzzHCIBU5VUB3V
JiWnZMzVOVvso6gX1s7cD2/gsDZkKcTcSLfC+O9s+8NKcZ6/jezNnnZMB65LeUGBr9V68BqF6uOk
6WoahcUciuohCvT0s42Uak64KRT9jWSIF14tzLqTH58mNyeFtLOwxEp4L31qQZ0+LcLW9uCYchfP
Ixdtgo42dBrhEpl0PHGmV3WfFdO6JEMQLQyfv0octd064fEYYGph8+2L8cp34jztfGljtbEVZePq
lxRBd/B1gjsqH1geSHj79gLywLfgnkM48NXw7Sx0PHkDsyEo58ybiyS3x1sF2LkE1e+Q32ukxxxk
g/ZUXAvwhB+7UU/xtX6bkGc4bAI3yRaVkQC5Ur5mBzQvH6LzGcsV0jdEqFTQKrT3Rfebi7W2I5oM
FwuFD3MCho0yY1dnmVul8pNutzBZuGXCT3jMUf9IQN5rxCdPqgbpwfetLuEoGFWhRTOyiSPjmPli
vQ++IUHQe1kwLBAMaT5mf7eI5D3TJytxgMY7sStxyH/bMDXQs47aKoWC9jruRUcGve8l8RuA4Rql
aXPyI1uEKhoIYCfFOYCJDCJblHLsKtQYoKtqZsd1QLpT2QrSa7ApsZikziWLXRXoedkprdvm4K6O
x6G8zP7vlmSC/X5SzYhu9KqiPUWfb+MuTy6COJqLLYcTwxXFvlPYX73/+TQqB4CEpRglX6Ovqkxd
qIQrX4Bedx8t5ppQ7ZqQ7QmIBQ7nI0Xl3Tj8mMrdSZQyCZJIilcJ2ZpTMDrLytYnXUUueundrxHZ
j8Tx+sDWzpB0oO8guFPYG3nLYBWZxOnVB9DK393gGTmcdIAG2S55UJf6vKRUl0u67iEv6y7WYc66
U39NTbTLElgYl8qDed6dcBxF3d4OKjFoy0vZbLG9iRCWvPBz/X93FYeK//u1zOm5CIi5cU6sG6m6
M6MAUPPvi8/Z/0FxyRWeCvMvwRGjg+YXqJg1xXOMuiMsledRHTmbCfQuxuCERzzCxPiwU9gthViA
lUQc96DLsaaxozWrHY/bL5QJtq9JN30KJR4/fgPNHhBYWAvHD7oDhuFrBqZyn5T8ukRfZaQxEEDS
8r6GuRLD83yvpAyqJLEgwB7rCRFIp+9Fwh4Hm1PvyIKh+j/luPInNWUJWJZfwP35W4Nreg2olAm6
L2i2xh5AZQvB2U3pR+Marlw4pLj6LNM3blmmibUn837LXLAlYlijJof6N5tvi1PV5DX21DWuh8mI
grfbTMd/B+jrOtTI1NIcXXNHRAWgDfnfhH+3C3zgfIIMRuWQ92gRKE8U2XVngejX5ObgJNIYm0u+
pivXrJxHwQ0xnR5koAg6v7pK93Pv9SXmKz49aknXl1Z8ZtDOvKDRANtMtaP9Eh3r/VQksT776Sn+
63zTDGuHj9jqWLjGt+OnbtSG/IDT3v7W9HOvuLvBKaZc/Am3cX5oHbC9QHcBXAhsO/5PGesdDYzR
9tiaROWgDUZl8zi0EOM/171FL9W96CGyOUH4JBNZI4YGQDt6Zaou767sXsJTrXd5VHEKcnX6gqUS
y3K/ycfn+NUx8YVr6Rh1VRD5RnBq40DLBQPry2kg8grqf/lFKeRZxioKelcrndbqPXhZ+tujaTnO
CmJ90be42ovBjOz/WDm/BFHnGyH//AplCg02QZLC2yH0UihxubCPQQzbR3hxdpKp/WeNlt6PPDXW
MAEmXOquvia44bZ16IZGs2pU6vnqBxdLKzCtTFSpuULo9jNFyAIt0EZXO3uX6QbkpXPfKA6W93Da
K2X8heZHSnpV8Eju2IUusC2Tn3BrKpXd9JagIQToGFxzwOFEveX+hYyuWYUxz2T04jEDzWYRx3nY
Zicut1JNKebA6w8c9FKP+55Pbc5OCgTBZ2m+Rk/NZgHoR2ID3k0xzSl0jDUikDxRWVqMi/NTnhB7
Dghi4Tw5XiaMqmYh0C31b07OEkTnIMuOvSx+pc6mxV21iOHbdJsu1qKNxCiQo8/XkdtzBz5PeGnz
bUaFy6bDVROaCqrzTg4lo0BxNChneUdakpQcQXbMvHcDF0Z6REFHXZYn3tpNSOU1LG5YBzgVy+SX
E2vE2Fm0BiG5Z9MmbzehF6anRINl6ltHAfINNu0nu5HYLDnnwOIKkfjtJzD1wE5qxC2nCxqMSapt
UpQIh6Ff1w7FHjbWoXTNONQPgHR8f+CHHcDKdYExpbWgQ/hIPBl0qC0UODcOqB/xMLXcSGZT/iRT
OrLjhfxOccu3+J0Xf0TpW57/LnjUXWl/A5LQ9OtulNLnNM7MAiYd5riTTDIBV3fjGN1/ggqej9U8
+LEjwTv/XByTgNAyb7PKiwixxFoA7jWjslLSY1w2hhnLE4pBLpb9IYAY4bEDNKbbDFFSH0qU3GTt
bQh6TlOyyGxKTAnDnw+vclF4peFLbTmry1pZLVtn+okznV2RvwVBLza8+h1ISLNw1Pkj4qpp1cCA
N5u+53tqAc2kdaNfPXzRguMI71UDMAoBX2dJHc9BujqQPhb31nu/8L+GbeXkj5pNraYO8x+q9wNC
6SGuQ6+JP/QlMCVVRPbl3NQ01S9agqYOP60ws/V8dEIqYRDmaobyxA782ts+wJ/4eA+D6ADIWm2N
SeG58t5RiZubDk8AqDoXLUPrSnLIwQT7bNATJkrn3KOQ+FBM7OhCs6UbUVmDYtjApNCM0T+FWvx/
dknCxMOj/39PY+hhgSqRsr6Ak0Uy8vARua96VI0TAFpmbm6zvRvI9knO150la9RTuZvz4dU7YcsQ
6zhthtN0DQjaodQHLw+wLpjZw1M7uOiQEBBwV/r3E9qvRyPDwXAL3SdYfQclGnn0GXNrZvAhEp8i
/hjJyzrYvgyDyhruCI4oLiMk8edtU+pUej3uWIiFTPSCfZfuExw74PmVlOm5RUT/1ILujdtQ1kMm
r62YIyUZdBUK8iwb/O6aGo/VPE+BSg0kEr1/0lptahDwuRuYPiyS2N84xSRYYhgBkS3OasRxWZg6
Z9n6GS+fQZFCkK2icDFzIQndMm4gz5f9q7sl3+8SBIrZS4xzFJu71S413Gq4qQcOGeMaDxujUVDY
H6v7SA4nKZ+MRKBoGgYOwEVfTPSo91qpDKBjWxz7hBGQnGvE39CY7ww9Kn2rEi3NgmNczV5UNdKZ
HWN3ZlBl/IknxoBjHs3qPfYC53mR78QOgImVZak1IupgFsNEPSBKLvZtp5w5TIAhs/UCPtG0WmlJ
dUd/U60RBTVWosIAuJsmpTE5vrFxKB4Rv5GfWjk0xL5p2EwqVB718Ti0XEuVR28Yv8+sxSswbDje
Sz6NtfgfnsBIodX75fNNHraYEmRNor0dfGGMAl/UaLdy5ktbQd//Tak8DftrvFP1PdJ4NXpPg6ad
Ch4RdJQ8dYwPCGY/h9cjx9aK0D2OEESND4Hen7w+EC0LuPHFwy6EBxzSuqhcPZRzuBPy5jJ/FXid
9n1oxUqfbKsc4RlXy4RyhwhjJcCWbcRaBD2V1csyfSO8BMjfzUV142u3QIMY/IXx36ZYrBwuw12e
x1+gUy/mqdn8rDJPaX5hkvrzXHLWgVo54THWG6/Spebao4iwIizqiLhO9YR8qpCsVp8XQ9xgQd/z
h9argOxMLRle4851DhC8ekFjaDdjUuZmW3ea3H+DQyWDSSOnrBk0lm0GoTX4aeI3LzHEJ7xAq0qE
r92o04i0OxLD0yfh0bO81kMXVM/xd5oXb64AwWFV9WjUq/MV4ZGYBH4HYc/BonjNSgi0rLBBvutY
5K7JtVRH4UArwk9Ev6ZK9BlnvfftDZcOZqNEaig0ZWwNV7qlUGAbCcS+XLJZJIyZ6H1VNjcAyihS
PQfZtuHL86ALQ0xOQZbWZUHF+b+vWWlRQnyJFpoHiJrOnDM3sYcPF1kiVy46J6P13kkqkGfXPB71
zB1Du6QamjM5RdfMe9r0tvtSAzgApA7R7Jd3fg7BKQ60guO9sbIQHh45Lsh18b3DznO7IkNhTqLo
UzZlGLuMheNgO/RsdULEYvpKAzVXkm7J5IjISsiBsA2aRpl+EelOI1UE68CnzJzLZ9P8uaSHTVEC
JF/CiDU5TL2kBMahLS+iBeJ76kBd6z/J3vsYhoa8WUTRlbp7UWduumM91R1B4zBwWnDII2TU3iF5
EXGwZMLqCylT9O60F0MYh8wPYZLhZiLoMC/OhZz3QT5jC36Y56VBB2eCKH1iWY3J/kn85ogyxuEZ
Cny0SbmG7QYCFE/bchI/BKqXmNr1RFGaUD1Rmv93sLu+EEAZzF2MM+4WgDQxIEd4omJzsKFufTRu
/Gvmi/MnSJq44cw5Cg2W2ToIB/7NeErcBuVe8SBkVZb3TO0hHoUD4a4k7bdwuTfyFfJ8X92qqqX4
Qn+MWp78c4V3r36FKMbCrWWgFz1g0FisfJujLbAbqLfP1UQgYllcMMIAgBt7RMGBIlQjiO1nWAQr
+C7edhlPKnUJMdrT5RG02j8+rFKKEloxEA7Z/4s7NXVul2l/b+EI/KyNUSpVRAOF/Je5yWZTY60L
YEg12lmThMo/mlKbPuFmyCfYh1GKdor1IC1tm9nNlrFcfzPJl6L19jar4l4noRy7dkQHEipmhQHb
oTx81tjPCGZqMnUJeYNuzG6RAxnF3+CJ+jEbnh0twBo4SibMHlw8LsPucu6HwXYIlwAYnv/YVvJP
nSNyCBq5T6UT65Huy0Np5V9oL6Gg/iuuqdWv9SxDa+GqAnQVVaw/I/abJfo7tGTEyTrlvS8EGHkh
0dT1HQJpF87JrEO7L8Rq+wtaLP2PVonR4KU1cGxfmkC+Cb8QdXHXrKemep9VejZ4gIvK4tKC+z3E
rvCDC5uP2QhRC2+swOhDuXMAMWYviJP5Y9aid7EoKG68mu0hbmxJdUqY+JhxLPKt4DQOK414xrnH
vqnLOU1aSP86m3/EGdNi6hsjg4RiP8Pc4Pl9rpwi7gVc5Jrv53CAIvh0MW/PO8jTuqLlndx4Ga9w
BMocuP9D0C77isVKA4RG9Ztn4obkGUBlibBAMigP02StFUw/4u0YxDrqyIGMoiO6p3OmfUnZBkKz
XUoPuI+SeyTvuWZ7K8X6J8NXGFdqjvbdkpN76P/DZxd9U/CIVUhQJewrwgugepBzXNEhUEULpnAd
OW/YeFz4uO2J83c/5kJyVNFKjCRD9byBtqlgQ6Bi+AOB6xYL5H1PktQJoE3hfZG8CRHfyGJF6+hR
UmpmDkVW3fslnRLeaW3Y+dfxxg77HxQxEZGeceWGUSAsn0c3kJJL9Wj0DpIF759goYel2Mu5PFqs
duQPo7MrZpitM1cYpOxtnSIUSyEFd5Jp6zpMqdijsaOQoAZVJ0wVGCAys4dxpySp9k+mnisHZiNt
VIDRl0ieBFpWDn/ZxuylFbT+B4hnVJ7Z1tzSXHOyrYJjUWLgFy7eT0UfZgL7Odoj4Y5q+DteiN8G
mvz0+mO2zJkvW2hlontPhH70OZMb63blB18MVTg8iU97z9Zmsay+vdZ6SH9Zcor269eaPQNlGOHr
X00bcntX3GbjnWF6VkBoIvabW6x2ILuDwmAp1CX6h4GYY2z9H2MNe15EuBLn0VZBBJpMmGkMF0fJ
1i/7NVnkCKwVFgqT4eikY+io5NWMokxe6+NThVk/EJUZDpmPyYRjc1xNXGt+BqqTrZLnvAuborPF
4KmEo0Gra3uxHq14AIB0l0WsadUmg3Tf3Rbi3kmhB8msJy3pWACvcvyPv9v2YG1zUMxI/fL1q/uU
fcUEEp7+MAaJB8p/hTtNkRmmQjg85uNChVQ1imDzyRq8w8mp1Ke5TKoa2k8S6KyFMfRFtACOXp9Y
OG+ejDu2ycSQe1wHNDmS3m4CvrZTYb/ivxGsqCvqVb8OxUcp/780nvJy/KAVFQ1NLbuJj5ne0OGO
BX9f3UQVzjCyuu8aCE6r4Jd3gbs3gnly0irwGOZXSFrXfVJFBuNkOaW8T2h2kf/UoNg2fMaSTBUR
mWhPwJh/hojDh21Yy6vqwlcv5xhbHEkJnFDge5Twgi66IBmNFxVt51tRQNkYCdOIFcCFwrBcKhz0
0cvYjnp6d0gzVN9LR55M+INHPQfXroNNEvPNw4xJPn1vn889k6TOSP+XhcQ2f6QNhVi1JxrjA1Hd
gqe5fDTeUMgmrWVnPETuuWzrlT1L8XONiB3+YgH+x1x3sLz6ivvtKgdO9Os2f6/nYgIN4LH/Nvtj
139xeWAPQu1txhhe8R4JHeuGebV7zlMAAIda9JAUceq94crzyOkds6X83tGovmY5FJiZ7h9uq9yT
LMTVcbxxb5Jvnn8btyfX5sFHp5vl/UpT4fvAmc687nbBnUZn7CJjzEbGi3yLdPkN0kACveWeGQUq
2iH4ubfH1SFLmQSFFz5/sPlkA+pa3VqBLEfSbPlOvF/SlwxjnWPDSrZp9F3aNfBYkbzaJHD4zun8
2g1rhwslT8GCQr7xo/dukSuH6J9eQFp2E2YGfHJvXj+lR7CU9PX+uvm+2jocpftUzzF0rK8UndGh
GD8Vi290fLsCgBZSFmNxq43Njum7RKsXqpXMTsQC0QO8TUdHpQF7mDTw7Amv8RO4kutWwmGjiBqx
LsRaL7+hNHixTBta8kNro2VO50iJD0jizX0TA62mdt7o8kGwHW7RecXIgA2wngJC5R4kxnHnEWDz
MjcTlfgoMr1ZNecwn5CvObQ/Yq83IN8CmDJQgLWlRyEgkIci4MUTTAVLqze9ikCS1DVmXIGPjR3y
ZkKYSE6h/cJc0lNbiDOYoBZ01aiY8KaRWp3sRczazvmMF0EEw+vBYhB2gt3mZhqM58bpuEPpFgYJ
nVOV9mp8u1I4V7TVplLZNw159/vUTLtJgnLDdEvxpnu5GHKCNrZULsXJycuJyzJx9tCYKwpNL9KA
4XyhU8hnnsDG2HiXC82QwLa9M+7HWXrTuUNYaiWik1Ame1a0G67k1JpyM2kd+i4/EK/9KvV8HWAy
KIt7mDtZiwYuIG2RyX6Tb00RpcuhizO5wh5v1aBuhyypJcFPDQLlL9m1d7s4v1gRw2iodCif1pvr
zXGdrjnOsD454zU6neM/YynRLKV5qG8MMX3fbm8nQXM8GqgiRcMuoFDLPq7lHmGqmKNFjhnI07x2
HtSSqhM8rde9l0kwoyex0l1nP+0Tw9BQ3UOl36cAO/7wlPgizyNEfqN//ZnLktvyyDfVbSAiJdtB
53iSTz9mJeEAYCVfQfzGix57/BzhNqguhhtKUcv0XZ4tJpa34zsXmEVwNGABNtf4n2j6b+XaG2wG
m1T/qmaUH1+vGgJ2BWGypLGw9+nIjbioDb+pTKrGwEErARavXFga4FxwDIidvuyvxQeekZQP9JaW
TJMj33AcguiXd9KZeUdoUKL2B6amg3h1zFUnPF7i3IL7bYvFnDsNy7s/w8YQvObfpZomms89c06A
uQ6XbVmEP7DakkeZnhb+yi7bmMe3K1RJtf1hmXS+bem/Qf3zfa010pMZOYwS5nLO+H/bTJpPJIh9
aJbGwledxTOJAGbMk9Tq0Bu1optAH67G5xsfhC8JFfxMzVcrWmR1+lScit1TVj4HdtJZKsMeaHyr
9Uq/EpJG85uDMiNyvd697NDbHvZtb8NbDAkyS5zM8c3jHwIYVDZHx3tVCpXZCh1WcXRFQFB4Ikc4
zJ7wpi3SdlzTUN8uyVqbUW3WlNPiAKAWdRvuFCqZN9yLolQbL1T5Qz4x6L+GYYte0O9GKtQ+3OXU
8T1y771CaoSSA1qB+EaQ4BrSB8iu49r6gIWwBh6EXELQG1mpYmlzsB7l2tnkHGDMq/cNX5LZIomv
Lg8P6lPT6cGw0Aa394wDV2PaIcPgvWXoegskJmoWliGvl9NVF0WnkY2mavC/10l9LnBC9jxKqp+X
9UfobTpqEbTMwo4oiZ+QkW6g/muxR+8nJOfETk5v2x5V0dCJHFZF+tFOtYks7/9EDDP4e5ivh84L
KKB03x2a+WV0D+ULD3PDL8Sjv4Ovdgh04D6zW/iD0nxkZNuu2vRFzZmY7yhEJVQijC9iNSSuiQQZ
mxmz5yBhcPCiPcKh+R/iDoey7CZw7GHtd81UxJjjlQ3tuwoMSEPRI5JnXjuZqo0GHBmMKCzHPtrK
KBuL+skZS3GMno4EIH7kAq300N5SfQj3TpKPckAd5EzC0t+5+MdCbpE5AlXsGxYj3v5HW/ecu6Pg
2CJvM5yxSjPH3Z/J7sag4NDrCT5/dXYZn1Uld54ea9lWKs4xxJuX82k3FOn7whTnDyeY2ERLRVWS
wE9E7jHWLXCgv6aVtM8REWrOaF9GBiytIVqsQg5odvKIGriSj2OXvX6UYtYwv11jgRye85qNVAq1
CkFZOkzRy61FGl9SiewnpPoyCD+EbpvJCfGWW+JGo/g6PTElAKA7poot6xCQabUtDPe1IscMhO0E
rGlZ2ifudtv1q81I5KRPcvlisMwUSfZx0sZOQ1x3xF/uxtvN26dKIhFY5E0p6X//iRXgXiSTD8+5
fj1Id3W5c6kyabNz5t0JoJ70M0zgaGz1khqsGzfo/JiI7G5jujKlrfWJCQGzyroQcW/eidhTPBx3
i9ST+7D1JlyTbyX1dLeqCs0aHu/T1JPT9CTrgM9Rg0GMqx9BuDr0b1BJGXOzhMLj2aRVLWLdy4Vl
+pU/sPQoyemJCLAB2gokPWIVIQWF9Zji6DBdpiDkNVZspwyuoRUSfLp/l8NLKfe4GD+xdx11Hvwm
sOupTXxyPTNOEoGGs2h7BFj7rQ9Ca+0tLM26IqSetolR2SoDR7/nz/wVAd3Z+fFdT1mAQmTQH37E
rurjR2ceR478lD8nVO5w529D7O1kQQdrnsUuJB/75cjq+yNAN7qnR8+rJRhR5imICWzvKPDGrCOw
EDfN7QQpz1deqLsVea4S5C0xhVq2o9VaU/3J3kOZPaehnIrl3TdomFdVJfriCobQoGoM52d6Yy8A
ZhSOrp7hoAulnuBf0L9H9Wi6F5DxSnbUFmZU2OAyd/8cmRz11fJJYJzFJKBt5vMoACp3HMU7PXwU
OAtXsdaazzzjuqdQvqyB4qvBl4UZsYdiyzF+xdIHmUWtzsQsEU1VymvANQTLU7S+oQ6P1aDP/bwe
DtKLL4RuHWRRHA63gc1glo5q0rfT4pLOsqWFtMfY/Lbvh4Hz8so0u/flIhg+gfma4jv4EPWuIZt5
MYU5LFeGpSa/s2S1QjgLZijv5LnTgpRNOVMV0kYq1HlQMfYDyXcVzy1zyREgbOaxLY+E7lxdGCm4
c7PDwN4bFxHmV7HnI0cnlfCO9pCLaE+SntovN3oT26HuVDa6YMKv/gW2+kSOWryvXVYhlFEcwXfB
JMIPRmT4WiJ+QtAyt5Pm5Wzari6CvBHhH8TavjyilqG90ekpP5/QAIeHSibwcppAde3sFRDWV7FC
A/wQVpT2Wbp4/AxZfAngDC08Op7TxierG2hjRrlwjryhLqNvQb17bGB1Kn6tf/xz
/Qc=
`protect end_protected
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/dmem.vhd
|
9
|
12163
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
An6KsaiYrulwxqqCTyrSzzHcxhHI84q3UlaJ2ztMp0Y91rLK0dC0j2isQ24fiJZ0WhzYiZrCc0eG
Whj66v/AMA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
PUXNoMyJk/CLuUZRXW6yA9w/aCvSD4KS0m+rQqTC9OMFAlMWa21jzZ1fElvoVCAArSjuCdB7ZUz6
VMCtVTWHmFRjDLUo6rJ56jZUnw7f+LD41SvmGWJAmWaSVCc030C9+ThQIs70xbnGcVnwZLoBcA6M
p0jFfCvKHFeZTpbjvgs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UUAaUpoxmLITpPzkE5LmCRGKvZ0+JBe+f5cb87Lcc1AZMOyA9lnrCCHuEefru5gs9XsGILXZhTC5
nizT/MXh7Xtgf759AFdAyzC/KFttobnssXP1vjnVvnKS6dvQcRlbbZ0hxZ/8hvlhD7Heuoc71w2R
kAxAKqVsKgxbbnTW+du2JF9Isee91EVej9zj1NYhuytNxf51EcF8VB+dssd2hcKYL0r+K2iEWqiq
fGBVxPr2IUxXkoYk21Ucs5MaZvN4jYsVQWUUi4yOGBlVJng1LIj57/NE4WXUVAs7ni7c4N6d77xf
/WNH+naxugwBnBiYVNJiEulZP9UdK0BsbbC+iA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IDLw/3tQFeSorgOJ91Bg4RMVGmlWTvk0dAJHaR5H7TD+L+abFlQ0WuArltEBRxeeJodt8YWLRbva
iMEf0MsflEGPr5xCr5v/0Nay8R88AcSroabyDH8N64M6yCye00ulFfXR6VOLurDD4nMFaphpVQ4p
9PqRf7HD33FJIZQ7ht4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BKKj9+Qx1I58JoS/BxXZl3fLldE3jrRrg27/9nODwp2GR5QXBRqyf/M2GPdsdjaeSMgu3PZ2OLmk
Lgpy2auLvHfkObs8OTBaAq8VTOkQuwpgC1g1zqhmVhdrMhULidVsvRutaeJCPd7CVpbpinOGfZx7
Qq6oaXwoy8k+cIpF6j11fSv1QUNZwTOTdzA2XEkn8BvUk6QVAVwhphnjcstaGz9CTjE+jZucUJ/H
iB7SfmdU8UjkGADqgjuMwvnAEvm079pBQas2pHe0Uz3n6aFAJpOBNt/SxBuyAQ0Ed+lfHWkW+6fD
6BWjeBWVOJ4QxIPklP2REpr3cw2PlK+Rhx9K6g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7264)
`protect data_block
WItqXlGLK1AKIAkC1GWUemBa8MA5gVsWdbfZszt5iFpCwkzjHSx5TR0fVa7KX9W29D8dfsoYVEgy
4now8JQ/sqHKpvvD5GpAjbh9VT0jbQDnXryvCoy/PnngtZgutaPz+QjeBu8yHyeyjMVJ7+YVAWqN
WB+m/h2gGRbhtSoiH9fVzRucinXSwKXLfx6p7wQ9z5rjh8yhzrBB5Cryia7Z2FjfDaiPLd9Thjyy
XKq+p12w7V0qlpcjSFTcbv1TXVweA0A5co9ituz5Qi+167JfZYDAPsxHmLKlMZ498e1SORI//wPh
Aw2jnnS5YlP1l1zk59ac5hPxplZq/giM2nKr7ZlZKYRUpm6DqXXNJPsmMJKL9NOnJxYVF77WvGOB
IKLuRCKGdlaXKv7g+ljqZUfS12skmx0kpGXINJsTIqjJ5gY/HvNkxm8u30fTR58QXhfbvDT3uK9o
RI9w9tfoJ9jXQCXmXs0eNpYoCHFaSQdUUAuPtpjHa65vgPY+3U9tLxskLjwKX8QxnOKpRtfQE8TU
Kgrcnuk8HOVlHhiUnbVlLtdnc2s30tIL/+t2yoykazI3aFnBeJcNGAtTIhkxRy5dUijmXZGKfuSe
gMEhzHuDWh6BorryaDsMnz/CRogPDbEXTmGg6gqpBWjhkhYO2tnGihR52NlEHQed2ESE3BGsgXcQ
g1mgtWPpwka4lmrqDjse7aH8lVaAr3+LabXyl4l1akZ6cogmAN5neINO7xRv0T0YZwc88gezxZmo
CkM0XzhXW5/r7hsGp42G3xcdPUy/+EP3tWeo+8S9HOO4XPysgMKsEiou3+HqUfpbvzzUVoso8wXU
BQPRNCUUrDio+GhpqGMxRXgDlYF2RnciLHrGs5le30nbhExX9tiaZvp0xUBrBaFmbzwiFQGYCuKy
Wray9t0aGxvcgfYZGhbDXRrSXHQju0aUnsRuY03LiRrbKAQa73Of2BqH8rGyql3xsM06z9lYtO9C
y15qqEzOpjiPekIy2PFjO0cEElN0wEa0LE+XFIm+IfmlMLFuTPErZYsofsdfBI/GQ8qna9mt6bxF
y/wUougQwmP2xZu2o44VUgaYWDg2NcpZoRKy5K+nI8iyVEajmdmBX5eNbh06d3NqqLdTWf7YWlLT
ZVEvvGwgzQgU+tkUe6OsrG/hrgzSc2Yw24Sw4WZyOFcO4w1rL3OrXR3ERy5wGC6ZtUSVKkJEx8j3
sfAOWkdzGNtsZjP1gzmLiKt0RNBLIKVslcgYkV8N4+RNv0GeXsyCxLdbrcrLMa6c0lLnfLlVTKJk
H+dfw/rRZQNJ6l64UnQ1odJDIqE3DYn4uxuXEoEL5m1Qmi/tt+0w6hzNSFch/cK+IjtdHgLFSrCk
2gRDTdz9EIUGSKUrbMn/p/8fabYY/ZLRUtpMiigd2xrSZVWS608AZTAoyG3KAy0ruK24Y2TJLuW6
j1WbanySmAMwWN8tCD/92sQC6CeDjoRSM7U8MI+igah+kupHkB99wN/bHsVUsl9Tk3AaTh3rDTyp
eokhGH1Dkthqo7QkxALO9TxjO6M83A/+SLqu8lS9c+Jw8EnJsxwXffZuJ1A107l5YECCvjkzy/8x
m/D6FuTiIjDCbnlsWXT7zoEM1T44PAFdBat+3ibjEjpScUwmjFsQw1nmXGztnhyQ7hLl36mX+tKc
91/5toHMWYuQBQ/WdP0gp+Ex5bVH12EyqgaD4RztP8ZiRmdqR/QuUtr9Dq68TXPxCdj1DUa51iwv
henfkb/PmqGn6le4pMPbWtynI/yD9Wjm9pvfXlcVV2t/nqocbmCLG7zxCnUxfiqmOgZrG+2pxWKN
NHRSjMu9WdF0ZbSz2E8obUZZPnVCBd7H6mm6igTMsRqeyU85s9/AIva6oNSKJn/SaPHjFErgg2hN
zLRE8nvp3brkFDIQCgQO7bDmISGWAcXY4v/7aqej31Xg1GTnMmOexU04GkgHfDVHmd9qGpuS9VVF
yEAoQew77KR7YItxapxLfiWBrZBRRuLVb0CLlwdxu+rOw45Vb2uLoEbZXjdt+3zPRnhM1cNWPP9e
zxed44PrVq2FB1Uflu3UeQp6QTCsTXbcus+iSoc6XHJtz3xG5fnBDQu9lE01a1RM6A6V9o4McaSS
+lZzztFSRHEDj45i7+PvvQ6FBv52ixFl0frlUyU+fgmlOh/Qwly4SqGpoPsnKrbw5YggFugOz9zi
d38OkeC92LSYV+ONH0IK/Vpo6HQpDsBJcvgyj1A2dVEJi4N41dczw3rhdv2688qjBc7N/jL3aIHQ
2EpEul+Yh2gqREutmQxW5IW8jiSl3a/L8fEAveElNWPFpjNIUtiNt/IquW/vgRAhIT4tqR0lbm5U
kpeQWuURD3YfYkwyPGw73c6m4TcRHbdC0/WjV2Bj+XIoqVzUUNM1kwg8eqTznvU8PKI/0rIrQATC
lpYDOdnAf+w3I5/zD6Nx8vLVb6O4Lc6LMYvj2QlQeK/OpnQ/BRi63ZjfEvC5DOnSssvyt5b4X+NA
3HQTVAz7KICd7VGqz17jVkVujHXu/T6RjQg3tVUMtuiaVfxTm05SQG9O8gHGUGPgqLXcqBZ3M3m2
d0zNkRvUVdkwVYb3lpAHStObXjCwRC7/WCveoL/fqSCcMrkBJOOq8I5YDt79dZMcSMbV36YTMsLM
ZDF+MP3dEbLTuoEkHJMA/yuLyl6jumMX3d7Lde9lMbyc8KENu4g2xkk1XxuMFp+mY2XC7a/a+j4J
UidoHNUOXOrMwhakdOPfPm6x5A7vTgGxulpzKnGbS/3hsy//5AioLdAPshytLkdbD7LT/r8V8aMi
RUdb1u0huo+jSiZlXvlq8patE2i3OBq5ZtZKEmjhSo4dod9edcPKH9Hw/oqw4RAeg4x/Aux6BqEi
JWB4Z3SoYrTZcGYFMq1VhTSV0zIswSJ0uPdB/VGNym6dsBjyS3hNZV96ZZH9CcFGJsRP2Ye4l0Fg
90xmpRKMJOmdsZKqvoGaT0jsSO96KQBv8aE3r8oWx9w8w3UDjEevxw8b4gPFcJEkcXy2eYDqQ/jp
KSSEWIsTqTkFpQBXj2wf6kGlDyJJ2oCSkBBA+AaYhqtXxDp3aVyJVxj5eZrFlGfyQ++dPnbcOUmm
EYk7e6NZlENtuBhF0iTqzDtuZdCxLW1XFY5iMlpUWEsrwzB1SSxMMBuyUsBw8Q34ozgZQk90mbYY
kcjo/1w22S5+NA0g1mtJS5vWIbHu0GOkIPmlPwuUZyXhh+O5ai1LL4aQeWv3rS/kQbTQpRMJjmxR
+q4mqoNhRr3ohDVg8ScZL5C7VNR86m4Gwdf5LVz/neBuiQxF9fh959gnIowDvxK8klG3m1425nPT
DiH3SXSK/bLhjSoXwROohmfklFXI0FC7Ew0EUnND6FLKLs4UYL++/MosVSHf8KZZpv06wjh3M3cn
qZcQ4AwElLpskdn+raPs5cvXkcDIq+fGoS9CzOorv/aJ1SKaIoz4gF1NC2sXhHgz8sCi10c2VKu1
WCdettVuuRy28/W8JSNVzqzv7L0uiAkcP7k6vzsvUQEGPgdJTG5RsL3spiEOsRAkvYLs58gsvDnp
IzvAfCrSBhVZ+IF41hcmeoBp6rrmzYyimxd+N2sM9u8R3ovEsAJl1B4KD2Pato+VSNjIt2AP5kIl
6Fyf41kmYDgh68d7ElvmqOb75u4AgzXHztFt2Ke2pS8RJFk3WguvDiY8BAjZKqdLqv0D4nOMqRFP
csK8WX9LfjFBOufh6RR16iWWd80fOdoIoUs3xYI5a+rqV29p7FvjdDr20rhxzMPLYBqI3F3NP3Bx
NtHiBiDaOpi5z5AE2Q1lS12MZgGT7pMZ3njlxOaJuuoqasvYlUtvaNY5rOlSiV8LkZhq547Ob32P
9z/zFXVzcYacwvHQSYwrJiLNAmRBH84fd0fP6INS3hvR1pC9MXX49f3CC6KbLnErnmNv+I9Xyk/k
yHk9C5VaFija+G4RHdg9r3b7LPlbyMsjYMWPYn3tSjbVkV59hSxUcZn2GNE3IArGDB+uHLghFAXf
+1UPXRjSPfzYJUZ/baGYT20eG2LCuiMmt5BDG3wTaaipXlrKXtQUfi6sdpL7bFDn0efiwDJEZERn
9RjHqO1T12AMD7A9sIJr+dmNzHq4PNGvlNwM7EBg/K/wRW5iFV0+/igZDFV+WM8PqZ8WwjdZBqvQ
SzKQdGq/BZUS4WA0rr2Ejan7U6JlWzcUYH3W717ssYpWo7gR0WI6SJ2EsZWEtad3GJQdwZZDdxEv
qFNpp45NRhjlQM24vtFPOqQvEzBJWg3DxeBBprGRj/qOmqmTmoZ7UQjYzyqaCctUrdBGbcNyi2V2
ZZmuJrG8gVXxlRojIQoQmZrq3ornNky6hqXZeUb/moinKpQmLKiwafEoBK16ZREUfwGhWA1HUgNP
vVJvpiBr+M0l9lZ3u6mINF4EeG1BOZH63rxe2rq2z53y1GYaz/34LvUlSEe2pJySvVwPDk70HQKJ
nq1R+nENj7NBsVL7T3znXIffdwuNk2cesVDL/Bba9XVqZGquctIgwI36UPJfKxOZVbt3Tdmz7xDa
M/j2Vcozac3Z8C5FrvSwuDBbO7hvD2+xL2YpdFZgAGPbzSKLRRcfyeGlxsT/xGkbngxDN73aTDEK
DGTqyVrVWSknS0IMSfTflBg/YWD8g68c64m8Oa1xf1SjGFT3JtGWYMVRLsKNzQXNcXALWiJESAv6
NY9tM2DmpGmfhkqYMAO7dQi7otlDbaUXBDZuvBvOHWFg7+Q2zhxP1GBT1FJiDYIIY+0DLW9cNvHG
SgfB08zc2AoiTACiK2PeSoQzFwjdcZUsl3R/ljdnOJySww9/WmLCQ3NtVsizA5K7tf0YgCghpXiZ
pHiLVkolzqRdaZQt0KwPPZp4Ix7g8JAKYcsOeZuRZmYmCybACO69qkD/sDDRrH+ZzagUU3yQqMVh
5cLFQNA8GnFjPxrjQujku39zrPWOeOSOsgkqkW5aVsmz7B0A1H2A4RUB/DHhJZz0uJIMJcAjpFfW
nnlU/dSBFhgaI5j+9e5zIVhCZ6zoz7I3wcggp1+Zx0hRd/0c7/KU03Ld1J2Oz+zB8EHiu2SGW4wY
1UUI9Jj4iZxDdcu9s0WE8aaeVH9kd1w+wfB4hy16wbq1lau+LbTUgUqWYX1PjMEd6aLaTyZKq60U
IB7CovdSePv1bD/rTPQGKgmApaXnpRo7jKOwiJidrfEoJ3V/sxoe9R7OmWKLl3beLk+V/r/0VR+J
icv7EnDASh4f1UBrk8EnWo6AJeffXge8iaYZ+MVVyfF9uPNY99UOEnmDaXTc0g5mEw2MI9ziQgdX
4Brdx1RVUm9HaYmdNMjmUlLjK/8ktKNwEWA0Mik5BBx+VMg+u1YszTFwTzPonFZll0KCrFgsCLWR
VERBCUN2itGNZQl1p/q61rvIdeUHIKfQfWgNV4fHUDv/lSAyd2ToJQ4HyaAFH9H/A4np2+/Qp2lB
XVMWXfP54fAJCNuHU/WTVIVqUsWldhRABx0GKMWc9Y7uq3rcm47KGvnRgY67KfYw7tjrZmKOfYL9
7IO00nbhmoyOZXvxG10W1Hd4coLWG7MydiSJoZFUpU/SvuoRaOLU4JB+qQh9ahNuzrpZtpKuR0N/
ZDdlkPHdNB/n7ca2ujjrox7aQEv1qdEM3t4+zAY9fzAfx1v+srYx92zGZsEX44E+iYstGIms5Hzw
I0yGzajv6BD/SxtzsuVd/qkpRaVi0okmGPKvYx2T4GLkp8x+h0PoDcyVq4cynl3mfNcybThLBikO
Ju8w3Nnk9aS73H7DjEXZmp9uIAzA7AtfmMm9HksGpMSOFNk3tLOpwXO5me1lYUCwJkNJfG+gCs3D
IXDma+Xv4L1TbXuf0XXGGbsFrCeFXo6kLS/Q0iUQSTKVpc9sqyZPVkIVqv5M/psZ+p3WEXtRyzun
3pN6GNvgKH8FnL4Vbu4O0dA86cWV5yRiVwvs0ca95z1lFsWfu+aPSFlxFCy+DyeY0BuZXZS7fvrB
PynYsAKLRNzDLFYSJ9TQoyaod0Ywyns5m4GjeHvUOK2Wxh1hz7/FXgGnSi/8dgynGt+9CR0pfCyk
jOBcWkGeLOUhTHC+NdgdwU93C5FIflyiZljieHGfIzWfi5DspQHVZ5PMqk3GlcImy4zy8WMEvOpC
1m5Q/nm8cPGqk7ksrhdrCZ2zKyHhWAx+veRCx6GDEWyYFopb5bVbCGYyiySpYB7O2t983d+52EfN
pb/w7x5c6zvsaUtysMPk9GOSibQ9iWhMvus4AF0JnEHYRljGwObTu7Fy1dugaLFH2+zlMFttjZjP
DfMCqh3RdYL0M3SCbxNXqra4oXH9Q1tMULsOPyvB74JTcByK85OPn3Q6CsylGJO0OKxGrhCPepZr
9L181Y1ly5OPMGIQPcuBD2feNdyQr2ibpnu6b1bQ3HuUBCY8F0H7WuEv9w3XgSlHihnpq6QBBza6
cT9LJKXB1EZZ/kEQj9cmCl+PeZ8e09giX0tJQ9MObvocH4OBCEJqG4lBqQJpTsxsWF1IilDAi4qW
pe7qF24orH3+ZcpAXYkZewg+OKqTpzSoBu6YGovioOuAHXH8IU+eHZXVxZTP81G1f543P09nvOlZ
+elHnZqQtjP7FMIX6JWl2Xo0G/14p+5xZMbdkt/Kvg6Jh4aBjAZCNiJzoLctLvSP845oIOPcIV1S
aEegHtHk6hZ78J3EjJdHHQCeXK7v94sar4Iol2TJ2IQdqe2tapvYv+PwpWLYdazGEDrjHtM4oCuc
sB0un6XSJSXAlwn92lc/M6t8SbBBA448s5OPuYt1L7AAZoRxat0kdih7HOVtpD6rEvelpBAHOCpM
XS+bAlDATSZed7GQc7ywIP8nBleWssJF4snuWFfU7CNtkeUQz5XZRvKSWH0E5ZJ1dPJ6gLTXvBX2
MCHh7gYWlVUN5pb30TRxMoET2f9rmERpoKiJvBcbVsH4Dq0jkSqtAjmgGpHLtYH3qh/fXdZLFbPf
f0djH8xGhUjbGqksRctJ8zkCYBwzu4DfLD1qly9AtV1BYVyB2SjFuDkYcjOzqHy9TsGeQOV00b6y
33okU+W4L2nwtP799NPl5/FgT2ii0ZoYuxMvzOfZ2vbIYHnP08zi4PeDxXpI1FXQjkddRliObxW8
eVcjoKXZwF25JN35q7nPgP6GIYR390aCZDyS4R7UPIwbCBqUbaxk57Q4dfuVq7z9qeyhFnRLDDLx
ytF28Gd6UE3Er+fle4mP8dldnApFzpiOCWTv04C+Td9ZUO7lEoYuRqpl9xDB3k2p0jGYKDL9PeVe
uUL3MYtROvIBwfbul/HLsLSRhCX2g8Z6Kn2NawzCTopSdi2KDiGt1mWpyuIwkacDC93ngYPc0cfj
b+2CKAAerQw/lsZO7YSO2un8Lw7qR9mE88lY+7wZFfrPYjSZIDUe/RUVmHgUEU4qpsipTyd872P3
XEOYpO1oHbckWYP+mS9YGUwmwJN4zIQBjVUj8yDPyJ7pzyUB+SSvFbQxfNQCbWK+8l8X6lnmPCkp
IY9FZdXZUXf+WDG7ypRM4QjE2Ab83JmIfdBqi+yo26QLL5DoGOttmt6ZyNPpu2oEygvyNPTcC4IL
CzuBlsjstYyFAXrKbCBB9bF5/Pd+l+cag5tSLJumP4IgX2x7FYOtLilyZ6e/I0xC/mEXeim7JCFi
eoIZW6lY7h5O1Mrk5LMbqcZ4ugOVLIIxpo1YttD0A4FScz3oLpx7bkJKpPeYAq8SqL4mGcinhylZ
bv5EC16fRicGin9RWYyD6RBSNKyEPVl8q0Zh7Dd5PHB98T8oYOBfOxXCpniOPKNgUbW2Wd5+JEip
+K80GYknsfIbazerLZQ5i41hhPRI9/5LiyAflctZJmEiAxPrN7yGP4yL//VZu2eTm/dM/RZhGhTL
L2UKPO6ZSvrPQg94ekewaWyluFDJ7T/dbx+2VzSAb7lUKEBm6UzaLF+UzdI22mqjgLbKByib4c0p
IahTG5/jSKeaoBclTx1Y99RhhnyQ4JNjyDZUghFt3oWmKRstgHOOfhIH2nGJKDwleeBZd2jotc+N
fLNL8/Gsxn+sVAOxWFS7kESp3lEQe5LCBf/miQ3zJ7MtsqPbkyhtWd1saCsu+hVPHbjlK0bEhbeT
x9V6gOKMvphMPKD6NZaZms4/vmElF7ZsLLF98BKCrNE+JgBMRqjIq8pMyJZ2hAoIsdPorIwgc16g
H2fs7V2TsWM8qeNj1ER05LMkhoatPWpylbjKX47KZL1dAxqJuFawoeT6hh0/s4oakaWPqnCG5BWO
glcJwrgyedR+ekGJohMmuAOBJx3CY0zdvG5kiX7F7n13OZHJDGwNBWbDVnMkjT9bCbcbAli0yafJ
ESBkhoGDtvWVWVuK6K7tC978XhJSM2CnwxnKt62apmb7MgngdqZ25yT+79t+fe0az5M6LXWf7Fl7
gA5TXXgBilDCC2WYqikvs4jPFGSjp2LlWSlIlcOZoGaIHpQVY0X4uvgxpC9JSe869i8UQ0ibhU/t
qD7o1/g2Ss1XKgAz+hlsizsvbtxvk3l8SGviiNwb2b8qKX6fCnXYMh0D1iB/DJnkCE8MAd38nflm
Snvc0kjiSInoZK/H2ZNUJwLduNd0ba5CifsQy+GuInZp9WakKlqSxcTzkWaqb2VfFUqFpfSg5OVy
/qKDh1JoBniK87WtuoIvCeC5ZMXil7YPmEb1z53y0cTKw9GvX0v+1qY5GyiwHEYmBJ5Z2s2QKc0p
fpCYCrxl5SiU7w1y3+hjIR8JcsfVj/E41fQ41IL1m6u0+W5NzrOkG9bUuonaqh7hfjkoJc1H1CWw
5yTW1VUQT142+Cdkq5NuhFBiSSZLPgSjpDjLoesPb5n6+V6TneJu1yzHD9fx8uU6jdFn3G88hDgY
btzU+rxmsp7jzS5wH1WIe0QrFjtXeTYZpe3GZIg3l4idf1G+X7Y+MMcdXX/LsBu4TWID85fWxJBz
nSZOCQKYrlKHHei1DPUM+WmELMHOQNgaA4EzdRcAgAAXowuQJlY7NL40N1ZNPEKOZicC+hetWFZg
LLZJ6jyGsE+NIHpKhkEltv3AJUi7Exjm2BInBgMrViZztVL354j8pHqAlSpNHg9OI7fiGtLlRZcv
TNIo6kaTW3jENKpPF2uMJ5H04ReMHh3Hbx995FOA+aJwF+zePSRgJ4Y7teQYVipijkRH48MWkwVH
UoLqGQBWlPhEbrwbMBcurYo6QRak6IVs7js0+1+Bw35DfgfV/tnRbBRRtIuGU9I/83t3NsimgtIT
ln05li7CfZXHYjPw/h/TkkfksDPGmvOyiW/glQjlHD55CmSoDnavLhsL8oWkJ4VuXbPqUfngMXZH
ErvFWg1pdXBVMANbrs48qWr8JDbzJv6h5vGBTGTfq22JE3qygLnkVWRQI64uh13trRSwy7CC23mh
i89Jw9cEWbZ8Xm5opt7M4UD31lwZVj8Vyu8vTCOfftmHq2AZexyNbUQsqt3N6bbieI26i2eBLViQ
Yf7vJKq3wNEN6Xw9bTe9FySTcYuNQBwy437Rmg/L1Np9o0E+LnlPUGS6PeaFQNBzTPwpX6DGbWFB
VeN560ChowbYcxZ2y3BRJzw/AAhf2u32IVyvGE9K2XOQhlrsJEnIz6BUmIX/fB6z81wwpMy+Sk/3
r12xNnZAU+GBKpJn6yD1fLI28djc7d0mbg==
`protect end_protected
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_top.vhd
|
9
|
40066
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
N69BdjVBL3zr447/IslHpcQt6uxnKlEGffBeT6O/HPhIhs63hO+yBTBpbZe83b9oQQkb3iO1iekX
AN7IS+Oj8A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Q2gSgSjShBThnpN7ocpVeIiupKozmKwVJ1Ka9owDuAS9y4GGTKN6eXAv6ND3rH3bK2m5rmiGc2dQ
GqvMSafR3R5aQyLhHV0vE9ItdvwRv/PiR6RGhNqN3zMe7lJ+6AH2FuJN2tV2YbHEWsMpvrS/ozM1
eW8vym4p2Nmkhc0/Q74=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rgf/hTKzUgzPmpRNjQkGUhm/PJt/6MCtp6g+tuGzA135di4HysJDD1buAgwquHID3E9k4d3QtgNV
jT7ynZQIoMsXOeKCy7IbT7749cprpDjO1OSVrXQIUUcP3F+gMYUpeL/mjQnfdCEN743AXdvxRnDc
gVeJsjU9N64MxSJjbMUJmaddW7RRGip+wgYF1dVschvt86zUuMsTTbRlWaGT8/PVkqEVuyGg73ia
FsMYBM8Oi9K0SgUyaUoQqHE7F5kjUaDy36Xg4c9dGuC4pkwoUfWUCMZPrgk/nygkA36gY8gDvz6U
20GmRwirRv5LPFdEu9omr/mfCV1tJE3cL2wf2Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
whJ+Mq4deBZDhR4gHJnHCL7JxuEJqNFrWBV6Ksnrye5rfDk+zUSuuj6k9MLoJRMZ9NpZeM9BbEn/
lx4N2zpT3HX4I7gsrzePK4hxagplucoM920UdfcilS8ZUjm0BM3SKRCGqgigpDbBNz1MyRAauRR2
TGMcoxB5Ne7BWv0iUBs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZsJUyEeEG26LW0tiqAAVmbPXGV42PcJw5qTIOROOgw6cXXLb+KKUvI0qo0WOH27D2IG2UjbZ7zpK
8frckgj+Ei6f1HtE74Q6zFaEuZsJ5XO7FGsTfepBz2OcwZ2tArvysAeDtRyFjKM04fsTIg4zCndt
4Vdzk9lAcb45wumS3BULfbRVGBM9rMHjGQgaLzK9mgTtjibUERm67lPM3rx4Sli2JlzzgXGzw4cK
3Pr3iYBz4/HwqPFPp/u4PgTZaWGmrGjaG+cGYqnmk1B2xC16prjJLhkisxGz7rsLaUay+Y9Qtah2
0cQFnUESovN+P8/1qwaKLu4FVsSMVNnVAlt63g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 27920)
`protect data_block
oUSJIenzMgR4/U5g+t0OV9b2YzRljk+3vTKsVmP/tjyeDBM/ad42F+YNEodlggZdHX4Uv/M2JDnX
F2Bh7bgipZFJXIBYgIbFzF+CYRIfBn195Mur30OM3bc9K2TZSqS23UiRqfv1EprYZe5PFr99TMIu
K3wlq3slmtPtuNGDxh8MIdZXbXSWWC6Qo6DIF9Y+jzxVZda0AhojaG3I0FHVGMyhk3bMbzvvMF+p
V9A8JHk5PIvvMCmMJ7BjSRz3Xp7qLx9dM7lFM4W4WlHlKAH9mPMFlrjcbjo4j0iQ6WaA1k9i4O6g
uL5tY6I/9Mr3RJuHCOvXOfdLT3aw2OdlbZ7aIqq+i16S7m1mvfWseFPy1exlEdhbh0QPzc+xsbic
A19eio1NUsGNUGcqfGiQRGpScFomvtfYsV+riUorPxwf9+xBaw/Fvyxuqb4Qm1qkJAl9g3xCbtZO
oPYqKV8mIKcUuTctDjSz6WHNX0Fi9ZHCrt2bnNVPH3fJzAa2u+QoRvebrnzpKVvR3z3eVtN2epCG
c1aFNiOhI77bMav5qlA8mJ8SJJB/r8AtIRPasi5t643Ypw8ejBb1LN1LnDENUP2tFrc1r0eIlA6y
XQjP+8wr5r/1BmsIrWwICOIkjxUICe1tNTwP2aa2YB9azPrG8INODj/XNeU6kcgBuFYJR3Ku9vCW
hDqCM077hhDT6Jw+X2dPC6F+Pv6ARhHcFRRC9nxu0JpVHPuhcnTARvCG5Z1SJPYekPHoc5dv32py
Ur5w9npZhvBOw4/QCloCLLCiJEAl0iCRFm0Tdz4US226nLjvMp/YKt6qQH6zdWQ9oqtcYWwGs/5L
VnXG7xMDtLz7CafNLAHqGM132lsGcueDH5fEzSrZwEGNkHbLEBpBmNCVwryOgFRDCW2fqWrNr0A1
Osb7EDkXvg2OaHOF+Cdv5VN1oEHYkOhDsIKfRtzyWgO8WUiyNhHpAbPXtCArwkoL4FmcY1hFAz2g
s3h4JZocLMppbqal6/Rk6YjvrxaZJYAZT4oSeJdUjR3hBinQJ9YzYlZ9bp9bWQp7fE65K9L4qnBi
CR3PqeQmks6hmtpC0CbcuTcjs2/oDqrMZ+avAALZ6U1Svw0Gm00xLlF4p7BlTdXE8HZH/4NsSSP7
8AWOnjnEHwlZf1OEEetUDSfxWmFylSzIbqmdGIE9xI6v6V0NzSGraJiepSHX1zaMdEd3X+3r38n5
XNWjxxh4wotPfVRuL2/6wbQ6YSjwArIgJTkfbU8JKg95uytqIT3xpqB6+4GoA58gzgXZ0qvuezqb
iSF9FYXAEYVGY/86JvltODA/Lo9uq0q8Ad/XZY34rnZys2C36KRAlraoiAN+v0hAVhwqKhKuz1ll
Nl0jEIPh4iU9rB+npZPlrZsqqgViIvc/vPdUCW75ZPDBz7NnOPWYgGJ3AoCwwVNDw5CmF6ing1Wa
jHJrhXdD/EN3pZVL+oBDrwD67QJ9eETq1KO+vAq9HbBQkCcxqOqI6NieFHk9RnaIZxDqn8RdTmaH
5Mv0crhxCxUYhuisW4QtIXgHx6J9UiV1z/6yQvQkJ2ksuwZGiN2vbzk6WXbNvBXex6B+pMn7wkoI
69hlJNy4Rmj92qxFhaeymjbBTDzTmsN4sM9OD4W0qpvsJV2MEYnvwn8Kq+JAJZygAKJlA7KyLiD6
XHwp+kyWuGgXjt6cUGxutWi+vyNrdZGhOsNYTR1Zzp7BifaWZVLPvN+x5+gEUvQIKcXyp5m2rlLj
X3Zce6d44129LbzVijWnfBWibpuytW4vNdxpmHkwnlEvGRY6+NT1fujpIj0QzVU1IeGOqBVIv8CU
/p5/fcIlho3td1ydWgnyf1aAcFRJ98DgQC0+QR7PobeVlDEGSpSmbenRBqIzL1FXtO1R27eJTkwl
WaA6gyTntGM5ZG0Lfn/GGABCaIrwxADNvCElxiYlY/uW3wAYGawAV9NOHmUb2xeC9bH8R1a42EHX
PXSUoJjZMyTZUDh9OQ9MLOELvdxAfsAOcKorPmLC2hKmy/qaKQekgPRuMHCXSDNgcfAhVayFUgun
5OOWh8Rm5D6XjQZuV4jC13M5giDDOJY0lz3dbbe5hgOYwKKhhxPfn0x605RzuXSIXUr7ii8iOv5u
wXVVA/pkfbmgAMJwd8zKeyJY2EeSTNTyDFIw2ZKTJOu6Ija3UxGv5Edon1U2Qex9pHqn05zz1M8O
eB5W8ISWQHX7/9PBNhMBYb683izyfATGF0TRpwjAnVg0ulYUekjGNq+uT2+43zXbCOhRR6OYFb2h
MGxO+LYdRyDwrFAZ3AIzQN0i2xl1Gea7m/9Yg3bIgkiCLbLXevEswynzdTW6mSstwrUY7I5bnGVC
kMHk7LJCH+pQpYXH8knc8biwuH0HLIgiINQxuKKAScIMcn9HQZTjhRXQ7Ygl7SAEy1Vzlb9dVsCR
cyvDyifCVmOh64OV1Oy06/1O0B3rhwxYal15LAsgFDiZ6Ealv5i49FseagSCIQBBht2mnOSTIWiS
4wc6m77G1dFYLtVyC9t3RP629zMxa5o4deOi1aKFlKbDeFGPr48J7cJW/oYl5pEREgt+8UDaCPAe
adwF6Qs/NkISAUKvsSgET2ZhXRNMqFtrcD+JbzUequsIJ8bnZv+IbxyJRXTKJ1vu/ldUDB7dDs50
K/h4rcRaqQ8cluDv8iGnbX6ECMwafwtlnHN+5P2oGLqn13nBEbZtEto2ncQ28ZlTxzJQwgA94BUU
cCQfzyZN2na4ooJRZUSZddl4HdL/RzzQNpqx0GUPdy7BGxSjdL0Yq/F41H0GycCdL+UgcdUWSeZl
yu+GY6Lco2TEfIjRgm4X5q6EuEranUumNkaCidHVgYhKItj6SpI7ybljgw31gbgB1cZP4+6cSkUp
hnFcBEFO+ubUsG3HaXKTFNgRdCdCLRCuYjgPpGSckeys1qIg7XsO/7EL7gJIolIFb6ehaGcEBL6I
CUfozmftZ8nLH//Q6aWDuEfA51N6vpHFo8VH8xEYBt1IiGwYmTQCrBgPdtUCXIBzXBbR5H2VFxml
l3HxuHj0hnS01q3KFaeLM3v0cBQFuASODdm5rSjElwMocRYceVjlf4GD5XaxX0Kutgovx0c/b0ip
olOOjO40DiKvU5Iab9QkMHkXmdlqE+s7Fr84m/W9jGR4i1IYyJe4bIbWuhYu2wiXLCTSLLpKIFnK
6souCx0zXVJLuVfW8sviV6dYYi/xPnWQvs2E/Ke/TJPqe6qonauwh6YYNyLy68m5cw5fXo+SWDi0
7+cDM7vLhEX3ELh25i1xlzowDQsELJwWskfJA2yNUrf5g68UJgrJyVjyrMkh2BJaFvqfA3jbAvEb
9Etx1JE97CdOqEuKqnPexYljewjMdXGz3UyzBBvNVcLA/migawlEKxPHvLpfy/GJBSiWIyTUYJxU
IrOWhBfdNuXTF6t61l2gPo86+ok4kiKMR0JZEbvVH2kxxrKDcZROW1ytkI3W0iWdRrJ/zmiGpqUL
81np8Fss50oTs6TXz7flk0nKyuT6shUqYd53udBu4CUjYYMcR1bVel/iGCOuctHqtw4OJGisOclt
TPOm70YaTFdtOlN5V/1DIsThRzlvFCm3WiHg0x+MwRwfa2RQ61Noth2gQe4+UzNyv3SQc0Il01ci
hB+sVFEmOjoWctbTHR+13ZSZpo1HetpUEW5dMP189nNiU1x2v7u7bo/tWYHGhNkmGv0s81Miw86G
TxbFvaTTuw4NwEaIFXko7o5XG2YrkaM6Gwd7LtBXKH5XsStJxdeY6zdtKzziK7P3W1TIJO4m2qK0
iVH8Y1Ao46A9Xr8VlC+/4E2LnZ97+2gAlpTbuhiPAp5NFz1cgqPG242/mdvQA13HC4k9ylV2hTdi
MMQCq3NuZ5WEI6Zd5yWsFmzT2EvFEo01TUQ1yy+1fFB+Ae6bV3ca5+jStAVVYSZ4O4EOjJcICv61
uktBxXzR28Nr2ZglbeignLWIy2sKEvnOMynEC7nlJrlwJl3Vyic5cAkVvfo+MFupHVPLr+/bhTnV
iUuhWZH++Cv8Ufp2VF25tpJ3kY0Yya+y+DvgpO3enxF1eDCTO6CSwM//jWHjR3cnK+CK2VeIjhbN
jY8vpd6mC7UIoZ5EtxqujAxlEsePn4AC91/x5sk5JbDIEA0aLhu9msXe5HuSmac6v8v1jeM2D9vr
D4cgnHP9gXDVVw1z8P6fCUZSNyhtDVsnkD80B71aADN4T3LFXx3Z4walWbazbxE7Fa83My87lQrq
sAl9cOxtu3KMkzxp2nZedpMPwYKjaSXti7dSWRpm+TPk/qudacrIrdCc+/BlOzEfKwfXI2N9NuJE
QgQwNyaNYaNbW4sVkx+yV+O2aF4HzvJrhqYulm2Xd1P8BLClX9MdSFZY6CIziSAc4J/Z3QMLu3O8
6hQ6Sja1wiVLJ4n0Mf6GkMC3Dk5GhJC5mvfp3qFjQctSN0l5s1e0lpBrq04LB0MalXUEoEF1o/Rr
7ffpK6J8WW2QtwXQYD9SzZ7vyMMTVg+3rbgpsTZiTJqtSpxPFI6MmpG+xqeGfi0INaIv62ptYgOB
ogTei2duZx6qrNSVd7tbtj8y66db5AbchLeFLktXvwahU2buyFkRhMTadtTpKwbWDqM6PpDgV9vH
fPC0gGBBFzDZgkY0HEVOf1p5zIPMWaF/i0RB3RgOQxfmFBVNDko7fEiOCFSF6Ghy85ghMxcUDYuD
RPpcjmqCP0DkKE7GYgvn2rqy+oPqfDk0SRnaa4U5Mry47MMtWLyte9ZuIxftEHtO0YD4jYMda0Hx
RVTwOlDj5C5pPM8hJ7WeQkrB9sr62PhyBLpvimw8i3jqaEyJY6eDcDcESvJJVf9hDJpUzdIq4gtM
FPOjNEBs+wwXDFqtryYvNrJQ7JcrTH0t+ACTyagiX04x1S2Id2ZgYPftgm1GvTr5DWkHGr72LqDj
v43k2GXS1+BXBjxBQ2xZRWfnVHLWOXT2ZGwquLQXEwNJgk/6NHoJNY3X9JMWe2iDidXPX8I/HUd2
FwaAGBFMyN6DTDN2rkgmZloF17N9ls3J67Y59lTVxQ6qwlcQem8IUZ59t8DAPipNr7ZpiUM+zHos
WlZFmO3mj1aDcWYWn+GIFo1YEHse0mWOH+1IJV0dZex4Uoz4pqdh/EKbgxc7KghGKSxyDeOWb7wk
TdINU6eAqPhil6uHuAbfLFnATIU8hY82bnc2ERrr6JDPMaEKiTdfUv/edsQXiA0Xx174Tba1Ne6Z
7ElEDcc0M5Mq51YLPfeUOs98i4Q3Be4L8pnSN1BoMxN34YCgJe/t9eUxdibUuf/pDd85LM+g44gb
WcG9Sm4ilEkA2dnKE9sHBCDOgSMXC1jfun/jNGjxcIi2VQ3d543VIrNzbRpzEtqK4dFrxSd+qZvB
RKlk6jR+Y2pmi+PoZdMkRnuECJFsmaUKF0zW7mgER5+Z2hQZhVm/TNzc+pYl4oLEI9Nyzk1f3ycT
u7ipmVUlWx3Jn3rp7Rt8xQ4kFBpYpUCfW6XJ++HRybc12EbtynHrRoW/TWdT11OjQp9nITW3ihIM
LrcS4wQlzqEXVuZkY5x3MEfPuhIMyMODcNgtsSnYzGd7qLKlolxXwxcOuUI2r1ZKtjBi1b3wHWaZ
666owtdmApoR8ffW9rrK0ivtW4FH0FYqTSFemaILBWI7QZ0Vg0bhc57nxyITJ6b0G1SaZQT/z+s8
wgvuf0+872WjLIVCEkJ1VKSUBQKCdOTVSFKXK215cZDQSO406dygsRYaqz73PlgieCyI2lU1rSx1
p2m8oGYkUTkyBWByOf7FTLRnFrdOxiqUxtHZSWt6RLAk+Zqz14InSTWijUI1IDdtvbZ6F/bsVHBM
3NJxxDnPs14DG1qCQCDwg3TFbL6Hr9q0SPfk1ks1qZrspEshfDj8jfGImX0sni4madBco17+ByJF
xLG57SaT5saRSHNSqDdAkM/hQUqI38VSyi8/2UxDRvBICn+ZAjWQIzWpdG1DneljRMDALOTUMvTV
aqtZi6Ogku0yId+8AOfJMNTFwO3tUdzCYG0oBaSRFCV7XuDkrFktZwhZnovGKmrp+gBH9G4J4vFb
YsSxwvDBLyaI3elMOVt+Ww4llZrol2UWY56VtXA98i4hhA01hDsfjmVv+9iF74fe3BYQC2ewKC/+
uyuvQGmfpxJHC6Ju/Vq/DDDEL9Wld22w05FaynpnyFyhvevt+HsG/YCII1AH0NByCHVPHBCO4wXF
HYjH6UPfiL31cC70dwg0IPhX/YFhQSmpAboja9M2YZo9mMfg/lSup7l2BBEyBK+QVmVjFmz7HPF2
xzC9Dy7LTEXm/xT9aFbxZ7NC0JGVTaRnAIZ0tG3Y0tkCvA4E6R9YTv5MyNPMG/UiUZ8T9TBl2XQ7
EujK06jFo/dYC2sImCOr2qESeWLqKcnRsYxdUb3xfsxqJV/uIe790XrDsMOj6LZ9DZytSAtPT9kC
TLpo3mv+SHUJV9Asbs6T2ZotapMeUydl44fJ5a+s3LCE1aiFX31BcXiJocZgV1Gu0oBKW/AL6wRC
cOw3TnyQFK/j2u+qaL54FjJMgOLYCnNvAQtJ7sYkIbgoP7Qnku3nN67mCSJx5+AzBk48PFhUGgqb
5Bsha3ocJrJPsm2MYbq9BbmBlBM4slXqUpE7qv9SoG0Ibs7lMBi2DnG9gM6SqhbosZ978/h5Zm62
I7wq9J43L+2gQwEHelH8ImVQm+V9lMKQsU0ta3WG6j+w3pWkqAw0++XZ8xK/Gsd4zQnudN/sUajx
q15xxNgYKoZ/WSJpnlT5RircfzxPnAIW4j/LJeUDAwl6oBmeznerkBNaTTS05Yi5m5IiuSGk2Z8M
cGsoD8DPpzqoqq2mImJiZnNnxI18lHXF+/i9rwqmDMD8eIU8dE/qadcDQXM5+Dwgu+Fqrm3TUlgF
n8/+kvJlhA1LVyMVahfvZZeWfoSCPkfZmUqc+AM/eF1eOEwy/UJQbENvPNIkJ9wBpT4X2Qky83yE
fbcou9CDU1D1Km9uqAMDCA4bM6aviZUtRFafIFCd13Fp79yKZ6ZNEu2VO7loeznrr/evqVyKVexW
O290EQxIvQvO4pgQAPs9x3V3sBOksHEPM4/vMoYlu89jlxuQdU5yAWLRg3863wZ+9ue3ij1DnqFI
AXKIlLspRmmTgPTGhyC03Nw07L2TeTwmQuCe7/dTTtm55yyedh7lTAmRIBrC4o1Nxp5bvPKMFU6z
ZhYZ0qsvlrQd/1jKH26cC5F5uqXaorgVuXv45VyITomobrv+cCauhUegWtl8HdRCXLs7lIMc+MGr
jTaExid9pIZf3WP1aoNMmN+S5IzX0mYMUJDc1V8uyhrdt66Za9gSJhanNZDmYMRGUe2ju1Coq+2h
Zt3cpKzZEODJN3Z9K4W09zpDZ+kMCDw9z+Jw9imRvJl9AceHUPo7uQyC8g+ADSqBZqdkJLlgOP3/
H+/WSEpbgcouelJ/DNKD5ZUhpSPG5TGZL3pqWve7zUEHFX8VMlu1c8twZQwi3tdauae16uX9JBEo
oQPcZ9RvaOqDcQ2MFucY/k7ZLAQv4OpjjLVAKNMnmjkog9seuq1OiZZiGujBi2v2S0Z2o2jgVCKB
1qfzY2CHTuWyclnR+MNNbuycY5mIJxg6G3cPA0eXc0lDg9UcMepTj0ZuDThV4uDBE3klDSkGXkPg
WyM7YDdln6WAV3OqrxmrKZqMuI2f2ma/BbF24cqS6oLNJE9DRcfpkwYk9WZbkOzc2Yoh4epCG1xW
P7rGraND8ajqXqq51PIo21NYsthm3lZXMeOA5sCoCmN7+3817SnlCvc7JBt1zs5QF+DA3TRTnrBN
4gkAwAcFhT0jUz8PlDg4Pie0/GJDXIm/dH+VJ2zXmb11djk8YhP//+lOLkHlNunYhQL5QI9TwwOI
Xe7aKlWv0tJ2FcuJOh601/KPWxsWvIzNPFsE6z1CsntQjHaunkmqRMutcJrpKTXbguavJmsm+zGt
xdTCd1EjxBTl35J3Tt9LFifC9ThnfxiubgxlliKnTpg9iWJog1Cfw3P4oBNcFpkGueZXlAx+uy8M
0IftsancCJMNOkpdQBZ6muOWEBqGLE6yP0Q1XwJKfz89Np+fFIyclYAwl7sctptEM9m+4RcoXumm
iwS8zDNFwzWhzr/x5udibIJNkkwLS+/jCVMBFEI/gyWfVkrr/Wxb6QR8Ob4K3GkxfayYdyWzxRH+
tWUbKoNq9g0vPsb8x3AujGVE7CkUmePulDXq/nOOZCaw9//MH0iVBaMR6obHJxF8S34zaLMWVtmW
Hid5NbUxOmUsDvi99ZTrfbzWqPDZkjuFcPXpIteH+XAyTOir6EJiezTOd+tWr0aPFxEgA2wtqzee
W5i9rXlX+EXDDb1JUBlRyIV+RqpY8Vlhe00NnpUJlkfBPj684Qmsp5JYXo8AufhvKcjemRTNPIvE
/OT9aZyZy3Lg8U8hwFh2VBPtns7KhsthcqyTgNSj2Jgxz0obaQIOZ195d/3KMvEgJnFYka5WMNuK
j8YPUZRVxqjgAXrW+AP/rUFoYG4ScgJqGoLiPboftFX72BM0NYWF6NRM6/Oh+hgnIFqEfdVTCpPj
365GOMC3HQLqEZiM9/UOQ+Xtp2a0kaAHqtW7Azl9W7L69cwPIkZIO7QG0z8Zrfu54CnKHoiaW3da
0E29NWeNY7I18NirX/7giar58JZtH2unUOo+earRInRIg044FdesiYwF2s3mzes50TY5ymOIyiaV
W1iWF/NPVf3cX8YYn/CGhRFUby/piZrFcsM2EjtRJ9YCRlRp0CiatQS9Mrw0F4ks07k6Q1waXShW
2JsO4dWDrBqMMpYRDuw8eRDymeq1mIdo1VI/v9Biv4lqdkU8FwLQ1m9epEltkfSy5hbeIAaMnk1s
0FS0dsQA/HSWbZ1EO4MWfMR4OAV0JxAmrbQgbWYiLduWtMbC97im+ZP9JoSDUTNNAqZriI4BRdah
3fTFt5fwNRMm+uwTfi7/jRpoU5x0VIm6AxJnAFhFNkrSZJJm9urJ0QkmOPhUxWdU15oYrcI2qHHk
WZV32eYiJq88yi3jN4u2DjzKpEc51OFiczR2G/kGZVsq3fIObGtsF0Vb+n2xXoF+V5KES6dpjQoy
yXjSJDWMZRjtZS5M8rKz3XeVcTT7K90ucgnwg+QtkVvcY2KPGEn8xFgH8r11u5ooC+5M4DW959R7
NQpI5rzMLlIE/qYzy9XC2VYAaFaCCptWT0HQRlNPZWQgQ6EpG4Yxh9//KYWPvOBsiK834HrRYHRA
Mo07OrYuBfkEuxo8WtGss/4L7CeR6E99Gqisj2TmMN9HiON4+KYwYpz7wMXQE2I3L6AmUa2jhd8D
peHv2EulZicX1HQw57T4Y+a62lH1dKYk+xc5hWz9bw2VX74VuaFVOE/8Z1XCC8gpQAOr5jzePNOY
MoQ+/Zq4URvOwUtgRVBnHO3vRpL2Iow9s+0tOZnft5dcAeMKKVLt2LYRFjI9Dm5+Gpu3TiPD/d19
2prtKQkpCNFL7XBXy8l/WmRmoqm/oBfc82yB5B/hdfcOmLxUIeWIG/lz6+hjh98+EzGh0TIhzjfP
LRgfY+xmrSK/i/E90VU/AM2k2LpMW4O8e5VQqKEc79FUT8AuQvSx3s0IMFeTSF0zojrYsXuUwKwa
OBj7Rf1OyOy2S7UusWrNYSvmTfMqyn6qMjP0fFSb4oU0Yfgc78hdZbSax++bRLHbagX4EiFPloMw
GSwyBn+bqsVSXwjOF9qxb9qA+Ws/8j6OAm+C2XdqksDha3g4fC1bJN0w1rHmMk1CHbUDDd6QZBgh
+sfYnA6EBaTdqoA+uFDBKYAkxtg2iPMy3cN4HHEF1iOdrrJwOvyaNRO3/PJA1JBwvYrYd93ISToF
7+bT9+7FJHAgF7cz6MY1vINMhwSNWSEg0tCRGdg7Yydsi9QBjJyf5czQIcfvZp7i87dSh+Pu2CxZ
Xg55KNevGN0oaOjjgdMFvANJRwQgeo7oP4HsF8HvWfPWr00axULI7sOETJTKTXCfkixKN5VNPUMt
wks97zyVsrRnCBOrTX+FwyPEnweyWWXfYL8lJtb0iMyzEFpls0vLkKCP+qG5QrQybwaGfyLg94bN
6ffcpoEbXfuliJTGX2CuWbPqwypfmq32LK7Tq4QGSr1oGvFRYAgLLrDaMzZIYmjQbgOrnyfyRbVQ
uRj64Cu9qcJwhbEKHVf4oXxGoAdbcg9W6mu4ZtBIWmPIBc2R4v+iff2iK0RzzMmxa2EQ28p3Z0uW
7OMeznHp7kgFgeVH0b4DgV6+tT9+IzdPW68l53IqIexTTjjTj1SAKnmuBNYnkZAHCXEaDb8/h6tb
P1a3QpzS9mV2IU42LNwUu6bJtQRHL3tkyINxEHvSV5tBIo0bEd+G4yMCBPNxV9dCR/RFp/Bu6D9A
qUBW7Y+A++m4AgB/NYd3vsUJKj5I2dsmNMJSoksFfEwLHqnXBzmiRRyMQeIIc+BqE/UkbWJHIPIN
ZE54w1vaEwmrtNxwNoJP2rU7wdB8dfRstLiMWkIDTbgHt1LAG6nt0If1r1go6ooJiWNUkiPUyxf7
HrshQn8lTmpHxCpSnPGfBhm1hao4DaFC2SQqJ9GOaznXmwaqOJvObiNYVVCMqe7KSBe0+xQF8Qwy
+HROROYu0dcQDjKpQC2GgTScxYbzCNBUmIc6WVKgtq80k27C9UG0BUG2v8C7HCJm86kCJ9K1JS9q
3pkra+Lz0yoOjn1aukl+O5l69li30yy/J/YNyWRVXiD25ygUlCdwgDMYbY42E89TIl8hDBQTWHas
Zp9OwaUfwQLYEQidVi5jByCkE9ynSEDf1h2EcszKQAz5iHqPsXjv/yb8GdbPDWNrW37cyhSj+d9/
l3aa6vZt6GsjCpgJh2tt8kxbPg6/0UzUcSQny+oH+gaIvoL3umXIpVmN9vIJWWprBUpEKreK+PCJ
1qtIF3OB1kI2KkyJTqglnNFya0Gsdq6RPjSQc4+pWCuGmZphNZOWMlo4T5PHrIqRv5rlnfSyFTP/
XHriZd+5BdS+pMcB7KtIYDBlRj1UZQykETTWgP+B726L6If6WxaAlYgmhzVwMVqUyDZzjQE1YSID
VhSSyQqIKwBSN50SW0M9EdDuiU6tJ0Id/ZwOGmdKqbOtKarA7cinh3IYdP0UBtnRz0YsI8vLRXZf
sRlL5on9LTfigwpndiYKO+AD3iMrz8o5vRorn6NfA14UBXV2qchW/6Yqw0sU38PCsBhCxBV299JZ
0lnQuOmwNDqOu4iNWVkHf7iA5hiJep8F8P0gdtKqTCRIE49jl5u80sH+KQ88Vj8BuTCKO3U7Aade
q9AcR+BotZZIdC9PTJHLlb9xHDKKC848RuGv8EGEfcoq+4q5/QP5a5vfF98MbfMeddguwhNAVLrC
K1FjvmxE5BcWF7tIlezkowO+JHx7G0lLxAHqKiML2hY1wUyz2E/9ChIDSKOft1IYZGpDja65vDFR
KT/qH57KeR1EIBVejNfm/oAdnw/YO1cAWrniOqQvgwwUlYEhuTLTu2YuJuGbZbXR5en5yaSQjRrN
EGcys7AmnnjI211ZdjOjvVAeLRr3jSQqZfhiGa30wNUgxlPvMX5WLOslKRSKA7gjzhULCrKA4qAH
bRmOiAm+robXxgQIPJdwgkKWUDatkXT10QaGjaMOQrvJ+5WCAqFPr39qJq+ao7DJ7ZhnQFdnLXtD
63Wrj5/0Vxkc9GPxEUo2bH2qpkZL/Td1CYv+oBnChg/S4wcJdikHvN8wb7kjgmG0l0RKQP8p46y+
1W6dZXKDL5m3U81B/F13OkflXxz6ggKRCcteQh55Lw6SABqJSexRWoHDNgc9siP96TcQAP6evIwb
IjptNf9wQ0IoQM6ZBIBDJ29HYoVfNZNw9YHb57rmWLNhmBAwn12+GQLtjJIaj+RD8+BBnDheJtuI
Q9DsMfdEph2GiOj13qju2/EZaCwoBQSvso0WWkdF79BGmtPF6twYlZLsmWt07ZrsI9xNlwk3DGvs
n8RWb9A34PMDVLiCJKMcdJ4ttRnRNmlR6U+QIY9VzCfM12mGASXrCib8o3ZF9ZjWy93u6bcDw/2k
q+1k3yTzXfDcfQejEzl8Cr58pEiHWhjfgmSv395Ondq5btEbh0hcQUGejd6c/H/2a0R3jtaQehCk
KtB0gB7wPINjA25DTXHohnHMiwNUbT7fn6jH7kC92etHZe5z+4FS6o0OdnY8I9Estgr/L3nr8XXV
mrwKLHuT/ygnTZ7F91Dt97XFs8A1FnPZuI6GH7QUiHp3SnJv/7SAWbVYPNT7D26XFO+JP5gJ672K
prrGv4PD86bTmMf/bUIa6yNquFcaQaD2U5PK5pPleh3fIiegem5GOVVrniPOZ2ob0uEO4Rq36JCX
UH11Tp05gOKr5AdPV6OtulqHp+JA+8mSfIR7S26qu7Amhbf93m+V1Zj34iARI5gnLmVv5MbK9UBV
89YI6uH/dQeOvrHRsqV7+AkCpEEsezTzCwS6+U1nFMnowjUNOE1XZYX4gUv5/YraXywxXyYofECF
dJPxJyo1hL0pDRpDzyQF+Es3udsxKn7q0u77f9I8uoBh6hh4HP8KQYResvkZZrgxTwQQTxiiaxqR
52PMlVjeMgqJ69ol0HaNdLLXDWxw+2z7SyFBtv8wBnp6byKzn23VWArM9E/nMh/m9HLm8YqNzd5s
J67DZumP4jIF8KN7ygAp/+LDsXVXj5/habTNycLSXHeSYKE1X023JjPqpyHpimOL22tnh/N2C+iK
1WOMkbAx0FZUkqb2lIIv7/xJEwvHx1W1tyWMEW18+qUvMx3Xt6ABgKAMJk94WW5jgNqzvMDvNbzF
V2J6Xkk8XqGZycLQtk4byLI1BGdgk3GjXADzqMLo7fCv/c6NS86EdWukaxa68HWRLf+jBFZrZB2C
iO0fvOiLTnqfUiuS+MRqi9Smkojl1PQnKSuGidDlBpdwo1FrcOJ5cu9IZcc1dvru4fa5WPxYbeHb
LV/3hHvqcixlMAPwmZsPxEg0C3dHzaVJM6UC+6x4sfnMnFLgrI6sUJF9whnDNGGgPOzBDDzx5W5f
v2KPXDtzqmAhpSqBS+x8t1xgmlvz/LDoXMaLbf1m8ERAM7ZU0IXXSEn6qA00tSd/MPTMOC9Wj4GN
QW7P5p26iQpANY9wI5Ki3GO5DmCqVj07leODPqBeEtKV0xseaCwnH3kT7FUqL/Y8xixO7wpq18qr
w8xdAW0fbYSmDZgOqUo6rFdeFq1Guk2CegdbR6Ny1QxCRP0aH4LsCkmmLWuO0+T9cgJe7jAuVnuv
SF1UW4RN0eVFdw3Tj36EfQqVOJmfBycSSiuhKjmI/2F7815WukvQCKhZmnstLC21nkZOuE1O/1Js
eG27dQ4PeYmM4iumvDxUSbpuWkMpDhdqJruMs/BssTQrViPTOLta/uBxYsNu1xN+tu36U7jJk0qQ
xvO9Gxy+Fd/W/6NFJMinjBMoA4lnyz2CtmQ0MyEZczVVn1YkP88Tgor+1jMMh5BCWRx8TPUfr62U
dRTEMGK8by6i4kGjmR2IrS8hKyqOjZ8VAT05FAfRQQCYvVyXA6L6jgFKGAfve8txKqZDeCR/UF4n
pOsgQUzb3bg4/GGSELqYct/NikR+6nQWJKkcCQYWM56D7pu/KGmjrSoEjESKjfMetvE9MKjGF24K
gpOJPU3w66PKO5U2ODSOjrxMJbmySMp9FHsQFKcp4mzEvfyahdaVTDaLiTnjQ2Nsdz92SRo9xP0q
33aTEzczQg9HJ4NEnUXxQ+j1K8d0iYnOFFOW4eAwfpzJ1S9NhJVuoWAjmrPP4Jq3S6Liq7vTyFYp
KqyeaWjIT+VQSLpEZLmyocip1IEdh+uPJyHVCpb3TTjtUZSHoy1oOAyhwjxV2WbRjKp48XzzruHT
UzxP1CWZYV4oFAp1Tl10UrXP+g3uiWAh2CHwEAW6Q08t6VQSskgGj4m32kmvAO/UQNUn88sKjyer
LM36W6eOWJAKG4hVzYNeBfQSFIMc5MHXnswYNrUIzcV50GCm4ho9wUeekzK4XIKV1pJvK78LNOS5
QBRKiq7a2gFroHnE9TV6U5dNmEcGVEIDLUqqlVr8YoyFbZKADpgSD3Ovz4Hb/ZeB4jY49pTHnPPR
zFSq4hCX2f2XOEf9wMsU3QOY8Mtw21ebcaJ/cAPcGTzbaBdBLAEm+xnXLnfySbkxwH1XhwNa+6ER
ldDipQaTWZhnzTMG4ZBzMRXSrhanm1lxsKtKXeGsQWhhlpRShOAu1XmVBeTz1frphiwNEziBjLBU
Olqw+MVCVFgN0IWrM/Gpak+Cgmo62SHvRXhFYB3SqL40nupwNjHELoTRcyfSlEN1HpRnLywC7vWz
iSl6O+tyCmB6G4lP1cWS1FDiPeglDqI0BgJbAOolPBJO/wHEQFhRYyfZJH5SdgUxExrpbxio6VOe
RqHfZoJ4XrJoyJYokJHDGmZ7hv5fH0/4Boa1H2zzXY5z1ieIQJZ+1c80cxMQzQqv5ccmFF6aQAyd
Z9BAZHdI4QU5jXfnTGjksKkc8j3gJ0Pbhv9YLB1d8vWXWlP87TulKfPuoHxGXwvXDvpin+7PzDhl
1so4g6jr5DC+gaG0sOTLXZB+F8ShzT0JxWxAUvJ/ECPYcDDgwZqbXj6PgsZLf5pxmPmNzHlgAK+C
I7t5dyFPYhgQ1hjMyIKHFRXgKw3sB8Cmwr4f+5rlMrKmd96KGGlJGQQLD2FrenwYbxpQ/RBxBqHn
WF8CVjSMHLnHEaG2LFFtLvKKXS9ouIe0WO5ZLPfqy2eW0Y6Lkk7nTo2Pl0Igg/zriODrINLDP9CZ
rtPnTWmmq/Pf/M52mKjMb0f5rSGepmGImmjuKLWCyc1AsqgivaQt2yl0XOzEr5kMF/C1+Jl7UN2L
J13OswrtaAg9yquxzYISvvx+YBnMUJ+e9zcLy7xLs2xXUPg/eeaHwM0YIoZEcQ+/h0/bQfMFiMUf
9efj0hC9h2450PvWK5pIt/os/gXLNTGDTiDmMQzOJLfCriPmi1c1qPm60AAsZstun3JByz2sM1oj
7KbdU2QZotS+Gd4r1atIcywRQrIUYPxcVNxgWCmw5EiDNBYXxIR7x5nbjAWxmKoE7Z/jXunTBqk0
c4mzCa3K3vq1z8Jh65jn8ch4sjNQkBoYuiIwWCuo/KmquW6tLuC2RAHB0K2JbUEJBAjoTvNwKWW3
1oFRIro2LGWbvNxYzYen1rJ02D5APcP7j4Jx6L7TjQ2NKv8cPrRjxFL/Ag9JLh7qd7xWyj2Bl2VO
D3D1niYmUm8KU/OC9qN42HHcx11O2k9IezTu7UWP3TK5wi2qtiJVrlyhzh2qYLMmkFwYzw3j2RWZ
z9RaceIR9ZYrfVo6ct2uCL1AkcZ5gruhDnOuxHb68jiI6yA11xBD8O2lYuqaPPUHDh95vpDUQ7QH
4TH+RI7vknEEl7eE7tEKb68QWVCESAwyuWPmq+ZJ81qTx11IhjqixV6RB50Wt9Wmas6N6FvkyX+L
SVXG3c5MpWmOBWb9pvTKYNvapocrdYLNF/Hl/Z+dxJHoMCBvtWm39Lvdu8lDOmnnUZSwTmWhPd0n
5upvGL13Ohv39nVhZofkpP9ttecIxGBJRtVKyV1LUvVoXf2rJAWZ8TgP8aqjodlfgsmH+rAlfQ/o
G6mN3rzSNeM00OsuBUKi37D1kzdZCLJKrF1CDsrR4nwku81zSYlXRBBjvmkVXeprhz7ovxFHTxkr
PEQyh2rHV2POj93jjQBQ4cy9T3HQhbpr3MDt0rvupqnPamLQVwSmNMisCgvhO6MTEu7EYm88pjcT
QVRfoZlurUqbCwK/+pQBtm3DAzK5ZUEWcNsSmETOPAF6CmBbEjAhMbZRFIkbfU15Wa+7BaNsRdn1
GvaIVHZEIOMqTwbrszhoUTDvurwRb1wSsbXmZQ/LswCjJKQ7JMB3ruKd/ay02Ega2I6yGvXhNbrE
xhF/BVt2wTGuhUJXQs2pbYVNfWZqeO4TViltyghMuNVc25+64SlvLj41Bg0Sub1LUiGMK8rZrj2l
3Is4YHEZY1phqaj92t2loCHR4C/PudiWj3Ja2h0eXSiYqPeGAwgsK65fjtJdFGhF3v1L6rzRJ4Mi
Q/D89/ZlREQ9PCKmKO3fWnOpTFvoCV8GK4Zy0dw7+ezxHI7TTD5E1WxxYO5coSFdY6r2NpkugpNX
F5ckupSi50adj9oqSwyCi/PxB7Zf8f/QVYZ8P6c/TNdGC9svHU9gQSbwzxmroMS+uoMQ+ZRHZ7Wa
7PFo1+6eoTpNnVqHW7HqRJf+Jl7k5rgWA/IoELzugSQLWhcSAWfgLL01I5AfRwvGUlBVJXFiAHk4
nNQPmE90E4Xjj1fft6EEUxax86L+UpR3Yy2wc0XDvqINC4TEu4cBeYwzYLCuhHM70lk/hgPfPUJ8
RS6gwJfrAD2JU36fs9nFUmEjp/GZsvAtnUkOrZTuCxFOXeZH8bW1hZWblHm7qlyDcEHypbYMdUIj
cct/gtGpyu5Q9NEx2mVrpl3dw6g3nhwb0pzJm5q6nOZx30JRZ2BcV0noqbIN6S3H1RhLhPeW+ftT
wNUuzam2HtTjJ8qWZsVo0F9d0uYZkCbfv3HvoCJLsqGEi+4uX6aV3ldzFq6Y4k5K5ANQDX+/cFfj
PGotvyPP1g/ylB3H0rFefzFcJ+y8vhGOm2GKJNDerX9j/boq2mnxEojGbBWkiNb8eF6/vcdTMtKD
YYhozzq6DxvKxb76kUFmlFg0OMB/BYQwzPKShQbVa2m+jfhaCuqKGF1RyNf6E0fyWhgWxDZyTKm8
5nnybao4wT1ecMRYWLHBiI56PTRhwlyRlQfmHfswCvTa7S3214PoWj9c9I3LDYVPtt69cWyQgWLi
SHNuvxNDec64kZ7WLE5RZYRx8qh+33U3Z2BYr91OSKhNSnWSg8NO4xTBpaKlnCCgqHOwdxOnEtYe
YMzLIzFtU4dNGGXAwyKKjcjvXnE9PAOn8m1ABYmuIA8FqsM4YBxDo73onclhiNz3NMtvGD+8qPxG
m724nfQ81NfjLxDFd7WUr4Ws1CtSr3XKkz+jNXbb8XH/d02gD2xLaZzG/YF7Sq6seh/ob6UQGCcD
zVzNlCmNBxMwT+bBbhssSrkRNxoo8bPvFOieb/isHugMGoVfUX1l4vy1OveO/lBrNZ69E5AxBO1A
7mFtanrAqRo88DXkIylGHIlJjpL6jGJZeSNzGu8lDfSmK8eKob5fMKbcNJW9bofIk5t7TXWtQ3bB
WIPd+mnfuKX62y9N0vVkAKwUfi16c9Zh+VCUJZNWsV/G4g7iakVKH1oDVkvF3LUP6VzkEcNcgf0V
Hii8ldtUY/ExNhJyThKLT08IrZwWj6P/QBDKZLkyVfrsB3PuzNGbfPbT7e+PNtTOY7y0S7yl/KU/
+AaBSsufapvQ/lZxJEbeMJHHBQuhqWbIU/LhFQNiddmYt8zmrY7U92/3ozGLF8+gyRf3tjUbeCdh
EQZAgQj9CXV6zUqvpiob/9cOpvMufSxwZcTynzMpRpBm7uTC0ZxjcuutQvlJofsBeSk+K1cd3Wif
cY0IxbanmjbQUQXJ5GDmvl6LeTeCSZrGElI9a7iY+SsL/bHDKI7Ohk3hlJ/aY3AzJHOFkpRVs7N+
szsMBRE4pJgT23ABEpHH+YzjJpjq4qERuE/3wvD8LVMx0B9hnuAfMzDT5y390sfJI0xHoxEhMJxs
fHL1GpWqGDH/NnzWQt1gOWLJmqmvjx3qzk0vrmEf0EZyeAMHvephoxCNndJDCrLiswlP6/98FL7/
MCi9Tm9hCBIJ7QfN4/1drNmIK3ZqwM0lWfkkpQ7zlbFKgoqTYnNHF6ZQ19lAmYQrOsne3RKmw8XY
dTCPPKadMbm4fyFctYKHZGVnzksoigIr3FlKGgmax6BmIrHcHAH86XBF51AKmqf1qWasQx4c3rR9
khm50lTpn2sZitB2KTps43WGB6PlpU70qBBDxjB8TR5AMGgkdMdHJNoKGjydIvW5lm9tXT4iVm+c
J1SeOm43NdCghm06bDHY7gxBmds9+kGIScSIWK3sWYQfTVwrTSLNLvvzNUd4BukoZ64Np+L5J7WY
jENmN+Sz1t/C+ThEq5I0PZ9KpmGWC+YIXtmfRzVI59ZeEzyaahoVwo4ErhEUXvZ84VfhLCphB0iV
LAG9mhhzU6SMYvmOKZmqrspo0hi9Ol9NQvskcK/kCYkbtnRZyoG3+MOYLVQzUGaw02ki3mWc0S9n
oGlQ0mbpZ9befQ0yJ1KX6XSiCSz2oe74Xzla4u51Fl6DERbs4Aq++vaVXJnLrlmQdw/+i4hTBTSU
8QF7qvX9MdXsOu4RdOX4gehoJWaES316w41v2SdZeg/Jutru8tD9L5bcY/43JAAanK6OxOmm+/xS
mlzmX54Z6tLP1FXWpeRUY6CH1oCHJ3oUhJBhMrSE0tPHV/SA9TV58Q/sbriYKLkZwvA25bfJJxT5
DKDDsxtIsX5q0z7zz1aKp9g2T+DyVqZDmqFxt0p49Uw48b/rwg/OkiRr7JD756kCn2lHlWt3lysh
3EMezATH7IMC6pgqokTri0KP6r5C8vtgj9SWbagmTPBLEf5PUkHce+k4GhLSjMKNmZfTle7ApTvM
UtEUdBox0yUIdAi34UDiRqVKNBeei3HPa16ghGEGONcZOWMrIM/00+/XKLECa7SYO28AlF+pDj+S
kTqfkQ5IWnQ4lFPjtS3Dz73WSPV2dVc4v3JFU4qweYC6Vdy3fCZQ/XESJC3rFcEN+JSlETneAanU
5JrIJ5+9/zn+h9dF21vW6BsvuUnvESpfvu9BixcnO1zrY9pzAKDUtTWt7KgLsL/Cq70otQTZGKFQ
vW1ae4w+q24LFTdpaLtnXzQtSm/rCLHtTXHKzBdjq246ddhvBAde9/a48sAQiuZtkqtfOWmcwwWH
24j7VDjthsimNgYh3hiUhsL7wqN6z44N9eZUjbxqleh+i6MVgBN0vKSRvd8ugX8zwqcxgVO+u/9L
4O9XxJX8HYUPF6mITMrTODisWohE6z4BZGPuFLCK6pE+oNh9GXFEgzRHeXJfJtUWwKxaZMonqfkQ
HukrnevEpaYq28rbKh+iDumIhLM+br9KjBgZAJBga6Ra1Tu88meMSJc5/u5Q4XcnU5J3q7SWg0ZU
8cO7O9sBwJbs0faW94h+/Jzm8/dAK7byxCsG/qjLH1uq+Jvsh8XT6eccwDQzxWTTBZJei4/9DaRz
Ed4z7CBu3aqU4IsgGJGxHRBy62bRn/vi2ZBFzM0IArek3m6OSXiJSIMoczDEsmbMCePSrLeUkn8y
TO3B8a3yCdvGLg0KSz45aedeSNmJUI4Ee5j5rNbINs1jQnwVnXHXvVWHjXX9rhEAZuZWIB4/u4pw
vQcCakig8fWQF1PjkIvxGsA47LJEXD+4j2HkfYoKOpxaVdVy4E8JJFv+0Uvi7qZv6i6iR/BkVMWb
v79kuayjtu78keD52ZCMyqi38XAmjlrQZYNfw5L9U7H+Ljj3VSfrpnbkReWJbythcrzZUupnQcuF
Mny52gHVFAffOtp52YB0JWKVZnVl27mfHJcXOXMwhDf65I0SiAAF8m44J8lA7INRHu5YVh0IPUqz
kEYXCxpPqy84vKLzv/bMHs+rYOKFIUpnwDSzcWCwBiz9FXSRDUurv+tg++LN6zdNdYhcUi1ubQ74
143GQsupMTPsoKVViA5G1/t0hJwsMY8Vn3hrDkwveO8yAvjt2Zu/kW1/5ohl1latD3TSsx6JZHf/
wCoby/0soteRlNobWzZAA29wDVptPAdea8dS/QiRK6BTyI6u+8DtrY8D/2V1i3WcXjdJOcXs8erO
X45H0WkNZjny+Cj4DqMwgiN2w1x8KROkK4X5NWQ9LapTu319/EKbQ7omwgU+O68QkrEnIseJEcYK
LTy0wlt3hJTTdlNv/FVEDibdB7wm7mWkTixd5TbYh1MH/wivMdgUgaIGS8KKmiwhY5yO44wkJ+BS
ferzfJKpR+ORiS5DLjQ/jv2aLESfC1N1oPIpKj+UmRfsF4CXMvgcsompIkQ6VCKKOYPDaozkE81j
kYCOnAwCbi7ApzUznSnfBEtx97I5MEbGgyheyX3zMCEfJAZAh1K15Z3prNCbH0cKUSXbwEWFxdnj
OwVPl+/+y8ggDiY+1uGm1p/9nVTGaB92q4cVdMjSM86xRaH9cpYcGX/SWpUzTWyvnhhRLfiEbtaH
sIh4TnbGRI/bXZ5OShJrgovQiBeaaFHQhyqAqLz6EbxJSZUmL24mQ25yhcyAvYoFd53UZvBOYL72
uHC3SUE5mObb1RFaxJjGH0VJgf52CIqh2AqdF7BnLxHRMMcD0p+IdQ/rfiv4+3AuJ4ZFriafbRRC
hpuOvs/+cLEwGOt6w1WfZUQJYW9O58rOWBaifdaBxEmvNb2MIMX3l+A4UA+iKx/PelQDPNJme4Xf
m41Zfiv79bW0R9ABJGCt/qOaQjO6/Y+gvG3QB5rPwtSEONq258S1bQVdfSs4//YNIfeb74ty/Qw+
Q71qmethXpNOIxRfIAksrcMfpOZstIwwXqzf008oKsAREZVK2qPCNtNQD70psq9FxdbczUoot00j
RpzIJ1aYjbYs0KjzD6b0Fc+YBJcLjCiiUA4XscudG7E4Q6lhiojYnlGvGeDmRReWNqsAJHG72O9+
kxlwkVMqAKvZgqxJWY0p6cBBO+oMLaahW8L95aK5EWvAtnzooi3hetCuuELrrhg+KmJegTmyvXQ4
DXglf+P5GSsVrp4aIYcfNmEj87a7MBs2fx+1K5s7VBq5kLkdHVnAoB9thWd4jLxoplhuFAUwa091
naoHAgWQNA1tA3HDeQViqvhvkznOiagOBNg5CJFgA0B6gksQAi5yE4LquZFeaDpzO9qU4I5+2rjh
L1JbwcQqiWQR+eIeOCzA1sKzjC30ZKsJbgUBEYYAuRv13e+lOxRZH5fe9/spTIWeIZr6Iqp0TKAD
XjMHsnpKL+dViCOu0BnwpEgg2Fo0PWAhPVICTk57QiSI9QNcPskRQsQK5GjNtFk9TmKkay1IZEuj
7uWuEr2SxZhO/33Mgu2p/IY/PV5gvfWsXU05REZZ06aiCz2dKqAc7LJOjy9X5b+CuW1p8l47qumQ
KjvUcj71GeTWbaAmoxb8g60d6e9ppnKMfen7PmTfb/TSE/Pcu126QEjkuSZF3+oR/WDE1dKuSgsx
8IdLX+/amFV5PWc0AsyZd6CuInMzL1otXXsKx/VVxO9TJq2lgUYZJNU7XX2JPf5oUM9+37tw5nSi
rzRydoUFPo0XH20SaZ4zPJaPmLlUdvrFveuHvwU40CvQKBJN6wCkwPjYPbS8DTCMgUwfBdeFYkXo
VOScDv3OkcpZcp8W2oAI8Tr4mPaW6mynOuw8idnY3BjruLhUBRmVWZNJEYjygEIhlQw8pOq3NtSW
4qXqqLtl9Pn2vA/7UNRwfPgvInj7PuWFlHsjzLbXLDSi2sB583WnP6DgJU4bKnrgwreg3aXCwybF
GFu9sYiXzYThtm04Z7KgaF9OB8HdslvR75Y28ZRkfHkSDvRmqiEjjasmqqRQri2Lc5kpGlS3eFjv
XJFKMM+tNiDdf2cBJ37EJ2F23LydmTWY2GgaKbUALncqRNXOVt0IlUPmq1mjnuBTiLvKQ7XQNTou
oeHaJptA7u7ZgBKjX2gVgZrtG4bzZuSfjFasyRrW65h0P2OeT5Mt878nay7auoFCpmgrby/9aNaK
jhdVPrfoSBDZUrfb5PMJTTpcorOhD7CwqU5AY+jJztpcjAGF2ICUz5a6wXpISu8JTHjH6/Ohig3S
qS5g2xgV2jSi9R3SOU7HWTMo7HW1q0/afnf16cPeO9O8HDzYm1bYWenKbISCfZmGxoIeOYxv+rpK
zFFEK65/AZEyvI+8PJslCItnZc5B2bwsOwfTSHT4yG+CYFOqK/MQPxFmqnw8XrHnwFCft5QVtfdt
lOOU7pQHOWh9Fv+nOAf8KKHB2wqw/WLTmXdutBKHllmiPmTt6baVefxloCSb65FaVUCmDlFdLktZ
RS9lZtTAZD1O5T60vNhTdEf+1V7YZlPig9UjOcEQrPVgfbDTsMWIylVfdXBQ790FhoJ/ovfrENIf
ucu8mWzl/uw+5pBmA2gaWOuUJgmgkHbElonhOnBBzwWOyQWPGC6+MjhZ312EoNIB8sz1H1D/bztf
s8oLoOUU7beBHuIaK8dBzF7EY53CZHXjKvT3vJRTkEncyG7wAPEwcIMlsR+YLguIjo+tWFRY4x+3
HsuH3boX4u59+/dD88XNIH0zs4RR/++06YPfrpMa2sUJ8hW/9hJkI2VZT5Sl9BWwtQaZLBnDZWXf
mC/fHW3QoXTuLBXaWPZnpJ67bCLED3GjhuFkLwnI/YDIeQIk/igPK6wtaWGQBmGruChClb7me3kz
f9pqJG7/P+lrkZAxBKT0hMRbf14uH94Q1vPCigpSYVOrS7UD1tmfkN9qNhE+Lva/HxtRgAvBaMvy
wnRXNqkjG931+8IJPAG3YB6FcpySzdKEaHETx6iL5RuHF4rFbo/C1g09p5B6L0FnDlfPujm0kuPC
cGowOdNoOAx92xpEf2G8UrLCA6a+3RTMCpO9gLw7+fzSOo1RZuQTDOnB37TYehSGU8W1d2o/5PzO
+tzSS48piN3E4FJoMbqjQVWFNHTKCPxtCPqxjfI+AyxI1fU7aDGpc//CfrEiDeJP02or92nIq/ax
Akkslnkn3edeOA8oLUWsCCqgd0qcuOSCQZDeWeCZFfZHXEgeH8LrJqtickAC9b7moC/xrURANWl4
S2CXMcY+vB8NaebxkAAjv8OaCPgL4sDoQL/A8De5wabCjzLxw2oXSQizT66b4PD+xI/OnTlvdm9O
E41EPATfBCONLcJcMgnb11Qxo4q43n0jylMh6mAJw+SmHjQUQavZnJGmpnuoHxXYaRGhIcmgCBho
SiUdO98fDYrE+OKjf3Cfiuf8s19G88W6rlVyRVuInC//3Xkn09XoLmKClYj29wO41RGwY08m/rgR
EgxoP2quNV2geZfdpNKlLJL2/OVnDVSfbcK/8IeeWJYjZSZMrcLkf/fg3Rb1xYth8MC0w1Sz2P50
JShm8dZbjJXXxfo6kw6bmE6HMz1FCwnEmnhvAZEy6Bt7rHEhr2eBYojoiXUiAjUu71HSWBVPAwXw
b/CRLYHMHVoTceu7CDv/FyGQItau8ZFETPY23qYvnwwzm6HsJ57JXZkKNkNnurmxoyKtdwHPBWer
Q/Ln4K4HPcZ1BRR7pFbG5+1ojwH5FJIPCiCg8jAs/9cq1WkSvkgo7YFBQjawpDUjJE8qj755h47x
tlVv+71+SK4SY9UZVCAwQtFDAX8HJN8yNHkkBqHUjiLOlfxai81pdf+71aztl33YC/qXXTPx59Ip
49x/IHHGddTbhRIwxdOUe0PXGJL3h83OZd/vymxkApcN/KXzhSRK2UJdWffZtKsRxXH+Bg3uWjCU
+dIObeNbmO9PFDh+te8oOYQWntuY7Sw+UURgs73ORmFL50qI7UrOH7/JxtUBp+5IR7SUY9gy03Y+
aCcPWJD+uwkHdaR0tXcyzWxuVRIaBl2BskTXWzIgAEluciCpBdxbqaSIL8B3vBLJ6MOoNe7WRIP1
eaRGntyCu2iqQypQ/fNktoGAwz+TfoHwBpLucZkl7Yp81zuQrEs0TSFULMGBFmm2BzevAN9kC6dM
i3qR6ws1ODZHfbb8RIRKgFeYOFqkxYASjuK5OdxsjYeuOTRG759vgZCkYw8etE2rzNcx27oqaASE
tEjGzCDSRz47Wr680xZINrEPmekdgcz69/RlHAccws5J7VDE+6EuI9xwgH6C6pnU3/lBWIG7+7uC
xq/3voidE64NB3TRuY81jZU0I8/JCDLHWqNsOCobT16aBBxHnuzEyMuWORQYVPNGlQipSwTNCtQ5
TM0Nb2SBeh+OQG9sGSWwVW4SkBBBoXtUFb//3aayRG9JLfJQzB3YWv099t8lsayx8I7qAcHbbUoX
JTkrCBhWNtx4ppm/U+KSQaoS887yLdtho3bkfJX/Z9bWlglNeSEo3BEuVSz9OBt8KQrmpv7v6DRB
gshyn4v6rFN2Ppqsc4GSeuGxDu9VKTycVzyr0t2HhcmckMQOcX5lKnSR3s08ncZHu6Cjm/P+dwDn
xXhhiG0tB/EfHdc8B1SKvjNhqSiNayUNTRUxWZ9phN0skyq6YQLi1Y8QdIIFzFqG4Ertv9Uu1+a8
AvqbjDig0ZpfUY5W0w+9ucjJG1Bp7Yjb6oQU2DjjhU61Kk0dVYJ/Kch0yWxW+BV3RHJUu+OF4Z6S
09oLpetNsWPVeoOcBEgRfchpQvRo7DU8f6xSBJ33OApMPHQZurQNjK3jU92mfRiHPEJjEa497xgu
p3Ok1wuEpp/EQstau0s/0Mi5cLFqNgLxoGlOjD78LVBM/34wUksMuqPA3E7zNqctN1youPuM8HGk
9yGUY6RvYXmUFbEVfZXrkw9k+w8LgZhKUWhgDy2Lt9bfn1jNRGewhIayFgpRZewleVIStE25YiUq
lBsk+RjnZaMOe13NRNic+P9z/xW7G3cqq5spTWgfg0PGO53/+jFeW6MDj6DGyDKMkpl85zL1mvKQ
SMl0TJ5Dvl3G++XbcVIEzXg6ZSQ+9EFV8c7zgrj76QXiatsb6KJoxJnaYN7J07fC0kJD2m0vd+eX
+z+QHXeyq8ZNDSgAym0P7V4emCcM94KhEcGrsxd2yoxmhGXpG3QNzYnAwQrcGf7IZZ/pbPliP0Bz
pyX/z4pDTuGSg70JvNLPCrDy9JHJVLwTEQK+/9rsOoU66oqe/wv8DnYVE0g4Qz7tqQhtonq//Zw8
AnEpXU1R2IiEwWIkzj2gT+cEHvvtwqyLMj5Iis1csXLjM2KXht2JMwfs0f5tW5Ni0lHJ3BqQxdTC
owaa2FbZfFzmuPNDl3alfYg+kDDaBeEYmF9mOfa/hdT3+72bUKVZDx3PRouq9MRPp5oXOTQmuzWx
2X60CaCj48PobENO66IAq9NBTC0FCOeMh5RLkP8oFibVfizBKkt3kh3BAKRZC/c7v8FOGOACjUYN
aOMsZbF1/7hdwsikdof8J4yUhFYJaogiCpkyVgvmF3CzAxd8ppGS6YaL6gx0xWSzBnjkApnmsFTv
cG/E+ffVjMJZRaypwepaYX4TwwkWRFHFUNboULS5rQDtG9BvBajyg23txZT5npyMcYEVw1kmBV/F
5erWlwx9TYjsWpPSZD5MjDAjChxmk812yI+drLwqv8pHZeqGEGVuV43vphYMKGcjMcIfpGTfN5mH
DBxNRHUdEPxmascSyw4vbNF1PGwj81RPODflan4v6+rwMTTmbO8gWP5nwzZe1BTflHQRXuGRB1sH
WabManfJhjbQb/3nQMG1Tnnlh50Ja1QHZrNjxWOr2mqWmj/dL8cUXZq94PKIyEKMhgerVX7SV1YB
yhNqOp3wY4qJmw6g5PKSlWeM1Tb/JN9kJLdiEoEm7ZTj+ZWgOykKw9V7vNnMYZ4jdlO1IMBXp2vR
ZV0FyfnwSfgKxDCp0gPry4zhxZW+E7SQYK4ao/MCyI6QD/ZeVLqciRrYQavi7PEnT3b/PsI/EgWz
oTdrbPJEQAfvkobI1Zo4LmdWKZqR4qkGuxXstJod8AcB8GsCuTi+u2bv6/EC+ZtSj3L1ACUSCYqx
6jcUhBTgygrnNqKR2HwxRAEmu8p08Co0Fzh9OvabsyaEoUavEF+zZSGfxdX1/9yfmEV6QyNMRnQX
xVjKKKYGGjXedguMOLdoA6cQDltLrlDK7JLj+2iJZXhjLWfEddJiWZHvh8eoTG1k/eervrayQM5p
MbFukix5zaY0S+r8LN26ITEnIkHAPZUpjOO0dXbVbanGak6SLwQlpkP6fD8fFF8NZDG3jo/b8I/J
DmjaAUQupWA2Pfu1If0V2OklziX/kQQdSmA9XAmOS3FlNqlcef+PH7dpTzDBzKK33f/5eyaJpQkf
h2cxaCoaVzjUQXMb5BD/pHgM5E401UJ+GnAsao/utocsv3gYVyMKMdPz0t/C/ANjWFgoFuIwKjLf
7/G2lXIz0v8M3PpjvmMRc5kKSDLoBwN2l4oJrNtGuE2ajOgS1N6POFn/gHa5QXIZiYqG9USoVOs7
Kb1eRt9jmsPf+p1xBpA09Lp/RJpezPCheipGxEh4Zt/XaPXcAm+6SOXGiFJnxGL1RvH2NTiPpP81
HdDogp39vNG5a5WBdVultHuNWZg4xuTluAoG0yHM0t6zIhEPXhBZKUEB5VtJMWSGm9BKbG7uNGaE
N0/KYTnZqpOfo7IP30mOVu1t3gMdk0X2OcU0ZOse4BV6iloKNR0leUYAMZP+nVt9O3MaSBLnOETC
K6b4Xjdf+acLDPCjiQGWnJmfat15sK+OL8WSteRcMBVoOw8Tq82w1gb32bSwqng/7pewUl9g1K7I
XTEU9YDb1Q1v79z70Pbqtjx1k/HqAcDhp8d9lrcm2Zik1E8MNWlIBaYKCjf2eoFLFlsaisJF/Axq
n3OTpVewxY2Zl8k8JchVVxtSQiktJWjRmztqXM72WygNbifjJjJv0mLIHo7yCqdszG2vVBamZesO
I/rph2Ba6JeMKP8nHOnZamOGUxQHazk1L8UHtsZRX4KBwYZmxRMTpBGNk57S0u2KyRaY64Zw6W5g
gASgqE12zR8JktTvxJ2pHZBsRMoyhDQWQ6TkvTdEa4UVoQ8ixpaHuKba2ai6obd+ZCWl7b0FbpqO
UA8W4fIIMU64UCJBWN89h5lnXfWVoBBoeJDf0xF0Q424qNv4EJGCN9HT8yvdbHCuTzPXP8xLO2DL
xucJ6ShhFdmosQzpOIiIjjU52spCTzTjkREvJJ1rZlmNu9D8bI6oSZRMOVraI4t9a20ySY7p3HWH
QA84G42rF3SyAtakhfNyGa3ZAf2HubfF86UUDFl/CVNH5QgTnVPJTddpABh0ZkXhqZa7Zt39KrBa
eP2IK0EqW6at1aEoodBPCOd0gx7W1XrTpkKER7Vgdlg04rHeHyCqWoVdFPMXnSrn8QoaQteH0uPM
DETgPuyNWXAT5gyXMF0uktf97VO9Eq/aBRr+POaYkrTbIl/ITYmlQyR2haJu189p/oCIbPPuWB1I
76kCtVnaCbcoekUE1BvAfjanax2eJmg4boLpStlAtOSKATLleYFNG0lAOPwo6PF2Stz/SAO+4+4d
3551HDBqL04+KnqtpFHk61Bo3XkA280secRxJn0OkM6qKsVVeQMoqVBCsyyMPwVLtvSpo5MuKsnN
H9sW3O/1u4CH3tqYfL/Lw1ZopQ6iTUnA3qYh7X1aflHHJTyY52IHfMUwCvbbg51dil3nrLPBDCCX
+YSzyqD351eRApn+CF0P3DhBV3edbYj2DbcyfnhVDSiYi/NyIntLIGiiG0W+2JCj59hvmylLQK5c
Mmv/2oj6pFwfO7/8XWipjUbJ2Dl3M1uvJBtmrm51TWHmcdD51qGmsF6czF+8kwPu3LriJFhT8/Jg
qAqcjRDqr8BuX0hnnO9u2nDyovTJBVnxkgPcIkNUeISuMOsmWIG9sSeu0URoAXhXIBcsRoaPSotL
MQX45nwma4aBQjxMGDMI0+GDF3Tb+1e7FapRhh2ZUGupEYaRvfjfBysTKaBzAPJy7SHpnHwH4vJC
ubR+aE6juj1v/fmVEn6JCPO9qJJvA63jxOGqVJTEAGD7q03VWF3jrEHMU3ze9IalfF5MYoiOB6DS
qQYsPUmvgW+grMTEueGQeR8QL5dY8R0uN/I9eYD5Qls4sexz3VLAArzA8QfCLi6SC53SBMik6HFa
uzmBkUYlRfJWdLfOvL3x4PxnbdJSAem45hA8tshMxfm0tAs/rskho8Gg4ZWiQY3WNcKlO7TaV/1f
/0p28LQ9ClyuZlvO6sKQfz0BvQkAwHtZKRCSG2PrHu/D2hw6FFVCsHYrUEni2LCSSbPvxZicTA20
9U0jAm2PXZrUobCYtje2ACkD7p1UdXHs2jW2XyEqPrzCyIa9DN0Uw+EKjBFrIeM3b2FzUzjLzD34
/9NpVY8a325TTWiCSM0N8J+ZA7SZcnAx5JZsax2Brl+WExBAKxYhZVY3r+GEXlGLaFN51CBQ/ZKS
Fidq2w9khP5rDvWXOd+2jPMuTCukUcIqMaM/BKlg3aeXLRFd3cs6Nao3msoPjaKR3rI8Axo3t1D9
3NNjLJQZl7eK54V5ozXY1r+VsEXunP4gHRZzjBk2KOaHSo6U+ZFKcCLsgwQBjPA9iDoEmfNW/v5T
MisoP8f4NTz4BlisDXodQ3a2LbMyxgYzZ69stWIqupZtzEyjLFmGn0AdUu1O3hJEnMIQ18iC6x6r
U/jy6Y3uYqa1lYr4DFJG/Jy0R7dXvX31JrSNhNEfXvPQ5FmPgF1orBzGtSjB2i8qkl863cNwfsxf
w1h5KF2HdCRw45S4PFDrdE2Bt9IqA139iKX3MNQUVkxvF6+uIWc91lMRWcA30leS7BhyIvedzjgS
XRH9wnmZw8JkW0L5Bybk9SE4HSAIs4KN/f6V0odBTywySmDbWIOmKL0BZDbudS1dOBeOiILAl1jX
xUUwrLnVP9p7dE7SEVJMvMJdMLdM4LRkh71DVOj+jE08SS84j+HUT56XEY61TJo72JdE5SPQSb4f
ckzbeRcbZyFvWvmiNQNMRMvKDy8CemWc/uyV3k+xumTtsBXKWA851zgEVqzb6yh6oJje49sag03j
vR+Z9XopigcF1Glcxx/FPN6SmYBoLE8uW305CDqGr6GufTdhf4HVtQHxBZd4baQ+2A6WRl7E6NYv
wcLml0k4h/eQRMxFEiij7uieLaTIPsNI8IDVMKS4xIeeTWGM6rdXJ0PBb/885qmehe+etJvX55Ya
cYpdi6UVII6wQYFCAS4XjbzdcuMrjarfwsfVyTN60sdEhv+HP/NzNdbYINJaw5wdUBSQ5a6T1lCs
i+H5dHJhCWhrl+H+34HB8+RJxHkXyhPvynYLmqCKqpa2lcBh3BqeUcxwTsxRXBj0jYysKAlkyfHW
Dw8fuCRpAWYukIaP0KoqmWlQVLUuqUmqPH7Zl9uu6krsxUf9Vr7RZ8FHtGVcf0KL75+OHzuHRX24
MgvC4j4Sf/OQq1JZa+lQv5r6Hy7cxvcuM9bzNa1Sc+N5mp1oLXFoHdUc99ZuNh3tmhlKzBPhtOkW
700kCmDcHxGM039xGqPy912vDH6YXwyWBD02jDDxLTMkXZ38/T4G7gUHRf0WjGsJ/088o+39NuzO
ooX61IszakvGjC6YHo1n2BvkcDaDgunLhlbcMg4/dAaFdkVsaXkVpp2Q7D7tTiZpgfWtsZjc5QW0
o//C60TX3gOiyKMApiQMe0Gl6UVq0V+XIq7Ia/sekqVkfJmcRw7/7LWp8+ZXwS1unbLghfFxQ6Cn
VGO4IcXd91DMl+5Q2ArstBXAQdLzPmJwpjaPjvNjNgqBD6CMmu8ZllLjaxfzIxyVLtAqwtp/Rc0n
ZwN83daTvnAG3U6ZIPctg/+HcHPpgiYWdrhdOwrH/7FeFGva6+kAnRb040ajr1R+LM9O3ggX07qU
kt6K1jcIQ1WxfBtdnIt75ro9/Mxl8iQw1P26LXCHc9Zv/Pq/ph9vpL4dXTmm7yrWahW8p2XCPkbw
aRRdQs3BmyqypqnwJYYzUPn3c7xywrB73oqNGgvdpSP19NO7OkWUxIYSRFOJ6YFfAwcDtGKGoLmt
sClU9CKDk0scfCpK5S4cGlrDiHxdZfrVSMuse3n7zgKTyfRofJEr2GL9Ckc/io+noJU/S9f/S8dl
Aj4HV5jnJ3SNSr/DGhwFMDn1ZG3FmIR6G0TJs0iJzQ/mreFvKA1FAEhgE2RB7FzuEKxzmPeIx3nn
IrFJFUpfHDRJURoY/KUwJsaxYgRFhVkH3fhq3R5x9YQX+4fVABqn1fP9d0zWnFZT0rudK/14QYlw
61Gy0Q1ZCwsWCD4SiHGD66pv4xspATRwTp1krZ9pOK5lL0B41Cn1yzs0tWd3YRmJf71qjck5SBOQ
TbbwrDYG1Tfq0Dk6o4FXHd1KwAYHkDda6I6HzrecnKU0tbnsitRcEB4kq2t8PD8XJxWe87eDhHxD
e3zG1rEbjS7eREbFq6O68WF7EMTZYWBS4/FPbIpI99dIArCdhtmBTjttBlikxAy8uqKqxKouIxtD
/5JsDNInX+acVysnwjv5GyYfogqCpeF55DTxN72g1x9TI7iWOO7vuVlxeKUWo9GdjfR3S/1vnHKw
7q8iP+b4fufvbK0fS9Z7gt5455cF28HMnCLKbIKeXITPKCUlClVZCRHbAs2+TkbD/KHLOZuj58MU
k6UOX+MgQBGPg7EpSsPxq+nGYj8I0JRtW6pBFxizzHbKhvIrSv01K45xnUXbj6xov1bKXRk5KpuG
/G3Fpt1yVl8hqyUiVzDiLqsXdIFG8wh7R2uCX8/Avi4VxJtOS6miMVC6P4Vw2zYQqllOd9/sKiEj
9GztXhdaFAc9g13h/bB5Ismd6+ymY8DBd5t//8H96JUn3lWZ+4E3Y5AX7FEbYjvoBBfHkt3HSbSq
rz38KxZ1w/M+uZV8Tq1vhW96sOJW6tPVoKQpSb9BiOHaqibJ+T0BVK2j37OY5gceDukKl3O+wqAD
wV6tm0mIFTHMtOyt+t10JEpqea+CknxbERITzAFjxxsuVMeoLSQyGEnBGtpgRgMA0KwmjqAVNaKo
//8wG63e5aKe1zSgsIgvphL2u2y68ZY9xRCxV9bLtGQbCB8Ih0FvbTreOXbMvt6ymScAVm7afup6
yTNFOhp5iED5Vy15rtE0exA0C2Ky6ThjlccaONZfcSWguHtcmUZjbMaSjZFy97i8LY7kjiXHA/Tc
GCoSAZ2cElD/WeEYE9XxL9d+5mtLeZkqkZrXFb1wWwOFisJFVOeqgUdGudSZKACPRh2kEws9RXcc
K+NIpLTKeKL2UZ+cSpQDynlJj5NJqmymJMHOLNASmXnN5t+vrm1Rzw8+OO6Ct4CxeVQo31FXdmr2
0R6sg3EDXrDEvKinhPa/6p43ILc9TbFOJI+2IWK8+qfpbmPJZucOADxjjMxYPoo69h6uSbACFNdE
2AKD2FwTHPqJJf0F1o7SQtMvmG4FmwekmGmzmgOWy2jcLYdxk9CnYeDqnu1i3J8WzJx3MzmEFi+c
QIfgoZXwxTambjG/NWPMrdzKZSD7k+pLGdPBIgM6l5FzHI5J4OAGXspRJN8OZC87Tm0M2Z0kh+GM
ctxDGpYUX7RziK6rqobXTMk6ui3aqHqawobe6BeUn/cc3QmQJQrOVhdj+0OSBtCnexdMw9Mm4myC
f6Z5qI3zjdNwvZsb2M/sAK+AqAYDCtz2eWjzA3Sb9CPtoeUnn6+ivPUx0nBq6k1FHBCDeDIPHhhi
hHUFYi0v192G2nBXNUs7b7SCnsvw+wmEKB4dfbBf4AITXPBh/xAkZY/8TxuSNfGFezapRHXcmv+5
wC4a4+KDmy3JycR2rbpEq/B3U5+NFdEghLk/n+lkPxFddVChnui2dDZFM89ovbS/RczOk2kZnV8o
BqzGSiaJnXJrFB3otwGezV5264J9TxVCU1ADHRZl/wMY7V9DX6oKLBqp4PDedDhscFbsc1F5xcZd
DeDruAn3ic7+geUEOXY1Vstdj+5W0D9lnpQKCU35j8Nl1EYY7RP5ZaKA9tJwdw1mIXok1kZLCx5Z
NSolPLSzBclmwyfqf45m/nrsC4b5rvSsa8QITbSF9jAXYsJROz3VhytW1xSRtvcaywVL2p4x7W2P
b+Cq2YpV9m83ZIzWiaQPKIkgTJ9oqkKg64G3M3OJVoSFgD8SktlVMb1rJmZ4+qRR++m8eThzXK/P
TPlSoZYFOxRcBl6b29K89pCarYL/2g+b8gSJfO8i1/ZS+fPTmUMEW91RaHwr4cdCVOWTQV2AsZTD
I07nd0F4bUUnNOfwGcYMoqBOzY+Bj+iqssEAWpnLIgvlH67irSEUbiTd4z+ytie6bEujXuca4nFV
IzELW4lo3MFOjPet3gPMurfZvSI3odoX2s1VsuRnrZW9lz/cFA7p3M8VrxIdJI6vdfXyGlVY96JD
esltaTT++REQG0VQrRrqLPi+e0/YFYfm6Qo8MeelitpHlCexFc96NfGHEcPhc3QVHqE2nk+RmRzg
SM+jxPZnvGWb/oZclVVKbpE75CAkwOLoKoKfLi1gMwKg4R5uNqGO7WevMdKHMp9jNFnaXCfsd/nm
+EPOgmm2x1WCdvZDhMbB5GGQy2rZtvylqGEPJpZWgppZr2bLuyPgzOQHgOO8erO5ELAdpHPzjw7A
VL3DQKBUsWaP/Sf6CKtU0kJO8j//2UUeRX315e6JyqYNGBDNbGpoW72Ufy/EIm9dqjEJnrJVqals
XChcFGMJfPxBxSMAek+5JKnQ2s8omByexF9SBWxGpgteZrnapyXVARfKPpmEVOA4M7AJDUE4OLIu
e5c297I7PcvuCa19IFzw768eQgnn8pElskdqHZSPJE0Yi8NRLLXW2nqD5xcAeCVxPg7AnJFwlCJH
XX2Il5pIVGDgmTNyY9+a+8VdH/lvXKjh9sEcGCBuz817Mws+Kj7k9PYvFZZZJMnL5/kAI3HCS04e
RZFI7Oywpgq3i3AL0F9b30A7CcjgjpNDyj9API5m1mkXeyA4/b3qv2h3jBeWfdCLSjGzchb0fUFM
mnZFklw0DGClwzgH5y5TexB/EX7JS3TkdmMXYj2/UTL2S9HwIaC8C7IDryIoUBk2zwOGqVlmzhe2
UAI9hEzuvY2OXie7+zpk8gk88wdIPv6kH2sR3zCdGydp1wIxTDOfjEzg4VIo5QfWA5sfOQuAL297
u4/VvHaO/0e44sCtMzyXxjwguFUfO5BjzrdhUFv5Ii38ms9PRAjm1epPfREeE5Bi6yNk5s6GyoBA
Q1Haz5fjJLZ5SDgdtQxNg2wCnI8Gk3x4+ijcvu54RysAJaVzHcwHDUwOhQiwNZP56JqSek59e93q
NZEqiUGhriE1XHE8jBTQJNA3fy4ietluXe7x4VMj8nb6Q5QmvSJV9663rjEDfkVRtS2v83AE9Wp1
FgLzt56m+5hijuEc8UtTTymivw1f6aNU9WNhlP1ktUZLYMUgUjKW+GEiOjThB6m5s1s5rCYjqUGk
r5bmkCVniUYdxmwVbyW4zxm0Fsyn8iOWbkdBVV9hmRKSGDqsAF8JkI5qvvY8r++tNcjnFgRJBnVT
HFdfxq/ik/RQ5Tvhkfv2XJE5K/Nulb75AXQ9yfl0CNWbdxrpf7Jnyq5kASBuAvj/Yy1EygF8f5Wa
0aEckqe5rOsIseLvwdLsNvBHHTP0egQjic7QqitXz3nlVj/PQ7mYwB74QrV8PGOSwl0U75b5JSX6
BO3qd8lLrrGr8Q4nh+psyZKhzuAa1YKvMguw6F9N+PAg2q1wrx96Y8ABITa3/G6pt3gCvaUI4M9d
c2Cv8+UxYvrr27jGL41qTeSn3IubQVQEYRXcOMenPAMHlaKgnqU6G9VpHiX6fpXhSX7m/KCWBTFz
v8LlIiDMeUfv8SNPnyXoXU0iEvdta2Zw3PD7MxyuBbFRx95uWghvYrArqhKzVdcVoeLxRZt0iD9M
e4o5axou2ipj8NYH0LPPhd+Oarmn721t32FjO8IsRwm2irjkI4pnp4/7ZYvSy0OH657YXqBSNOWZ
IZVZQGIvVqv+310Vmrcv8TO6HTyI+H9pM0A6Mx98FSMcbofNSG5bM+e80Pi3MZuc64T51dFVnti2
Tkbg/n3vswBAGEU25/gWg/eKmwnXmaxgHMVkJYPn4ktOcxFjpe9M/zXBmSxgu11xrj2xg1kDU1X2
N1M58Ej6VxzevCblCu5CYLU+xszE+dK5z1DQjOCKiXmlYFDZFiqKCKp2dIT8B3hgzUlM/WRCofXM
dij23uWkLbP1nRprLwe32Ov2acJwPPXHit1tmMpNIVAC0cnsFmNrWQqiX9UpXVKUn+FahY2ypqaT
81IDe517Z4wu3KkvB4Pvs+dHqTnnpHp33nMLUM8O104nhduG7HmKiRMOTX2OXG8t5j7Cb4ezKPfA
RlQ/DMFIp+N2R6/Iq5w0Nj+ECMfpScy9rPKC2W70NCs3R1Lp/WLoLbPS8Z45GPxSyJJbk0dVxrbV
++UfHuOJ0Y01CBQ+8M3lRnmUTZtRJzjYLHrkDzFLxUQwtjB8sIi1QJpSC290bpLENfqtxJ15YoSx
yY13ZQ4TPZfjsFYPQIqipUhUiPtzQxKvaRgAWCIyXg8gdCbXjGK5TMuPi/xCUa3wtWCcKCZtDJEB
+4HQG6EUI70f7YEVc9ESImpdoGxh/pMJhM7UF62Nm3tWlfLTWiI2KrPr3G8nAY4fxGQ5A9HajS0f
j+qcMqhVLF9P372STEaICvGsnJyGdI7sw2tQOlsslmG2hk4nAIx5A1PlxryhrUm6ALKsDKHpI2M2
eeBW3DSommZEyHRYGjSdPwACJa6b7eP7QdRVd18h0oK66BVGB3Pgtro2nnSTCk0oX/qGbB1fxerU
SjpRVHHfgpHJTEUigdkMDMpkB6qubYp3zS6oYIucJSilkFn58HZQO4y4PR5SCZF3VU9CFMe/WJew
YPiZ7nZliktTvyl/P9Ms968Z3pvkhfz1wiSd4aSb8p7cL/jOkpUIx9xw7D3qOIm0oN+MnIIqXeyQ
E+K1EmHlbkhfkxH5oIbeTXjfyDRNXKb9bN4AsQyB8kR3YNeeBRmoB3fYHdDfw3Fd6jpoRGjI4XJm
Xz5dWXbDxwdBmGF0R0OczOmzl2iaumXx9IwTlzK/xryRltTC9jvV39ap1ZiC/9WFNAyOP7Nk0G60
0uYfqJGHlB7EGXxCZ2eu9Pz9HVHT87C+tqoj9f9xZEQtbrs2tN49sCdGUa3+jlwP3rLt1xTtW6wI
EAbFrpWGzMstwsmYm/qD5emjjM5oSdyg4W95f+5Tmhm3u4dwZgLPAwPJlGgLcoiyFNF9L0wHSGRI
LPataXZh8Uk0m6tGPSl7TkBU6ii6cnWdRb+R8yG9iCjq0AQyhGmbJgmUdtgpLkHmdVwmgpK5vKmU
HfaJl1bLCxvYbl2S2dqsLb22+3rF/+VM2L65ReNqC8jYbd26Y2wVwVzM0F5A8BPNvH1k4fz/LmZY
axLCGQipFsDBImjWEQjoJzDDRoXOUe5cPeO/EZAQFB+Q//4A6tu0eJXSpWSSve8G5OrGrq36cu4E
IIngDNqQDlCN6ypenNEkPdhshTUGv5BSa8O8zSZK5nY+hnqB8c5/PhXyfJO/YrCUUaYfmhRw/bMX
K0qoCXqHNsWOWYTmbYLnf/N1nZR+nCLnCCID7OdltNy1tnsOBxoxivPnmv6VKpSFmeEX3HSgGrqd
YNLAQijyGuRIUXrXO4PpadOFdh++0bBfAHzyImD19sPQzRT5GVmkXYjmi44IyLbGYsyxVlPiCx8o
LNniHdKjWhfQUKytLWX7S7BM+MKU9+C8wnOmvpqmCoDFtL+IPUnFQthDR0WSyJf6quTFHAl+ZPiB
fuiYnoqYWQcpyIgZsyhiyweEJhAMn2KG8NMRJVi5k4YrKP/5Am1upEl02RAeX8ef5QZlge4xmHW8
YlsdwJLWfrkLIZEN8UoAIEtBXRlsvxnp8vK7CkNnFJgaT7fLCy4LBHZ2nbWG2RfUhe196wMgFaaU
ENCx78VWMYlUZ9khM7EBnxpTjBqQdQrENzEkNfVWZpQpBm0idwHo9jNM2XuV3XagazjJd+jU2hM4
jIv2ypf2nw/om1CdlEFogb+rECZDeBMUeWT2IGKr2yDEvoOMg3f6phnCaQdLt7/GBIJ5aW2kvdKs
G86UFmFwTEG1Y1BgVKnoyHG3OxgDa22Rs4zVamZQYtmob28FnryJwmpzyKsRaMCOvt9mqcIYeTSl
Qtoetyd0SFo9LBbvz94kHfgf37aYpYB8BUuqRigajBEKwFm/+4nDk8LzjJ7jocKSVECG6Gfk1TlM
rq8jjbLR5rY4cZ5QtzsZyUlwywE0UpnRutayaeDn7MIx62iH7wpgv2uCM3Ulj8BJQdT3K0HgeHvE
DoQ1fs0yZ+RvvmflCAGZjHqB+5savcC4WBwjKdAvi3MDZrqUrIS/u8W/Po6WUxF7TrYFG87cTkXM
K1IMa0rUu2kLMxT+exSr0FNwsi69TwkMPaK4h7x0UF+uGRZRgtzP8x0MZSCslmOfb26ei8MmRY2q
XZHiTdrK+JVD9EedfENI+Q9zc0hrgaTo3NRf27vNU8ZUEApsGTSJOUbLW+jcZDVAsKEXXInkuxcz
AGpwaxnRJ0kNjsDZZchW7jjJJI8OSerhcGbUFUeBdCBDUCcIMGmGPTfdgltjZX8P+bM4xipd7a2y
2hYYMtVbpxBjpyHxBLIqk4ToDBfwz+MR3TC8Yftn34qEyaLbaHnigItjKRCjDB/yEDJd8qw+rsvc
i+Qbng1bTWpcJstn3OnEP77mWZ47zC8/UmLMJjfC40VBNxlH4yBKriCIhQOCLbNKO0hVDkibSny/
En/2UyEbzbiqWjv29YSa18Y+iv6WgyaQb9bCIhNhJErWdeh33UW86tnRBZgoOMohcFFIX0p/jZt6
eaLl5qHMHdQmgwsOIOBebX2gtIKaAPFBRYEebLkeAWjMTx626QbG5njkB1bqUwHo+Nafbd4sBw+j
UcLKNJpJR/AbbFwkHqw3nBv5f06zLTRrFe3tLlcexFGqNHEstU5hMxCnmLbuPDm1vNnqxihP+rmt
neIFUBO2I+hym81AswSpRxQpZ+5cpknTbfLwXmC7Q872Tr/SSeQtIKGu1prDPQ/Uhzotbc8qDE7j
J2J/zYza4wepX37S2podyJbeG9DA2313X5dVk8sNHe5zCwC3AuElMDiB+uRstpN5ENtbU0XeXG7k
S1H9Kko8u81p/73xyu6MeT2EuSzgDB6zPrnMZvfG0RfbK28iCDXO0177DiPsA67Zi0rcjdXTZ3zr
Upxum0U31TQrxTMxiWSehFMSjpBpWAEUbCLYs75seGbO8osjdUcmTHcUlsRWBEfjY81R5OefsbSP
mHi+L6J8M/7CL0kVVAX55A4mueeCh5CPbNd/sBtmTtu2KHzpCZVHQf3zLLrWGxGKVLaE1Cfl8cQn
qQcKlwbp7JyLqKbMAtWO6pQIXy7fGF7iaCOEN6AFAz29F9j4dgGTv/0Bkv5v+LRXsq9xe4gvq70L
jgLzH2a8d8DeYdopnYUZEwR3kPbcs+7kKwwl5jyBzX60O1ykJIs2MdizlawNp/c=
`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00550.vhd
|
1
|
3171
|
-- NEED RESULT: ARCH00550: Constant declarations - composite globally static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00550
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.1 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00550)
-- ENT00550_Test_Bench(ARCH00550_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00550 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
constant co_bit_vector_1 : bit_vector
:= c_st_bit_vector_1 ;
constant co_string_1 : string
:= c_st_string_1 ;
constant co_t_rec1_1 : t_rec1
:= c_st_rec1_1 ;
constant co_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
constant co_t_rec2_1 : t_rec2
:= c_st_rec2_1 ;
constant co_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
constant co_t_rec3_1 : t_rec3
:= c_st_rec3_1 ;
constant co_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
constant co_t_arr1_1 : t_arr1
:= c_st_arr1_1 ;
constant co_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
constant co_t_arr2_1 : t_arr2
:= c_st_arr2_1 ;
constant co_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
constant co_t_arr3_1 : t_arr3
:= c_st_arr3_1 ;
constant co_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
begin
correct := correct and co_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and co_string_1 = c_st_string_1 ;
correct := correct and co_t_rec1_1 = c_t_rec1_1 ;
correct := correct and co_st_rec1_1 = c_st_rec1_1 ;
correct := correct and co_t_rec2_1 = c_t_rec2_1 ;
correct := correct and co_st_rec2_1 = c_st_rec2_1 ;
correct := correct and co_t_rec3_1 = c_t_rec3_1 ;
correct := correct and co_st_rec3_1 = c_st_rec3_1 ;
correct := correct and co_t_arr1_1 = c_t_arr1_1 ;
correct := correct and co_st_arr1_1 = c_st_arr1_1 ;
correct := correct and co_t_arr2_1 = c_t_arr2_1 ;
correct := correct and co_st_arr2_1 = c_st_arr2_1 ;
correct := correct and co_t_arr3_1 = c_t_arr3_1 ;
correct := correct and co_st_arr3_1 = c_st_arr3_1 ;
test_report ( "ARCH00550" ,
"Constant declarations - composite globally static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00550 ;
--
entity ENT00550_Test_Bench is
end ENT00550_Test_Bench ;
--
architecture ARCH00550_Test_Bench of ENT00550_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00550 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00550_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00253.vhd
|
1
|
3182
|
-- NEED RESULT: ENT00253: Open scalar linkage ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00253
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00253(ARCH00253)
-- ENT00253_Test_Bench(ARCH00253_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00253 is
port (
i_boolean_1, i_boolean_2 : linkage boolean
;
i_bit_1, i_bit_2 : linkage bit
;
i_severity_level_1, i_severity_level_2 : linkage severity_level
;
i_character_1, i_character_2 : linkage character
;
i_t_enum1_1, i_t_enum1_2 : linkage t_enum1
;
i_st_enum1_1, i_st_enum1_2 : linkage st_enum1
;
i_integer_1, i_integer_2 : linkage integer
;
i_t_int1_1, i_t_int1_2 : linkage t_int1
;
i_st_int1_1, i_st_int1_2 : linkage st_int1
;
i_time_1, i_time_2 : linkage time
;
i_t_phys1_1, i_t_phys1_2 : linkage t_phys1
;
i_st_phys1_1, i_st_phys1_2 : linkage st_phys1
;
i_real_1, i_real_2 : linkage real
;
i_t_real1_1, i_t_real1_2 : linkage t_real1
;
i_st_real1_1, i_st_real1_2 : linkage st_real1
) ;
begin
end ENT00253 ;
--
architecture ARCH00253 of ENT00253 is
begin
process
variable correct : boolean := true ;
begin
test_report ( "ENT00253" ,
"Open scalar linkage ports with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00253 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00253_Test_Bench is
end ENT00253_Test_Bench ;
--
architecture ARCH00253_Test_Bench of ENT00253_Test_Bench is
begin
L1:
block
--
signal toggle : switch ;
--
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00253 ( ARCH00253 )
port map (
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open
) ;
--
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00253_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_extdepth_low_latency.vhd
|
9
|
37992
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
MZXEstTSOPKn8d5gf+3b10LFSw1L9kvafhezpuljrAF/7ghdUav62CewvwgRX4SemyQaR291yKZu
bGSff5WMXg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kLYSw7WMBCamT+m4atNFnoIZxka3g3JtON0cEggFoebXF71E9cyWqze2b5I3JNud2dq0mGJH86Cd
tM81uqf2Xg9WhxjI6FuBts9Vex6Dv6Nj04kCYSbuxNDshz7+gd5ia/7qUkXzcA4guNI5WUF1UBV6
vDQhVHruydJ1Ww/FftE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
lMrOCGyxZ/Fxxm6s9SRkkqLKs/uI+at6ayAxg/a9ANgJfEz/Zb4jsgW4Xt69KeT3jWnYXdV6GL0O
jm2lG3IkYft69rEThC+KNJd6SQCFL1T3ZYzv/OA0eNyOCL0xoNpv5H8+4CBzH8WTy+/ggroV26dR
hQoPf+zy21Zc8/t3QBPXnKLuBdUSREEg+EuSQd0FBzePur8B0T6IZAmI6EvX+dL0R/TZucTJyiX2
BTX6CcjyTSEuH7bbLRjv9rLpnNMdGbH6kj2fBldtAH9Gk9q7MchvRLlwmD+ZzXbSr+2L+Ep90L91
mZShWV7rMZzb3Dhq/4hW/q78PrJ+r6ohca3tjQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WAKJ9pPjicuiVZ/fl+UB5nOkuvOQJAs9LrqbFlgs8XDnUZpCaLb9BpTjQQ7lcfETin0krqrmPbEL
Wuu6HfE8W0t30hwzR9t4xMkSGvKZ8OHZfnNuw3XYNLdqIpYQMH5RkOkP7LxnZa+4iClFwjRZiY5q
qYSdY8Ga52Wi5cC2Hbo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QjKrVi7WlHib6bKGT0OGTYs84rdmdleh6oyJXreK+5fkpjerLYbeEOPTjafziaS2WrFtudblMdrM
E/LNohWFMg6HI5Be26qj8xWEs0q0AC8WTaKp6gJqvbS6/F7+AKuVdcIPelTrXKZOdyuOFLF64ju3
ybXKkvB/gCzTX5yFRChHQ+LRxfg2IkNNBF5JGaz+YyvIs2ar2kXSbUjGTl0tOC3QQ0oOO/oHlU7y
bZvJ/NYdMJGcDDpZOufURSkyS0wkF3aAOdsXQRalncGVFQfbyohwEc4ZKnhd4xUEvAdlWzeSxdvO
1KZnNrgRbhhqLJkrU6oEQC+8G6eTCrAD3PT+hw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26384)
`protect data_block
T5hEEpYZDyI6IFna9r87axT1ja05gx9M51V3cKofAcPT3uPoqwWN9CdcaQ2czOfPxeq+BwxpiZmk
5ouxPXHBQi1Ey8mKyAPBofva6jhS6BEN7y8ZjdjeMWhcHepRGx5Z8s/XKWl+D6mtihVlJ7U0D+5S
g/s6UKhwUHFsJTM45xxzVXqVWq9pOsioMGIlv7jk4HCnZjiPHFdhSbI+jbgKRnfbJHaiP8ega6VB
A9DBqqZmM3rkg0V3MC0j6bJ4lyA/NCna8zJibq7G+p9HZ+7/nO/HvZNJp3h3L8u5JdSWbhOKwXiJ
UjoiS5BhuPxd7kv859ById04Ss18OJp5Nd+Q/BOV0USYrelqdZ2XMZoMzhRTVJDdEhDPovAr2D7f
zYYUEhvx/z5e1GqnTTL4bhD7xRYamBOyhCRFs35KwoemFk2UvrzJBqSWc4ceI5DQaozOXcDd/41u
cqRN7WcB3Nt6hpfyGS9/2vjd+rZLP5xUp7muWZx8ITdmar5rQDwL/nfVCAD1VPvnO3LRVDchbTsc
TASUTRzkMqPHNyU+LLk+cAvkrqK7o4W0enGAjncaoOkg2Q3qcy/E9slq7cEnQ88iXem7MTbi2WfN
y0Vsfs4A6Mec/kxKQfPQgD733dyTE+EsKtpNc/ZlZT6uR5vPWlc4Ysbnd+DaZbHPhmaWWFzCyNLo
8vOMMdtKOEam7sp8E/HjQjQZXhl6AKmG2gZscHP7EuAHu1G3HxszgkGRqljaAlXvDF0oyyINW9BX
gG7mg3KtacZgaQHuXQp974lkdaD5QeeZpYxBqteY9YlBX9wSoAXTSgBbb+2suwIX/vleCcMXTrXs
ZYPde8h8uwlKjdCfW0ApAWU2Wc9rVDQdjbtbIBULqiGcqnLkhD47Ik513wH1Oaxez9Vz2yCYFCHj
g5JCu0Qc0fVax+h1F81XpTXoZxsL2rJM/hnAsI7LYzeCDmaAK5iG7DdHEISYd/6FVksuY+ZU6qKu
9TtG3+pbC3BfZvsutgEDDBjaiseiTwFZ6MxgoJtNPKef1n8ocSvOpZsS2JPsI6JduIPnmf0h1N9w
9EiRAQlwh1ME2uwavEM1T/G+1ZDTOKfiw/IgjSt6hMZQD1y0ndwJopGjGQIL1adpcTGRD6bnPmpI
XCsp9B5BL7gVeJ3VweYirBxI339wmAW87arvKFYuDbPoMZ1bYjzi701sy5Knh/eyFmG0qi1YkPxB
sNYCjFgT1Dw0U7Y70siSm5UjZN7Sq6gS8+u9lM5meS7r9yIm/0xp5EwFktG7E7KTistYgS4XbDyE
6k3+TwthfHq/bUaHZxwz+ViWzcxNtyfGZ17YstLpJcjMi3pwi907NMtP3/n3R+oxRrBcF+VBzkbi
GCR9KhdfWcHsIyNrCEzS1dK6tA5pUmPnehZD6fYKgd7ZuBEh2oYsWStMJl/y3A7fq8wRPEEy4f6C
fY5EFhhCfsOH3MboTDCeb3gONwjq/xJQzpRgBw2QZ66MGiHW2SP9GWcmrc7VAHkH/7yAZHPCEHEH
TtAO/8GHbfmbN2FTM9zJN2NG8UNwknfki/ArWh8TZ6rS4hXWLPkoHO/WzwaPZSzBWCJd+4sr+4PQ
Tpj0I/JhYtPQY/hR3IolPXCCTH3TNta/LQJ6QPROeNdeiU8WBkZ/kqa4FU1ovK11H4lhtKRVLjlV
SdlMZuYZameh9hqvLb1HDRBHWufGgq2q4R/CWLIVxXjhr/fSSwCrxuwQHSVdvHkwK6WZR+QkPL5p
He+1RInYYXprQnF5lDGwom4K2qOWAXqJ4m18pEvGgF73Hte2R1dY6C8lhMtNsrLK3XMv9WJomptQ
OYkOcVz2NiGEpZwLuofg7aCMDtBDnYyBjMh0st+00KjGKy8bR9SvTBElyn472MxM/Dv1s4CFZpwp
unay1ixJt0HNNMlktvtz4/BY8hr7L5wD1Dp8HUSBvFsFchM+/0d1ogoNffdlDkfKYTHKJiXy24BP
aP2UxlrjGpCbxBbwGdp9nang/Wzgg9UMnWH2c/hBAH5D+lNYO8P6R6EAJwsZsaUu9CI7PVe4HHJM
rXvTdgi26gjn1kueXwCweltZAlIqRWuuPgOVKm1tyKDS9qYLIosgrCptaWbx057DrW93TbHa5vfu
dcPC/7883B+SYy/VO77EpVEiElpNTPLwyPFxFNMx8cqMuJtPS1iDBxYDNSGmP5bXO/rC9DsCUzST
BaEks/moElYWK0tFNYiGmv/s3/rLc8FfEe6vPnKhBahOHwkkJTqjS1XsiFPSPPRpxsrRc7m3A8zW
km8H9Hw9rxismtu05K8dl+ZfEoe8N/bI9pNjd/FJlXnTIm0x7n4anMKTd7fFYe2EN4DlsLOtnzbE
bc/S7dLmq84E8Umej8bBXTim1fCKQ/CmofscKeg6nmR6D9VGDFILzyzuYpcgl/Nd2NFmxXs1c2my
FgOlkgOj0mOeRNDhQ7WsSGFmC+EV2TwLY3Yl3UOd68AkM1oCiUoEdkqGvokcLrODqGcHz5KVMX8Z
YcRkBHKdRLKUKINPpWd6ux8lFsbSzIVpw+5JGa1UBoUPvye+9242T1SVd+UHgskmL670+KARvLIu
4d0WP0waZaezscgGa+Nl8BYg6lz7sb6jGJC9T/DPck8pdUqesi7Iw3iLfsCMN2ve+e+tKQfB/KqY
+ZjvwC1WqozGAdq6hvAhFrMDr2YQztDQZBBG/4DDNTCuNHtELBqLIUbyP5b4ciEBSQfa/cuSbDeq
ByY8cCxb4iH2poCBeSN0+f0/112jeUn+EZLnSqwkaUz4Hs/dqtFjcgR3kRHMYpkszvP9mRPm0Pnt
WhUS1Qf+JXVqS6hX9oWD5weumsalaYiiKSoVMEwAZWVHIyf5SSlANdBGe9QCozlauOmWElsqObcC
xYSsSj+HlMrGNehmm0GxdJeCSWsXjNFvuquw/6eNbf9o/lzitr7j0aAMrA7S6JPVMqD2hT2l453w
R+d2YMOkwDxLliizqI8fR+WxN7LK49baR7t77hgBcYaq+VOOI02qj/xfvPQy49R+IGJ6fNolI7HT
cXFSCpfqP30mnJZIw5dUCWDsR0Sa22pAUTbHGHu1BvfDNtoS+CmGxQazivicMUjfihxFujx08lIZ
bMTwkppsBdxJ4a88/jY/o/2lezlLESOWOZ7H9/+9y0hTs3JUhXuEpmd8GrM7y4uCMEFyZNzOHkHi
E+tG2dHWY+nMsV0qep6mxbhKTqsufSg5F7cTebDe/r7ZacSD+QXHbI//LOZhf4N4BxwBvbRRaeOJ
ewxeulT8DH4OU2qLPfUe9U5tSIFFtRCWIwuLI8SsXz3K+32tofkyWKZh3UndsClklFfxGqu4EFMh
SSZew+ZpJTSPmRVVlI52sXe1rpZAF1uuddWv7Vc1TOAMkZzz9IZV9jjGOlKZBH3gO5onUy6NzWn/
1W1jU6pDUO51/dn7/MQ6+aCWI+LZNxcwb7rYTGX7bkEuPdRDpUDuVe+Uzl8XQYZBLsTRVVx0qzhP
HRNMqRwRv6QQNCCawvyj9abE5vv73yBNaT48UzmPLOU/52z5wbLQbQ5d1yCtxkC+OzuSezq+H+Sx
hcDAW3lbKUPWKn8Mz2qkOBX/u8VRVBzEVa/2heqK/aFB1DvM8b9rIfkHBRSetLDzQi7Cmh6+e27x
4lNCJLFShTI+7Gc852xQRp5v/WKJ1+ZPKWPUsUVjpcB0pFKYZeKXqgcIqdjLBCCjlH0PaAoK0Pio
qV+rzcwmSwRzNEF4isVx0+zWxu1mJM8fYwl/J+FkVqQxaRfYsDFdrBMsdjhzKOiuk7faYXdPEUb5
neE+0en5dOyDSwj455qkqc9ni+Q6LZFALTceR6F/plw57riH54VmkOSovj0ZSUcczKqWbRsjxqpO
b+0WAbI9W77q7uFA9F4X8D39MOxHoWYkgEIzlnbohFc3QpD1Rb4AigtnPbIQta/5voZhnAy3ctfM
+M7qSczGLY0I/3hW2jUKt+iWzYqauYNXgQ/lss96TvYQz3CIAFqOhi0L950Gkmp/zYZg7hbR34yJ
EIZF/o3soFLte7NMwW2cfJx+EK5agx+N/LIL8IzWTY4vi+7w2bgdMpUcl3ioQEa4OijO34j/IlwK
hYhsrOF3oWPGVuLtwk6lf2inUubTrfTIOgtzA6gAJDSQpoX3VlEKOuC8iyeW3kRDPVeIJrhuo7um
CfK9F8tYdJZ8Tr+qYppzfyW6VDb7QPSaZViRjz9dhU/yALfTB5RVs35jnCyUDIVXsnCCUQgOFmBi
vRq5M/5WQsMwVRn+XqcUG0/7znTcT7ERtrZ0CeZor5wCoBn1yn2+VFjOJlyxbs7n1hqirBQg/Qyv
k/xBGyJasYJ9FllH1498v8wcXHLptn3oppa4jXKT0Uc7XkarG8Q8nTu2t9vrHZENha1lk+Gwg7hv
yRzvsfJF9gcdwKp6aFqoaZqh3YFFTep6rFSLzm6MyddT3MjaPtJdmQ8rOPR46mEDnrKBl8hzmebJ
ufXxiScvKN+npusLE29PqGBUpGoY3LQe3ZTIC8WvWGa5KI3h4GBiVC+E+pJlnDxLpV5RFvTRQlki
Vn6n6oRt4BKwPOFR+DMuJ1HTNMN5ZLx0aUn6HLTkXYTycj17qBi+1Z2w2W7MeLx7QcuAz367h/GF
Xe3C6yGCC72KJi6xy4411yXl7qU2nI/f2WFtkwXguCtLrJlrCEKkj7hYrGkl/UniBJSSqpMZHKwM
r3A7K5tJRH0h6wZ7cpY9jgZYwAtW6GqI+totO+1xi0kWPnc1OZuJMTTOsSD3Sy7EguYlM5PJsSHX
OKS4vr5aXwTOFNByMWCI4uEKuUhn51kQjP9h5GQVJ2YNN5zUVFkup5ixW+KvMufhsyvfuuYLG20H
uTkMdX/upXmzFDxxQPO0JIDKIzDHXC4Go5ZCvbU3RqLHFSBo3vVwHpFlfIaFDELpZFz25WSk1quj
TZDHqJvTBIs93D1c6+p+ROD2DDYRp/ijLsCyVcx+4VNVoh+HnlS8DdQCsac5ZXG9WzKa4RTKWagr
SZnZNiA5rkSDri2maWv3iWapcZRB7tQ4AHy3XTZzxV4KfPET5UItLXM8GNCTEwyEPX+Y6r5pH5Rx
IZdIvgJ4UB7lZfCqkq973SIPOARRcN45IZw/sEakS8oiXSZGqwO0nAUBsuPC3kafLf9z6vpPh79D
rrJ1atqFWHLGMwk1zYzhsHwyR9KHr7D975dsrr9IFzu41MhcPGxWr+ejUBSG9nv3ayzaZNgIo6um
iZofhPYF4NgJdgqmR0XBob9TrLKhDCL7Xao476A3izeW/7NR3yKT0Ky6Rdtq2/kJCqx5Bv1ZLZ8P
rVzrNmGJZ8lhZOQ8UvEGgvzT8WLLzqOq6zSUkFMiCbRgY9GtgOH5mq4mGpTAPUa98Gi66HtkV52Y
p0lKs+BYbRBEpK9uPvvdIGL0HrRFpVYGUahqovOfvfxk3DCmJM90hnVd8YW9/ab6ZfffTlkyIHMt
CfVK1ZO92uN2lADN4MzDxdh7bGkiIvuQb+KCusu5q5M2YU8qnvUzvx/UW898hKgUJIpzKnI6P6yK
TFEXYQRSU9n4nX5pL/tWxhrKAwxqglfLCMbuj1+JT41FiKXkiaLnN9mBoXwAb2cAeEYhaM0C6f2/
FxqZagopTAC7M5XRhi2jh8URFsSpICLmwhWPGdlEDMzA+42e/h/GnXNXix1zqgUFLPWH6Lx9gjlM
8rJm4tQvCFJWsT4Mvp3ytkxxWq7sL3JzcavWC4Zd5cCtDnnhHaTmjIObACZwupWxbbruKpkq92xZ
bHR+wzhHYO07aG869hCKxlxlVGxr7fdcbU8KlD9WS+ojFU2o7bSeDSSlYuLjURJdzDkwLQEMHkAC
NxM8vr5NOKA65onfAQFqbJ+5xpZuW7srQahIHUujzluIf9WUKRV5Flq+Yrx3coXuGivsUFxw374E
crcAXUp55gWs26NAk21gjCi0Rz6zVgDloAAgv5zKcmP34QwcMUL44m36DfYCPx1N0E+fhhPuKiLY
NpKQDFS94XuOanieJiktbqPCWAhd7T23lHtZ1ZWad2JsKmEkniCUXS0gPWOzXZA1LYtZechjj8sd
3hidnQVfr8sjTbrU5XTtzrbB9+EmPu2AJk3An0t/YnH22l83qq7LvrMtB7nz/aWbyo57NJ8vhQqJ
5rkXf5lfs9DEBuK+fRBwJ0uXXNxBzwgNY4KEHp0NqENhrWCV3suDZojJr2IfsoX+kHiYuc4pkSqu
w2s9EArUY4y9rrItgi6qNWP8BPWt3ssqJyhkHyGclybRN4fVVkTEObDoWx/DKjCvjXSqzXELIRv+
5OR2DO2OGG50YJwh9NydXLH1G01d/wNJIB4IQ0iON/RAQ3g7RHrzPZY0uSdPBGkKmlbt2/MPJG9F
II3ZgSrurKW/SswqRzYZTgvb7DrwFc5gGflD3Yzc0qHROdpzx5pW+CISud5ytWV/59Rv7eAp9QD2
KCNGP1VBcoUHhFlczEKvdAtm9vtK6ulS4kdBFPRISCK1sSXj0BJzE4TS5+1luqMz/B6xdMHZ01zB
t6rO51hMyYRRvalJKWcTWsSPB+l5NutnV3TLGyMu3maztgrWdl5aXX0pYwQO5LSxg6oHXEovLRmL
QUHXd6I0mK5hfFTvRgJklGID24UAdphp8R4fzRgBm8fEwBezAXVgNsRHoF5eiOF+PnNXScT5DBdg
Wm7J72IJ8iP+PVte944b4Q4MoizieN8eh/Yn9PJHdMGMPuNI3V+W9N2lCRNpIqWGrQheWZmlTrQc
mywcVfdm4KBLrfP6cCmi3HBs6VbuWAVNfvuG2dFCZZ+fycqPoBF+ZtSDYNryDM5rPYzz5ELdQaBV
0EC6f55/e3yrRlQOzgqkVXvfKldfU7lqVx8h7U2TTz2yzBhJrjq5X4DyiZiriXZMI5qYekCdMdYM
bieZjz3Pl4tZzv6JcjNYxOBBc5R6oM7NHOPGauRwjhrLlErIX+w2fwDd8DSlZTrN+hNteyh75CzG
HmC0mQTJ+AX42x2tdlgMP6OTKuVqS7pZ/2MkwcfzZVlZX3QzSivj4h4/4gradEdv5F6/3OyNp/yQ
/rlIyJu7a0baA+r9xE7tlmtilhjli1JRZ0XSaaO1e4XIyqz6Je/bPNSAhZHD9hLLixXHept6ETzW
VJ6x9cvUGbXaHNSzLcG6mp0PUIvsxrWbkjdpdSyo5GKCjEu898r5PcdkCxYLzd0HV/e+300bDSZi
Koev9Hc+6M3HBk6RTpRnTnH/uwOJ0OEPybUN0nyq6/LrTnJ8VXSFa4IlnB0r5kWSem8yX3UDWhF/
3PIqbn5R5gUd2Hgs2uYswAFe39bQnIOzo2I2MT9zw7y1tOZIpIglMHbf+5jSqVus0QrVLG9Oo4u1
f8Z7pwb7G0C3ckQ2KTFIxGxsXZS4b68PcHwAROmRpMPH9lPjAibGyg70NKM43JgsMVOGWVh5HUvR
9q69KnBvr3QtsquuVIVEHLGE0C0vYVd4zkMaUBM2cjzuS5KMhoB1mHwi8HgGW/bC1fDkyNzV7ICw
eloYojix56CDhjySo4GfmmioIOVOsb75KWFLBBE7Bz0nLwfq0LCKJ4rpaB77nGhAbeJU+oB+9ZGv
+tcvfDTr9S/C1EtYBZdbYX4y57E/t4Fk8DbljUURFipZekTd8RCFk/JpQX/q8jYG/wvHEw7wTAY3
oVRX8BOkfwXjM+XjJf6txOctUdU6nQuOB/1Vz1tpyymgO7KMvOncg8IKvJHPjUR9ONcVpOU7LTdQ
Qt9kgRJYXRg6WmaNOuHmVMTulFwGXF1uMacyJP5Q+rLcIRFMz4r4toi+r16QCbcMeJBUluKpHqRK
pBdVKoD7XQOZ6sO7DpG7yVM5Zq+qlrGxvyX0tGxccDJlpDlhnfkAHVhKILoI+gWtXA9RKOzgoAPB
AUjzkEHds00ndtS7Q5TykhpDH9e5PRfob01rqIaZBY7KJhtCPkjaB8noFChD8RGzzzg+b+tSmrAC
vFs//poeE19G4X+M1RYwgFwoINiN1BJTVoxteEMwyz4hVOG5W22m9eASrXD7fR9kz5Dyq2SNNhql
JJdVh7EHptUnSIRO+D4Ob3MDlQ+hnyOHW3RBjh5v9RP202oCkAjmLb4fCbQNez2NOuica/ggDZOd
oBZi8D/zd3U8z7qdzcRhKjhiDIdbivmZ7DnhWM3WxM6p243RNKi1alKVgCtViKgJS8vOyPRfplLF
OK8MznZFVVbAlxn26tM60HPX8l+PEtV4X3fwmIvgan6ehaw2edUQjIDHR97FWTg/rVMjoPPaiiw2
9HVBDcYLYev5jtYP4qEpGKXlftdJ/OFofXPkCnCciB44IjU8QCyl4CPuHJwPMNkeV0uBtlk5uQSx
LmUH6fMSkPpd75HxWcWl325Mhzqg17AOieDtT/aQgNEiykrWcdfI3XaWp0RBNpm0TBBwZ6HrlPvR
Ql0YK4j4uQMLr00sew1NazPKtBrMg5L6dSfF6n/6Q9Vw8aFd1f3PWCZqbkzi7UbEmCDOMsmJ/z37
K647eXx3mRLT0pwOlSXIRKb0Kkkmd239RmH1D+vjqRvTfxwuBVTbxRR1m93Xj+W0D6j0ocCBvC0C
nbSraJf5sc61JRnmgJWhuZY5U3enpMfWaPJOrxu/LsyacqzZP2D3TKX3lZmgyHx+1s//7j3zNi04
5vsXtrpzUlCKj7FA3Bx6IPV4LpCUBeJndlr+8hns04Aw48RX0MMq7h0bF9UdujdARg8bpzjneXEu
26ZdH5pt80iLfj0LABQb/24w6rt5vt71E6Y2vIuRY+y3rY2spKGd7t3J8DAwwoZ4ElYE2dmAYGzM
J09IeTegMXrOea0pqtL+aDz8TA3MR9LXtm4RmpS21JX7obQc6LmKvHqvONDV+ybMTlHM2mIS5Oce
ZWDlsWeI6asmlZNVHPexGZwkOajx3vfHbS2Sjgt6lr2nIEyw3yrq24rK+FD4eTAfUAHc94DRlBcH
qceIZufk3EJZ2kVk4IvIsB6Fd5QCZLJmuPIMUSX9y7gShfcUIrZKAxjKN6qZCpCukZA08GMfKLj0
SZ40WyUqZVrzPAGRCtHJI93DLUkFXVsPuRfBWuGmV505Wgd6IXIPJWVF7XYMUd1yEiekUvxo9Fxl
uLmb7KUodKVkY5fAAiihlbbjSm5IUhTmD7HfaITfBt6Zdl9EMLq0WsurAiVwUdnGouT6nEd9LZNF
schYDU6odbl08iseWjoZcF1GyB9UfTnqzhlt4/0IEHqFz1vEiABj67al7WRV8sbovp0HXSei3+7s
KOGv+9CP4Hi01vs5Wrqg+hKp56Bv4BZhnjo1DiRmJLVznKiqM8U+mzDzkJmWtHR9VmAjGrHR6Fb0
hV9tVk7dwzQTc6tWn6I3UPY629fKrtHXqiUEt0OZdDqvmvr3vggQkMPUcGzm/5wyCQOmIHdggM8B
RRShm5I9wbxNW6AMLSWUBp7BLpWEoteNLFl3DRa/5avCoVoM//DVVuNRwCluW9NLooM/hifOw9vd
DllA0wX5AKwN3jTfduI3bfkjA9uMPosItPdh7TyFtpAP4rC2JSjl7yWIEviIMn/yWYNeqUQHqv67
uCeesBqNMJwOopoNSYYnwlHNSLlaI+9tF5QFu85RzAq4taf1Dqfpz0jjcOhGEc3hp+PkkTef7E3r
JhfHgEQt9Pb+uchraQ6EeEl0JWpAEoJV5cbJEaGURZCql9UMnBZRK6ZoNVi9xhdK9rFmvq6Avu2a
TPpciy0wT0ylaaoVvc7HxLSV0vNNodyL87Z9FQQhJ9X+4f43KQa5ewz7nxFMigjLI9sQiUtNpadl
7sL/f4jR0EY/OWY0yKrsioz4PgTIhaESSfEd6l3ZYtNVyHPD4FoVnR3Cs3g87/ployhbhwFZl80o
NL13RwBgI7sqwUrBEsHe4r0dlMh0L+WUmGGwPWjlbG6MGefNwFIZ00SAWk7/k0IytFtvjLsTIcho
5QqLSKgHXBqn2D2DpCbtl5+cmGpW+4dNgJF8kfhx4pfAj8XHIaCMPDvkPd/TWwFhgHMZ+lHtB3l6
f2EZKwZA3wPAsuUoXNVfl6wRHqSi6eOwx87R5F5aAOGnzP5By3MsG5WKILG+Z8JKRnA223m6WhYR
PuzErCRgzGSGwD6U9XTh9jC/BjYO7EgnlG7Ph6AabY4Rhw1zpz2PmRVZuQAy+qAbB9OydBlwRMn7
JoXmsObXfT9DVEo4QETvMooYswVGTwpE1ihV4hMWplKxP8Leud7DOf9kO1fRubIjWP9fCCuRpK0o
pEw4HjC2yLi90tdBQg5G0I8WRmMo5KTYT1rMbcmTCucqiKu+lHOwnB24Ig7CvQ5IP2Fxa4vHP3of
0RcBusgEWi1l3fHD2Hu+OTSuZ/p9JfSevecJBhIrSXDvIl5588H1B9m8R+rfhyLtclaR/PZRzocl
jqih3OfLWj0JpKiqmpZb+wHCVp4WizZTSlrvMQ3Z37qEJI+L+YxK/Vm+R52dBDjk1WDnOLGzYz7j
X2L6sYH0V7aF+fQaFVUn14H1ZCyXbqKsEZ9iPpnlBGxZctcwZh7C1fBPQUTsqFlWxUbKGPiqVRKS
fRzFwc4kIO+ynGmBsPtW18RBv1CBAPzBCHKx1Dq+g7l6SAUxQOUyNrFLPIYOQQv7bs0EZ+AlppZM
WqEoJS6/0mQXSSMihrRbetkEK7mRj5SWBbLZrt6ZVlkXCjK6wO2WR3Lhp7HUn7HT388lcNZz3FfI
EO8caeZOcFsy8ERe/MuiHV1e5u9lEtx0ENKXPQOt2bnh57nfRh2MsBpSFcCCgUpuwTm5HMv4InpV
0RowQPICQNnQK9rIxCa5DUYIRghWdoCsPzMStZFKFLpE9RsiEB6A9/ppqEGyL/pER4Lf53bslKke
mtFG04aUGWKSxYKe+QqrW2UV4f10N2EcfOY0l6PZJKaTLe9fMMxhVwwsWyS4OqWE8Qs37CnvapU2
7UF/9/TgyCdRiOY1GpCkkBsSFQNRObDTXjBkXHop2HLdDigRlhX8Ef92k4EtxfgrdNKVFh0ZIWxJ
hdvrGaOe7ZuWCnhChMzoot36+hZHS2+RUnqH3NgiHkHVIG3qOjyHnZhdrClcNK+Fnz7SLyNsKvAc
wFz2k4gCy0n02nH2UJkmtB3C4mSMfb4Edyq/bqWR52UF84CxwZu+EFVS1PqIg7sFLlN58NLF4zp4
ofkR0VGYgChQK+/K47vDsnEfXUBmR+8Gt8B2uy4g6pkeRMyEWrhchNnw6e4ONa5KKzZXQR3hBp/p
HPwrvAz/f1bJGEG6Msm31OLJsKfN9Byz716dW54lo3Nft5XjvcZCb5jeevN+1Kdbj1pjBbRmyWNQ
xPk1f/NPkF8cnhIqnNUCcKjVypcS2LmPtf7HMJY9JhYhtqyoQtQrGbbpS5GDgD3D57QflmklfFzY
wwlE3JRmVgcAFDM0yu09L9JsUSYhwf7CYhgRwu/YZc4LjcqMn8/lHi450An4SD9JN1oau5w5XhpO
E3QM+nKqgzGOS98xtD/DkWhYPAsHiOCN4VdRcn0mMz1u1Gm9F9Lam3YjgGo9XVmiCfva1nmVtEqb
JaXWBCTfYDcwM5FKUSaRca9TVPUVwxoliPIYIrbotD7fpxvuSKDZJKWEp7eNZSxKw2UtpnAhMt3l
JYoQZxcM8Dh3t8m6WdR3hBKnsUiqucMj1tpv7t9rvygUSgLmyURnmrKUUdF7ty+FAHYQyqhbuvnB
7HEwhqV4r0gwjUx3S+/8BjwfMs79p+xVdzTso1+tlLEa2tqnYfr62/oy5K0LuMxUSei800cpVcNY
znUr+pF8L20Zjm5tP3hBGECjRpTpFkKq8mYga5s82g+9jLv2JLeQmfYr9jaKeRjk5K44gBcdarOg
MfPXwSrpY5soGcG/Ga5zDvwuddL8OKDfTn9Da+vd7KTb/IUzHdqn+cHiqKWKmZhOwEhLdl1uTogf
LjXmwYmk7Z2XK4wsPhU++sM0FVOPDwuBVA1hElzM0yRoySTMdjHch7d323c4ei9U3woNAYu2BP+2
fr+Tyt3wPAZDtK3lLHEimoHWolqKKBC9LlpTxB+KyVpAcXDWdYt3PqytURhqwP5LQ+EjyHlEC90A
AVL0e3Z0MKR8r8etc67/C2ozvUmRVFfGGI9rn6hWufoxM9sar875aJ8Mcx/VnvOEG94KHPyer0Rq
L1gOJ7N+rapghyf9e0Bd6AQF5WJDRk8in54GrzRK8UiSuq2nnekXiUI1ElkyiZ87HStilpcS3ojc
hs9c89afygZfgqHhjDw25WDCfb8NFTptdghkFggJyY2TWcPcYJIZAtB0VnZhyKlCAcArFkdDUqGM
2vsENM3pLkbuj/GmwyZENi1j5ghTVbtyzs6z9vas9jZeo8iy/53CHkl2V5OgcLNdpQkgLL/rqeQG
P0fbsXrKrHQ93ts3gNcZjZ/4QXD5uT4eN3NnFt8ldwf3Lj/+0VTdKBzZoHSu6ynLafk0v6pt1Bwg
VTqhenxFn6DLTAschVFc6o7S29+2nJtFl5IC7mVpj807KRHOd41JjIBYsKwTRr7uvCyZv7djP8f2
q2spGus2ABn+mnE5itjI6ifLg0sYmNo7rXk+0tNZkDfdFA9g05Np5i8cuN8OVcKsyF1ephFCLRc8
RVIkNGZGgVKBuz41PUU8r4q4cpJo9ys8fqY/r9XrBMrbw3m7dd9JpZzvNJwyynGK4yvmXgrgG4zn
1pcWhbkogXdzwQ+GlsEh1DfD/vdYox84u7ngP79zferlPqpvjtEreadudXdoU9xcAG9mZfDEO+sL
iJtCgADnO07llzBq9ec/Ieq+TU65OzsLMwaydNpFO+drBirZtlW4S4MVO/WPBb0UtQlihS5TTGEw
1USTSlLge1HPRy6BwVA5Bw5JOgs2/LeKBuedsJ5SswSWwoYvX1vPQzwg2e/dzANivaxYlhXquoPc
y28n33pmmPpMqh3bHIXSc0R5441oO+yWiWKl8/r6kkHsTwhuAobbe8fklVBQDVbHUdTrF/I848gB
ZaK8M+RqROJ/MY26nwOZh0fLtUP/QZjJ2qC8q3ukVTtHwFVqvKrFuUg6yiMF3yzm+qG9R3WWp7cj
4XeB5kivHz3camUk1U6vG8vsq0/hHQR//CrcWnRS+5tHoCzOkK1ztbnW30fW1Gg61GaFOO3pCI3H
dJiL1PewqVQx4tBz5RtekEzHHdbHFAHLNFb9GGep6yaNmEVdJtNRcguWXemWFVh/A0RcJT4k3mLi
5rw8av4iuWrT7Yb45Wyd4Z3YmZpulxXqihvTJhKvXzBJADIaTgHJ9erwj4gaexePj0d1dcDFaJkM
5vjK42SFqkCxsOZKrCyfATpqIfieTVZk3rfLYZlLXNYcyTWNkBDy11Bx6od0q8raieKMk3vJ9koJ
yL6aosGNsRrNOuHYbDA8pB/+cJDSrIdo8jbbWongGUvjkDur7NA3igM7CjXxqUAJeqt0AjAQg8jx
FvKXMT+bSKwPmvnWjGRN5JbC6ppABvUd1Uj1ldcoT7R1GH7UtFnVx8Jf73zkNd66A7iwgUfcgnzq
V2tTYGZZi+bnnKkjzVTqjd3vgy6a3qwUZv7UtTTyFiW1JpBU1eOHySDN6/V4HzRsY4l7ZSCUrIz5
idOxSc7ykEP6waId10bsR3hkwvIK1HjXbhoIU/OWAALMDKwnKCQsYfYywFXsk1qjM6+ltP6SJk8C
QtpS7pIV9bPN2Jhy1TLLMrtrCHRg/jSF1C64OcbTY3F+U3O70ogGV9CvRBuBTPKqcO/KPrEmsCsU
fWqDGH6rRrt2f8Q75lvEQ7GauK6vmOpI1wb/mlnsxnV+JyBlkSHiBxxe7NIOFVsrWYpcfs0rTu8J
TRXO3ZBmoSQKCF/K3wu+JSaHFGwWra1PaRjT5F6KWwWG3rUsVp2segJRyv+HJnlinhq+1LXTlgVT
rDps1xfSLbDMDo1/NgWsrYfhg2BEGh2KIwHx5SlUfYPeCUcDWgmruhZr6+6yazhJUvvYE1NlL0M0
Q0ILOji1bJTufyfXrmaFJRYGbWzRVh2OtFWVdckEikVXiG2vRzPc2GucKdOeHqFct7xVym1Yq6+3
lLd3RGhkEjo0Cs7sVDuMSmuBDrsN+k+UMYr9dpsNUbSNK6xZodG5D7U80XxxbatJx5hIKbQ2aJOO
9ASCR5D6rWz/ZekbQhxabupOm3CE20F+TCLsq5xBFEzjoAaK8eIgxQnT0a4Q5ZSBjgc5PFkXGM2F
qMU6uhpC3NL0NfqqJK5fx6PiU4u1lkVtYvvTJePUo0cXKWVfyKQ6vR2HGmahcWcrtffsU+2Centi
n3y8KpnSxkQGDcmw0tmvDACEuq+AvHb770A0svLkRJikMlGgpC/j04pffRZZXhCzoJuW4PF0JLIY
u/uaKgRpmqUtdaq5Kn0XpYPgJVyaBbysZop1aidoHdCpq3Tu6PmbT6s/fpzckg0hJ4G5e27yDLNk
seXHh8AubvOJYMZLmKa/0bamQYirpBP+UWwRo4xtboqteXeopbjRSULzSk/e3kNAj03gwRwq3hkS
NmL6RamtowRq6u9zZYCrP/9fSkPr7MfB2mvxp47M0+UUWGSDMUTht09uzLiTkrgHsJ7UCW4AKlc4
r9fsstPCaMFNBsarh90zX0h5RgxDeYvazAvh+tdVNRYQKIOFvUR8seIxmuH2QtS4VhPOyI9qPT29
LOqbs67ifI8BW31TRz2cVyJ2gLxk45rtKVUiwjVBAZPY1RIxo/vobWfgZckMWJc5Afe5fFfcwKGn
iXunXPOfHUDOcwCu1VLHn1tRUfLPMwDK1dWvkvDyCJTckqAMFvN5Bmltns1HgQjNUkifF35Ak5TM
14YMBCemGmOCL7JR3yvkgC4H7tQVJJl/cxKqoywfhzkf/50q1sAEeK+Pekkfmn8BqnYAk9ZrKMW7
p+h2vRNiaHmtU+lJnkX8QmpJbKG8GYaYvRCOuk8DrTwmTo8FYWo0G49hPYQzZvJaF653wWpXLyAw
TJgw+NhibPgBSh0zuPYtbHPWWLQC6pSkOpnDGGDgId7b7BDTgnOIiEvkahyE9aUr3yM0mh7NLreT
kUhudTzgn01Dcm+488aVNslTNMwaWqcaa3qygc0caRcUEb7qZu9/pkKLGFRoJYDSmYZDk5ZW1MrD
P5ZuHNiUflA5q3AGmfdmJpufYsqID+doqj9xH8QPEL2gFG89iSVEJL9onCye1HJ/mOFUXYCvD54e
l7SJ3OVLm+hwnRrM1rymVwRXMgwOsimqtf6IqJjMRYvUFBfjoKhT8c9SUevrfJC5IyomGi8Pyk/z
f5QfwENYTXv9TbEH+B8NgTMdfpZ0lP1NxMRYKipysoLlKYUEIhyilz1R7jsQX63p1pXxguI2Pkfs
248uPc3iQs+FKSxXF8nKykJLFPbVsuM+DLv76/Lnjtn2eckrMWPY3UvNLif+EMzQtNu1GPRYikZH
gpDt6vEHnPIYZ08ZHQ25CQL5H2Q1DAltWJOaT0UDBqVHgl6okm9cakqD/3Xr24+5op5sl3QzwtSy
i0msayZca+e2IdAa4lqmNTjEVcv6V1NMWzliQkYyv/lFJDL+vNbpDIMtDUZVYV04Hb9494npPfbn
AYjTAe/EtR84Kr+8vfaFb0kmzKVgOkWFGx8SF8sIs/iNMdLvy2pLN++N7QOOrq50kXffPqvtTp6Y
BLj5yBuVesiZlhuR1lj9Reog+gWvBe/djqPosSlBiMykdQxGPdNLlR7PCJipHAP/+su3c4EWFg6a
qfD7DQ1k+JocuFvnHuju9zZkywmWX+EXFY/sFRfagn1b0dfNltsvkXHXK4xfjTzsDw6mPTPoliv1
Me06VGB+psOHTSxWuMLAZZ3KllrlBlTvg8yoxV2y/yg95HFLIKzoFcCEint6mCZnOHZ4zazpV8il
QZSDY6n1Gpdb1S7zlef4/NksX1GLk3bRjbqrZLcZOcCa07coUdpjUcM+AotSENPJromzJA/a68rU
DPu+9zCbm4JRmLui0Yj9t3b0ahQOHZRKuPvBoswZ5d+aW73J7ZVi6lOX1rn0Hesrknk7WNZZW3mG
X+XZavCcCHC54pT5pALkbjhteoWif2on/eqmP8qnLtivmNDlAhLqIqUTrZGf84OUx8iNEWQSOXhJ
RDOVKn9EnJ+LlhZpl2j5bBCxVY84SzAKTY9XkZa3zABDbH4O5aQIR4QlQJveUSYSlcxMc3nTGlA5
Kcx9f91hPJwGci1gBNReojgXPV9JlRo3xE5T1c5vFgvUk4YEyhflCGZG974NqgwLzAPtCEr6fZ23
yI89ukbp/s8S51HNpTg1wATrslC2hwdMAEsfV206PYiqZ0zjY3Ur1FFx/HbGTfVF95w8yT3gyAEO
tsnwLSbXbRVa5twKvghfuBkn3EZyxDU/oxPZ4V5ceOlPMYmJEKeFKYg6w7L5TyOP3sXW0/hcH6F9
6+blhYmD+IAv90sOjRLerDxM9qewjCXX8yZa/oURHlvk6Fc1R44sHqdfAG0uHUbp8K1C3Iokgn1l
pKuedKD45w9pZQbfj2B1ZPr94XThATRMh3hNtLSS2v4nioiCC0xoctQn2ZOcOvZue5KzFqFY66Uq
DF4PaxyIq7aO2717K7kDmlekxVmpZBhg3cdoG9Osg936Ixf/5J3zr2L2/lZAzsRHpXRfqMaQfETr
dqeZrrhtLu3G7Rs6Mj81ri+C5bqV/w9KSVC/Q0+81E7ypMqZT4i9Ddx00yGn98/lZwX5ztoLRTAm
17kH/prMr+Gvbd3y2aIDqu2viDEieKpNzpUqJDQasMdkQZ53uYKWASwUXWz3taox6JzW151Fz+FE
rV5MSx6gTszaFe3mC9ce9lrcUGsN+9MT6wk4yzSZvOILE8/DCjQ+SGCiBVzUqeM1qQ3ZEgh3Mlhk
qbZt9HZeWvrEw1hBW6vcWffx8eFZ4NZw7360DrtYAsR9Dl65/RJvPvlV3ct44tam1qAnGeDcNMAy
7xyDdsL8zFoOMizBSdGE/W23XfgVdURZzAeuIWQn08aq0l7mPpReblGLbJPi2fjBhzU15EFVtAxo
VIjcnaCYJl1lvLoGZ8S3g/V15Igh6wUYnzdFEwdlz8FgINYsX0pIFhI7dL/Fbyq0/86OoJpXWx+I
wU927ZmoAKv+RrWwvkLljZlLBLNxYufDnbhQVGy1AnWrrQl6UG+QDcKvP6Ci1VQPJmGJzuJIWARu
FVd3aViRa/IR44hhfjiRhpGJm13o/17kVmDuNDvl0ru6zkLs46nA16M3oWbELN3p9i8T6ZxtMWK7
hcbY8mw0S3LqJB/EfV24v8Z5pbSM65KcYpEdvpYtXoDCYq8qC0WHP4S9q/GUw/+gZoI3xPFBy9s2
1vjtdXajD5d7Nxkk75sYe6Vc9QFqOhKQpAg4F0uLVvd8tlq4K51huKyiE0C4PsQyvyn8hJGuB9KR
FQFes9R8zzeoIxy0BzdBaMd3eBLnKIkVZ3LgLPNis99vwQ5oOTdNSRWUoMNfxEohVII/PSlUzCMz
JYeTEonWMqqVG3L5Ynx3UTSkXrUkLYlaXbPFSdYxF5FC/tgimAaMin/l+iTUJhmK/bn580QmpCu7
KAHUazrjh8QoszK+WjOkzJjxe96zxaA3ZpRQJUuv4YDKTymifX+D76ueNPPCBZi8u5LPgDymG1j5
Zv/gTOD3FdNuI5JIUZ4fQp2zcJuviKkAm+DcbLFVaxCV2njsubuZT8uyxU7mbFFvfhWMmawEF7Ua
Tizh9zTDAhM+J1/WqhzmfeTUvK9FOiawIs3EwSsdA7nOfFiR1cgtoLuqJe1pBLKM+rFD+GbvBoGg
MJmVeXXwJTZ4g81W6f+Oesu1ahkwdF6p+YVYBT1fBqOLIV/FJlaMNnrycUG3G4khA3FJcDDTMVPt
a9anYcOSEQrRJDBSwSRvvKevaXUW7dYXTB8wvpLmYbvdezQ8iDtBYSYnSVXAQOhxEv1OCMsXDvmm
YmYnpD8S5hWbWubbqedYfp43bjZN2NgqljwgGBlnE/oZ6PBk1I5rt7k5FoXkXXVkesXv/cgEsxcT
x+3Rc91HrO417qc70s58lpaZM38XkhPvxHQbvFdYX+LW+fH6NarAfzPUADFd/nm7KLyLv1M9YmeR
Dh+1tieQKRr0s+ltLyalvWrweqgPVrvxdXTCbhVbRnawcVb8WoZFZawG/BpuEL5+4Igi7X3/jUpT
lsUHlPTN3PvEi890KUF47+5zLQnrH2mND9erZZT7xjtzO2WG70LgC9gSwEdlSZx50/JHsolGmSw0
x5Gzw2uxOYH+Sdqm97luLHruSLp/NvnkV2gu2Zn86Ot3ufx4PBqfbtx4Qn6MFLJuU4FdeyHeBUa8
LYGf2TS44nCqY/ReQz8K09IXeMYsIBdiEXymb/cdxtD71IKdK7hTaApOkYpLndq+33J2HbPBNi9n
nSiM7jQ3+QRlkOiFSGo9IBYxWK0wm45YrYcifP1surj2Aqi7+j3pjfXMSRSr0EQPauE737LTtQNA
4L2ZVxBM4g4MhDaL8iuzuj+0F+5M5VcZBWWGEdSwZbK+Kvp/JFjMymBsXG3oBePQkbGgpfl4bFWC
0JiLh5ZXcVdXDChVPvPk4DTFaw36i3vTMqIzlMno7q6HHiCS0vgjm9qmbDluGj/Wiq0pKLo9FhXe
sjh813QaCRYD387RFzLw5gErKU37x+JdzVmzpeJfA4FI55aj+QzPh2t+RO0ywhYjbuEc6nRDPK7S
rI1mCuQhT6flIgnvmtHqOBWL2nWYjM+9N0hL0LYjQkHuewZDP9olo3hcH9rlz3NYYJI05I7R2yH4
yqZ5Ewrxy6wyaeTpE+zGduEia324bPOJ9ccYBmK+W29I/enAATm6XGwgXxRcLRroCBBk5dYyfv5N
SHCTuZhaDtSDptgt8aprDCDYiNuvu3kZ/hkPxCEmCbMHKs4DogLmUJy1U9F8UiWydzL1IPqGaIr3
bg6RY/trbVIcpwpsZZ7awV8OQ/oAC4o4rldRikQxYVuQfaBepbkGzhP+MrVA0JvFbiVacfsITnXj
4dV0rPf+6OegXExeHBkSIvU2ZF48tc5RXlB4ceAY1jrXu+Mj+op8hMyqdCte/G6aGku60FhlJFIF
pDc4gPQZouUbNjwomzqLFLxDTYpKKE0TJodRF6ooWRfrxvlDwMOmFyOpi5ggL3q/nLUkvok2P5ch
B+oi4nZ6GwzRZh18pyZEOHPIJKVDly/urJ16vQw/df5XxgazvGQyhC4pX6HqqUnCs3mBWAJ5IPwn
xaesLhU326DvQgc+CBbvEWB3nWSNL7ecCyFHIDwQ2kHHNFk2lXuL3KD5cEAfa4vVZfzhL7A7xqR1
ci3J6Uc/rgpByJ4MTNVbqSzYANSjEJSF/vsLBvHsHERnWnSAKBb+W9daasxJwu33NgSCUMG+/x8X
ekNtaKhcyq7grwQ9EgUHzMK1k40pZ36PaYSPk1S/nvvcgevoiMoOypCmM6AXpwRqD/jxylIzYKhu
zzGQi0IGzyRxGlIl6uWS8MBM+ANAv8l/410wuVUaQz0l7XCr0JzqCTblo3/rwbVdVjnYPx4BFV66
OOXu3Oxo49ZgJsnazLziWazhrLHLPW+CSHuDDVpOjsm4wCePWf6DoWhetMADD6zzfZd1aUhB4dGB
XmP7Eu0OuTM9nRGz89QewWrcd7/Vp+KmQAht9H6/NOue8hkwIiI7YPDp/TcmOzMwWQMi/iEKB/Fh
mWAXaG/ZCJu+Djmb2L5DgTQakh7mOF/YstameEAItMHaqUqMY2f8K+T38NBytd5xw8Z2eE1414Q5
LVHgtn7xup8zX9C9lJ1gbAuuT/eokSeTJlqFIE3A92zOwg5U+6IwBcHDM/9ipmzZBeOxM2y6t2uj
/nFMK4nYpABpm0wga/S0NaeZ7j9i56vC5aHuAosLa7gvAJx04dw1jTHO6VMXSQkwlmyZvZU06z7X
jwipX6q/1nUcUw/ZQCD82dzOkGVSSIgWl4bzFMjHCBMlMNDR1UWV7x+m6GJZ84dMBdTf6n3o6OC3
NXhGI+5JDBljjHUhulas5sR2bZduJcPSjJ+tsVMRSA10nZQutstuwMIMMZiFPzWSgF4z8ifijhY/
JLFYThaukeWbTJ+3DsSG4WVEydXuZhrICYDWXa3tPPT3PJPaJuLIv+wddJ/5O6wjAbIeYqz6/HVC
IPaHdx32EksOx4oJfS4QoP8ySTNTjPEuuRR5cCsoKzk2VYB73g7Q54XZqaqmOASCOgpc3YSb5pGY
CNBQLKhk10n56xMpNv8npWT5Kh/fNC54ne0G77KpuFZ/KfINkXzCqzkE4l14Ev3u9E7TF3W0iMvP
ykzVguUafZxsbjHhr3zRRWNCKgY40a0NPC4gtmogzQ8yKy3crcDKrTxJ1JAwdNNGcvu3TBvOL+uP
KA99burzNhLQj+SZwNxkCJ8/iPj6GiDeXkpO4aZKK0MKeoE3GpeqqjwmpUSufNzJuEPCpJrJ+jWU
DPYXLrrGvgzYKFkZI6TCVJXosoCdFzwApvG0UeStV1kFHd1uLKjp37UPy5ypRbT/AKjIl/biWSF7
lERWPX4QHIOU957qiHxJANa76yflcUubH8K5YqCe2m/t50zxwx6FYRKlXUS45y2apcKfFje5osi3
J7GMyyesQsar6ch4I5HzjaliXPylIQPKWGI+cY23dnmERXMyWdj0mBljtIyclGfaz/S5EeuEI29X
aOD3IF4KOCOUSuXK7PcxGj80d6qc2tKdyzUbDCFElLpk/IqPCMcPAGIaJr7iYmXgjMJFeRK+WQ8C
ERNnQ7V3qJNhmpz+YpQxTJQ0+G63Q+ZK8cv1R1eexLLzOAPzDY1y2x9kHrTSyKYcRsii+3pulxVG
K9v+CKeH9gyBC7aJVAe9awdHUfCxDvSXgTyTC2RqIxRtohWlMZ364LJpfyZ6rYghxcnUdVFZD/F/
+SDD9REKBl4TjewngY+/2iKIUECZk/iau4Ezv1jGRFBNiWB04PZ5OglHb6z6wFdtjV224WLyAO/U
P5eEiw+stZcpJtypz7ZAYNkCJRc4Rvj+t7QQBSM+ybz/gSNGuzjnNXhz2agjfv8LTz313tszoH7i
zte4xuhRkYmeUxtAuf1r549y4lXkbQ2QjoghnZP14Uy8Gqhq65bb2Q3SAFwvFejaPxtU6h008LyU
TaHxRpU8hIqqEvHxUoCp+ScdTe0nxuDAuxTj245YKyrGS1em/pSb6WJ+1IhETQQ9GJ6vhHEq3XjD
I2Ziy88++ZwS5ykg8T+yVwQsS2mjwn+tZvoqACk7GqZEh4TTJ3/H4uz+nT5RxTygcfThdFehm0zR
ZWXfcyvqZ3tUHJmync9zU+AFglVZrEiyChBhL0Pi8ofGaygDIs6q3DHToR1aMbKEhVBBaFiD/dEI
MwoCcG46YTjLVGkKw6f7htYD08a2mH0DTokhcl9tSV1uAfSYryzaWoMpQjV5rRe+BkBMm6d6ZlhJ
poSyUG1408RM3kjSpAWaKX8TgCYZX+t+8QCNdv540I9qB2cXi22YW2hzgUZNmbrwS3xhzA4TKK6N
8aOWDxktEOD2fGnM1GDR3E8FpBn++bYMZ+GUhI+8jsaZFBMVXET4MbWfdrKnsYnGEEGljbq+ci+K
hI6DH16gyBzmKBZcFa1U+ElYDE12WaaFR+yacQhTIYmVdxS1FQzZ/ljE492yXLanWlNig3t0Exef
MK6MR1rHi4fKI+xq7hpkCIoRKHb4/vtgTIGf/lub1RadyOIAUqodr557W7ojBMBavGEe6B0m5hmy
dnSPZ6WduSLIZMwhN3tAZFh11PZsNdGFaJjaIXq5FoTpks/vVmLRj9CkeIvP3s5726mDSk8XILBf
JJvWUxShODByUr7WfGgaKOX4kqbM1fKR4nTNlm56xEHSSewtAzDz1ztiQwleOhcJdnJWqB9+o46b
YRr8b8rNjkahCY8dRt77s15SMoqzUVy5ijUa0FobdnS+K/1cEZ42iR6Ssy9Nen937JesZV00Sp8R
DKXIu37A4ZFJ9mSj05k1RogV9/clGr4K74ohkR9IvhuxQPWL6/x0Si1O288kpn7J7m8CRTlUtcWP
rZJYFcCllqK9wiqmkzzSbgsUGcvBbaSUOPY8++y2dT7yzlgVQ9DGBlHCjCLBpS83Brb6cU45kqVs
tvlJbFwOxHV1I/z2BqnuUiVVPiztu/oJmFuO6gYHwIFGturI30q9N8OSAJbDcETzwxvW8VwMcfBo
12tKzv7jGr71lYo9ea4rYSUnAcDbTjKRaBDdl6cBytYWRrTG4wyipd8IHVLq27M9WUHSJMI2MX1S
xhvKhXcDCe+hChHoODHYVe8oSqlBn+qgaW2GIacZ7wORhPq6FMGWyLqQZqL7/NiNpf7kELDFZKAE
4vZGHqIcXWSuaJTX2UG9mtX0LwN+tkQNbTqN1d7RVFly+NE10vMOJ+NjUTAwuFp9VQkaYsdlm7TW
vlHa2r16MrB0QEbFEAniGFwlpvbfnutjxmLmkY8fVI9jxIVyTR96l3p0xfHmBMidV1ozJzC8OD7H
mbwv7fL3AB+99u9xIsRVRSu13hoemG/VLQCIwn+n+Pw+3rhHf4hDxd+xn8yGJ0RuCh66dXwxlTuy
pU4EGKWopUFsRSAi6gIokwlGc7VuVY58y3f21qXJebabwtE1XcGRj4nV8YunEs147kC68ecayQ3I
VT9Rnns4KfX17uHkfKZwq2Yvu4Y9pN3LB1aaY2Wkbts/O7/2g+XdvN/bIFf77M0uPd0oUF/VY+BS
oqpYCMiT7sJPMsvSbXqzH0ct6azFnOu7kE7KiWBIuHAvVMEI1oipzrS3Xs4727zB4llAGxoruUpu
STs6S2XQ3OaOjgRYHRTdIvTUo2yTmzdd9cR9dV36/Y3Aay+EJY2bpVg+4QyHP9TgrFN2La4txPlZ
Ks/bV2Da5gkest9VXdISS491M1MfyPgZqDdiyb4p3fgE1KANF+Xp+8ikH3SIvXJnf6RjG+o5rdJW
BU84hx2oHvH7NzMdRMN+tnXgwyYGKh0eXPYTm80khgQ6Ybx/1IQt+TvAT4CcB08oP4GdeNpoOGwM
dnCueXh4ZckTXBIHZ/Rs6vFoshwpgOuCIuFneeygm3UNAT7frTjOhfUarm1ZI0H6m8O0nOtql6Sd
oRPWz5OZrVT/7CxGklab5b/VnaksmoTESseHm5eIoEAxeJ+hu2LuYIp6R/DdsGllxCoj5Lv9b+Az
UL7PvIeI9hQpKCulJ6ROJnVyWqJ6tjaPJkOK5nunxJAiL5zXkhehs3hPWXO2uZFmxuLDIQxVRod6
YZkZ6bCCxzu4yng6uZCpNiOvqVQilUVngRHpEoCUvo3yNqaWXjfVQmfSvk85qoUJjv+BCmBIDNaF
BjpVte0mSe8NbHM3XZC1u8ZeIVOEpT5wMVmKlMvACJVk4UWu0lXIR03O5yKvFV4V+4mMIxNnUdH/
z+r7YyOxh+g0cNV16gH6PjOxwZ+1v/a6xiKvGbLYO63GNTyi3596mUgVBn1PlW5O8DawuJwLON6y
M+f9qpXVB2UtWJ/yVHk0ukRku8siJk8FRMBemZdx8fxwrmSzDaPqyKO2pc7zmaf38iYqw2OxcQLb
hUPG2LeNjnwsZkjs6XDPZqD7d0QMzppbtalIURwkOy15P4LgMwWVFAwv9SDwaqyOOY0+CgiB025+
DmjpeBZg4yNKMKamA62TEEqHOrNyJ3uY2AyrQ30cg3k8p0U6D5cgRa6smM+nNzXOA5ysMe+I1IVN
vOd8Qfhu/6kWUMFvVb094cMqYzNiFLQ2H6jTBU3SPgaGsPpJtYvQ9JmC9kieBdOSEzz6WMsbaN4P
0algjFyK+JbNkT94orlQIeLtS7mJGIHqH+7VVsgslufIQfBCyv7IMHgIIXbza/MriJnwlcKeitp8
2HQperO9zI+DJLQ7wHo2LQY2xezG8xNFnlzlJUTJtD3RaC/QolZL5Lvcw0NLj1O7DYhbFAkOLCim
ZThi2nemjmSuo2p44fqGepVDKHY7e0fGRn9A3/kVtckczZ93SHnbO3e7Ecj2xpRETVt6uBWeKRPe
aP4sf4mlhXXP+bellFAPga0LK5Y4cVT+irC1elYLMao8b00YeWWjLxzK/ctLnPToDheDF6YoLYtS
xQDrIgQtDBV1Yx5SZtE6rYaH+SzzCIX3qssWgiuz36kDHDWdoaaial/FX91YWbNYnVePA2y2QoXJ
tKKFeUqlbqM8ZqR5TDKR9Qx0RCekwJ3cPDqiwTFFd20YOLIhwC8ZZiKkv/tM1RDckmGVcVoFELzs
jqcvBHo+iKP0m55/hBL8BPuglglXmfHmeCJ16a1/fBWw6a1IWYMQ5yqVB3PDIlfTagEjJWrHKIpS
oNejsKPYvIPxzdff0rnSpDg5ClX2Jhc+U2KNerCFq++PQ/lq/jGK3U2EyXGeawFz3JheMPpokATq
nCjz8KRrfUxWesBYwONBoeaWRq0rWjUH7ChphY7wRjKEB4e7iCOJFaOLa43SMUfjFLyBXxfTWJ60
78HzBJtuq6/Nwax9oBvBIRTpXfH5SCoAuY+0BpXIF/j22/IjvU3dLZZsFf5fUvXrkgFTGlDRutD4
WB3uyrmIZs/jsleNte/EmCer/mY5fnn8S4BNF4Dxk7U2cmQmnowC/fvGsMoAr8WOaHHlwC+XexWe
z9oCXH41M3xkDi+351YKmvL1qP4L5Vy9eNEcDvhtZJUtHqlsVV651n54vqqlLxvXLST6k7NOrM2B
9lS2SePPbLttlduwLRhq/ZmqFZLC13jyEZ+Bj6fWDIKsJ20CLcgQ6dO40nft0w1LFRQ1K4ibZSxz
G7U4V+qCp4LNgZRgzzhoQME0unDwL8xY+5/IoaNa92UxiXqv2Jh7UzUOOhT8o2KPi8m3T+Jc8fLa
bshryxSH3/QFKcGE9O6gkEtV5wCtAMaRk2/WDGP8prsnSU1E7d9NDQpwK5UFYMaXVPd5iHLY4oTN
FvlJeql/kiWWkl/v6r+QHcD+tNGWtDC7Hqfg66sTq/4nbmve1nxzpYtbxu6lbNDFngIXoj4e2tof
3yL3XbRGL6EJSg+qN0mgTemFBsSf3N8iBqP4+EYidegfvdnRS+HCdThE3ZQYfUwJO0DhJZ4lZH9z
xH5CDsMXI2rETgHibDwZe33ANfsWG72TtWide97qUIE9ny8fwI620R0ub3vXwzAuWk7TklIOjy1O
jK44i9LTzIKh9HFM7AEMp0aGGPk2ZWo/3ptLVMVeWZkiDg8B3wTzup9e+spwdE+uLErr2bTbEQHd
iRcm2cHfQYBP6dBIt7bEUzhXJK6GsGmyc93GtG9LrV4vh4yB0MP6RfAYgdKIWeCWjArivWLY0YD8
AJdwAj/N6Ht6vQMEYTeZIi3OeC3k08bEGpbUiyh0nNpQejUHWQhBUH2rLlyw7IORPCaP/XD6fzP5
UWEk2l5MqmxVXpHAECPkItcFkewZsrXSLGAdzFOJFtD6BHpn5xX5ugYR3jkkd8dHwBNqXW+7f7qB
NMahX/+weoU80ADXdeSVj26DeMHO2wYwg5qPI/K1oKG3Vbxj3f/BLkWAx65Rnaw75Hh5Zm+C+dE9
JQB0UqZjq2RmUXY8xLuTWh+UHhDT/2+Y+BkNobW1T4UneJYElWIDbZaCerG26EIcRsFOVGKqAPMM
GaeFpPNF2Csx6/OtlBD9FfBBkhr8s7lJF8X1Vk0C9RkLd92VovA5UAmESQcYID91SEja7j2aVZFq
c4WlIjVnYUb0d3+137bU6u30+P2mRnwr4BpiY4xzILXi5KVLSdgJT57NWbMME0eAsEuZiBFj7fxg
C4y2h87sfzm0/c8El3n6rB9e9Kk/028etHd8ptfWHyJwJARyqOzVF9iGfXaZDxv2UWi9MlrnnSBg
f+RGYmZT/buwfUxh+GjV6I1qf5f/zAQVgmafAfulWMzCNwLqGJKOGV5Q8ThGQX5gFEyJCDqe4C61
ZtUmvfxAwLKjtGUB2LXa8Qp960IOmESy/SsbjhLllJ9DonD0CBk+dI5NGj+e7kfmZF+BqmIHYk3V
PzgWEXRziqTq/829ScVbnx4NU48t4CcZ/wetojbJqVr0Gqw+pwmkePyfX4hWv9xSFLVdTvXSs4H8
/NjLxtg94xx1B7rC6kgHV/j0fO1w9aB14fYxFRVafFZ4WNSBOrm3YCEtFu93LPqhMdvWSaYofUw7
tBPNXYJRe4OEb6l/7pSrzkbZDo8Fcq0IIzrLCCi/3QxfIc3mwymhBt8UKaF4/mVhpur9vJ67aJbn
dCuHTqOc1wYl6/gbEjbfj1E4BZTbWMwRH7AmCsoB1aSrFa6X3h1/M4FW/i33zPNAGHI+c6FVXQ38
qu//ClYB9r1APoTBh/yeyXVAu+3erp6mGJ7rHmeFVl9AflrpEXeerati+VExmlx8PQ3Wj3qNLJ1X
t1gqh68ByQ18KFU37ZoOTsRaA4FFetlgv2lFl9s0OZ7+88U7pM5bXFi1bLtpLoohxkOfMbswztkm
5qKvLAvXe9Z1ev3wwKnGrBN0ruFW3jZgM+ijMmT+2sgOXFHK6++LK5STcGZxWtx7aNuYFhi+rGpo
Og2Wd9MQaM64nAlVYl+6hCzwp2mTEjAtpcnUCrKm/AuK04XtNP3PxlmliiQkpsawOLt0lzwxOrDc
0a3rEcmavUw+Pcku+0xZ1l2p482J5CJxhR7ZH2d8Dv8mfqo5LQSlsGhv2+Ul/JIPVe/6NOECfNJG
7kZuTacGenS5PyI4Z6jDicCHC8KanL6Q/4cQrO8/WPT4nyc07H3xyps+kiKfZ5t5UjQgwhDJF72m
viJ3ChStoedZ5m/tiRtQ47MZNNeveOG0+vBibAwQOu1JCyOYOykXKSgH5VeDlIhTOWFaHhVoWlXQ
fE5SIAZaGsU9fxpVWSa6SH9g5mflivuPL6NrZ2J9OfSHHqI19ZG75k1jiYf+YTOW6HfrjQiCX+jh
bAdXFSwiCwD0ZnAijvPqmG1OyNE8sPRrfahFlz1zTT/256Sz9Kcu2+4+AJ3HuX9jNXptJn6oA/vy
z1ntcysL4pj9SvWoWijn3eBpcV+B2ZCCOTb/E60Lnd5ENkCD39EJ0WOMoOcTLkdhulS5KrXgB+Ci
u7eaocNonZCCbg6i1cvCglsD5nftWgkztFYAeKiJxJVdkrmh/aGWefz0SzXOyj4BYedb43VlZOOI
QzZvfNmkLsqC3rIK89xv1qpy7jQ/UJVXskADUZotDq4YMKZBZegsnYeteJOOHzgNydZ0B8LB5ybl
zri4+f3+B4Li6y7Yzxb2/BfowKIbdik5AkguufMhnHQaz7hbL8A4cVcjMlhtm0p8oo+nmI9AVzsX
RC/J2VtU15U+xWwt8lU3cHPt+NgakwbHdKk1NRzh1MKLQA8G0L4cvxHUL60SMasf4Ordx+cg39+E
igMTcPPaLXrPfN8iCascY9i0w5vFrpS/K/+W4D28gWA41WTLHLUHxLqb23P/8xpw69B1/bmL/raq
YCEIfFwCFMjCEbTih8bpw+7qOQvsF3AQyt9+Fbr+SHr/tp1cKm/KUslqyDNhVxT7CvlhgBuuDbMl
vrfFspieZ0LAqC4Cc2l8SL5iSfR47GLg9NuadAgW4UJl58vp+ghDjw4hj0XOECT53nWSo4+HEu/h
gqAUS9OIr+JSQbwqrOZGV2c2SqYMSYsE55VNFBSAaqGHNuzfsWQfAWW0kWbQnROk42J28B8RZiT7
C4/UP7KI0r/YPBScyJ3/zMOuutAkNKJBIf7xHXBF5Nb4Gec94N41CWq1nvvrCKF8olIlT9H9Df9W
mRr32724HMk85NcDMnVymg++DFgwljfGKbVpju0mAhiwT0qsTlOS4WK9kKCfEnBPw/6qRSmx2S3y
rpiy1xU4m5f7kDk2klOaLQyV8IfPW0RDGHOJ1am8MhZ3CsBOOFg02yGkNSQEV0PF9WRwfvnMmyTY
Jd6bzk/5MCt0LKEZZfqCpo0R5E/vPjHp9sAWT1gaBsuVoDVv26XzzTpvAX3XzkVSil0Pet89SzbS
ZgnKwoa/8wOkeNZBRW+HDaV3ccF+4k15T9ITWZKOPMq3oUKlSS/JUGwefaz3nJ3J6PnCDdtrKqE7
8zzVDVyfiJA5OnM1AafFkeUSYhwGlcrSl83wHPFoGydchPIdxuyJC/PQ50MdqbwblwN5KK+Cq6FS
Zcvcl8Su/eZmctuw5uCIGCOMRx3LayvRnPWW8mRLABmWMQ2RBAURUDOB5QxAsScqfJXeY3fg6m+9
9WvLf8n49f8uOAAwBaY6f99YQu+mLZCFXAfMxVLq5+LNi5DTZsDrWqJNDIymns3jYhgyBiaz/JnR
E+A4T4pPfEfMMdHhdVwE+CFa2qImRWgcFph5edUFTbrXXCqe9cs0venmLfMwj6DFdKgsV5jxuLV2
9clCbshg+Qg6ikxmIc9Ix1mhEjlsMcbJGF0V9D+pG795qEZhYC4HgsKX6VKYHWmTCUCP4JpSRy6p
iLNxCi85ORUOCItKNdpA3ozSJamAFQjP4ztzpeXkS/HbgzPJXZOdrRTF/SaYLMGMxWk3nvtFTNY6
Rz6FeW3WUqiqENRhns5tuVfE5ZqTmCC8v42uCJX45XVrdE0np5ezyhlE9gGA5OVt3rQAjDiZRehY
3+bzXCmStfN8MuvCjdMyAdSAkOusYmaym+1DSbRrWhFEI5L5tcrdgNUiLk7hgYDouoTb0IUj8ohj
gWLXfspQH3Pw2dZC4UTTrIiTGqBNweGrijxh9dxdFjcRnbx/OwMoTVf+lRa1BN6pARd80kvecXtm
VfgISLx1+ucyq4SplDZwWSviSfvIVMPqUBN2giXWp1y+6zJLn93llM6voE+2uCI/6uSC0EFDu6hv
IoM313iIw0Su0DkOjj7u8zp7ulQeTt3NWIzp3N9NC31WFFE14vR1qNeS/ZAyajRTvWwpyGc/Kr+E
TL/S/Z3PsshvJg/510duoojvZePFuli1aBVjbML8Z6k9ViVvUo/8nAJEs+LvxS1Tz5ZnoWCvVRsY
t7j2SsLRBrGeqnlVmFshvb4OHTBd2vTTxsqkJz61CeGFOuIFPhtN+YEpPX1nh99Wlz6En+6IlJoi
P0F9GHMoxIwNnUTGG+iVtf3D0+R6jgPSsJn7uZ+yt7HJROn7xvQWxeraJ8IyCPnA8HioadN9v9mA
qqtzYX1q5AoIrgkHIJJ5/kJOnvTDmPaMpKqg6R0B+er58sBsbALYe9ddAreZ3H7ZyFkNRI1qrR0P
fegvV5gC9/dadwEwZR7EpYYcMSfgL+wdOAi7mXaKpfN2BoF3ibT3U2vwBWahgyBz1izImojgTR3M
4eqenu7cVOkp4zqgC2JXKYsbpcwtvf55vVZTxK0+L1iLGmg+MNY9P2R2ICjuOYeVC2tv7BUG+LVe
//mawzKl/qhWU6o1K7USVZqweHqY7Hkmn3GjrAAnAIIGSuQlcA5k14TksyrwiUyAiPpTXofH4Wf+
zWtxdA5tlm/afPQQsCCbnxempdhzaxPwkTdTfnWSP93sJmS6fWhnM91Iet1m2IXA+M6e71gBtnJv
Lx8t9hgJzcCq7897TNF5fJDNDAieXAAr3gktRW/tyvLNXG9Qh+dTM6DPWw+/PSiS28QzBeNwxdxw
gi/TDoHI91FM0hejpZ/B15/tHxbZLKkm60tswgrvbLUz6w0///wvFEz7/qBu0Zl9gc/sJblmigdD
eYmjvkt3QgaLv7+oCd9HvW6LvHRok3eqCFE45mTNhPXBkzwfp2V247S2nKWF9NSXxkGB2IQ0Kx9P
tMTIQUGvSjey5kyYEnpdVutzc3NPl8K2h0BAt9kh5YlRpKteNuo96KLnj66SOTptLJX+szxoLw+m
+w2Ad8a/D7hw66/XiMBxbFXuHg/pIbeXjFnx/a9tUlg8RbRZlbCNSrfZYH6bUIFZv6V8SbRlO1Ki
Zsrpz5ggVo6Jqp1DldBdywwUN0LMKYMeWRyJTofClEZTy/g2OuMvfa+0kP6kjfboNXPFWAKFK8eg
5WwWjsEvN++GM0G537sYvfek1LRwUk91P/vfxcVCU4J0e8oZejhnRXshlsMnfj8Y34rsJqll/7Hf
tEPrqz/YIAb8n61z9N9tngsiVbaocCemgkMwQSHCM6CmEUPCwCnSHwaRgYYNhSIhcbcdhLtAavw0
DmIv/kgCokP3RzcXt1SmE7VOPyAXhbZbxGK3Z6gOOhwcaX9zSzPoWkf4fQkz5kO8e972dMxwYgZz
oNUQGgPn3FLWFHMkAxNj+UcZhTKHv75CMYVNACQ2ZNNCMOKZaNnu8yKU7gkell08woYcTaxZNv6Y
/Fyyi9KTqvJBZYkeu4rheEyBfB4oHeOLzsabTS4sfMuWIyhtj1L7TJQcneiYVphhR+h8EGv7sBBi
oc7YCz+ehrQ310PuhcmNdEedZ0juNBQrgmGjx8z+T1OHyfe4k7bdrTwj9r1xQbM2X7UYh/kygy9p
L+fTmSdHaUHY4r25WU7Dk46msT/n9mVBNttItZcHwLCVx/SCS1qWQljZZSHIZXBxS80K/Jyljo5n
EA0ksnp/OnGPfeGrEJ0lkcPG+6ngGBnX/IFKX438Sp6l05G5i8TmGkUlh0o/IcMLMCjWfQUO+0Ma
kYhKZekcnhBF4jNXKmWzkAvYRzsuKdOW4GKdy9HOB3onmv9l2vJvEewtcAl4D31h90am9txblGvl
SUad+Zan1JNjC7+rhjtzegEeH+Pe5cDkt7JbgHphhj8WtYTOGnJmqQP6iFSsSgW8UjpAMBddbjQV
eAoqZTbqpKkOYfEZXSiv1HGC+KGPQIJ4dckZdplWfEVGbv6qPRDHSVO6Isn/AFrFh2qlA1KtGYPw
kZspglEfkj7DMvnyaEEvLJFmn+vVAo4IIhwzeebePFSJwuW0UC4SwfXW+mIFeIsXtxUojtciYmRi
egnof4UzZTOPjIUWQr087WtiVpHezLAvSpIjBuaypgY1Y1vKTvvxcAIlJkbfP+LoKzFmlsb9ER9x
YEh94CdQmfNGjNNpqgAz2gcCumRrtiKpzEU+90ZstCBc/llS9h9JiqlK8ogOX7tC4Aby4RZOQu15
8gpmsY+fRMaY1A7wyG6abHg+zfQnRRbBZAyU0xcThM/HZ2DF2CRTs0bDc23gn4Wd4vckx0TSm5ws
1FnV5Oj11WnkRcX4Sbula0fLSrGbNBhr+GHvJNHOHfgiY+82OG0Lzzy3r6AV0JIlmiev2dO6W4jb
/C07NuBTp5BuEhlPZDOaAAsGISUQzc34woF9AimrGhtRuZDvLTuN41YJZP5Hosky9QM9IvIHy3JI
MUSke8oozYN1iU2K/JfohI70QTsq5ngiGnpoE6nkPQrfiWzn4JWbmTpkZ5WzaUFr6ICe2n4KWIik
BvlVO8bcAmNINw5AaXr7UTEmlkVNc6zXTK8+IsOq2fNRP7ZgMKzSTyq0VYeWDyZblOegGsOypAlt
gRfJ+lS3RIUFqDKiUvV2b/x3KsxRjl2Rpz+7rKZ8Sw8D3FIlO1nrmTJsecAfTg0DE+LjdKzt/pNi
ukreYSGYYCIVLCUWpvgblXpPCYA5dChUtQxXBz+lGLjoWnMvxJS7t+cVbDnYn33W6inDDtdLr+zi
MY/+1QNQpAcWbTkUA7k3n+7flncsDlm/wySDzxhlDpmf+j3XC6U3eG4e8GYBFKfb1ysRQHnrmV9t
zUyYcm8ZT7ynk1mc5rErcKqxD4DxlswdN1aUGH6nk8DyYaLEq1FwB+mMaCq9CNSew27VvVYsbaxs
n0F/ofnjW3w3G6M/ev4lUlGVUpo6eJSbFni4g2wacjxd8SGrtAeSXPzcxbcj4T4fvnbHBhQZ4UF7
nKa75DzZS1921JBkXjedGGcQrPkFe/7IjcmPE3A14jbbVD6cl8iZh4KPnwcOGMMnx5YZpdwQAdzR
IlA1J07zQ8LI8HBDblntxNJPMcDtYVxmrIlGJBc8+SnhbWqKajV/qYaUFifutuyWDwYaVAyljr9n
vLnSOKXnHwyqMpUStahG7EzybVxzqIxNAQ2Px7lQXKTbA5nEfWG33LV65TBCryqj/EIRDFZbelVg
bmUpdF/aIiQGmjFsPEO6bHVI7iL7CCxdBLuphQsYbsko6AkGRMs+vU9/IyiAtpD4+ONQPRUnlXOx
2adv0FFmnmeXTaE9PP3ivqguiP9vMO9F6azv9t7BvnreNkTAKGFolgGqhKDs+JpsVCil74EkeAIn
VlhkEzBYZI1zWu+jSBxeSF66cDsDSqKwsrRaTMmOf7qfGwggxRILoNBY66InrVEZ6KZAD9siStiv
g4d8NQU9DVAUQgC143MrVD4DJ6Cd+HJczUl8zOhUQdFi852ezZwjAHvdJF5TyNA4aShVfSgUCMYf
iv5XyH137L0kuMdwijJExWXWG48SrAOnjjf8uoI2DapqBJTCcvlZFyoKQyvREbcONKhQqSYWXBN5
5bI+O3hgOouF8Xd7xV+pvnedIkkwLta5wvYjU0463ZnMRUiiNKaylcre1RwJlk1nwOfprG1vIAUf
94yL4YUWoBcfMbzCrx5yJD5J7r4u0uqgd660K58kOoFQyOoirpWY2x+nPFE2gcJrDTfLbpsOowgN
W1x1m4UL2cNWyrhCaKqIzFPloc3RBs3vfCHHufJNDwV0vO2aZrkziA4x/Eb/6jYTQo6IaXKIimpZ
LKhaaixxOshkRs7CoubWLo3ffhL1CWYPFA7GtKfRg7m0+uTJFuLA6NXOl5vYhEXkwJMH0Dff58ac
Beu8iquKvK/lWvoNT/sZAzWDACKOnuIt831xpBki3puiStsrq9iP6Ow28AZbzNC5bOvWzR/1QtwI
c1meafqX4A77UVV7SkmKGw6hzAgSxPdapcwgsvHIuY6yPhSiP8QzROAaZ5+VAOfUExDhfC5Fssms
NVXtMg6ZplIOqjyiNzgdg6OkzP4k25tl9IzSuxl6FabA4STD21vDKDLymzuq0RK6kk/6C2tTa8C7
qlW+CTvPqkS/RsOOcdaoT7OzD2oZD8TmB8csZqKF/+8z3LaJvOR12wSd8URdAiQ95EXw6GzEhezK
lFrTMgM8XpPSrQ+XpYdjcje9eLuIXEMzs2gccl+i6nO9wk2rpxabAKlqpHWtgAd6RpzhRzBFuujt
ywPD1o08EpWtQK8bPLiN/TLP+9Cv9/o4uWE5PZDKpDXZKUXDe+5dLbZkmCJss/IN9fv/D5dRqMhj
7hWir6Ez/W47JTn+w9D0WnD4MUb217ZOnMUYLh8qOgqMXCsRF9L8SRCgsA5ZxuaG7E5O4+Bczlek
+8hXP4IzRSrcHK7p1gvQySqwFrprSTUBlzZRkJXCBM2JUXlIO3S6IriRnbgZTDqJlzmX3hPykug3
oJOAhwmtNSS+vCVC4/09hKxcMjTsfs2/Sjlm1erFAPjV72A8BjpEIQvNV1+XeIZrc1/0MHr8pXTH
lsUfD7tsBdG9zHsRi7onaGviXo5YNIsQiJfnLNVEoe6DeEw7YwVPS60pifgaqPfTwWOPGhErlyIc
UrUpvW9Vq0Sc3Bsl9FEkkigD/sfPXT/iMD2ofM5Nja47sonJk1zsv0O/pypGdrwxl9zQOIEEB8E6
NaUqGMWz/awf76yN/Yv2dBEb1ezbKRQ25f9r0e6d+DhoXqRjCD0dUSYXHLdKl2vQQxDs0bAbWppx
nQjXQyAH94evYKnaiuOwhloFPJrgD4lqK9IyFV4CW5ezzvnB4EGRXVSsEQm02NueR9b0s8glpYR0
2aqAzlqhjWR9etiElGNwRh6ptlFfD6z4QfBd0xxw7EAvQk7V0ZhaSks2DtpUT3HZGyiMNSh7grmL
lqomAGWqn9XNzqD8uj8H05Q8wjz42yMZlWM/lkjKC7csQNgip1bFhrTqOjclg8i9VVJIbA6dLGG4
m4qbKfgOVJrAmwhZvHM1yUbM4q5SZoBiNU71G6wCyVApGqV9hh2Q0OvkWQynr2IITl8K/J2z4+ZX
z4CXSmmx6P2lihEr7hAgYg1PRxJFt8MgKfDjvSS09OqAvOL5iVVIq9bRp+0l4FDLN2plf6fgizTT
hKGl+YQWNaC5GKNtIgV2J2GY3BegqlVrviWTTfbsrySw+1/96Y8qAfpWvaIUvuGUE0LCXputvM2B
0wa2+0hBVzapn0wYyozcUWLeUuAHNcaUjcDFGjWogoU97kSx3CHtDmkKiIh77B6TvbMY1c3n2eZ8
hFJ+wgyyNNGOV2UNRcJHky3dqWpQs29GrLRa85lpfJOjJghxKx/vc+W4cxYfzUp4OSpYbUjgdiPz
KrY7oqG4K1YPtM7PbdcvMYzZU3NgElBnZSqEQsjg30f1COee2kborzNRMTAzOmqIAA7n//4dxGnX
61L72/8Tq/MVj7eF8F0Hpban6uT9Sga3rmHU6zoxuTUwzMPKTnw9JABcGEGEBXE3OFvhCWow4wI0
00oBEosPs/0E6RA0JFBcATAs8Q/hVQ2AfDYIGQ16L5NIlihdukzSWTmeXnpWs4uC7qSUdtm18e+b
06IpO8j86lCTWYRnc0a/U5B+ofJPfRJ+zgyLbD+zhW38627y9VyS25UwmTmkyMaAJS7gMRj4VBD5
Xiugzohu03CN87trO24SYjjPmw2M4lpes217jzNup7Qkh/eykItLy7jrTkmo2iAMmniKsEM+0ORG
DUaCtsy4q46Qfa1o5aP/VCWr0k+Tru5GSnv7g6rWGrKJuXpiOlO5fxfNsiYd/9/QTIgr/0yjonfe
HapWGPIjmbY2Snm1mW0wZkk66ANGRsgc+YTUQaNt7k5YEGP78uWkwIzq8aicj4ZNxqtgGdZUMHPH
JWF7Vrv5xHkF2Bw99qQv6AB6/D3HjwK7jCdXck3rlt99Wb8Qqn16aFeXisg+uPxIEdcH57vRKjK/
lQW6oaHFS9IrVc65VOCW3HsDQIUkMJO7UXeyeG+4iGdUFyBkWX9d9oxeMrEgejWgCarF6o9Eiko0
CLFncP4+oyPZM6NvYSPfjlLIVIR2kp+24fTK+htBSnv9B5qJDrS5n0Xh6SQUHuAsNIyWFAQ/frCA
5UFBoXCtEH0y8OYLokKmbEcVF4YtqYa0YxClNcAZR2mIOjGa0ydQ7aRmCj9lmFGGQDX4dX1NK4km
jes6MKcgYaJsHJiAwZKgpL3T31ASKR8jmDYQg/iB1vRmZ13JtKnZEoAyIqoCGNm8Bkic8OD1BuWT
+o2JXMFIkkhPAsSWN2MIs6FfZE7a1sCqKtWxWuemGEGX0xoiplZgEH7mhxKUrZDa
NV4=
`protect end_protected
|
gpl-3.0
|
dcliche/mdsynth
|
rtl/src/acia6850.vhd
|
1
|
34541
|
--===========================================================================--
-- --
-- Synthesizable 6850 compatible ACIA --
-- --
--===========================================================================--
--
-- File name : acia6850.vhd
--
-- Entity name : acia6850
--
-- Purpose : Implements a RS232 6850 compatible
-- Asynchronous Communications Interface Adapter (ACIA)
--
-- Dependencies : ieee.std_logic_1164
-- ieee.numeric_std
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Origins : miniUART written by Ovidiu Lupas [email protected]
--
-- Registers :
--
-- IO address + 0 Read - Status Register
--
-- Bit[7] - Interrupt Request Flag
-- Bit[6] - Receive Parity Error (parity bit does not match)
-- Bit[5] - Receive Overrun Error (new character received before last read)
-- Bit[4] - Receive Framing Error (bad stop bit)
-- Bit[3] - Clear To Send level
-- Bit[2] - Data Carrier Detect (lost modem carrier)
-- Bit[1] - Transmit Buffer Empty (ready to accept next transmit character)
-- Bit[0] - Receive Data Ready (character received)
--
-- IO address + 0 Write - Control Register
--
-- Bit[7] - Rx Interupt Enable
-- 0 - disabled
-- 1 - enabled
-- Bits[6..5] - Transmit Control
-- 0 0 - TX interrupt disabled, RTS asserted
-- 0 1 - TX interrupt enabled, RTS asserted
-- 1 0 - TX interrupt disabled, RTS cleared
-- 1 1 - TX interrupt disabled, RTS asserted, Send Break
-- Bits[4..2] - Word Control
-- 0 0 0 - 7 data, even parity, 2 stop
-- 0 0 1 - 7 data, odd parity, 2 stop
-- 0 1 0 - 7 data, even parity, 1 stop
-- 0 1 1 - 7 data, odd parity, 1 stop
-- 1 0 0 - 8 data, no parity, 2 stop
-- 1 0 1 - 8 data, no parity, 1 stop
-- 1 1 0 - 8 data, even parity, 1 stop
-- 1 1 1 - 8 data, odd parity, 1 stop
-- Bits[1..0] - Baud Control
-- 0 0 - Baud Clk divide by 1
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - Reset
--
-- IO address + 1 Read - Receive Data Register
--
-- Read when Receive Data Ready bit set
-- Read resets Receive Data Ready bit
--
-- IO address + 1 Write - Transmit Data Register
--
-- Write when Transmit Buffer Empty bit set
-- Write resets Transmit Buffer Empty Bit
--
--
-- Copyright (C) 2002 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 2000-01-15 New model
-- 1.0 Ovidiu Lupas 2000-01 Synthesis optimizations
-- 2.0 Ovidiu Lupas 2000-04 Bugs removed - the RSBusCtrl did not
-- process all possible situations
--
-- 3.0 John Kent 2002-10 Changed Status bits to match MC6805
-- Added CTS, RTS, Baud rate control & Software Reset
-- 3.1 John Kent 2003-01-05 Added Word Format control a'la mc6850
-- 3.2 John Kent 2003-07-19 Latched Data input to UART
-- 3.3 John Kent 2004-01-16 Integrated clkunit in rxunit & txunit
-- TX / RX Baud Clock now external
-- also supports x1 clock and DCD.
-- 3.4 John Kent 2005-09-13 Removed LoadCS signal.
-- Fixed ReadCS and Read
-- in miniuart_DCD_Init process
-- 3.5 John Kent 2006-11-28 Cleaned up code.
--
-- 4.0 John Kent 2007-02-03 Renamed ACIA6850
-- 4.1 John Kent 2007-02-06 Made software reset synchronous
-- 4.2 John Kent 2007-02-25 Changed sensitivity lists
-- Rearranged Reset process.
-- 4.3 John Kent 2010-06-17 Updated header
-- 4.4 John Kent 2010-08-27 Combined with ACIA_RX & ACIA_TX
-- Renamed to acia6850
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
--library unisim;
-- use unisim.vcomponents.all;
-----------------------------------------------------------------------
-- Entity for ACIA_6850 --
-----------------------------------------------------------------------
entity acia6850 is
port (
--
-- CPU Interface signals
--
clk : in std_logic; -- System Clock
rst : in std_logic; -- Reset input (active high)
cs : in std_logic; -- miniUART Chip Select
addr : in std_logic; -- Register Select
rw : in std_logic; -- Read / Not Write
data_in : in std_logic_vector(7 downto 0); -- Data Bus In
data_out : out std_logic_vector(7 downto 0); -- Data Bus Out
irq : out std_logic; -- Interrupt Request out
--
-- RS232 Interface Signals
--
RxC : in std_logic; -- Receive Baud Clock
TxC : in std_logic; -- Transmit Baud Clock
RxD : in std_logic; -- Receive Data
TxD : out std_logic; -- Transmit Data
DCD_n : in std_logic; -- Data Carrier Detect
CTS_n : in std_logic; -- Clear To Send
RTS_n : out std_logic -- Request To send
);
end acia6850; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for ACIA_6850 Interface registees
-------------------------------------------------------------------------------
architecture rtl of acia6850 is
type DCD_State_Type is (DCD_State_Idle, DCD_State_Int, DCD_State_Reset);
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
--
-- Reset signals
--
signal ac_rst : std_logic; -- Reset (Software & Hardware)
signal rx_rst : std_logic; -- Receive Reset (Software & Hardware)
signal tx_rst : std_logic; -- Transmit Reset (Software & Hardware)
--------------------------------------------------------------------
-- Status Register: StatReg
----------------------------------------------------------------------
--
-- IO address + 0 Read
--
-----------+--------+-------+--------+--------+--------+--------+--------+
-- Irq | PErr | OErr | FErr | CTS | DCD | TxRdy | RxRdy |
-----------+--------+-------+--------+--------+--------+--------+--------+
--
-- Irq - Bit[7] - Interrupt request
-- PErr - Bit[6] - Receive Parity error (parity bit does not match)
-- OErr - Bit[5] - Receive Overrun error (new character received before last read)
-- FErr - Bit[4] - Receive Framing Error (bad stop bit)
-- CTS - Bit[3] - Clear To Send level
-- DCD - Bit[2] - Data Carrier Detect (lost modem carrier)
-- TxRdy - Bit[1] - Transmit Buffer Empty (ready to accept next transmit character)
-- RxRdy - Bit[0] - Receive Data Ready (character received)
--
signal StatReg : std_logic_vector(7 downto 0) := (others => '0'); -- status register
----------------------------------------------------------------------
-- Control Register: CtrlReg
----------------------------------------------------------------------
--
-- IO address + 0 Write
--
-----------+--------+--------+--------+--------+--------+--------+--------+
-- RxIE |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
-----------+--------+--------+--------+--------+--------+--------+--------+
-- RxIEnb - Bit[7]
-- 0 - Rx Interrupt disabled
-- 1 - Rx Interrupt enabled
-- TxCtl - Bits[6..5]
-- 0 1 - Tx Interrupt Enable
-- 1 0 - RTS high
-- WdFmt - Bits[4..2]
-- 0 0 0 - 7 data, even parity, 2 stop
-- 0 0 1 - 7 data, odd parity, 2 stop
-- 0 1 0 - 7 data, even parity, 1 stop
-- 0 1 1 - 7 data, odd parity, 1 stop
-- 1 0 0 - 8 data, no parity, 2 stop
-- 1 0 1 - 8 data, no parity, 1 stop
-- 1 1 0 - 8 data, even parity, 1 stop
-- 1 1 1 - 8 data, odd parity, 1 stop
-- BdCtl - Bits[1..0]
-- 0 0 - Baud Clk divide by 1
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - reset
signal CtrlReg : std_logic_vector(7 downto 0) := (others => '0'); -- control register
----------------------------------------------------------------------
-- Receive Register
----------------------------------------------------------------------
--
-- IO address + 1 Read
--
signal RxReg : std_logic_vector(7 downto 0) := (others => '0');
----------------------------------------------------------------------
-- Transmit Register
----------------------------------------------------------------------
--
-- IO address + 1 Write
--
signal TxReg : std_logic_vector(7 downto 0) := (others => '0');
signal TxDat : std_logic := '1'; -- Transmit data bit
signal TxRdy : std_logic := '0'; -- Transmit buffer empty
signal RxRdy : std_logic := '0'; -- Receive Data ready
--
signal FErr : std_logic := '0'; -- Frame error
signal OErr : std_logic := '0'; -- Output error
signal PErr : std_logic := '0'; -- Parity Error
--
signal TxIE : std_logic := '0'; -- Transmit interrupt enable
signal RxIE : std_logic := '0'; -- Receive interrupt enable
--
signal RxRd : std_logic := '0'; -- Read receive buffer
signal TxWr : std_logic := '0'; -- Write Transmit buffer
signal StRd : std_logic := '0'; -- Read status register
--
signal DCDState : DCD_State_Type; -- DCD Reset state sequencer
signal DCDDel : std_logic := '0'; -- Delayed DCD_n
signal DCDEdge : std_logic := '0'; -- Rising DCD_N Edge Pulse
signal DCDInt : std_logic := '0'; -- DCD Interrupt
signal BdFmt : std_logic_vector(1 downto 0) := "00"; -- Baud Clock Format
signal WdFmt : std_logic_vector(2 downto 0) := "000"; -- Data Word Format
-----------------------------------------------------------------------------
-- RX Signals
-----------------------------------------------------------------------------
type RxStateType is ( RxState_Wait, RxState_Data, RxState_Parity, RxState_Stop );
signal RxState : RxStateType; -- receive bit state
signal RxDatDel0 : Std_Logic := '0'; -- Delayed Rx Data
signal RxDatDel1 : Std_Logic := '0'; -- Delayed Rx Data
signal RxDatDel2 : Std_Logic := '0'; -- Delayed Rx Data
signal RxDatEdge : Std_Logic := '0'; -- Rx Data Edge pulse
signal RxClkDel : Std_Logic := '0'; -- Delayed Rx Input Clock
signal RxClkEdge : Std_Logic := '0'; -- Rx Input Clock Edge pulse
signal RxStart : Std_Logic := '0'; -- Rx Start request
signal RxEnable : Std_Logic := '0'; -- Rx Enabled
signal RxClkCnt : Std_Logic_Vector(5 downto 0) := (others => '0'); -- Rx Baud Clock Counter
signal RxBdClk : Std_Logic := '0'; -- Rx Baud Clock
signal RxBdDel : Std_Logic := '0'; -- Delayed Rx Baud Clock
signal RxReq : Std_Logic := '0'; -- Rx Data Valid
signal RxAck : Std_Logic := '0'; -- Rx Data Valid
signal RxParity : Std_Logic := '0'; -- Calculated RX parity bit
signal RxBitCount : Std_Logic_Vector(2 downto 0) := (others => '0'); -- Rx Bit counter
signal RxShiftReg : Std_Logic_Vector(7 downto 0) := (others => '0'); -- Shift Register
-----------------------------------------------------------------------------
-- TX Signals
-----------------------------------------------------------------------------
type TxStateType is ( TxState_Idle, TxState_Start, TxState_Data, TxState_Parity, TxState_Stop );
signal TxState : TxStateType; -- Transmitter state
signal TxClkDel : Std_Logic := '0'; -- Delayed Tx Input Clock
signal TxClkEdge : Std_Logic := '0'; -- Tx Input Clock Edge pulse
signal TxClkCnt : Std_Logic_Vector(5 downto 0) := (others => '0'); -- Tx Baud Clock Counter
signal TxBdClk : Std_Logic := '0'; -- Tx Baud Clock
signal TxBdDel : Std_Logic := '0'; -- Delayed Tx Baud Clock
signal TxReq : std_logic := '0'; -- Request transmit start
signal TxAck : std_logic := '0'; -- Acknowledge transmit start
signal TxParity : Std_logic := '0'; -- Parity Bit
signal TxBitCount : Std_Logic_Vector(2 downto 0) := (others => '0'); -- Data Bit Counter
signal TxShiftReg : Std_Logic_Vector(7 downto 0) := (others => '0'); -- Transmit shift register
begin
---------------------------------------------------------------
-- ACIA Reset may be hardware or software
---------------------------------------------------------------
acia_reset : process( clk, rst, ac_rst, dcd_n )
begin
--
-- ACIA reset Synchronous
-- Includes software reset
--
if falling_edge(clk) then
ac_rst <= (CtrlReg(1) and CtrlReg(0)) or rst;
end if;
-- Receiver reset
rx_rst <= ac_rst or DCD_n;
-- Transmitter reset
tx_rst <= ac_rst;
end process;
-----------------------------------------------------------------------------
-- Generate Read / Write strobes.
-----------------------------------------------------------------------------
acia_read_write : process(clk, ac_rst)
begin
if falling_edge(clk) then
if rst = '1' then
CtrlReg(1 downto 0) <= "11";
CtrlReg(7 downto 2) <= (others => '0');
TxReg <= (others => '0');
RxRd <= '0';
TxWr <= '0';
StRd <= '0';
else
RxRd <= '0';
TxWr <= '0';
StRd <= '0';
if cs = '1' then
if Addr = '0' then -- Control / Status register
if rw = '0' then -- write control register
CtrlReg <= data_in;
else -- read status register
StRd <= '1';
end if;
else -- Data Register
if rw = '0' then -- write transmiter register
TxReg <= data_in;
TxWr <= '1';
else -- read receiver register
RxRd <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- ACIA Status Register
-----------------------------------------------------------------------------
acia_status : process( clk )
begin
if falling_edge( clk ) then
StatReg(0) <= RxRdy; -- Receive Data Ready
StatReg(1) <= TxRdy and (not CTS_n); -- Transmit Buffer Empty
StatReg(2) <= DCDInt; -- Data Carrier Detect
StatReg(3) <= CTS_n; -- Clear To Send
StatReg(4) <= FErr; -- Framing error
StatReg(5) <= OErr; -- Overrun error
StatReg(6) <= PErr; -- Parity error
StatReg(7) <= (RxIE and RxRdy) or
(RxIE and DCDInt) or
(TxIE and TxRdy);
end if;
end process;
-----------------------------------------------------------------------------
-- ACIA Transmit Control
-----------------------------------------------------------------------------
acia_control : process(CtrlReg, TxDat)
begin
case CtrlReg(6 downto 5) is
when "00" => -- Disable TX Interrupts, Assert RTS
TxD <= TxDat;
TxIE <= '0';
RTS_n <= '0';
when "01" => -- Enable TX interrupts, Assert RTS
TxD <= TxDat;
TxIE <= '1';
RTS_n <= '0';
when "10" => -- Disable Tx Interrupts, Clear RTS
TxD <= TxDat;
TxIE <= '0';
RTS_n <= '1';
when "11" => -- Disable Tx interrupts, Assert RTS, send break
TxD <= '0';
TxIE <= '0';
RTS_n <= '0';
when others =>
null;
end case;
RxIE <= CtrlReg(7);
WdFmt <= CtrlReg(4 downto 2);
BdFmt <= CtrlReg(1 downto 0);
end process;
---------------------------------------------------------------
-- Set Data Output Multiplexer
--------------------------------------------------------------
acia_data_mux : process(Addr, RxReg, StatReg)
begin
if Addr = '1' then
data_out <= RxReg; -- read receiver register
else
data_out <= StatReg; -- read status register
end if;
end process;
irq <= StatReg(7);
---------------------------------------------------------------
-- Data Carrier Detect Edge rising edge detect
---------------------------------------------------------------
acia_dcd_edge : process( clk, ac_rst )
begin
if falling_edge(clk) then
if ac_rst = '1' then
DCDDel <= '0';
DCDEdge <= '0';
else
DCDDel <= DCD_n;
DCDEdge <= DCD_n and (not DCDDel);
end if;
end if;
end process;
---------------------------------------------------------------
-- Data Carrier Detect Interrupt
---------------------------------------------------------------
-- If Data Carrier is lost, an interrupt is generated
-- To clear the interrupt, first read the status register
-- then read the data receive register
acia_dcd_int : process( clk, ac_rst )
begin
if falling_edge(clk) then
if ac_rst = '1' then
DCDInt <= '0';
DCDState <= DCD_State_Idle;
else
case DCDState is
when DCD_State_Idle =>
-- DCD Edge activates interrupt
if DCDEdge = '1' then
DCDInt <= '1';
DCDState <= DCD_State_Int;
end if;
when DCD_State_Int =>
-- To reset DCD interrupt,
-- First read status
if StRd = '1' then
DCDState <= DCD_State_Reset;
end if;
when DCD_State_Reset =>
-- Then read receive register
if RxRd = '1' then
DCDInt <= '0';
DCDState <= DCD_State_Idle;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
---------------------------------------------------------------------
-- Receiver Clock Edge Detection
---------------------------------------------------------------------
-- A rising edge will produce a one clock cycle pulse
--
acia_rx_clock_edge : process( clk, rx_rst )
begin
if falling_edge(clk) then
if rx_rst = '1' then
RxClkDel <= '0';
RxClkEdge <= '0';
else
RxClkDel <= RxC;
RxClkEdge <= (not RxClkDel) and RxC;
end if;
end if;
end process;
---------------------------------------------------------------------
-- Receiver Data Edge Detection
---------------------------------------------------------------------
-- A falling edge will produce a pulse on RxClk wide
--
acia_rx_data_edge : process( clk, rx_rst )
begin
if falling_edge(clk) then
if rx_rst = '1' then
RxDatDel0 <= '0';
RxDatDel1 <= '0';
RxDatDel2 <= '0';
RxDatEdge <= '0';
else
RxDatDel0 <= RxD;
RxDatDel1 <= RxDatDel0;
RxDatDel2 <= RxDatDel1;
RxDatEdge <= RxDatDel0 and (not RxD);
end if;
end if;
end process;
---------------------------------------------------------------------
-- Receiver Start / Stop
---------------------------------------------------------------------
-- Enable the receive clock on detection of a start bit
-- Disable the receive clock after a byte is received.
--
acia_rx_start_stop : process( clk, rx_rst )
begin
if falling_edge(clk) then
if rx_rst = '1' then
RxEnable <= '0';
RxStart <= '0';
elsif (RxEnable = '0') and (RxDatEdge = '1') then
-- Data Edge detected
RxStart <= '1'; -- Request Start and
RxEnable <= '1'; -- Enable Receive Clock
elsif (RxStart = '1') and (RxAck = '1') then
-- Data is being received
RxStart <= '0'; -- Reset Start Request
elsif (RxStart = '0') and (RxAck = '0') then
-- Data has now been received
RxEnable <= '0'; -- Disable Receiver until next Start Bit
end if;
end if;
end process;
---------------------------------------------------------------------
-- Receiver Clock Divider
---------------------------------------------------------------------
-- Hold the Rx Clock divider in reset when the receiver is disabled
-- Advance the count only on a rising Rx clock edge
--
acia_rx_clock_divide : process( clk, rx_rst )
begin
if falling_edge(clk) then
if rx_rst = '1' then
RxClkCnt <= (others => '0');
elsif RxDatEdge = '1' then
-- reset on falling data edge
RxClkCnt <= (others => '0');
elsif RxClkEdge = '1' then
-- increment count on Clock edge
RxClkCnt <= RxClkCnt + "000001";
end if;
end if;
end process;
---------------------------------------------------------------------
-- Receiver Baud Clock Selector
---------------------------------------------------------------------
-- BdFmt
-- 0 0 - Baud Clk divide by 1
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - Reset
--
acia_rx_baud_clock_select : process( BdFmt, RxC, RxClkCnt )
begin
case BdFmt is
when "00" => -- Div by 1
RxBdClk <= RxC;
when "01" => -- Div by 16
RxBdClk <= RxClkCnt(3);
when "10" => -- Div by 64
RxBdClk <= RxClkCnt(5);
when others => -- Software Reset
RxBdClk <= '0';
end case;
end process;
---------------------------------------------------------------------
-- Receiver process
---------------------------------------------------------------------
-- WdFmt - Bits[4..2]
-- 0 0 0 - 7 data, even parity, 2 stop
-- 0 0 1 - 7 data, odd parity, 2 stop
-- 0 1 0 - 7 data, even parity, 1 stop
-- 0 1 1 - 7 data, odd parity, 1 stop
-- 1 0 0 - 8 data, no parity, 2 stop
-- 1 0 1 - 8 data, no parity, 1 stop
-- 1 1 0 - 8 data, even parity, 1 stop
-- 1 1 1 - 8 data, odd parity, 1 stop
acia_rx_receive : process( clk, rst )
begin
if falling_edge( clk ) then
if rx_rst = '1' then
FErr <= '0';
OErr <= '0';
PErr <= '0';
RxShiftReg <= (others => '0'); -- Reset Shift register
RxReg <= (others => '0');
RxParity <= '0'; -- reset Parity bit
RxAck <= '0'; -- Receiving data
RxBitCount <= (others => '0');
RxState <= RxState_Wait;
else
RxBdDel <= RxBdClk;
if RxBdDel = '0' and RxBdClk = '1' then
case RxState is
when RxState_Wait =>
RxShiftReg <= (others => '0'); -- Reset Shift register
RxParity <= '0'; -- Reset Parity bit
if WdFmt(2) = '0' then -- WdFmt(2) = '0' => 7 data bits
RxBitCount <= "110";
else -- WdFmt(2) = '1' => 8 data bits
RxBitCount <= "111";
end if;
if RxDatDel2 = '0' then -- look for start bit
RxState <= RxState_Data; -- if low, start reading data
end if;
when RxState_Data => -- Receiving data bits
RxShiftReg <= RxDatDel2 & RxShiftReg(7 downto 1);
RxParity <= RxParity xor RxDatDel2;
RxAck <= '1'; -- Flag receive in progress
RxBitCount <= RxBitCount - "001";
if RxBitCount = "000" then
if WdFmt(2) = '0' then -- WdFmt(2) = '0' => 7 data
RxState <= RxState_Parity; -- 7 bits always has parity
elsif WdFmt(1) = '0' then -- WdFmt(2) = '1' => 8 data
RxState <= RxState_Stop; -- WdFmt(1) = '0' => no parity
PErr <= '0'; -- Reset Parity Error
else
RxState <= RxState_Parity; -- WdFmt(1) = '1' => 8 data + parity
end if;
end if;
when RxState_Parity => -- Receive Parity bit
if WdFmt(2) = '0' then -- if 7 data bits, shift parity into MSB
RxShiftReg <= RxDatDel2 & RxShiftReg(7 downto 1); -- 7 data + parity
end if;
if RxParity = (RxDatDel2 xor WdFmt(0)) then
PErr <= '1'; -- If parity not the same flag error
else
PErr <= '0';
end if;
RxState <= RxState_Stop;
when RxState_Stop => -- stop bit (Only one required for RX)
RxAck <= '0'; -- Flag Receive Complete
RxReg <= RxShiftReg;
if RxDatDel2 = '1' then -- stop bit expected
FErr <= '0'; -- yes, no framing error
else
FErr <= '1'; -- no, framing error
end if;
if RxRdy = '1' then -- Has previous data been read ?
OErr <= '1'; -- no, overrun error
else
OErr <= '0'; -- yes, no over run error
end if;
RxState <= RxState_Wait;
when others =>
RxAck <= '0'; -- Flag Receive Complete
RxState <= RxState_Wait;
end case;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------
-- Receiver Read process
---------------------------------------------------------------------
acia_rx_read : process( clk, rst, RxRdy )
begin
if falling_edge(clk) then
if rx_rst = '1' then
RxRdy <= '0';
RxReq <= '0';
elsif RxRd = '1' then
-- Data was read,
RxRdy <= '0'; -- Reset receive full
RxReq <= '1'; -- Request more data
elsif RxReq = '1' and RxAck = '1' then
-- Data is being received
RxReq <= '0'; -- reset receive request
elsif RxReq = '0' and RxAck = '0' then
-- Data now received
RxRdy <= '1'; -- Flag RxRdy and read Shift Register
end if;
end if;
end process;
---------------------------------------------------------------------
-- Transmit Clock Edge Detection
-- A falling edge will produce a one clock cycle pulse
---------------------------------------------------------------------
acia_tx_clock_edge : process( Clk, tx_rst )
begin
if falling_edge(clk) then
if tx_rst = '1' then
TxClkDel <= '0';
TxClkEdge <= '0';
else
TxClkDel <= TxC;
TxClkEdge <= TxClkDel and (not TxC);
end if;
end if;
end process;
---------------------------------------------------------------------
-- Transmit Clock Divider
-- Advance the count only on an input clock pulse
---------------------------------------------------------------------
acia_tx_clock_divide : process( clk, tx_rst )
begin
if falling_edge(clk) then
if tx_rst = '1' then
TxClkCnt <= (others=>'0');
elsif TxClkEdge = '1' then
TxClkCnt <= TxClkCnt + "000001";
end if;
end if;
end process;
---------------------------------------------------------------------
-- Transmit Baud Clock Selector
---------------------------------------------------------------------
acia_tx_baud_clock_select : process( BdFmt, TxClkCnt, TxC )
begin
-- BdFmt
-- 0 0 - Baud Clk divide by 1
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - reset
case BdFmt is
when "00" => -- Div by 1
TxBdClk <= TxC;
when "01" => -- Div by 16
TxBdClk <= TxClkCnt(3);
when "10" => -- Div by 64
TxBdClk <= TxClkCnt(5);
when others => -- Software reset
TxBdClk <= '0';
end case;
end process;
-----------------------------------------------------------------------------
-- Implements the Tx unit
-----------------------------------------------------------------------------
-- WdFmt - Bits[4..2]
-- 0 0 0 - 7 data, even parity, 2 stop
-- 0 0 1 - 7 data, odd parity, 2 stop
-- 0 1 0 - 7 data, even parity, 1 stop
-- 0 1 1 - 7 data, odd parity, 1 stop
-- 1 0 0 - 8 data, no parity, 2 stop
-- 1 0 1 - 8 data, no parity, 1 stop
-- 1 1 0 - 8 data, even parity, 1 stop
-- 1 1 1 - 8 data, odd parity, 1 stop
acia_tx_transmit : process( clk, tx_rst)
begin
if falling_edge(clk) then
if tx_rst = '1' then
TxDat <= '1';
TxShiftReg <= (others=>'0');
TxParity <= '0';
TxBitCount <= (others=>'0');
TxAck <= '0';
TxState <= TxState_Idle;
else
TxBdDel <= TxBdClk;
-- On rising edge of baud clock, run the state machine
if TxBdDel = '0' and TxBdClk = '1' then
case TxState is
when TxState_Idle =>
TxDat <= '1';
if TxReq = '1' then
TxShiftReg <= TxReg; -- Load Shift reg with Tx Data
TxAck <= '1';
TxState <= TxState_Start;
end if;
when TxState_Start =>
TxDat <= '0'; -- Start bit
TxParity <= '0';
if WdFmt(2) = '0' then
TxBitCount <= "110"; -- 7 data + parity
else
TxBitCount <= "111"; -- 8 data
end if;
TxState <= TxState_Data;
when TxState_Data =>
TxDat <= TxShiftReg(0);
TxShiftReg <= '1' & TxShiftReg(7 downto 1);
TxParity <= TxParity xor TxShiftReg(0);
TxBitCount <= TxBitCount - "001";
if TxBitCount = "000" then
if (WdFmt(2) = '1') and (WdFmt(1) = '0') then
if WdFmt(0) = '0' then -- 8 data bits
TxState <= TxState_Stop; -- 2 stops
else
TxAck <= '0';
TxState <= TxState_Idle; -- 1 stop
end if;
else
TxState <= TxState_Parity; -- parity
end if;
end if;
when TxState_Parity => -- 7/8 data + parity bit
if WdFmt(0) = '0' then
TxDat <= not(TxParity); -- even parity
else
TxDat <= TxParity; -- odd parity
end if;
if WdFmt(1) = '0' then
TxState <= TxState_Stop; -- 2 stops
else
TxAck <= '0';
TxState <= TxState_Idle; -- 1 stop
end if;
when TxState_Stop => -- first of two stop bits
TxDat <= '1';
TxAck <= '0';
TxState <= TxState_Idle;
end case;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------
-- Transmitter Write process
---------------------------------------------------------------------
acia_tx_write : process( clk, tx_rst, TxWr, TxReq, TxAck )
begin
if falling_edge(clk) then
if tx_rst = '1' then
TxRdy <= '0';
TxReq <= '0';
elsif TxWr = '1' then
-- Data was read,
TxRdy <= '0'; -- Reset transmit empty
TxReq <= '1'; -- Request data transmit
elsif TxReq = '1' and TxAck = '1' then -- Data is being transmitted
TxReq <= '0'; -- reset transmit request
elsif TxReq = '0' and TxAck = '0' then -- Data transmitted
TxRdy <= '1'; -- Flag TxRdy
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00619.vhd
|
1
|
11470
|
-- NEED RESULT: ARCH00619: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00619: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00619.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00619.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00619: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00619: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00619: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00619: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00619: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00619: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00619
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00619(ARCH00619)
-- ENT00619_Test_Bench(ARCH00619_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00619 is
end ENT00619 ;
--
--
architecture ARCH00619 of ENT00619 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr3_vector_select : select_type := 1 ;
--
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
procedure P1
(signal s_st_arr2_vector : in st_arr2_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
-- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns ;
--
when 4
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00619" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00619" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr2_vector_cnt + 1 ;
--
end ;
--
procedure P2
(signal s_st_arr3_vector : in st_arr3_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr3_vector_cnt is
when 0
=> null ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
-- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns ;
--
when 4
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00619" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00619" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr3_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr3_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_arr2_vector ,
st_arr2_vector_select ,
s_st_arr2_vector_savt ,
chk_st_arr2_vector ,
s_st_arr2_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb)(highb,false) <= transport
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb)(highb,false) after 5 ns when 3 ;
--
CHG2 :
P2(
s_st_arr3_vector ,
st_arr3_vector_select ,
s_st_arr3_vector_savt ,
chk_st_arr3_vector ,
s_st_arr3_vector_cnt ) ;
--
PGEN_CHKP_2 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_arr3_vector_select select
s_st_arr3_vector(highb)(lowb,true) <= transport
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns
when 1,
--
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns
when 2,
--
c_st_arr3_vector_1(highb)(lowb,true) after 5 ns when 3 ;
--
end ARCH00619 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00619_Test_Bench is
end ENT00619_Test_Bench ;
--
--
architecture ARCH00619_Test_Bench of ENT00619_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00619 ( ARCH00619 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00619_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_status_flags_ss.vhd
|
9
|
17955
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
f2+u8rrKz+aRj2l97hS/lgQYsNHnPNXGUhkhHOtp35Q1MZZbGQ/InkVJ9iM99NSrspoaaHjQ8YbX
RBsHYdSqRg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RHoEjL1eMTFznVV16U9m20PUhZfShaTI/uXl3wndj38r/6kf4mlAyxDMEl3a69bnOJrNsrUlhJOP
7T961sKqAatosnanTctgWqebY0w/xnFcoHWaY+FkgOil7Jf5fsi2RdBRqiwB1mga+89dNGjNvsr1
MFLz6HnG5RFmCwPK5VI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IvIAiqJ9vqoTsn+b8o5LAzP+7/YlesJxxrJkFHckI3zj38rsBtZ44o574tFhmNEipNlSvYoUAzdR
yYcYkQRU0sg5BKgDcqJF7g7cIk9XWVUJxsXmWdjWFndlgoGdPmBJuQ7tT8+ZpnzQrEIpZsdRIJxT
7jf2QnT7mlskURjOFRq4di8G3NxXmVd6A5xDxcLONKno9PrxKVxafOf9zwbpYa4pV/C2w6cYhb//
ME4sgq3GI/KN5fAkkemoGpYBQlh1dStq0M1DzrYNoml+FtGwViZMePmOte7RtwxwUlnf8yCbdM1B
Nb+abaTawUW98/RoLEIztUJD9xd/jWhgHW3MxQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
fyYO86Tzw/quZ4ar8LXSBSVrPSyKwH+hJuSFhYQbacrYEk2hEnV10SGXpWfRh0flPn3JTXAltLQO
Ndt+XhT3xCoZTmWbSwYdJPNaYrDeCXG28zl6Ue7bKu7XytaJuBPCdHFqITYyoiedxSyGxLWOno4U
328r5Pbuxwy4+nBqxQw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KSbKYK1S/TunYdw+Z+kzk7bOuAFWgrxZ3D4/AwHbTt7U+4nRhRnL+GS+YxFGzIrGqIgBchZA5rDf
3yivmzsJJgD+M7mbH64DEaTqM9l7Ya7wyEZ7e0O975v9baKCG2kg1duJDwbh6h3AjL7mWT8+UUM2
p/zO/nhfjf7vRI1dNJEMEolnvUpT3dyt3SaVa5Lzs8qSx3oopl14iLO/v06IlQY1wNZvSJGFzjCI
xz4asUemg1SX1/UHrl3lDYzXKWFV2OCfhDXz9VGxYV/wO9b6JnRzOndZroKfg1oehFUmN7zteu9L
sZRN51atDolmOLf3hKO51qva8oK6MmvfDkSIJQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11552)
`protect data_block
P79w0YVbuzBvOaqJNymjZs6O5mlDxSv6DVmKrRmhIcYWT1pLlm5H3FtaHN3tBype7hkyq0AoTyA5
veK5JE0LlzJ56u5Uv3OD+GYvgMlW5SHTLZr02lfT+31/NQnYx7x3//msJUmpcqKj/5qKwPUrmdzp
89LK9yiwUvNc8d2E+Sr3PKzXir8fz/luPwVz4qoigH0Ib/EeOvth8E1eO0lHyu8YOEaEs63r3iW3
1IFHwtzk5jWUYlZo+vSMxkvRH3uKhjVU5He3qR1nfSRzDXW0RxCluxXI+vvtC5yq+daMU1n3rXyt
CTfLFao+BicLXdxaCAe62w49xXEuTYxIWMJdpIsnPMtttyfe1mk90pV8VFypceg/1dK0fskLrKAH
vIaMZBrKrsTVA3K3ZeA74NT7tyZaB/cKuPOK5FCJrjfMvPTzFN45raH4VE/2hil4mNy8mA3rDLqm
pQSzrE8A7qMCa+kOkWY6OW3nOhxIWHuk8/rP4suqXLzV4QjIpXsswEo20sDM6AxaxOt5xwuyzNXR
8dnrKzO4TyLac39i/mIfUFXzKSNVjWx+R4QAtOk1vC1QWgXW7MjUvSFaSJ/dY0w570iBk8AG/uD2
pOhjTB06BLLXZ6llFaUz5iSgWbm+qMniXcWZX6SP64baSLh9aHJr4KxciJJO0OFPRIPGfojYf1CG
J+OgYE0Wx6D3Huqjx38+KOARl1kZzEuvBL8rhqCeK1biUskbXmWb8U9bumNlFpF2PTj9Ve3uO10J
+n4dfk3IVIm079I4E9gV1gC2RSttoty0fJ1kfvs4s5AMF+ivk9Qmru1cQd3j5WKYYjlHC2MfFv8D
LjU+OCufScL6grGfjlQPNMvCv3zkzyDp2sPWIXlhvTtImUZv3IH5z2okmfeNlV2+UBI5y6GmN2E8
Z+Rb+XiQzqxxp1g9Qyt09bYdzNfSLxSD2LlwGgG42FltJRzT5r4U002wnzmoWsd1TB8gc0C1dYGq
FWe0TigjywC0zwqDtymwZHTS/Xx/gqo+t9CN33PPJvzfuCj1S8SHbFcJtxGJOy7zDmk0k9bCR/lW
dF5mTqjGzQAlnZm5W8Wi5Fu9Im2vJZ0Qz1b29JwmyA+gnEKp8JHJASMOezvOyCWHC+CqLyzGO1OL
sBLlM4/kSsRBr97vT9+iAQzxzr6zpSIxD005+ec/CqMVPeLwXgk1dRK5m3jsPVPZ5s8vBTYWqnud
JeN4C+B62EKCA6lC96v32S41MSpu/Vvn4kS5P5MLnHtnLVHLb6IDNfFW8PCR2zAFuIP+vG+uuQnN
odZzF/f/jvZE/ZR92bz+xEn3l+5AJI1YdxqC/zO/LOf9oeGCmsF0Bsw4/VoSdOK0tRqbrxBehYla
oFN42XOamO4uK33vTF5xO423DLmBSzt6gMVa6LJbwyB8kje6yzKZME+zjaYH3Np9BcD45NGDsDbP
rE05EsawESnSf8doL8RuKqWMsmSwowjvQ9xSFMWcA6CqA0Kj3/sNLChdHt0kopAULWa3qczDTV68
bNpc8yiHl5/boRu2uGISYZ3t051pOufotVpz3fQvQfwt93T8MXkrekofCCkmgTt3dNVtjGAL47EZ
M6RJv2xpHqRQrNkuGoUKSvPHFZDUw0or5YbIDt4HC8Po24qGcKZpnFAuxrzFQXkJUlz3g8hWZBha
xBulUynBt8vhmwho1W8tsOw0ripy6FRB7/9mnxeK2rYDSFVgJ206iOAyXVT91blDcQjTGCrT01eC
69ffIiNTQxQYeUdnacZW2P1Oc+fLktWAJXLe8Hewx7Isw8hVYlk0CN/4nvVHzP5zANweiwkRx49U
XmDSjKr5oBHuigPGRRf1a3qhFLaMfXq+RcIfK6C2bYIQLC406ViH4EqibbBQgEd1GNFWhhkj8j3S
z+jVoS9uzW6XTn3l7Od9b+KuWlik/aWGVbaSBtYiZhuWZEUgiTD3Ji1d4QSWiSdVBsHsCEKokATO
4d6pJejQX3QKqD0SE4z//iyCIp7+KeSLih3Fs0GASN7P/8QTAh6xTZRpWC9iCzkhWe5rELJfPQvx
Pd/t5L2kD1n6arnXIpGR4o95A1VmN5qaNvMQja6JWyt+3kXIgTGpZ9gn1Wrpns3H/JRjw2jM4WN6
Bfhm4H2wTqPJPpupNKX+27Wx2Qs5xxsaE+6+l1XbtQDogsJwHzWZun2MtaUJUpjq8Jlr32XpqvNd
dLdNafta2KS7Q5MMweFBUMv1t0t/aqCKXXq5sJRx9n0q3Am//Hb3SVss7uUqHwOj+s3ji7txRrlS
2WJSJHmsTmpEi2F65Yi1rILQmZn6VXNTTi+OFXW5qBvO3dio2Sig+FodYe0s6u6Wdb/y8z0n3Sc7
p+GLbzFuZ083yO3yl67/V8iSaIKizNduWDXIUwawNB3WAkauQmKfv8cBolIGbONQo1pSaIOu+Rn4
FC5180kn6d3SpYqL/4wfbeCDAVJS5aVW0MQ1JnJODsPOdm+gEhlN2u+XWB/LVYRkbFP0Wsr4a/Y1
s9ASrVFUVbM12RWGCVfvr5VtkLU7EXNxA+TRr+RQADVulC2/wBbgUx1Cp2SXXo4dyY0CP4YMprRZ
dGCCo/EIchPdPjBfm/hVKz3axxDfvP964liWX6S6KHFH5evxYIpw1JoycyhGzwc4hVIoLs5zixtU
moTE028Sjsn3lyHNtCrQlVKesm6eARhO0lMkjDc82A4Tgr6VC2d0yfILQx+nKQ5wttijTLwwz94t
jhy4I0zDACPEOoQgdfxVIMmMSRrQkzruNdkH6Q8O6560FrmkTHEjN8liL/jdJ3yhU+XT+0xFKQPg
D9mCbt5YpVJJG/nSpItJvQPPCbrzg4W0p5RMEYvyZeDh2I39NxiwvDQ1sR3ztYxv42TrsonGePlS
utTkO/jot8fwOHc013ATq7UIzYw4Tr3OiXQqAme+RY36OL2tgM17xxey8dMED+gXJghf++g4CjBY
H7LT978m/7CEqwtQ1OOmVfX/sh3a5nBFEHlRXYDUrhTKdRMvAPuebuAJv6i0X5C8LAjfpFgffPBu
J/7mApNpNRpTC4ASl3hWBabvgVcMBZqKS6j6SiQCx85IRAo9U9eVf2h60jl0f/NIwDwVez1AFeUH
1/zd4bZNTeM5/B3gVY4P0JpxorWcbmfc3Hy60f65A9mvOuLoQudRgGNofmEWWGJtek5ZQrJCBKZk
RVbhFVZHUrPMjyM//5SOwz5lnlf88zIVBCCbKmwhxWC4lhr1RutyDkKqWLQwbrc3Q/chZ6XiaUJJ
d2VRx0pKfKyc5pr1UmDnK/swNhtzsUs7wcCSsJHu+fuS5O0suSMXaFISZcyQ9tZZZunbjlAYkr/j
Kn83aXT/pBI/rr1Poh9zhUkxbtvYSlH0BE9d+9Yozvam/nKI+l47P+QGJvU+8m2iqXRmNTO9IBDF
MFBZDTUxrg64YlcBoM5gsBodI0lE1a0vN47tbN3QdtYqwjGV+lsoMc8KRiXK+fS1CCsM4bY5PuIe
CwYr6zsv+TFd3cVwjKDqtjkB5f/Ep51huTF9YSeHN/EjJEAGD8UNrScQSacRelRi3t3zo/MD3PHR
cbXkdV1Du4NZpyJoA0Vssk/ZP3nxQNu67vQ54Y/fckvop1ey28KNvzPnYofJaIA+hwH7XrKtuUI1
6T52KeDNKaMfg5q4KoehJHd7yUg/JI2ZRYBCLD0WdL6KTr9K46Ce3nx8ChB84o2PW3RPlTGn5T6o
AZx1b5t9kkvz9l7GeB4H8fSvJUOajCchFpZvcyDaLlW3hjKH8Rh+F26WgXBEtEbC9YMBFMiOXiXm
niEY01rLJTUcrb1rbSjYB1AbbD4ddrfjvEZSkiBx9BRsT1XIPQbylv8vVWld5gHtJRnEseKHNioY
4aGI8BC4/oo55opmYDa4JTdapBM9jxl37Xhxeb8SRRQLjWdrRXPFDzEBZ49rc96NKYKr0yoZirYO
87ebAuDDIug34wfcqDMuuUi75fVTeXKYgqKlO3wOHcmn2Mpd3hM8Rf92xMWsGKskd/ewvJ1GUHvm
HGmZjE1i4cPBICn/EWYCnQ1F8UZSW4QHakqjZrofhSf11U4uh7Dck7h9JuGKJeWVthDBBfTp1tNV
RTPd75w9p99ZSyhuH3lMJhKFvHs+8oymuiIY07uUS359isgkv+YWjmhHCfy29HhU6ThUj7P0FZhu
eHlMvd+vYfwvG7KXuZbsxvcU6g7LNwqxPZwb4Z5s+lPCLK/PHkbWdZoDacwsmUvIjps+LsruC+36
f8AHz+e31itMIp1gu8g/hxFbTu0EsXYVitdW8ENk2fjLS4WhLAIyguFXgsJblOKREPg8nQeXQLcV
VO3kdxlv8og/nnBYPhaxstB8uAPJaZnMbHOk103wzBNbuNPiiEwectNSd+3AqNdC3XzT/HWPlkOT
/2XZCMTQ71Q3Yrf+jXyBs7/cSIKJpNw9BmgjWm3rR8txKE+C4XrwkLFlSEf0VHQ0QqINyX2WyfQ9
/xds2DAoomuM+Pg/SLfnH2SbFFiigJsAi/mbI14Gamt6opR/knTao6QVvZbDE7MVwig445FAJaqa
cwkmXOaoQT35+0tpCo4s0oOG3uCLf9azr6nxCRXaL9bVLI/n1dV6EBrnYDT3QRzffTU6Add8OwO+
g3QOFxoBsbSK8t/xRFSprr6hjfEu7tQt10y17dTzdNJ8YuVhoK0jJiRadsA37FooZfasQQ3ZqZ4J
aP5ybUTaPw/jDioCaRXKHYp1JczLZDXnjfowK5W8tegQp+MfasHVLRvcYYUkGJ40XENxUI8NChdo
2s1kL+z2mHrOzgZILC+VXz6XWOUQxRAvomIttBmm18XXIK6gc3vrVsmLAEAYWdWQb0NAaG3B2Rf5
T4e78WYOc+72vpJPng3OttcVtH9na6ETtq2eqsK7iz69MbC82ZhDECUFCwCX+kqBQTLYmJXb+UHX
4Q+CsKwWvhv7JSHdrCL98NSBac+XNDuFMjqcAg4EvtXXWaKvSPaKOmB3dLKQjb6l3xn1h6dx9dp1
XWR3hoqm5mOd0cNZEEMJfLmhwl1EqYOCZvLFdVNChTI56caat6uZedj/nO++aEODA1DiD/olFdsc
55Ga/Qghdn/c3fVCuK8zgS7u1gefLLBIKMDlJ5ehOjGDQeOeTGcwkGKakhupvj62bGGgHlUq5uJh
07EiqYHgqE3XxFoBHt7MUQfLMo2OJLYgQgQ0zrE3BeD5ncwo6D0UXTH/XQDWrOx5Tp/D4x8r9c60
y/EHPUFD04fMHjN4NzfHzxEMGXMv2IkauY55caAwEbQqq+UQEMXHRvZrWVmkaRq1bs4m1PDLyiir
NR6MmPqT7iIk4UPUAMQgxljXFBOMLefx7tGelNMR93tBG1Tg/o5Y0OqmzSJnX/RJF86kxE4lUJSA
13kK3N9QWMyN00a/ulghtWdWdc0z6PkkZRbT4jkNKgbq4fnS/RMOdXbUctF3Y+ixMxJBdvoR7l4r
J6+pgwcK2WIIqOYWF1yvUdC+ZdCp/91jYXcV4Hn40g+MkJz35hasjT1xWGEVtO6gtybozbK3d+R3
23gHhE6RGKqaLcgR7flWvintrsuluuGd46uPk5NYRDj8pjcHOEnTHagdKGivr0OvGuIzYfgCEKNE
27lGLBBSl7Jjb2KEH0VZsTpPn1YUkGbUTSL6QkGkO1jjcOHfqEj8yNhz1ursRgDDgnf652K9WR0M
zZke02/ZuXK9QeoFKo82MXEiqntgyLp5IhUyUosisGsPsLBa1dCjTtVqaxK5kKQsxMAFk8Vt6hjJ
1ZM/M8CGJkTW4f1BnojonN+RXveZFO8y7vY3cic2oziAEYCsANFfYEZX8zRYI9SoBIVRzX5BR/UM
Hm39+3aNEFqZYDRgojXJnCpfIunCqdoXv2Lkf4R7LbXezgluvIjI/x9TslBUtdPMUEBo8X5OjDDe
oL7BJJOSQ7Cih7/U5x+S+mxcO0VrkHIhxgxLkNfIO5qeUvTW+9p6jZtCtbs47gwqT3V2SyQ4YI0u
O6UntgRRIptyQ+xEP9iJAHDJVtAphpclgjfyso+Kiepah5HRZu/9i8baVpyYivkaYu62u0I7WhoC
ZsBhMzyEJMeSd2mgGEX7+nDjMybOYR6kTfI0Ep6isv5bqCQiabPgU/WSRWmgx2RPD+iuqnH8w53S
OHis4sr1xzVHvGrvdpZtqyzAGUoRefyy+8vJz2kUdaw85bShcZogIdQ5cjjRVS2Ok78R4vjjZM1y
HoxK+Ni4r3woLX2epKICjBEMA5Ivzqfk9xnhR10t4pxO1mM89gIIwoR3qeJkeLpSwzRWipOhowGL
tj8dT67mBboBQMkUyPseJ3af4QZ1QKpBJZ65/6fecy7w3/3bNeTcAb4m96A9yTifw8gt4/kwy2YM
l68YG7bKGEFa+UWf3wRywRh7qzXkzwKL4O8fR6Hk+Q5dqYNFRojyVUzXY23aSCtk7658W4txhWlC
43mVozrAZPYj6UmEy6yktZo0sXMXFx6DFeylHSPbXlXKtInkL9aOXcmJtuNrBvXaVrUwCurhw7Uh
MozFgyjKL/BeiCDPhuCRwM+c+Q0JKFdLxj24E0HW6hqr5ExS9W/X0Kl62HwbajGIbmpWJG2CYkTW
wbjzJ3VLvAVt4XoWJ5ILFPPUEOU0jRG3JkTADkVYh+zCbXzg0/Au3Gt8K3n1OzcVhuLz+KLbwLXL
7S66Tvm4VAZjpcR4uhK/Hi4Iw5RId7WtQhKiDDemEc/C6DUo3oWgO16Zv3UBAgLZrl7Vbo6BqFkX
nD4EK778Xk3mwUW90zIrailF/TTzoIelQCzO8uLK1Vlw/0uwTBhigeCZEHOVjGoxlPEtE51Z3HO8
iubndn7c3aFvcfIKZ49P1MURu+uwGWrBsFDUDvVai4NPMBgD1D5O/4l0z50w6lf4HM4McGjD+dwF
4x4wwmL1cbb0+ryvzoS8lVQhRlm2Xi127A27jo9ByNKts4OhMv/lLaHcmANyfO7d0VBh9rvZbjZJ
rdAB/KLb41LHspIy4rH7A2khUV2nhPPPh6sEDSMm5YQVexmY5Vsp+sZ1dMTuwGDUA2bU0iKOrMfo
bpMolWkVNasJbs+KnXend8kyfEjMN39XsHVOrZ9QAIZSD6K0ZBWvNt6PYuhZMzLiO/BYjZQnWN4I
z+maktut5SczNi/r1S0rCSA53mrbgKmK50MVlKEYKgB/fBb1mOke2O9szxNJttRXRh+WAKiCdpMM
PwyZJgcCiPb/U4dO9/BoAgjWoD/qsQQ7X6fq5/dDVjh2nM0jATArW7GRVi+K4uqxeVrwq63hUuYD
GoPcaswXZFr/iqV32FU8Ei+jDb9I2r0PBxd/GTSAI03IF1Bn4y3mx4+XJ+VHjBxZi8bEnSZeKjgT
tqHy63NPDmWeJwx6rR7V5njepuGnfuvQNxeqQXV2JKdLI7h42wx7mV/a2Yw7ZdYH0kAdJiDb1J8O
rcfe58BJpeMercxN5I/FeqIxDGP0WfsLLIAzblbyEVEoPF+f5OeKksGSAhhl4XOd1aZ8TN7xwrb2
HfpdoPQNSkqYe9pge8DEfDzKk5WyMYT3wqa3uKOg4wAQToA955aGUvXUH8s97D0FWeBEQsP+bkgk
XRS95lJ/YwipZ1WXBg1gZ4EVlfUeUEkUbrCJhYKZ34hNiWz4vQNgg5ScR6FyEMGq3S7U+cjIXfEV
9M0kTjKV4O8KdduQH5ucPD20QSu8WnqTQy8KGT8o8zY1S7+R4UZj0JV9hoS9uzEIkVjny3VQa2mD
tjtIalaoxpFguazYFaMV9J7scGnMt8d448JBBPTbiEdR2tX5ewqZbxuIiV3dM6Mxr3jiZQXfvoMU
CbNGf9v42dHZv7cGkNKv5kaV4wG9b6YSumtrruzOuzziMQHocsrR98noIZSCyxfPIoCpSnHfloTP
0Alk49mjg1kAQcc7qQuFhEGTyWJ89woODhRodCWmPe9d/iVlEBrmRHP4H+k6Il/JdMicwekMIhP/
AgNC0HFo2U+u7IAQKNwBxS8BNzEhh+h8NgoZt/1hkRiV0GmpbgA9pMkw8XDYmuI2sqIy0kbw152v
vYD0H0JCl+NWF7EIotW6jFnHozqKZhN3jXMqQtuUAwnpeB/izf7BnadTVqWCEzB8uL7RSPV97tp3
A+Jy1KuB/Jf/gsmG/Kn4U8YYhamO1WuRInzh2i6mWjDg/RaT/XjGeZmZJuzwtd5yZezEfWdGUvjJ
YnHMDu5EeDBh5MOd0cvoGo6+5TSaWNsLiJ4I5hLr9Bo/lIhl0DXaQvKIvAg7ulW5pjiiyH8kfD4P
DMqaUOfKB9O1VyyIfXVvHc+Zy19sM6EGCzPPohrBS5Nw42gT6DNlZjo7MGJdwGDumC41O5t6fWJC
2b+ddAnURPbdcyEw++TlJNxRVpQkI/VqAErInNA7+AKtr9GY0yf7/IMeVdfI9WjUy6T3XA7cAwso
0qHu7UNuwizeSx624eVDLd+MRJ//2ZfGaJA1GJo1Y1/uK0umesUygO0kv7k2InecKBYfJClyuTFV
2s1KAD0C94PR0U0qBHtODGq/QoZ2R2ujZSYIQMB/O63qeT4+JrcyEsekAN23Pt57V8+CWxsZGMWp
9VcuRjBnTKjYK/1ufXZGz/1ld6MKNxpudqaXG0XkCfHCp64/dYmAxtZ97BJ+7kvTWgiycSLPQ9WN
dm2LHS/jRj/CtZk0EzBdI0W1qq6TQGrSihC4oPf64JKie8nf4tb5opiEj5ndHO/2vrQvyyntgdwk
DfK0ue7lcHpbsmX7+Ewu2yyDZEdUMxYiG+cOJIDBb+G2ynSXG7+abzFwpjxv4URduJhM6NyzOSSv
B1kyWBartFh34VefGaXPfD8p/3DhI9QdlSn71o3rRRxe5PrANLujt/jv5wI4WEC3HcTxJNjIoZrf
iB1iWAKBzJN7drlug69xu0DFKvCLwbn+YAvgfYJyYwxqhlyjpWHr9ZutFjEGyA9SXoD7r7n9aLOr
+ltFm3eJ7Y6YI2L/s2d2Gf+18FAGXVHOxx8C5T44g64QnTnw9mxNFSDMCq4t/pJ9iJWe/uh1WFlZ
mw+FlSYj6cLtzHkG6II/5Wax73AKZuxJ/9YkzDSYRFJeYZwSzZT1N5xZk/UJ+wNHzOoSpVygxp8o
T2dvpUMHD1l7ADcPY0eYLPzMjM+8nmoBjJJ8IZBlEa68qt3IOAs4GWyjUBW9Bibd3oD+6Gtifwbo
oDLRAQAZRbmv7EN6dbU6PI8M7AesO4EOZN9djaws1845AdQSOtGkmCICDdQUd6PtecmL2tCZxA7d
UqjxOFcF9lIo7ObRcSpr9rcrlhjCk/lqNe1myWea3kgDGTrAS++mxZvHumCfA6/sk7i1vxiCKTVp
GVqKpPkOoiCJcF3Gf2dxrQekhGN9AwWekpV9njVTMvmiSX/hrT97iX/M383KecsQK6mxz7NFskuJ
IB/vU867TPOph1v7NU60x/7kAMRcyeNEw1o+grRoPtUhpayjZTO6iAN/btY+EKi4RpLp7dBi8ZUI
3ViGnonG3zUV2x6YQKoXicV3pqwLPr9yoGEuKWAMePMAB3gCPBhm3QwpwICL9aNoQDtUe20VtsQg
Dgqw9DVHqW29x6a/55GZIUT8kSDV6aoQUG7G0qwnFIUCdy5gC0CU8xHkst6Gw+i2epIjzAqumhVw
TEvsUl/sohlt8ufZCSqCp+4T4nJQdSIENRj9CdBhquDzoRV3BqUJbF7WgxBFZJluL9/1G89Co/Y7
00nfFVZ+VKqgRh0nK0PjLfSl+9H/3bc7drGoO+YuewLpAudb6qnV+R2wvHA6U4kkKVsp8yaaVedu
eIrUGqvKTDmqRB9NJX7fZqexVY3KwEq0v1JEcMtBimQIyM5fAienxEZxEEya5bXBUUf/zS2YXTUx
zaGlcAaST5cYimLSv1EE+kD+sKbsEMvypEQxd8Ca3jULALZ6D2NbX0tRIkzXPcJgxLp+KdJK3Smc
wRUBbEwCsXrQSx8VR1pWt4Nof2vCuaJp7s//WZad/m6t8LCEvhPN/QmToBS1LLNAgnC0FD5OYZ0t
auJuyYFw9ZUrSBDGKVXAZSerQnRazAv7fX+twusqaqzP2DOnz9beuG8lrhqnx8dgRG8e3vdlQMQO
bQQ2MpEIZJquqe0MjmyXPRfSnBGvcVomlCWh3i3kSHINhwKR73plMOYUlDbMzZs9aG6BrLI1fNFX
jHJbEG0HPehLzrCq23Gr59Z+5wKOWVkxw3Svfw8eOJpSzkaNg2qR2bEQ5fl9ROxQMjEf4dO4saOX
ozdPQNK5YgqtL1aT04gUIcSA4vmOHrrebNk7hPAe2xE2QCQ0A7BfkyKF47WEeXohdXowpY+Ckayu
FpkP+W8qxIRFViRFX91YSJweXawjcHkit6NnA0hlYLksgrF0U6Q4J8wa2hp5nbp6a9IMlM+dWmkv
6trMNyw/PVeC1XZ0t7MP+bi7JMPqJtPrh2pxbu1fuNYct6qXjhGP3joKeGfHbnNq+Gil1X115u54
YWV1odH3WUuSEgJmvNXCJ6HXtb7tsYizwNWU/kGZI2ghYHLmApA1sTS0c8JI7r/t2nItI/17ppz0
h3njaFCquSmbNoof0aLsMqPTdHhdEg0siRGHT0nVf5SJlTr2is+k2dWJwjqqK56PPhiYlkeeiooG
OLhtkFSF5xNVD6HPCwkp3wXCZB1BagEtELtPHTwNJwLpJS+igEDJlSBpA7FFXHxK3jANcmfqkpXB
ETxnXbudxKC1kQdeADmjAxzALaKQS1bR+Xh+/Hema5Xxm3wEX2PLS8K89Ek9N29YRavuQflcDckR
u4k75T7sO4Tdqq5iLC+Lh+v9DIEFCFaE3dbeCBlzxyRSqgFf7i9Q3/XqseVbn1PXZARC/Njd7xWf
xMUyCDpDG+YyignsmZVnBTbGzkSULbu2+72mF7Zs5Jh9C6XgeP+gIbeoFU9m09p/70zOOlXi6jEZ
nJYfNCZT2XbbHfk6tMVStUveS0PZDb7bfxTY4Tu0w1hcTEdf0e2ENTwaoVygDSOXodPWIKThi43Z
l7xEq4fz0jzAWLVBix3h/YblKJsk+XGDyc4m8HJsyHAU/+41zqcnPBd86EZrFlBX2g+smTnuEZhz
cRwyIRXeP4/YxtC0etN/GkVU9eJF9yu2EVbXwEZCxpisIaBoyF7hQJ9y7+LvVW4Ka7J4TF2ZlGjL
QpapxRRquL0gPA8VSoggyH+gBs83AudBAtvzxwR0h7rHG4LM1uxTNtCXLpk28qJA01dYuLyBADxt
mbTCxAQcBWMNN9YvXM7D2WXlYNEp3bx5CIFwgBa1Y3FX6BNkFOjf4MTL9S4fTGW88wqkR2ctxI6b
vLJkms5pV7OIF8g0bKGLwzwUVAikreTnpETgrSgU8PaASu2pYBkvLgXeI/kiDsq0BYZSq8R+Ahnz
JU7uDuAO+X/8mBYk6zl4xajXp7NevTixur+SOP0Fuzo4HHQg0uESiKCJu1eqUVGwKrDfXGyyaumi
rvf7NLFDUxSZnNpuk8y52ibAzHp1JEvQnjoKZ2Lne6zlLxIt+ZvodstCrakvgdl/4R6N47PeMpEg
uihCGGtMPPcvmjxdrIZ/0zm8nSOnK01YPvYSIIJ6lGm7sZOIC3s6RhjdTk2PQfxdilxfXkYcy3v7
+tFj+IJtLgPr1xEAyUp++11hRaP+wJ/f0cewUQ1qe2YiDTiBdA0D0qpnv818lbECZbExgQ3j5zW4
d2l2yn9QJQLzllBKcwLdTe0Wpzw8tORFwdYFJj+L5KHcfybqtRomd6iLFDDuhDE+jWNLrdSseeK/
OOoloWtAW/C1xKXFIFsVPKHUGLQqga0Ti7slqlSbb7pGGE0BS5GLX4/zEgWwGAmvrccQvJxDE43n
RZpltaww4/YdOfbb34IrDCthimYOJloX5QuQRGW9yb/+Yyd3FLxgqoICd8QXwSt3JQT0u4v3WoG1
8890wZ5r7jy7oSi355I3S9lfdoneLmdvePjq+QLX1Ljl8JzkW1u03wIz3yxXhf9IFUBmHReDv87F
XWImTQT5KrtTIpLrPjwdF3h8wPCyOkAmJaKz2KCSh27s+dp2+bvBTgxG4okT0GhwZWxfQa5chnyo
SOuu+6V7iRQTm9NMQMdELtP44WnbEjiGMrkQQx4vCBCFsFnYE3WYDe9PNB3gW4wFdvqxPdLj9Y9w
9gMg322BrU/C2AEC6DDKI9Qsxc3bKp5yNa9Zurl9o2WEjrZDZUEv5VyreYF9Q0/YiuprYmHrtfcs
akBsJOGG8GOdRf20Pvyi5AHMZL7gvuNEFI3J8iWEy/bOwK2jlykKycyFMBTb/5HWL8CVIyb0Oxtg
mUKmORitFAD1+QqJYNkz7jlqvVH9QKIUPTVML4b/qvhAUGwkny3EdpDSam+mCTrIBgvZLB0vYUMv
Nh9GdsclsTtvetjGAKYXMJkC21qRIl5flALtCbu7e4s0zxbE6Nz4i0K0Nr+0MKZvuAdy1OeRbkaZ
p6tvihWCOMtMB55ckFchg759R47nXumvh5UsN8Ewmg2Jlh72Scx9YFK70/JQBLtXfBgnlvC9AZ3T
InLIjkOuH20j3gwuNkbAwIZ4P3yAAw3yomJzf6/TTcXGrzkV2LpCqmJXk/K0uZl2sXWeZ7W/5jTp
l0WMLS4akkYsmX+bKfQT2X1Cf11exptNOwM+XfOBkI+Pmt0oof7Gi9RuXhGp4zLAb1W2gHOi+4Ym
TcKl6DkBNQqecyBXIZof6Pn/50E0rL5fWkZai7c+heeTrI0kulJHQ56++3GaKmVjtyAs7nYHKLol
QL2kt0XZOUhricRT7wz9Y2fhQpXEVaJH7Z3ORbJciOhZzyimemPELpT748IiLTUoHWi70Y2XqKkr
9B7/p1YMtl0JQDOqQy9Yz0CjpQBEndlKRszlz4Sydjc3ne9nHGsc0NGMyhvE0PI96IH78D7VuIRA
GJ1Z8U6rF4c8wWkeZWiEhGr8AnYBx+wj07zHpNJRkfZk9VqmrOsA9r9VV1fPXXTipAy1LIMq/B4S
+mSBUT18g0weIu4FVANXUW0uqUBLrggTpUB5ENnWA7cA5ushFcCalpwfQbdPIEzcT+KN9lF1YhY0
7bUYs2TpHHFGpexzrG8W3wbxfszQRCPSLsBDYGJ16jMxhN3Fye4BJc8GXEjZf51Zee3Z0Lxn5WGi
N0X9SH1zKY7Law7ITp756vIbAfqvZtiPlCtoNGIcB7JXsVTE61maUjREK9q3Ud/ODK/L+W4XZzFb
seIvofAG5iNLhlc2+xtWRai+3OCBn+CmDE/BRKNizMHj2DkuUbX6dFu5yRCYzuz5rKT42v0fZDkY
7ujeDAJ9/198qYVOib/pL+vr8SnzXDwvAx+SeIImFEbKXvMh1vHseaTUjz/Nip55dAJ/ogdGfHfg
pvuuEGpWDJq9OUjumJ4hNKPe5jnuX8DUp/cVSgbxp3GOkywwn2yD1CuXbAh8cctrEWNyR0SaG3/E
cYeW4Ki5oMwUDqeNxgQt5mQ/QUSUY0vhpmrWxFNMkGo8gErjYAaDMmwxO21njl4v3+Q6DbPTWBoY
4IJRgz/TRyRYrBOGT9qKXBiPabf86gCc4i+ZPKiEunYVsQTHNgm5GzYyeGjecDK0SuXRqKFJz4eq
BfzFMH8ijdY3gg2QqJI0OGgc1THYJ1wGLqJyyIVU581sRhvpAXVvEo+4LlbEs8OXCXpgk1kEYQVg
jjQBNzxMtkYLXOh2qMetb7u7EJ3oY2oHrBpaJmwbvMCQmuGMxzKW8n6aAn3jdjee6IQ3G0abksFS
3016A3RSEmdiHB2AJc8wjaoGpNQ2sguv5YZhd6SvzQHEh5bPbeSTsld9N9uQKPyAHPdB56kGIjQM
kw4UGBCyNVqKqjY+cXv1ay8QNWUyu7WVTkt40ERKPSCsIf36ewLuTox+vNWjjxCFiWRxdy5p6Nll
gDB8x5n1/tGITKGKnLY+/hSdA6uNTBNCAztkaw5fCJWosWh7LQmQQh4lNXg1nkQ3l9vFp1uv5Xi+
osbBj4ITNxc7XeusJJ/C0uDsJeUc2qPP4FDkqWhr4ceQ/AlUSK1k0KdXlCXMFhH+3ulZ1wAqW6yy
8LDp1z7AsswMaWHSIVogmGLoDw2e4WMK6tQtDD/QKe25a73oKONhpE9LVm12TIckDW62DHu5ERHG
ywhXWA3xmHGirSataN9eUaRRgvjWn32ZX+P8ZFF8V41rD9Fvj1nEo3wvZC9Iel0sZuB5VxJvfVmP
SMj9xQv3/DkT5uow7hcPOD7KmXEaWUHmyci2pZzl8EnP754Lbd4lCNR7eGB0DgwZY5AKMZPmW76l
ql2dn1RLvrXC+uEU3p70LjluEsjI0zMHMNrRLUVp2sGqzsqdrQcQ9YR9O86qH2vbk3t9Z3qb0fDQ
wxpv0vhtgxLO+ZcJF839IX60nmutxMD+g9kA9QbNX4RskrNZ/dKncuf0pn8RFnRgzZmWicmSunFI
9ZQ7GB6sA/kkRhu1NS/5LuOktS570w5gYcisHTq4loWqU7DdcRnN8R1ZKavaGx0SOlU00uMvuCCz
mdSER0IHbpG2WCO4YC7gWNeOQEpiArqPz3AUv/vCkMyqY/2jlsE9XXNxqYGDRB+W7zyRhfV1CPeT
omvYvS3R7GG5jETUqZofqkDRGkhuZM0uC9e4EgH07l6iLwrTVU7zvdImU4t17VuR88JjsEh2U7mZ
F6NJ8tXcoIVrKinZ3twfomffjpn1YOsEqm3ekC7ICONduKeE9P+n7/ANRvX1yfDfO8S2p99NI6fh
vKmbgdp2uYzM+dZz7OSuZbplTvsLGTA4J0LZsh5xTOHQ7BjeDInOZB7pdPNrmlOgqDfzaVJfOjUM
Fq72Lo/XzMPqCpyMbQtCux58Z8lQ6VDIbq7RMcS/zC6uwIKGe+uSAbkd7sIWZ5bkh2ZUKere+m1q
e20ZRcHWcKtrfSp96Y8PfrabZxYKHrXvAd4UKEhDz3A87v0gm2qS7RH4HxYFYfgW9+LihGpVrCr8
CJVvC4VBR+IvYNwr0vXhamBk68b5e9KigIzooEGOzXpxCW8W4JvPiMXSoe72zt/fiDF33ZroT4pZ
96UGMDy7NBXCjoPKliaxBHtrvT/BgseoppHbu0Z4pzDJwvUP3G2dolxB+3iO46jgeptX2mCbBR5v
Q+O0tbKpBBZ44wczpcn/3M5QOz7hwMcaR/2Bmp+7t9gStZY74IWbY6p1zmkmtNeKYpZskw2i975X
f3P5URLARWjnQ8jnTAk6r2EyUqNixJCU2INlhiX/qc3ZFlyYTyBqWli01Z5euVpR7rqQloPQHvip
hgeqPnIeO5tgKveMT7F0lc0L4n5LY6N7Mo71wof+EEMHrScsiSBP8O8a85QTxIJKfTIiHbUI17gK
36aJRBX2+UlDqT+jSPg4D1ree9wLUaMg2p7u8vcgQufRqmSLYrY=
`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00599.vhd
|
1
|
1896
|
-- NEED RESULT: ARCH00599: Index constraints passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00599
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.2.1.1 (13)
-- 3.2.1.1 (14)
-- 3.2.1.1 (15)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00599(ARCH00599)
-- ENT00599_Test_Bench(ARCH00599_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES ; use STANDARD_TYPES.all ;
entity ENT00599 is
generic ( g1 : integer := 2;
g2 : integer := 5) ;
end ENT00599 ;
--
architecture ARCH00599 of ENT00599 is
begin
P :
process
variable a1 : STANDARD_TYPES.t_arr1 (31 downto 0) ; -- 3.2.1.1 (13)
variable a2 : STANDARD_TYPES.t_arr1 (g2 downto g1) ; -- 3.2.1.1 (14)
function f ( lo, hi : integer ) return integer is
variable v : STANDARD_TYPES.t_arr1 (lo to hi) ; -- 3.2.1.1 (15)
begin
return 256*v'high + v'low ;
end f ;
begin
test_report ( "ARCH00599" ,
"Index constraints" ,
(a1'left = 31) and
(a1'right = 0) and
(a2'left = 5) and
(a2'right = 2) and
(f(2,5) = 256*5+2)
) ;
wait ;
end process P ;
end ARCH00599 ;
--
entity ENT00599_Test_Bench is
end ENT00599_Test_Bench ;
architecture ARCH00599_Test_Bench of ENT00599_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00599 ( ARCH00599 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00599_Test_Bench ;
--
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/a8core/gtia.vhdl
|
1
|
57191
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY gtia IS
PORT
(
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ANTIC_FETCH : in std_logic;
CPU_ENABLE_ORIGINAL : in std_logic; -- on cycle data is ready
RESET_N : IN STD_LOGIC;
PAL : IN STD_LOGIC;
-- ANTIC interface
COLOUR_CLOCK_ORIGINAL : in std_logic;
COLOUR_CLOCK : in std_logic;
COLOUR_CLOCK_HIGHRES : in std_logic;
AN : IN STD_LOGIC_VECTOR(2 downto 0);
-- keyboard interface
CONSOL_START : IN STD_LOGIC;
CONSOL_SELECT : IN STD_LOGIC;
CONSOL_OPTION : IN STD_LOGIC;
-- keyboard interface
TRIG0 : IN STD_LOGIC;
TRIG1 : IN STD_LOGIC;
TRIG2 : IN STD_LOGIC;
TRIG3 : IN STD_LOGIC;
-- CPU interface
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- TO scandoubler...
COLOUR_out : out std_logic_vector(7 downto 0);
VSYNC : out std_logic;
HSYNC : out std_logic;
BLANK : out std_logic;
BURST : out std_logic;
START_OF_FIELD : out std_logic;
ODD_LINE : out std_logic;
-- To speaker
sound : out std_logic
);
END gtia;
ARCHITECTURE vhdl OF gtia IS
COMPONENT complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
component simple_counter IS
generic
(
COUNT_WIDTH : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
increment : in std_logic;
load : IN STD_LOGIC;
load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
);
END component;
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
component wide_delay_line IS
generic(COUNT : natural := 1; WIDTH : natural :=1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
);
END component;
component gtia_player IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : in std_logic;
COLOUR_ENABLE : IN STD_LOGIC;
LIVE_POSITION : in std_logic_vector(7 downto 0); -- counter ticks as display is drawn
PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
SIZE : in std_logic_vector(1 downto 0);
bitmap : in std_logic_vector(7 downto 0);
output : out std_logic
);
END component;
component gtia_priority IS
PORT
(
CLK : in std_logic;
colour_enable : in std_logic;
PRIOR : in std_logic_vector(7 downto 0);
P0 : in std_logic;
P1 : in std_logic;
P2 : in std_logic;
P3 : in std_logic;
PF0 : in std_logic;
PF1 : in std_logic;
PF2 : in std_logic;
PF3 : in std_logic;
BK : in std_logic;
P0_OUT : out std_logic;
P1_OUT : out std_logic;
P2_OUT : out std_logic;
P3_OUT : out std_logic;
PF0_OUT : out std_logic;
PF1_OUT : out std_logic;
PF2_OUT : out std_logic;
PF3_OUT : out std_logic;
BK_OUT : out std_logic
);
END component;
signal addr_decoded : std_logic_vector(31 downto 0);
signal hposp0_raw_next : std_logic_vector(7 downto 0);
signal hposp0_raw_reg : std_logic_vector(7 downto 0);
signal hposp1_raw_next : std_logic_vector(7 downto 0);
signal hposp1_raw_reg : std_logic_vector(7 downto 0);
signal hposp2_raw_next : std_logic_vector(7 downto 0);
signal hposp2_raw_reg : std_logic_vector(7 downto 0);
signal hposp3_raw_next : std_logic_vector(7 downto 0);
signal hposp3_raw_reg : std_logic_vector(7 downto 0);
signal hposp0_delayed_reg : std_logic_vector(7 downto 0);
signal hposp1_delayed_reg : std_logic_vector(7 downto 0);
signal hposp2_delayed_reg : std_logic_vector(7 downto 0);
signal hposp3_delayed_reg : std_logic_vector(7 downto 0);
signal hposm0_raw_next : std_logic_vector(7 downto 0);
signal hposm0_raw_reg : std_logic_vector(7 downto 0);
signal hposm1_raw_next : std_logic_vector(7 downto 0);
signal hposm1_raw_reg : std_logic_vector(7 downto 0);
signal hposm2_raw_next : std_logic_vector(7 downto 0);
signal hposm2_raw_reg : std_logic_vector(7 downto 0);
signal hposm3_raw_next : std_logic_vector(7 downto 0);
signal hposm3_raw_reg : std_logic_vector(7 downto 0);
signal hposm0_delayed_reg : std_logic_vector(7 downto 0);
signal hposm1_delayed_reg : std_logic_vector(7 downto 0);
signal hposm2_delayed_reg : std_logic_vector(7 downto 0);
signal hposm3_delayed_reg : std_logic_vector(7 downto 0);
signal sizep0_raw_next : std_logic_vector(1 downto 0);
signal sizep0_raw_reg : std_logic_vector(1 downto 0);
signal sizep1_raw_next : std_logic_vector(1 downto 0);
signal sizep1_raw_reg : std_logic_vector(1 downto 0);
signal sizep2_raw_next : std_logic_vector(1 downto 0);
signal sizep2_raw_reg : std_logic_vector(1 downto 0);
signal sizep3_raw_next : std_logic_vector(1 downto 0);
signal sizep3_raw_reg : std_logic_vector(1 downto 0);
signal sizem_raw_next : std_logic_vector(7 downto 0);
signal sizem_raw_reg : std_logic_vector(7 downto 0);
signal sizep0_delayed_reg : std_logic_vector(1 downto 0);
signal sizep1_delayed_reg : std_logic_vector(1 downto 0);
signal sizep2_delayed_reg : std_logic_vector(1 downto 0);
signal sizep3_delayed_reg : std_logic_vector(1 downto 0);
signal sizem_delayed_reg : std_logic_vector(7 downto 0);
signal grafp0_next : std_logic_vector(7 downto 0);
signal grafp0_reg : std_logic_vector(7 downto 0);
signal grafp1_next : std_logic_vector(7 downto 0);
signal grafp1_reg : std_logic_vector(7 downto 0);
signal grafp2_next : std_logic_vector(7 downto 0);
signal grafp2_reg : std_logic_vector(7 downto 0);
signal grafp3_next : std_logic_vector(7 downto 0);
signal grafp3_reg : std_logic_vector(7 downto 0);
signal grafm_next : std_logic_vector(7 downto 0);
signal grafm_reg : std_logic_vector(7 downto 0);
signal grafm_reg10_extended : std_logic_vector(7 downto 0);
signal grafm_reg32_extended : std_logic_vector(7 downto 0);
signal grafm_reg54_extended : std_logic_vector(7 downto 0);
signal grafm_reg76_extended : std_logic_vector(7 downto 0);
signal colpm0_raw_next : std_logic_vector(7 downto 1);
signal colpm0_raw_reg : std_logic_vector(7 downto 1);
signal colpm1_raw_next : std_logic_vector(7 downto 1);
signal colpm1_raw_reg : std_logic_vector(7 downto 1);
signal colpm2_raw_next : std_logic_vector(7 downto 1);
signal colpm2_raw_reg : std_logic_vector(7 downto 1);
signal colpm3_raw_next : std_logic_vector(7 downto 1);
signal colpm3_raw_reg : std_logic_vector(7 downto 1);
signal colpm0_delayed_reg : std_logic_vector(7 downto 1);
signal colpm1_delayed_reg : std_logic_vector(7 downto 1);
signal colpm2_delayed_reg : std_logic_vector(7 downto 1);
signal colpm3_delayed_reg : std_logic_vector(7 downto 1);
signal colpf0_raw_next : std_logic_vector(7 downto 1);
signal colpf0_raw_reg : std_logic_vector(7 downto 1);
signal colpf1_raw_next : std_logic_vector(7 downto 1);
signal colpf1_raw_reg : std_logic_vector(7 downto 1);
signal colpf2_raw_next : std_logic_vector(7 downto 1);
signal colpf2_raw_reg : std_logic_vector(7 downto 1);
signal colpf3_raw_next : std_logic_vector(7 downto 1);
signal colpf3_raw_reg : std_logic_vector(7 downto 1);
signal colpf0_delayed_reg : std_logic_vector(7 downto 1);
signal colpf1_delayed_reg : std_logic_vector(7 downto 1);
signal colpf2_delayed_reg : std_logic_vector(7 downto 1);
signal colpf3_delayed_reg : std_logic_vector(7 downto 1);
signal colbk_raw_next : std_logic_vector(7 downto 1);
signal colbk_raw_reg : std_logic_vector(7 downto 1);
signal colbk_delayed_reg : std_logic_vector(7 downto 1);
signal prior_raw_next : std_logic_vector(7 downto 0);
signal prior_raw_reg : std_logic_vector(7 downto 0);
signal prior_delayed_reg : std_logic_vector(7 downto 0);
signal prior_delayed2_reg : std_logic_vector(7 downto 6);
signal vdelay_next : std_logic_vector(7 downto 0);
signal vdelay_reg : std_logic_vector(7 downto 0);
signal gractl_next : std_logic_vector(2 downto 0);
signal gractl_reg : std_logic_vector(2 downto 0);
signal consol_output_next : std_logic_vector(3 downto 0);
signal consol_output_reg : std_logic_vector(3 downto 0);
signal trig0_next : std_logic;
signal trig0_reg : std_logic;
signal trig1_next : std_logic;
signal trig1_reg : std_logic;
signal trig2_next : std_logic;
signal trig2_reg : std_logic;
signal trig3_next : std_logic;
signal trig3_reg : std_logic;
-- collisions
signal hitclr_write : std_logic;
signal m0pf_next : std_logic_vector(3 downto 0);
signal m0pf_reg : std_logic_vector(3 downto 0);
signal m1pf_next : std_logic_vector(3 downto 0);
signal m1pf_reg : std_logic_vector(3 downto 0);
signal m2pf_next : std_logic_vector(3 downto 0);
signal m2pf_reg : std_logic_vector(3 downto 0);
signal m3pf_next : std_logic_vector(3 downto 0);
signal m3pf_reg : std_logic_vector(3 downto 0);
signal m0pl_next : std_logic_vector(3 downto 0);
signal m0pl_reg : std_logic_vector(3 downto 0);
signal m1pl_next : std_logic_vector(3 downto 0);
signal m1pl_reg : std_logic_vector(3 downto 0);
signal m2pl_next : std_logic_vector(3 downto 0);
signal m2pl_reg : std_logic_vector(3 downto 0);
signal m3pl_next : std_logic_vector(3 downto 0);
signal m3pl_reg : std_logic_vector(3 downto 0);
signal p0pf_next : std_logic_vector(3 downto 0);
signal p0pf_reg : std_logic_vector(3 downto 0);
signal p1pf_next : std_logic_vector(3 downto 0);
signal p1pf_reg : std_logic_vector(3 downto 0);
signal p2pf_next : std_logic_vector(3 downto 0);
signal p2pf_reg : std_logic_vector(3 downto 0);
signal p3pf_next : std_logic_vector(3 downto 0);
signal p3pf_reg : std_logic_vector(3 downto 0);
signal p0pl_next : std_logic_vector(3 downto 0);
signal p0pl_reg : std_logic_vector(3 downto 0);
signal p1pl_next : std_logic_vector(3 downto 0);
signal p1pl_reg : std_logic_vector(3 downto 0);
signal p2pl_next : std_logic_vector(3 downto 0);
signal p2pl_reg : std_logic_vector(3 downto 0);
signal p3pl_next : std_logic_vector(3 downto 0);
signal p3pl_reg : std_logic_vector(3 downto 0);
-- priority
signal set_p0 : std_logic;
signal set_p1 : std_logic;
signal set_p2 : std_logic;
signal set_p3 : std_logic;
signal set_pf0 : std_logic;
signal set_pf1 : std_logic;
signal set_pf2 : std_logic;
signal set_pf3 : std_logic;
signal set_bk : std_logic;
-- ouput/sync
signal COLOUR_NEXT : std_logic_vector(7 downto 0);
signal COLOUR_REG : std_logic_vector(7 downto 0);
signal HRCOLOUR_NEXT : std_logic_vector(7 downto 0);
signal HRCOLOUR_REG : std_logic_vector(7 downto 0);
signal vsync_next : std_logic;
signal vsync_reg : std_logic;
signal hsync_next : std_logic;
signal hsync_reg : std_logic;
signal hsync_start : std_logic;
signal hsync_end : std_logic;
signal burst_next : std_logic;
signal burst_reg : std_logic;
signal burst_start : std_logic;
signal burst_end : std_logic;
signal hblank_next : std_logic;
signal hblank_reg : std_logic;
-- visible region (no collision detection outside this)
signal visible_live : std_logic;
-- antic input decode
signal an_prev3_next : std_logic_vector(2 downto 0);
signal an_prev3_reg : std_logic_vector(2 downto 0);
signal an_prev2_next : std_logic_vector(2 downto 0);
signal an_prev2_reg : std_logic_vector(2 downto 0);
signal an_prev_next : std_logic_vector(2 downto 0);
signal an_prev_reg : std_logic_vector(2 downto 0);
signal active_bk_modify_next : std_logic_vector(7 downto 0);
signal active_bk_modify_reg : std_logic_vector(7 downto 0);
signal active_bk_valid_next : std_logic_vector(7 downto 0);
signal active_bk_valid_reg : std_logic_vector(7 downto 0);
signal active_bk_live : std_logic;
signal active_pf0_live : std_logic;
signal active_pf1_live : std_logic;
signal active_pf2_live : std_logic;
signal active_pf2_collision_live : std_logic;
signal active_pf3_live : std_logic;
signal active_pf3_collision_live : std_logic;
signal active_pm0_live : std_logic;
signal active_pm1_live : std_logic;
signal active_pm2_live : std_logic;
signal active_pm3_live : std_logic;
signal active_p0_live : std_logic;
signal active_p1_live : std_logic;
signal active_p2_live : std_logic;
signal active_p3_live : std_logic;
signal active_m0_live : std_logic;
signal active_m1_live : std_logic;
signal active_m2_live : std_logic;
signal active_m3_live : std_logic;
signal active_hr_next : std_logic_vector(1 downto 0);
signal active_hr_reg : std_logic_vector(1 downto 0);
signal highres_next : std_logic;
signal highres_reg : std_logic;
-- horizontal position counter
signal hpos_reg : std_logic_vector(7 downto 0);
signal reset_counter : std_logic;
signal counter_load_value : std_logic_vector(7 downto 0);
-- sub colour clock highres mode
signal trigger_secondhalf : std_logic;
-- pmg dma
signal grafm_dma_load : std_logic;
signal grafm_dma_next : std_logic_vector(7 downto 0);
signal grafp0_dma_load : std_logic;
signal grafp0_dma_next : std_logic_vector(7 downto 0);
signal grafp1_dma_load : std_logic;
signal grafp1_dma_next : std_logic_vector(7 downto 0);
signal grafp2_dma_load : std_logic;
signal grafp2_dma_next : std_logic_vector(7 downto 0);
signal grafp3_dma_load : std_logic;
signal grafp3_dma_next : std_logic_vector(7 downto 0);
signal odd_scanline_next : std_logic;
signal odd_scanline_reg : std_logic;
signal pmg_dma_state_next : std_logic_vector(2 downto 0);
signal pmg_dma_state_reg : std_logic_vector(2 downto 0);
constant pmg_dma_missile : std_logic_vector(2 downto 0) := "000";
constant pmg_dma_player0 : std_logic_vector(2 downto 0) := "001";
constant pmg_dma_player1 : std_logic_vector(2 downto 0) := "010";
constant pmg_dma_player2 : std_logic_vector(2 downto 0) := "011";
constant pmg_dma_player3 : std_logic_vector(2 downto 0) := "100";
constant pmg_dma_done : std_logic_vector(2 downto 0) := "101";
constant pmg_dma_instruction : std_logic_vector(2 downto 0) := "110";
begin
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
hposp0_raw_reg <= (others=>'0');
hposp1_raw_reg <= (others=>'0');
hposp2_raw_reg <= (others=>'0');
hposp3_raw_reg <= (others=>'0');
hposm0_raw_reg <= (others=>'0');
hposm1_raw_reg <= (others=>'0');
hposm2_raw_reg <= (others=>'0');
hposm3_raw_reg <= (others=>'0');
sizep0_raw_reg <= (others=>'0');
sizep1_raw_reg <= (others=>'0');
sizep2_raw_reg <= (others=>'0');
sizep3_raw_reg <= (others=>'0');
sizem_raw_reg <= (others=>'0');
grafp0_reg <= (others=>'0');
grafp1_reg <= (others=>'0');
grafp2_reg <= (others=>'0');
grafp3_reg <= (others=>'0');
grafm_reg <= (others=>'0');
colpm0_raw_reg <= (others=>'0');
colpm1_raw_reg <= (others=>'0');
colpm2_raw_reg <= (others=>'0');
colpm3_raw_reg <= (others=>'0');
colpf0_raw_reg <= (others=>'0');
colpf1_raw_reg <= (others=>'0');
colpf2_raw_reg <= (others=>'0');
colpf3_raw_reg <= (others=>'0');
colbk_raw_reg <= (others=>'0');
prior_raw_reg <= (others=>'0');
vdelay_reg <= (others=>'0');
gractl_reg <= (others=>'0');
consol_output_reg <= (others=>'1');
COLOUR_REG <= (OTHERS=>'0');
HRCOLOUR_REG <= (OTHERS=>'0');
vsync_reg <= '0';
hsync_reg <= '0';
burst_reg <= '0';
hblank_reg <= '0';
an_prev_reg <= (others=>'0');
an_prev2_reg <= (others=>'0');
an_prev3_reg <= (others=>'0');
highres_reg <= '0';
active_hr_reg <= (others=>'0');
trig0_reg <= '0';
trig1_reg <= '0';
trig2_reg <= '0';
trig3_reg <= '0';
odd_scanline_reg <= '0';
pmg_dma_state_reg <= pmg_dma_done;
m0pf_reg <= (others=>'0');
m1pf_reg <= (others=>'0');
m2pf_reg <= (others=>'0');
m3pf_reg <= (others=>'0');
m0pl_reg <= (others=>'0');
m1pl_reg <= (others=>'0');
m2pl_reg <= (others=>'0');
m3pl_reg <= (others=>'0');
p0pf_reg <= (others=>'0');
p1pf_reg <= (others=>'0');
p2pf_reg <= (others=>'0');
p3pf_reg <= (others=>'0');
p0pl_reg <= (others=>'0');
p1pl_reg <= (others=>'0');
p2pl_reg <= (others=>'0');
p3pl_reg <= (others=>'0');
active_bk_modify_reg <= (others=>'0');
active_bk_valid_reg <= (others=>'0');
elsif (clk'event and clk='1') then
hposp0_raw_reg <= hposp0_raw_next;
hposp1_raw_reg <= hposp1_raw_next;
hposp2_raw_reg <= hposp2_raw_next;
hposp3_raw_reg <= hposp3_raw_next;
hposm0_raw_reg <= hposm0_raw_next;
hposm1_raw_reg <= hposm1_raw_next;
hposm2_raw_reg <= hposm2_raw_next;
hposm3_raw_reg <= hposm3_raw_next;
sizep0_raw_reg <= sizep0_raw_next;
sizep1_raw_reg <= sizep1_raw_next;
sizep2_raw_reg <= sizep2_raw_next;
sizep3_raw_reg <= sizep3_raw_next;
sizem_raw_reg <= sizem_raw_next;
grafp0_reg <= grafp0_next;
grafp1_reg <= grafp1_next;
grafp2_reg <= grafp2_next;
grafp3_reg <= grafp3_next;
grafm_reg <= grafm_next;
colpm0_raw_reg <= colpm0_raw_next;
colpm1_raw_reg <= colpm1_raw_next;
colpm2_raw_reg <= colpm2_raw_next;
colpm3_raw_reg <= colpm3_raw_next;
colpf0_raw_reg <= colpf0_raw_next;
colpf1_raw_reg <= colpf1_raw_next;
colpf2_raw_reg <= colpf2_raw_next;
colpf3_raw_reg <= colpf3_raw_next;
colbk_raw_reg <= colbk_raw_next;
prior_raw_reg <= prior_raw_next;
vdelay_reg <= vdelay_next;
gractl_reg <= gractl_next;
consol_output_reg <= consol_output_next;
COLOUR_REG <= colour_next;
HRCOLOUR_REG <= hrcolour_next;
vsync_reg <= vsync_next;
hsync_reg <= hsync_next;
burst_reg <= burst_next;
hblank_reg <= hblank_next;
an_prev_reg <= an_prev_next;
an_prev2_reg <= an_prev2_next;
an_prev3_reg <= an_prev3_next;
highres_reg <= highres_next;
active_hr_reg <= active_hr_next;
trig0_reg <= trig0_next;
trig1_reg <= trig1_next;
trig2_reg <= trig2_next;
trig3_reg <= trig3_next;
odd_scanline_reg <= odd_scanline_next;
pmg_dma_state_reg <= pmg_dma_state_next;
m0pf_reg <= m0pf_next;
m1pf_reg <= m1pf_next;
m2pf_reg <= m2pf_next;
m3pf_reg <= m3pf_next;
m0pl_reg <= m0pl_next;
m1pl_reg <= m1pl_next;
m2pl_reg <= m2pl_next;
m3pl_reg <= m3pl_next;
p0pf_reg <= p0pf_next;
p1pf_reg <= p1pf_next;
p2pf_reg <= p2pf_next;
p3pf_reg <= p3pf_next;
p0pl_reg <= p0pl_next;
p1pl_reg <= p1pl_next;
p2pl_reg <= p2pl_next;
p3pl_reg <= p3pl_next;
active_bk_modify_reg <= active_bk_modify_next;
active_bk_valid_reg <= active_bk_valid_next;
end if;
end process;
-- decode address
decode_addr1 : complete_address_decoder
generic map(width=>5)
port map (addr_in=>addr, addr_decoded=>addr_decoded);
-- decode antic input
process (AN, COLOUR_CLOCK, COLOUR_CLOCK_ORIGINAL, an_prev_reg, an_prev2_reg, an_prev3_reg, hblank_reg, vsync_reg, highres_reg, odd_scanline_reg, prior_delayed_reg, prior_delayed2_reg, hpos_reg, active_p0_live, active_p1_live, active_p2_live, active_p3_live, active_m0_live, active_m1_live, active_m2_live, active_m3_live, active_pf3_collision_live, active_bk_modify_reg, active_bk_modify_next, active_bk_valid_reg, active_hr_reg, visible_live)
begin
hblank_next <= hblank_reg;
reset_counter <= '0';
counter_load_value <= (others=>'0');
vsync_next <= vsync_reg;
odd_scanline_next <= odd_scanline_reg;
start_of_field <= '0';
-- NB high res mode gives pf2 - which is or of the two pixels
highres_next <= highres_reg;
-- for gtia modes
an_prev_next <= an_prev_reg;
an_prev2_next <= an_prev2_reg;
an_prev3_next <= an_prev3_reg;
-- decoded AN
visible_live <= '0';
active_hr_next <= active_hr_reg;
active_bk_modify_next <= active_bk_modify_reg;
active_bk_valid_next <= active_bk_valid_reg;
active_bk_live <= '0';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_live <= '0';
active_pf3_collision_live <= '0';
active_pm0_live <= '0';
active_pm1_live <= '0';
active_pm2_live <= '0';
active_pm3_live <= '0';
if (COLOUR_CLOCK = '1') then
visible_live <= '1';
vsync_next <= '0';
hblank_next <= '0';
an_prev_next <= an;
an_prev2_next <= an_prev_reg;
an_prev3_next <= an_prev2_reg;
active_pm0_live <= active_p0_live or (active_m0_live and not(prior_delayed_reg(4)));
active_pm1_live <= active_p1_live or (active_m1_live and not(prior_delayed_reg(4)));
active_pm2_live <= active_p2_live or (active_m2_live and not(prior_delayed_reg(4)));
active_pm3_live <= active_p3_live or (active_m3_live and not(prior_delayed_reg(4)));
active_bk_modify_next <= (others=>'0');
active_bk_valid_next <= (others=>'1');
active_hr_next <= (others=>'0');
-- 000 background colour
-- 001 vsync
-- 01X hsync (low bit is high res mode - i.e. 2 pixels per colour clock)
-- 1XX colour 0 to colour 3
-- in gtia modes then we listen for 2 colour clocks to get one pixels
-- 1ZY (giving signal ZYXV for 4 bit colour reg/luminance - unfortunately we only have 9 colour regs!)
-- 1XV
if (highres_reg = '1') then
if (an(2) = '1') then
active_hr_next <= AN(1 downto 0);
end if;
active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= an(2);
active_pf2_collision_live <= an(2) and (an(1) or an(0));
active_pf3_collision_live <= '0';
else
-- gtia modes
case prior_delayed_reg(7 downto 6) is
when "00" =>
-- normal mode
active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
active_pf0_live <= an(2) and not(an(1)) and not(an(0));
active_pf1_live <= an(2) and not(an(1)) and an(0);
active_pf2_live <= an(2) and an(1) and not(an(0));
active_pf2_collision_live <= an(2) and an(1) and not(an(0));
active_pf3_collision_live <= an(2) and an(1) and an(0);
when "01" =>
-- 1 colour/16 luminance
-- no playfield collisions
-- 5th player gets my luminance
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_collision_live <= '0';
active_bk_live <= '1';
if (hpos_reg(0) = '1') then
active_bk_modify_next(3 downto 0) <= an_prev_reg(1 downto 0)&an(1 downto 0);
else
active_bk_modify_next(3 downto 0) <= active_bk_modify_reg(3 downto 0);
end if;
when "10" =>
-- 9 colour
-- playfield collisions
-- no missile/player collisions from 'playfield' data though
-- offset by 1 colour clock...
if (hpos_reg(0) = '1') then
active_bk_live <= '0';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_collision_live <= '0';
case an_prev_reg(1 downto 0)&an(1 downto 0) is
when "0000" =>
active_pm0_live <= '1';
when "0001" =>
active_pm1_live <= '1';
when "0010" =>
active_pm2_live <= '1';
when "0011" =>
active_pm3_live <= '1';
when "0100"|"1100" =>
active_pf0_live <= an(2);
active_bk_live <= not(an(2));
when "0101"|"1101" =>
active_pf1_live <= an(2);
active_bk_live <= not(an(2));
when "0110"|"1110" =>
active_pf2_live <= an(2);
active_pf2_collision_live <= an(2);
active_bk_live <= not(an(2));
when "0111"|"1111" =>
active_pf3_collision_live <= an(2);
active_bk_live <= not(an(2));
when others =>
active_bk_live <= '1';
end case;
else
active_bk_live <= '0';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_collision_live <= '0';
case an_prev2_reg(1 downto 0)&an_prev_reg(1 downto 0) is
when "0000" =>
active_pm0_live <= '1';
when "0001" =>
active_pm1_live <= '1';
when "0010" =>
active_pm2_live <= '1';
when "0011" =>
active_pm3_live <= '1';
when "0100"|"1100" =>
active_pf0_live <= an_prev_reg(2);
active_bk_live <= not(an_prev_reg(2));
when "0101"|"1101" =>
active_pf1_live <= an_prev_reg(2);
active_bk_live <= not(an_prev_reg(2));
when "0110"|"1110" =>
active_pf2_live <= an_prev_reg(2);
active_pf2_collision_live <= an_prev_reg(2);
active_bk_live <= not(an_prev_reg(2));
when "0111"|"1111" =>
active_pf3_collision_live <= an_prev_reg(2);
active_bk_live <= not(an_prev_reg(2));
when others =>
active_bk_live <= '1';
end case;
end if;
when "11" =>
-- 16 colour/1 luminance
-- no playfield collisions
-- 5th player gets our luminance
active_bk_live <= '1';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_collision_live <= '0';
if (hpos_reg(0) = '1') then
active_bk_modify_next(7 downto 4) <= an_prev_reg(1 downto 0)&an(1 downto 0);
else
active_bk_modify_next(7 downto 4) <= active_bk_modify_reg(7 downto 4);
end if;
if (active_bk_modify_next(7 downto 4) = "0000") then
active_bk_valid_next(3 downto 0) <= "0000";
end if;
when others =>
-- nop
end case;
end if;
if (prior_delayed_reg(4) = '1') then
active_pf3_live <= active_pf3_collision_live or active_m0_live or active_m1_live or active_m2_live or active_m3_live;
else
active_pf3_live <= active_pf3_collision_live;
end if;
if (not (prior_delayed2_reg(7 downto 6) = "00")) then
-- force off flip flop when in gtia mode
highres_next <= '0';
end if;
-- hblank
if (an_prev_reg(2 downto 1) = "01") then
hblank_next <= '1';
active_bk_live <= '0';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_live <= '0';
active_pf3_collision_live <= '0';
highres_next <= an_prev_reg(0);
if (COLOUR_CLOCK_ORIGINAL='1') then
if (hblank_reg = '0' and vsync_reg = '0') then
reset_counter <= '1';
counter_load_value <= X"E0"; -- 2 lower than antic
odd_scanline_next <= not(odd_scanline_reg);
end if;
end if;
end if;
if (an(2 downto 1) = "01") then
visible_live <= '0';
end if;
-- vsync
if (an_prev_reg = "001") then
active_bk_live <= '0';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_live <= '0';
active_pf3_collision_live <= '0';
vsync_next <= '1';
odd_scanline_next <= '0';
visible_live <= '0';
start_of_field <= not(vsync_reg);
end if;
-- during vblank we reset our own counter - since Antic does not clear hblank_reg
if (hpos_reg = X"E3" and COLOUR_CLOCK_ORIGINAL='1') then
reset_counter <= '1';
counter_load_value <= X"00";
end if;
end if;
end process;
-- hpos
counter_hpos : simple_counter
generic map (COUNT_WIDTH=>8)
port map (clk=>clk, reset_n=>reset_n, increment=>COLOUR_CLOCK_ORIGINAL, load=>reset_counter, load_value=>counter_load_value, current_value=>hpos_reg);
-- visible region
-- process(hpos_reg,vpos_reg)
-- begin
-- visible_live <= '1';
--
---- if (unsigned(vpos_reg) < to_unsigned(8,9)) then
---- visible_live <= '0';
---- end if;
----
---- if (unsigned(vpos_reg) > to_unsigned(247,9)) then
---- visible_live <= '0';
---- end if;
----
---- if (unsigned(hpos_reg) <= to_unsigned(34,8)) then
---- visible_live <= '0';
---- end if;
----
---- if (unsigned(hpos_reg) > to_unsigned(221,8)) then
---- visible_live <= '0';
---- end if;
-- end process;
-- generate hsync
process(hpos_reg, hsync_reg, hsync_end, burst_reg, burst_end, vsync_reg, vsync_next)
begin
hsync_start <= '0';
hsync_next <= hsync_reg;
burst_start <= '0';
burst_next <= burst_reg;
if (unsigned(hpos_reg) = X"D4" and vsync_reg = '1') then
hsync_start <= '1';
hsync_next <= '1';
end if;
if (unsigned(hpos_reg) = X"0" and vsync_reg = '0' ) then
hsync_start <= '1';
hsync_next <= '1';
end if;
if (unsigned(hpos_reg) = X"14" and vsync_reg = '0' ) then
burst_start <= '1';
burst_next <= '1';
end if;
if (hsync_end = '1') then
hsync_next <= '0';
end if;
if (burst_end = '1') then
burst_next <= '0';
end if;
if (vsync_next = '0' and vsync_reg = '1') then
hsync_next <= '0';
end if;
end process;
hsync_delay : delay_line
generic map (COUNT=>15)
port map(clk=>clk,sync_reset=>'0',data_in=>hsync_start,enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hsync_end);
burst_delay : delay_line
generic map (COUNT=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>burst_start,enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>burst_end);
-- pmg dma
process(CPU_ENABLE_ORIGINAL,antic_fetch,memory_data_in,hsync_start,pmg_dma_state_reg,gractl_reg,odd_scanline_reg,vdelay_reg,grafm_reg, visible_live,hpos_reg, hblank_reg)
begin
pmg_dma_state_next <= pmg_dma_state_reg;
grafm_dma_load <= '0';
grafm_dma_next <= grafm_reg;
grafp0_dma_load <= '0';
grafp0_dma_next <= (others=>'0');
grafp1_dma_load <= '0';
grafp1_dma_next <= (others=>'0');
grafp2_dma_load <= '0';
grafp2_dma_next <= (others=>'0');
grafp3_dma_load <= '0';
grafp3_dma_next <= (others=>'0');
-- pull pmg data from bus
if (hpos_reg = X"E1") then
pmg_dma_state_next <= pmg_dma_missile;
end if;
-- we start from the first antic fetch
-- TODO - CPU enable does not identify next 'antic' cycle in turbo mode...
case pmg_dma_state_reg is
when pmg_dma_missile =>
if (antic_fetch = '1' and cpu_enable_original = '1' and hblank_reg = '1' and visible_live = '0' and hpos_reg(7 downto 4) = "0000") then
-- here we have the missile0
grafm_dma_load <= gractl_reg(0);
if ((odd_scanline_reg or not(vdelay_reg(0))) = '1') then
grafm_dma_next(1 downto 0) <= memory_data_in(1 downto 0);
end if;
if ((odd_scanline_reg or not(vdelay_reg(1))) = '1') then
grafm_dma_next(3 downto 2) <= memory_data_in(3 downto 2);
end if;
if ((odd_scanline_reg or not(vdelay_reg(2))) = '1') then
grafm_dma_next(5 downto 4) <= memory_data_in(5 downto 4);
end if;
if ((odd_scanline_reg or not(vdelay_reg(3))) = '1') then
grafm_dma_next(7 downto 6) <= memory_data_in(7 downto 6);
end if;
pmg_dma_state_next <= pmg_dma_instruction;
end if;
when pmg_dma_instruction =>
if (CPU_ENABLE_ORIGINAL = '1') then
pmg_dma_state_next <= pmg_dma_player0;
end if;
when pmg_dma_player0 =>
if (CPU_ENABLE_ORIGINAL = '1') then
-- here we have player0
grafp0_dma_next <= memory_data_in;
grafp0_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(4)));
pmg_dma_state_next <= pmg_dma_player1;
end if;
when pmg_dma_player1 =>
if (CPU_ENABLE_ORIGINAL = '1') then
-- here we have player1
grafp1_dma_next <= memory_data_in;
grafp1_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(5)));
pmg_dma_state_next <= pmg_dma_player2;
end if;
when pmg_dma_player2 =>
if (CPU_ENABLE_ORIGINAL = '1') then
-- here we have player1
grafp2_dma_next <= memory_data_in;
grafp2_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(6)));
pmg_dma_state_next <= pmg_dma_player3;
end if;
when pmg_dma_player3 =>
if (CPU_ENABLE_ORIGINAL = '1') then
-- here we have player1
grafp3_dma_next <= memory_data_in;
grafp3_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(7)));
pmg_dma_state_next <= pmg_dma_done;
end if;
when others =>
-- nop
end case;
end process;
-- pmg display - same for all pmgs
-- TODO: priority
player0 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp0_delayed_reg,size=>sizep0_delayed_reg(1 downto 0),bitmap=>grafp0_reg, output=>active_p0_live);
player1 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp1_delayed_reg,size=>sizep1_delayed_reg(1 downto 0),bitmap=>grafp1_reg, output=>active_p1_live);
player2 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp2_delayed_reg,size=>sizep2_delayed_reg(1 downto 0),bitmap=>grafp2_reg, output=>active_p2_live);
player3 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp3_delayed_reg,size=>sizep3_delayed_reg(1 downto 0),bitmap=>grafp3_reg, output=>active_p3_live);
grafm_reg10_extended <= grafm_reg(1 downto 0)&"000000";
grafm_reg32_extended <= grafm_reg(3 downto 2)&"000000";
grafm_reg54_extended <= grafm_reg(5 downto 4)&"000000";
grafm_reg76_extended <= grafm_reg(7 downto 6)&"000000";
missile0 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg10_extended, output=>active_m0_live);
missile1 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg32_extended, output=>active_m1_live);
missile2 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg54_extended, output=>active_m2_live);
missile3 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg76_extended, output=>active_m3_live);
-- calculate atari colour
priority_rules : gtia_priority
port map(clk=>clk, colour_enable=>colour_clock, prior=>prior_delayed_reg,p0=>active_pm0_live,p1=>active_pm1_live,p2=>active_pm2_live,p3=>active_pm3_live,pf0=>active_pf0_live,pf1=>active_pf1_live,pf2=>active_pf2_live,pf3=>active_pf3_live,bk=>active_bk_live,p0_out=>set_p0,p1_out=>set_p1,p2_out=>set_p2,p3_out=>set_p3,pf0_out=>set_pf0,pf1_out=>set_pf1,pf2_out=>set_pf2,pf3_out=>set_pf3,bk_out=>set_bk);
trigger_secondhalf <= colour_clock_HIGHRES and not colour_clock;
process(set_p0,set_p1,set_p2,set_p3,set_pf0,set_pf1,set_pf2,set_pf3,set_bk,highres_reg, active_hr_reg, colbk_delayed_reg, colpf0_delayed_reg, colpf1_delayed_reg, colpf2_delayed_reg, colpf3_delayed_reg, colpm0_delayed_reg, colpm1_delayed_reg, colpm2_delayed_reg, colpm3_delayed_reg, trigger_secondhalf, colour_clock, COLOUR_REG, hrcolour_reg, visible_live, active_bk_modify_next, active_bk_valid_next)
begin
colour_next <= colour_reg;
hrcolour_next <= hrcolour_reg;
if (trigger_secondhalf = '1') then
if (highres_reg = '1') then
colour_next <= hrcolour_reg;
end if;
end if;
if (colour_clock = '1') then
colour_next <=
(
((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
);
hrcolour_next <= -- SAME FIXME
(
((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
);
-- finally high-res mode overrides the luma
if (set_bk = '0' and highres_reg = '1') then
if (active_hr_reg(1) = '1') then
colour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';
end if;
if (active_hr_reg(0) = '1') then
hrcolour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';
end if;
end if;
if (visible_live = '0') then
colour_next <= X"00";
hrcolour_next <= X"00";
end if;
end if;
end process;
-- collision detection
process (colour_clock, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg,hitclr_write,active_pf0_live,active_pf1_live,active_pf2_collision_live,active_pf3_collision_live,active_p0_live,active_p1_live,active_p2_live,active_p3_live,active_m0_live,active_m1_live,active_m2_live,active_m3_live, visible_live)
begin
m0pf_next <= m0pf_reg;
m1pf_next <= m1pf_reg;
m2pf_next <= m2pf_reg;
m3pf_next <= m3pf_reg;
m0pl_next <= m0pl_reg;
m1pl_next <= m1pl_reg;
m2pl_next <= m2pl_reg;
m3pl_next <= m3pl_reg;
p0pf_next <= p0pf_reg;
p1pf_next <= p1pf_reg;
p2pf_next <= p2pf_reg;
p3pf_next <= p3pf_reg;
p0pl_next <= p0pl_reg;
p1pl_next <= p1pl_reg;
p2pl_next <= p2pl_reg;
p3pl_next <= p3pl_reg;
if (hitclr_write = '1') then
m0pf_next <= (others=>'0');
m1pf_next <= (others=>'0');
m2pf_next <= (others=>'0');
m3pf_next <= (others=>'0');
m0pl_next <= (others=>'0');
m1pl_next <= (others=>'0');
m2pl_next <= (others=>'0');
m3pl_next <= (others=>'0');
p0pf_next <= (others=>'0');
p1pf_next <= (others=>'0');
p2pf_next <= (others=>'0');
p3pf_next <= (others=>'0');
p0pl_next <= (others=>'0');
p1pl_next <= (others=>'0');
p2pl_next <= (others=>'0');
p3pl_next <= (others=>'0');
else
if (visible_live = '1' and colour_clock = '1') then
m0pl_next <= m0pl_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
m1pl_next <= m1pl_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
m2pl_next <= m2pl_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
m3pl_next <= m3pl_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
m0pf_next <= m0pf_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
m1pf_next <= m1pf_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
m2pf_next <= m2pf_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
m3pf_next <= m3pf_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
p0pl_next <= p0pl_reg or (active_p0_live&active_p0_live&active_p0_live&'0' and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
p1pl_next <= p1pl_reg or (active_p1_live&active_p1_live&'0' &active_p1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
p2pl_next <= p2pl_reg or (active_p2_live&'0' &active_p2_live&active_p2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
p3pl_next <= p3pl_reg or ('0' &active_p3_live&active_p3_live&active_p3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
p0pf_next <= p0pf_reg or (active_p0_live&active_p0_live&active_p0_live&active_p0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
p1pf_next <= p1pf_reg or (active_p1_live&active_p1_live&active_p1_live&active_p1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
p2pf_next <= p2pf_reg or (active_p2_live&active_p2_live&active_p2_live&active_p2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
p3pf_next <= p3pf_reg or (active_p3_live&active_p3_live&active_p3_live&active_p3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
end if;
end if;
end process;
-- Writes to registers
process(cpu_data_in,wr_en,addr_decoded,hposp0_raw_reg,hposp1_raw_reg,hposp2_raw_reg,hposp3_raw_reg,hposm0_raw_reg,hposm1_raw_reg,hposm2_raw_reg,hposm3_raw_reg,sizep0_raw_reg,sizep1_raw_reg,sizep2_raw_reg,sizep3_raw_reg,sizem_raw_reg,grafp0_reg,grafp1_reg,grafp2_reg,grafp3_reg, grafm_reg, colpm0_raw_reg, colpm1_raw_reg, colpm2_raw_reg, colpm3_raw_reg, colpf0_raw_reg, colpf1_raw_reg,colpf2_raw_reg, colpf3_raw_reg, colbk_raw_reg, prior_raw_reg, vdelay_reg, gractl_reg, consol_output_reg, grafm_dma_load, grafm_dma_next, grafp0_dma_load, grafp0_dma_next, grafp1_dma_load, grafp1_dma_next, grafp2_dma_load, grafp2_dma_next, grafp3_dma_load, grafp3_dma_next)
begin
hposp0_raw_next <= hposp0_raw_reg;
hposp1_raw_next <= hposp1_raw_reg;
hposp2_raw_next <= hposp2_raw_reg;
hposp3_raw_next <= hposp3_raw_reg;
hposm0_raw_next <= hposm0_raw_reg;
hposm1_raw_next <= hposm1_raw_reg;
hposm2_raw_next <= hposm2_raw_reg;
hposm3_raw_next <= hposm3_raw_reg;
sizep0_raw_next <= sizep0_raw_reg;
sizep1_raw_next <= sizep1_raw_reg;
sizep2_raw_next <= sizep2_raw_reg;
sizep3_raw_next <= sizep3_raw_reg;
sizem_raw_next <= sizem_raw_reg;
grafp0_next <= grafp0_reg;
grafp1_next <= grafp1_reg;
grafp2_next <= grafp2_reg;
grafp3_next <= grafp3_reg;
grafm_next <= grafm_reg;
colpm0_raw_next <= colpm0_raw_reg;
colpm1_raw_next <= colpm1_raw_reg;
colpm2_raw_next <= colpm2_raw_reg;
colpm3_raw_next <= colpm3_raw_reg;
colpf0_raw_next <= colpf0_raw_reg;
colpf1_raw_next <= colpf1_raw_reg;
colpf2_raw_next <= colpf2_raw_reg;
colpf3_raw_next <= colpf3_raw_reg;
colbk_raw_next <= colbk_raw_reg;
prior_raw_next <= prior_raw_reg;
vdelay_next <= vdelay_reg;
gractl_next <= gractl_reg;
consol_output_next <= consol_output_reg;
hitclr_write <= '0';
if (grafm_dma_load = '1') then
grafm_next <= grafm_dma_next;
end if;
if (grafp0_dma_load = '1') then
grafp0_next <= grafp0_dma_next;
end if;
if (grafp1_dma_load = '1') then
grafp1_next <= grafp1_dma_next;
end if;
if (grafp2_dma_load = '1') then
grafp2_next <= grafp2_dma_next;
end if;
if (grafp3_dma_load = '1') then
grafp3_next <= grafp3_dma_next;
end if;
if (wr_en = '1') then
if(addr_decoded(0) = '1') then
hposp0_raw_next <= cpu_data_in;
end if;
if(addr_decoded(1) = '1') then
hposp1_raw_next <= cpu_data_in;
end if;
if(addr_decoded(2) = '1') then
hposp2_raw_next <= cpu_data_in;
end if;
if(addr_decoded(3) = '1') then
hposp3_raw_next <= cpu_data_in;
end if;
if(addr_decoded(4) = '1') then
hposm0_raw_next <= cpu_data_in;
end if;
if(addr_decoded(5) = '1') then
hposm1_raw_next <= cpu_data_in;
end if;
if(addr_decoded(6) = '1') then
hposm2_raw_next <= cpu_data_in;
end if;
if(addr_decoded(7) = '1') then
hposm3_raw_next <= cpu_data_in;
end if;
if(addr_decoded(8) = '1') then
sizep0_raw_next <= cpu_data_in(1 downto 0);
end if;
if(addr_decoded(9) = '1') then
sizep1_raw_next <= cpu_data_in(1 downto 0);
end if;
if(addr_decoded(10) = '1') then
sizep2_raw_next <= cpu_data_in(1 downto 0);
end if;
if(addr_decoded(11) = '1') then
sizep3_raw_next <= cpu_data_in(1 downto 0);
end if;
if(addr_decoded(12) = '1') then
sizem_raw_next <= cpu_data_in;
end if;
if(addr_decoded(13) = '1') then
grafp0_next <= cpu_data_in;
end if;
if(addr_decoded(14) = '1') then
grafp1_next <= cpu_data_in;
end if;
if(addr_decoded(15) = '1') then
grafp2_next <= cpu_data_in;
end if;
if(addr_decoded(16) = '1') then
grafp3_next <= cpu_data_in;
end if;
if(addr_decoded(17) = '1') then
grafm_next <= cpu_data_in;
end if;
if(addr_decoded(18) = '1') then
colpm0_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(19) = '1') then
colpm1_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(20) = '1') then
colpm2_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(21) = '1') then
colpm3_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(22) = '1') then
colpf0_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(23) = '1') then
colpf1_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(24) = '1') then
colpf2_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(25) = '1') then
colpf3_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(26) = '1') then
colbk_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(27) = '1') then
prior_raw_next <= cpu_data_in;
end if;
if(addr_decoded(28) = '1') then
vdelay_next <= cpu_data_in;
end if;
if(addr_decoded(29) = '1') then
gractl_next <= cpu_data_in(2 downto 0);
end if;
if(addr_decoded(30) = '1') then
-- clear the collision regs
hitclr_write <= '1';
end if;
if(addr_decoded(31) = '1') then
consol_output_next <= cpu_data_in(3 downto 0);
end if;
end if;
end process;
-- delays...
-- TODO - needs more attention ...
-- The prior behaviour here in real hardware is all over the place...
-- THESE CAN TAKE MUCH LESS SPACE - only need to store per CPU cycle, not per colour clock original
prior_short_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>6)
port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(5 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(5 downto 0));
prior_long_delay : wide_delay_line
generic map (COUNT=>3, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(7 downto 6));
prior_longer_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed2_reg(7 downto 6));
colbk_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colbk_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colbk_delayed_reg(7 downto 1));
colpm0_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpm0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm0_delayed_reg(7 downto 1));
colpm1_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpm1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm1_delayed_reg(7 downto 1));
colpm2_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpm2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm2_delayed_reg(7 downto 1));
colpm3_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpm3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm3_delayed_reg(7 downto 1));
colpf0_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpf0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf0_delayed_reg(7 downto 1));
colpf1_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpf1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf1_delayed_reg(7 downto 1));
colpf2_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpf2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf2_delayed_reg(7 downto 1));
colpf3_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpf3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf3_delayed_reg(7 downto 1));
hposp0_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposp0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp0_delayed_reg(7 downto 0));
hposp1_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposp1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp1_delayed_reg(7 downto 0));
hposp2_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposp2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp2_delayed_reg(7 downto 0));
hposp3_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposp3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp3_delayed_reg(7 downto 0));
hposm0_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposm0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm0_delayed_reg(7 downto 0));
hposm1_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposm1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm1_delayed_reg(7 downto 0));
hposm2_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposm2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm2_delayed_reg(7 downto 0));
hposm3_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposm3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm3_delayed_reg(7 downto 0));
sizep0_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>sizep0_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep0_delayed_reg(1 downto 0));
sizep1_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>sizep1_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep1_delayed_reg(1 downto 0));
sizep2_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>sizep2_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep2_delayed_reg(1 downto 0));
sizep3_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>sizep3_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep3_delayed_reg(1 downto 0));
sizem_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>sizem_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizem_delayed_reg(7 downto 0));
-- joystick
process(trig0_reg, trig1_reg, trig2_reg, trig3_reg, trig0, trig1, trig2, trig3, gractl_reg)
begin
trig0_next <= trig0;
trig1_next <= trig1;
trig2_next <= trig2;
trig3_next <= trig3;
if (gractl_reg(2) = '1') then
trig0_next <= trig0_reg and trig0;
trig1_next <= trig1_reg and trig1;
trig2_next <= trig2_reg and trig2;
trig3_next <= trig3_reg and trig3;
end if;
end process;
-- Read from registers
process(addr_decoded, CONSOL_OPTION, CONSOL_SELECT, CONSOL_START, consol_output_reg, trig0_reg, trig1_reg, trig2_reg, trig3_reg, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg, pal)
begin
data_out <= X"0F";
if (addr_decoded(0) = '1') then
data_out <= "0000"&m0pf_reg;
end if;
if (addr_decoded(1) = '1') then
data_out <= "0000"&m1pf_reg;
end if;
if (addr_decoded(2) = '1') then
data_out <= "0000"&m2pf_reg;
end if;
if (addr_decoded(3) = '1') then
data_out <= "0000"&m3pf_reg;
end if;
if (addr_decoded(4) = '1') then
data_out <= "0000"&p0pf_reg;
end if;
if (addr_decoded(5) = '1') then
data_out <= "0000"&p1pf_reg;
end if;
if (addr_decoded(6) = '1') then
data_out <= "0000"&p2pf_reg;
end if;
if (addr_decoded(7) = '1') then
data_out <= "0000"&p3pf_reg;
end if;
if (addr_decoded(8) = '1') then
data_out <= "0000"&m0pl_reg;
end if;
if (addr_decoded(9) = '1') then
data_out <= "0000"&m1pl_reg;
end if;
if (addr_decoded(10) = '1') then
data_out <= "0000"&m2pl_reg;
end if;
if (addr_decoded(11) = '1') then
data_out <= "0000"&m3pl_reg;
end if;
if (addr_decoded(12) = '1') then
data_out <= "0000"&p0pl_reg;
end if;
if (addr_decoded(13) = '1') then
data_out <= "0000"&p1pl_reg;
end if;
if (addr_decoded(14) = '1') then
data_out <= "0000"&p2pl_reg;
end if;
if (addr_decoded(15) = '1') then
data_out <= "0000"&p3pl_reg;
end if;
if (addr_decoded(16) = '1') then
data_out <= "0000000"&trig0_reg;
end if;
if (addr_decoded(17) = '1') then
data_out <= "0000000"&trig1_reg;
end if;
if (addr_decoded(18) = '1') then
data_out <= "0000000"&trig2_reg;
end if;
if (addr_decoded(19) = '1') then
data_out <= "0000000"&trig3_reg;
end if;
if (addr_decoded(20) = '1') then
data_out <= "0000"¬(pal&pal&pal)&'1';
end if;
if (addr_decoded(31) = '1') then
data_out <= "0000"&('0'¬(CONSOL_OPTION)¬(CONSOL_SELECT)¬(CONSOL_START) and (not consol_output_reg));
end if;
end process;
-- output
colour_out <= colour_reg;
vsync<=vsync_reg;
hsync<=hsync_reg;
blank<=hblank_reg or vsync_reg;
burst<=burst_reg;
odd_line<=odd_scanline_reg;
sound <= consol_output_reg(3);
end vhdl;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_STD
|
Extras/VHDL/STD_06600_bad.vhd
|
1
|
3438
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06600_bad.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Dimension of comparison elements: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_06600_bad is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(3 downto 0); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end STD_06600_bad;
--CODE
architecture Behavioral of STD_06600_bad is
signal Count : signed(7 downto 0); -- Counter output signal (unsigned converted)
signal Count_Length : unsigned(3 downto 0); -- Length input signal (unsigned converted)
begin
Count_Length <= unsigned(i_Length);
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count >= Count_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable = '1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
--CODE
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/lvov-pk02-mips/src/xsd/xsd_ram.vhd
|
1
|
5590
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file xsd_ram.vhd when simulating
-- the core, xsd_ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY xsd_ram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END xsd_ram;
ARCHITECTURE xsd_ram_a OF xsd_ram IS
-- synthesis translate_off
COMPONENT wrapped_xsd_ram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_xsd_ram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_xsd_ram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END xsd_ram_a;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/lvov-pk02-mips/src/lvov.vhd
|
1
|
21478
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- SRAM is used for Lvov Main 64Kb RAM
-- FPGA is used for all ROM's (16Kb Standard, 16Kb Chameleon )
-- FPGA is used for 16Kb Dual Port VRAM
entity lvov is
Port (
CLK50 : IN STD_LOGIC;
PS2_CLK : in STD_LOGIC;
PS2_DATA : in STD_LOGIC;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : buffer std_logic;
SRAM_OE : buffer std_logic;
SRAM_CE0 : buffer std_logic;
SRAM_CE1 : buffer std_logic;
SRAM_LB : buffer std_logic;
SRAM_UB : buffer std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
IO : out std_logic_vector(15 downto 0);
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
VGA_R : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_HSYNC : OUT STD_LOGIC;
VGA_VSYNC : OUT STD_LOGIC );
end lvov;
architecture Behavioral of lvov is
component T80se is
generic (
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 ); -- 0 => Single cycle I/O, 1 => Std I/O cycle
port (
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end component;
component mips_soc
port (
-- CLOCK
CPU_CLK : in std_logic;
VGA_CLK : in std_logic;
CPU_RESET : in std_logic;
-- VGA
VGA_R : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_VSYNC : out std_logic;
VGA_HSYNC : out std_logic;
-- SRAM
MEM_A : out std_logic_vector(31 downto 2);
MEM_DI : out std_logic_vector(31 downto 0);
MEM_DO : in std_logic_vector(31 downto 0);
MEM_MASK : out std_logic_vector(3 downto 0);
MEM_WR : out std_logic;
MEM_REQ : out std_logic;
MEM_BUSY : in std_logic;
-- Keyboard
KEYB_DATA : in std_logic_vector(7 downto 0);
-- Sound
MIPS_BEEPER : out std_logic;
-- SD Card
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
-- FDC Ports
VG93_CLK : in std_logic;
VG93_nCLR : in std_logic;
VG93_IRQ : out std_logic;
VG93_DRQ : out std_logic;
VG93_A : in std_logic_vector(1 downto 0);
VG93_D_IN : in std_logic_vector(7 downto 0);
VG93_D_OUT : out std_logic_vector(7 downto 0);
VG93_nCS : in std_logic;
VG93_nRD : in std_logic;
VG93_nWR : in std_logic;
VG93_nDDEN : in std_logic;
VG93_HRDY : in std_logic;
FDC_DRIVE : in std_logic_vector(1 downto 0);
FDC_nSIDE : in std_logic;
TST : out std_logic
);
end component;
COMPONENT a8255 IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
nCS : IN std_logic;
nRD : IN std_logic;
nWR : IN std_logic;
A : IN std_logic_vector (1 DOWNTO 0);
DIN : IN std_logic_vector (7 DOWNTO 0);
PAIN : IN std_logic_vector (7 DOWNTO 0);
PBIN : IN std_logic_vector (7 DOWNTO 0);
PCIN : IN std_logic_vector (7 DOWNTO 0);
DOUT : OUT std_logic_vector (7 DOWNTO 0);
PAOUT : OUT std_logic_vector (7 DOWNTO 0);
PAEN : OUT std_logic;
PBOUT : OUT std_logic_vector (7 DOWNTO 0);
PBEN : OUT std_logic;
PCOUT : OUT std_logic_vector (7 DOWNTO 0);
PCEN : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
-- CLK 32.5 MHz is 1/2 of pixelxlock 1024x768@60Hz (65MHz)
signal CLK : std_logic;
signal nRESET : std_logic := '0';
signal TICK : std_logic_vector(3 downto 0) := "0000";
signal LOCKED : std_logic;
signal nRESET_MEM : std_logic := '0';
signal SRAM_DO : std_logic_vector(7 downto 0);
signal KEYB_A : std_logic_vector(7 downto 0);
signal KEYB_D : std_logic_vector(7 downto 0);
signal KEYB_A2 : std_logic_vector(3 downto 0);
signal KEYB_D2 : std_logic_vector(3 downto 0);
signal KEYB_CTRL : std_logic_vector(7 downto 0);
signal COLORS : std_logic_vector(6 downto 0);
-- ROM_INIT = 1 on reset and maps ROM to address 0000
-- ROM_INIT = 0 on first I/O write
signal ROM_INIT : std_logic := '1';
-- CPU_CLK is 2.16MHz (32.5MHz/15) CPU Clock (Original 2.22MHz (20MHz/9))
signal CPU_CLK : std_logic;
signal nCPU_RD : std_logic;
signal nCPU_WR : std_logic;
signal CPU_A : std_logic_vector(15 downto 0);
signal RAM_A : std_logic_vector(17 downto 0);
signal CPU_DI : std_logic_vector(7 downto 0);
signal CPU_DO : std_logic_vector(7 downto 0);
signal nIO_RQ : std_logic;
signal nMEM_RQ : std_logic;
signal nCPU_WAIT : std_logic;
signal LV_SRAM_DO : std_logic_vector(7 downto 0);
signal nLV_SRAM_CS : std_logic;
signal ROM_D : std_logic_vector(7 downto 0);
signal SD_CLK_R : std_logic;
signal SD_DATA : std_logic_vector(6 downto 0);
signal SD_O : std_logic_vector(7 downto 0);
signal VRAM_DO : std_logic_vector(7 downto 0);
signal VRAM_WE : std_logic_vector(0 downto 0);
signal VRAM_VA : std_logic_vector(13 downto 0);
signal VRAM_VD : std_logic_vector(7 downto 0);
signal nVRAM_CS : std_logic;
signal nVRAM_EN : std_logic;
signal VV55_SYS_DO : std_logic_vector(7 downto 0);
signal VV55_KBD_DO : std_logic_vector(7 downto 0);
signal nVV55_SYS_CS : std_logic;
signal nVV55_KBD_CS : std_logic;
signal nROM_CS : std_logic;
signal nHALT : std_logic;
signal nRFSH : std_logic;
signal BEEPER : std_logic;
signal BEEPER_EN : std_logic;
-- Lvov VGA Signals
signal LV_VGA_R : STD_LOGIC_VECTOR(3 downto 0);
signal LV_VGA_G : STD_LOGIC_VECTOR(3 downto 0);
signal LV_VGA_B : STD_LOGIC_VECTOR(3 downto 0);
signal LV_VGA_HSYNC : STD_LOGIC;
signal LV_VGA_VSYNC : STD_LOGIC;
-- VGA Select Signal
signal VGA_SEL : std_logic := '0';
signal CLK25 : std_logic;
signal MIPS_RESET : std_logic := '1';
-- Host VGA Signals
signal MIPS_VGA_R : STD_LOGIC_VECTOR(3 downto 0);
signal MIPS_VGA_G : STD_LOGIC_VECTOR(3 downto 0);
signal MIPS_VGA_B : STD_LOGIC_VECTOR(3 downto 0);
signal MIPS_VGA_HSYNC : STD_LOGIC;
signal MIPS_VGA_VSYNC : STD_LOGIC;
-- Host SRAM Signals
signal MIPS_MEM_A : std_logic_vector(31 downto 2);
signal MIPS_MEM_DI : std_logic_vector(31 downto 0);
signal MIPS_MEM_DO : std_logic_vector(31 downto 0);
signal MIPS_MEM_MASK : std_logic_vector(3 downto 0);
signal MIPS_MEM_WR : std_logic;
signal MIPS_MEM_REQ : std_logic;
signal MIPS_MEM_BUSY : std_logic;
signal MIPS_KEYB_DATA : std_logic_vector(7 downto 0);
signal MIPS_BEEPER : std_logic;
-- FDC Ports
signal VG93_nCLR : std_logic;
signal VG93_CLK : std_logic;
signal VG93_IRQ : std_logic;
signal VG93_DRQ : std_logic;
signal VG93_D_OUT : std_logic_vector(7 downto 0);
signal VG93_nCS : std_logic;
signal VG93_nDDEN : std_logic;
signal VG93_HRDY : std_logic;
signal FDC_DRIVE : std_logic_vector(1 downto 0);
signal FDC_nSIDE : std_logic;
signal nFDC_CS : std_logic;
signal TST : std_logic;
-- PK-02 Signals
signal PORT_F0_CS : std_logic;
signal RAM_PAGE0 : std_logic;
signal RAM_PAGE1 : std_logic;
signal nROM_EN : std_logic;
signal HI_RES : std_logic;
signal BLANK_SCR : std_logic;
signal INT_EN : std_logic;
signal RAM_BANK0 : std_logic;
signal RAM_BANK1 : std_logic;
signal int_cnt : std_logic_vector(19 downto 0);
signal nINT : std_logic := '1';
signal nM1 : std_logic;
-- AY Signals
signal CLC : std_logic;
signal nAY_CS : std_logic;
signal AY_DO : std_logic_vector(7 downto 0);
signal AY_A : std_logic_vector(7 downto 0);
signal AY_B : std_logic_vector(7 downto 0);
signal AY_C : std_logic_vector(7 downto 0);
signal AY_BC : std_logic;
signal AUDIO_L : std_logic_vector(9 downto 0);
signal AUDIO_R : std_logic_vector(9 downto 0);
signal clc_cnt : std_logic_vector(4 downto 0);
begin
LV_Z80:T80se
port map (
RESET_n => nRESET,
CLK_n => CPU_CLK,
CLKEN => '1',
WAIT_n => nCPU_WAIT,
INT_n => nINT,
NMI_n => '1',
BUSRQ_n => '1',
M1_n => nM1,
MREQ_n => nMEM_RQ,
IORQ_n => nIO_RQ,
RD_n => nCPU_RD,
WR_n => nCPU_WR,
RFSH_n => nRFSH,
HALT_n => nHALT,
BUSAK_n => open,
A => CPU_A,
DI => CPU_DI,
DO => CPU_DO
);
u_Host : mips_soc
PORT MAP (
-- CLOCK
CPU_CLK => CLK,
VGA_CLK => CLK25,
CPU_RESET => MIPS_RESET,
-- VGA
VGA_R => MIPS_VGA_R,
VGA_G => MIPS_VGA_G,
VGA_B => MIPS_VGA_B,
VGA_VSYNC => MIPS_VGA_VSYNC,
VGA_HSYNC => MIPS_VGA_HSYNC,
-- SRAM
MEM_A => MIPS_MEM_A,
MEM_DI => MIPS_MEM_DI,
MEM_DO => MIPS_MEM_DO,
MEM_MASK => MIPS_MEM_MASK,
MEM_WR => MIPS_MEM_WR,
MEM_REQ => MIPS_MEM_REQ,
MEM_BUSY => MIPS_MEM_BUSY,
-- Keyboard
KEYB_DATA => MIPS_KEYB_DATA,
-- Sound
MIPS_BEEPER => MIPS_BEEPER,
-- SD Card
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_SCK => SD_SCK,
SD_CS => SD_CS,
-- FDC Ports
VG93_CLK => VG93_CLK,
VG93_nCLR => VG93_nCLR,
VG93_IRQ => VG93_IRQ,
VG93_DRQ => VG93_DRQ,
VG93_A => CPU_A (1 downto 0),
VG93_D_IN => CPU_DO,
VG93_D_OUT => VG93_D_OUT,
VG93_nCS => VG93_nCS,
VG93_nRD => nCPU_RD,
VG93_nWR => nCPU_WR,
VG93_nDDEN => VG93_nDDEN,
VG93_HRDY => VG93_HRDY,
FDC_DRIVE => FDC_DRIVE,
FDC_nSIDE => FDC_nSIDE,
TST => TST
);
u_dp_ram : entity work.dp_sram
PORT MAP (
-- CLOCK
CLK => CLK,
nRESET => nRESET_MEM,
-- PORT A
DI_A => CPU_DO,
DO_A => LV_SRAM_DO,
ADDR_A => RAM_A,
nWE_A => nCPU_WR,
nCS_A => nLV_SRAM_CS,
nOE_A => nCPU_RD,
nWAIT_A => nCPU_WAIT,
-- PORT B - MIPS must be on chanel B
DI_B => MIPS_MEM_DI,
DO_B => MIPS_MEM_DO,
ADDR_B => MIPS_MEM_A,
nWE_B => not MIPS_MEM_WR,
nCS_B => not MIPS_MEM_REQ,
nOE_B => '0',
WAIT_B => MIPS_MEM_BUSY,
MEM_MASK_B => MIPS_MEM_MASK,
-- SRAM
SRAM_A => SRAM_A,
SRAM_D => SRAM_D,
SRAM_WE => SRAM_WE,
SRAM_OE => SRAM_OE,
SRAM_CE0 => SRAM_CE0,
SRAM_CE1 => SRAM_CE1,
SRAM_LB => SRAM_LB,
SRAM_UB => SRAM_UB
);
-- Silicone device resets port registers on reset signal
-- VHDL device - not
-- Important for nVRAM_EN
SYS_VV55: a8255
port map(
RESET => not nRESET,
CLK => CLK,
nCS => nVV55_SYS_CS,
nRD => nCPU_RD,
nWR => nCPU_WR,
A => CPU_A(1 downto 0),
DIN => CPU_DO,
PAIN => (others => '1'),
PBIN => (others => '1'),
PCIN(7 downto 5) => (others => '1'),
PCIN(4) => '1', -- TAPE IN
PCIN(3) => '1', -- PCIN 3 to 0 must be connected like this
PCIN(2) => '1', -- in order to play Hawk Storm game to work
PCIN(1) => nVRAM_EN, -- and do not corrupt memory in Hawk Storm
PCIN(0) => BEEPER, -- and other PK-02 games
DOUT => VV55_SYS_DO,
PAOUT => open,
PAEN => open,
PBOUT(6 downto 0) => COLORS,
PBOUT(7) => BEEPER_EN,
PBEN => open,
PCOUT(0) => BEEPER,
PCOUT(1) => nVRAM_EN,
PCOUT(7 downto 2) => open,
PCEN => open
);
KBD_VV55: a8255
port map(
RESET => not nRESET,
CLK => CLK,
nCS => nVV55_KBD_CS,
nRD => nCPU_RD,
nWR => nCPU_WR,
A => CPU_A(1 downto 0),
DIN => CPU_DO,
PAIN => (others => '1'),
PBIN => KEYB_D,
PCIN(3 downto 0) => KEYB_A2, -- PCIN 3 to 0 must be connected like this,
PCIN(7 downto 4) => KEYB_D2, -- otherwize BASICZ80 will run in step execution (F5) mode always
DOUT => VV55_KBD_DO,
PAOUT => KEYB_A,
PAEN => open,
PBOUT => open,
PBEN => open,
PCOUT(3 downto 0) => KEYB_A2,
PCOUT(7 downto 4) => open,
PCEN => open
);
u_AY8910 : entity work.ay8910
port map(
CLK => CLK,
CLC => CLC,
RESET => nRESET,
BDIR => not nCPU_WR,
CS => nAY_CS,
BC => CPU_A(14),
DI => CPU_DO,
DO => AY_DO,
OUT_A => AY_A,
OUT_B => AY_B,
OUT_C => AY_C );
u_DAC_L : entity work.dac
port map(
clk_i => CLK,
res_n_i => nRESET,
dac_i => AUDIO_L,
dac_o => SOUND_L );
u_DAC_R : entity work.dac
port map(
clk_i => CLK,
res_n_i => nRESET,
dac_i => AUDIO_R,
dac_o => SOUND_R );
-- u_CLOCK is PLL 50 to 32.5 MHz created using wizard
-- CLK 32.5 MHz is 1/2 of pixelxlock 1024x768@60Hz (65MHz)
u_CLOCK : entity work.clock
port map(
CLK_IN => CLK50,
CLK_OUT => CLK,
CLK_OUT2 => CLK25,
LOCKED => LOCKED
);
-- FPGA Standard Lvov ROM 16Kb first 2K replaced with Chameleon DOS ROM created using wizard.
u_ROM : entity work.cham_rom
port map(
CLKA => CLK,
ADDRA => CPU_A(13 downto 0),
DOUTA => ROM_D );
-- Handcrafted Lvov video section
u_VIDEO : entity work.video
port map(
CLK => CLK,
RESET => '1',
VRAM_A => VRAM_VA,
VRAM_D => VRAM_VD,
COLORS => COLORS,
R => LV_VGA_R,
G => LV_VGA_G,
B => LV_VGA_B,
HSYNC => LV_VGA_HSYNC,
VSYNC => LV_VGA_VSYNC,
HI_RES => HI_RES,
BLANK_SCR => BLANK_SCR );
-- FPGA Dual Port RAM 16Kb created using wizard.
u_VRAM : entity work.vram
port map(
clka => CLK,
wea => VRAM_WE,
addra => CPU_A(13 downto 0),
dina => CPU_DO,
douta => VRAM_DO,
clkb => CLK,
web => "0",
addrb => VRAM_VA,
dinb => "11111111",
doutb => VRAM_VD );
-- Handcrafted PS2 to Lvov Matrix keyboard adapter
u_KEYBOARD : entity work.keyboard
port map(
CLK => CLK,
RESET => nRESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CONTROL => KEYB_CTRL,
KEYB_A => KEYB_A,
KEYB_D => KEYB_D,
KEYB_A2 => KEYB_A2,
KEYB_D2 => KEYB_D2,
VGA_SEL => VGA_SEL,
KEYB_DATA => MIPS_KEYB_DATA
);
-- Divider for CPU CLK
-- Generate CPU_CLK 2.16MHz (32.5MHz/15) CPU Clock (Original 2.22MHz (20MHz/9))
-- CLK 32.5 MHz is 1/2 of pixelxlock 1024x768@60Hz (65MHz)
-- nRESET is active during one period of CPU_CLK
process (CLK)
begin
if rising_edge(CLK) then
if KEYB_CTRL(0) = '1' then
TICK <= (others => '0');
nRESET <= '0';
CPU_CLK <= '0';
else
if KEYB_CTRL(1) = '1' then
MIPS_RESET <= '1';
end if;
if KEYB_CTRL(2) = '1' then
VGA_SEL <= '1';
end if;
if KEYB_CTRL(3) = '1' then
VGA_SEL <= '0';
end if;
if LOCKED = '1' then
TICK <= TICK + 1;
end if;
CPU_CLK <= '0';
if TICK = "1111" then
CPU_CLK <= '1';
nRESET <= '1';
MIPS_RESET <= '0';
nRESET_MEM <= '1';
end if;
end if;
end if;
end process;
-- Video output selector
VGA_R <= LV_VGA_R when VGA_SEL = '0' else MIPS_VGA_R;
VGA_G <= LV_VGA_G when VGA_SEL = '0' else MIPS_VGA_G;
VGA_B <= LV_VGA_B when VGA_SEL = '0' else MIPS_VGA_B;
VGA_HSYNC <= LV_VGA_HSYNC when VGA_SEL = '0' else MIPS_VGA_HSYNC;
VGA_VSYNC <= LV_VGA_VSYNC when VGA_SEL = '0' else MIPS_VGA_VSYNC;
-- Debug Stuff
IO(1) <= CLK; -- OSC D8
IO(3) <= MIPS_MEM_REQ;
IO(5) <= MIPS_MEM_WR;
IO(7) <= MIPS_MEM_BUSY;
IO(9) <= nLV_SRAM_CS;
IO(11) <= nCPU_WR;
IO(13) <= nCPU_WAIT;
IO(15) <= MIPS_RESET or (not nRESET); -- OSC D15
IO(14) <= '0'; --SRAM_CE0; -- OSC D0
IO(12) <= '0'; --SRAM_CE1;
IO(10) <= '0'; --SRAM_OE;
IO(8) <= '0'; --SRAM_WE;
IO(6) <= '0'; --SRAM_LB;
IO(4) <= '0'; --SRAM_UB;
IO(2) <= '0';
IO(0) <= TST; -- OSC D7
--IO(14) <= MIPS_MEM_DO(0); -- OSC D0
--IO(12) <= MIPS_MEM_DO(1);
--IO(10) <= MIPS_MEM_DO(2);
--IO(8) <= MIPS_MEM_DO(3);
--IO(6) <= MIPS_MEM_DO(4);
--IO(4) <= MIPS_MEM_DO(5);
--IO(2) <= MIPS_MEM_DO(6);
--IO(0) <= MIPS_MEM_DO(7); -- OSC D7
-- System bus device multiplexor
-- Connecting appropriate memory or I/O to the system bus for reading and writing
-- ROM is in CPU address space 0xC000 - 0xFFFF
-- nLV_SRAM_CS <= '0' when nMEM_RQ = '0' and nRFSH = '1' and nHALT = '1' and nVRAM_CS = '1' and nROM_CS = '1' and TICK = "0100" else '1';
nLV_SRAM_CS <= '0' when nMEM_RQ = '0' and nRFSH = '1' and nHALT = '1' and nVRAM_CS = '1' and nROM_CS = '1' and (nCPU_WR = '0' or nCPU_RD = '0') else '1';
-- Read ROM, VRAM and RAM
CPU_DI <=
ROM_D when nROM_CS = '0' else
VRAM_DO when nVRAM_CS = '0' else
LV_SRAM_DO when nMEM_RQ = '0' and nRFSH = '1' else
-- Read ports
VG93_IRQ & VG93_DRQ & "111111" when nFDC_CS = '0' else
VG93_D_OUT when VG93_nCS = '0' else
VV55_SYS_DO when nVV55_SYS_CS = '0' else
VV55_KBD_DO when nVV55_KBD_CS = '0' else
AY_DO when nAY_CS = '0' else
(others => '1');
nROM_CS <= '0' when nMEM_RQ = '0' and nRFSH = '1' and nHALT = '1' and ( (CPU_A(15 downto 14) = "11" and nROM_EN = '0') or ROM_INIT = '1' ) else '1';
-- VRAM Control
-- VRAM is in CPU address space 0x4000 - 0x7FFF
nVRAM_CS <= '0' when nMEM_RQ = '0' and nRFSH = '1' and nHALT = '1' and CPU_A(15 downto 14) = "01" and nVRAM_EN = '0' else '1';
VRAM_WE <= "1" when nCPU_WR = '0' and nVRAM_CS = '0' else "0";
-- Ports 0xD0-0xDF - PK-02 bits 7-6 (15-14) are ignored
nVV55_KBD_CS <= '0' when nIO_RQ = '0' and CPU_A(5 downto 4) = "01" else '1';
nVV55_SYS_CS <= '0' when nIO_RQ = '0' and CPU_A(5 downto 4) = "00" else '1';
-- VG93 Ports 0xE0-0xE3
VG93_nCS <= '0' when nIO_RQ = '0' and CPU_A(7 downto 2) = "111000" else '1';
VG93_CLK <= '0' when TICK = "0011" else '1';
-- FDC Port 0xE4
nFDC_CS <= '0' when nIO_RQ = '0' and CPU_A(7 downto 0) = x"E4" else '1';
-- Write to ports
process(CLK)
begin
if rising_edge(CLK) then
if nRESET = '0' then
ROM_INIT <= '1';
-- Port #F0 PK-02 Reset
RAM_PAGE0 <= '0';
RAM_PAGE1 <= '0';
nROM_EN <= '0';
HI_RES <= '0';
BLANK_SCR <= '0';
INT_EN <= '0';
RAM_BANK0 <= '0';
RAM_BANK1 <= '0';
elsif TICK = "1011" then
if nIO_RQ = '0' and nCPU_WR = '0' then
ROM_INIT <= '0';
if CPU_A(5 downto 4) = "11" then -- Port #F0 PK-02
RAM_PAGE0 <= CPU_DO(0);
RAM_PAGE1 <= CPU_DO(1);
nROM_EN <= CPU_DO(2);
HI_RES <= CPU_DO(3);
BLANK_SCR <= CPU_DO(4);
INT_EN <= CPU_DO(5);
RAM_BANK0 <= CPU_DO(6);
RAM_BANK1 <= CPU_DO(7);
elsif nFDC_CS = '0' then -- Port #E4 FDC
VG93_nCLR <= CPU_DO(2);
VG93_nDDEN <= CPU_DO(6);
VG93_HRDY <= CPU_DO(3);
FDC_DRIVE <= CPU_DO(1 downto 0);
FDC_nSIDE <= CPU_DO(4);
end if;
end if;
end if;
end if;
end process;
-- PK-02 Interupts and AY CLC
-- Input 38.5 Mhz Output 49 Hz
-- 20 bit counter used, pulse width 10 us
process (CLK)
begin
if rising_edge(CLK) then
int_cnt <= int_cnt + 1;
clc_cnt <= clc_cnt + 1;
-- AY CLC 1.77 MHz (Actial 1.8MHz)
CLC <= '0';
if clc_cnt = 17 then
clc_cnt <= "00000";
CLC <= '1';
end if;
if int_cnt = 325 then
int_cnt <= int_cnt + 1;
nINT <= '1';
end if;
if int_cnt = 663260 then
int_cnt <= (others => '0');
if INT_EN = '1' then
nINT <= '0';
end if;
end if;
end if;
end process;
-- PK-02 RAM Page Switching
RAM_A <= RAM_BANK1 & RAM_BANK0 & RAM_PAGE1 & RAM_PAGE0 & CPU_A(13 downto 0) when CPU_A(15 downto 14) = "11" else
"11" & CPU_A(15 downto 0);
-- PK-02 AY8910 Port
nAY_CS <= '0' when nIO_RQ = '0' and nM1 = '1' and CPU_A(15) = '1' and CPU_A(1) = '0' else '1';
AUDIO_L <= std_logic_vector( unsigned('0' & AY_A & '0') + unsigned('0' & ( (BEEPER and BEEPER_EN) xor MIPS_BEEPER ) & AY_B) );
AUDIO_R <= std_logic_vector( unsigned('0' & AY_C & '0') + unsigned('0' & ( (BEEPER and BEEPER_EN) xor MIPS_BEEPER ) & AY_B) );
end Behavioral;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_STD
|
Extras/VHDL/STD_06500_bad.vhd
|
1
|
3430
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-09 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06500_bad.vhd
-- File Creation date : 2015-04-09
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Counters end of counting: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_06500_bad is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(3 downto 0); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end STD_06500_bad;
--CODE
architecture Behavioral of STD_06500_bad is
signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
signal Count_Length : unsigned(3 downto 0); -- Length input signal (unsigned converted)
begin
Count_Length <= unsigned(i_Length);
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count = Count_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable = '1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
--CODE
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/a8core/cpu.vhd
|
1
|
3885
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
ENTITY cpu IS
PORT
(
CLK,RESET,ENABLE : IN STD_logic;
DI : IN std_logic_vector(7 downto 0);
IRQ_n : in std_logic;
NMI_n : in std_logic;
MEMORY_READY : in std_logic;
THROTTLE : in std_logic;
RDY : in std_logic;
DO : OUT std_logic_vector(7 downto 0);
A : OUT std_logic_vector(15 downto 0);
R_W_n : OUT std_logic;
CPU_FETCH : out std_logic
);
END cpu;
architecture vhdl of cpu is
component cpu_65xx is
generic (
pipelineOpcode : boolean;
pipelineAluMux : boolean;
pipelineAluOut : boolean
);
port (
clk : in std_logic;
enable : in std_logic;
halt : in std_logic := '0';
reset : in std_logic;
nmi_n : in std_logic := '1';
irq_n : in std_logic := '1';
so_n : in std_logic := '1';
d : in unsigned(7 downto 0);
q : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
we : out std_logic;
debugOpcode : out unsigned(7 downto 0);
debugPc : out unsigned(15 downto 0);
debugA : out unsigned(7 downto 0);
debugX : out unsigned(7 downto 0);
debugY : out unsigned(7 downto 0);
debugS : out unsigned(7 downto 0);
debug_flags : out unsigned(7 downto 0)
);
end component;
signal CPU_ENABLE: std_logic; -- Apply Antic HALT and throttle
-- Support for Peter's core (NMI patch applied)
signal debugOpcode : unsigned(7 downto 0);
signal debugPc : unsigned(15 downto 0);
signal debugA : unsigned(7 downto 0);
signal debugX : unsigned(7 downto 0);
signal debugY : unsigned(7 downto 0);
signal debugS : unsigned(7 downto 0);
signal di_unsigned : unsigned(7 downto 0);
signal do_unsigned : unsigned(7 downto 0);
signal addr_unsigned : unsigned(15 downto 0);
signal CPU_ENABLE_RDY : std_logic; -- it has not RDY line
signal WE : std_logic;
signal nmi_pending_next : std_logic; -- NMI during RDY
signal nmi_pending_reg : std_logic;
signal nmi_n_adjusted : std_logic;
signal nmi_n_reg : std_logic;
signal nmi_edge : std_logic;
signal CPU_ENABLE_RESET : std_logic;
signal not_rdy : std_logic;
BEGIN
CPU_ENABLE <= ENABLE and memory_ready and THROTTLE;
-- CPU designed by Peter W - as used in Chameleon
di_unsigned <= unsigned(di);
cpu_6502_peter:cpu_65xx
generic map
(
pipelineOpcode => false,
pipelineAluMux => false,
pipelineAluOut => false
)
port map (
clk => clk,
enable => CPU_ENABLE_RDY,
halt => '0',
reset=>reset,
nmi_n=>nmi_n_adjusted,
irq_n=>irq_n,
d=>di_unsigned,
q=>do_unsigned,
addr=>addr_unsigned,
WE=>WE,
debugOpcode => debugOpcode,
debugPc => debugPc,
debugA => debugA,
debugX => debugX,
debugY => debugY,
debugS => debugS
);
CPU_ENABLE_RDY <= (CPU_ENABLE and (rdy or we)) or reset;
CPU_ENABLE_RESET <= CPU_ENABLE or reset;
not_rdy <= not(rdy);
nmi_edge <= not(nmi_n) and nmi_n_reg;
nmi_pending_next <= (nmi_edge and not(rdy or we)) or (nmi_pending_reg and not(rdy)) or (nmi_pending_reg and rdy and not(cpu_enable));
nmi_n_adjusted <= not(nmi_pending_reg) and nmi_n;
-- register
process(clk,reset)
begin
if (RESET = '1') then
nmi_pending_reg <= '0';
nmi_n_reg <= '1';
elsif (clk'event and clk='1') then
nmi_pending_reg <= nmi_pending_next;
nmi_n_reg <= nmi_n;
end if;
end process;
-- outputs
r_w_n <= not(we);
do <= std_logic_vector(do_unsigned);
a <= std_logic_vector(addr_unsigned);
CPU_FETCH <= ENABLE and THROTTLE;
END vhdl;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/lvov-pk02-mips/src/host/VGA Console/mips_vram/mips_vram/example_design/mips_vram_exdes.vhd
|
1
|
5405
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: mips_vram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY mips_vram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END mips_vram_exdes;
ARCHITECTURE xilinx OF mips_vram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT mips_vram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : mips_vram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/lvov-pk02-mips/src/host/plasma v3.0/uart.vhd
|
1
|
6245
|
---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(8 downto 0);
signal busy_write_sig : std_logic;
signal read_value_reg : std_logic_vector(7 downto 0);
signal uart_read2 : std_logic;
begin
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg, read_value_reg, uart_read2)
constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
"0110110010"; --25MHz/57600Hz = 0x1b2
-- "0000000100"; --for debug (shorten read_value_reg)
begin
uart_read2 <= read_value_reg(read_value_reg'length - 1);
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
read_value_reg <= ONES(7 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(8 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
if delay_write_reg /= COUNT_VALUE then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Average uart_read signal
if uart_read = '1' then
if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg + 1;
end if;
else
if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg - 1;
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read2 = '0' then --wait for start bit
delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
delay_read_reg <= COUNT_VALUE; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
data_save_reg <= '1' & data_read_reg;
elsif enable_read = '1' then
data_save_reg(8) <= '0'; --data_available
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000" and log_file = "UNUSED" then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line had to be commented out for synthesis
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; --uart_sel
end if; --rising_edge(clk)
end process; --uart_proc
end generate; --uart_logger
end; --architecture logic
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/lvov-pk02-mips/src/host/plasma v3.0/mlite_pack.vhd
|
1
|
19674
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_add_sub
GENERIC (
lpm_width : NATURAL;
lpm_direction : STRING := "UNUSED";
lpm_type : STRING;
lpm_hint : STRING);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
add_sub : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0));
END COMPONENT;
-- For Altera
COMPONENT lpm_ram_dp
GENERIC (
lpm_width : NATURAL;
lpm_widthad : NATURAL;
rden_used : STRING;
intended_device_family : STRING;
lpm_indata : STRING;
lpm_wraddress_control : STRING;
lpm_rdaddress_control : STRING;
lpm_outdata : STRING;
use_eab : STRING;
lpm_type : STRING);
PORT (
wren : IN STD_LOGIC ;
wrclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component ramb4_s16_s16
port (
clka : in std_logic;
rsta : in std_logic;
addra : in std_logic_vector;
dia : in std_logic_vector;
ena : in std_logic;
wea : in std_logic;
doa : out std_logic_vector;
clkb : in std_logic;
rstb : in std_logic;
addrb : in std_logic_vector;
dib : in std_logic_vector;
enb : in std_logic;
web : in std_logic);
end component;
-- For Xilinx
component reg_file_dp_ram
port (
addra : IN std_logic_VECTOR(4 downto 0);
addrb : IN std_logic_VECTOR(4 downto 0);
clka : IN std_logic;
clkb : IN std_logic;
dinb : IN std_logic_VECTOR(31 downto 0);
douta : OUT std_logic_VECTOR(31 downto 0);
web : IN std_logic);
end component;
-- For Xilinx
component reg_file_dp_ram_xc4000xla
port (
A : IN std_logic_vector(4 DOWNTO 0);
DI : IN std_logic_vector(31 DOWNTO 0);
WR_EN : IN std_logic;
WR_CLK : IN std_logic;
DPRA : IN std_logic_vector(4 DOWNTO 0);
SPO : OUT std_logic_vector(31 DOWNTO 0);
DPO : OUT std_logic_vector(31 DOWNTO 0));
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
mem_address : out std_logic_vector(31 downto 2);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 3); --3 or 4
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
mem_address : out std_logic_vector(31 downto 0);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0);
mem_pause : in std_logic);
end component;
component ram
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
write_byte_enable : out std_logic_vector(3 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
gpl-3.0
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.