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dummylink/plnk_fpga-stack
Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/OpenHUB.vhd
5
6692
------------------------------------------------------------------------------------------------------------------------ -- OpenHUB -- -- Copyright (C) 2009 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Note: RxDv, RxDat0 and RxDat1 have to be synchron to CLK -- ReceivePort return currently active Port -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2009-08-07 V0.01 Converted from V3.1 to first official version. -- 2011-11-28 V0.02 zelenkaj Changed reset level to high-active ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_unsigned.ALL; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ENTITY OpenHUB IS GENERIC ( Ports : integer := 3 ); PORT ( Rst : IN std_logic; Clk : IN std_logic; RxDv : IN std_logic_vector(Ports DOWNTO 1); RxDat0, RxDat1 : IN std_logic_vector(Ports DOWNTO 1); TxEn : OUT std_logic_vector(Ports DOWNTO 1); TxDat0, TxDat1 : OUT std_logic_vector(Ports DOWNTO 1); internPort : IN integer RANGE 1 TO Ports := 1; TransmitMask : IN std_logic_vector(Ports DOWNTO 1) := (OTHERS => '1'); ReceivePort : OUT integer RANGE 0 TO Ports ); END ENTITY OpenHUB; ARCHITECTURE struct OF OpenHUB IS SIGNAL RxDvI, RxDvL : std_logic_vector(Ports DOWNTO 0); SIGNAL RxDatI0, RxDatL0 : std_logic_vector(Ports DOWNTO 0); SIGNAL RxDatI1, RxDatL1 : std_logic_vector(Ports DOWNTO 0); SIGNAL TxEnI : std_logic_vector(Ports DOWNTO 0); SIGNAL TxDatI0 : std_logic_vector(Ports DOWNTO 0); SIGNAL TxDatI1 : std_logic_vector(Ports DOWNTO 0); SIGNAL MasterAtCollNumber : integer RANGE 0 TO Ports; SIGNAL HubActive : boolean; SIGNAL CollStatus : boolean; SIGNAL TransmitMask_L : std_logic_vector(Ports DOWNTO 1); BEGIN RxDvI(Ports DOWNTO 0) <= RxDv(Ports DOWNTO 1) & '0'; RxDatI0(Ports DOWNTO 0) <= RxDat0(Ports DOWNTO 1) & '0'; RxDatI1(Ports DOWNTO 0) <= RxDat1(Ports DOWNTO 1) & '0'; TxEn(Ports DOWNTO 1) <= TxEnI(Ports DOWNTO 1); TxDat0(Ports DOWNTO 1) <= TxDatI0(Ports DOWNTO 1); TxDat1(Ports DOWNTO 1) <= TxDatI1(Ports DOWNTO 1); do: PROCESS (Rst, Clk) VARIABLE Active : boolean; VARIABLE Master : integer RANGE 0 TO Ports; VARIABLE Master_at_Coll : integer RANGE 0 TO Ports; VARIABLE Coll : boolean; VARIABLE RxDvM : std_logic_vector(Ports DOWNTO 0); BEGIN IF Rst = '1' THEN RxDvL <= (OTHERS => '0'); RxDatL0 <= (OTHERS => '0'); RxDatL1 <= (OTHERS => '0'); TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0'); Active := false; Master := 0; Master_at_Coll := 0; Coll := false; TransmitMask_L <= (OTHERS => '1'); ELSIF rising_edge(Clk) THEN RxDvL <= RxDvI; RxDatL0 <= RxDatI0; RxDatL1 <= RxDatI1; IF Active = false THEN IF RxDvL /= 0 THEN FOR i IN 1 TO Ports LOOP IF RxDvL(i) = '1' AND (RxDatL0(i) = '1' OR RxDatL1(i) = '1') THEN Master := i; Active := true; EXIT; END IF; END LOOP; END IF; ELSE IF RxDvL(Master) = '0' AND RxDvI(Master) = '0' THEN Master := 0; END IF; IF RxDvL = 0 AND RxDvI = 0 THEN Active := false; END IF; END IF; IF Master = 0 THEN TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0'); -- Overtake new TransmitMask only, when there is no active frame. TransmitMask_L <= TransmitMask; ELSE FOR i IN 1 TO Ports LOOP -- output received frame to every port IF i /= Master THEN -- but not to the port where it is coming from - "eh kloar!" -- only send data to active ports (=> TransmitMask is set to '1') or the internal Port (Mac) IF TransmitMask_L(i) = '1' OR Master = internPort THEN TxEnI(i) <= '1'; TxDatI0(i) <= RxDatL0(Master); TxDatI1(i) <= RxDatL1(Master); END IF; -- If there is a frame received and another is sent => collision! IF RxDvL(i) = '1' THEN Coll := true; Master_at_Coll := Master; END IF; END IF; END LOOP; END IF; IF Coll = true THEN TxEnI(Master_at_Coll) <= '1'; TxDatI0(Master_at_Coll) <= '1'; TxDatI1(Master_at_Coll) <= '0'; RxDvM := RxDvL; RxDvM(Master_at_Coll) := '0'; IF RxDvM = 0 THEN TxEnI(Master_at_Coll) <= '0'; TxDatI0(Master_at_Coll) <= '0'; TxDatI1(Master_at_Coll) <= '0'; Coll := false; Master_at_Coll := 0; END IF; END IF; END IF; HubActive <= Active; MasterAtCollNumber <= Master_at_Coll; CollStatus <= Coll; -- Output the Master Port - identifies the port (1...n) which has received the packet. -- If Master is 0, the Hub is inactive. ReceivePort <= Master; END PROCESS do; END struct;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/pdi_tripleVBufLogic.vhd
5
12460
------------------------------------------------------------------------------------------------------------------------ -- Triple Buffer Control Logic -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2010-08-16 V0.01 zelenkaj First version -- 2010-10-11 V0.02 zelenkaj Bugfix: PCP can't be producer in any case => added generic -- 2010-10-25 V0.03 zelenkaj Use one Address Adder per DPR port side (reduces LE usage) -- 2011-04-26 V0.04 zelenkaj generic for clock domain selection -- 2011-12-13 V0.05 zelenkaj Added constants for one hot code -- Reduced clkXing to two signals (one hot -> bin -> one hot) ------------------------------------------------------------------------------------------------------------------------ -- This logic implements the virtual triple buffers, by selecting the appropriate address offset -- The output address offset has to be added to the input address. -- The trigger signal switches to the next available buffer. The switch mechanism is implemented in the -- PCP's clock domain. Thus the switch over on the PCP side is performed without delay. An AP switch over crosses -- from AP to PCP clock domain (2x pcpClk) and back from PCP to AP (2x apClk). ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY tripleVBufLogic IS GENERIC( genOnePdiClkDomain_g : boolean := false; --base address of virtual buffers in DPR iVirtualBufferBase_g : INTEGER := 0; --size of one virtual buffer in DPR (must be aligned!!!) iVirtualBufferSize_g : INTEGER := 1024; --out address width iOutAddrWidth_g : INTEGER := 13; --in address width iInAddrWidth_g : INTEGER := 11; --ap is producer bApIsProducer : BOOLEAN := FALSE ); PORT ( pcpClk : IN STD_LOGIC; pcpReset : IN STD_LOGIC; pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change --pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0); pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded) apClk : IN STD_LOGIC; apReset : IN STD_LOGIC; apTrigger : IN STD_LOGIC; --trigger virtual buffer change --apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0); apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded) ); END ENTITY tripleVBufLogic; ARCHITECTURE rtl OF tripleVBufLogic IS --constants ---virtual buffer base address CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g; CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g; CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g; ---one hot code constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001"; constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010"; constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100"; ---triple buffer mechanism ----initial states CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0; CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1; CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2; --signals ---PCP and AP selected virtual buffer SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain BEGIN pcpOutSelVBuf <= pcpSelVBuf_s; apOutSelVBuf <= apSelVBuf_s; theAddrCalcer : BLOCK --depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr) -- ???SelVBuf_s | ???OutAddr -- ------------------------- -- "001" | ???InAddr + iVirtualBufferBase0_c -- "010" | ???InAddr + iVirtualBufferBase1_c -- "100" | ???InAddr + iVirtualBufferBase2_c SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); --SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); BEGIN --select address offset pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE (OTHERS => '0'); pcpOutAddrOff <= pcpAddrOffset; --calculate address for dpr, leading zero is a sign! --pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset); --pcpOutAddr <= pcpSum(pcpOutAddr'RANGE); --select address offset apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE (OTHERS => '0'); apOutAddrOff <= apAddrOffset; --calculate address for dpr, leading zero is a sign! --apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset); --apOutAddr <= apSum(apOutAddr'RANGE); END BLOCK theAddrCalcer; theLockSync : block constant cBinLockWidth : integer := 2; constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01"; constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11"; constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10"; signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0); signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0); begin --conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be -- synchronized from PCP clock- to AP clock domain! --In addition the one hot approach is transformed to save one line binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else cBinLock2; apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else cOneHotVirtualBuffer2; vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE theLockedSync : ENTITY work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) PORT MAP ( din => binLockedVBuf(i), dout => binApSelVBuf(i), clk => apClk, rst => apReset ); END GENERATE; end block; theTripleBufferLogic : BLOCK --The PCP triggers with triggerA and sets buffers to valid. --The AP triggers with triggerB and locks buffers for reading. SIGNAL clk, rst : STD_LOGIC; SIGNAL triggerA : STD_LOGIC; SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain! SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP -- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN --triple buffer logic is implemented in PCP clock domain! clk <= pcpClk; rst <= pcpReset; --triggerA is the producer's trigger triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s; --conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses! ---thus a toggling signal crosses the clock domain genToggleB : PROCESS(apClk, apReset) BEGIN IF apReset = '1' THEN toggleB <= '0'; ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used! IF apTrigger = '1' THEN toggleB <= not toggleB; END IF; END IF; END PROCESS genToggleB; theToggleSync : ENTITY work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) PORT MAP ( din => toggleB, dout => toggleBsync, clk => clk, rst => rst ); toggleShiftReg: PROCESS(clk, rst) BEGIN IF rst = '1' THEN toggleEdge <= (OTHERS => '0'); ELSIF clk = '1' AND clk'event THEN --shift register toggleEdge <= toggleEdge(0) & toggleBsync; END IF; END PROCESS toggleShiftReg; triggerB_s <= toggleEdge(1) xor toggleEdge(0); --triggerB is the consumer's trigger triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger; --currentA is set by PCP (currently used buffer by PCP) pcpSelVBuf_s <= currentA when bApIsProducer = false else locked; --locked virtual buffer in PCP clock domain lockedVBuf_s <= locked when bApIsProducer = false else currentA; tripleBufMechanism : PROCESS(clk, rst) VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN IF rst = '1' THEN --initial state: ---buffer "001" is valid valid_v := initialValid_c; ---buffer "010" is locked locked <= initialLocked_c; ---buffer "100" is currently used by PCP currentA <= initialCurrent_c; ELSIF clk = '1' AND clk'EVENT THEN IF triggerA = '1' THEN --PCP triggers buffer change ---set valid to current selected buffer ---search for free buffer (not locked and valid) valid_v := currentA; --free buffer search ex.: -- locked "001" -- valid "010" -- ============ -- free "100" currentA <= not locked and not valid_v; END IF; IF triggerB = '1' THEN --AP triggers buffer change ---change AP to valid buffer locked <= valid_v; END IF; END IF; END PROCESS tripleBufMechanism; END BLOCK theTripleBufferLogic; END ARCHITECTURE rtl;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/altera_nios2/EBV_DBC3C40/design_nios2_directIO/POWERLINK/src/OpenMAC.vhd
5
49609
------------------------------------------------------------------------------------------------------------------------ -- OpenMAC -- -- Copyright (C) 2009 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files: -- OpenMAC_DPR_Altera.vhd -- OpenMAC_DPR_Xilinx.vhd -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- V0.00-0.30 First generation. -- 2009-08-07 V0.31 Converted to official version. -- 2010-04-12 V0.40 zelenkaj Added Auto-Response Delay functionality (TxDel) -- 2010-06-28 V0.41 zelenkaj Bug Fix: exit sDel if Tx_Off, set Tx_Del_Run without Ipg consideration -- 2010-08-02 V0.42 zelenkaj Added Timer triggered TX functionality (TxSyncOn) -- 2011-01-25 V0.43 zelenkaj Changed IPG preload value from 900ns to 960ns -- 2011-11-28 V0.44 zelenkaj Changed reset level to high-active -- Clean up -- Added Dma qualifiers (Rd/Wr done) -- 2011-12-02 V0.45 zelenkaj Added Dma Request Overflow -- 2011-12-05 V0.46 zelenkaj Minor change of constants (logic level) -- 2011-12-23 V0.47 zelenkaj Improvement of Dma Request Overflow determination ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY OpenMAC IS GENERIC( HighAdr : IN integer := 16; Timer : IN boolean := false; TxSyncOn : IN boolean := false; TxDel : IN boolean := false; Simulate : IN boolean := false ); PORT ( Rst, Clk : IN std_logic; -- Processor s_nWr, Sel_Ram, Sel_Cont : IN std_logic := '0'; S_nBe : IN std_logic_vector( 1 DOWNTO 0); S_Adr : IN std_logic_vector(10 DOWNTO 1); S_Din : IN std_logic_vector(15 DOWNTO 0); S_Dout : OUT std_logic_vector(15 DOWNTO 0); nTx_Int, nRx_Int : OUT std_logic; nTx_BegInt : OUT std_logic; -- DMA Dma_Rd_Done : OUT std_logic; Dma_Wr_Done : OUT std_logic; Dma_Req, Dma_Rw : OUT std_logic; Dma_Ack : IN std_logic; Dma_Req_Overflow : OUT std_logic; Dma_Addr : OUT std_logic_vector(HighAdr DOWNTO 1); Dma_Dout : OUT std_logic_vector(15 DOWNTO 0); Dma_Din : IN std_logic_vector(15 DOWNTO 0); -- RMII rRx_Dat : IN std_logic_vector( 1 DOWNTO 0); rCrs_Dv : IN std_logic; rTx_Dat : OUT std_logic_vector( 1 DOWNTO 0); rTx_En : OUT std_logic; Hub_Rx : IN std_logic_vector( 1 DOWNTO 0) := "00"; Mac_Zeit : OUT std_logic_vector(31 DOWNTO 0) ); END ENTITY OpenMAC; ARCHITECTURE struct OF OpenMAC IS CONSTANT cInactivated : std_logic := '0'; CONSTANT cActivated : std_logic := '1'; SIGNAL Rx_Dv : std_logic; SIGNAL R_Req : std_logic; SIGNAL Auto_Desc : std_logic_vector( 3 DOWNTO 0); SIGNAL Zeit : std_logic_vector(31 DOWNTO 0); SIGNAL Tx_Dma_Req, Rx_Dma_Req : std_logic; SIGNAL Tx_Dma_Ack, Rx_Dma_Ack : std_logic; SIGNAL Tx_Dma_Req_Overflow : std_logic; SIGNAL Rx_Dma_Req_Overflow : std_logic; SIGNAL Tx_Ram_Dat, Rx_Ram_Dat : std_logic_vector(15 DOWNTO 0); SIGNAL Tx_Reg, Rx_Reg : std_logic_vector(15 DOWNTO 0); SIGNAL Dma_Tx_Addr, Dma_Rx_Addr : std_logic_vector(Dma_Addr'RANGE); SIGNAL Tx_Col : std_logic; SIGNAL Sel_Tx_Ram, Sel_Tx_Reg : std_logic; SIGNAL Tx_LatchH, Tx_LatchL : std_logic_vector( 7 DOWNTO 0); BEGIN S_Dout <= Tx_Ram_Dat WHEN Sel_Ram = '1' AND Sel_Tx_Ram = '1' ELSE Rx_Ram_Dat WHEN Sel_Ram = '1' ELSE Tx_Reg WHEN Sel_Cont = '1' AND Sel_Tx_Reg = '1' ELSE Rx_Reg; Mac_Zeit <= Zeit; Dma_Req_Overflow <= Tx_Dma_Req_Overflow or Rx_Dma_Req_Overflow; b_Dma: BLOCK SIGNAL Rx_Dma, Tx_Dma : std_logic; BEGIN Dma_Req <= '1' WHEN (Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Rx_Dma_Req = '1' ELSE '0'; Dma_Rw <= '1' WHEN (Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Tx_Dma = '1' ELSE '0'; Dma_Addr <= Dma_Tx_Addr WHEN (Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Tx_Dma = '1' ELSE Dma_Rx_Addr; Rx_Dma_Ack <= '1' WHEN Rx_Dma = '1' AND Dma_Ack = '1' ELSE '0'; pDmaArb: PROCESS( Clk, Rst ) IS BEGIN IF Rst = '1' THEN Rx_Dma <= '0'; Tx_Dma <= '0'; Tx_Dma_Ack <= '0'; Tx_LatchH <= (OTHERS => '0'); Tx_LatchL <= (OTHERS => '0'); Zeit <= (OTHERS => '0'); ELSIF rising_edge( Clk ) THEN IF Timer THEN Zeit <= Zeit + 1; END IF; Sel_Tx_Ram <= s_Adr(8); Sel_Tx_Reg <= NOT s_Adr(3); IF Dma_Ack = '0' THEN IF Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0' THEN Tx_Dma <= '1'; ELSIF Tx_Dma = '0' AND Rx_Dma_Req = '1' THEN Rx_Dma <= '1'; END IF; ELSE IF Rx_Dma = '1' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0' THEN Tx_Dma <= '1'; Rx_Dma <= '0'; ELSIF Tx_Dma = '1' AND Rx_Dma_Req = '1' THEN Tx_Dma <= '0'; Rx_Dma <= '1'; ELSE Tx_Dma <= '0'; Rx_Dma <= '0'; END IF; END IF; IF Tx_Dma = '1' AND Dma_Ack = '1' THEN Tx_Dma_Ack <= '1'; ELSE Tx_Dma_Ack <= '0'; END IF; IF Tx_Dma_Ack = '1' THEN Tx_LatchH <= Dma_Din(15 DOWNTO 8); Tx_LatchL <= Dma_Din( 7 DOWNTO 0); END IF; END IF; END PROCESS pDmaArb; END BLOCK b_Dma; b_Full_Tx: BLOCK TYPE MACTX_TYPE IS ( R_Idl, R_Bop, R_Pre, R_Txd, R_Crc, R_Col, R_Jam ); SIGNAL Sm_Tx : MACTX_TYPE; SIGNAL Start_Tx, ClrCol, Tx_On : std_logic; SIGNAL Dibl_Cnt : std_logic_vector( 1 DOWNTO 0); SIGNAL F_End, Was_Col, Block_Col : std_logic; SIGNAL Ipg_Cnt, Tx_Timer : std_logic_vector( 7 DOWNTO 0); ALIAS Ipg : std_logic IS Ipg_Cnt(7); ALIAS Tx_Time : std_logic IS Tx_Timer(7); SIGNAL Tx_Ipg : std_logic_vector( 5 DOWNTO 0); SIGNAL Tx_Count : std_logic_vector(11 DOWNTO 0); SIGNAL Tx_En, F_Val, Tx_Half : std_logic; SIGNAL Tx_Sr, F_TxB : std_logic_vector( 7 DOWNTO 0); SIGNAL Crc : std_logic_vector(31 DOWNTO 0); SIGNAL CrcDin, Tx_Dat : std_logic_vector( 1 DOWNTO 0); SIGNAL Col_Cnt : std_logic_vector( 3 DOWNTO 0); SIGNAL Auto_Coll : std_logic; SIGNAL Rnd_Num : std_logic_vector( 9 DOWNTO 0); SIGNAL Retry_Cnt : std_logic_vector( 9 DOWNTO 0); SIGNAL Max_Retry : std_logic_vector( 3 DOWNTO 0); BEGIN rTx_En <= Tx_En; rTx_Dat <= Tx_Dat; pTxSm: PROCESS ( Clk, Rst ) IS BEGIN IF Rst = '1' THEN Sm_Tx <= R_Idl; ELSIF rising_edge( Clk ) THEN IF Sm_Tx = R_Idl OR Sm_Tx = R_Bop OR Dibl_Cnt = "11" THEN CASE Sm_Tx IS WHEN R_Idl => IF Start_Tx = '1' AND (Tx_Half = '0' OR Rx_Dv = '0') AND Ipg = '0' THEN Sm_Tx <= R_Bop; END IF; WHEN R_Bop => Sm_Tx <= R_Pre; WHEN R_Pre => IF Tx_Time = '1' THEN Sm_Tx <= R_Txd; END IF; WHEN R_Txd => IF Was_Col = '1' THEN Sm_Tx <= R_Col; ELSIF Tx_Count = 0 THEN Sm_Tx <= R_Crc; END IF; WHEN R_Col => Sm_Tx <= R_Jam; WHEN R_Jam => IF Tx_Time = '1' THEN Sm_Tx <= R_Idl; END IF; WHEN R_Crc => IF Was_Col = '1' THEN Sm_Tx <= R_Col; ELSIF Tx_Time = '1' THEN Sm_Tx <= R_Idl; END IF; WHEN OTHERS => NULL; END CASE; END IF; END IF; END PROCESS pTxSm; pTxCtl: PROCESS ( Clk, Rst ) IS VARIABLE Preload : std_logic_vector(Tx_Timer'RANGE); VARIABLE Load : std_logic; BEGIN IF Rst = '1' THEN Tx_Dat <= "00"; Tx_En <= '0'; Dibl_Cnt <= "00"; F_End <= '0'; F_Val <= '0'; Tx_Col <= '0'; Was_Col <= '0'; Block_Col <= '0'; Ipg_Cnt <= (OTHERS => '0'); Tx_Timer <= (OTHERS => '0'); Tx_Sr <= (OTHERS => '0'); ELSIF rising_edge( Clk ) THEN IF Sm_Tx = R_Bop THEN Dibl_Cnt <= "00"; ELSE Dibl_Cnt <= Dibl_Cnt + 1; END IF; IF Tx_En = '1' THEN Ipg_Cnt <= "1" & conv_std_logic_vector( 44, 7); ELSIF Rx_Dv = '1' AND Tx_Half = '1' THEN Ipg_Cnt <= "10" & Tx_Ipg; ELSIF Ipg = '1' THEN Ipg_Cnt <= Ipg_Cnt - 1; END IF; IF Dibl_Cnt = "11" AND Sm_Tx = R_Crc AND Tx_Time = '1' THEN F_End <= '1'; ELSIF Dibl_Cnt = "11" AND Sm_Tx = R_Col THEN IF Col_Cnt = (Max_Retry - 1) THEN F_End <= '1'; ELSIF Col_Cnt < x"E" THEN Tx_Col <= '1'; ELSE F_End <= '1'; END IF; ELSE F_End <= '0'; Tx_Col <= '0'; END IF; IF Tx_Half = '1' AND Rx_Dv = '1' AND (Sm_Tx = R_Pre OR Sm_Tx = R_Txd) THEN Was_Col <= '1'; ELSIF Sm_Tx = R_Col THEN Was_Col <= '0'; END IF; IF Sm_Tx = R_Col THEN Block_Col <= '1'; ELSIF Auto_Coll = '1' THEN Block_Col <= '0'; ELSIF Retry_Cnt = 0 THEN Block_Col <= '0'; END IF; IF Dibl_Cnt = "10" AND Sm_Tx = R_Pre AND Tx_Time = '1' THEN F_Val <= '1'; ELSIF Dibl_Cnt = "10" AND Sm_Tx = R_Txd THEN F_Val <= '1'; ELSE F_Val <= '0'; END IF; Load := '0'; IF Sm_Tx = R_Bop THEN Preload := x"06"; Load := '1'; ELSIF Sm_Tx = R_Txd THEN Preload := x"02"; Load := '1'; ELSIF Sm_Tx = R_Col THEN Preload := x"01"; Load := '1'; ELSIF Tx_Time = '1' THEN Preload := x"3e"; Load := '1'; END IF; IF Dibl_Cnt = "11" OR Sm_Tx = R_Bop THEN IF Load = '1' THEN Tx_Timer <= Preload; ELSE Tx_Timer <= Tx_Timer - 1; END IF; END IF; IF F_Val = '1' THEN Tx_Sr <= F_TxB; ELSE Tx_Sr <= "00" & Tx_Sr(7 DOWNTO 2); END IF; IF Sm_Tx = R_Pre THEN Tx_En <= '1'; ELSIF Sm_Tx = R_Idl OR (Sm_Tx = R_Jam AND Tx_Time = '1') THEN Tx_En <= '0'; END IF; IF Sm_Tx = R_Pre AND Tx_Time = '1' AND Dibl_Cnt = "11" THEN Tx_Dat <= "11"; ELSIF Sm_Tx = R_Pre THEN Tx_Dat <= "01"; ELSIF Sm_Tx = R_Txd THEN Tx_Dat <= CrcDin; ELSIF Sm_Tx = R_Crc THEN Tx_Dat <= NOT Crc(30) & NOT Crc(31); ELSIF Sm_Tx = R_Col OR Sm_Tx = R_Jam THEN Tx_Dat <= "11"; ELSE Tx_Dat <= "00"; END IF; END IF; END PROCESS pTxCtl; pBackDel: PROCESS ( Clk, Rst ) IS BEGIN IF Rst = '1' THEN Rnd_Num <= (OTHERS => '0'); Col_Cnt <= (OTHERS => '0'); Retry_Cnt <= (OTHERS => '0'); ELSIF rising_edge( Clk ) THEN Rnd_Num <= Rnd_Num(8 DOWNTO 0) & (Rnd_Num(9) XOR NOT Rnd_Num(2)); IF ClrCol = '1' THEN Col_Cnt <= x"0"; ELSIF Dibl_Cnt = "11" AND Sm_Tx = R_Col THEN Col_Cnt <= Col_Cnt + 1; END IF; IF Dibl_Cnt = "11" THEN IF Tx_On = '0' OR Auto_Coll = '1' THEN Retry_Cnt <= (OTHERS => '0'); ELSIF Sm_Tx = R_Col THEN FOR i IN 0 TO 9 LOOP IF Col_Cnt >= i THEN Retry_Cnt(i) <= Rnd_Num(i); ELSE Retry_Cnt(i) <= '0'; END IF; END LOOP; ELSIF Sm_Tx /= R_Jam AND Tx_Time = '1' AND Retry_Cnt /= 0 THEN Retry_Cnt <= Retry_Cnt - 1; END IF; END IF; END IF; END PROCESS pBackDel; CrcDin <= Tx_Sr(1 DOWNTO 0); Calc: PROCESS ( Clk, Crc, CrcDin ) IS VARIABLE H : std_logic_vector(1 DOWNTO 0); BEGIN H(0) := Crc(31) XOR CrcDin(0); H(1) := Crc(30) XOR CrcDin(1); IF rising_edge( Clk ) THEN IF Sm_Tx = R_Pre THEN Crc <= x"FFFFFFFF"; ELSIF Sm_Tx = R_Crc THEN Crc <= Crc(29 DOWNTO 0) & "00"; ELSE Crc( 0) <= H(1); Crc( 1) <= H(0) XOR H(1); Crc( 2) <= Crc( 0) XOR H(0) XOR H(1); Crc( 3) <= Crc( 1) XOR H(0) ; Crc( 4) <= Crc( 2) XOR H(1); Crc( 5) <= Crc( 3) XOR H(0) XOR H(1); Crc( 6) <= Crc( 4) XOR H(0) ; Crc( 7) <= Crc( 5) XOR H(1); Crc( 8) <= Crc( 6) XOR H(0) XOR H(1); Crc( 9) <= Crc( 7) XOR H(0) ; Crc(10) <= Crc( 8) XOR H(1); Crc(11) <= Crc( 9) XOR H(0) XOR H(1); Crc(12) <= Crc(10) XOR H(0) XOR H(1); Crc(13) <= Crc(11) XOR H(0) ; Crc(14) <= Crc(12) ; Crc(15) <= Crc(13) ; Crc(16) <= Crc(14) XOR H(1); Crc(17) <= Crc(15) XOR H(0) ; Crc(18) <= Crc(16) ; Crc(19) <= Crc(17) ; Crc(20) <= Crc(18) ; Crc(21) <= Crc(19) ; Crc(22) <= Crc(20) XOR H(1); Crc(23) <= Crc(21) XOR H(0) XOR H(1); Crc(24) <= Crc(22) XOR H(0) ; Crc(25) <= Crc(23) ; Crc(26) <= Crc(24) XOR H(1); Crc(27) <= Crc(25) XOR H(0) ; Crc(28) <= Crc(26) ; Crc(29) <= Crc(27) ; Crc(30) <= Crc(28) ; Crc(31) <= Crc(29) ; END IF; END IF; END PROCESS Calc; bTxDesc: BLOCK TYPE sDESC IS (sIdle, sLen, sTimL, sTimH, sAdrH, sAdrL, sBegL, sBegH, sDel, sData, sStat, sColl ); SIGNAL Dsm, Tx_Dsm_Next : sDESC; SIGNAL DescRam_Out, DescRam_In : std_logic_vector(15 DOWNTO 0); ALIAS TX_LEN : std_logic_vector(11 DOWNTO 0) IS DescRam_Out(11 DOWNTO 0); ALIAS TX_OWN : std_logic IS DescRam_Out( 8); ALIAS TX_LAST : std_logic IS DescRam_Out( 9); ALIAS TX_READY : std_logic IS DescRam_Out(10); ALIAS TX_BEGDEL : std_logic IS DescRam_Out(12); ALIAS TX_BEGON : std_logic IS DescRam_Out(13); ALIAS TX_TIME : std_logic IS DescRam_Out(14); ALIAS TX_RETRY : std_logic_vector( 3 DOWNTO 0) IS DescRam_Out(3 DOWNTO 0); SIGNAL Ram_Be : std_logic_vector( 1 DOWNTO 0); SIGNAL Ram_Wr, Desc_We : std_logic; SIGNAL Desc_Addr : std_logic_vector( 7 DOWNTO 0); SIGNAL DescIdx : std_logic_vector( 2 DOWNTO 0); SIGNAL Last_Desc : std_logic; SIGNAL ZeitL : std_logic_vector(15 DOWNTO 0); SIGNAL Tx_Ie, Tx_Wait : std_logic; SIGNAL Tx_BegInt, Tx_BegSet, Tx_Early : std_logic; SIGNAL Tx_Del : std_logic; SIGNAL Ext_Tx, Ext_Ack : std_logic; SIGNAL Tx_Desc, Tx_Desc_One, Ext_Desc : std_logic_vector( 3 DOWNTO 0); SIGNAL Tx_Icnt : std_logic_vector( 4 DOWNTO 0); SIGNAL Tx_SoftInt : std_logic; SIGNAL Sel_TxH, Sel_TxL, H_Byte : std_logic; SIGNAL Tx_Buf : std_logic_vector( 7 DOWNTO 0); SIGNAL Tx_Idle, TxInt, Tx_Beg, Tx_Sync : std_logic; SIGNAL Tx_Ident : std_logic_vector( 1 DOWNTO 0); SIGNAL Tx_Cmp_High : std_logic_vector(15 downto 0); SIGNAL Start_TxS : std_logic; SIGNAL Tx_Dma_Out : std_logic; SIGNAL Tx_Del_Cnt : std_logic_vector(32 downto 0); ALIAS Tx_Del_End : std_logic is Tx_Del_Cnt(Tx_Del_Cnt'high); SIGNAL Tx_Del_Run : std_logic; signal Tx_Done : std_logic; BEGIN Dma_Rd_Done <= Tx_Done; Tx_Done <= '1' when Dsm = sStat or Dsm = sColl else '0'; --Read request overflows... -- * before preamble ends -- * during transfer before every 8th cycle (halfx) or 4th cycle (fullx) -- * after exiting crc state (data feteched by dma is not used since crc is calc in hw) Tx_Dma_Req_Overflow <= '1' when Dibl_Cnt = "01" and Sm_Tx = R_Pre and Tx_Timer(7) = '1' else '1' when Dibl_Cnt = "10" and Sm_Tx = R_Txd and H_Byte = '0' else '1' when Dibl_Cnt = "10" and Sm_Tx = R_Crc and Tx_Timer(7) = '1' else '0'; Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '1' ELSE '0'; Ram_Be(1) <= '1' WHEN s_nWr = '1' OR s_nBE(1) = '0' ELSE '0'; Ram_Be(0) <= '1' WHEN s_nWr = '1' OR s_nBE(0) = '0' ELSE '0'; DescIdx <= "000" WHEN Desc_We = '0' AND Tx_Dsm_Next = sIdle ELSE "000" WHEN Desc_We = '1' AND Dsm = sIdle ELSE "001" WHEN Desc_We = '0' AND Tx_Dsm_Next = sLen ELSE "001" WHEN Desc_We = '1' AND Dsm = sLen ELSE "010" WHEN Desc_We = '0' AND Tx_Dsm_Next = sAdrH ELSE "010" WHEN Desc_We = '1' AND Dsm = sAdrH ELSE "011" WHEN Desc_We = '0' AND Tx_Dsm_Next = sAdrL ELSE "011" WHEN Desc_We = '1' AND Dsm = sAdrL ELSE "100" WHEN Desc_We = '0' AND Tx_Dsm_Next = sBegH ELSE "100" WHEN Desc_We = '1' AND Dsm = sBegH ELSE "101" WHEN Desc_We = '0' AND Tx_Dsm_Next = sBegL ELSE "101" WHEN Desc_We = '1' AND Dsm = sBegL ELSE "110" WHEN Desc_We = '0' AND Tx_Dsm_Next = sTimH ELSE "110" WHEN Desc_We = '1' AND Dsm = sTimH ELSE "111" WHEN Desc_We = '0' AND Tx_Dsm_Next = sTimL ELSE "111" WHEN Desc_We = '1' AND Dsm = sTimL ELSE "111" WHEN Desc_We = '0' AND Tx_Dsm_Next = sData ELSE "111" WHEN Desc_We = '1' AND Dsm = sData ELSE "000"; Desc_We <= '1' WHEN Dsm = sTimL OR Dsm = sTimH OR Dsm = sStat ELSE '0'; Desc_Addr <= '1' & Tx_Desc & DescIdx WHEN Ext_Tx = '0' ELSE '1' & Ext_Desc & DescIdx; gTxTime: IF Timer GENERATE DescRam_In <= Zeit(31 DOWNTO 16) WHEN Dsm = sTimH ELSE ZeitL WHEN Dsm = sTimL ELSE x"000" & "01" & Tx_Ident WHEN Dsm = sBegL ELSE Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt; END GENERATE; gnTxTime: IF NOT Timer GENERATE DescRam_In <= x"000" & "01" & Tx_Ident WHEN Dsm = sBegL ELSE Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt; END GENERATE; RamH: ENTITY work.Dpr_16_16 GENERIC MAP(Simulate => Simulate) PORT MAP ( CLKA => Clk, CLKB => Clk, EnA => cActivated, Enb => cActivated, BEA => Ram_Be, WEA => Ram_Wr, WEB => Desc_We, ADDRA => s_Adr(8 DOWNTO 1), ADDRB => Desc_Addr, DIA => s_Din, DIB => DescRam_In, DOA => Tx_Ram_Dat, DOB => DescRam_Out ); ASSERT NOT( TxSyncOn AND NOT Timer ) REPORT "TxSyncOn needs Timer!" severity failure; pTxSm: PROCESS( Rst, Clk, Dsm, Tx_On, TX_OWN, Retry_Cnt, Ext_Tx, Tx_Wait, Tx_Sync, Sm_Tx, F_End, Tx_Col, Ext_Ack, Tx_Del, Tx_Beg ) BEGIN Tx_Dsm_Next <= Dsm; CASE Dsm IS WHEN sIdle => IF Tx_On = '1' AND TX_OWN = '1' AND Retry_Cnt = 0 THEN IF (Ext_Tx = '1' AND Ext_Ack = '0') OR Tx_Wait = '0' THEN Tx_Dsm_Next <= sLen; END IF; END IF; WHEN sLen => IF Tx_Sync = '0' THEN Tx_Dsm_Next <= sAdrH; ELSE Tx_Dsm_Next <= sBegH; END IF; WHEN sBegH => Tx_Dsm_Next <= sBegL; WHEN sBegL => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle; ELSIF Tx_Sync = '0' THEN if Tx_Del = '1' then Tx_Dsm_Next <= sDel; elsIF Sm_Tx = R_Pre THEN Tx_Dsm_Next <= sTimH; END IF; ELSIF Tx_Beg = '1' THEN Tx_Dsm_Next <= sAdrH; END IF; WHEN sDel => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle; --avoid FSM hang ELSIF Tx_Del_End = '1' THEN Tx_Dsm_Next <= sTimH; END IF; WHEN sAdrH => Tx_Dsm_Next <= sAdrL; WHEN sAdrL => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle; elsif Tx_Del = '1' then Tx_Dsm_Next <= sBegH; ELSIF Tx_Sync = '0' THEN Tx_Dsm_Next <= sBegL; ELSIF Sm_Tx = R_Bop THEN Tx_Dsm_Next <= sTimH; END IF; WHEN sTimH => Tx_Dsm_Next <= sTimL; WHEN sTimL => Tx_Dsm_Next <= sData; WHEN sData => IF F_End = '1' THEN Tx_Dsm_Next <= sStat; ELSIF Tx_Col = '1' THEN Tx_Dsm_Next <= sColl; END IF; WHEN sStat => Tx_Dsm_Next <= sIdle; WHEN sColl => if sm_tx = r_idl then if Tx_Sync = '1' then Tx_Dsm_Next <= sStat; else Tx_Dsm_Next <= sIdle; end if; end if; WHEN OTHERS => END CASE; IF Rst = '1' THEN Dsm <= sIdle; ELSIF rising_edge( Clk ) THEN Dsm <= Tx_Dsm_Next; END IF; END PROCESS pTxSm; pTxControl: PROCESS( Rst, Clk ) BEGIN IF Rst = '1' THEN Last_Desc <= '0'; Start_TxS <= '0'; Tx_Dma_Req <= '0'; H_Byte <= '0'; Tx_Beg <= '0'; Tx_BegSet <= '0'; Tx_Early <= '0'; Auto_Coll <= '0'; Tx_Dma_Out <= '0'; Ext_Tx <= '0'; Ext_Ack <= '0'; ClrCol <= '0'; Ext_Desc <= (OTHERS => '0'); Tx_Sync <= '0'; Max_Retry <= (others => '0'); ZeitL <= (OTHERS => '0'); Tx_Count <= (OTHERS => '0'); Tx_Ident <= "00"; Dma_Tx_Addr <= (OTHERS => '0'); Tx_Cmp_High <= (others => '0'); Tx_Del_Run <= '0'; Tx_Del <= '0'; Tx_Del_Cnt <= (others => '0'); ELSIF rising_edge( Clk ) THEN IF TxSyncOn = true THEN IF Tx_Sync = '1' AND Dsm = sBegL AND (Tx_Cmp_High & DescRam_Out) = Zeit THEN Tx_Beg <= '1'; ELSE Tx_Beg <= '0'; END IF; END IF; IF Dsm = sStat AND Desc_We = '1' THEN ClrCol <= '1'; ELSE ClrCol <= '0'; END IF; IF Timer THEN IF Dsm = sTimH THEN ZeitL <= Zeit(15 DOWNTO 0); END IF; END IF; IF Ext_Ack = '0' AND R_Req = '1' THEN Ext_Desc <= Auto_Desc; Ext_Ack <= '1'; ELSIF Ext_Tx = '1' OR Tx_On = '0' THEN Ext_Ack <= '0'; END IF; IF Dsm = sIdle AND Ext_Ack = '1' THEN Ext_Tx <= '1'; ELSIF Dsm = sStat OR Tx_Col = '1' OR Tx_On = '0' THEN Ext_Tx <= '0'; END IF; IF (F_End = '1' OR Tx_On = '0' OR (Tx_Col = '1' AND Ext_Tx = '1' ) OR dsm = sColl ) THEN Start_TxS <= '0'; Auto_Coll <= Auto_Coll OR (Tx_Col AND Ext_Tx); ELSIF Dsm = sAdrH and Tx_Del = '0' THEN Start_TxS <= '1'; ELSIF Dsm = sDel and Tx_Del_End = '1' THEN Start_TxS <= '1'; ELSIF Sm_Tx = R_Idl THEN Auto_Coll <= '0'; END IF; IF Dsm = sIdle THEN Last_Desc <= TX_LAST; END IF; IF Dsm = sLen THEN Tx_Count <= TX_LEN; ELSIF F_Val = '1' THEN Tx_Count <= Tx_Count - 1; END IF; IF Dsm = sBegH THEN Tx_Cmp_High <= DescRam_Out; END IF; IF Dsm = sIdle AND Tx_On = '1' AND TX_OWN = '1' AND Retry_Cnt = 0 THEN IF Ext_Tx = '1' OR Tx_Wait = '0' THEN IF TxSyncOn THEN Tx_Sync <= TX_TIME; ELSE Tx_Sync <= '0'; END IF; Max_Retry <= TX_RETRY; Tx_Early <= TX_BEGON; IF TxDel = true THEN Tx_Del <= TX_BEGDEL; END IF; END IF; ELSIF Dsm = sTimH THEN Tx_BegSet <= Tx_Early; ELSIF Dsm = sTimL THEN Tx_BegSet <= '0'; ELSIF Dsm = sIdle THEN Tx_Del <= '0'; END IF; if TxDel = true and Tx_Del = '1' then if Dsm = sBegH then Tx_Del_Cnt(Tx_Del_Cnt'high) <= '0'; Tx_Del_Cnt(31 downto 16) <= DescRam_Out; elsif Dsm = sBegL then Tx_Del_Cnt(15 downto 0) <= DescRam_Out; elsif Dsm = sDel and Tx_Del_Run = '1' then Tx_Del_Cnt <= Tx_Del_Cnt - 1; end if; if Tx_Del_Run = '0' and Dsm = sDel then Tx_Del_Run <= '1'; --don't consider Ipg elsif Tx_Del_End = '1' then Tx_Del_Run <= '0'; end if; end if; IF Dsm = sAdrL THEN Dma_Tx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1); ELSIF Tx_Dma_Ack = '1' THEN Dma_Tx_Addr(15 DOWNTO 1) <= Dma_Tx_Addr(15 DOWNTO 1) + 1; END IF; IF Dsm = sAdrH THEN Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0); Tx_Ident <= DescRam_Out(15 DOWNTO 14); ELSIF Tx_Dma_Ack = '1' AND Dma_Tx_Addr(15 DOWNTO 1) = x"FFF" & "111" THEN Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) <= Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) + 1; END IF; IF DSM = sAdrL OR (F_Val = '1' AND H_Byte = '0') THEN Tx_Dma_Req <= '1' AFTER 0 nS; ELSIF Tx_Dma_Ack = '1' THEN Tx_Dma_Req <= '0'; END IF; IF Sm_Tx = R_Bop THEN H_Byte <= '0'; ELSIF F_Val = '1' THEN H_Byte <= NOT H_Byte; END IF; IF F_Val = '1' THEN Tx_Buf <= Tx_LatchL; END IF; if H_Byte = '0' and F_Val = '1' and Tx_Dma_Req = '1' then Tx_Dma_Out <= '1'; elsif Sm_Tx = R_Bop then Tx_Dma_Out <= '0'; end if; END IF; END PROCESS pTxControl; Start_Tx <= '1' WHEN Start_TxS = '1' AND Block_Col = '0' ELSE '1' WHEN not TxDel and not TxSyncOn and R_Req = '1' ELSE '0'; F_TxB <= Tx_LatchH WHEN H_Byte = '0' ELSE Tx_Buf; nTx_Int <= '1' WHEN (Tx_Icnt = 0 AND Tx_SoftInt = '0') OR Tx_Ie = '0' ELSE '0'; Tx_Idle <= '1' WHEN Sm_Tx = R_Idl AND Dsm = sIdle ELSE '0'; Tx_Reg(15 DOWNTO 4) <= Tx_Ie & Tx_SoftInt & Tx_Half & Tx_Wait & (Tx_Icnt(4) OR Tx_Icnt(3)) & Tx_Icnt(2 DOWNTO 0) & Tx_On & Tx_BegInt & Tx_Idle & "0" ; Tx_Reg( 3 DOWNTO 0) <= Tx_Desc; Sel_TxH <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '0' AND Ram_Be(1) = '1' ELSE '0'; Sel_TxL <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '0' AND Ram_Be(0) = '1' ELSE '0'; Tx_Desc <= Tx_Desc_One; Tx_SoftInt <= '0'; pTxRegs: PROCESS( Rst, Clk ) BEGIN IF Rst = '1' THEN Tx_On <= '0'; Tx_Ie <= '0'; Tx_Half <= '0'; Tx_Wait <= '0'; nTx_BegInt <= '0'; Tx_Desc_One <= (OTHERS => '0'); Tx_Icnt <= (OTHERS => '0'); TxInt <= '0'; Tx_BegInt <= '0'; Tx_Ipg <= conv_std_logic_vector( 42, 6); ELSIF rising_edge( Clk ) THEN IF Sel_TxL = '1' THEN IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_On <= S_Din( 7); ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din( 7) = '1' THEN Tx_On <= '1'; ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din( 7) = '1' THEN Tx_On <= '0'; END IF; END IF; IF Tx_BegSet = '1' AND Tx_Ie = '1' THEN Tx_BegInt <= '1'; ELSIF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "01" AND S_Din( 6) = '1' THEN Tx_BegInt <= '1'; ELSIF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din( 6) = '1' THEN Tx_BegInt <= '0'; END IF; nTx_BegInt <= NOT Tx_BegInt; IF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "11" THEN Tx_Desc_One <= S_Din( 3 DOWNTO 0); ELSIF Dsm = sStat AND Ext_Tx = '0' THEN IF Last_Desc = '1' THEN Tx_Desc_One <= x"0"; ELSE Tx_Desc_One <= Tx_Desc + 1; END IF; END IF; IF Sel_TxH = '1' THEN IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Ie <= S_Din(15); ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(15) = '1' THEN Tx_Ie <= '1'; ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(15) = '1' THEN Tx_Ie <= '0'; END IF; END IF; IF Sel_TxH = '1' THEN IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Half <= S_Din(13); ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(13) = '1' THEN Tx_Half <= '1'; ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(13) = '1' THEN Tx_Half <= '0'; END IF; END IF; IF Sel_TxH = '1' THEN IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Wait <= S_Din(12); ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(12) = '1' THEN Tx_Wait <= '1'; ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(12) = '1' THEN Tx_Wait <= '0'; END IF; END IF; IF Sel_TxH = '1' THEN IF s_Adr(2 DOWNTO 1) = "11" AND S_Din(14) = '1' THEN Tx_Ipg <= S_Din(13 DOWNTO 8); END IF; END IF; IF Tx_Ie = '1' AND Dsm = sStat AND Desc_We = '1' THEN TxInt <= '1'; ELSE TxInt <= '0'; END IF; IF Sel_TxH = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din(8) = '1' AND Tx_Icnt /= 0 THEN Tx_Icnt <= Tx_Icnt - NOT TxInt; ELSIF TxInt = '1' AND Tx_Icnt /= "11111" THEN Tx_Icnt <= Tx_Icnt + 1; END IF; END IF; END PROCESS pTxRegs; END BLOCK bTxDesc; END BLOCK b_Full_Tx; b_Full_Rx: BLOCK TYPE MACRX_TYPE IS ( R_Idl, R_Sof, R_Rxd ); SIGNAL Sm_Rx : MACRX_TYPE; SIGNAL Rx_Dat, Rx_DatL : std_logic_vector( 1 DOWNTO 0); SIGNAL Tx_Timer : std_logic_vector( 7 DOWNTO 0); SIGNAL Dibl_Cnt : std_logic_vector( 1 DOWNTO 0); SIGNAL Crc, nCrc : std_logic_vector(31 DOWNTO 0); SIGNAL CrcDin : std_logic_vector( 1 DOWNTO 0); SIGNAL F_Err, P_Err, N_Err, A_Err : std_logic; SIGNAL F_End, F_Val, Rx_Beg : std_logic; SIGNAL Rx_Sr : std_logic_vector( 7 DOWNTO 0); SIGNAL nCrc_Ok, Crc_Ok : std_logic; SIGNAL WrDescStat : std_logic; SIGNAL PreCount : std_logic_vector( 4 DOWNTO 0); SIGNAL PreBeg, PreErr : std_logic; SIGNAL Rx_DvL : std_logic; SIGNAL Diag : std_logic; BEGIN Rx_Beg <= '1' WHEN Rx_Dv = '1' AND Sm_Rx = R_SOF AND Rx_Dat = "11" ELSE '0'; nCrc_Ok <= '1' WHEN nCrc = x"C704DD7B" ELSE '0'; rxsm: PROCESS ( Clk, Rst ) IS BEGIN IF Rst = '1' THEN Sm_Rx <= R_Idl; ELSIF rising_edge( Clk ) THEN IF Sm_Rx = R_Idl OR Sm_Rx = R_Rxd OR Sm_Rx = R_Sof OR Dibl_Cnt = "11" THEN CASE Sm_Rx IS WHEN R_Idl => IF Rx_Dv = '1' THEN Sm_Rx <= R_Sof; END IF; WHEN R_Sof => IF Rx_Dat = "11" THEN Sm_Rx <= R_Rxd; ELSIF Rx_Dv = '0' THEN Sm_Rx <= R_Idl; END IF; WHEN R_Rxd => IF Rx_Dv = '0' THEN Sm_Rx <= R_Idl; END IF; WHEN OTHERS => NULL; END CASE; END IF; END IF; END PROCESS rxsm; pRxCtl: PROCESS ( Clk, Rst ) IS VARIABLE Preload : std_logic_vector(Tx_Timer'RANGE); VARIABLE Load : std_logic; BEGIN IF Rst = '1' THEN Rx_DatL <= "00"; Rx_Dat <= "00"; Rx_Dv <= '0'; Dibl_Cnt <= "00"; PreCount <= (OTHERS => '0'); F_End <= '0'; F_Err <= '0'; F_Val <= '0'; Crc_Ok <= '0'; A_Err <= '0'; N_Err <= '0'; P_Err <= '0'; PreBeg <= '0'; PreErr <= '0'; ELSIF rising_edge( Clk ) THEN Rx_DatL <= rRx_Dat; Rx_Dat <= Rx_DatL; IF Rx_Dv = '0' AND rCrs_Dv = '1' THEN Rx_Dv <= '1'; ELSIF Rx_Dv = '1' AND rCrs_Dv = '0' AND Dibl_Cnt(0) = '1' THEN Rx_Dv <= '0'; END IF; IF Rx_Beg = '1' THEN Dibl_Cnt <= "00"; ELSE Dibl_Cnt <= Dibl_Cnt + 1; END IF; Crc_Ok <= nCrc_Ok; IF (Sm_Rx = R_Rxd AND Rx_Dv = '0') THEN F_End <= '1'; F_Err <= NOT Crc_Ok; ELSE F_End <= '0'; END IF; IF Dibl_Cnt = "11" AND Sm_Rx = R_Rxd THEN F_Val <= '1'; ELSE F_Val <= '0'; END IF; IF WrDescStat = '1' THEN A_Err <= '0'; ELSIF F_End = '1' AND Dibl_Cnt /= 1 THEN A_Err <= '1'; END IF; IF Rx_Dv = '0' OR Rx_Dat(0) = '0' THEN PreCount <= (OTHERS => '1'); ELSE PreCount <= PreCount - 1; END IF; IF Rx_Dv = '0' THEN PreBeg <= '0'; ELSIF Rx_Dat = "01" THEN PreBeg <= '1'; END IF; IF WrDescStat = '1' THEN N_Err <= '0'; ELSIF Sm_Rx = R_Sof AND Rx_Dv = '0' THEN N_Err <= '1'; END IF; IF Rx_DvL = '0' THEN PreErr <= '0'; ELSIF PreBeg = '0' AND (Rx_Dat = "10" OR Rx_Dat = "11") THEN PreErr <= '1'; ELSIF PreBeg = '1' AND (Rx_Dat = "10" OR Rx_Dat = "00") THEN PreErr <= '1'; END IF; IF WrDescStat = '1' THEN P_Err <= '0'; ELSIF Rx_Beg = '1' AND PreErr = '1' THEN P_Err <= '1'; ELSIF Rx_Beg = '1' AND PreCount /= 0 THEN P_Err <= '1'; END IF; Rx_Sr <= Rx_Dat(1) & Rx_Dat(0) & Rx_Sr(7 DOWNTO 2); Rx_DvL <= Rx_Dv; END IF; END PROCESS pRxCtl; CrcDin <= Rx_Dat; Calc: PROCESS ( Clk, Crc, nCrc, CrcDin, Sm_Rx ) IS VARIABLE H : std_logic_vector(1 DOWNTO 0); BEGIN H(0) := Crc(31) XOR CrcDin(0); H(1) := Crc(30) XOR CrcDin(1); IF Sm_Rx = R_Sof THEN nCrc <= x"FFFFFFFF"; ELSE nCrc( 0) <= H(1); nCrc( 1) <= H(0) XOR H(1); nCrc( 2) <= Crc( 0) XOR H(0) XOR H(1); nCrc( 3) <= Crc( 1) XOR H(0) ; nCrc( 4) <= Crc( 2) XOR H(1); nCrc( 5) <= Crc( 3) XOR H(0) XOR H(1); nCrc( 6) <= Crc( 4) XOR H(0) ; nCrc( 7) <= Crc( 5) XOR H(1); nCrc( 8) <= Crc( 6) XOR H(0) XOR H(1); nCrc( 9) <= Crc( 7) XOR H(0) ; nCrc(10) <= Crc( 8) XOR H(1); nCrc(11) <= Crc( 9) XOR H(0) XOR H(1); nCrc(12) <= Crc(10) XOR H(0) XOR H(1); nCrc(13) <= Crc(11) XOR H(0) ; nCrc(14) <= Crc(12) ; nCrc(15) <= Crc(13) ; nCrc(16) <= Crc(14) XOR H(1); nCrc(17) <= Crc(15) XOR H(0) ; nCrc(18) <= Crc(16) ; nCrc(19) <= Crc(17) ; nCrc(20) <= Crc(18) ; nCrc(21) <= Crc(19) ; nCrc(22) <= Crc(20) XOR H(1); nCrc(23) <= Crc(21) XOR H(0) XOR H(1); nCrc(24) <= Crc(22) XOR H(0) ; nCrc(25) <= Crc(23) ; nCrc(26) <= Crc(24) XOR H(1); nCrc(27) <= Crc(25) XOR H(0) ; nCrc(28) <= Crc(26) ; nCrc(29) <= Crc(27) ; nCrc(30) <= Crc(28) ; nCrc(31) <= Crc(29) ; END IF; IF rising_edge( Clk ) THEN Crc <= nCrc; END IF; END PROCESS Calc; bRxDesc: BLOCK TYPE sDESC IS (sIdle, sLen, sTimL, sTimH, sAdrH, sAdrL, sData, sOdd, sStat, sLenW ); SIGNAL Dsm, Rx_Dsm_Next : sDESC; SIGNAL Rx_Buf, Rx_LatchH, Rx_LatchL : std_logic_vector( 7 DOWNTO 0); SIGNAL Rx_Ovr : std_logic; SIGNAL DescRam_Out, DescRam_In : std_logic_vector(15 DOWNTO 0); ALIAS RX_LEN : std_logic_vector(11 DOWNTO 0) IS DescRam_Out(11 DOWNTO 0); ALIAS RX_OWN : std_logic IS DescRam_Out( 8); ALIAS RX_LAST : std_logic IS DescRam_Out( 9); SIGNAL Ram_Be : std_logic_vector( 1 DOWNTO 0); SIGNAL Ram_Wr, Desc_We : std_logic; SIGNAL Desc_Addr : std_logic_vector( 7 DOWNTO 0); SIGNAL ZeitL : std_logic_vector(15 DOWNTO 0); SIGNAL Rx_On, Rx_Ie, Sel_RxH, Sel_RxL : std_logic; SIGNAL Rx_Desc, Match_Desc : std_logic_vector( 3 DOWNTO 0); SIGNAL Rx_Icnt : std_logic_vector( 4 DOWNTO 0); SIGNAL Rx_Lost, Last_Desc, Answer_Tx : std_logic; SIGNAL DescIdx : std_logic_vector( 2 DOWNTO 0); SIGNAL Rx_Count, Rx_Limit : std_logic_vector(11 DOWNTO 0); SIGNAL Match, Filt_Cmp : std_logic; SIGNAL Rx_Idle, RxInt : std_logic; SIGNAL Hub_Rx_L : std_logic_vector( 1 DOWNTO 0); SIGNAL Rx_Dma_Out : std_logic; signal Rx_Done : std_logic; BEGIN Rx_Done <= '1' when Dsm /= sIdle and Rx_Dsm_Next = sIdle else '0'; Dma_Wr_Done <= Rx_Done; Rx_Dma_Req_Overflow <= '1' when Dsm = sOdd and Rx_Ovr = '0' else '1' when Dsm = sData and Rx_Ovr = '0' and F_Val = '1' and Rx_Count(0) = '1' and RX_Count > 1 else '1' when Rx_Done = '1' else '0'; WrDescStat <= '1' WHEN Dsm = sStat ELSE '0'; Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '1' ELSE '0'; Ram_Be(1) <= '1' WHEN s_nWr = '1' OR s_nBE(1) = '0' ELSE '0'; Ram_Be(0) <= '1' WHEN s_nWr = '1' OR s_nBE(0) = '0' ELSE '0'; DescIdx <= "001" WHEN Desc_We = '0' AND (Rx_Dsm_Next = sLen OR Rx_Dsm_Next = sLenW) ELSE "001" WHEN Desc_We = '1' AND (Dsm = sLen OR Dsm = sLenW) ELSE "010" WHEN Desc_We = '0' AND Rx_Dsm_Next = sAdrH ELSE "010" WHEN Desc_We = '1' AND Dsm = sAdrH ELSE "011" WHEN Desc_We = '0' AND Rx_Dsm_Next = sAdrL ELSE "011" WHEN Desc_We = '1' AND Dsm = sAdrL ELSE "110" WHEN Desc_We = '0' AND Rx_Dsm_Next = sTimH ELSE "110" WHEN Desc_We = '1' AND Dsm = sTimH ELSE "111" WHEN Desc_We = '0' AND Rx_Dsm_Next = sTimL ELSE "111" WHEN Desc_We = '1' AND Dsm = sTimL ELSE "000"; Desc_We <= '1' WHEN Dsm = sTimL OR Dsm = sTimH ELSE '1' WHEN (Dsm = sLenW OR Dsm = sStat) AND Match = '1' ELSE '0'; Desc_Addr <= "0" & Rx_Desc & DescIdx; gRxTime: IF timer GENERATE DescRam_In <= Zeit(31 DOWNTO 16) WHEN Dsm = sTimH ELSE ZeitL WHEN Dsm = sTimL ELSE x"0" & Rx_Count WHEN Dsm = sLenW ELSE Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err; END GENERATE; ngRxTime: IF NOT timer GENERATE DescRam_In <= x"0" & Rx_Count WHEN Dsm = sLenW ELSE Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err; END GENERATE; RxRam: ENTITY work.Dpr_16_16 GENERIC MAP(Simulate => Simulate) PORT MAP ( CLKA => Clk, CLKB => Clk, EnA => cActivated, Enb => cActivated, BEA => Ram_Be, WEA => Ram_Wr, WEB => Desc_We, ADDRA => s_Adr(8 DOWNTO 1), ADDRB => Desc_Addr, DIA => s_Din, DIB => DescRam_In, DOA => Rx_Ram_Dat, DOB => DescRam_Out ); pRxSm: PROCESS( Rst, Clk, Dsm, Rx_Beg, Rx_On, RX_OWN, F_End, F_Err, Diag, Rx_Count ) BEGIN Rx_Dsm_Next <= Dsm; CASE Dsm IS WHEN sIdle => IF Rx_Beg = '1' AND Rx_On = '1' AND RX_OWN = '1' THEN Rx_Dsm_Next <= sLen; END IF; WHEN sLen => Rx_Dsm_Next <= sAdrH; WHEN sAdrH => Rx_Dsm_Next <= sAdrL; WHEN sAdrL => Rx_Dsm_Next <= sTimH; WHEN sTimH => Rx_Dsm_Next <= sTimL; WHEN sTimL => Rx_Dsm_Next <= sData; WHEN sData => IF F_End = '1' THEN IF F_Err = '0' OR Diag = '1' THEN Rx_Dsm_Next <= sStat; ELSE Rx_Dsm_Next <= sIdle; END IF; END IF; WHEN sStat => Rx_Dsm_Next <= sLenW; WHEN sLenW => IF Rx_Count(0) = '0' THEN Rx_Dsm_Next <= sIdle; ELSE Rx_Dsm_Next <= sOdd; END IF; WHEN sOdd => Rx_Dsm_Next <= sIdle; WHEN OTHERS => END CASE; IF Rst = '1' THEN Dsm <= sIdle; ELSIF rising_edge( Clk ) THEN Dsm <= Rx_Dsm_Next; END IF; END PROCESS pRxSm; pRxControl: PROCESS( Rst, Clk ) BEGIN IF Rst = '1' THEN Rx_Ovr <= '0'; Rx_Dma_Req <= '0'; Last_Desc <= '0'; Rx_Dma_Out <= '0'; Rx_Count <= (OTHERS => '0'); Rx_Buf <= (OTHERS => '0'); Rx_LatchL <= (OTHERS => '0'); Rx_LatchH <= (OTHERS => '0'); Dma_Rx_Addr <= (OTHERS => '0'); ELSIF rising_edge( Clk ) THEN IF Timer THEN IF Dsm = sTimH THEN ZeitL <= Zeit(15 DOWNTO 0); END IF; END IF; IF Dsm = sIdle THEN Rx_Count <= (OTHERS => '0'); Last_Desc <= RX_LAST; ELSIF F_Val = '1' THEN Rx_Count <= Rx_Count + 1; END IF; IF Dsm = sLen THEN Rx_Limit <= RX_LEN; Hub_Rx_L <= Hub_Rx; END IF; IF F_Val = '1' THEN Rx_Buf <= Rx_Sr; END IF; IF (F_Val = '1' AND Rx_Count(0) = '1') OR Dsm = sStat THEN Rx_LatchH <= Rx_Buf; Rx_LatchL <= Rx_Sr; IF Rx_Dma_Req = '1' AND Sm_Rx /= R_Idl THEN Rx_Dma_Out <= '1'; END IF; ELSIF Dsm = sLen THEN Rx_Dma_Out <= '0'; END IF; IF Dsm = sLen THEN Rx_Ovr <= '0'; ELSIF F_Val = '1' AND Rx_Limit = Rx_Count THEN Rx_Ovr <= '1'; END IF; IF Dsm = sAdrL THEN Dma_Rx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1); ELSIF Rx_Dma_Ack = '1' THEN Dma_Rx_Addr(15 DOWNTO 1) <= Dma_Rx_Addr(15 DOWNTO 1) + 1; END IF; IF Dsm = sAdrH THEN Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0); ELSIF Rx_Dma_Ack = '1' AND Dma_Rx_Addr(15 DOWNTO 1) = x"FFF" & "111" THEN Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) <= Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) + 1; END IF; IF Filt_Cmp = '0' AND Match ='0' THEN Rx_Dma_Req <= '0'; ELSIF (Dsm = sOdd AND Rx_Ovr = '0') OR (Dsm = sData AND Rx_Ovr = '0' AND F_Val = '1' AND Rx_Count(0) = '1') THEN Rx_Dma_Req <= '1' AFTER 101 nS; ELSIF Rx_Dma_Ack = '1' THEN Rx_Dma_Req <= '0'; END IF; END IF; END PROCESS pRxControl; Dma_Dout <= Rx_LatchH & Rx_LatchL; nRx_Int <= '1' WHEN Rx_Icnt = 0 OR Rx_Ie = '0' ELSE '0'; Rx_Idle <= '1' WHEN Sm_Rx = R_Idl ELSE '0'; Rx_Reg(15 DOWNTO 4) <= Rx_Ie & '0' & "0" & '0' & (Rx_Icnt(4) OR Rx_Icnt(3)) & Rx_Icnt(2 DOWNTO 0) & Rx_On & "0" & Rx_Idle & Rx_Lost; Rx_Reg( 3 DOWNTO 0) <= Rx_Desc; bFilter: BLOCK SIGNAL Ram_Addr : std_logic_vector( 7 DOWNTO 0); SIGNAL Ram_BeH, Ram_BeL : std_logic_vector( 1 DOWNTO 0); SIGNAL Ram_Wr : std_logic; SIGNAL Filter_Addr : std_logic_vector( 6 DOWNTO 0); SIGNAL Filter_Out_H, Filter_Out_L : std_logic_vector(31 DOWNTO 0); ALIAS DIRON_0 : std_logic IS Filter_Out_H( 11); ALIAS DIRON_1 : std_logic IS Filter_Out_H( 27); ALIAS DIRON_2 : std_logic IS Filter_Out_L( 11); ALIAS DIRON_3 : std_logic IS Filter_Out_L( 27); ALIAS TX_0 : std_logic IS Filter_Out_H( 7); ALIAS TX_1 : std_logic IS Filter_Out_H(23); ALIAS TX_2 : std_logic IS Filter_Out_L( 7); ALIAS TX_3 : std_logic IS Filter_Out_L(23); ALIAS ON_0 : std_logic IS Filter_Out_H( 6); ALIAS ON_1 : std_logic IS Filter_Out_H(22); ALIAS ON_2 : std_logic IS Filter_Out_L( 6); ALIAS ON_3 : std_logic IS Filter_Out_L(22); ALIAS DESC_0 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_H( 3 DOWNTO 0); ALIAS DESC_1 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_H(19 DOWNTO 16); ALIAS DESC_2 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_L( 3 DOWNTO 0); ALIAS DESC_3 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_L(19 DOWNTO 16); SIGNAL Byte_Cnt : std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0'); SIGNAL Erg0, Erg1, Erg2, Erg3 : std_logic_vector( 7 DOWNTO 0); SIGNAL Mat_Reg : std_logic_vector(15 DOWNTO 0); SIGNAL Filt_Idx : std_logic_vector( 1 DOWNTO 0); SIGNAL Mat_Sel : std_logic_vector( 3 DOWNTO 0); SIGNAL M_Prio : std_logic_vector( 2 DOWNTO 0); ALIAS Found : std_logic IS M_Prio(2); BEGIN Ram_Addr <= s_Adr(9 DOWNTO 8) & s_Adr(5 DOWNTO 1) & s_Adr(6); Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '0' ELSE '0'; Ram_BeH(1) <= '1' WHEN s_nWr = '1' OR (s_nBE(1) = '0' AND s_Adr( 7) = '0') ELSE '0'; Ram_BeH(0) <= '1' WHEN s_nWr = '1' OR (s_nBE(0) = '0' AND s_Adr( 7) = '0') ELSE '0'; Ram_BeL(1) <= '1' WHEN s_nWr = '1' OR (s_nBE(1) = '0' AND s_Adr( 7) = '1') ELSE '0'; Ram_BeL(0) <= '1' WHEN s_nWr = '1' OR (s_nBE(0) = '0' AND s_Adr( 7) = '1') ELSE '0'; Filter_Addr <= Dibl_Cnt & Byte_Cnt; FiltRamH: ENTITY work.Dpr_16_32 GENERIC MAP(Simulate => Simulate) PORT MAP ( CLKA => Clk, CLKB => Clk, EnA => cActivated, EnB => cActivated, BEA => Ram_BeH, WEA => Ram_Wr, ADDRA => Ram_Addr, ADDRB => Filter_Addr, DIA => s_Din, DOB => Filter_Out_H ); FiltRamL: ENTITY work.Dpr_16_32 GENERIC MAP(Simulate => Simulate) PORT MAP ( CLKA => Clk, CLKB => Clk, EnA => cActivated, EnB => cActivated, BEA => Ram_BeL, WEA => Ram_Wr, ADDRA => Ram_Addr, ADDRB => Filter_Addr, DIA => s_Din, DOB => Filter_Out_L ); Erg0 <= (Rx_Buf XOR Filter_Out_H( 7 DOWNTO 0)) AND Filter_Out_H(15 DOWNTO 8); Erg1 <= (Rx_Buf XOR Filter_Out_H(23 DOWNTO 16)) AND Filter_Out_H(31 DOWNTO 24); Erg2 <= (Rx_Buf XOR Filter_Out_L( 7 DOWNTO 0)) AND Filter_Out_L(15 DOWNTO 8); Erg3 <= (Rx_Buf XOR Filter_Out_L(23 DOWNTO 16)) AND Filter_Out_L(31 DOWNTO 24); genMatSel: FOR i IN 0 TO 3 GENERATE Mat_Sel(i) <= Mat_Reg( 0 + i) WHEN Filt_Idx = "00" ELSE Mat_Reg( 4 + i) WHEN Filt_Idx = "01" ELSE Mat_Reg( 8 + i) WHEN Filt_Idx = "10" ELSE Mat_Reg(12 + i); -- WHEN Filt_Idx = "11"; END GENERATE; M_Prio <= "000" WHEN Filt_Cmp = '0' OR Match = '1' ELSE "100" WHEN Mat_Sel(0) = '1' AND On_0 = '1' AND (DIRON_0 = '0') ELSE "101" WHEN Mat_Sel(1) = '1' AND On_1 = '1' AND (DIRON_1 = '0') ELSE "110" WHEN Mat_Sel(2) = '1' AND On_2 = '1' AND (DIRON_2 = '0') ELSE "111" WHEN Mat_Sel(3) = '1' AND On_3 = '1' AND (DIRON_3 = '0') ELSE "000"; pFilter: PROCESS( Rst, Clk ) BEGIN IF Rst = '1' THEN Filt_Idx <= "00"; Match <= '0'; Filt_Cmp <= '0'; Mat_Reg <= (OTHERS => '0'); Byte_Cnt <= (OTHERS =>'0'); Match_Desc <= (OTHERS => '0');Auto_Desc <= (OTHERS =>'0'); Answer_Tx <= '0'; ELSIF rising_edge( Clk ) THEN Filt_Idx <= Dibl_Cnt; IF Dibl_Cnt = "11" AND Rx_Count(5) = '0' THEN Byte_Cnt <= Rx_Count(Byte_Cnt'RANGE); END IF; IF Dsm = sTiml THEN Filt_Cmp <= '1'; ELSIF Rx_Dv = '0' OR (F_Val = '1' AND Rx_Count(5) = '1') THEN Filt_Cmp <= '0'; END IF; IF Dsm = sTimL THEN Mat_Reg <= (OTHERS => '1'); ELSE FOR i IN 0 TO 3 LOOP IF Erg0 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 0) <= '0'; END IF; IF Erg1 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 1) <= '0'; END IF; IF Erg2 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 2) <= '0'; END IF; IF Erg3 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 3) <= '0'; END IF; END LOOP; END IF; IF Dsm = sTimL THEN Match <= '0'; ELSIF Found = '1' THEN Match <= '1'; Match_Desc <= Filt_Idx & M_Prio(1 DOWNTO 0); IF M_Prio(1 DOWNTO 0) = "00" THEN Answer_Tx <= TX_0; Auto_Desc <= DESC_0; ELSIF M_Prio(1 DOWNTO 0) = "01" THEN Answer_Tx <= TX_1; Auto_Desc <= DESC_1; ELSIF M_Prio(1 DOWNTO 0) = "10" THEN Answer_Tx <= TX_2; Auto_Desc <= DESC_2; ELSIF M_Prio(1 DOWNTO 0) = "11" THEN Answer_Tx <= TX_3; Auto_Desc <= DESC_3; END IF; ELSIF F_End = '1' THEN Answer_Tx <= '0'; END IF; END IF; END PROCESS pFilter; R_Req <= Answer_Tx WHEN F_End = '1' AND F_Err = '0' ELSE '0'; END BLOCK bFilter; Sel_RxH <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '1' AND s_nBe(1) = '0' ELSE '0'; Sel_RxL <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '1' AND s_nBe(0) = '0' ELSE '0'; pRxRegs: PROCESS( Rst, Clk ) BEGIN IF Rst = '1' THEN Rx_Desc <= (OTHERS => '0'); Rx_On <= '0'; Rx_Ie <= '0'; Rx_Lost <= '0'; Rx_Icnt <= (OTHERS => '0'); RxInt <= '0'; Diag <= '0'; ELSIF rising_edge( Clk ) THEN IF Sel_RxH = '1' THEN IF s_Adr(2 DOWNTO 1) = "00" THEN Rx_Ie <= S_Din(15); ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(15) = '1' THEN Rx_Ie <= '1'; ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(15) = '1' THEN Rx_Ie <= '0'; END IF; END IF; IF Sel_RxH = '1' THEN IF s_Adr(2 DOWNTO 1) = "00" THEN Diag <= S_Din(12); ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(12) = '1' THEN Diag <= '1'; ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(12) = '1' THEN Diag <= '0'; END IF; END IF; IF Sel_RxL = '1' THEN IF s_Adr(2 DOWNTO 1) = "00" THEN Rx_On <= S_Din( 7); ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din( 7) = '1' THEN Rx_On <= '1'; ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din( 7) = '1' THEN Rx_On <= '0'; END IF; END IF; IF Rx_Beg = '1' AND (RX_OWN = '0' OR Rx_On = '0') THEN Rx_Lost <= '1'; ELSIF Sel_RxL = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din( 4) = '1' THEN Rx_Lost <= '0'; END IF; IF Sel_RxL = '1' AND s_Adr(2 DOWNTO 1) = "11" THEN Rx_Desc <= S_Din( 3 DOWNTO 0); ELSIF Dsm = sLenW AND Desc_We = '1' THEN IF Last_Desc = '1' THEN Rx_Desc <= x"0"; ELSE Rx_Desc <= Rx_Desc + 1; END IF; END IF; IF Rx_Ie = '1' AND Desc_We = '1' AND Dsm = sStat THEN RxInt <= '1'; ELSE RxInt <= '0'; END IF; IF Sel_RxH = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din(8) = '1' AND Rx_Icnt /= 0 THEN Rx_Icnt <= Rx_Icnt - NOT RxInt; ELSIF RxInt = '1' AND Rx_Icnt /= "11111" THEN Rx_Icnt <= Rx_Icnt + 1; END IF; END IF; END PROCESS pRxRegs; END BLOCK bRxDesc; END BLOCK b_Full_Rx; END ARCHITECTURE struct;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/xilinx_microblaze/avnet_lx150t/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC_rmii2mii.vhd
5
9192
------------------------------------------------------------------------------------------------------------------------ -- RMII to MII converter -- ex: openMAC - openHUB - RMII2MII - MII PHY -- -- Copyright (C) 2009 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files: -- OpenMAC_DPR_Altera.vhd -- OpenMAC_DPR_Xilinx.vhd -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2010-09-13 V0.01 first version -- 2010-11-15 V0.02 bug fix: increased size of rx fifo, because of errors with marvel 88e1111 mii phy -- 2010-11-30 V0.03 bug fix: in case of no link some phys confuse tx fifo during tx => aclr fifo -- 2011-05-06 V0.10 bug fix: use the RX_ER signal, it has important meaning! -- 2011-07-23 V0.11 forward RxErr to RMII -- 2011-10-13 V0.20 abuse openMAC_DMAFifo for the converter to use it in Altera/Xilinx easily -- 2011-11-07 V0.21 increased fifo word size to be on the save side -- 2011-11-18 V0.22 forward of RxErr not necessary ------------------------------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity rmii2mii is port ( clk50 : in std_logic; --used by RMII as well!!! rst : in std_logic; --RMII (MAC) rTxEn : in std_logic; rTxDat : in std_logic_vector(1 downto 0); rRxDv : out std_logic; rRxDat : out std_logic_vector(1 downto 0); rRxEr : out std_logic; --MII (PHY) mTxEn : out std_logic; mTxDat : out std_logic_vector(3 downto 0); mTxClk : in std_logic; mRxDv : in std_logic; mRxEr : in std_logic; mRxDat : in std_logic_vector(3 downto 0); mRxClk : in std_logic ); end rmii2mii; architecture rtl of rmii2mii is constant DIBIT_SIZE : integer := 2; constant NIBBLE_SIZE : integer := 4; begin TX_BLOCK : block --fifo size must not be larger than 2**5 constant FIFO_NIBBLES_LOG2 : integer := 5; signal fifo_half, fifo_full, fifo_empty, fifo_valid, fifo_wrempty : std_logic; signal fifo_wr, fifo_rd : std_logic; signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0); signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0); signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0); signal fifo_wrUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0); --necessary for clr fifo signal aclr, rTxEn_l : std_logic; --convert dibits to nibble signal sel_dibit : std_logic; signal fifo_din_reg : std_logic_vector(rTxDat'range); begin fifo_din <= rTxDat & fifo_din_reg; fifo_wr <= sel_dibit; --convert dibits to nibble (to fit to fifo) process(clk50, rst) begin if rst = '1' then sel_dibit <= '0'; fifo_din_reg <= (others => '0'); elsif clk50 = '1' and clk50'event then if rTxEn = '1' then sel_dibit <= not sel_dibit; if sel_dibit = '0' then fifo_din_reg <= rTxDat; end if; else sel_dibit <= '0'; end if; end if; end process; mTxDat <= fifo_dout; --brauch ma net... when fifo_valid = '1' else (others => '0'); mTxEn <= fifo_valid; fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left); process(mTxClk, rst) begin if rst = '1' then fifo_rd <= '0'; fifo_valid <= '0'; elsif mTxClk = '1' and mTxClk'event then if fifo_rd = '0' and fifo_half = '1' then fifo_rd <= '1'; elsif fifo_rd = '1' and fifo_empty = '1' then fifo_rd <= '0'; end if; if fifo_rd = '1' and fifo_rdUsedWord > conv_std_logic_vector(1, fifo_rdUsedWord'length) then fifo_valid <= '1'; else fifo_valid <= '0'; end if; end if; end process; --abuse openMAC's DMA FIFO theRMII2MII_TXFifo : entity work.openMAC_DMAfifo generic map ( fifo_data_width_g => NIBBLE_SIZE, fifo_word_size_g => 2**FIFO_NIBBLES_LOG2, fifo_word_size_log2_g => FIFO_NIBBLES_LOG2 ) port map ( aclr => aclr, rd_clk => mTxClk, wr_clk => clk50, --read port rd_req => fifo_rd, rd_data => fifo_dout, rd_empty => fifo_empty, rd_full => open, rd_usedw => fifo_rdUsedWord, --write port wr_req => fifo_wr, wr_data => fifo_din, wr_empty => fifo_wrempty, wr_full => fifo_full, wr_usedw => fifo_wrUsedWord ); --sync Mii Tx En (=fifo_valid) to wr clk process(clk50, rst) begin if rst = '1' then aclr <= '1'; --reset fifo rTxEn_l <= '0'; elsif clk50 = '1' and clk50'event then rTxEn_l <= rTxEn; aclr <= '0'; --default --clear the full fifo after TX on RMII side is done if fifo_full = '1' and rTxEn_l = '1' and rTxEn = '0' then aclr <= '1'; end if; end if; end process; end block; RX_BLOCK : block --fifo size must not be larger than 2**5 constant FIFO_NIBBLES_LOG2 : integer := 5; signal fifo_half, fifo_full, fifo_empty, fifo_valid : std_logic; signal fifo_wr, fifo_rd : std_logic; signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0); signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0); signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0); signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0); --convert nibble to dibits signal sel_dibit : std_logic; signal fifo_rd_s : std_logic; begin fifo_din <= mRxDat; fifo_wr <= mRxDv and not mRxEr; rRxDat <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = '1' else fifo_dout(fifo_dout'left downto fifo_dout'left-1); rRxDv <= fifo_valid; fifo_rd <= fifo_rd_s and not sel_dibit; process(clk50, rst) begin if rst = '1' then sel_dibit <= '0'; elsif clk50 = '1' and clk50'event then if fifo_rd_s = '1' or fifo_valid = '1' then sel_dibit <= not sel_dibit; else sel_dibit <= '0'; end if; end if; end process; fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left); rRxEr <= '0'; process(clk50, rst) begin if rst = '1' then fifo_rd_s <= '0'; fifo_valid <= '0'; elsif clk50 = '1' and clk50'event then if fifo_rd_s = '0' and fifo_half = '1' then fifo_rd_s <= '1'; elsif fifo_rd_s = '1' and fifo_empty = '1' then fifo_rd_s <= '0'; end if; if fifo_rd_s = '1' then fifo_valid <= '1'; else fifo_valid <= '0'; end if; end if; end process; --abuse openMAC's DMA FIFO theMII2RMII_RXFifo : entity work.openMAC_DMAfifo generic map ( fifo_data_width_g => NIBBLE_SIZE, fifo_word_size_g => 2**FIFO_NIBBLES_LOG2, fifo_word_size_log2_g => FIFO_NIBBLES_LOG2 ) port map ( aclr => rst, rd_clk => clk50, wr_clk => mRxClk, --read port rd_req => fifo_rd, rd_data => fifo_dout, rd_empty => fifo_empty, rd_full => open, rd_usedw => fifo_rdUsedWord, --write port wr_req => fifo_wr, wr_data => fifo_din, wr_empty => open, wr_full => fifo_full, wr_usedw => fifo_wrUsedWord ); end block; end rtl;
gpl-2.0
istankovic/geda-gaf
gnetlist/examples/vams/vhdl/basic-vhdl/capacitor.vhdl
15
320
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CAPACITOR IS GENERIC ( v_init : REAL := 0.0; c : REAL := 10.0e-12 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CAPACITOR;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/portio_cnt.vhd
5
3520
------------------------------------------------------------------------------------------------------------------------ -- Simple Port I/O valid pulse counter -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2011-09-14 V0.01 zelenkaj Extract from portio.vhd ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity portio_cnt is generic ( maxVal : integer := 50 --clock ticks of pcp_clk ); port ( clk : in std_logic; rst : in std_logic; pulse : in std_logic; valid : out std_logic ); end entity portio_cnt; architecture rtl of portio_cnt is signal cnt : integer range 0 to maxVal-2; signal tc, en : std_logic; begin genCnter : if maxVal > 1 generate tc <= '1' when cnt = maxVal-2 else '0'; valid <= en or pulse; counter : process(clk, rst) begin if rst = '1' then cnt <= 0; elsif clk = '1' and clk'event then if tc = '1' then cnt <= 0; elsif en = '1' then cnt <= cnt + 1; else cnt <= 0; end if; end if; end process; enGen : process(clk, rst) begin if rst = '1' then en <= '0'; elsif clk = '1' and clk'event then if pulse = '1' then en <= '1'; elsif tc = '1' then en <= '0'; end if; end if; end process; end generate; genSimple : if maxVal = 1 generate valid <= pulse; end generate; end architecture rtl;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/xilinx_microblaze/avnet_lx150t/pcores/plb_powerlink_v1_00_a/hdl/vhdl/portio_cnt.vhd
5
3520
------------------------------------------------------------------------------------------------------------------------ -- Simple Port I/O valid pulse counter -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2011-09-14 V0.01 zelenkaj Extract from portio.vhd ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity portio_cnt is generic ( maxVal : integer := 50 --clock ticks of pcp_clk ); port ( clk : in std_logic; rst : in std_logic; pulse : in std_logic; valid : out std_logic ); end entity portio_cnt; architecture rtl of portio_cnt is signal cnt : integer range 0 to maxVal-2; signal tc, en : std_logic; begin genCnter : if maxVal > 1 generate tc <= '1' when cnt = maxVal-2 else '0'; valid <= en or pulse; counter : process(clk, rst) begin if rst = '1' then cnt <= 0; elsif clk = '1' and clk'event then if tc = '1' then cnt <= 0; elsif en = '1' then cnt <= cnt + 1; else cnt <= 0; end if; end if; end process; enGen : process(clk, rst) begin if rst = '1' then en <= '0'; elsif clk = '1' and clk'event then if pulse = '1' then en <= '1'; elsif tc = '1' then en <= '0'; end if; end if; end process; end generate; genSimple : if maxVal = 1 generate valid <= pulse; end generate; end architecture rtl;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/xilinx_microblaze/avnet_lx150t/pcores/plb_powerlink_v1_00_a/hdl/vhdl/lib/slow2fastSync.vhd
5
3843
------------------------------------------------------------------------------- -- -- Title : slow2fastSync -- Design : POWERLINK -- ------------------------------------------------------------------------------- -- -- File : C:\my_designs\POWERLINK\src\lib\slow2fastSync.vhd -- Generated : Tue Aug 9 16:38:41 2011 -- From : interface description file -- By : Itf2Vhdl ver. 1.22 -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- 2011-08-09 V0.01 zelenkaj First version -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY slow2fastSync IS GENERIC ( doSync_g : BOOLEAN := TRUE ); PORT ( dataSrc : IN STD_LOGIC; dataDst : OUT STD_LOGIC; clkSrc : IN STD_LOGIC; rstSrc : IN STD_LOGIC; clkDst : IN STD_LOGIC; rstDst : IN STD_LOGIC ); END ENTITY slow2fastSync; ARCHITECTURE rtl OF slow2fastSync IS signal toggle, toggleSync, pulse, dataDst_s : std_logic; begin dataDst <= dataDst_s when doSync_g = TRUE else dataSrc; genSync : IF doSync_g = TRUE GENERATE firstEdgeDet : entity work.edgeDet port map ( din => dataSrc, rising => pulse, falling => open, any => open, clk => clkSrc, rst => rstSrc ); process(clkSrc, rstSrc) begin if rstSrc = '1' then toggle <= '0'; elsif clkSrc = '1' and clkSrc'event then if pulse = '1' then toggle <= not toggle; end if; end if; end process; sync : entity work.sync port map ( din => toggle, dout => toggleSync, clk => clkDst, rst => rstDst ); secondEdgeDet : entity work.edgeDet port map ( din => toggleSync, rising => open, falling => open, any => dataDst_s, clk => clkDst, rst => rstDst ); END GENERATE; END ARCHITECTURE rtl;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC_cmp.vhd
5
4720
------------------------------------------------------------------------------- -- -- Title : openMAC_cmp -- Design : plk_mn -- ------------------------------------------------------------------------------- -- -- File : OpenMAC_cmp.vhd -- Generated : Wed Jul 27 10:52:27 2011 -- From : interface description file -- By : Itf2Vhdl ver. 1.22 -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- 2011-07-26 V0.01 zelenkaj First version -- 2012-01-11 V0.02 mairt moved registers to seperate cmp int and tog int -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity openMAC_cmp is generic( mac_time_width_g : integer := 32; gen2ndCmpTimer_g : boolean := false ); port( clk : in std_logic; rst : in std_logic; wr : in std_logic; addr : in std_logic_vector(1 downto 0); din : in std_logic_vector(31 downto 0); dout : out std_logic_vector(31 downto 0); mac_time : in std_logic_vector(mac_time_width_g-1 downto 0); irq : out std_logic; toggle : out std_logic ); end openMAC_cmp; architecture rtl of openMAC_cmp is signal cmp_enable, tog_enable : std_logic; signal cmp_value, tog_value : std_logic_vector(mac_time'range); signal irq_s, toggle_s : std_logic; begin irq <= irq_s; toggle <= toggle_s; process(clk, rst) begin if rst = '1' then cmp_enable <= '0'; cmp_value <= (others => '0'); irq_s <= '0'; if gen2ndCmpTimer_g = TRUE then tog_enable <= '0'; tog_value <= (others => '0'); toggle_s <= '0'; end if; elsif clk = '1' and clk'event then --cmp if cmp_enable = '1' and mac_time = cmp_value then irq_s <= '1'; end if; --tog if tog_enable = '1' and mac_time = tog_value and gen2ndCmpTimer_g = TRUE then toggle_s <= not toggle_s; end if; --memory mapping if wr = '1' then case addr is when "00" => cmp_value <= din; irq_s <= '0'; when "01" => cmp_enable <= din(0); when "10" => if gen2ndCmpTimer_g = TRUE then tog_value <= din; end if; when "11" => if gen2ndCmpTimer_g = TRUE then tog_enable <= din(0); end if; when others => --go and get a coffee... end case; end if; end if; end process; dout <= mac_time when addr = "00" else x"000000" & "00" & "00" & "00" & irq_s & cmp_enable when addr = "01" else tog_value when addr = "10" and gen2ndCmpTimer_g = TRUE else x"000000" & "00" & "00" & "00" & toggle_s & tog_enable when addr = "11" and gen2ndCmpTimer_g = TRUE else mac_time; --otherwise give me the current time... end rtl;
gpl-2.0
Monash-2015-Ultrasonic/Logs
Final System Code/SYSTEMV3/Source/IP/FIR/FIR_sim/auk_dspip_avalon_streaming_source_hpfir.vhd
2
19165
-- (C) 2001-2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ------------------------------------------------------------------------- ------------------------------------------------------------------------- -- -- Revision Control Information -- -- $Revision: #1 $ -- $Date: 2009/07/29 $ -- Author : Boon Hong Oh -- -- Project : Avalon_streaming II Source Interface with ready_latency=0 -- -- Description : -- -- This interface is capable of handling single or multi channel streams as -- well as blocks of data. The at_source_sop and at_source_eop are generated as -- described in the Avalon_streaming II specification. The at_source_error output is a 2- -- bit signal that complies with the PFC error format (by Kent Orthner). -- -- 00: no error -- 01: missing sop -- 10: missing eop -- 11: unexpected eop -- other types of errors also marked as 11. Any error signal is accompanied -- by at_sink_eop flagged high. -- -- When packet_size is greater than one, this interface expects the main design -- to supply the count of data starting from 1 to the packet_size. When it -- receives the valid flag together with the data_count=1, it starts pumping -- out data by flagging the at_source_sop and at_source_valid both high. -- -- When the data_count=packet_size, the at_source_eop is flagged high together -- with at_source_valid. THERE IS NO ERROR CHECKING FOR THE data_count signal. -- -- If the receiver is not ready to accept any data, the interface flags the source_ -- stall signal high to tell the design to stall. It is the designers -- responsibility to use this signal properly. In some design, the stall signal -- needs to stall all of the design so that no new data can be accepted (as in -- FIR), in other cases (i.e. a FIFO built on a dual port RAM),the input can -- still accept new data although it cannot send any output. -- -- ALTERA Confidential and Proprietary -- Copyright 2006 (c) Altera Corporation -- All rights reserved -- ------------------------------------------------------------------------- ------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; use ieee.numeric_std.all; library altera_mf; use altera_mf.altera_mf_components.all; use work.auk_dspip_math_pkg_hpfir.all; entity auk_dspip_avalon_streaming_source_hpfir is generic( WIDTH_g : integer := 8; -- DATA_PORT_COUNT * DATA_WIDTH DATA_WIDTH : integer := 8; DATA_PORT_COUNT : integer := 1; PACKET_SIZE_g : natural := 2; FIFO_DEPTH_g : natural := 0; HAVE_COUNTER_g : boolean := false; COUNTER_LIMIT_g : natural := 4; --MULTI_CHANNEL_g : boolean := true; USE_PACKETS : integer := 1; --FAMILY_g : string := "Stratix II"; --MEM_TYPE_g : string := "Auto"; ENABLE_BACKPRESSURE_g : boolean := true ); port( clk : in std_logic; reset_n : in std_logic; ----------------- DESIGN SIDE SIGNALS data_in : in std_logic_vector (WIDTH_g-1 downto 0); data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0'); source_valid_ctrl : in std_logic; source_stall : out std_logic; packet_error : in std_logic_vector (1 downto 0); ----------------- AVALON_STREAMING SIDE SIGNALS at_source_ready : in std_logic; at_source_valid : out std_logic; at_source_data : out std_logic_vector (WIDTH_g-1 downto 0); at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0); at_source_error : out std_logic_vector (1 downto 0); at_source_sop : out std_logic; at_source_eop : out std_logic ); -- Declarations end auk_dspip_avalon_streaming_source_hpfir; -- hds interface_end architecture rtl of auk_dspip_avalon_streaming_source_hpfir is --constant FIFO_HINT_c : string := "RAM_BLOCK_TYPE="& MEM_TYPE_g; constant FIFO_DEPTH_c : natural := FIFO_DEPTH_g; constant LOG2PACKET_SIZE_c : natural := log2_ceil_one(PACKET_SIZE_g); constant MIN_DATA_COUNT_g : natural := 2; type STATE_TYPE_t is (start, sop, run1, st_err, end1); --wait1, stall, signal source_state : STATE_TYPE_t; signal source_next_state : STATE_TYPE_t; signal packet_error0 : std_logic; signal at_source_error_int : std_logic_vector(1 downto 0); signal at_source_sop_int : std_logic := '0'; signal at_source_eop_int : std_logic := '0'; signal count_finished : boolean := false; signal count_started : boolean := false; signal at_source_valid_s : std_logic; signal data_valid : std_logic; signal data_out : std_logic_vector(WIDTH_g-1 downto 0); signal fifo_count : std_logic_vector(DATA_PORT_COUNT*log2_ceil(FIFO_DEPTH_g)-1 downto 0); signal fifo_empty : std_logic_vector(DATA_PORT_COUNT-1 downto 0); -- multichan, multiinout signal fifo_alm_empty : std_logic_vector(DATA_PORT_COUNT-1 downto 0); signal fifo_alm_full : std_logic_vector(DATA_PORT_COUNT-1 downto 0); signal fifo_full : std_logic_vector(DATA_PORT_COUNT-1 downto 0); signal clear_fifo : std_logic; signal fifo_rdreq : std_logic; signal fifo_rdreq_d : std_logic; signal fifo_wrreq : std_logic; signal fifo_empty_d : std_logic; signal reset_design_int : std_logic; signal channel_out : std_logic_vector(log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0'); signal fifo_sop_in : std_logic := '0'; signal fifo_eop_in : std_logic := '0'; signal fifo_error_in : std_logic_vector(1 downto 0); signal at_source_sop_s : std_logic := '0'; signal at_source_eop_s : std_logic := '0'; signal at_source_error_s : std_logic_vector(1 downto 0); signal in_ready : std_logic; component altera_avalon_sc_fifo is generic( SYMBOLS_PER_BEAT : integer := 1; BITS_PER_SYMBOL : integer := 8; FIFO_DEPTH : integer := 16; CHANNEL_WIDTH : integer := 2; ERROR_WIDTH : integer := 2; --EMPTY_LATENCY : integer := 0; USE_PACKETS : integer := 0 ); port ( -- inputs: signal clk : IN STD_LOGIC; signal in_channel : IN STD_LOGIC_VECTOR (log2_ceil_one(PACKET_SIZE_g)-1 DOWNTO 0); signal in_data : IN STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0); signal in_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0); signal in_endofpacket : IN STD_LOGIC; signal in_startofpacket : IN STD_LOGIC; signal in_valid : IN STD_LOGIC; signal out_ready : IN STD_LOGIC; signal reset : IN STD_LOGIC; signal in_empty : IN STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0); signal csr_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0); signal csr_write : IN STD_LOGIC; signal csr_read : IN STD_LOGIC; signal csr_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- outputs: signal in_ready : OUT STD_LOGIC; signal out_channel : OUT STD_LOGIC_VECTOR (log2_ceil_one(PACKET_SIZE_g)-1 DOWNTO 0); signal out_data : OUT STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0); signal out_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); signal out_endofpacket : OUT STD_LOGIC; signal out_startofpacket : OUT STD_LOGIC; signal out_valid : OUT STD_LOGIC; signal out_empty : OUT STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0) ); end component altera_avalon_sc_fifo; begin single_channel : if USE_PACKETS = 0 generate at_source_sop_int <= '0'; at_source_eop_int <= '0'; packet_error0 <= packet_error(0); at_source_error_int(1) <= '0'; at_source_error_int(0) <= packet_error0; end generate single_channel; packet_multi : if USE_PACKETS = 1 generate packet_error0 <= packet_error(1) or packet_error(0); counter_no : if HAVE_COUNTER_g = false generate signal data_counter : unsigned(LOG2PACKET_SIZE_c-1 downto 0); begin count_finished <= true when data_counter = to_unsigned(PACKET_SIZE_g-1, LOG2PACKET_SIZE_c) else false; data_counter <= unsigned(data_count); count_started <= true when data_counter = 0 else false; end generate counter_no; counter_yes : if HAVE_COUNTER_g = true generate signal data_counter : unsigned(log2_ceil(COUNTER_LIMIT_g)-1 downto 0); begin count_finished <= true when data_counter = to_unsigned(COUNTER_LIMIT_g-1, log2_ceil(COUNTER_LIMIT_g)) else false; count_started <= true when data_counter = 0 else false; packet_counter : process (clk, reset_n) begin -- process packet_counter if reset_n = '0' then data_counter <= (others => '0'); elsif rising_edge(clk) then if source_state = start and source_next_state = sop then data_counter <= --(others => '0'); -- data_counter +1; elsif data_valid = '1' and at_source_ready = '1' and (data_counter < COUNTER_LIMIT_g-1) then data_counter <= data_counter +1; elsif count_finished = true then data_counter <= (others => '0'); end if; end if; end process packet_counter; end generate counter_yes; source_comb_update : process (--at_source_ready, count_finished, count_started, packet_error, packet_error0, source_state, --at_source_valid_s in_ready, source_valid_ctrl) begin -- process source_comb_update case source_state is when start => if packet_error0 = '1' then source_next_state <= st_err; at_source_error_int <= packet_error; at_source_sop_int <= '0'; at_source_eop_int <= '1'; else at_source_eop_int <= '0'; at_source_error_int <= "00"; if source_valid_ctrl = '1' and count_started = true then --and at_source_ready='1' then source_next_state <= sop; at_source_sop_int <= '1'; else source_next_state <= start; at_source_sop_int <= '0'; end if; end if; when sop => if packet_error0 = '1' then source_next_state <= st_err; at_source_error_int <= packet_error; at_source_sop_int <= '0'; at_source_eop_int <= '1'; else at_source_error_int <= "00"; at_source_eop_int <= '0'; --if source_valid_ctrl = '1' and at_source_ready = '1' and count_finished = false then if source_valid_ctrl = '1' and in_ready = '1' and count_finished = false then if PACKET_SIZE_g > 2 then source_next_state <= run1; else source_next_state <= end1; end if; at_source_sop_int <= '0'; --elsif (at_source_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or elsif (in_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or (source_valid_ctrl = '0' and count_finished = true) then --valid_ctrl_int = '1' and source_next_state <= end1; at_source_error_int <= "00"; at_source_eop_int <= '1'; at_source_sop_int <= '0'; else source_next_state <= sop; at_source_sop_int <= '1'; end if; end if; when run1 => at_source_sop_int <= '0'; if packet_error0 = '1' then source_next_state <= st_err; at_source_error_int <= packet_error; at_source_eop_int <= '1'; else --if (at_source_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or if (in_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or (source_valid_ctrl = '0' and count_finished = true) then --valid_ctrl_int = '1' and source_next_state <= end1; at_source_error_int <= "00"; at_source_eop_int <= '1'; else source_next_state <= run1; at_source_error_int <= "00"; at_source_eop_int <= '0'; end if; end if; when end1 => if packet_error0 = '1' then source_next_state <= st_err; at_source_error_int <= packet_error; at_source_sop_int <= '0'; at_source_eop_int <= '1'; else at_source_error_int <= "00"; --if source_valid_ctrl = '1' and count_started = true and at_source_ready = '1' then if source_valid_ctrl = '1' and count_started = true and in_ready = '1' then source_next_state <= sop; at_source_sop_int <= '1'; at_source_eop_int <= '0'; --elsif source_valid_ctrl = '1' and at_source_ready = '1' then elsif source_valid_ctrl = '1' and in_ready = '1' then source_next_state <= start; at_source_sop_int <= '0'; at_source_eop_int <= '0'; else source_next_state <= end1; at_source_sop_int <= '0'; at_source_eop_int <= '1'; end if; end if; when st_err => at_source_sop_int <= '0'; at_source_eop_int <= '0'; if packet_error0 = '1' then source_next_state <= st_err; at_source_error_int <= packet_error; else source_next_state <= start; at_source_error_int <= "00"; end if; when others => source_next_state <= st_err; at_source_sop_int <= '0'; at_source_eop_int <= '1'; at_source_error_int <= "11"; end case; end process source_comb_update; source_state_update : process (clk, reset_n) begin -- process if reset_n = '0' then source_state <= start; elsif clk'event and clk = '1' then source_state <= source_next_state; end if; end process source_state_update; end generate packet_multi; at_source_sop <= at_source_sop_s; at_source_eop <= at_source_eop_s; at_source_error <= at_source_error_s; channel_info_exists : if USE_PACKETS = 1 generate at_source_channel <= channel_out; end generate channel_info_exists; no_channel_info : if USE_PACKETS = 0 generate at_source_channel <= (others => '0'); end generate no_channel_info; at_source_data <= data_out; at_source_valid <= data_valid; backpressure_support: if ENABLE_BACKPRESSURE_g = true generate reset_design_int <= not reset_n; --source_stall <= not(in_ready); source_stall <= not(at_source_ready); fifo_sop_in <= '0' when USE_PACKETS = 0 else at_source_sop_int; fifo_eop_in <= '0' when USE_PACKETS = 0 else at_source_eop_int; fifo_error_in <= "00" when USE_PACKETS = 0 else at_source_error_int; scfifo : altera_avalon_sc_fifo generic map ( SYMBOLS_PER_BEAT => DATA_PORT_COUNT, BITS_PER_SYMBOL => DATA_WIDTH, FIFO_DEPTH => FIFO_DEPTH_c, CHANNEL_WIDTH => log2_ceil_one(PACKET_SIZE_g), ERROR_WIDTH => 2, --EMPTY_LATENCY => 1, USE_PACKETS => USE_PACKETS) port map ( clk => clk, reset => reset_design_int, in_ready => in_ready, --in_data => fifo_datain(((0*DATA_WIDTH)+DATA_WIDTH-1) downto (0*DATA_WIDTH)), in_data => data_in, in_valid => source_valid_ctrl, in_error => fifo_error_in, in_channel => data_count, in_startofpacket => fifo_sop_in, in_endofpacket => fifo_eop_in, in_empty => (others => '0'), csr_address => (others => '0'), csr_write => '0', csr_read => '0', csr_writedata => (others => '0'), out_ready => at_source_ready, --out_data => fifo_dataout(((0*DATA_WIDTH)+DATA_WIDTH-1) downto (0*DATA_WIDTH)), out_data => data_out, out_valid => data_valid, out_error => at_source_error_s, out_channel => channel_out, out_startofpacket => at_source_sop_s, out_endofpacket => at_source_eop_s, out_empty => open); end generate backpressure_support; backpressure_no_support: if ENABLE_BACKPRESSURE_g = false generate in_ready <= '1'; source_stall <= '0'; output_registers : process (clk, reset_n) begin if reset_n = '0' then channel_out <= (others => '0'); data_out <= (others => '0'); data_valid <= '0'; at_source_error_s <= "00"; at_source_sop_s <= '0'; at_source_eop_s <= '0'; elsif rising_edge(clk) then channel_out <= data_count; data_out <= data_in; data_valid <= source_valid_ctrl; at_source_error_s <= at_source_error_int; at_source_sop_s <= at_source_sop_int; at_source_eop_s <= at_source_eop_int; end if; end process output_registers; end generate backpressure_no_support; end rtl;
gpl-2.0
istankovic/geda-gaf
gnetlist/examples/vams/vhdl/basic-vhdl/sp_diode.vhdl
15
539
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY SP_DIODE IS GENERIC ( RS : REAL := 1.0; VT : REAL := 25.85e-3; AF : REAL := 1.0; KF : REAL := 0.0; PT : REAL := 3.0; EG : REAL := 1.11; M : REAL := 0.5; PB : REAL := 1.0; TT : REAL := 0.0; CJ0 : REAL := 0.0; N : REAL := 1.0; ISS : REAL := 10.0e-14 ); PORT ( terminal KATHODE : electrical; terminal ANODE : electrical ); END ENTITY SP_DIODE;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/OpenMAC_DMAFifo_Altera.vhd
3
6936
------------------------------------------------------------------------------------------------------------------------ -- OpenMAC DMA FIFO -- -- Copyright (C) 2011 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2011-06-06 V0.01 added generic and export fifo word vector -- 2011-08-03 V0.10 changed to dual clocked fifo (DCFIFO) ------------------------------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library altera_mf; use altera_mf.all; entity openMAC_DMAfifo is generic ( fifo_data_width_g : natural := 16; fifo_word_size_g : natural := 32; fifo_word_size_log2_g : natural := 5 ); port ( aclr : in std_logic; rd_clk : in std_logic; wr_clk : in std_logic; --read port rd_req : in std_logic; rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0); rd_empty : out std_logic; rd_full : out std_logic; rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0); --write port wr_req : in std_logic; wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0); wr_empty : out std_logic; wr_full : out std_logic; wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0) ); end openmac_dmafifo; architecture struct of openMAC_DMAfifo is component dcfifo generic ( lpm_width : natural; --width of data and q ports (input/output) lpm_widthu : natural; --width of wrusedw and rdusedw lpm_numwords : natural; --depth of fifo lpm_showahead : string; --fifo showahead off/on (rdreq works as req/ack) lpm_type : string; --SCFIFO or DCFIFO (single/dual clocked) overflow_checking : string; --protection circuit for wrreq underflow_checking : string; --protection circuit for rdreq rdsync_delaypipe : natural; --number of sync from wr to rd wrsync_delaypipe : natural; --number of sync from rd to wr use_eab : string; --construct fifo as LE/RAM (off/on) write_aclr_synch : string; --sync async. clear to wr clk (avoids race cond.) intended_device_family : string --specifies the intended device for functional simulation ); port ( wrclk : in std_logic; --clock for wr port rdclk : in std_logic; --clock for rd port data : in std_logic_vector(fifo_data_width_g-1 downto 0); --data to be written wrreq : in std_logic; --write request rdreq : in std_logic; --read request aclr : in std_logic; --asynchronous clear fifo q : out std_logic_vector(fifo_data_width_g-1 downto 0); --read data wrfull : out std_logic; --fifo is full on wr port rdfull : out std_logic; --fifo is full on rd port wrempty : out std_logic; --fifo is empty on wr port rdempty : out std_logic; --fifo is empty on rd port wrusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0); --number of words stored on wr port rdusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0) --number of words stored on rd port ); end component; constant fifo_useRam_c : string := "ON"; constant fifo_words_c : natural := fifo_word_size_g; --e.g. 32 constant fifo_usedw_c : natural := fifo_word_size_log2_g; --e.g. log2(32) = 5 --constant fifo_rd_usedw_c : natural := 5; --constant fifo_wr_usedw_c : natural := 5; constant fifo_data_width_c : natural := fifo_data_width_g; --constant fifo_rd_data_width_c : natural := 16; --constant fifo_wr_data_width_c : natural := 16; begin dcfifo_inst : dcfifo generic map ( lpm_width => fifo_data_width_c, --width of data and q ports (input/output) lpm_widthu => fifo_usedw_c, --width of wrusedw and rdusedw lpm_numwords => fifo_words_c, --depth of fifo lpm_showahead => "OFF", --fifo showahead off/on (rdreq works as req/ack) lpm_type => "DCFIFO", --SCFIFO or DCFIFO (single/dual clocked) overflow_checking => "ON", --protection circuit for wrreq underflow_checking => "ON", --protection circuit for rdreq rdsync_delaypipe => 4, --number of sync from wr to rd wrsync_delaypipe => 4, --number of sync from rd to wr use_eab => fifo_useRam_c, --construct fifo as LE/RAM (off/on) write_aclr_synch => "ON", --sync async. clear to wr clk (avoids race cond.) intended_device_family => "Cyclone IV" --specifies the intended device for functional simulation ) port map ( wrclk => wr_clk, --clock for wr port rdclk => rd_clk, --clock for rd port data => wr_data, --data to be written wrreq => wr_req, --write request rdreq => rd_req, --read request aclr => aclr, --asynchronous clear fifo q => rd_data, --read data wrfull => wr_full, --fifo is full on wr port rdfull => rd_full, --fifo is full on rd port wrempty => wr_empty, --fifo is empty on wr port rdempty => rd_empty, --fifo is empty on rd port wrusedw => wr_usedw, --number of words stored on wr port rdusedw => rd_usedw --number of words stored on rd port ); end struct;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/altera_nios2/EBV_DBC3C40/design_nios2_directIO/POWERLINK/src/pdi_controlStatusReg.vhd
5
20582
------------------------------------------------------------------------------------------------------------------------ -- Process Data Interface (PDI) status control register -- -- Copyright (C) 2011 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd -- 2011-11-21 V0.02 zelenkaj added time synchronization feature -- added 12 bytes to DPR as reserved -- 2011-11-29 V0.03 zelenkaj led and event is optional -- 2011-12-20 V0.04 zelenkaj changed 2xbuf switch source to ap irq -- 2012-01-26 V0.05 zelenkaj en-/disable double buffer with genTimeSync_g ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity pdiControlStatusReg is generic ( bIsPcp : boolean := true; iAddrWidth_g : integer := 8; iBaseDpr_g : integer := 16#4#; --base address (in external mapping) of content in dpr iSpanDpr_g : integer := 12; --span of content in dpr iBaseMap2_g : integer := 0; --base address in dpr iDprAddrWidth_g : integer := 11; iRpdos_g : integer := 3; genLedGadget_g : boolean := false; genTimeSync_g : boolean := false; genEvent_g : boolean := false; --register content ---constant values magicNumber : std_Logic_vector(31 downto 0) := (others => '0'); pdiRev : std_logic_vector(15 downto 0) := (others => '0'); tPdoBuffer : std_logic_vector(31 downto 0) := (others => '0'); rPdo0Buffer : std_logic_vector(31 downto 0) := (others => '0'); rPdo1Buffer : std_logic_vector(31 downto 0) := (others => '0'); rPdo2Buffer : std_logic_vector(31 downto 0) := (others => '0'); asyncBuffer1Tx : std_logic_vector(31 downto 0) := (others => '0'); asyncBuffer1Rx : std_logic_vector(31 downto 0) := (others => '0'); asyncBuffer2Tx : std_logic_vector(31 downto 0) := (others => '0'); asyncBuffer2Rx : std_logic_vector(31 downto 0) := (others => '0') ); port ( --memory mapped interface clk : in std_logic; rst : in std_logic; sel : in std_logic; wr : in std_logic; rd : in std_logic; addr : in std_logic_vector(iAddrWidth_g-1 downto 0); be : in std_logic_vector(3 downto 0); din : in std_logic_vector(31 downto 0); dout : out std_logic_vector(31 downto 0); --register content ---virtual buffer control signals rpdo_change_tog : in std_logic_vector(2 downto 0); --change buffer from hw acc tpdo_change_tog : in std_logic; --change buffer from hw acc pdoVirtualBufferSel : in std_logic_vector(31 downto 0); --for debugging purpose from SW side --TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK tPdoTrigger : out std_logic; --TPDO virtual buffer change trigger rPdoTrigger : out std_logic_vector(2 downto 0); --RPDOs virtual buffer change triggers ---is used for Irq Generation and should be mapped to apIrqGen apIrqControlOut : out std_logic_vector(15 downto 0); apIrqControlIn : in std_logic_vector(15 downto 0); ---event registers eventAckIn : in std_logic_vector(15 downto 0); eventAckOut : out std_logic_vector(15 downto 0); ---async irq (by event) asyncIrqCtrlIn : In std_logic_vector(15 downto 0); --Ap only asyncIrqCtrlOut : out std_logic_vector(15 downto 0); --Ap only ---led stuff ledCnfgIn : in std_logic_vector(15 downto 0); ledCnfgOut : out std_logic_vector(15 downto 0); ledCtrlIn : in std_logic_vector(15 downto 0); ledCtrlOut : out std_logic_vector(15 downto 0); ---time synchronization doubleBufSel_out : out std_logic; --Ap only doubleBufSel_in : in std_logic := '0'; --Pcp only timeSyncIrq : in std_logic; --SYNC IRQ to Ap (Ap only) --dpr interface (from PCP/AP to DPR) dprAddrOff : out std_logic_vector(iDprAddrWidth_g downto 0); dprDin : out std_logic_vector(31 downto 0); dprDout : in std_logic_vector(31 downto 0); dprBe : out std_logic_vector(3 downto 0); dprWr : out std_logic ); end entity pdiControlStatusReg; architecture rtl of pdiControlStatusReg is constant c_num_dbuf_dpr : integer := 4; --number of dbuf in DPR (per buffer 4 byte) signal selDpr : std_logic; --if '1' get/write content from/to dpr signal nonDprDout : std_logic_vector(31 downto 0); signal addrRes : std_logic_vector(dprAddrOff'range); --signal apIrqValue_s : std_logic_vector(31 downto 0); --pcp only signal virtualBufferSelectTpdo : std_logic_vector(15 downto 0); signal virtualBufferSelectRpdo0 : std_logic_vector(15 downto 0); signal virtualBufferSelectRpdo1 : std_logic_vector(15 downto 0); signal virtualBufferSelectRpdo2 : std_logic_vector(15 downto 0); --edge detection signal rpdo_change_tog_l : std_logic_vector(2 downto 0); --change buffer from hw acc signal tpdo_change_tog_l : std_logic; --change buffer from hw acc --time synchronization signal timeSyncIrq_rising : std_logic; ---select signals signal sel_time_after_sync : std_logic; signal sel_double_buffer : std_logic; ----double buffered content signal sel_relative_time_l : std_logic; signal sel_relative_time_h : std_logic; signal sel_nettime_nsec : std_logic; signal sel_nettime_sec : std_logic; signal sel_time_sync_regs : std_logic; ---time after sync counter constant c_time_after_sync_cnt_size : integer := 16; --revise code if changed signal time_after_sync_cnt : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0); signal time_after_sync_cnt_latch : std_logic_vector(c_time_after_sync_cnt_size/2-1 downto 0); signal time_after_sync_cnt_next : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0); signal time_after_sync_cnt_out : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0) := (others => '0'); constant time_after_sync_res : std_logic_vector(32-c_time_after_sync_cnt_size-1 downto 0) := (others => '0'); ---address offsets constant c_addr_time_after_sync : integer := 16#50#; constant c_addr_relative_time_l : integer := 16#40#; constant c_addr_relative_time_h : integer := 16#44#; constant c_addr_nettime_nsec : integer := 16#48#; constant c_addr_nettime_sec : integer := 16#4C#; begin --map to 16bit register --TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK virtualBufferSelectRpdo0 <= pdoVirtualBufferSel( 7 downto 0) & pdoVirtualBufferSel( 7 downto 0); virtualBufferSelectRpdo1 <= pdoVirtualBufferSel(15 downto 8) & pdoVirtualBufferSel(15 downto 8); virtualBufferSelectRpdo2 <= pdoVirtualBufferSel(23 downto 16) & pdoVirtualBufferSel(23 downto 16); virtualBufferSelectTpdo <= pdoVirtualBufferSel(31 downto 24) & pdoVirtualBufferSel(31 downto 24); --generate dpr select signal selDpr <= sel when (conv_integer(addr) >= iBaseDpr_g AND conv_integer(addr) < iBaseDpr_g + iSpanDpr_g - c_num_dbuf_dpr) else '0'; --time sync select content if the double buffer has to be generated (genTimeSync_g) sel_time_after_sync <= '1' when conv_integer(addr)*4 = c_addr_time_after_sync and genTimeSync_g else '0'; sel_relative_time_l <= '1' when conv_integer(addr)*4 = c_addr_relative_time_l and genTimeSync_g else '0'; sel_relative_time_h <= '1' when conv_integer(addr)*4 = c_addr_relative_time_h and genTimeSync_g else '0'; sel_nettime_nsec <= '1' when conv_integer(addr)*4 = c_addr_nettime_nsec and genTimeSync_g else '0'; sel_nettime_sec <= '1' when conv_integer(addr)*4 = c_addr_nettime_sec and genTimeSync_g else '0'; ---or them up... sel_time_sync_regs <= sel_relative_time_l or sel_relative_time_h or sel_nettime_nsec or sel_nettime_sec; genTimeSync : if genTimeSync_g generate begin --we need a rising edge to do magic apSyncIrqEdgeDet : entity work.edgedet port map ( din => timeSyncIrq, rising => timeSyncIrq_rising, falling => open, any => open, clk => clk, rst => rst ); genDoubleBufPcp : if bIsPcp generate begin --take the other buffer (Ap has already inverted, see lines below!) sel_double_buffer <= doubleBufSel_in; --Pcp has no timer time_after_sync_cnt_out <= (others => '0'); end generate; genDoubleBufAp : if not bIsPcp generate begin --output the inverted to the PCP doubleBufSel_out <= not sel_double_buffer; --switch the double buffer with the sync irq, rising edge of course process(clk, rst) begin if rst = '1' then sel_double_buffer <= '0'; elsif rising_edge(clk) then if timeSyncIrq_rising = '1' then --rising edge sel_double_buffer <= not sel_double_buffer; end if; end if; end process; end generate; genTimeAfterSyncCnt : if not bIsPcp generate constant ZEROS : std_logic_vector(time_after_sync_cnt'range) := (others => '0'); constant ONES : std_logic_vector(time_after_sync_cnt'range) := (others => '1'); begin --TIME_AFTER_SYNC counter process(clk, rst) begin if rst = '1' then time_after_sync_cnt <= (others => '0'); elsif clk = '1' and clk'event then time_after_sync_cnt <= time_after_sync_cnt_next; --there are some kind of interfaces that read only the half of a word... -- so store the half that is not read -- and forward it to the Ap at the next read if sel = '1' and sel_time_after_sync = '1' and be = "0001" then time_after_sync_cnt_latch <= time_after_sync_cnt(c_time_after_sync_cnt_size-1 downto c_time_after_sync_cnt_size/2); end if; end if; end process; time_after_sync_cnt_next <= ZEROS when timeSyncIrq_rising = '1' else --rising edge time_after_sync_cnt when time_after_sync_cnt = ONES else --saturate time_after_sync_cnt + 1; --count for your life! time_after_sync_cnt_out <= time_after_sync_cnt when be(3 downto 2) = "11" or be(1 downto 0) = "11" else time_after_sync_cnt_latch & time_after_sync_cnt(time_after_sync_cnt_latch'range); end generate; end generate; --assign content depending on selDpr dprDin <= din; dprBe <= be; dprWr <= wr when selDpr = '1' else '0'; dout <= dprDout when selDpr = '1' else nonDprDout; dprAddrOff <= addrRes + 4 when sel_double_buffer = '1' and sel_time_sync_regs = '1' and genTimeSync_g else --select 2nd double buffer addrRes; --select 1st double buffer or other content --address conversion ---map external address mapping into dpr addrRes <= conv_std_logic_vector(iBaseMap2_g - iBaseDpr_g, addrRes'length); --non dpr read with conv_integer(addr)*4 select nonDprDout <= magicNumber when 16#00#, (x"0000" & pdiRev) when 16#04#, --STORED IN DPR when 16#08#, --STORED IN DPR when 16#0C#, --STORED IN DPR when 16#10#, --STORED IN DPR when 16#14#, --STORED IN DPR when 16#18#, --STORED IN DPR when 16#1C#, --STORED IN DPR when 16#20#, --STORED IN DPR when 16#24#, --STORED IN DPR when 16#28#, --STORED IN DPR when 16#2C#, --STORED IN DPR when 16#30#, --STORED IN DPR when 16#34#, --RESERVED --STORED IN DPR when 16#38#, --RESERVED --STORED IN DPR when 16#3C#, --RESERVED --STORED IN DPR x2 when c_addr_relative_time_l, --RELATIVE_TIME low --STORED IN DPR x2 when c_addr_relative_time_h, --RELATIVE_TIME high --STORED IN DPR x2 when c_addr_nettime_nsec, --NETTIME nsec --STORED IN DPR x2 when c_addr_nettime_sec, --NETTIME sec (time_after_sync_res & time_after_sync_cnt_out) when c_addr_time_after_sync, --RES / TIME_AFTER_SYNC (eventAckIn & asyncIrqCtrlIn) when 16#54#, tPdoBuffer when 16#58#, rPdo0Buffer when 16#5C#, rPdo1Buffer when 16#60#, rPdo2Buffer when 16#64#, asyncBuffer1Tx when 16#68#, asyncBuffer1Rx when 16#6C#, asyncBuffer2Tx when 16#70#, asyncBuffer2Rx when 16#74#, --RESERVED when 16#78#, --RESERVED when 16#7C#, (virtualBufferSelectRpdo0 & virtualBufferSelectTpdo) when 16#80#, (virtualBufferSelectRpdo2 & virtualBufferSelectRpdo1) when 16#84#, (x"0000" & apIrqControlIn) when 16#88#, --RESERVED when 16#8C#, --RESERVED when 16#90#, (ledCnfgIn & ledCtrlIn) when 16#94#, (others => '0') when others; --ignored values asyncIrqCtrlOut(14 downto 1) <= (others => '0'); eventAckOut(15 downto 8) <= (others => '0'); --non dpr write process(clk, rst) begin if rst = '1' then tPdoTrigger <= '0'; rPdoTrigger <= (others => '0'); --apIrqControlOut <= (others => '0'); if bIsPcp = true then apIrqControlOut(7) <= '0'; apIrqControlOut(6) <= '0'; end if; if bIsPcp = false then apIrqControlOut(15) <= '0'; end if; apIrqControlOut(0) <= '0'; if genEvent_g then if bIsPcp = false then asyncIrqCtrlOut(0) <= '0'; asyncIrqCtrlOut(15) <= '0'; end if; eventAckOut(7 downto 0) <= (others => '0'); end if; if genLedGadget_g then ledCtrlOut(7 downto 0) <= (others => '0'); ledCnfgOut(7 downto 0) <= (others => '0'); end if; if bIsPcp then rpdo_change_tog_l <= (others => '0'); tpdo_change_tog_l <= '0'; end if; elsif clk = '1' and clk'event then --default assignments tPdoTrigger <= '0'; rPdoTrigger <= (others => '0'); apIrqControlOut(0) <= '0'; --PCP: set pulse // AP: ack pulse if genEvent_g then eventAckOut(7 downto 0) <= (others => '0'); --PCP: set pulse // AP: ack pulse end if; if bIsPcp then --shift register for edge det rpdo_change_tog_l <= rpdo_change_tog; tpdo_change_tog_l <= tpdo_change_tog; --edge detection ---tpdo if tpdo_change_tog_l /= tpdo_change_tog then tPdoTrigger <= '1'; end if; ---rpdo for i in rpdo_change_tog'range loop if rpdo_change_tog_l(i) /= rpdo_change_tog(i) then rPdoTrigger(i) <= '1'; end if; end loop; end if; if wr = '1' and sel = '1' and selDpr = '0' then case conv_integer(addr)*4 is when 16#00# => --RO when 16#04# => --RO when 16#08# => --STORED IN DPR when 16#0C# => --STORED IN DPR when 16#10# => --STORED IN DPR when 16#14# => --STORED IN DPR when 16#18# => --STORED IN DPR when 16#1C# => --STORED IN DPR when 16#20# => --STORED IN DPR when 16#24# => --STORED IN DPR when 16#28# => --STORED IN DPR when 16#2C# => --STORED IN DPR when 16#30# => --STORED IN DPR when 16#34# => --STORED IN DPR RESERVED when 16#38# => --STORED IN DPR RESERVED when 16#3C# => --STORED IN DPR RESERVED when 16#40# => --STORED IN DPR x2 when 16#44# => --STORED IN DPR x2 when 16#48# => --STORED IN DPR x2 when 16#4C# => --STORED IN DPR x2 when c_addr_time_after_sync => --RO when 16#54# => --AP ONLY if genEvent_g then if be(0) = '1' and bIsPcp = false then --asyncIrqCtrlOut(7 downto 0) <= din(7 downto 0); asyncIrqCtrlOut(0) <= din(0); --rest is ignored end if; if be(1) = '1' and bIsPcp = false then --asyncIrqCtrlOut(15 downto 8) <= din(15 downto 8); asyncIrqCtrlOut(15) <= din(15); --rest is ignored end if; if be(2) = '1' then eventAckOut(7 downto 0) <= din(23 downto 16); end if; --ignore higher byte of event ack -- if be(3) = '1' then -- eventAckOut(15 downto 8) <= din(31 downto 24); -- end if; end if; when 16#58# => --RO when 16#5C# => --RO when 16#60# => --RO when 16#64# => --RO when 16#68# => --RO when 16#6C# => --RO when 16#70# => --RO when 16#74# => --RO when 16#78# => --RESERVED when 16#7C# => --RESERVED when 16#80# => if be(0) = '1' then tPdoTrigger <= '1'; end if; if be(1) = '1' then tPdoTrigger <= '1'; end if; if be(2) = '1' then rPdoTrigger(0) <= '1'; end if; if be(3) = '1' then rPdoTrigger(0) <= '1'; end if; when 16#84# => if be(0) = '1' then rPdoTrigger(1) <= '1'; end if; if be(1) = '1' then rPdoTrigger(1) <= '1'; end if; if be(2) = '1' then rPdoTrigger(2) <= '1'; end if; if be(3) = '1' then rPdoTrigger(2) <= '1'; end if; when 16#88# => if be(0) = '1' then --apIrqControlOut(7 downto 0) <= din(7 downto 0); if bIsPcp = true then apIrqControlOut(7) <= din(7); apIrqControlOut(6) <= din(6); end if; apIrqControlOut(0) <= din(0); end if; if be(1) = '1' then --apIrqControlOut(15 downto 8) <= din(15 downto 8); if bIsPcp = false then apIrqControlOut(15) <= din(15); end if; end if; when 16#8C# => --RESERVED when 16#90# => --RESERVED when 16#94# => if genLedGadget_g then if be(0) = '1' then ledCtrlOut(7 downto 0) <= din(7 downto 0); end if; if be(1) = '1' then ledCtrlOut(15 downto 8) <= din(15 downto 8); end if; if be(2) = '1' then ledCnfgOut(7 downto 0) <= din(23 downto 16); end if; if be(3) = '1' then ledCnfgOut(15 downto 8) <= din(31 downto 24); end if; end if; when others => end case; end if; end if; end process; end architecture rtl;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/altera_nios2/EBV_DBC3C40/design_nios2_directIO/POWERLINK/src/pdi_simpleReg.vhd
5
3879
------------------------------------------------------------------------------------------------------------------------ -- Process Data Interface (PDI) simple register -- -- Copyright (C) 2011 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity pdiSimpleReg is generic ( iAddrWidth_g : integer := 10; --only use effective addr range (e.g. 2kB leads to iAddrWidth_g := 10) iBaseMap2_g : integer := 0; --base address in dpr iDprAddrWidth_g : integer := 12 ); port ( --memory mapped interface sel : in std_logic; wr : in std_logic; rd : in std_logic; addr : in std_logic_vector(iAddrWidth_g-1 downto 0); be : in std_logic_vector(3 downto 0); din : in std_logic_vector(31 downto 0); dout : out std_logic_vector(31 downto 0); --dpr interface (from PCP/AP to DPR) dprAddrOff : out std_logic_vector(iDprAddrWidth_g downto 0); dprDin : out std_logic_vector(31 downto 0); dprDout : in std_logic_vector(31 downto 0); dprBe : out std_logic_vector(3 downto 0); dprWr : out std_logic ); end entity pdiSimpleReg; architecture rtl of pdiSimpleReg is signal addrRes : std_logic_vector(dprAddrOff'range); begin --assign content to dpr dprDin <= din; dprBe <= be; dprWr <= wr when sel = '1' else '0'; dout <= dprDout when sel = '1' else (others => '0'); dprAddrOff <= addrRes when sel = '1' else (others => '0'); --address conversion ---map external address mapping into dpr addrRes <= '0' & conv_std_logic_vector(iBaseMap2_g, addrRes'length - 1); end architecture rtl;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/lib/edgedet.vhd
5
3130
------------------------------------------------------------------------------- -- -- Title : sync -- Design : plk_mn -- ------------------------------------------------------------------------------- -- -- File : edgedet.vhd -- Generated : Wed Jul 27 09:33:40 2011 -- From : interface description file -- By : Itf2Vhdl ver. 1.22 -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- 2011-07-26 V0.01 zelenkaj First version -- 2011-11-29 V0.02 zelenkaj omitted out reset -- 2011-12-12 V0.03 zelenkaj reduced to one FF -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY edgeDet IS PORT ( din : IN STD_LOGIC; rising : OUT STD_LOGIC; falling : OUT STD_LOGIC; any : OUT STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC ); END ENTITY edgeDet; ARCHITECTURE rtl OF edgeDet IS signal RegDin : std_logic; BEGIN any <= RegDin xor din; falling <= RegDin and not din; rising <= not RegDin and din; process(clk) begin if rising_edge(clk) then RegDin <= din after 10 ns; end if; end process; END ARCHITECTURE rtl;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/lib/edgedet.vhd
5
3130
------------------------------------------------------------------------------- -- -- Title : sync -- Design : plk_mn -- ------------------------------------------------------------------------------- -- -- File : edgedet.vhd -- Generated : Wed Jul 27 09:33:40 2011 -- From : interface description file -- By : Itf2Vhdl ver. 1.22 -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- 2011-07-26 V0.01 zelenkaj First version -- 2011-11-29 V0.02 zelenkaj omitted out reset -- 2011-12-12 V0.03 zelenkaj reduced to one FF -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY edgeDet IS PORT ( din : IN STD_LOGIC; rising : OUT STD_LOGIC; falling : OUT STD_LOGIC; any : OUT STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC ); END ENTITY edgeDet; ARCHITECTURE rtl OF edgeDet IS signal RegDin : std_logic; BEGIN any <= RegDin xor din; falling <= RegDin and not din; rising <= not RegDin and din; process(clk) begin if rising_edge(clk) then RegDin <= din after 10 ns; end if; end process; END ARCHITECTURE rtl;
gpl-2.0
dummylink/plnk_fpga-stack
Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/OpenMAC_DPR_Altera.vhd
3
9712
------------------------------------------------------------------------------------------------------------------------ -- OpenMAC - DPR for Altera FPGA -- -- Copyright (C) 2009 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2009-08-07 V0.01 Converted to official version. -- 2010-05-03 V0.02 added packet buffer dpr -- 2011-12-22 V0.03 added initialization files -- removed dpr_8_8 -- 2012-01-04 V0.04 replaced initialization files with mif ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------- -- 16 / 16 DPR -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity Dpr_16_16 is generic(Simulate : in boolean); port ( ClkA, ClkB : in std_logic; WeA, WeB : in std_logic := '0'; EnA, EnB : in std_logic := '1'; BeA : in std_logic_vector ( 1 downto 0) := "11"; AddrA : in std_logic_vector ( 7 downto 0); DiA : in std_logic_vector (15 downto 0) := (others => '0'); DoA : out std_logic_vector(15 downto 0); BeB : in std_logic_vector ( 1 downto 0) := "11"; AddrB : in std_logic_vector ( 7 downto 0); DiB : in std_logic_vector (15 downto 0) := (others => '0'); DoB : out std_logic_vector(15 downto 0) ); end Dpr_16_16; architecture struct of Dpr_16_16 is begin Ram: COMPONENT altsyncram GENERIC MAP ( OPERATION_MODE => "BIDIR_DUAL_PORT", INIT_FILE => "mif/dpr_16_16.mif", WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2, WIDTH_B => 16, WIDTHAD_B => 8, NUMWORDS_B => 256, WIDTH_BYTEENA_B => 2 ) PORT MAP( clock0 => ClkA, clock1 => ClkB, wren_a => WeA, wren_b => WeB, clocken0 => EnA, clocken1 => EnB, byteena_a => BeA, byteena_b => BeB, address_a => AddrA, address_b => AddrB, data_a => DiA, data_b => DiB, q_a => DoA, q_b => DoB ); end struct; ------------------------------------------------------------------------------- -- 16 / 32 DPR -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity Dpr_16_32 is generic(Simulate : in boolean); port ( ClkA, ClkB : in std_logic; WeA : in std_logic := '0'; EnA, EnB : in std_logic := '1'; AddrA : in std_logic_vector ( 7 downto 0); DiA : in std_logic_vector (15 downto 0) := (others => '0'); BeA : in std_logic_vector ( 1 downto 0) := "11"; AddrB : in std_logic_vector ( 6 downto 0); DoB : out std_logic_vector(31 downto 0) ); end Dpr_16_32; architecture struct of Dpr_16_32 is begin Ram: COMPONENT altsyncram GENERIC MAP ( OPERATION_MODE => "DUAL_PORT", INIT_FILE => "mif/dpr_16_32.mif", WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2, WIDTH_B => 32, WIDTHAD_B => 7, NUMWORDS_B => 128 ) PORT MAP( clock0 => ClkA, clock1 => ClkB, wren_a => WeA, clocken0 => EnA, clocken1 => EnB, byteena_a => BeA, address_a => AddrA, address_b => AddrB, data_a => DiA, q_b => DoB ); end struct; ------------------------------------------------------------------------------- -- Packet buffer -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; USE ieee.math_real.log2; USE ieee.math_real.ceil; LIBRARY altera_mf; USE altera_mf.all; ENTITY OpenMAC_DPRpackets IS GENERIC ( memSizeLOG2_g : integer := 10; memSize_g : integer := 1024 ); PORT ( address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0); address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0); byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1'); byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1'); clock_a : IN STD_LOGIC := '1'; clock_b : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); rden_a : IN STD_LOGIC := '1'; rden_b : IN STD_LOGIC := '1'; wren_a : IN STD_LOGIC := '0'; wren_b : IN STD_LOGIC := '0'; q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); END OpenMAC_DPRpackets; ARCHITECTURE SYN OF openmac_dprpackets IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); COMPONENT altsyncram GENERIC ( address_reg_b : STRING; byteena_reg_b : STRING; byte_size : NATURAL; clock_enable_input_a : STRING; clock_enable_input_b : STRING; clock_enable_output_a : STRING; clock_enable_output_b : STRING; indata_reg_b : STRING; intended_device_family : STRING; lpm_type : STRING; numwords_a : NATURAL; numwords_b : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_aclr_b : STRING; outdata_reg_a : STRING; outdata_reg_b : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; read_during_write_mode_port_b : STRING; widthad_a : NATURAL; widthad_b : NATURAL; width_a : NATURAL; width_b : NATURAL; width_byteena_a : NATURAL; width_byteena_b : NATURAL; wrcontrol_wraddress_reg_b : STRING ); PORT ( wren_a : IN STD_LOGIC ; clock0 : IN STD_LOGIC ; wren_b : IN STD_LOGIC ; clock1 : IN STD_LOGIC ; byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0); byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0); address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0); rden_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); rden_b : IN STD_LOGIC ; q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ); END COMPONENT; BEGIN q_a <= sub_wire0(15 DOWNTO 0); q_b <= sub_wire1(31 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_reg_b => "CLOCK1", byteena_reg_b => "CLOCK1", byte_size => 8, clock_enable_input_a => "BYPASS", clock_enable_input_b => "BYPASS", clock_enable_output_a => "BYPASS", clock_enable_output_b => "BYPASS", indata_reg_b => "CLOCK1", intended_device_family => "Cyclone III", lpm_type => "altsyncram", numwords_a => memSize_g/2, numwords_b => memSize_g/4, operation_mode => "BIDIR_DUAL_PORT", outdata_aclr_a => "NONE", outdata_aclr_b => "NONE", outdata_reg_a => "CLOCK0", outdata_reg_b => "CLOCK1", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", widthad_a => memSizeLOG2_g-1, widthad_b => memSizeLOG2_g-2, width_a => 16, width_b => 32, width_byteena_a => 2, width_byteena_b => 4, wrcontrol_wraddress_reg_b => "CLOCK1" ) PORT MAP ( wren_a => wren_a, clock0 => clock_a, wren_b => wren_b, clock1 => clock_b, byteena_a => byteena_a, byteena_b => byteena_b, address_a => address_a, address_b => address_b, rden_a => rden_a, rden_b => rden_b, data_a => data_a, data_b => data_b, q_a => sub_wire0, q_b => sub_wire1 ); END SYN;
gpl-2.0
kokx/exuberant-ctags
Test/bug2374109.vhd
98
196
function Pow2( N, Exp : integer ) return mylib.myinteger is Variable Result : integer := 1; begin for i in 1 to Exp loop Result := Result * N; end loop; return( Result ); end Pow;
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_dre_mux4_1_x_n.vhd
18
5491
------------------------------------------------------------------------------- -- axi_datamover_dre_mux4_1_x_n.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_dre_mux4_1_x_n.vhd -- -- Description: -- -- This VHDL file provides a 4 to 1 by N bits wide mux for the AXI Data Realignment -- Engine (DRE). -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.STD_LOGIC_UNSIGNED.all; use ieee.std_logic_arith.all; ------------------------------------------------------------------------------- -- Start 4 to 1 xN Mux ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- Entity axi_datamover_dre_mux4_1_x_n is generic ( C_WIDTH : Integer := 8 -- Sets the bit width of the 4x Mux slice ); port ( Sel : In std_logic_vector(1 downto 0); -- Mux select control I0 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 0 input I1 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 1 input I2 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 2 input I3 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 3 input Y : Out std_logic_vector(C_WIDTH-1 downto 0) -- Mux output value ); end entity axi_datamover_dre_mux4_1_x_n; -- Architecture implementation of axi_datamover_dre_mux4_1_x_n is begin ------------------------------------------------------------- -- Combinational Process -- -- Label: SELECT4_1 -- -- Process Description: -- This process implements an 4 to 1 mux. -- ------------------------------------------------------------- SELECT4_1 : process (Sel, I0, I1, I2, I3) begin case Sel is when "00" => Y <= I0; when "01" => Y <= I1; when "10" => Y <= I2; when "11" => Y <= I3; when others => Y <= I0; end case; end process SELECT4_1; end implementation; -- axi_datamover_dre_mux4_1_x_n ------------------------------------------------------------------------------- -- End 4 to 1 xN Mux -------------------------------------------------------------------------------
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_vid_cdc.vhd
2
33659
------------------------------------------------------------------------------- -- axi_vdma_vid_cdc ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_vdma_vid_cdc.vhd -- Description: This entity encompases the Clock Domain Crossing Pulse -- Generator -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_vdma.vhd -- |- axi_vdma_pkg.vhd -- |- axi_vdma_intrpt.vhd -- |- axi_vdma_rst_module.vhd -- | |- axi_vdma_reset.vhd (mm2s) -- | | |- axi_vdma_cdc.vhd -- | |- axi_vdma_reset.vhd (s2mm) -- | | |- axi_vdma_cdc.vhd -- | -- |- axi_vdma_reg_if.vhd -- | |- axi_vdma_lite_if.vhd -- | |- axi_vdma_cdc.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_vdma_sg_cdc.vhd (mm2s) -- |- axi_vdma_vid_cdc.vhd (mm2s) -- |- axi_vdma_fsync_gen.vhd (mm2s) -- |- axi_vdma_sof_gen.vhd (mm2s) -- |- axi_vdma_reg_module.vhd (mm2s) -- | |- axi_vdma_register.vhd (mm2s) -- | |- axi_vdma_regdirect.vhd (mm2s) -- |- axi_vdma_mngr.vhd (mm2s) -- | |- axi_vdma_sg_if.vhd (mm2s) -- | |- axi_vdma_sm.vhd (mm2s) -- | |- axi_vdma_cmdsts_if.vhd (mm2s) -- | |- axi_vdma_vidreg_module.vhd (mm2s) -- | | |- axi_vdma_sgregister.vhd (mm2s) -- | | |- axi_vdma_vregister.vhd (mm2s) -- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s) -- | | |- axi_vdma_blkmem.vhd (mm2s) -- | |- axi_vdma_genlock_mngr.vhd (mm2s) -- | |- axi_vdma_genlock_mux.vhd (mm2s) -- | |- axi_vdma_greycoder.vhd (mm2s) -- |- axi_vdma_mm2s_linebuf.vhd (mm2s) -- | |- axi_vdma_sfifo_autord.vhd (mm2s) -- | |- axi_vdma_afifo_autord.vhd (mm2s) -- | |- axi_vdma_skid_buf.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (mm2s) -- | -- |- axi_vdma_sg_cdc.vhd (s2mm) -- |- axi_vdma_vid_cdc.vhd (s2mm) -- |- axi_vdma_fsync_gen.vhd (s2mm) -- |- axi_vdma_sof_gen.vhd (s2mm) -- |- axi_vdma_reg_module.vhd (s2mm) -- | |- axi_vdma_register.vhd (s2mm) -- | |- axi_vdma_regdirect.vhd (s2mm) -- |- axi_vdma_mngr.vhd (s2mm) -- | |- axi_vdma_sg_if.vhd (s2mm) -- | |- axi_vdma_sm.vhd (s2mm) -- | |- axi_vdma_cmdsts_if.vhd (s2mm) -- | |- axi_vdma_vidreg_module.vhd (s2mm) -- | | |- axi_vdma_sgregister.vhd (s2mm) -- | | |- axi_vdma_vregister.vhd (s2mm) -- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm) -- | | |- axi_vdma_blkmem.vhd (s2mm) -- | |- axi_vdma_genlock_mngr.vhd (s2mm) -- | |- axi_vdma_genlock_mux.vhd (s2mm) -- | |- axi_vdma_greycoder.vhd (s2mm) -- |- axi_vdma_s2mm_linebuf.vhd (s2mm) -- | |- axi_vdma_sfifo_autord.vhd (s2mm) -- | |- axi_vdma_afifo_autord.vhd (s2mm) -- | |- axi_vdma_skid_buf.vhd (s2mm) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL) -- |- axi_sg_v3_00_a.axi_sg.vhd -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_vdma_v6_2; use axi_vdma_v6_2.axi_vdma_pkg.all; library lib_cdc_v1_0; ------------------------------------------------------------------------------- entity axi_vdma_vid_cdc is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ; C_GENLOCK_MSTR_PTR_DWIDTH : integer := 32 ; C_GENLOCK_SLVE_PTR_DWIDTH : integer := 32 ; C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0 ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Cross pntr/fsync to opposing channel -- othrchnl_aclk : in std_logic ; -- othrchnl_resetn : in std_logic ; -- othrchnl2cdc_frame_ptr_out : in std_logic_vector -- (C_GENLOCK_MSTR_PTR_DWIDTH-1 downto 0) ; -- cdc2othrchnl_frame_ptr_in : out std_logic_vector -- (C_GENLOCK_MSTR_PTR_DWIDTH-1 downto 0) ; -- cdc2othrchnl_fsync : out std_logic ; -- -- -- -- GEN-LOCK Clock Domain Crossing -- dmac2cdc_frame_ptr_out : in std_logic_vector -- (C_GENLOCK_MSTR_PTR_DWIDTH-1 downto 0) ; -- cdc2top_frame_ptr_out : out std_logic_vector -- (C_GENLOCK_MSTR_PTR_DWIDTH-1 downto 0) ; -- -- top2cdc_frame_ptr_in : in std_logic_vector -- (C_GENLOCK_SLVE_PTR_DWIDTH-1 downto 0) ; -- cdc2dmac_frame_ptr_in : out std_logic_vector -- (C_GENLOCK_SLVE_PTR_DWIDTH-1 downto 0) ; -- -- dmac2cdc_mstrfrm_tstsync : in std_logic ; -- cdc2dmac_mstrfrm_tstsync : out std_logic ; -- -- -- SOF Detection Domain Crossing (secondary to primary) -- vid2cdc_packet_sof : in std_logic ; -- cdc2dmac_packet_sof : out std_logic ; -- -- -- Frame Sync Generation Domain Crossing -- vid2cdc_fsync : in std_logic ; -- cdc2dmac_fsync : out std_logic ; -- -- dmac2cdc_fsync_out : in std_logic ; -- cdc2vid_fsync_out : out std_logic ; -- -- dmac2cdc_prmtr_update : in std_logic ; -- cdc2vid_prmtr_update : out std_logic -- ); end axi_vdma_vid_cdc; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_vdma_vid_cdc is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Cross sample and held fsync to secondary signal s_fsync_d1 : std_logic := '0'; signal s_fsync_d2 : std_logic := '0'; signal s_fsync_fe : std_logic := '0'; signal frame_ptr_in_d1_cdc_tig : std_logic_vector(C_GENLOCK_SLVE_PTR_DWIDTH-1 downto 0) := (others => '0'); signal frame_ptr_in_d2 : std_logic_vector(C_GENLOCK_SLVE_PTR_DWIDTH-1 downto 0) := (others => '0'); signal frame_ptr_out_d1_cdc_tig : std_logic_vector(C_GENLOCK_MSTR_PTR_DWIDTH-1 downto 0) := (others => '0'); signal frame_ptr_out_d2 : std_logic_vector(C_GENLOCK_MSTR_PTR_DWIDTH-1 downto 0) := (others => '0'); signal othrchnl_frame_ptr_in_d1_cdc_tig : std_logic_vector(C_GENLOCK_MSTR_PTR_DWIDTH-1 downto 0) := (others => '0'); signal othrchnl_frame_ptr_in_d2 : std_logic_vector(C_GENLOCK_MSTR_PTR_DWIDTH-1 downto 0) := (others => '0'); signal cdc2dmac_fsync_i : std_logic := '0'; ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF frame_ptr_in_d1_cdc_tig : SIGNAL IS "true"; ATTRIBUTE async_reg OF frame_ptr_in_d2 : SIGNAL IS "true"; ATTRIBUTE async_reg OF frame_ptr_out_d1_cdc_tig : SIGNAL IS "true"; ATTRIBUTE async_reg OF frame_ptr_out_d2 : SIGNAL IS "true"; ATTRIBUTE async_reg OF othrchnl_frame_ptr_in_d1_cdc_tig : SIGNAL IS "true"; ATTRIBUTE async_reg OF othrchnl_frame_ptr_in_d2 : SIGNAL IS "true"; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin cdc2dmac_fsync <= cdc2dmac_fsync_i; -- register fsync in and set up for creating fall edge REG_FSYNC_IN : process(scndry_aclk) begin if(scndry_aclk'EVENT and scndry_aclk ='1')then if(scndry_resetn = '0')then s_fsync_d1 <= '0'; s_fsync_d2 <= '0'; else s_fsync_d1 <= vid2cdc_fsync; s_fsync_d2 <= s_fsync_d1; end if; end if; end process REG_FSYNC_IN; -- Pass scndry fe out for frame sync if running s_fsync_fe <= not s_fsync_d1 and s_fsync_d2; -- Aysnchronous mode therefore instantiate clock domain crossing logic GEN_CDC_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate begin --***************************************************************************** --** GenLock CDC --***************************************************************************** -- From GenLock manager to AXIS clock domain ---- M_PTR_OUT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc ---- generic map( ---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED , ---- C_VECTOR_WIDTH => C_GENLOCK_MSTR_PTR_DWIDTH ---- ) ---- port map ( ---- prmry_aclk => prmry_aclk , ---- prmry_resetn => prmry_resetn , ---- scndry_aclk => scndry_aclk , ---- scndry_resetn => scndry_resetn , ---- scndry_in => '0' , ---- prmry_out => open , ---- prmry_in => dmac2cdc_mstrfrm_tstsync , ---- scndry_out => cdc2dmac_mstrfrm_tstsync , ---- scndry_vect_s_h => '0' , ---- scndry_vect_in => ZERO_VALUE_VECT ---- (C_GENLOCK_MSTR_PTR_DWIDTH-1 downto 0) , ---- prmry_vect_out => open , ---- prmry_vect_s_h => '0' , ---- prmry_vect_in => ZERO_VALUE_VECT ---- (C_GENLOCK_MSTR_PTR_DWIDTH-1 downto 0) , ---- scndry_vect_out => open ---- ); ---- M_PTR_OUT_CDC_I : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 0, C_FLOP_INPUT => 1, --valid only for level CDC C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => prmry_aclk, prmry_resetn => prmry_resetn, prmry_in => dmac2cdc_mstrfrm_tstsync, prmry_vect_in => (others => '0'), prmry_ack => open, scndry_aclk => scndry_aclk, scndry_resetn => scndry_resetn, scndry_out => cdc2dmac_mstrfrm_tstsync, scndry_vect_out => open ); -- frame_ptr is grey coded and thus double register is all that is needed CROSS_FRMPTR_IN_1 : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then frame_ptr_in_d1_cdc_tig <= top2cdc_frame_ptr_in; frame_ptr_in_d2 <= frame_ptr_in_d1_cdc_tig; end if; end process CROSS_FRMPTR_IN_1; CROSS_FRMPTR_IN_2 : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then cdc2dmac_frame_ptr_in <= (others => '0'); else cdc2dmac_frame_ptr_in <= frame_ptr_in_d2; end if; end if; end process CROSS_FRMPTR_IN_2; -- frame_ptr is grey coded and thus double register is all that is needed CROSS_FRMPTR_OUT_1 : process(scndry_aclk) begin if(scndry_aclk'EVENT and scndry_aclk = '1')then frame_ptr_out_d1_cdc_tig <= dmac2cdc_frame_ptr_out; frame_ptr_out_d2 <= frame_ptr_out_d1_cdc_tig; end if; end process CROSS_FRMPTR_OUT_1; CROSS_FRMPTR_OUT_2 : process(scndry_aclk) begin if(scndry_aclk'EVENT and scndry_aclk = '1')then if(scndry_resetn = '0')then cdc2top_frame_ptr_out <= (others => '0'); else cdc2top_frame_ptr_out <= frame_ptr_out_d2; end if; end if; end process CROSS_FRMPTR_OUT_2; GEN_FOR_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 1 generate begin -- Cross from primary channel to other channel -- (or opposing channel, i.e. mm2s to s2mm or s2mm to mm2s) -- Used for internal genlock option CROSS_TO_OTHR_CHANNEL_1 : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then othrchnl_frame_ptr_in_d1_cdc_tig <= othrchnl2cdc_frame_ptr_out; othrchnl_frame_ptr_in_d2 <= othrchnl_frame_ptr_in_d1_cdc_tig; end if; end process CROSS_TO_OTHR_CHANNEL_1; CROSS_TO_OTHR_CHANNEL_2 : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then cdc2othrchnl_frame_ptr_in <= (others => '0'); else cdc2othrchnl_frame_ptr_in <= othrchnl_frame_ptr_in_d2; end if; end if; end process CROSS_TO_OTHR_CHANNEL_2; end generate GEN_FOR_INTERNAL_GENLOCK; GEN_FOR_NO_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 0 generate begin cdc2othrchnl_frame_ptr_in <= (others => '0'); end generate GEN_FOR_NO_INTERNAL_GENLOCK; -- Cross other fsync into primary clock domain ---- OTHR_FSYNC_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc ---- generic map( ---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED , ---- C_VECTOR_WIDTH => 1 ---- ) ---- port map ( ---- prmry_aclk => othrchnl_aclk , ---- prmry_resetn => othrchnl_resetn , ---- scndry_aclk => scndry_aclk , ---- scndry_resetn => scndry_resetn , ---- scndry_in => s_fsync_fe , ---- prmry_out => cdc2othrchnl_fsync , ---- prmry_in => '0' , ---- scndry_out => open , ---- scndry_vect_s_h => '0' , ---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , ---- prmry_vect_out => open , ---- prmry_vect_s_h => '0' , ---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , ---- scndry_vect_out => open ---- ); OTHR_FSYNC_CDC_I : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 0, C_FLOP_INPUT => 1, --valid only for level CDC C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => scndry_aclk, prmry_resetn => scndry_resetn, prmry_in => s_fsync_fe, prmry_vect_in => (others => '0'), prmry_ack => open, scndry_aclk => othrchnl_aclk, scndry_resetn => othrchnl_resetn, scndry_out => cdc2othrchnl_fsync, scndry_vect_out => open ); --***************************************************************************** --** SOF CDC --***************************************************************************** ---- SOF_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc ---- generic map( ---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED , ---- C_VECTOR_WIDTH => 1 ---- ) ---- port map ( ---- prmry_aclk => prmry_aclk , ---- prmry_resetn => prmry_resetn , ---- scndry_aclk => scndry_aclk , ---- scndry_resetn => scndry_resetn , ---- scndry_in => vid2cdc_packet_sof , ---- prmry_out => cdc2dmac_packet_sof , ---- prmry_in => '0' , ---- scndry_out => open , ---- scndry_vect_s_h => '0' , ---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , ---- prmry_vect_out => open , ---- prmry_vect_s_h => '0' , ---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , ---- scndry_vect_out => open ---- ); ---- SOF_CDC_I : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 0, C_FLOP_INPUT => 1, --valid only for level CDC C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => scndry_aclk, prmry_resetn => scndry_resetn, prmry_in => vid2cdc_packet_sof, prmry_vect_in => (others => '0'), prmry_ack => open, scndry_aclk => prmry_aclk, scndry_resetn => prmry_resetn, scndry_out => cdc2dmac_packet_sof, scndry_vect_out => open ); --***************************************************************************** --** Frame Sync CDC --***************************************************************************** -- From axi vdma top out (scndry_aclk) to frame sync gen (prmry_aclk) ---- FSYNC_IN_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc ---- generic map( ---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED , ---- C_VECTOR_WIDTH => 1 ---- ) ---- port map ( ---- prmry_aclk => prmry_aclk , ---- prmry_resetn => prmry_resetn , ---- scndry_aclk => scndry_aclk , ---- scndry_resetn => scndry_resetn , ---- ---- scndry_in => s_fsync_fe , ---- prmry_out => cdc2dmac_fsync_i , ---- prmry_in => '0' , ---- scndry_out => open , ---- ---- scndry_vect_s_h => '0' , ---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , ---- prmry_vect_out => open , ---- prmry_vect_s_h => '0' , ---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , ---- scndry_vect_out => open ---- ); ---- FSYNC_IN_CDC_I : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 0, C_FLOP_INPUT => 1, --valid only for level CDC C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => scndry_aclk, prmry_resetn => scndry_resetn, prmry_in => s_fsync_fe, prmry_vect_in => (others => '0'), prmry_ack => open, scndry_aclk => prmry_aclk, scndry_resetn => prmry_resetn, scndry_out => cdc2dmac_fsync_i, scndry_vect_out => open ); -- From frame sync gen (prmry_aclk) to axi vdma top out (scndry_aclk) ---- FSYNC_OUT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc ---- generic map( ---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED , ---- C_VECTOR_WIDTH => 1 ---- ) ---- port map ( ---- prmry_aclk => prmry_aclk , ---- prmry_resetn => prmry_resetn , ---- scndry_aclk => scndry_aclk , ---- scndry_resetn => scndry_resetn , ---- scndry_in => '0' , ---- prmry_out => open , ---- prmry_in => dmac2cdc_fsync_out , ---- scndry_out => cdc2vid_fsync_out , ---- scndry_vect_s_h => '0' , ---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , ---- prmry_vect_out => open , ---- prmry_vect_s_h => '0' , ---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , ---- scndry_vect_out => open ---- ); ---- FSYNC_OUT_CDC_I : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 0, C_FLOP_INPUT => 1, --valid only for level CDC C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => prmry_aclk, prmry_resetn => prmry_resetn, prmry_in => dmac2cdc_fsync_out, prmry_vect_in => (others => '0'), prmry_ack => open, scndry_aclk => scndry_aclk, scndry_resetn => scndry_resetn, scndry_out => cdc2vid_fsync_out, scndry_vect_out => open ); -- From frame sync gen (prmry_aclk) to axi vdma top out (scndry_aclk) ---- PRMTR_UPDT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc ---- generic map( ---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED , ---- C_VECTOR_WIDTH => 1 ---- ) ---- port map ( ---- prmry_aclk => prmry_aclk , ---- prmry_resetn => prmry_resetn , ---- scndry_aclk => scndry_aclk , ---- scndry_resetn => scndry_resetn , ---- scndry_in => '0' , ---- prmry_out => open , ---- prmry_in => dmac2cdc_prmtr_update , ---- scndry_out => cdc2vid_prmtr_update , ---- scndry_vect_s_h => '0' , ---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , ---- prmry_vect_out => open , ---- prmry_vect_s_h => '0' , ---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , ---- scndry_vect_out => open ---- ); PRMTR_UPDT_CDC_I : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 0, C_FLOP_INPUT => 1, --valid only for level CDC C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => prmry_aclk, prmry_resetn => prmry_resetn, prmry_in => dmac2cdc_prmtr_update, prmry_vect_in => (others => '0'), prmry_ack => open, scndry_aclk => scndry_aclk, scndry_resetn => scndry_resetn, scndry_out => cdc2vid_prmtr_update, scndry_vect_out => open ); end generate GEN_CDC_FOR_ASYNC; -- Synchronous Mode therefore map inputs to associated -- outputs directly. GEN_NO_CDC_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate begin cdc2top_frame_ptr_out <= dmac2cdc_frame_ptr_out ; cdc2dmac_frame_ptr_in <= top2cdc_frame_ptr_in ; cdc2dmac_mstrfrm_tstsync <= dmac2cdc_mstrfrm_tstsync ; cdc2dmac_packet_sof <= vid2cdc_packet_sof; cdc2dmac_fsync_i <= s_fsync_fe ; cdc2vid_fsync_out <= dmac2cdc_fsync_out ; cdc2vid_prmtr_update <= dmac2cdc_prmtr_update ; cdc2othrchnl_fsync <= s_fsync_fe ; GEN_FOR_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 1 generate begin cdc2othrchnl_frame_ptr_in <= othrchnl2cdc_frame_ptr_out; end generate GEN_FOR_INTERNAL_GENLOCK; GEN_FOR_NO_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 0 generate begin cdc2othrchnl_frame_ptr_in <= (others => '0'); end generate GEN_FOR_NO_INTERNAL_GENLOCK; end generate GEN_NO_CDC_FOR_SYNC; end implementation;
gpl-2.0
freecores/t48
syn/t8048/b5x300/t48_rom.vhd
2
885
-- This file was generated with hex2rom written by Daniel Wallner library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity rom_t48 is port( Clk : in std_logic; A : in std_logic_vector(9 downto 0); D : out std_logic_vector(7 downto 0) ); end rom_t48; architecture rtl of rom_t48 is signal A_r : std_logic_vector(9 downto 0); begin process (Clk) begin if Clk'event and Clk = '1' then A_r <= A; end if; end process; process (A_r) begin case to_integer(unsigned(A_r)) is when 000000 => D <= "00100011"; -- 0x0000 when 000001 => D <= "11111111"; -- 0x0001 when 000002 => D <= "00111001"; -- 0x0002 when 000003 => D <= "11010011"; -- 0x0003 when 000004 => D <= "00000001"; -- 0x0004 when 000005 => D <= "00000100"; -- 0x0005 when 000006 => D <= "00000010"; -- 0x0006 when others => D <= "--------"; end case; end process; end;
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_updt_queue.vhd
2
39104
------------------------------------------------------------------------------- -- axi_sg_ftchq_if ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_queue.vhd -- Description: This entity is the descriptor fetch queue interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_sg.vhd -- axi_sg_pkg.vhd -- |- axi_sg_ftch_mngr.vhd -- | |- axi_sg_ftch_sm.vhd -- | |- axi_sg_ftch_pntr.vhd -- | |- axi_sg_ftch_cmdsts_if.vhd -- |- axi_sg_updt_mngr.vhd -- | |- axi_sg_updt_sm.vhd -- | |- axi_sg_updt_cmdsts_if.vhd -- |- axi_sg_ftch_q_mngr.vhd -- | |- axi_sg_ftch_queue.vhd -- | | |- proc_common_v4_0.sync_fifo_fg.vhd -- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd -- | |- axi_sg_ftch_noqueue.vhd -- |- axi_sg_updt_q_mngr.vhd -- | |- axi_sg_updt_queue.vhd -- | | |- proc_common_v4_0.sync_fifo_fg.vhd -- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd -- | |- axi_sg_updt_noqueue.vhd -- |- axi_sg_intrpt.vhd -- |- axi_datamover_v5_0.axi_datamover.vhd -- ------------------------------------------------------------------------------- -- Author: Gary Burch -- History: -- GAB 3/19/10 v1_00_a -- ^^^^^^ -- - Initial Release -- ~~~~~~ -- GAB 8/26/10 v2_00_a -- ^^^^^^ -- Seperated update queues into two seperate files, no queue and queue to -- simplify maintainance. -- ~~~~~~ -- GAB 10/21/10 v4_03 -- ^^^^^^ -- Rolled version to v4_03 -- ~~~~~~ -- GAB 11/15/10 v2_01_a -- ^^^^^^ -- CR582800 -- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH -- ~~~~~~ -- GAB 6/13/11 v4_03 -- ^^^^^^ -- Update to AXI Datamover v4_03 -- Added aynchronous operation -- ~~~~~~ ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_vdma_v6_2; use axi_vdma_v6_2.axi_sg_pkg.all; library lib_pkg_v1_0; library lib_fifo_v1_0; use lib_fifo_v1_0.sync_fifo_fg; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_queue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_FAMILY : string := "virtex6" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- s_axis_updt_aclk : in std_logic ; -- -- --********************************-- -- --** Control and Status **-- -- --********************************-- -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- -- --********************************-- -- --** Update Interfaces In **-- -- --********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- -- --********************************-- -- --** Update Interfaces Out **-- -- --********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_queue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_queue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs -- Number of words deep fifo needs to be. Depth required to store 2 word -- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2 --constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2); constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2)); -- Width of fifo rd and wr counts - only used for proper fifo operation constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1); -- Select between BRAM or LOGIC memory type constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16); -- Number of words deep fifo needs to be. Depth required to store all update -- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * C_SG_WORDS_TO_UPDATE)); -- Select between BRAM or LOGIC memory type constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16); -- Width of fifo rd and wr counts - only used for proper fifo operation constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; -- State Machine Signal signal writing_status : std_logic := '0'; signal dataq_rden : std_logic := '0'; signal stsq_rden : std_logic := '0'; -- Pointer Queue FIFO Signals signal ptr_queue_rden : std_logic := '0'; signal ptr_queue_wren : std_logic := '0'; signal ptr_queue_empty : std_logic := '0'; signal ptr_queue_full : std_logic := '0'; signal ptr_queue_din : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ptr_queue_dout : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); -- Status Queue FIFO Signals signal sts_queue_wren : std_logic := '0'; signal sts_queue_rden : std_logic := '0'; signal sts_queue_din : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts_queue_dout : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts_queue_full : std_logic := '0'; signal sts_queue_empty : std_logic := '0'; -- Misc Support Signals signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; signal sinit : std_logic := '0'; signal updt_tvalid : std_logic := '0'; signal updt_tlast : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- channel 1 REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active; end if; end if; end process REG_ACTIVE; updt_active_re <= updt_active and not updt_active_d1; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active_re, ptr_queue_empty, m_axis_updt_tready, updt_tvalid, updt_tlast) begin write_curdesc_lsb <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; dataq_rden <= '0'; stsq_rden <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if(updt_active_re = '1')then pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor pointer -- Reads one word from data queue fifo --------------------------------------------------------------- when READ_CURDESC_LSB => -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(ptr_queue_empty = '0')then write_curdesc_lsb <= '1'; dataq_rden <= '1'; pntr_ns <= READ_CURDESC_MSB; else pntr_ns <= READ_CURDESC_LSB; end if; --------------------------------------------------------------- -- Get upper current descriptor -- Reads one word from data queue fifo --------------------------------------------------------------- when READ_CURDESC_MSB => -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. if(ptr_queue_empty = '0')then dataq_rden <= '1'; write_curdesc_msb <= '1'; pntr_ns <= WRITE_STATUS; else pntr_ns <= READ_CURDESC_MSB; end if; --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => -- De-MUX appropriage tvalid/tlast signals writing_status <= '1'; -- Enable reading of Status Queue if datamover can -- accept data stsq_rden <= m_axis_updt_tready; -- Hold in the status state until tlast is pulled -- from status fifo if(updt_tvalid = '1' and m_axis_updt_tready = '1' and updt_tlast = '1')then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; when others => pntr_ns <= IDLE; end case; end process CURDESC_PNTR_STATE; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate begin -- Channel Pointer Queue (Generate Synchronous FIFO) I_UPDT_DATA_FIFO : entity lib_fifo_v1_0.sync_fifo_fg generic map ( C_FAMILY => C_FAMILY , C_MEMORY_TYPE => UPD_Q_MEMORY_TYPE , C_WRITE_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_WRITE_DEPTH => UPDATE_QUEUE_DEPTH , C_READ_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_READ_DEPTH => UPDATE_QUEUE_DEPTH , C_PORTS_DIFFER => 0, C_HAS_DCOUNT => 1, --req for proper fifo operation C_DCOUNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH, C_HAS_ALMOST_FULL => 0, C_HAS_RD_ACK => 0, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_ERR_LOW => 0, C_WR_ACK_LOW => 0, C_WR_ERR_LOW => 0, C_PRELOAD_REGS => 1,-- 1 = first word fall through C_PRELOAD_LATENCY => 0 -- 0 = first word fall through ) port map ( Clk => m_axi_sg_aclk , Sinit => sinit , Din => ptr_queue_din , Wr_en => ptr_queue_wren , Rd_en => ptr_queue_rden , Dout => ptr_queue_dout , Full => ptr_queue_full , Empty => ptr_queue_empty , Almost_full => open , Data_count => open , Rd_ack => open , Rd_err => open , Wr_ack => open , Wr_err => open ); -- Channel Status Queue (Generate Synchronous FIFO) I_UPDT_STS_FIFO : entity lib_fifo_v1_0.sync_fifo_fg generic map ( C_FAMILY => C_FAMILY , C_MEMORY_TYPE => STS_Q_MEMORY_TYPE , C_WRITE_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage C_WRITE_DEPTH => UPDATE_STS_QUEUE_DEPTH , C_READ_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage C_READ_DEPTH => UPDATE_STS_QUEUE_DEPTH , C_PORTS_DIFFER => 0 , C_HAS_DCOUNT => 1 , --req for proper fifo operation C_DCOUNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH , C_HAS_ALMOST_FULL => 0 , C_HAS_RD_ACK => 0 , C_HAS_RD_ERR => 0 , C_HAS_WR_ACK => 0 , C_HAS_WR_ERR => 0 , C_RD_ACK_LOW => 0 , C_RD_ERR_LOW => 0 , C_WR_ACK_LOW => 0 , C_WR_ERR_LOW => 0 , C_PRELOAD_REGS => 1 ,-- 1 = first word fall through C_PRELOAD_LATENCY => 0 -- 0 = first word fall through ) port map ( Clk => m_axi_sg_aclk , Sinit => sinit , Din => sts_queue_din , Wr_en => sts_queue_wren , Rd_en => sts_queue_rden , Dout => sts_queue_dout , Full => sts_queue_full , Empty => sts_queue_empty , Almost_full => open , Data_count => open , Rd_ack => open , Rd_err => open , Wr_ack => open , Wr_err => open ); end generate GEN_Q_FOR_SYNC; GEN_Q_FOR_ASYNC : if C_AXIS_IS_ASYNC = 1 generate begin -- Generate Asynchronous FIFO I_UPDT_DATA_FIFO : entity axi_vdma_v6_2.axi_sg_afifo_autord generic map( C_DWIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_DEPTH => UPDATE_QUEUE_DEPTH , C_CNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH , C_USE_BLKMEM => UPD_Q_MEMORY_TYPE , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => sinit , AFIFO_Wr_clk => m_axi_sg_aclk , AFIFO_Wr_en => ptr_queue_wren , AFIFO_Din => ptr_queue_din , AFIFO_Rd_clk => s_axis_updt_aclk , AFIFO_Rd_en => ptr_queue_rden , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => open , AFIFO_Dout => ptr_queue_dout , AFIFO_Full => ptr_queue_full , AFIFO_Empty => ptr_queue_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); -- Generate Asynchronous FIFO I_UPDT_STS_FIFO : entity axi_vdma_v6_2.axi_sg_afifo_autord generic map( C_DWIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , C_DEPTH => UPDATE_STS_QUEUE_DEPTH , C_CNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH , C_USE_BLKMEM => STS_Q_MEMORY_TYPE , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => sinit , AFIFO_Wr_clk => s_axis_updt_aclk , AFIFO_Wr_en => sts_queue_wren , AFIFO_Din => sts_queue_din , AFIFO_Rd_clk => m_axi_sg_aclk , AFIFO_Rd_en => sts_queue_rden , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => open , AFIFO_Dout => sts_queue_dout , AFIFO_Full => sts_queue_full , AFIFO_Empty => sts_queue_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); end generate GEN_Q_FOR_ASYNC; -- FIFO Reset is active high sinit <= not m_axi_sg_aresetn; --***************************************** --** Channel Data Port Side of Queues --***************************************** -- Pointer Queue Update - Descriptor Pointer (32bits) -- i.e. 2 current descriptor pointers and any app fields ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- Data Queue Write Enable - based on tvalid and queue not full ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid and not ptr_queue_full; -- Data Queue NOT Full -- Drive channel port with ready if room in data queue s_axis_updtptr_tready <= not ptr_queue_full; --***************************************** --** Channel Status Port Side of Queues --***************************************** -- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits) -- Note: Type field is stripped off sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- Status Queue Write Enable - based on tvalid and queue not full sts_queue_wren <= s_axis_updtsts_tvalid and not sts_queue_full; -- Drive channel port with ready if room in status queue s_axis_updtsts_tready <= not sts_queue_full; --************************************* --** SG Engine Side of Queues --************************************* -- Indicate NOT empty if both status queue and data queue are not empty updt_queue_empty <= ptr_queue_empty or sts_queue_empty; -- Data queue read enable ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable and ptr_queue_empty = '0' -- Data Queue NOT empty else '0'; -- Status queue read enable sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status and sts_queue_empty = '0' -- Status fifo NOT empty else '0'; ----------------------------------------------------------------------- -- TVALID - status queue not empty and writing status ----------------------------------------------------------------------- updt_tvalid <= not sts_queue_empty and writing_status; ----------------------------------------------------------------------- -- TLAST - status queue not empty, writing status, and last asserted ----------------------------------------------------------------------- -- Drive last as long as tvalid is asserted and last from fifo -- is asserted updt_tlast <= not sts_queue_empty and writing_status and sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH); ----------------------------------------------------------------------- -- TDATA - drive data to datamover from status queue ----------------------------------------------------------------------- m_axis_updt_tdata <= sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid <= updt_tvalid; m_axis_updt_tlast <= updt_tlast; --********************************************************************* --** POINTER CAPTURE LOGIC --********************************************************************* --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1')then updt_curdesc(31 downto 0) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1')then updt_curdesc(63 downto 32) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_msb = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --********************************************************************* --** ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; ----------------------------------------------------------------------- -- Caputure IOC begin set ----------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re = '1')then updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re = '1')then dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re = '1')then dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re = '1')then dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; end implementation;
gpl-2.0
freecores/t48
bench/vhdl/tb.vhd
1
18038
------------------------------------------------------------------------------- -- -- The testbench for t48_core. -- -- $Id: tb.vhd,v 1.14 2006-06-21 01:04:05 arniml Exp $ -- -- Copyright (c) 2004, Arnim Laeuger ([email protected]) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- The latest version of this file can be found at: -- http://www.opencores.org/cvsweb.shtml/t48/ -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity tb is end tb; use work.t48_core_comp_pack.all; use work.t48_tb_pack.all; architecture behav of tb is -- clock period, 11 MHz constant period_c : time := 90 ns; component if_timing port( xtal_i : in std_logic; ale_i : in std_logic; psen_n_i : in std_logic; rd_n_i : in std_logic; wr_n_i : in std_logic; prog_n_i : in std_logic; db_bus_i : in std_logic_vector(7 downto 0); p2_i : in std_logic_vector(7 downto 0) ); end component; component lpm_rom generic ( LPM_WIDTH : positive; LPM_TYPE : string := "LPM_ROM"; LPM_WIDTHAD : positive; LPM_NUMWORDS : natural := 0; LPM_FILE : string; LPM_ADDRESS_CONTROL : string := "REGISTERED"; LPM_OUTDATA : string := "REGISTERED"; LPM_HINT : string := "UNUSED" ); port ( address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); inclock : in std_logic; outclock : in std_logic; memenab : in std_logic; q : out std_logic_vector(LPM_WIDTH-1 downto 0) ); end component; signal xtal_s : std_logic; signal xtal_n_s : std_logic; signal res_n_s : std_logic; signal xtal3_s : std_logic; signal int_n_s : std_logic; signal ale_s : std_logic; signal rom_addr_s : std_logic_vector(11 downto 0); signal rom_data_s : std_logic_vector( 7 downto 0); signal ram_data_to_s : std_logic_vector( 7 downto 0); signal ram_data_from_s : std_logic_vector( 7 downto 0); signal ram_addr_s : std_logic_vector( 7 downto 0); signal ram_we_s : std_logic; signal p1_s : std_logic_vector( 7 downto 0); signal t48_p1_s : std_logic_vector( 7 downto 0); signal p1_low_imp_s : std_logic; signal p2_s : std_logic_vector( 7 downto 0); signal t48_p2_s : std_logic_vector( 7 downto 0); signal p2l_low_imp_s : std_logic; signal p2h_low_imp_s : std_logic; signal psen_n_s : std_logic; signal prog_n_s : std_logic; signal bus_s : std_logic_vector( 7 downto 0); signal t48_bus_s : std_logic_vector( 7 downto 0); signal bus_dir_s : std_logic; signal ext_mem_addr_q : std_logic_vector( 7 downto 0); signal ext_ram_data_from_s : std_logic_vector( 7 downto 0); signal ext_ram_we_q : std_logic; signal rd_n_s : std_logic; signal wr_n_s : std_logic; signal ext_rom_data_s : std_logic_vector( 7 downto 0); signal ext_rom_addr_s : std_logic_vector(11 downto 0); signal tb_p1_q : std_logic_vector( 7 downto 0); signal tb_p2_q : std_logic_vector( 7 downto 0); signal ext_mem_sel_we_q : boolean; signal ena_ext_ram_q : boolean; signal ena_tb_periph_q : boolean; signal zero_s : std_logic; signal one_s : std_logic; signal zero_byte_s : std_logic_vector( 7 downto 0); begin zero_s <= '0'; one_s <= '1'; zero_byte_s <= (others => '0'); ----------------------------------------------------------------------------- -- Internal ROM, 2k bytes -- Initialized by file rom_t49.hex. ----------------------------------------------------------------------------- rom_internal_2k : lpm_rom generic map ( LPM_WIDTH => 8, LPM_TYPE => "LPM_ROM", LPM_WIDTHAD => 11, LPM_NUMWORDS => 2 ** 11, LPM_FILE => "rom_t49.hex", LPM_ADDRESS_CONTROL => "REGISTERED", LPM_OUTDATA => "UNREGISTERED", LPM_HINT => "UNUSED" ) port map ( address => rom_addr_s(10 downto 0), inclock => xtal_s, outclock => zero_s, -- unused memenab => one_s, q => rom_data_s ); ----------------------------------------------------------------------------- -- External ROM, 2k bytes -- Initialized by file rom_t49_ext.hex. ----------------------------------------------------------------------------- ext_rom_addr_s(11 downto 8) <= t48_p2_s(3 downto 0); ext_rom_addr_s( 7 downto 0) <= ext_mem_addr_q; rom_external_2k : lpm_rom generic map ( LPM_WIDTH => 8, LPM_TYPE => "LPM_ROM", LPM_WIDTHAD => 11, LPM_NUMWORDS => 2 ** 11, LPM_FILE => "rom_t49_ext.hex", LPM_ADDRESS_CONTROL => "REGISTERED", LPM_OUTDATA => "UNREGISTERED", LPM_HINT => "UNUSED" ) port map ( address => ext_rom_addr_s(10 downto 0), inclock => xtal_s, outclock => zero_s, -- unused memenab => one_s, q => ext_rom_data_s ); ----------------------------------------------------------------------------- -- Internal RAM, 256 bytes ----------------------------------------------------------------------------- ram_256 : generic_ram_ena generic map ( addr_width_g => 8, data_width_g => 8 ) port map ( clk_i => xtal_s, a_i => ram_addr_s, we_i => ram_we_s, ena_i => one_s, d_i => ram_data_to_s, d_o => ram_data_from_s ); ----------------------------------------------------------------------------- -- External RAM, 256 bytes ----------------------------------------------------------------------------- ext_ram_b : generic_ram_ena generic map ( addr_width_g => 8, data_width_g => 8 ) port map ( clk_i => xtal_s, a_i => ext_mem_addr_q, we_i => ext_ram_we_q, ena_i => one_s, d_i => bus_s, d_o => ext_ram_data_from_s ); t48_core_b : t48_core generic map ( xtal_div_3_g => 1, register_mnemonic_g => 1, include_port1_g => 1, include_port2_g => 1, include_bus_g => 1, include_timer_g => 1, sample_t1_state_g => 4 ) port map ( xtal_i => xtal_s, xtal_en_i => one_s, reset_i => res_n_s, t0_i => p1_s(0), t0_o => open, t0_dir_o => open, int_n_i => int_n_s, ea_i => rom_addr_s(11), rd_n_o => rd_n_s, psen_n_o => psen_n_s, wr_n_o => wr_n_s, ale_o => ale_s, db_i => bus_s, db_o => t48_bus_s, db_dir_o => bus_dir_s, t1_i => p1_s(1), p2_i => p2_s, p2_o => t48_p2_s, p2l_low_imp_o => p2l_low_imp_s, p2h_low_imp_o => p2h_low_imp_s, p1_i => p1_s, p1_o => t48_p1_s, p1_low_imp_o => p1_low_imp_s, prog_n_o => prog_n_s, clk_i => xtal_s, en_clk_i => xtal3_s, xtal3_o => xtal3_s, dmem_addr_o => ram_addr_s, dmem_we_o => ram_we_s, dmem_data_i => ram_data_from_s, dmem_data_o => ram_data_to_s, pmem_addr_o => rom_addr_s, pmem_data_i => rom_data_s ); if_timing_b : if_timing port map ( xtal_i => xtal_s, ale_i => ale_s, psen_n_i => psen_n_s, rd_n_i => rd_n_s, wr_n_i => wr_n_s, prog_n_i => prog_n_s, db_bus_i => bus_s, p2_i => t48_p2_s ); ----------------------------------------------------------------------------- -- Port logic -- ports: process (t48_p1_s, p1_low_imp_s, t48_p2_s, p2l_low_imp_s, p2h_low_imp_s) function t48_port_f(t48_p : std_logic_vector; low_imp : std_logic) return std_logic_vector is variable p_v : std_logic_vector(t48_p'range); begin if low_imp = '1' then p_v := t48_p; else for i in p_v'range loop if t48_p(i) = '1' then p_v(i) := 'H'; else p_v(i) := t48_p(i); end if; end loop; end if; return p_v; end; begin p1_s <= t48_port_f(t48_p => t48_p1_s, low_imp => p1_low_imp_s); p2_s(3 downto 0) <= t48_port_f(t48_p => t48_p2_s(3 downto 0), low_imp => p2l_low_imp_s); p2_s(7 downto 4) <= t48_port_f(t48_p => t48_p2_s(7 downto 4), low_imp => p2h_low_imp_s); end process ports; -- ----------------------------------------------------------------------------- bus_s <= t48_bus_s when bus_dir_s = '1' else (others => 'Z'); bus_s <= ext_ram_data_from_s when rd_n_s = '0' and ena_ext_ram_q else (others => 'Z'); bus_s <= ext_rom_data_s when psen_n_s = '0' else (others => 'Z'); ----------------------------------------------------------------------------- -- External memory access signals -- ext_mem: process (wr_n_s, ext_mem_addr_q, ena_ext_ram_q, ale_s, bus_s, xtal_s) begin if ale_s'event and ale_s = '0' then if not is_X(bus_s) then ext_mem_addr_q <= bus_s; else ext_mem_addr_q <= (others => '0'); end if; end if; if wr_n_s'event and wr_n_s = '1' then -- write enable for external RAM if ena_ext_ram_q then ext_ram_we_q <= '1'; end if; -- process external memory selector if ext_mem_addr_q = "11111111" then ext_mem_sel_we_q <= true; end if; end if; if xtal_s'event and xtal_s = '1' then ext_ram_we_q <= '0'; ext_mem_sel_we_q <= false; end if; end process ext_mem; -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Process ext_mem_sel -- -- Purpose: -- Select external memory address space. -- This is either -- + external RAM -- + testbench peripherals -- ext_mem_sel: process (res_n_s, xtal_s) begin if res_n_s = '0' then ena_ext_ram_q <= true; ena_tb_periph_q <= false; elsif xtal_s'event and xtal_s = '1' then if ext_mem_sel_we_q then if bus_s(0) = '1' then ena_ext_ram_q <= true; else ena_ext_ram_q <= false; end if; if bus_s(1) = '1' then ena_tb_periph_q <= true; else ena_tb_periph_q <= false; end if; end if; end if; end process ext_mem_sel; -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Process tb_periph -- -- Purpose: -- Implements the testbenc peripherals driving P1 and P2. -- tb_periph: process (res_n_s, wr_n_s) function oc_f (pX : std_logic_vector) return std_logic_vector is variable r_v : std_logic_vector(pX'range); begin for i in pX'range loop if pX(i) = '0' then r_v(i) := '0'; else r_v(i) := 'H'; end if; end loop; return r_v; end; begin if res_n_s = '0' then tb_p1_q <= (others => 'H'); tb_p2_q <= (others => 'H'); elsif wr_n_s'event and wr_n_s = '1' then if ena_tb_periph_q then case ext_mem_addr_q is -- P1 when "00000000" => tb_p1_q <= oc_f(t48_bus_s); -- P2 when "00000001" => tb_p2_q <= oc_f(t48_bus_s); when others => null; end case; end if; end if; end process tb_periph; -- ----------------------------------------------------------------------------- p1_s <= tb_p1_q; p2_s <= tb_p2_q; xtal_n_s <= not xtal_s; ----------------------------------------------------------------------------- -- The clock generator -- clk_gen: process begin xtal_s <= '0'; wait for period_c/2; xtal_s <= '1'; wait for period_c/2; end process clk_gen; -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- The reset generator -- res_gen: process begin res_n_s <= '0'; wait for 5 * period_c; res_n_s <= '1'; wait; end process res_gen; -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- The interrupt generator -- int_gen: process begin int_n_s <= '1'; wait for 750 * period_c; int_n_s <= '0'; wait for 45 * period_c; end process int_gen; -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- End of simulation detection -- eos: process begin outer: loop wait on tb_accu_s; if tb_accu_s = "10101010" then wait on tb_accu_s; if tb_accu_s = "01010101" then wait on tb_accu_s; if tb_accu_s = "00000001" then -- wait for instruction strobe of this move wait until tb_istrobe_s'event and tb_istrobe_s = '1'; -- wait for next strobe wait until tb_istrobe_s'event and tb_istrobe_s = '1'; assert false report "Simulation Result: PASS." severity note; else assert false report "Simulation Result: FAIL." severity note; end if; assert false report "End of simulation reached." severity failure; end if; end if; end loop; end process eos; -- ----------------------------------------------------------------------------- end behav; ------------------------------------------------------------------------------- -- File History: -- -- $Log: not supported by cvs2svn $ -- Revision 1.13 2006/06/20 00:45:26 arniml -- new input xtal_en_i -- -- Revision 1.12 2005/11/01 21:21:48 arniml -- split low impedance markers for P2 -- -- Revision 1.11 2005/09/07 17:39:40 arniml -- fix missing assignment to outclock -- -- Revision 1.10 2004/05/21 11:24:47 arniml -- split 4k internal ROM into -- + 2k internal ROM -- + 2k external ROM -- EA of t48_core is driven by MSB of internal ROM address -- if upper 2k block is selected, the system switches to EA mode on the fly -- -- Revision 1.9 2004/05/17 14:43:33 arniml -- add testbench peripherals for P1 and P2 -- this became necessary to observe a difference between externally applied -- port data and internally applied port data -- -- Revision 1.8 2004/04/25 20:41:48 arniml -- connect if_timing to P2 output of T48 -- -- Revision 1.7 2004/04/25 16:23:21 arniml -- added if_timing -- -- Revision 1.6 2004/04/14 20:57:44 arniml -- wait for instruction strobe after final end-of-simulation detection -- this ensures that the last mov instruction is part of the dump and -- enables 100% matching with i8039 simulator -- -- Revision 1.5 2004/03/29 19:45:15 arniml -- rename pX_limp to pX_low_imp -- -- Revision 1.4 2004/03/28 21:30:25 arniml -- connect prog_n_o -- -- Revision 1.3 2004/03/26 22:39:28 arniml -- enhance simulation result string -- -- Revision 1.2 2004/03/24 23:22:35 arniml -- put ext_ram on falling clock edge to sample the write enable properly -- -- Revision 1.1 2004/03/24 21:42:10 arniml -- initial check-in -- -------------------------------------------------------------------------------
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/7820e39a/hdl/src/vhdl/proc_sys_reset.vhd
30
22280
------------------------------------------------------------------------------- -- proc_sys_reset - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************ -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2012 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: proc_sys_reset.vhd -- Version: v4.00a -- Description: Parameterizeable top level processor reset module. -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: This section should show the hierarchical structure of the -- designs.Separate lines with blank lines if necessary to improve -- readability. -- -- proc_sys_reset.vhd -- upcnt_n.vhd -- lpf.vhd -- sequence.vhd ------------------------------------------------------------------------------- -- Author: rolandp -- History: -- kc 11/07/01 -- First version -- -- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to -- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to -- C_AUX_RESET_HIGH to match generics used in -- MicroBlaze. Added the DCM Lock as an input -- to keep reset active until after the Lock -- is valid. -- lcw 10/11/2004 -- Updated for NCSim -- Ravi 09/14/2006 -- Added Attributes for synthesis -- rolandp 04/16/2007 -- version 2.00a -- ~~~~~~~ -- SK 03/11/10 -- ^^^^^^^ -- 1. Updated the core so support the active low "Interconnect_aresetn" and -- "Peripheral_aresetn" signals. -- ^^^^^^^ -- ~~~~~~~ -- SK 05/12/11 -- ^^^^^^^ -- 1. Updated the core so remove the support for PPC related functionality. -- ^^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; library proc_sys_reset_v5_0; use proc_sys_reset_v5_0.all; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- -- Definition of Generics: -- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting -- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting -- C_EXT_RESET_HIGH -- External Reset Active High or Active Low -- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low -- C_NUM_BUS_RST -- Number of Bus Structures reset to generate -- C_NUM_PERP_RST -- Number of Peripheral resets to generate -- -- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect -- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral -- Definition of Ports: -- slowest_sync_clk -- Clock -- ext_reset_in -- External Reset Input -- aux_reset_in -- Auxiliary Reset Input -- mb_debug_sys_rst -- MDM Reset Input -- dcm_locked -- DCM Locked, hold system in reset until 1 -- mb_reset -- MB core reset out -- bus_struct_reset -- Bus structure reset out -- peripheral_reset -- Peripheral reset out -- interconnect_aresetn -- Interconnect Bus structure registered rst out -- peripheral_aresetn -- Active Low Peripheral registered reset out ------------------------------------------------------------------------------- entity proc_sys_reset is generic ( C_FAMILY : string := "virtex7"; C_EXT_RST_WIDTH : integer := 4; C_AUX_RST_WIDTH : integer := 4; C_EXT_RESET_HIGH : std_logic := '0'; -- High active input C_AUX_RESET_HIGH : std_logic := '1'; -- High active input C_NUM_BUS_RST : integer := 1; C_NUM_PERP_RST : integer := 1; C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010 C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010 ); port ( slowest_sync_clk : in std_logic; ext_reset_in : in std_logic; aux_reset_in : in std_logic; -- from MDM mb_debug_sys_rst : in std_logic; -- DCM locked information dcm_locked : in std_logic := '1'; -- -- from PPC -- Core_Reset_Req_0 : in std_logic; -- Chip_Reset_Req_0 : in std_logic; -- System_Reset_Req_0 : in std_logic; -- Core_Reset_Req_1 : in std_logic; -- Chip_Reset_Req_1 : in std_logic; -- System_Reset_Req_1 : in std_logic; -- RstcPPCresetcore_0 : out std_logic := '0'; -- RstcPPCresetchip_0 : out std_logic := '0'; -- RstcPPCresetsys_0 : out std_logic := '0'; -- RstcPPCresetcore_1 : out std_logic := '0'; -- RstcPPCresetchip_1 : out std_logic := '0'; -- RstcPPCresetsys_1 : out std_logic := '0'; -- to Microblaze active high reset mb_reset : out std_logic := '0'; -- active high resets bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1) := (others => '0'); peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1) := (others => '0'); -- active low resets interconnect_aresetn : out std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1)) := (others => '1'); peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1)) := (others => '1') ); end entity proc_sys_reset; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture imp of proc_sys_reset is ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Signal and Type Declarations -- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req -- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req -- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req -- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req -- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req -- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0 signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1 signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output signal lpf_reset : std_logic; -- Low pass filtered ext or aux --signal Chip_Reset_Req : std_logic := '0'; --signal System_Reset_Req : std_logic := '0'; signal Bsr_out : std_logic; signal Pr_out : std_logic; -- signal Core_out : std_logic; -- signal Chip_out : std_logic; -- signal Sys_out : std_logic; signal MB_out : std_logic; ------------------------------------------------------------------------------- -- Attributes to synthesis ------------------------------------------------------------------------------- attribute equivalent_register_removal: string; attribute equivalent_register_removal of bus_struct_reset : signal is "no"; attribute equivalent_register_removal of peripheral_reset : signal is "no"; attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; begin ------------------------------------------------------------------------------- -- --------------------- -- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze -- --------------------- -- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate -- begin MB_Reset_PROCESS: process (slowest_sync_clk) begin if (slowest_sync_clk'event and slowest_sync_clk = '1') then mb_reset <= MB_out; end if; end process; -- ---------------------------------------------------------------------------- -- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s) -- ---------------------------------------------------------------------------- BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate BSR_DFF : process (slowest_sync_clk) begin if (slowest_sync_clk'event and slowest_sync_clk = '1') then bus_struct_reset(i) <= Bsr_out; end if; end process; end generate BSR_OUT_DFF; -- --------------------------------------------------------------------------- -- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s) -- --------------------------------------------------------------------------- ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate BSR_DFF : process (slowest_sync_clk) begin if (slowest_sync_clk'event and slowest_sync_clk = '1') then interconnect_aresetn(i) <= not (Bsr_out); end if; end process; end generate ACTIVE_LOW_BSR_OUT_DFF; ------------------------------------------------------------------------------- -- ---------------------------------------------------------------------------- -- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s) -- ---------------------------------------------------------------------------- PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate PR_DFF : process (slowest_sync_clk) begin if (slowest_sync_clk'event and slowest_sync_clk = '1') then peripheral_reset(i) <= Pr_out; end if; end process; end generate PR_OUT_DFF; -- ---------------------------------------------------------------------------- -- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s) -- ---------------------------------------------------------------------------- ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate ACTIVE_LOW_PR_DFF : process (slowest_sync_clk) begin if (slowest_sync_clk'event and slowest_sync_clk = '1') then peripheral_aresetn(i) <= not(Pr_out); end if; end process; end generate ACTIVE_LOW_PR_OUT_DFF; ------------------------------------------------------------------------------- -- This process defines the RstcPPCreset and MB_Reset outputs ------------------------------------------------------------------------------- -- Rstc_output_PROCESS_0: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and -- core_cnt_0(1) and core_cnt_0(0)) -- or Core_out; -- RstcPPCresetchip_0 <= Chip_out; -- RstcPPCresetsys_0 <= Sys_out; -- end if; -- end process; -- Rstc_output_PROCESS_1: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and -- core_cnt_1(1) and core_cnt_1(0)) -- or Core_out; -- RstcPPCresetchip_1 <= Chip_out; -- RstcPPCresetsys_1 <= Sys_out; -- end if; -- end process; ------------------------------------------------------------------------------- --------------------------------------------------------------------------------- ---- This process delays signals so the the edge can be detected and used ---- Double register to sync up with slowest_sync_clk --------------------------------------------------------------------------------- -- DELAY_PROCESS_0: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- core_reset_req_0_d1 <= Core_Reset_Req_0; -- core_reset_req_0_d2 <= core_reset_req_0_d1; -- core_reset_req_0_d3 <= core_reset_req_0_d2; -- end if; -- end process; -- -- DELAY_PROCESS_1: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- core_reset_req_1_d1 <= Core_Reset_Req_1; -- core_reset_req_1_d2 <= core_reset_req_1_d1; -- core_reset_req_1_d3 <= core_reset_req_1_d2; -- end if; -- end process; -- ** -- ------------------------------------------------------------------------------- -- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a -- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks -- ** -- ------------------------------------------------------------------------------- -- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0.UPCNT_N -- ** -- generic map (C_SIZE => 4) -- ** -- port map( -- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); -- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC; -- ** -- Load => '0', -- in STD_LOGIC; -- ** -- Clr => core_req_edge_0, -- in STD_LOGIC; -- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC; -- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) -- ** -- ); -- ** -- -- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0.UPCNT_N -- ** -- generic map (C_SIZE => 4) -- ** -- port map( -- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); -- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC; -- ** -- Load => '0', -- in STD_LOGIC; -- ** -- Clr => core_req_edge_1, -- in STD_LOGIC; -- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC; -- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) -- ** -- ); -- ** -- -- ** -- ------------------------------------------------------------------------------- -- ** -- -- CORE_RESET_PROCESS -- ** -- ------------------------------------------------------------------------------- -- ** -- -- This generates the reset pulse and the count enable to core reset counter -- ** -- -- -- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk) -- ** -- begin -- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1)); -- ** -- --or not core_req_edge_0; -- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3); -- ** -- end if; -- ** -- end process; -- ** -- -- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk) -- ** -- begin -- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1)); -- ** -- --or not core_req_edge_1; -- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3); -- ** -- end if; -- ** -- end process; ------------------------------------------------------------------------------- -- This instantiates a low pass filter to filter both External and Auxiliary -- Reset Inputs. ------------------------------------------------------------------------------- EXT_LPF : entity proc_sys_reset_v5_0.LPF generic map ( C_EXT_RST_WIDTH => C_EXT_RST_WIDTH, C_AUX_RST_WIDTH => C_AUX_RST_WIDTH, C_EXT_RESET_HIGH => C_EXT_RESET_HIGH, C_AUX_RESET_HIGH => C_AUX_RESET_HIGH ) port map( MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic Dcm_locked => dcm_locked, -- in std_logic External_System_Reset => ext_reset_in, -- in std_logic Auxiliary_System_Reset => aux_reset_in, -- in std_logic Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic Lpf_reset => lpf_reset -- out std_logic ); ------------------------------------------------------------------------------- -- This instantiates the sequencer -- This controls the time between resets becoming inactive ------------------------------------------------------------------------------- -- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1; -- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1; SEQ : entity proc_sys_reset_v5_0.SEQUENCE --generic map ( -- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH --) port map( Lpf_reset => lpf_reset, -- in std_logic --System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic --Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic Bsr_out => Bsr_out, -- out std_logic Pr_out => Pr_out, -- out std_logic --Core_out => open, -- Core_out, -- out std_logic --Chip_out => open, -- Chip_out, -- out std_logic --Sys_out => open, -- Sys_out, -- out std_logic MB_out => MB_out); -- out std_logic end imp; --END_SINGLE_FILE_TAG
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma.vhd
2
258518
------------------------------------------------------------------------------- -- axi_vdma ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_vdma.vhd -- Description: This entity is the top level entity for the AXI VDMA core. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_vdma.vhd -- |- axi_vdma_pkg.vhd -- |- axi_vdma_intrpt.vhd -- |- axi_vdma_rst_module.vhd -- | |- axi_vdma_reset.vhd (mm2s) -- | | |- axi_vdma_cdc.vhd -- | |- axi_vdma_reset.vhd (s2mm) -- | | |- axi_vdma_cdc.vhd -- | -- |- axi_vdma_reg_if.vhd -- | |- axi_vdma_lite_if.vhd -- | |- axi_vdma_cdc.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_vdma_sg_cdc.vhd (mm2s) -- |- axi_vdma_vid_cdc.vhd (mm2s) -- |- axi_vdma_fsync_gen.vhd (mm2s) -- |- axi_vdma_sof_gen.vhd (mm2s) -- |- axi_vdma_reg_module.vhd (mm2s) -- | |- axi_vdma_register.vhd (mm2s) -- | |- axi_vdma_regdirect.vhd (mm2s) -- |- axi_vdma_mngr.vhd (mm2s) -- | |- axi_vdma_sg_if.vhd (mm2s) -- | |- axi_vdma_sm.vhd (mm2s) -- | |- axi_vdma_cmdsts_if.vhd (mm2s) -- | |- axi_vdma_vidreg_module.vhd (mm2s) -- | | |- axi_vdma_sgregister.vhd (mm2s) -- | | |- axi_vdma_vregister.vhd (mm2s) -- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s) -- | | |- axi_vdma_blkmem.vhd (mm2s) -- | |- axi_vdma_genlock_mngr.vhd (mm2s) -- | |- axi_vdma_genlock_mux.vhd (mm2s) -- | |- axi_vdma_greycoder.vhd (mm2s) -- |- axi_vdma_mm2s_linebuf.vhd (mm2s) -- | |- axi_vdma_sfifo_autord.vhd (mm2s) -- | |- axi_vdma_afifo_autord.vhd (mm2s) -- | |- axi_vdma_skid_buf.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (mm2s) -- | -- |- axi_vdma_sg_cdc.vhd (s2mm) -- |- axi_vdma_vid_cdc.vhd (s2mm) -- |- axi_vdma_fsync_gen.vhd (s2mm) -- |- axi_vdma_sof_gen.vhd (s2mm) -- |- axi_vdma_reg_module.vhd (s2mm) -- | |- axi_vdma_register.vhd (s2mm) -- | |- axi_vdma_regdirect.vhd (s2mm) -- |- axi_vdma_mngr.vhd (s2mm) -- | |- axi_vdma_sg_if.vhd (s2mm) -- | |- axi_vdma_sm.vhd (s2mm) -- | |- axi_vdma_cmdsts_if.vhd (s2mm) -- | |- axi_vdma_vidreg_module.vhd (s2mm) -- | | |- axi_vdma_sgregister.vhd (s2mm) -- | | |- axi_vdma_vregister.vhd (s2mm) -- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm) -- | | |- axi_vdma_blkmem.vhd (s2mm) -- | |- axi_vdma_genlock_mngr.vhd (s2mm) -- | |- axi_vdma_genlock_mux.vhd (s2mm) -- | |- axi_vdma_greycoder.vhd (s2mm) -- |- axi_vdma_s2mm_linebuf.vhd (s2mm) -- | |- axi_vdma_sfifo_autord.vhd (s2mm) -- | |- axi_vdma_afifo_autord.vhd (s2mm) -- | |- axi_vdma_skid_buf.vhd (s2mm) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_datamover_v5_1.axi_datamover.vhd (FULL) -- |- axi_vdma_v6_2.axi_sg_v4_03.axi_sg.vhd -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_vdma_v6_2; use axi_vdma_v6_2.axi_vdma_pkg.all; --library axi_sg_v4_03; --use axi_sg_v4_03.all; library axi_datamover_v5_1; use axi_datamover_v5_1.all; library lib_cdc_v1_0; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.max2; --use proc_common_v4_0.family_support.all; ------------------------------------------------------------------------------- entity axi_vdma is generic( C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9; -- Address width of the AXI Lite Interface C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32; -- Data width of the AXI Lite Interface C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125; -- Interrupt Delay Timer resolution in usec C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 1; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - all clocks may be asynchronous. ----------------------------------------------------------------------- -- Video Specific Parameters ----------------------------------------------------------------------- C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1; -- Specifies whether video parameters are readable by axi_lite interface -- when configure for Register Direct Mode -- 0 = Disable Video Parameter Reads (Saves FPGA Resources) -- 1 = Enable Video Parameter Reads ----------------------------------------------------------------------- C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1; -- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE -- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE -- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE. ----------------------------------------------------------------------- C_NUM_FSTORES : integer range 1 to 32 := 3; -- Number of Frame Stores C_USE_FSYNC : integer range 0 to 3 := 1; -- 2013.1 : Spilt into C_USE_MM2S_FSYNC & C_USE_S2MM_FSYNC. C_USE_FSYNC is no longer used. C_USE_MM2S_FSYNC : integer range 0 to 1 := 0; --2013.1 -- Specifies MM2S channel operation synchronized to frame sync input -- 0 = channel is Free running -- 1 = channel uses mm2s_fsync as a frame_sync C_USE_S2MM_FSYNC : integer range 0 to 2 := 2; --2013.1 -- Specifies MM2S channel operation synchronized to frame sync input -- 0 = channel is Free running -- 1 = channel uses s2mm_fsync as a frame_sync -- 2 = channel uses s2mm_tuser(0) as a frame_sync C_FLUSH_ON_FSYNC : integer range 0 to 3 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5) -- Specifies VDMA will flush on frame sync -- 0 = Disabled - both channel halts on error detection -- 1 = Enabled - both channel does not halt and will flush on next fsync -- 2 = Enabled - ONLY MM2S channel does not halt and will flush on next fsync -- 3 = Enabled - ONLY S2MM channel does not halt and will flush on next fsync C_INCLUDE_INTERNAL_GENLOCK : integer range 0 to 1 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5) -- Include or exclude the use of internal genlock bus. -- 0 = Exclude internal genlock bus -- 1 = Include internal genlock bus ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_INCLUDE_SG : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Engine -- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode) -- 1 = Include Scatter Gather Engine C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port ----------------------------------------------------------------------- -- Memory Map to Stream (MM2S) Parameters ----------------------------------------------------------------------- C_INCLUDE_MM2S : integer range 0 to 1 := 1; -- Include or exclude MM2S primary data path -- 0 = Exclude MM2S primary data path -- 1 = Include MM2S primary data path C_MM2S_GENLOCK_MODE : integer range 0 to 3 := 3; -- Specifies the Gen-Lock mode for the MM2S Channel -- 0 = Master Mode -- 1 = Slave Mode C_MM2S_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1; -- Specifies the number of Gen-Lock masters a Gen-Lock slave -- can be synchronized with C_MM2S_GENLOCK_REPEAT_EN : integer range 0 to 1 := 0; -- In flush on frame sync mode specifies whether frame number -- will increment on error'ed frame or repeat error'ed frame -- 0 = increment frame -- 1 = repeat frame C_MM2S_SOF_ENABLE : integer range 0 to 1 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5) -- Enable/Disable start of frame generation on tuser(0). -- 0 = disable SOF -- 1 = enable SOF C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0; -- Include or exclude MM2S data realignment engine (DRE) -- 0 = Exclude MM2S DRE -- 1 = Include MM2S DRE C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0; -- Include or exclude MM2S Store And Forward Functionality -- 0 = Exclude MM2S Store and Forward -- 1 = Include MM2S Store and Forward C_MM2S_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- Depth of line buffer. Width of the line buffer is derived from Streaming width. C_MM2S_LINEBUFFER_THRESH : integer range 1 to 65536 := 4; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5) -- Almost Empty Threshold. Threshold point at which MM2S line buffer -- almost empty flag asserts high. Must be a resolution of -- C_M_AXIS_MM2S_TDATA_WIDTH/8 -- Minimum valid value is C_M_AXIS_MM2S_TDATA_WIDTH/8 -- Maximum valid value is C_MM2S_LINEBUFFER_DEPTH C_MM2S_MAX_BURST_LENGTH : integer range 2 to 256 := 8; -- Maximum burst size in databeats per burst request on MM2S Read Port C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Address Width for MM2S Read Port C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 64; -- Master AXI Memory Map Data Width for MM2S Read Port C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32; -- Master AXI Stream Data Width for MM2S Channel C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1; -- Master AXI Stream User Width for MM2S Channel ----------------------------------------------------------------------- -- Stream to Memory Map (S2MM) Parameters ----------------------------------------------------------------------- C_INCLUDE_S2MM : integer range 0 to 1 := 1; -- Include or exclude S2MM primary data path -- 0 = Exclude S2MM primary data path -- 1 = Include S2MM primary data path C_S2MM_GENLOCK_MODE : integer range 0 to 3 := 2; -- Specifies the Gen-Lock mode for the S2MM Channel -- 0 = Master Mode -- 1 = Slave Mode C_S2MM_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1; -- Specifies the number of Gen-Lock masters a Gen-Lock slave -- can be synchronized with C_S2MM_GENLOCK_REPEAT_EN : integer range 0 to 1 := 1; -- In flush on frame sync mode specifies whether frame number -- will increment on error'ed frame or repeat error'ed frame -- 0 = increment frame -- 1 = repeat frame C_S2MM_SOF_ENABLE : integer range 0 to 1 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5) -- Enable/Disable start of frame generation on tuser(0). -- 0 = disable SOF -- 1 = enable SOF C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0; -- Include or exclude S2MM data realignment engine (DRE) -- 0 = Exclude S2MM DRE -- 1 = Include S2MM DRE C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1; -- Include or exclude MM2S Store And Forward Functionality -- 0 = Exclude S2MM Store and Forward -- 1 = Include S2MM Store and Forward C_S2MM_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- Depth of line buffer. Width of the line buffer is derived from Streaming width. C_S2MM_LINEBUFFER_THRESH : integer range 1 to 65536 := 4; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5) -- Almost Full Threshold. Threshold point at which S2MM line buffer -- almost full flag asserts high. Must be a resolution of -- C_M_AXIS_MM2S_TDATA_WIDTH/8 -- Minimum valid value is C_S_AXIS_S2MM_TDATA_WIDTH/8 -- Maximum valid value is C_S2MM_LINEBUFFER_DEPTH C_S2MM_MAX_BURST_LENGTH : integer range 2 to 256 := 8; -- Maximum burst size in data beats per burst request on S2MM Write Port C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Address Width for S2MM Write Port C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 64; -- Master AXI Memory Map Data Width for MM2SS2MMWrite Port C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32; -- Slave AXI Stream Data Width for S2MM Channel C_S_AXIS_S2MM_TUSER_BITS : integer range 1 to 1 := 1; -- Slave AXI Stream User Width for S2MM Channel --C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '0'); -- Enable debug information C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 0; -- Setting this make core backward compatible to 2012.4 version in terms of ports and registers C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 0; -- Enable debug information bit 0 C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 0; -- Enable debug information bit 1 C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 0; -- Enable debug information bit 2 C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 0; -- Enable debug information bit 3 C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 0; -- Enable debug information bit 4 C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 0; -- Enable debug information bit 5 C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1; -- Enable debug information bit 6 C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1; -- Enable debug information bit 7 C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 0; -- Enable debug information bit 8 C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 0; -- Enable debug information bit 9 C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 0; -- Enable debug information bit 10 C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 0; -- Enable debug information bit 11 C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 0; -- Enable debug information bit 12 C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 0; -- Enable debug information bit 13 C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1; -- Enable debug information bit 14 C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1; -- Enable debug information bit 15 C_INSTANCE : string := "axi_vdma"; C_FAMILY : string := "virtex7" -- Target FPGA Device Family ); port ( -- Control Clocks s_axi_lite_aclk : in std_logic := '0' ; -- m_axi_sg_aclk : in std_logic := '0' ; -- -- MM2S Clocks m_axi_mm2s_aclk : in std_logic := '0' ; -- m_axis_mm2s_aclk : in std_logic := '0' ; -- -- S2MM Clocks m_axi_s2mm_aclk : in std_logic := '0' ; -- s_axis_s2mm_aclk : in std_logic := '0' ; -- axi_resetn : in std_logic := '0' ; -- -- ----------------------------------------------------------------------- -- -- AXI Lite Control Interface -- ----------------------------------------------------------------------- -- -- AXI Lite Write Address Channel -- s_axi_lite_awvalid : in std_logic := '0' ; -- s_axi_lite_awready : out std_logic ; -- s_axi_lite_awaddr : in std_logic_vector -- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- -- -- AXI Lite Write Data Channel -- s_axi_lite_wvalid : in std_logic := '0' ; -- s_axi_lite_wready : out std_logic ; -- s_axi_lite_wdata : in std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- -- -- AXI Lite Write Response Channel -- s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; -- s_axi_lite_bvalid : out std_logic ; -- s_axi_lite_bready : in std_logic := '0' ; -- -- -- AXI Lite Read Address Channel -- s_axi_lite_arvalid : in std_logic := '0' ; -- s_axi_lite_arready : out std_logic ; -- s_axi_lite_araddr : in std_logic_vector -- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- s_axi_lite_rvalid : out std_logic ; -- s_axi_lite_rready : in std_logic := '0' ; -- s_axi_lite_rdata : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; -- -- ----------------------------------------------------------------------- -- -- AXI Video Interface -- ----------------------------------------------------------------------- -- mm2s_fsync : in std_logic := '0' ; -- mm2s_frame_ptr_in : in std_logic_vector -- ((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0) := (others => '0'); -- mm2s_frame_ptr_out : out std_logic_vector(5 downto 0); -- s2mm_fsync : in std_logic := '0'; -- s2mm_frame_ptr_in : in std_logic_vector -- ((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0) := (others => '0'); -- s2mm_frame_ptr_out : out std_logic_vector(5 downto 0); -- mm2s_buffer_empty : out std_logic ; -- mm2s_buffer_almost_empty : out std_logic ; -- s2mm_buffer_full : out std_logic ; -- s2mm_buffer_almost_full : out std_logic ; -- -- mm2s_fsync_out : out std_logic ; -- s2mm_fsync_out : out std_logic ; -- mm2s_prmtr_update : out std_logic ; -- s2mm_prmtr_update : out std_logic ; -- -- ----------------------------------------------------------------------- -- -- AXI Scatter Gather Interface -- ----------------------------------------------------------------------- -- -- Scatter Gather Read Address Channel -- m_axi_sg_araddr : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; -- m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; -- m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; -- m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; -- m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; -- m_axi_sg_arvalid : out std_logic ; -- m_axi_sg_arready : in std_logic := '0'; -- -- -- Memory Map to Stream Scatter Gather Read Data Channel -- m_axi_sg_rdata : in std_logic_vector -- (C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); -- m_axi_sg_rresp : in std_logic_vector(1 downto 0) := (others => '0') ; -- m_axi_sg_rlast : in std_logic := '0'; -- m_axi_sg_rvalid : in std_logic := '0'; -- m_axi_sg_rready : out std_logic ; -- -- ----------------------------------------------------------------------- -- -- AXI MM2S Channel -- ----------------------------------------------------------------------- -- -- Memory Map To Stream Read Address Channel -- m_axi_mm2s_araddr : out std_logic_vector -- (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); -- m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; -- m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; -- m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; -- m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; -- m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; -- m_axi_mm2s_arvalid : out std_logic ; -- m_axi_mm2s_arready : in std_logic := '0'; -- -- -- Memory Map to Stream Read Data Channel -- m_axi_mm2s_rdata : in std_logic_vector -- (C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); -- m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := (others => '0'); -- m_axi_mm2s_rlast : in std_logic := '0'; -- m_axi_mm2s_rvalid : in std_logic := '0'; -- m_axi_mm2s_rready : out std_logic ; -- -- -- Memory Map to Stream Stream Interface -- mm2s_prmry_reset_out_n : out std_logic ; -- m_axis_mm2s_tdata : out std_logic_vector -- (C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); -- m_axis_mm2s_tkeep : out std_logic_vector -- ((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); -- m_axis_mm2s_tuser : out std_logic_vector -- (C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); -- m_axis_mm2s_tvalid : out std_logic ; -- m_axis_mm2s_tready : in std_logic := '0'; -- m_axis_mm2s_tlast : out std_logic ; -- -- ----------------------------------------------------------------------- -- -- AXI S2MM Channel -- ----------------------------------------------------------------------- -- -- Stream to Memory Map Write Address Channel -- m_axi_s2mm_awaddr : out std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; -- m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; -- m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; -- m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; -- m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; -- m_axi_s2mm_awvalid : out std_logic ; -- m_axi_s2mm_awready : in std_logic := '0'; -- -- -- Stream to Memory Map Write Data Channel -- m_axi_s2mm_wdata : out std_logic_vector -- (C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); -- m_axi_s2mm_wstrb : out std_logic_vector -- ((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); -- m_axi_s2mm_wlast : out std_logic ; -- m_axi_s2mm_wvalid : out std_logic ; -- m_axi_s2mm_wready : in std_logic := '0'; -- -- -- Stream to Memory Map Write Response Channel -- m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := (others => '0'); -- m_axi_s2mm_bvalid : in std_logic := '0'; -- m_axi_s2mm_bready : out std_logic ; -- -- -- Stream to Memory Map Steam Interface -- s2mm_prmry_reset_out_n : out std_logic ; -- s_axis_s2mm_tdata : in std_logic_vector -- (C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); -- s_axis_s2mm_tkeep : in std_logic_vector -- ((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); -- s_axis_s2mm_tuser : in std_logic_vector -- (C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0'); -- s_axis_s2mm_tvalid : in std_logic := '0'; -- s_axis_s2mm_tready : out std_logic ; -- s_axis_s2mm_tlast : in std_logic := '0'; -- -- -- -- MM2S and S2MM Channel Interrupts -- mm2s_introut : out std_logic ; -- s2mm_introut : out std_logic ; -- axi_vdma_tstvec : out std_logic_vector(63 downto 0) -- ); ----------------------------------------------------------------- -- Start of PSFUtil MPD attributes ----------------------------------------------------------------- attribute IP_GROUP : string; attribute IP_GROUP of axi_vdma : entity is "LOGICORE"; attribute IPTYPE : string; attribute IPTYPE of axi_vdma : entity is "PERIPHERAL"; attribute RUN_NGCBUILD : string; attribute RUN_NGCBUILD of axi_vdma : entity is "TRUE"; ----------------------------------------------------------------- -- End of PSFUtil MPD attributes ----------------------------------------------------------------- end axi_vdma; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_vdma is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_vdma,{" --& "C_FAMILY= " & C_FAMILY --& ",C_INSTANCE = " & C_INSTANCE --& ",C_DLYTMR_RESOLUTION= " & integer'image(C_DLYTMR_RESOLUTION) --& ",C_PRMRY_IS_ACLK_ASYNC= " & integer'image(C_PRMRY_IS_ACLK_ASYNC) --& ",C_ENABLE_VIDPRMTR_READS= " & integer'image(C_ENABLE_VIDPRMTR_READS) --& ",C_DYNAMIC_RESOLUTION= " & integer'image(C_DYNAMIC_RESOLUTION) --& ",C_NUM_FSTORES= " & integer'image(C_NUM_FSTORES) --& ",C_USE_MM2S_FSYNC= " & integer'image(C_USE_MM2S_FSYNC) --& ",C_USE_S2MM_FSYNC= " & integer'image(C_USE_S2MM_FSYNC) --& ",C_INCLUDE_SG= " & integer'image(C_INCLUDE_SG) --& ",C_INCLUDE_MM2S= " & integer'image(C_INCLUDE_MM2S) --& ",C_MM2S_GENLOCK_MODE= " & integer'image(C_MM2S_GENLOCK_MODE) --& ",C_MM2S_GENLOCK_NUM_MASTERS= " & integer'image(C_MM2S_GENLOCK_NUM_MASTERS) --& ",C_INCLUDE_MM2S_DRE= " & integer'image(C_INCLUDE_MM2S_DRE) --& ",C_MM2S_LINEBUFFER_DEPTH= " & integer'image(C_MM2S_LINEBUFFER_DEPTH) --& ",C_MM2S_MAX_BURST_LENGTH= " & integer'image(C_MM2S_MAX_BURST_LENGTH) --& ",C_M_AXI_MM2S_DATA_WIDTH = " & integer'image(C_M_AXI_MM2S_DATA_WIDTH) --& ",C_M_AXIS_MM2S_TDATA_WIDTH = " & integer'image(C_M_AXIS_MM2S_TDATA_WIDTH) --& ",C_INCLUDE_S2MM= " & integer'image(C_INCLUDE_S2MM) --& ",C_S2MM_GENLOCK_MODE= " & integer'image(C_S2MM_GENLOCK_MODE) --& ",C_S2MM_GENLOCK_NUM_MASTERS= " & integer'image(C_S2MM_GENLOCK_NUM_MASTERS) --& ",C_INCLUDE_S2MM_DRE= " & integer'image(C_INCLUDE_S2MM_DRE) --& ",C_S2MM_LINEBUFFER_DEPTH= " & integer'image(C_S2MM_LINEBUFFER_DEPTH) --& ",C_S2MM_MAX_BURST_LENGTH= " & integer'image(C_S2MM_MAX_BURST_LENGTH) --& ",C_M_AXI_S2MM_DATA_WIDTH= " & integer'image(C_M_AXI_S2MM_DATA_WIDTH) --& ",C_S_AXIS_S2MM_TDATA_WIDTH= " & integer'image(C_S_AXIS_S2MM_TDATA_WIDTH) --& "}"; --attribute CORE_GENERATION_INFO : string; --attribute CORE_GENERATION_INFO of implementation : architecture is C_CORE_GENERATION_INFO; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Major Version number 0, 1, 2, 3 etc. constant VERSION_MAJOR : std_logic_vector (3 downto 0) := X"6" ; -- Minor Version Number 00, 01, 02, etc. constant VERSION_MINOR : std_logic_vector (7 downto 0) := X"20"; -- Version Revision character (EDK) a,b,c,etc constant VERSION_REVISION : std_logic_vector (3 downto 0) := X"0" ; -- Internal build number constant REVISION_NUMBER : string := "Build Number: P80"; --***************************************************************************** --** Scatter Gather Engine Configuration --***************************************************************************** constant SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing -- Number of Fetch Descriptors to Queue constant SG_FTCH_DESC2QUEUE : integer := SG_INCLUDE_DESC_QUEUE * 4; -- Number of Update Descriptors to Queue constant SG_UPDT_DESC2QUEUE : integer := SG_INCLUDE_DESC_QUEUE * 4; -- Number of fetch words per descriptor for channel 1 (MM2S) constant SG_CH1_WORDS_TO_FETCH : integer := 7; -- Number of fetch words per descriptor for channel 2 (S2MM) constant SG_CH2_WORDS_TO_FETCH : integer := 7; -- Number of update words per descriptor for channel 1 (MM2S) constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- No Descriptor update for video -- Number of update words per descriptor for channel 2 (S2MM) constant SG_CH2_WORDS_TO_UPDATE : integer := 1; -- No Descriptor update for video -- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S) constant SG_CH1_FIRST_UPDATE_WORD : integer := 0; -- No Descriptor update for video -- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S) constant SG_CH2_FIRST_UPDATE_WORD : integer := 0; -- No Descriptor update for video -- Enable stale descriptor check for channel 1 constant SG_CH1_ENBL_STALE_ERR : integer := 0; -- Enable stale descriptor check for channel 2 constant SG_CH2_ENBL_STALE_ERR : integer := 0; -- Width of descriptor fetch bus constant M_AXIS_SG_TDATA_WIDTH : integer := 32; -- Width of descriptor pointer update bus constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32; -- Width of descriptor status update bus constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33; -- Include SG Descriptor Updates constant EXCLUDE_DESC_UPDATE : integer := 0; -- No Descriptor update for video -- Include SG Interrupt Logic constant EXCLUDE_INTRPT : integer := 0; -- Interrupt logic external to sg engine -- Include SG Delay Interrupt constant INCLUDE_DLYTMR : integer := 1; constant EXCLUDE_DLYTMR : integer := 0; --***************************************************************************** --** General/Misc Constants --***************************************************************************** --constant C_USE_MM2S_FSYNC : integer :=find_mm2s_fsync(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM); --constant C_USE_S2MM_FSYNC : integer :=find_s2mm_fsync(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM); constant C_USE_S2MM_FSYNC_01 : integer :=find_s2mm_fsync_01(C_USE_S2MM_FSYNC); --constant ENABLE_FLUSH_ON_MM2S_FSYNC : integer :=find_mm2s_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_FLUSH_ON_FSYNC); --constant ENABLE_FLUSH_ON_S2MM_FSYNC : integer :=find_s2mm_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_FLUSH_ON_FSYNC); --constant ENABLE_FLUSH_ON_MM2S_FSYNC : integer :=find_mm2s_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_USE_FSYNC); --constant ENABLE_FLUSH_ON_S2MM_FSYNC : integer :=find_s2mm_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_USE_FSYNC); constant ENABLE_FLUSH_ON_MM2S_FSYNC : integer := C_USE_MM2S_FSYNC; constant ENABLE_FLUSH_ON_S2MM_FSYNC : integer := C_USE_S2MM_FSYNC_01; --***************************************************************************** --** AXI LITE Interface Constants --***************************************************************************** --constant TOTAL_NUM_REGISTER : integer := NUM_REG_TOTAL_REGDIR; constant TOTAL_NUM_REGISTER : integer := get_num_registers(C_INCLUDE_SG,NUM_REG_TOTAL_SG,NUM_REG_TOTAL_REGDIR); constant C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED : integer := calculated_mm2s_tdata_width(C_M_AXIS_MM2S_TDATA_WIDTH); constant C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED : integer := calculated_s2mm_tdata_width(C_S_AXIS_S2MM_TDATA_WIDTH); constant C_MM2S_ENABLE_TKEEP : integer := enable_tkeep_connectivity(C_M_AXIS_MM2S_TDATA_WIDTH,C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED,C_INCLUDE_MM2S_DRE); constant C_S2MM_ENABLE_TKEEP : integer := enable_tkeep_connectivity(C_S_AXIS_S2MM_TDATA_WIDTH,C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED,C_INCLUDE_S2MM_DRE); -- Specifies to register module which channel is which constant CHANNEL_IS_MM2S : integer := 1; constant CHANNEL_IS_S2MM : integer := 0; --***************************************************************************** --** DataMover General Constants --***************************************************************************** -- Primary DataMover Configuration -- DataMover Command / Status FIFO Depth -- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to -- update data fifo full before constant DM_CMDSTS_FIFO_DEPTH : integer := 4; -- DataMover Include Status FIFO constant DM_INCLUDE_STS_FIFO : integer := 1; -- DataMover outstanding address request fifo depth constant DM_ADDR_PIPE_DEPTH : integer := 4; -- Base status vector width constant BASE_STATUS_WIDTH : integer := 8; -- AXI DataMover Full mode value constant AXI_FULL_MODE : integer := 1; -- Datamover clock always synchronous constant DM_CLOCK_SYNC : integer := 0; -- Always allow datamover address requests constant ALWAYS_ALLOW : std_logic := '1'; constant ZERO_VALUE : std_logic_vector(1023 downto 0) := (others => '0'); --***************************************************************************** --** S2MM DataMover Specific Constants --***************************************************************************** -- AXI DataMover mode for S2MM Channel (0 if channel not included) constant S2MM_AXI_FULL_MODE : integer := C_INCLUDE_S2MM * AXI_FULL_MODE; -- CR591965 - Modified for flush on frame sync -- Enable indeterminate BTT on datamover when S2MM Store And Forward Present -- In this mode, the DataMovers S2MM store and forward buffer will be used -- and underflow and overflow will be detected via receive byte compare -- Enable indeterminate BTT on datamover when S2MM flush on frame sync is -- enabled allowing S2MM AXIS stream absorption and prevent datamover -- halt. Overflow and Underfow error detected external to datamover -- in axi_vdma_cmdsts.vhd constant DM_SUPPORT_INDET_BTT : integer := 1; -- Indterminate BTT Mode additional status vector width constant INDETBTT_ADDED_STS_WIDTH : integer := 24; -- DataMover status width is based on mode of operation constant S2MM_DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH + (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH); -- Never extend on S2MM constant S2MM_DM_CMD_EXTENDED : integer := 0; -- Minimum value required for length width based on burst size and stream dwidth -- If hsize is too small based on setting of burst size and -- dwidth then this will reset the width to a larger mimimum requirement. constant S2MM_DM_BTT_LENGTH_WIDTH : integer := required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED, C_S2MM_MAX_BURST_LENGTH, HSIZE_DWIDTH); constant C_INCLUDE_S2MM_SF_INT : integer := 1; -- Enable store and forward on datamover if data widths are mismatched (allows upsizers -- to be instantiated) or when enabled by user. constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF_INT, C_M_AXI_S2MM_DATA_WIDTH, C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED); --***************************************************************************** --** MM2S DataMover Specific Constants --***************************************************************************** -- AXI DataMover mode for MM2S Channel (0 if channel not included) constant MM2S_AXI_FULL_MODE : integer := C_INCLUDE_MM2S * AXI_FULL_MODE; -- Never extend on MM2S constant MM2S_DM_CMD_NOT_EXTENDED : integer := 0; -- DataMover status width - fixed to 8 for MM2S constant MM2S_DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH; -- Minimum value required for length width based on burst size and stream dwidth -- If hsize is too small based on setting of burst size and -- dwidth then this will reset the width to a larger mimimum requirement. constant MM2S_DM_BTT_LENGTH_WIDTH : integer := required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED, C_MM2S_MAX_BURST_LENGTH, HSIZE_DWIDTH); -- Enable store and forward on datamover if data widths are mismatched (allows upsizers -- to be instantiated) or when enabled by user. ----constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF, ---- C_M_AXI_MM2S_DATA_WIDTH, ---- C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED); ---- constant DM_MM2S_INCLUDE_SF : integer := enable_snf(0, C_M_AXI_MM2S_DATA_WIDTH, C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED); --constant DM_MM2S_INCLUDE_SF : integer := 0; --***************************************************************************** --** Line Buffer Constants --***************************************************************************** -- For LineBuffer, track vertical lines to allow de-assertion of tready -- when s2mm finished with frame. MM2S does not need to track lines constant TRACK_NO_LINES : integer := 0; constant TRACK_LINES : integer := 1; -- zero vector of vsize width used to tie off mm2s line tracking ports constant VSIZE_ZERO : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- Linebuffer default Almost Empty Threshold and Almost Full threshold constant LINEBUFFER_AE_THRESH : integer := 1; constant LINEBUFFER_AF_THRESH : integer := max2(1,C_MM2S_LINEBUFFER_DEPTH/2); -- Include and Exclude settings for linebuffer skid buffers constant INCLUDE_MSTR_SKID_BUFFER : integer := 1; constant EXCLUDE_MSTR_SKID_BUFFER : integer := 0; constant INCLUDE_SLV_SKID_BUFFER : integer := 1; constant EXCLUDE_SLV_SKID_BUFFER : integer := 0; -------- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode -------- Also converts depth in bytes to depth in data beats ------constant MM2S_LINEBUFFER_DEPTH : integer := max2(128,(max2((C_MM2S_LINEBUFFER_DEPTH/(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8)), ------ (C_PRMRY_IS_ACLK_ASYNC*512)))); ------ -------- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode -------- Also converts depth in bytes to depth in data beats ------constant S2MM_LINEBUFFER_DEPTH : integer := max2(128,(max2((C_S2MM_LINEBUFFER_DEPTH/(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8)), ------ (C_PRMRY_IS_ACLK_ASYNC*512)))); ------ --2013.1 --constant MM2S_LINEBUFFER_DEPTH : integer := C_MM2S_LINEBUFFER_DEPTH; --constant S2MM_LINEBUFFER_DEPTH : integer := C_S2MM_LINEBUFFER_DEPTH; -- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode constant MM2S_LINEBUFFER_DEPTH : integer := max2(128,(max2(C_MM2S_LINEBUFFER_DEPTH,(C_PRMRY_IS_ACLK_ASYNC*512)))); -- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode constant S2MM_LINEBUFFER_DEPTH : integer := max2(128,(max2(C_S2MM_LINEBUFFER_DEPTH,(C_PRMRY_IS_ACLK_ASYNC*512)))); -- Enable SOF only for external frame sync and when SOF Enable parameter set ----constant MM2S_SOF_ENABLE : integer := C_USE_MM2S_FSYNC * C_MM2S_SOF_ENABLE; --constant MM2S_SOF_ENABLE : integer := C_MM2S_SOF_ENABLE; constant MM2S_SOF_ENABLE : integer := 1; --constant S2MM_SOF_ENABLE : integer := C_USE_S2MM_FSYNC * C_S2MM_SOF_ENABLE; --constant S2MM_SOF_ENABLE : integer := C_USE_S2MM_FSYNC ; constant S2MM_SOF_ENABLE : integer := C_USE_S2MM_FSYNC_01 ; --***************************************************************************** --** GenLock Constants --***************************************************************************** -- GenLock Data Widths for Clock Domain Crossing Module constant MM2S_GENLOCK_SLVE_PTR_DWIDTH : integer := (C_MM2S_GENLOCK_NUM_MASTERS*NUM_FRM_STORE_WIDTH); constant S2MM_GENLOCK_SLVE_PTR_DWIDTH : integer := (C_S2MM_GENLOCK_NUM_MASTERS*NUM_FRM_STORE_WIDTH); --constant INTERNAL_GENLOCK_ENABLE : integer := enable_internal_genloc(C_INCLUDE_MM2S, C_INCLUDE_S2MM, C_INCLUDE_INTERNAL_GENLOCK, -- C_MM2S_GENLOCK_MODE, -- C_S2MM_GENLOCK_MODE); -- constant INTERNAL_GENLOCK_ENABLE : integer := enable_internal_genloc(C_INCLUDE_MM2S, C_INCLUDE_S2MM, 1, C_MM2S_GENLOCK_MODE, C_S2MM_GENLOCK_MODE); constant C_MM2S_LINEBUFFER_THRESH_INT : integer := calculated_minimum_mm2s_linebuffer_thresh(C_INCLUDE_MM2S, C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED, C_MM2S_LINEBUFFER_DEPTH); constant C_S2MM_LINEBUFFER_THRESH_INT : integer := calculated_minimum_s2mm_linebuffer_thresh(C_INCLUDE_S2MM, C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED, C_S2MM_LINEBUFFER_DEPTH); Constant C_ROOT_FAMILY : string := C_FAMILY; -- function from family_support.vhd ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal mm2s_prmry_resetn : std_logic := '1'; -- AXI MM2S Primary Reset signal mm2s_dm_prmry_resetn : std_logic := '1'; -- AXI MM2S DataMover Primary Reset (Raw) signal mm2s_axis_resetn : std_logic := '1'; -- AXIS MM2S Primary Reset signal mm2s_axis_linebuf_reset_out : std_logic := '1'; -- AXIS MM2S Primary Reset signal s2mm_axis_linebuf_reset_out : std_logic := '1'; -- AXIS MM2S Primary Reset signal s2mm_axis_linebuf_reset_out_inv : std_logic := '1'; -- AXIS MM2S Primary Reset signal s2mm_prmry_resetn : std_logic := '1'; -- AXI S2MM Primary Reset signal s2mm_dm_prmry_resetn : std_logic := '1'; -- AXI S2MM DataMover Primary Reset (Raw) signal s2mm_axis_resetn : std_logic := '1'; -- AXIS S2MM Primary Reset signal s_axi_lite_resetn : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only) signal m_axi_sg_resetn : std_logic := '1'; -- AXI Scatter Gather Interface Reset signal m_axi_dm_sg_resetn : std_logic := '1'; -- AXI Scatter Gather Interface Reset (Raw) signal mm2s_hrd_resetn : std_logic := '1'; -- AXI Hard Reset Only for MM2S signal s2mm_hrd_resetn : std_logic := '1'; -- AXI Hard Reset Only for S2MM -- MM2S Register Module Signals signal mm2s_stop : std_logic := '0'; signal mm2s_stop_reg : std_logic := '0'; signal mm2s_halted_clr : std_logic := '0'; signal mm2s_halted_set : std_logic := '0'; signal mm2s_idle_set : std_logic := '0'; signal mm2s_idle_clr : std_logic := '0'; signal mm2s_dma_interr_set : std_logic := '0'; signal mm2s_dma_interr_set_minus_frame_errors : std_logic := '0'; signal mm2s_dma_slverr_set : std_logic := '0'; signal mm2s_dma_decerr_set : std_logic := '0'; signal mm2s_ioc_irq_set : std_logic := '0'; signal mm2s_dly_irq_set : std_logic := '0'; signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0'); signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0'); signal mm2s_new_curdesc_wren : std_logic := '0'; signal mm2s_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal mm2s_tailpntr_updated : std_logic := '0'; signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal mm2s_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal mm2s_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal mm2s_num_frame_store : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); signal mm2s_linebuf_threshold : std_logic_vector(THRESH_MSB_BIT downto 0) := (others => '0'); signal mm2s_packet_sof : std_logic := '0'; signal mm2s_all_idle : std_logic := '0'; signal mm2s_cmdsts_idle : std_logic := '0'; signal mm2s_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal mm2s_chnl_current_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal mm2s_genlock_pair_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal mm2s_crnt_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); signal mm2s_crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); signal mm2s_dlyirq_dsble : std_logic := '0'; signal mm2s_irqthresh_rstdsbl : std_logic := '0'; signal mm2s_valid_video_prmtrs : std_logic := '0'; signal mm2s_all_lines_xfred : std_logic := '0'; signal mm2s_all_lines_xfred_s : std_logic := '0'; signal mm2s_all_lines_xfred_s_dwidth : std_logic := '0'; signal mm2s_fsize_mismatch_err : std_logic := '0'; -- CR591965 signal mm2s_lsize_mismatch_err : std_logic := '0'; -- CR591965 signal mm2s_lsize_more_mismatch_err : std_logic := '0'; -- CR591965 signal mm2s_frame_ptr_out_i : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); signal mm2s_to_s2mm_fsync : std_logic := '0'; -- MM2S Register Direct Support signal mm2s_regdir_idle : std_logic := '0'; signal mm2s_prmtr_updt_complete : std_logic := '0'; signal mm2s_reg_module_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0); signal mm2s_reg_module_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0); signal mm2s_reg_module_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0); signal mm2s_reg_module_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0); signal mm2s_reg_module_strt_addr : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1); -- MM2S Register Interface Signals signal mm2s_axi2ip_wrce : std_logic_vector(TOTAL_NUM_REGISTER-1 downto 0) := (others => '0'); signal mm2s_axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0') ; signal mm2s_axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0') ; --signal mm2s_axi2ip_rden : std_logic := '0'; signal mm2s_ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0') ; --signal mm2s_ip2axi_rddata_valid : std_logic := '0'; signal mm2s_ip2axi_frame_ptr_ref : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal mm2s_ip2axi_frame_store : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal mm2s_ip2axi_introut : std_logic := '0'; -- MM2S Scatter Gather clock domain crossing signals signal mm2s_cdc2sg_run_stop : std_logic := '0'; signal mm2s_cdc2sg_stop : std_logic := '0'; signal mm2s_cdc2sg_taildesc_wren : std_logic := '0'; signal mm2s_cdc2sg_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal mm2s_cdc2sg_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal mm2s_sg2cdc_ftch_idle : std_logic := '0'; signal mm2s_sg2cdc_ftch_interr_set : std_logic := '0'; signal mm2s_sg2cdc_ftch_slverr_set : std_logic := '0'; signal mm2s_sg2cdc_ftch_decerr_set : std_logic := '0'; -- MM2S DMA Controller Signals signal mm2s_ftch_idle : std_logic := '0'; signal mm2s_updt_ioc_irq_set : std_logic := '0'; signal mm2s_irqthresh_wren : std_logic := '0'; signal mm2s_irqdelay_wren : std_logic := '0'; signal mm2s_ftchcmdsts_idle : std_logic := '0'; -- SG MM2S Descriptor Fetch AXI Stream IN signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_mm2s_ftch_tvalid : std_logic := '0'; signal m_axis_mm2s_ftch_tready : std_logic := '0'; signal m_axis_mm2s_ftch_tlast : std_logic := '0'; -- DataMover MM2S Command Stream Signals signal s_axis_mm2s_cmd_tvalid : std_logic := '0'; signal s_axis_mm2s_cmd_tready : std_logic := '0'; signal s_axis_mm2s_cmd_tdata : std_logic_vector ((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0'); -- DataMover MM2S Status Stream Signals signal m_axis_mm2s_sts_tvalid : std_logic := '0'; signal m_axis_mm2s_sts_tready : std_logic := '0'; signal m_axis_mm2s_sts_tdata : std_logic_vector(MM2S_DM_STATUS_WIDTH - 1 downto 0) := (others => '0'); -- CR608521 signal m_axis_mm2s_sts_tkeep : std_logic_vector((MM2S_DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0'); -- CR608521 signal mm2s_err : std_logic := '0'; signal mm2s_halt : std_logic := '0'; signal mm2s_halt_reg : std_logic := '0'; signal mm2s_halt_cmplt : std_logic := '0'; -- DataMover To Line Buffer AXI Stream Signals signal dm2linebuf_mm2s_tdata : std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0); signal dm2linebuf_mm2s_tkeep : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8)-1 downto 0); signal dm2linebuf_mm2s_tlast : std_logic := '0'; signal dm2linebuf_mm2s_tvalid : std_logic := '0'; signal linebuf2dm_mm2s_tready : std_logic := '0'; -- MM2S Error Status Control signal mm2s_ftch_interr_set : std_logic := '0'; signal mm2s_ftch_slverr_set : std_logic := '0'; signal mm2s_ftch_decerr_set : std_logic := '0'; -- MM2S Soft Reset support signal mm2s_soft_reset : std_logic := '0'; signal mm2s_soft_reset_clr : std_logic := '0'; -- MM2S SOF generation support signal m_axis_mm2s_tvalid_i : std_logic := '0'; signal m_axis_mm2s_tvalid_i_axis_dw_conv : std_logic := '0'; signal m_axis_mm2s_tlast_i : std_logic := '0'; signal m_axis_mm2s_tlast_i_axis_dw_conv : std_logic := '0'; signal s_axis_s2mm_tdata_i : std_logic_vector -- (C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0) := (others => '0'); -- signal s_axis_s2mm_tkeep_i : std_logic_vector -- ((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8)-1 downto 0) := (others => '0'); -- signal s_axis_s2mm_tuser_i : std_logic_vector -- (C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0'); -- signal s_axis_s2mm_tvalid_i : std_logic ; -- signal s_axis_s2mm_tvalid_int : std_logic ; -- signal s_axis_s2mm_tlast_i : std_logic ; signal m_axis_mm2s_tdata_i : std_logic_vector -- (C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) := (others => '0'); -- signal m_axis_mm2s_tkeep_i : std_logic_vector -- ((C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8)-1 downto 0) := (others => '0'); -- signal m_axis_mm2s_tuser_i : std_logic_vector -- (C_M_AXIS_MM2S_TUSER_BITS-1 downto 0) := (others => '0'); -- signal m_axis_mm2s_tready_i : std_logic ; -- -- S2MM Register Module Signals signal s2mm_stop : std_logic := '0'; signal s2mm_halted_clr : std_logic := '0'; signal s2mm_halted_set : std_logic := '0'; signal s2mm_idle_set : std_logic := '0'; signal s2mm_idle_clr : std_logic := '0'; signal s2mm_dma_interr_set : std_logic := '0'; signal s2mm_dma_interr_set_minus_frame_errors : std_logic := '0'; signal s2mm_dma_slverr_set : std_logic := '0'; signal s2mm_dma_decerr_set : std_logic := '0'; signal s2mm_ioc_irq_set : std_logic := '0'; signal s2mm_dly_irq_set : std_logic := '0'; signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0'); signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0'); signal s2mm_new_curdesc_wren : std_logic := '0'; signal s2mm_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal s2mm_tailpntr_updated : std_logic := '0'; signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal s2mm_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal s2mm_num_frame_store : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); signal s2mm_linebuf_threshold : std_logic_vector(THRESH_MSB_BIT downto 0) := (others => '0'); signal s2mm_packet_sof : std_logic := '0'; signal s2mm_all_idle : std_logic := '0'; signal s2mm_cmdsts_idle : std_logic := '0'; signal s2mm_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal s2mm_chnl_current_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal s2mm_genlock_pair_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal s2mm_dlyirq_dsble : std_logic := '0'; signal s2mm_irqthresh_rstdsbl : std_logic := '0'; signal s2mm_valid_video_prmtrs : std_logic := '0'; signal s2mm_crnt_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');-- CR575884 signal s2mm_update_frmstore : std_logic := '0'; --CR582182 signal s2mm_frmstr_err_addr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); --CR582182 signal s2mm_all_lines_xfred : std_logic := '0'; -- CR591965 signal all_lasts_rcvd : std_logic := '0'; signal s2mm_capture_hsize_at_uf_err_sig : std_logic_vector(15 downto 0) ; signal s2mm_capture_dm_done_vsize_counter_sig : std_logic_vector(12 downto 0) ; signal s2mm_fsize_mismatch_err_flag : std_logic := '0'; -- CR591965 signal s2mm_fsize_mismatch_err : std_logic := '0'; -- CR591965 signal s2mm_lsize_mismatch_err : std_logic := '0'; -- CR591965 signal s2mm_lsize_more_mismatch_err : std_logic := '0'; -- CR591965 signal s2mm_tuser_fsync : std_logic := '0'; signal s2mm_frame_ptr_out_i : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); signal s2mm_to_mm2s_fsync : std_logic := '0'; -- S2MM Register Direct Support signal s2mm_regdir_idle : std_logic := '0'; signal s2mm_prmtr_updt_complete : std_logic := '0'; signal s2mm_reg_module_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0); signal s2mm_reg_module_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0); signal s2mm_reg_module_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0); signal s2mm_reg_module_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0); signal s2mm_reg_module_strt_addr : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1); -- S2MM Register Interface Signals signal s2mm_axi2ip_wrce : std_logic_vector(TOTAL_NUM_REGISTER-1 downto 0) := (others => '0'); signal s2mm_axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --signal s2mm_axi2ip_rden : std_logic := '0'; signal s2mm_ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --signal s2mm_ip2axi_rddata_valid : std_logic := '0'; signal s2mm_ip2axi_frame_ptr_ref : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal s2mm_ip2axi_frame_store : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal s2mm_ip2axi_introut : std_logic := '0'; -- S2MM Scatter Gather clock domain crossing signals signal s2mm_cdc2sg_run_stop : std_logic := '0'; signal s2mm_cdc2sg_stop : std_logic := '0'; signal s2mm_cdc2sg_taildesc_wren : std_logic := '0'; signal s2mm_cdc2sg_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal s2mm_cdc2sg_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal s2mm_sg2cdc_ftch_idle : std_logic := '0'; signal s2mm_sg2cdc_ftch_interr_set : std_logic := '0'; signal s2mm_sg2cdc_ftch_slverr_set : std_logic := '0'; signal s2mm_sg2cdc_ftch_decerr_set : std_logic := '0'; -- S2MM DMA Controller Signals signal s2mm_desc_flush : std_logic := '0'; signal s2mm_ftch_idle : std_logic := '0'; signal s2mm_irqthresh_wren : std_logic := '0'; signal s2mm_irqdelay_wren : std_logic := '0'; signal s2mm_ftchcmdsts_idle : std_logic := '0'; -- SG S2MM Descriptor Fetch AXI Stream IN signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_s2mm_ftch_tvalid : std_logic := '0'; signal m_axis_s2mm_ftch_tready : std_logic := '0'; signal m_axis_s2mm_ftch_tlast : std_logic := '0'; -- DataMover S2MM Command Stream Signals signal s_axis_s2mm_cmd_tvalid : std_logic := '0'; signal s_axis_s2mm_cmd_tready : std_logic := '0'; signal s_axis_s2mm_cmd_tdata : std_logic_vector ((C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0'); -- DataMover S2MM Status Stream Signals signal m_axis_s2mm_sts_tvalid : std_logic := '0'; signal m_axis_s2mm_sts_tready : std_logic := '0'; signal m_axis_s2mm_sts_tdata : std_logic_vector(S2MM_DM_STATUS_WIDTH - 1 downto 0) := (others => '0'); -- CR608521 signal m_axis_s2mm_sts_tkeep : std_logic_vector((S2MM_DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0'); -- CR608521 signal s2mm_err : std_logic := '0'; signal s2mm_halt : std_logic := '0'; signal s2mm_halt_cmplt : std_logic := '0'; -- Line Buffer To DataMover AXI Stream Signals signal linebuf2dm_s2mm_tdata : std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0); signal linebuf2dm_s2mm_tkeep : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8)-1 downto 0); signal linebuf2dm_s2mm_tlast : std_logic := '0'; signal linebuf2dm_s2mm_tvalid : std_logic := '0'; signal dm2linebuf_s2mm_tready : std_logic := '0'; -- S2MM Error Status Control signal s2mm_ftch_interr_set : std_logic := '0'; signal s2mm_ftch_slverr_set : std_logic := '0'; signal s2mm_ftch_decerr_set : std_logic := '0'; -- S2MM Soft Reset support signal s2mm_soft_reset : std_logic := '0'; signal s2mm_soft_reset_clr : std_logic := '0'; -- S2MM SOF generation support signal s_axis_s2mm_tready_i : std_logic := '0'; signal s_axis_s2mm_tready_i_axis_dw_conv : std_logic := '0'; -- Video specific signal s2mm_frame_sync : std_logic := '0'; signal mm2s_frame_sync : std_logic := '0'; signal mm2s_parameter_update : std_logic := '0'; signal s2mm_parameter_update : std_logic := '0'; -- Line Buffer Support signal mm2s_allbuffer_empty : std_logic := '0'; signal mm2s_dwidth_fifo_pipe_empty : std_logic := '0'; signal mm2s_dwidth_fifo_pipe_empty_m : std_logic := '0'; -- Video CDC support signal mm2s_cdc2dmac_fsync : std_logic := '0'; signal mm2s_dmac2cdc_fsync_out : std_logic := '0'; signal mm2s_dmac2cdc_prmtr_update : std_logic := '0'; signal mm2s_vid2cdc_packet_sof : std_logic := '0'; signal s2mm_cdc2dmac_fsync : std_logic := '0'; signal s2mm_dmac2cdc_fsync_out : std_logic := '0'; signal s2mm_dmac2cdc_prmtr_update : std_logic := '0'; signal s2mm_vid2cdc_packet_sof : std_logic := '0'; -- fsync qualified by valid parameters for frame count -- decrement signal mm2s_valid_frame_sync : std_logic := '0'; signal s2mm_valid_frame_sync : std_logic := '0'; signal mm2s_valid_frame_sync_cmb : std_logic := '0'; signal s2mm_valid_frame_sync_cmb : std_logic := '0'; --signal for test bench and for output signal s2mm_tstvect_err : std_logic := '0'; signal mm2s_tstvect_err : std_logic := '0'; signal s2mm_tstvect_fsync : std_logic := '0'; signal mm2s_tstvect_fsync : std_logic := '0'; signal s2mm_tstvect_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal mm2s_tstvect_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal s2mm_fsync_out_i : std_logic := '0'; signal s2mm_fsync_out_m_i : std_logic := '0'; signal mm2s_fsync_out_i : std_logic := '0'; signal mm2s_mask_fsync_out : std_logic := '0'; signal s2mm_mask_fsync_out : std_logic := '0'; signal mm2s_mstrfrm_tstsync_out : std_logic := '0'; signal s2mm_mstrfrm_tstsync_out : std_logic := '0'; -- Genlock pointer signals signal mm2s_mstrfrm_tstsync : std_logic := '0'; signal mm2s_s_frame_ptr_in : std_logic_vector(MM2S_GENLOCK_SLVE_PTR_DWIDTH-1 downto 0) := (others => '0'); signal mm2s_m_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); signal s2mm_mstrfrm_tstsync : std_logic := '0'; signal s2mm_s_frame_ptr_in : std_logic_vector(S2MM_GENLOCK_SLVE_PTR_DWIDTH-1 downto 0) := (others => '0'); signal s2mm_m_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); signal mm2s_tstvect_frm_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal s2mm_tstvect_frm_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal sg2cdc_ftch_err_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sg2cdc_ftch_err : std_logic := '0'; signal mm2s_ftch_err_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal mm2s_ftch_err : std_logic := '0'; signal s2mm_ftch_err_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal s2mm_ftch_err : std_logic := '0'; -- Internal GenLock bus support signal s2mm_to_mm2s_frame_ptr_in : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); signal mm2s_to_s2mm_frame_ptr_in : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); signal mm2s_reg_index : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_reg_index : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); signal s2mm_fsync_src_select_s : std_logic_vector(1 downto 0) := (others => '0'); signal hold_dummy_tready_low : std_logic := '0'; signal hold_dummy_tready_low2 : std_logic := '0'; signal drop_fsync_d_pulse_gen_fsize_less_err : std_logic := '0'; signal s2mm_tuser_fsync_top : std_logic := '0'; signal s2mm_fsync_core : std_logic := '0'; signal s2mm_chnl_ready : std_logic := '0'; signal s2mm_strm_not_finished : std_logic := '0'; signal s2mm_strm_all_lines_rcvd : std_logic := '0'; signal s2mm_all_vount_rcvd : std_logic := '0'; signal s2mm_fsize_mismatch_err_s : std_logic := '0'; signal s2mm_fsize_less_err_internal_tvalid_gating : std_logic := '0'; signal s2mm_dummy_tready : std_logic := '0'; signal s2mm_fsize_more_or_sof_late_s : std_logic := '0'; signal s2mm_fsize_more_or_sof_late : std_logic := '0'; signal s_axis_s2mm_tdata_signal : std_logic_vector -- (C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); -- signal s_axis_s2mm_tkeep_signal : std_logic_vector -- ((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); -- signal s_axis_s2mm_tuser_signal : std_logic_vector -- (C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0'); -- signal s_axis_s2mm_tvalid_signal : std_logic := '0'; -- signal s_axis_s2mm_tready_signal : std_logic := '0'; -- signal s_axis_s2mm_tlast_signal : std_logic := '0'; -- signal mm2s_fsync_core : std_logic := '0'; signal mm2s_fsize_mismatch_err_s : std_logic := '0'; signal mm2s_fsize_mismatch_err_m : std_logic := '0'; signal MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : std_logic := '0'; signal m_axis_mm2s_tready_i2 : std_logic ; -- signal m_axis_mm2s_tvalid_i2 : std_logic ; -- signal mm2s_fsync_out_m : std_logic := '0'; signal mm2s_fsize_mismatch_err_flag : std_logic := '0'; -- CR591965 signal mm2s_vsize_cntr_clr_flag : std_logic := '0'; -- CR591965 signal mm2s_fsync_d1 : std_logic := '0'; signal mm2s_fsync_d2 : std_logic := '0'; signal mm2s_fsync_fe : std_logic := '0'; signal s2mm_fsync_d1 : std_logic := '0'; signal s2mm_fsync_d2 : std_logic := '0'; signal s2mm_fsync_fe : std_logic := '0'; signal mm2s_buffer_empty_i : std_logic := '0'; signal s2mm_buffer_full_i : std_logic := '0'; signal mm2s_buffer_almost_empty_i : std_logic := '0'; signal s2mm_buffer_almost_full_i : std_logic := '0'; signal mm2s_prmtr_update_i : std_logic := '0'; signal s2mm_prmtr_update_i : std_logic := '0'; signal mm2s_fsync_out_sig : std_logic := '0'; signal s2mm_fsync_out_sig : std_logic := '0'; signal axi_vdma_tstvec_i : std_logic_vector(63 downto 0) := (others => '0'); signal mm2s_prmry_reset_out_n_i : std_logic := '1'; signal s2mm_prmry_reset_out_n_i : std_logic := '1'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ENABLE_MM2S_PRMRY_RESET_OUT_N : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_0 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate begin mm2s_prmry_reset_out_n <= mm2s_prmry_reset_out_n_i; end generate ENABLE_MM2S_PRMRY_RESET_OUT_N; DISABLE_MM2S_PRMRY_RESET_OUT_N : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_0 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate begin mm2s_prmry_reset_out_n <= '1'; end generate DISABLE_MM2S_PRMRY_RESET_OUT_N; ENABLE_MM2S_BUFFER_EMPTY : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate begin mm2s_buffer_empty <= mm2s_buffer_empty_i; mm2s_buffer_almost_empty <= mm2s_buffer_almost_empty_i; end generate ENABLE_MM2S_BUFFER_EMPTY; DISABLE_MM2S_BUFFER_EMPTY : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate begin mm2s_buffer_empty <= '0'; mm2s_buffer_almost_empty <= '0'; end generate DISABLE_MM2S_BUFFER_EMPTY; ENABLE_MM2S_PRMTR_UPDATE : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_2 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate begin mm2s_prmtr_update <= mm2s_prmtr_update_i; end generate ENABLE_MM2S_PRMTR_UPDATE; DISABLE_MM2S_PRMTR_UPDATE : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_2 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate begin mm2s_prmtr_update <= '0'; end generate DISABLE_MM2S_PRMTR_UPDATE; ENABLE_MM2S_FSYNC_OUT : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_3 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate begin mm2s_fsync_out <= mm2s_fsync_out_sig; end generate ENABLE_MM2S_FSYNC_OUT; DISABLE_MM2S_FSYNC_OUT : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_3 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate begin mm2s_fsync_out <= '0'; end generate DISABLE_MM2S_FSYNC_OUT; ENABLE_AXI_VDMA_TSTVEC : if (C_ENABLE_DEBUG_INFO_4 = 1 or C_ENABLE_DEBUG_ALL = 1) generate begin axi_vdma_tstvec <= axi_vdma_tstvec_i; end generate ENABLE_AXI_VDMA_TSTVEC; DISABLE_AXI_VDMA_TSTVEC : if (C_ENABLE_DEBUG_INFO_4 = 0 and C_ENABLE_DEBUG_ALL = 0) generate begin axi_vdma_tstvec <= (others => '0'); end generate DISABLE_AXI_VDMA_TSTVEC; ENABLE_S2MM_PRMRY_RESET_OUT_N : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_8 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate begin s2mm_prmry_reset_out_n <= s2mm_prmry_reset_out_n_i; end generate ENABLE_S2MM_PRMRY_RESET_OUT_N; DISABLE_S2MM_PRMRY_RESET_OUT_N : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_8 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate begin s2mm_prmry_reset_out_n <= '1'; end generate DISABLE_S2MM_PRMRY_RESET_OUT_N; ENABLE_S2MM_BUFFER_FULL : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate begin s2mm_buffer_full <= s2mm_buffer_full_i; s2mm_buffer_almost_full <= s2mm_buffer_almost_full_i; end generate ENABLE_S2MM_BUFFER_FULL; DISABLE_S2MM_BUFFER_FULL : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate begin s2mm_buffer_full <= '0'; s2mm_buffer_almost_full <= '0'; end generate DISABLE_S2MM_BUFFER_FULL; ENABLE_S2MM_PRMTR_UPDATE : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_10 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate begin s2mm_prmtr_update <= s2mm_prmtr_update_i; end generate ENABLE_S2MM_PRMTR_UPDATE; DISABLE_S2MM_PRMTR_UPDATE : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_10 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate begin s2mm_prmtr_update <= '0'; end generate DISABLE_S2MM_PRMTR_UPDATE; ENABLE_S2MM_FSYNC_OUT : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_11 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate begin s2mm_fsync_out <= s2mm_fsync_out_sig; end generate ENABLE_S2MM_FSYNC_OUT; DISABLE_S2MM_FSYNC_OUT : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_11 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate begin s2mm_fsync_out <= '0'; end generate DISABLE_S2MM_FSYNC_OUT; -- AXI DMA Test Vector (For Xilinx Internal Use Only) axi_vdma_tstvec_i(63 downto 59) <= s2mm_tstvect_frm_ptr_out; --- axi_vdma_tstvec_i(58 downto 54) <= mm2s_tstvect_frm_ptr_out; --- axi_vdma_tstvec_i(53 downto 49) <= s2mm_tstvect_frame; --- axi_vdma_tstvec_i(48 downto 44) <= mm2s_tstvect_frame; --- axi_vdma_tstvec_i(43 downto 33) <= (others => '0'); axi_vdma_tstvec_i(32) <= s2mm_strm_all_lines_rcvd; -- axi_vdma_tstvec_i(31) <= s2mm_halt; -- DataMover halt tracking axi_vdma_tstvec_i(30) <= mm2s_halt; -- DataMover halt tracking axi_vdma_tstvec_i(29) <= s2mm_tstvect_err; axi_vdma_tstvec_i(28) <= mm2s_tstvect_err; axi_vdma_tstvec_i(27 downto 24) <= s2mm_tstvect_frm_ptr_out(3 downto 0); -- axi_vdma_tstvec_i(23 downto 20) <= mm2s_tstvect_frm_ptr_out(3 downto 0); -- axi_vdma_tstvec_i(19) <= s2mm_mstrfrm_tstsync_out; axi_vdma_tstvec_i(18) <= mm2s_mstrfrm_tstsync_out; axi_vdma_tstvec_i(17) <= s2mm_dmasr(DMASR_HALTED_BIT); axi_vdma_tstvec_i(16) <= mm2s_dmasr(DMASR_HALTED_BIT); axi_vdma_tstvec_i(15 downto 12) <= s2mm_tstvect_frame(3 downto 0); -- axi_vdma_tstvec_i(11 downto 8) <= mm2s_tstvect_frame(3 downto 0); -- axi_vdma_tstvec_i(7) <= s2mm_tstvect_fsync and not s2mm_mask_fsync_out; axi_vdma_tstvec_i(6) <= mm2s_tstvect_fsync and not mm2s_mask_fsync_out; axi_vdma_tstvec_i(5) <= s2mm_tstvect_fsync; axi_vdma_tstvec_i(4) <= mm2s_tstvect_fsync; axi_vdma_tstvec_i(3) <= s2mm_dummy_tready and s_axis_s2mm_tvalid_signal; axi_vdma_tstvec_i(2) <= s2mm_packet_sof; axi_vdma_tstvec_i(1) <= mm2s_all_lines_xfred; axi_vdma_tstvec_i(0) <= mm2s_packet_sof; GEN_MM2S_D1_REG : process(m_axis_mm2s_aclk) begin if(m_axis_mm2s_aclk'EVENT and m_axis_mm2s_aclk = '1')then mm2s_fsync_d1 <= mm2s_fsync; mm2s_fsync_d2 <= mm2s_fsync_d1; end if; end process GEN_MM2S_D1_REG; mm2s_fsync_fe <= mm2s_fsync_d2 and not mm2s_fsync_d1; GEN_S2MM_D1_REG : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then s2mm_fsync_d1 <= s2mm_fsync; s2mm_fsync_d2 <= s2mm_fsync_d1; end if; end process GEN_S2MM_D1_REG; s2mm_fsync_fe <= s2mm_fsync_d2 and not s2mm_fsync_d1; s2mm_fsize_more_or_sof_late_s <= s2mm_dummy_tready and s_axis_s2mm_tvalid_signal and not s2mm_fsize_less_err_internal_tvalid_gating; --s_axis_s2mm_tready <= s_axis_s2mm_tready_i_axis_dw_conv; --m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i_axis_dw_conv; m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i2; m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i_axis_dw_conv; mm2s_frame_ptr_out <= mm2s_frame_ptr_out_i ; s2mm_frame_ptr_out <= s2mm_frame_ptr_out_i ; --***************************************************************************** --** RESET MODULE ** --***************************************************************************** I_RST_MODULE : entity axi_vdma_v6_2.axi_vdma_rst_module generic map( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_INCLUDE_SG => C_INCLUDE_SG , C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ) port map( ----------------------------------------------------------------------- -- Clock Sources ----------------------------------------------------------------------- s_axi_lite_aclk => s_axi_lite_aclk , m_axi_sg_aclk => m_axi_sg_aclk , m_axi_mm2s_aclk => m_axi_mm2s_aclk , m_axis_mm2s_aclk => m_axis_mm2s_aclk , m_axi_s2mm_aclk => m_axi_s2mm_aclk , s_axis_s2mm_aclk => s_axis_s2mm_aclk , ----------------------------------------------------------------------- -- Hard Reset ----------------------------------------------------------------------- axi_resetn => axi_resetn , ----------------------------------------------------------------------- -- MM2S Soft Reset Support ----------------------------------------------------------------------- mm2s_soft_reset => mm2s_soft_reset , mm2s_soft_reset_clr => mm2s_soft_reset_clr , mm2s_stop => mm2s_stop , mm2s_all_idle => mm2s_ftchcmdsts_idle , mm2s_fsize_mismatch_err => mm2s_fsize_mismatch_err , -- CR591965 mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) , ----------------------------------------------------------------------- -- MM2S Soft Reset Support ----------------------------------------------------------------------- s2mm_soft_reset => s2mm_soft_reset , s2mm_soft_reset_clr => s2mm_soft_reset_clr , s2mm_stop => s2mm_stop , s2mm_all_idle => s2mm_ftchcmdsts_idle , s2mm_fsize_mismatch_err => s2mm_fsize_mismatch_err , -- CR591965 s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) , ----------------------------------------------------------------------- -- SG Status ----------------------------------------------------------------------- ftch_err => sg2cdc_ftch_err , ----------------------------------------------------------------------- -- MM2S Distributed Reset Out ----------------------------------------------------------------------- -- AXI Upsizer and Line Buffer mm2s_prmry_resetn => mm2s_prmry_resetn , -- AXI DataMover Primary Reset (Raw) mm2s_dm_prmry_resetn => mm2s_dm_prmry_resetn , -- AXI Stream Logic Reset mm2s_axis_resetn => mm2s_axis_resetn , -- AXI Stream Reset Outputs mm2s_axis_reset_out_n => mm2s_prmry_reset_out_n_i , ----------------------------------------------------------------------- -- S2MM Distributed Reset Out ----------------------------------------------------------------------- s2mm_prmry_resetn => s2mm_prmry_resetn , -- AXI DataMover Primary Reset (Raw) s2mm_dm_prmry_resetn => s2mm_dm_prmry_resetn , -- AXI Stream Logic Reset s2mm_axis_resetn => s2mm_axis_resetn , -- AXI Stream Reset Outputs s2mm_axis_reset_out_n => s2mm_prmry_reset_out_n_i , ----------------------------------------------------------------------- -- Scatter Gather Distributed Reset Out ----------------------------------------------------------------------- m_axi_sg_resetn => m_axi_sg_resetn , m_axi_dm_sg_resetn => m_axi_dm_sg_resetn , ----------------------------------------------------------------------- -- AXI Lite Interface Reset Out (Hard Only) ----------------------------------------------------------------------- s_axi_lite_resetn => s_axi_lite_resetn , mm2s_hrd_resetn => mm2s_hrd_resetn , s2mm_hrd_resetn => s2mm_hrd_resetn ); --***************************************************************************** --** AXI LITE REGISTER INTERFACE ** --***************************************************************************** ------------------------------------------------------------------------------- -- Provides the s_axi_lite inteface and clock domain crossing between -- axi lite and mm2s/s2mm register modules ------------------------------------------------------------------------------- AXI_LITE_REG_INTERFACE_I : entity axi_vdma_v6_2.axi_vdma_reg_if generic map( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_INCLUDE_SG => C_INCLUDE_SG , C_ENABLE_VIDPRMTR_READS => C_ENABLE_VIDPRMTR_READS , C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL , C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 , C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 , C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 , C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 , C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 , C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 , C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 , C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 , C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 , C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 , C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 , C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 , C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 , C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 , C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 , C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 , C_TOTAL_NUM_REGISTER => TOTAL_NUM_REGISTER , C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH , C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH , C_VERSION_MAJOR => VERSION_MAJOR , C_VERSION_MINOR => VERSION_MINOR , C_VERSION_REVISION => VERSION_REVISION , C_REVISION_NUMBER => REVISION_NUMBER ) port map( ----------------------------------------------------------------------- -- AXI Lite Control Interface ----------------------------------------------------------------------- s_axi_lite_aclk => s_axi_lite_aclk , s_axi_lite_reset_n => s_axi_lite_resetn , s_axi_lite_awvalid => s_axi_lite_awvalid , s_axi_lite_awready => s_axi_lite_awready , s_axi_lite_awaddr => s_axi_lite_awaddr , s_axi_lite_wvalid => s_axi_lite_wvalid , s_axi_lite_wready => s_axi_lite_wready , s_axi_lite_wdata => s_axi_lite_wdata , s_axi_lite_bresp => s_axi_lite_bresp , s_axi_lite_bvalid => s_axi_lite_bvalid , s_axi_lite_bready => s_axi_lite_bready , s_axi_lite_arvalid => s_axi_lite_arvalid , s_axi_lite_arready => s_axi_lite_arready , s_axi_lite_araddr => s_axi_lite_araddr , s_axi_lite_rvalid => s_axi_lite_rvalid , s_axi_lite_rready => s_axi_lite_rready , s_axi_lite_rdata => s_axi_lite_rdata , s_axi_lite_rresp => s_axi_lite_rresp , -- MM2S Register Interface m_axi_mm2s_aclk => m_axi_mm2s_aclk , mm2s_hrd_resetn => mm2s_hrd_resetn , mm2s_axi2ip_wrce => mm2s_axi2ip_wrce , mm2s_axi2ip_wrdata => mm2s_axi2ip_wrdata , mm2s_axi2ip_rdaddr => mm2s_axi2ip_rdaddr , --mm2s_axi2ip_rden => mm2s_axi2ip_rden , mm2s_ip2axi_rddata => mm2s_ip2axi_rddata , --mm2s_ip2axi_rddata_valid => mm2s_ip2axi_rddata_valid , mm2s_ip2axi_frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref , mm2s_ip2axi_frame_store => mm2s_ip2axi_frame_store , mm2s_chnl_current_frame => mm2s_chnl_current_frame , mm2s_genlock_pair_frame => mm2s_genlock_pair_frame , mm2s_ip2axi_introut => mm2s_ip2axi_introut , mm2s_introut => mm2s_introut , -- S2MM Register Interface m_axi_s2mm_aclk => m_axi_s2mm_aclk , s2mm_hrd_resetn => s2mm_hrd_resetn , s2mm_axi2ip_wrce => s2mm_axi2ip_wrce , s2mm_axi2ip_wrdata => s2mm_axi2ip_wrdata , --s2mm_axi2ip_rden => s2mm_axi2ip_rden , s2mm_axi2ip_rdaddr => s2mm_axi2ip_rdaddr , s2mm_ip2axi_rddata => s2mm_ip2axi_rddata , --s2mm_ip2axi_rddata_valid => s2mm_ip2axi_rddata_valid , s2mm_ip2axi_frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref , s2mm_ip2axi_frame_store => s2mm_ip2axi_frame_store , s2mm_capture_dm_done_vsize_counter => s2mm_capture_dm_done_vsize_counter_sig , s2mm_capture_hsize_at_uf_err => s2mm_capture_hsize_at_uf_err_sig , s2mm_chnl_current_frame => s2mm_chnl_current_frame , s2mm_genlock_pair_frame => s2mm_genlock_pair_frame , s2mm_ip2axi_introut => s2mm_ip2axi_introut , s2mm_introut => s2mm_introut ); --***************************************************************************** --** INTERRUPT CONTROLLER ** --***************************************************************************** I_AXI_DMA_INTRPT : entity axi_vdma_v6_2.axi_vdma_intrpt generic map( C_INCLUDE_CH1 => C_INCLUDE_MM2S , C_INCLUDE_CH2 => C_INCLUDE_S2MM , --C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO , C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL , C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 , C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 , C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 , C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 , C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 , C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 , C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 , C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 , C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 , C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 , C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 , C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 , C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 , C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 , C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 , C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 , C_INCLUDE_DLYTMR => INCLUDE_DLYTMR , C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ) port map( m_axi_ch1_aclk => m_axi_mm2s_aclk , m_axi_ch1_aresetn => mm2s_prmry_resetn , m_axi_ch2_aclk => m_axi_s2mm_aclk , m_axi_ch2_aresetn => s2mm_prmry_resetn , ch1_irqthresh_decr => mm2s_tstvect_fsync , ch1_irqthresh_decr_mask => mm2s_fsize_mismatch_err_flag , ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , ch1_dlyirq_dsble => mm2s_dlyirq_dsble , ch1_irqdelay_wren => mm2s_irqdelay_wren , ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) , ch1_irqthresh_wren => mm2s_irqthresh_wren , ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) , ch1_packet_sof => mm2s_packet_sof , ch1_packet_eof => mm2s_tstvect_fsync , ch1_packet_eof_mask => mm2s_fsize_mismatch_err_flag , ch1_ioc_irq_set => mm2s_ioc_irq_set , ch1_dly_irq_set => mm2s_dly_irq_set , ch1_irqdelay_status => mm2s_irqdelay_status , ch1_irqthresh_status => mm2s_irqthresh_status , ch2_irqthresh_decr => s2mm_tstvect_fsync , ch2_irqthresh_decr_mask => s2mm_fsize_mismatch_err_flag , ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , ch2_dlyirq_dsble => s2mm_dlyirq_dsble , ch2_irqdelay_wren => s2mm_irqdelay_wren , ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) , ch2_irqthresh_wren => s2mm_irqthresh_wren , ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) , ch2_packet_sof => s2mm_packet_sof , ch2_packet_eof => s2mm_tstvect_fsync , ch2_packet_eof_mask => s2mm_fsize_mismatch_err_flag , ch2_ioc_irq_set => s2mm_ioc_irq_set , ch2_dly_irq_set => s2mm_dly_irq_set , ch2_irqdelay_status => s2mm_irqdelay_status , ch2_irqthresh_status => s2mm_irqthresh_status ); --***************************************************************************** --** SCATTER GATHER ENGINE ** --***************************************************************************** -- If Scatter Gather Engine is included the instantiate axi_sg GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate ------------------------------------------------------------------------------- -- Scatter Gather Engine ------------------------------------------------------------------------------- I_SG_ENGINE : entity axi_vdma_v6_2.axi_sg generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH , C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE , C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE , C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH , C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE , C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD , C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERR , C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH , C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE , C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD , C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERR , C_INCLUDE_CH1 => C_INCLUDE_MM2S , C_INCLUDE_CH2 => C_INCLUDE_S2MM , C_INCLUDE_DESC_UPDATE => EXCLUDE_DESC_UPDATE , C_INCLUDE_INTRPT => EXCLUDE_INTRPT , C_INCLUDE_DLYTMR => EXCLUDE_DLYTMR , C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION , C_AXIS_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_FAMILY => C_ROOT_FAMILY ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_resetn , dm_resetn => m_axi_dm_sg_resetn , -- Scatter Gather Write Address Channel m_axi_sg_awaddr => open , m_axi_sg_awlen => open , m_axi_sg_awsize => open , m_axi_sg_awburst => open , m_axi_sg_awprot => open , m_axi_sg_awcache => open , m_axi_sg_awvalid => open , m_axi_sg_awready => '0' , -- Scatter Gather Write Data Channel m_axi_sg_wdata => open , m_axi_sg_wstrb => open , m_axi_sg_wlast => open , m_axi_sg_wvalid => open , m_axi_sg_wready => '0' , -- Scatter Gather Write Response Channel m_axi_sg_bresp => "00" , m_axi_sg_bvalid => '0' , m_axi_sg_bready => open , -- Scatter Gather Read Address Channel m_axi_sg_araddr => m_axi_sg_araddr , m_axi_sg_arlen => m_axi_sg_arlen , m_axi_sg_arsize => m_axi_sg_arsize , m_axi_sg_arburst => m_axi_sg_arburst , m_axi_sg_arprot => m_axi_sg_arprot , m_axi_sg_arcache => m_axi_sg_arcache , m_axi_sg_arvalid => m_axi_sg_arvalid , m_axi_sg_arready => m_axi_sg_arready , -- Memory Map to Stream Scatter Gather Read Data Channel m_axi_sg_rdata => m_axi_sg_rdata , m_axi_sg_rresp => m_axi_sg_rresp , m_axi_sg_rlast => m_axi_sg_rlast , m_axi_sg_rvalid => m_axi_sg_rvalid , m_axi_sg_rready => m_axi_sg_rready , -- Channel 1 Control and Status ch1_run_stop => mm2s_cdc2sg_run_stop , ch1_desc_flush => mm2s_cdc2sg_stop , ch1_ftch_idle => mm2s_sg2cdc_ftch_idle , ch1_ftch_interr_set => mm2s_sg2cdc_ftch_interr_set , ch1_ftch_slverr_set => mm2s_sg2cdc_ftch_slverr_set , ch1_ftch_decerr_set => mm2s_sg2cdc_ftch_decerr_set , ch1_ftch_err_early => open , ch1_ftch_stale_desc => open , ch1_updt_idle => open , ch1_updt_ioc_irq_set => open , ch1_updt_interr_set => open , ch1_updt_slverr_set => open , ch1_updt_decerr_set => open , ch1_dma_interr_set => open , ch1_dma_slverr_set => open , ch1_dma_decerr_set => open , ch1_tailpntr_enabled => '1' , ch1_taildesc_wren => mm2s_cdc2sg_taildesc_wren , ch1_taildesc => mm2s_cdc2sg_taildesc , ch1_curdesc => mm2s_cdc2sg_curdesc , -- Channel 1 Interrupt Coalescing Signals ch1_dlyirq_dsble => '0' , ch1_irqthresh_rstdsbl => '0' , ch1_irqdelay_wren => '0' , ch1_irqdelay => ZERO_VALUE(7 downto 0) , ch1_irqthresh_wren => '0' , ch1_irqthresh => ZERO_VALUE(7 downto 0) , ch1_packet_sof => '0' , ch1_packet_eof => '0' , ch1_ioc_irq_set => open , ch1_dly_irq_set => open , ch1_irqdelay_status => open , ch1_irqthresh_status => open , -- Channel 1 AXI Fetch Stream Out m_axis_ch1_ftch_aclk => m_axi_mm2s_aclk , m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata , m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid , m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready , m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast , -- Channel 1 AXI Update Stream In s_axis_ch1_updt_aclk => '0' , s_axis_ch1_updtptr_tdata => ZERO_VALUE(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0), s_axis_ch1_updtptr_tvalid => '0' , s_axis_ch1_updtptr_tready => open , s_axis_ch1_updtptr_tlast => '0' , s_axis_ch1_updtsts_tdata => ZERO_VALUE(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0), s_axis_ch1_updtsts_tvalid => '0' , s_axis_ch1_updtsts_tready => open , s_axis_ch1_updtsts_tlast => '0' , -- Channel 2 Control and Status ch2_run_stop => s2mm_cdc2sg_run_stop , ch2_desc_flush => s2mm_cdc2sg_stop , ch2_ftch_idle => s2mm_sg2cdc_ftch_idle , ch2_ftch_interr_set => s2mm_sg2cdc_ftch_interr_set , ch2_ftch_slverr_set => s2mm_sg2cdc_ftch_slverr_set , ch2_ftch_decerr_set => s2mm_sg2cdc_ftch_decerr_set , ch2_ftch_err_early => open , ch2_ftch_stale_desc => open , ch2_updt_idle => open , ch2_updt_ioc_irq_set => open , ch2_updt_interr_set => open , ch2_updt_slverr_set => open , ch2_updt_decerr_set => open , ch2_dma_interr_set => open , ch2_dma_slverr_set => open , ch2_dma_decerr_set => open , ch2_tailpntr_enabled => '1' , ch2_taildesc_wren => s2mm_cdc2sg_taildesc_wren , ch2_taildesc => s2mm_cdc2sg_taildesc , ch2_curdesc => s2mm_cdc2sg_curdesc , -- Channel 2 Interrupt Coalescing Signals ch2_dlyirq_dsble => '0' , ch2_irqthresh_rstdsbl => '0' , ch2_irqdelay_wren => '0' , ch2_irqdelay => ZERO_VALUE(7 downto 0) , ch2_irqthresh_wren => '0' , ch2_irqthresh => ZERO_VALUE(7 downto 0) , ch2_packet_sof => '0' , ch2_packet_eof => '0' , ch2_ioc_irq_set => open , ch2_dly_irq_set => open , ch2_irqdelay_status => open , ch2_irqthresh_status => open , -- Channel 2 AXI Fetch Stream Out m_axis_ch2_ftch_aclk => m_axi_s2mm_aclk , m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata , m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid , m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready , m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast , -- Channel 2 AXI Update Stream In s_axis_ch2_updt_aclk => '0' , s_axis_ch2_updtptr_tdata => ZERO_VALUE(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0), s_axis_ch2_updtptr_tvalid => '0' , s_axis_ch2_updtptr_tready => open , s_axis_ch2_updtptr_tlast => '0' , s_axis_ch2_updtsts_tdata => ZERO_VALUE(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0), s_axis_ch2_updtsts_tvalid => '0' , s_axis_ch2_updtsts_tready => open , s_axis_ch2_updtsts_tlast => '0' , -- Error addresses ftch_error_addr => sg2cdc_ftch_err_addr , ftch_error => sg2cdc_ftch_err , updt_error => open , updt_error_addr => open ); --********************************************************************* --** MM2S Clock Domain To/From Scatter Gather Clock Domain ** --********************************************************************* MM2S_SG_CDC_I : entity axi_vdma_v6_2.axi_vdma_sg_cdc generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ) port map( prmry_aclk => m_axi_mm2s_aclk , prmry_resetn => mm2s_prmry_resetn , scndry_aclk => m_axi_sg_aclk , scndry_resetn => m_axi_sg_resetn , -- From Register Module (Primary Clk Domain) reg2cdc_run_stop => mm2s_dmacr(DMACR_RS_BIT) , reg2cdc_stop => mm2s_stop , reg2cdc_taildesc_wren => mm2s_tailpntr_updated , reg2cdc_taildesc => mm2s_taildesc , reg2cdc_curdesc => mm2s_curdesc , -- To Scatter Gather Engine (Secondary Clk Domain) cdc2sg_run_stop => mm2s_cdc2sg_run_stop , cdc2sg_stop => mm2s_cdc2sg_stop , cdc2sg_taildesc_wren => mm2s_cdc2sg_taildesc_wren , cdc2sg_taildesc => mm2s_cdc2sg_taildesc , cdc2sg_curdesc => mm2s_cdc2sg_curdesc , -- From Scatter Gather Engine (Secondary Clk Domain) sg2cdc_ftch_idle => mm2s_sg2cdc_ftch_idle , sg2cdc_ftch_interr_set => mm2s_sg2cdc_ftch_interr_set , sg2cdc_ftch_slverr_set => mm2s_sg2cdc_ftch_slverr_set , sg2cdc_ftch_decerr_set => mm2s_sg2cdc_ftch_decerr_set , sg2cdc_ftch_err_addr => sg2cdc_ftch_err_addr , sg2cdc_ftch_err => sg2cdc_ftch_err , -- To DMA Controller cdc2dmac_ftch_idle => mm2s_ftch_idle , -- To Register Module cdc2reg_ftch_interr_set => mm2s_ftch_interr_set , cdc2reg_ftch_slverr_set => mm2s_ftch_slverr_set , cdc2reg_ftch_decerr_set => mm2s_ftch_decerr_set , cdc2reg_ftch_err_addr => mm2s_ftch_err_addr , cdc2reg_ftch_err => mm2s_ftch_err ); --********************************************************************* --** S2MM Clock Domain To/From Scatter Gather Clock Domain ** --********************************************************************* S2MM_SG_CDC_I : entity axi_vdma_v6_2.axi_vdma_sg_cdc generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ) port map( prmry_aclk => m_axi_s2mm_aclk , prmry_resetn => s2mm_prmry_resetn , scndry_aclk => m_axi_sg_aclk , scndry_resetn => m_axi_sg_resetn , -- From Register Module (Primary Clk Domain) reg2cdc_run_stop => s2mm_dmacr(DMACR_RS_BIT) , reg2cdc_stop => s2mm_stop , reg2cdc_taildesc_wren => s2mm_tailpntr_updated , reg2cdc_taildesc => s2mm_taildesc , reg2cdc_curdesc => s2mm_curdesc , -- To Scatter Gather Engine (Secondary Clk Domain) cdc2sg_run_stop => s2mm_cdc2sg_run_stop , cdc2sg_stop => s2mm_cdc2sg_stop , cdc2sg_taildesc_wren => s2mm_cdc2sg_taildesc_wren , cdc2sg_taildesc => s2mm_cdc2sg_taildesc , cdc2sg_curdesc => s2mm_cdc2sg_curdesc , -- From Scatter Gather Engine (Secondary Clk Domain) sg2cdc_ftch_idle => s2mm_sg2cdc_ftch_idle , sg2cdc_ftch_interr_set => s2mm_sg2cdc_ftch_interr_set , sg2cdc_ftch_slverr_set => s2mm_sg2cdc_ftch_slverr_set , sg2cdc_ftch_decerr_set => s2mm_sg2cdc_ftch_decerr_set , sg2cdc_ftch_err_addr => sg2cdc_ftch_err_addr , sg2cdc_ftch_err => sg2cdc_ftch_err , -- To DMA Controller cdc2dmac_ftch_idle => s2mm_ftch_idle , -- To Register Module cdc2reg_ftch_interr_set => s2mm_ftch_interr_set , cdc2reg_ftch_slverr_set => s2mm_ftch_slverr_set , cdc2reg_ftch_decerr_set => s2mm_ftch_decerr_set , cdc2reg_ftch_err_addr => s2mm_ftch_err_addr , cdc2reg_ftch_err => s2mm_ftch_err ); end generate GEN_SG_ENGINE; -- No scatter gather engine therefore tie off unused signals GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate begin m_axi_sg_araddr <= (others => '0'); m_axi_sg_arlen <= (others => '0'); m_axi_sg_arsize <= (others => '0'); m_axi_sg_arburst <= (others => '0'); m_axi_sg_arcache <= (others => '0'); m_axi_sg_arprot <= (others => '0'); m_axi_sg_arvalid <= '0'; m_axi_sg_rready <= '0'; mm2s_ftch_idle <= '1'; mm2s_ftch_interr_set <= '0'; mm2s_ftch_slverr_set <= '0'; mm2s_ftch_decerr_set <= '0'; m_axis_mm2s_ftch_tdata <= (others => '0'); m_axis_mm2s_ftch_tvalid <= '0'; m_axis_mm2s_ftch_tlast <= '0'; s2mm_ftch_idle <= '1'; s2mm_ftch_interr_set <= '0'; s2mm_ftch_slverr_set <= '0'; s2mm_ftch_decerr_set <= '0'; m_axis_s2mm_ftch_tdata <= (others => '0'); m_axis_s2mm_ftch_tvalid <= '0'; m_axis_s2mm_ftch_tlast <= '0'; mm2s_ftch_err_addr <= (others => '0'); mm2s_ftch_err <= '0'; s2mm_ftch_err_addr <= (others => '0'); s2mm_ftch_err <= '0'; sg2cdc_ftch_err <= '0'; end generate GEN_NO_SG_ENGINE; --***************************************************************************** --** MM2S CHANNEL ** --***************************************************************************** -- Generate support logic for MM2S GEN_SPRT_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate begin GEN_FLUSH_SOF_MM2S : if (ENABLE_FLUSH_ON_MM2S_FSYNC = 1 and MM2S_SOF_ENABLE = 1) generate begin --m_axis_mm2s_tvalid_i2 <= m_axis_mm2s_tvalid_i_axis_dw_conv when MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S = '0' -- else '0'; m_axis_mm2s_tvalid_i2 <= '0' when MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S = '1' or mm2s_fsync_core = '1' else m_axis_mm2s_tvalid_i_axis_dw_conv; m_axis_mm2s_tready_i2 <= m_axis_mm2s_tready when MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S = '0' else '1'; end generate GEN_FLUSH_SOF_MM2S; GEN_NO_FLUSH_SOF_MM2S : if (ENABLE_FLUSH_ON_MM2S_FSYNC = 0 or MM2S_SOF_ENABLE = 0) generate begin m_axis_mm2s_tvalid_i2 <= m_axis_mm2s_tvalid_i_axis_dw_conv; m_axis_mm2s_tready_i2 <= m_axis_mm2s_tready; end generate GEN_NO_FLUSH_SOF_MM2S; GEN_AXIS_MM2S_DWIDTH_CONV : if (C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED /= C_M_AXIS_MM2S_TDATA_WIDTH) generate constant C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 : integer := C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8; constant C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 : integer := C_M_AXIS_MM2S_TDATA_WIDTH/8; signal m_axis_mm2s_dwidth_tuser_i : std_logic_vector -- (C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) := (others => '0'); -- signal m_axis_mm2s_dwidth_tuser : std_logic_vector -- (C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0) := (others => '0'); -- begin m_axis_mm2s_dwidth_tuser_i(0) <= m_axis_mm2s_tuser_i(0); MM2S_TUSER_CNCT : for i in 1 to C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 generate begin m_axis_mm2s_dwidth_tuser_i(i) <= '0'; end generate MM2S_TUSER_CNCT; m_axis_mm2s_tuser(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0) <= m_axis_mm2s_dwidth_tuser(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); AXIS_MM2S_DWIDTH_CONVERTER_I: entity axi_vdma_v6_2.axi_vdma_mm2s_axis_dwidth_converter generic map(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED , C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , --C_AXIS_SIGNAL_SET => 255 , C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 , C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 => C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 , C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE , ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC, C_AXIS_TID_WIDTH => 1 , C_AXIS_TDEST_WIDTH => 1 , C_FAMILY => C_ROOT_FAMILY ) port map( ACLK => m_axis_mm2s_aclk , ARESETN => mm2s_axis_linebuf_reset_out , ACLKEN => '1' , dm_halt_reg => mm2s_halt_reg , stop_reg => mm2s_stop_reg , crnt_vsize_d2 => mm2s_crnt_vsize_d2 , fsync_out => mm2s_fsync_out_i , mm2s_vsize_cntr_clr_flag => mm2s_vsize_cntr_clr_flag , dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty , all_lines_xfred_s_dwidth => mm2s_all_lines_xfred_s_dwidth , S_AXIS_TVALID => m_axis_mm2s_tvalid_i , S_AXIS_TREADY => m_axis_mm2s_tready_i , S_AXIS_TDATA => m_axis_mm2s_tdata_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) , --S_AXIS_TSTRB => ZERO_VALUE(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) , S_AXIS_TSTRB => m_axis_mm2s_tkeep_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) , S_AXIS_TKEEP => m_axis_mm2s_tkeep_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) , S_AXIS_TLAST => m_axis_mm2s_tlast_i , S_AXIS_TID => ZERO_VALUE(0 downto 0) , S_AXIS_TDEST => ZERO_VALUE(0 downto 0) , S_AXIS_TUSER => m_axis_mm2s_dwidth_tuser_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) , M_AXIS_TVALID => m_axis_mm2s_tvalid_i_axis_dw_conv , M_AXIS_TREADY => m_axis_mm2s_tready_i2 , M_AXIS_TDATA => m_axis_mm2s_tdata(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0) , M_AXIS_TSTRB => open , M_AXIS_TKEEP => m_axis_mm2s_tkeep(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) , M_AXIS_TLAST => m_axis_mm2s_tlast_i_axis_dw_conv , M_AXIS_TID => open , M_AXIS_TDEST => open , M_AXIS_TUSER => m_axis_mm2s_dwidth_tuser(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0) ) ; end generate GEN_AXIS_MM2S_DWIDTH_CONV; GEN_NO_AXIS_MM2S_DWIDTH_CONV : if (C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED = C_M_AXIS_MM2S_TDATA_WIDTH) generate begin m_axis_mm2s_tvalid_i_axis_dw_conv <= m_axis_mm2s_tvalid_i; m_axis_mm2s_tdata <= m_axis_mm2s_tdata_i; m_axis_mm2s_tkeep <= m_axis_mm2s_tkeep_i; m_axis_mm2s_tlast_i_axis_dw_conv <= m_axis_mm2s_tlast_i; m_axis_mm2s_tuser <= m_axis_mm2s_tuser_i; m_axis_mm2s_tready_i <= m_axis_mm2s_tready_i2; mm2s_dwidth_fifo_pipe_empty <= '1'; mm2s_all_lines_xfred_s_dwidth <= '0'; end generate GEN_NO_AXIS_MM2S_DWIDTH_CONV; --************************************************************************* --** MM2S AXI4 Clock Domain - (m_axi_mm2s_aclk) --************************************************************************* --------------------------------------------------------------------------- -- MM2S Register Module --------------------------------------------------------------------------- MM2S_REGISTER_MODULE_I : entity axi_vdma_v6_2.axi_vdma_reg_module generic map( C_TOTAL_NUM_REGISTER => TOTAL_NUM_REGISTER , C_INCLUDE_SG => C_INCLUDE_SG , C_CHANNEL_IS_MM2S => CHANNEL_IS_MM2S , C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC , -- CR591965 C_ENABLE_VIDPRMTR_READS => C_ENABLE_VIDPRMTR_READS , C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE , C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION , --C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO , C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL , C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 , C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 , C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 , C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 , C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 , C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 , C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 , C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 , C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 , C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 , C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 , C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 , C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 , C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 , C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 , C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 , C_LINEBUFFER_THRESH => C_MM2S_LINEBUFFER_THRESH_INT , C_NUM_FSTORES => C_NUM_FSTORES , C_GENLOCK_MODE => C_MM2S_GENLOCK_MODE , C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH , C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH , C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ) port map( prmry_aclk => m_axi_mm2s_aclk , prmry_resetn => mm2s_prmry_resetn , -- Register to AXI Lite Interface axi2ip_wrce => mm2s_axi2ip_wrce , axi2ip_wrdata => mm2s_axi2ip_wrdata , axi2ip_rdaddr => mm2s_axi2ip_rdaddr , --axi2ip_rden => mm2s_axi2ip_rden , axi2ip_rden => '0' , ip2axi_rddata => mm2s_ip2axi_rddata , --ip2axi_rddata_valid => mm2s_ip2axi_rddata_valid , ip2axi_rddata_valid => open , ip2axi_frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref , ip2axi_frame_store => mm2s_ip2axi_frame_store , ip2axi_introut => mm2s_ip2axi_introut , -- Soft Reset soft_reset => mm2s_soft_reset , soft_reset_clr => mm2s_soft_reset_clr , -- DMA Control / Status Register Signals halted_clr => mm2s_halted_clr , halted_set => mm2s_halted_set , idle_set => mm2s_idle_set , idle_clr => mm2s_idle_clr , ioc_irq_set => mm2s_ioc_irq_set , dly_irq_set => mm2s_dly_irq_set , irqdelay_status => mm2s_irqdelay_status , irqthresh_status => mm2s_irqthresh_status , frame_sync => mm2s_frame_sync , fsync_mask => mm2s_mask_fsync_out , new_curdesc_wren => mm2s_new_curdesc_wren , new_curdesc => mm2s_new_curdesc , update_frmstore => '1' , -- Always Update new_frmstr => mm2s_frame_number , tstvect_fsync => mm2s_tstvect_fsync , valid_frame_sync => mm2s_valid_frame_sync , irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , dlyirq_dsble => mm2s_dlyirq_dsble , irqthresh_wren => mm2s_irqthresh_wren , irqdelay_wren => mm2s_irqdelay_wren , tailpntr_updated => mm2s_tailpntr_updated , -- Error Detection Control stop => mm2s_stop , dma_interr_set => mm2s_dma_interr_set , dma_interr_set_minus_frame_errors => mm2s_dma_interr_set_minus_frame_errors , dma_slverr_set => mm2s_dma_slverr_set , dma_decerr_set => mm2s_dma_decerr_set , ftch_slverr_set => mm2s_ftch_slverr_set , ftch_decerr_set => mm2s_ftch_decerr_set , fsize_mismatch_err => mm2s_fsize_mismatch_err , lsize_mismatch_err => mm2s_lsize_mismatch_err , lsize_more_mismatch_err => mm2s_lsize_more_mismatch_err , s2mm_fsize_more_or_sof_late => '0' , -- VDMA Base Registers reg_index => mm2s_reg_index , dmacr => mm2s_dmacr , dmasr => mm2s_dmasr , curdesc => mm2s_curdesc , taildesc => mm2s_taildesc , num_frame_store => mm2s_num_frame_store , linebuf_threshold => mm2s_linebuf_threshold , -- Register Direct Support regdir_idle => mm2s_regdir_idle , prmtr_updt_complete => mm2s_prmtr_updt_complete , reg_module_vsize => mm2s_reg_module_vsize , reg_module_hsize => mm2s_reg_module_hsize , reg_module_stride => mm2s_reg_module_stride , reg_module_frmdly => mm2s_reg_module_frmdly , reg_module_strt_addr => mm2s_reg_module_strt_addr , -- Fetch/Update error addresses frmstr_err_addr => mm2s_frame_number , ftch_err_addr => mm2s_ftch_err_addr ); --------------------------------------------------------------------------- -- MM2S DMA Controller --------------------------------------------------------------------------- I_MM2S_DMA_MNGR : entity axi_vdma_v6_2.axi_vdma_mngr generic map( C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH , C_INCLUDE_SF => DM_MM2S_INCLUDE_SF , C_USE_FSYNC => C_USE_MM2S_FSYNC , -- CR582182 C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC , -- CR591965 C_NUM_FSTORES => C_NUM_FSTORES , C_GENLOCK_MODE => C_MM2S_GENLOCK_MODE , C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION , C_GENLOCK_NUM_MASTERS => C_MM2S_GENLOCK_NUM_MASTERS , --C_GENLOCK_REPEAT_EN => C_MM2S_GENLOCK_REPEAT_EN , -- CR591965 --C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO , C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL , C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 , C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 , C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 , C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 , C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 , C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 , C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 , C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 , C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 , C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 , C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 , C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 , C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 , C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 , C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 , C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 , C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE , C_INCLUDE_SG => C_INCLUDE_SG , -- CR581800 C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH , C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_DM_STATUS_WIDTH => MM2S_DM_STATUS_WIDTH , -- CR608521 C_EXTEND_DM_COMMAND => MM2S_DM_CMD_NOT_EXTENDED , C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE , C_S2MM_SOF_ENABLE => 0 , C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_INCLUDE_S2MM => 0 , C_FAMILY => C_ROOT_FAMILY ) port map( -- Secondary Clock and Reset prmry_aclk => m_axi_mm2s_aclk , prmry_resetn => mm2s_prmry_resetn , soft_reset => mm2s_soft_reset , scndry_aclk => '0' , scndry_resetn => '1' , -- MM2S Control and Status run_stop => mm2s_dmacr(DMACR_RS_BIT) , dmacr_repeat_en => mm2s_dmacr(DMACR_REPEAT_EN_BIT) , dmasr_halt => mm2s_dmasr(DMASR_HALTED_BIT) , sync_enable => mm2s_dmacr(DMACR_SYNCEN_BIT) , regdir_idle => mm2s_regdir_idle , ftch_idle => mm2s_ftch_idle , halt => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , halted_clr => mm2s_halted_clr , halted_set => mm2s_halted_set , idle_set => mm2s_idle_set , idle_clr => mm2s_idle_clr , stop => mm2s_stop , s2mm_dmasr_lsize_less_err => '0' , s2mm_fsize_more_or_sof_late => '0' , capture_hsize_at_uf_err => open , all_idle => mm2s_all_idle , cmdsts_idle => mm2s_cmdsts_idle , ftchcmdsts_idle => mm2s_ftchcmdsts_idle , s2mm_fsync_out_m => '0' , frame_sync => mm2s_frame_sync , mm2s_fsync_out_m => mm2s_fsync_out_m , -- CR616211 update_frmstore => open , -- Not Needed for MM2S channel frmstr_err_addr => open , -- Not Needed for MM2S channel frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref , frame_ptr_in => mm2s_s_frame_ptr_in , frame_ptr_out => mm2s_m_frame_ptr_out , internal_frame_ptr_in => s2mm_to_mm2s_frame_ptr_in , valid_frame_sync => mm2s_valid_frame_sync , valid_frame_sync_cmb => mm2s_valid_frame_sync_cmb , valid_video_prmtrs => mm2s_valid_video_prmtrs , parameter_update => mm2s_parameter_update , circular_prk_mode => mm2s_dmacr(DMACR_CRCLPRK_BIT) , mstr_pntr_ref => mm2s_dmacr(DMACR_PNTR_NUM_MSB downto DMACR_PNTR_NUM_LSB) , genlock_select => mm2s_dmacr(DMACR_GENLOCK_SEL_BIT), line_buffer_empty => mm2s_allbuffer_empty , dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty_m , crnt_vsize => mm2s_crnt_vsize , -- CR616211 num_frame_store => mm2s_num_frame_store , all_lines_xfred => mm2s_all_lines_xfred , -- CR616211 all_lasts_rcvd => all_lasts_rcvd , -- fsize_mismatch_err_flag => mm2s_fsize_mismatch_err_flag , -- CR591965 s2mm_fsize_mismatch_err_s => open , -- Not Needed for MM2S channel drop_fsync_d_pulse_gen_fsize_less_err => '0' , s2mm_strm_all_lines_rcvd => '0' , -- : out std_logic; s2mm_fsync_core => '0' , mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s , -- CR591965 mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m , -- CR591965 fsize_mismatch_err => mm2s_fsize_mismatch_err , -- CR591965 lsize_mismatch_err => mm2s_lsize_mismatch_err , -- CR591965 lsize_more_mismatch_err => mm2s_lsize_more_mismatch_err , -- CR591965 -- Register Direct Support prmtr_updt_complete => mm2s_prmtr_updt_complete , reg_module_vsize => mm2s_reg_module_vsize , reg_module_hsize => mm2s_reg_module_hsize , reg_module_stride => mm2s_reg_module_stride , reg_module_frmdly => mm2s_reg_module_frmdly , reg_module_strt_addr => mm2s_reg_module_strt_addr , -- Fsync signals and Genlock for test vector tstvect_err => mm2s_tstvect_err , tstvect_fsync => mm2s_tstvect_fsync , tstvect_frame => mm2s_tstvect_frame , tstvect_frm_ptr_out => mm2s_tstvect_frm_ptr_out , mstrfrm_tstsync_out => mm2s_mstrfrm_tstsync , -- AXI Stream Timing packet_sof => '1' , -- NOT Used for MM2S -- Primary DMA Errors dma_interr_set => mm2s_dma_interr_set , dma_interr_set_minus_frame_errors => mm2s_dma_interr_set_minus_frame_errors , dma_slverr_set => mm2s_dma_slverr_set , dma_decerr_set => mm2s_dma_decerr_set , -- SG MM2S Descriptor Fetch AXI Stream In m_axis_ftch_tdata => m_axis_mm2s_ftch_tdata , m_axis_ftch_tvalid => m_axis_mm2s_ftch_tvalid , m_axis_ftch_tready => m_axis_mm2s_ftch_tready , m_axis_ftch_tlast => m_axis_mm2s_ftch_tlast , -- Currently Being Processed Descriptor/Frame frame_number => mm2s_frame_number , chnl_current_frame => mm2s_chnl_current_frame , genlock_pair_frame => mm2s_genlock_pair_frame , new_curdesc => mm2s_new_curdesc , new_curdesc_wren => mm2s_new_curdesc_wren , tailpntr_updated => mm2s_tailpntr_updated , -- User Command Interface Ports (AXI Stream) s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid , s_axis_cmd_tready => s_axis_mm2s_cmd_tready , s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_sts_tvalid => m_axis_mm2s_sts_tvalid , m_axis_sts_tready => m_axis_mm2s_sts_tready , m_axis_sts_tdata => m_axis_mm2s_sts_tdata , m_axis_sts_tkeep => m_axis_mm2s_sts_tkeep , err => mm2s_err , ftch_err => mm2s_ftch_err ); --------------------------------------------------------------------------- -- MM2S Frame sync generator --------------------------------------------------------------------------- MM2S_FSYNC_I : entity axi_vdma_v6_2.axi_vdma_fsync_gen generic map( C_USE_FSYNC => C_USE_MM2S_FSYNC , ENABLE_FLUSH_ON_S2MM_FSYNC => 0 , ENABLE_FLUSH_ON_MM2S_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC , C_INCLUDE_S2MM => 0 , C_INCLUDE_MM2S => 1 , C_SOF_ENABLE => MM2S_SOF_ENABLE -- Always disabled ) port map( prmry_aclk => m_axi_mm2s_aclk , prmry_resetn => mm2s_prmry_resetn , -- Frame Count Enable Support valid_frame_sync_cmb => mm2s_valid_frame_sync_cmb , valid_video_prmtrs => mm2s_valid_video_prmtrs , frmcnt_ioc => mm2s_ioc_irq_set , dmacr_frmcnt_enbl => mm2s_dmacr(DMACR_FRMCNTEN_BIT) , dmasr_frmcnt_status => mm2s_irqthresh_status , mask_fsync_out => mm2s_mask_fsync_out , -- VDMA process status run_stop => mm2s_dmacr(DMACR_RS_BIT) , all_idle => mm2s_all_idle , parameter_update => mm2s_parameter_update , -- VDMA Frame Sync Sources fsync => mm2s_cdc2dmac_fsync , tuser_fsync => '0' , -- Not used by MM2S othrchnl_fsync => s2mm_to_mm2s_fsync , fsync_src_select => mm2s_dmacr(DMACR_FSYNCSEL_MSB downto DMACR_FSYNCSEL_LSB) , -- VDMA frame sync output to core frame_sync => mm2s_frame_sync , -- VDMA frame sync output to ports frame_sync_out => mm2s_dmac2cdc_fsync_out , prmtr_update => mm2s_dmac2cdc_prmtr_update ); -- Clock Domain Crossing between m_axi_mm2s_aclk and m_axis_mm2s_aclk MM2S_VID_CDC_I : entity axi_vdma_v6_2.axi_vdma_vid_cdc generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_GENLOCK_MSTR_PTR_DWIDTH => NUM_FRM_STORE_WIDTH , C_GENLOCK_SLVE_PTR_DWIDTH => MM2S_GENLOCK_SLVE_PTR_DWIDTH , C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ) port map( prmry_aclk => m_axi_mm2s_aclk , prmry_resetn => mm2s_prmry_resetn , scndry_aclk => m_axis_mm2s_aclk , scndry_resetn => mm2s_axis_resetn , -- Genlock internal bus cdc othrchnl_aclk => m_axi_s2mm_aclk , othrchnl_resetn => s2mm_prmry_resetn , othrchnl2cdc_frame_ptr_out => s2mm_frame_ptr_out_i , cdc2othrchnl_frame_ptr_in => s2mm_to_mm2s_frame_ptr_in , cdc2othrchnl_fsync => mm2s_to_s2mm_fsync , -- GenLock Clock Domain Crossing dmac2cdc_frame_ptr_out => mm2s_m_frame_ptr_out , cdc2top_frame_ptr_out => mm2s_frame_ptr_out_i , top2cdc_frame_ptr_in => mm2s_frame_ptr_in , cdc2dmac_frame_ptr_in => mm2s_s_frame_ptr_in , dmac2cdc_mstrfrm_tstsync => mm2s_mstrfrm_tstsync , cdc2dmac_mstrfrm_tstsync => mm2s_mstrfrm_tstsync_out , -- SOF Detection Domain Crossing vid2cdc_packet_sof => mm2s_vid2cdc_packet_sof , cdc2dmac_packet_sof => mm2s_packet_sof , -- Frame Sync Generation Domain Crossing vid2cdc_fsync => mm2s_fsync_core , cdc2dmac_fsync => mm2s_cdc2dmac_fsync , dmac2cdc_fsync_out => mm2s_dmac2cdc_fsync_out , dmac2cdc_prmtr_update => mm2s_dmac2cdc_prmtr_update , cdc2vid_fsync_out => mm2s_fsync_out_i , cdc2vid_prmtr_update => mm2s_prmtr_update_i ); mm2s_fsync_out_sig <= mm2s_fsync_out_i; -- Start of Frame Detection - used for interrupt coalescing MM2S_SOF_I : entity axi_vdma_v6_2.axi_vdma_sof_gen port map( scndry_aclk => m_axis_mm2s_aclk , scndry_resetn => mm2s_axis_resetn , axis_tready => m_axis_mm2s_tready_i2 , ---axis_tvalid => m_axis_mm2s_tvalid_i , axis_tvalid => m_axis_mm2s_tvalid_i2 , fsync => mm2s_fsync_out_i , -- CR622884 packet_sof => mm2s_vid2cdc_packet_sof ); --------------------------------------------------------------------------- -- Primary MM2S Line Buffer --------------------------------------------------------------------------- MM2S_LINEBUFFER_I : entity axi_vdma_v6_2.axi_vdma_mm2s_linebuf generic map( C_DATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED , C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , --C_INCLUDE_MM2S_SF => C_INCLUDE_MM2S_SF , C_INCLUDE_MM2S_SF => 0 , C_INCLUDE_MM2S_DRE => C_MM2S_ENABLE_TKEEP , C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE , C_M_AXIS_MM2S_TUSER_BITS => C_M_AXIS_MM2S_TUSER_BITS , C_TOPLVL_LINEBUFFER_DEPTH => C_MM2S_LINEBUFFER_DEPTH , -- CR625142 ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC, --C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO , C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL , C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 , C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 , C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 , C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 , C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 , C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 , C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 , C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 , C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 , C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 , C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 , C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 , C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 , C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 , C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 , C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 , C_LINEBUFFER_DEPTH => MM2S_LINEBUFFER_DEPTH , C_LINEBUFFER_AE_THRESH => C_MM2S_LINEBUFFER_THRESH_INT , C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_FAMILY => C_ROOT_FAMILY ) port map( ------------------------------------------------------------------- -- AXI Scatter Gather Interface ------------------------------------------------------------------- -- MM2S AXIS Datamover side s_axis_aclk => m_axi_mm2s_aclk , s_axis_resetn => mm2s_prmry_resetn , -- MM2S AXIS Out side m_axis_aclk => m_axis_mm2s_aclk , m_axis_resetn => mm2s_axis_resetn , mm2s_axis_linebuf_reset_out => mm2s_axis_linebuf_reset_out , run_stop => mm2s_dmacr(DMACR_RS_BIT) , s2mm_axis_resetn => s2mm_axis_resetn , s_axis_s2mm_aclk => s_axis_s2mm_aclk , mm2s_fsync => mm2s_fsync_fe , s2mm_fsync => s2mm_fsync_fe , mm2s_fsync_core => mm2s_fsync_core , mm2s_vsize_cntr_clr_flag => mm2s_vsize_cntr_clr_flag , mm2s_fsize_mismatch_err_flag => mm2s_fsize_mismatch_err_flag , MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S => MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S , mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m , mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s , fsync_src_select => mm2s_dmacr(DMACR_FSYNCSEL_MSB downto DMACR_FSYNCSEL_LSB) , -- Graceful shut down control cmdsts_idle => mm2s_cmdsts_idle , dm_halt => mm2s_halt , dm_halt_reg_out => mm2s_halt_reg , stop => mm2s_stop , -- CR623291 stop_reg_out => mm2s_stop_reg , -- CR623291 -- Vertical Line Count control crnt_vsize => mm2s_crnt_vsize , -- CR616211 crnt_vsize_d2_out => mm2s_crnt_vsize_d2 , -- CR616211 fsync_out => mm2s_fsync_out_i , -- CR616211 fsync_out_m => mm2s_fsync_out_m , -- CR616211 frame_sync => mm2s_frame_sync , -- CR616211 -- Threshold linebuf_threshold => mm2s_linebuf_threshold , -- Stream In (Datamover to Linebuffer) s_axis_tdata => dm2linebuf_mm2s_tdata , s_axis_tkeep => dm2linebuf_mm2s_tkeep , s_axis_tlast => dm2linebuf_mm2s_tlast , s_axis_tvalid => dm2linebuf_mm2s_tvalid , s_axis_tready => linebuf2dm_mm2s_tready , -- Stream Out (Linebuffer to AXIS Out) m_axis_tdata => m_axis_mm2s_tdata_i , m_axis_tkeep => m_axis_mm2s_tkeep_i , m_axis_tlast => m_axis_mm2s_tlast_i , m_axis_tvalid => m_axis_mm2s_tvalid_i , m_axis_tready => m_axis_mm2s_tready_i , m_axis_tuser => m_axis_mm2s_tuser_i , -- Fifo Status Flags dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty , dwidth_fifo_pipe_empty_m => mm2s_dwidth_fifo_pipe_empty_m , mm2s_fifo_pipe_empty => mm2s_allbuffer_empty , mm2s_fifo_empty => mm2s_buffer_empty_i , mm2s_fifo_almost_empty => mm2s_buffer_almost_empty_i , mm2s_all_lines_xfred_s_dwidth => mm2s_all_lines_xfred_s_dwidth , mm2s_all_lines_xfred_s => mm2s_all_lines_xfred_s , mm2s_all_lines_xfred => mm2s_all_lines_xfred -- CR616211 ); end generate GEN_SPRT_FOR_MM2S; -- Do not generate support logic for MM2S GEN_NO_SPRT_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate begin -- Register Module Tie-Offs mm2s_ip2axi_rddata <= (others => '0'); --mm2s_ip2axi_rddata_valid <= '0'; mm2s_ip2axi_frame_ptr_ref <= (others => '0'); mm2s_ip2axi_frame_store <= (others => '0'); mm2s_ip2axi_introut <= '0'; mm2s_soft_reset <= '0'; mm2s_irqthresh_rstdsbl <= '0'; mm2s_dlyirq_dsble <= '0'; mm2s_irqthresh_wren <= '0'; mm2s_irqdelay_wren <= '0'; mm2s_tailpntr_updated <= '0'; mm2s_dmacr <= (others => '0'); mm2s_dmasr <= (others => '0'); mm2s_curdesc <= (others => '0'); mm2s_taildesc <= (others => '0'); --internal to mm2s generate (dont really need to tie off) mm2s_num_frame_store <= (others => '0'); mm2s_linebuf_threshold <= (others => '0'); mm2s_regdir_idle <= '0'; mm2s_prmtr_updt_complete <= '0'; mm2s_reg_module_vsize <= (others => '0'); mm2s_reg_module_hsize <= (others => '0'); mm2s_reg_module_stride <= (others => '0'); mm2s_reg_module_frmdly <= (others => '0'); -- Must zero each element of an array of vectors to zero -- all vectors. GEN_MM2S_ZERO_STRT : for i in 0 to C_NUM_FSTORES-1 generate begin mm2s_reg_module_strt_addr(i) <= (others => '0'); end generate GEN_MM2S_ZERO_STRT; -- Line Buffer Tie-Offs linebuf2dm_mm2s_tready <= '0'; m_axis_mm2s_tdata <= (others => '0'); m_axis_mm2s_tdata_i <= (others => '0'); m_axis_mm2s_tkeep <= (others => '0'); m_axis_mm2s_tkeep_i <= (others => '0'); m_axis_mm2s_tlast_i <= '0'; m_axis_mm2s_tlast_i_axis_dw_conv <= '0'; m_axis_mm2s_tuser <= (others => '0'); m_axis_mm2s_tuser_i <= (others => '0'); m_axis_mm2s_tvalid_i <= '0'; m_axis_mm2s_tvalid_i2 <= '0'; m_axis_mm2s_tvalid_i_axis_dw_conv <= '0'; mm2s_allbuffer_empty <= '0'; mm2s_dwidth_fifo_pipe_empty <= '0'; mm2s_buffer_empty_i <= '0'; mm2s_buffer_almost_empty_i <= '0'; mm2s_all_lines_xfred <= '0'; -- SOF generator mm2s_packet_sof <= '0'; -- DMA Controller mm2s_halted_clr <= '0'; mm2s_halted_set <= '0'; mm2s_idle_set <= '0'; mm2s_idle_clr <= '0'; mm2s_frame_number <= (others => '0'); mm2s_chnl_current_frame <= (others => '0'); mm2s_genlock_pair_frame <= (others => '0'); mm2s_new_curdesc <= (others => '0'); mm2s_new_curdesc_wren <= '0'; mm2s_stop <= '0'; mm2s_stop_reg <= '0'; mm2s_all_idle <= '1'; mm2s_cmdsts_idle <= '1'; mm2s_ftchcmdsts_idle <= '1'; m_axis_mm2s_ftch_tready <= '0'; s_axis_mm2s_cmd_tvalid <= '0'; s_axis_mm2s_cmd_tdata <= (others => '0'); m_axis_mm2s_sts_tready <= '0'; mm2s_m_frame_ptr_out <= (others => '0'); mm2s_frame_ptr_out_i <= (others => '0'); s2mm_to_mm2s_frame_ptr_in <= (others => '0'); mm2s_valid_frame_sync <= '0'; mm2s_valid_frame_sync_cmb <= '0'; mm2s_valid_video_prmtrs <= '0'; mm2s_parameter_update <= '0'; mm2s_tstvect_err <= '0'; mm2s_tstvect_fsync <= '0'; mm2s_tstvect_frame <= (others => '0'); mm2s_dma_interr_set <= '0'; mm2s_dma_interr_set_minus_frame_errors <= '0'; mm2s_dma_slverr_set <= '0'; mm2s_dma_decerr_set <= '0'; mm2s_crnt_vsize <= (others => '0'); mm2s_crnt_vsize_d2 <= (others => '0'); mm2s_fsize_mismatch_err <= '0'; mm2s_lsize_mismatch_err <= '0'; mm2s_lsize_more_mismatch_err <= '0'; -- Frame Sync generator mm2s_frame_sync <= '0'; mm2s_fsync_out_sig <= '0'; mm2s_prmtr_update_i <= '0'; mm2s_mask_fsync_out <= '0'; mm2s_mstrfrm_tstsync <= '0'; mm2s_mstrfrm_tstsync_out <= '0'; mm2s_tstvect_frm_ptr_out <= (others => '0'); mm2s_to_s2mm_fsync <= '0'; end generate GEN_NO_SPRT_FOR_MM2S; --***************************************************************************** --** S2MM CHANNEL ** --***************************************************************************** -- Generate support logic for S2MM GEN_SPRT_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate signal no_fsync_before_vsize_sel_00_01 : std_logic := '0'; begin ------------------------------------------------------------------------------------------------------------------------------------------------------ s2mm_axis_linebuf_reset_out_inv <= not s2mm_axis_linebuf_reset_out; GEN_S2MM_DRE_ON_SKID : if C_S2MM_ENABLE_TKEEP = 1 generate begin --*********************************************************-- --** S2MM SLAVE SKID BUFFER **-- --*********************************************************-- I_S2MM_SKID_FLUSH_SOF : entity axi_vdma_v6_2.axi_vdma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS ) port map( -- System Ports ACLK => s_axis_s2mm_aclk , ARST => s2mm_axis_linebuf_reset_out_inv , -- Shutdown control (assert for 1 clk pulse) skid_stop => '0' , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_tvalid , S_READY => s_axis_s2mm_tready , S_Data => s_axis_s2mm_tdata , S_STRB => s_axis_s2mm_tkeep , S_Last => s_axis_s2mm_tlast , S_User => s_axis_s2mm_tuser , -- Master Side (Stream Data Output) M_VALID => s_axis_s2mm_tvalid_signal , M_READY => s_axis_s2mm_tready_signal , M_Data => s_axis_s2mm_tdata_signal , M_STRB => s_axis_s2mm_tkeep_signal , M_Last => s_axis_s2mm_tlast_signal , M_User => s_axis_s2mm_tuser_signal ); end generate GEN_S2MM_DRE_ON_SKID; GEN_S2MM_DRE_OFF_SKID : if C_S2MM_ENABLE_TKEEP = 0 generate begin --*********************************************************-- --** S2MM SLAVE SKID BUFFER **-- --*********************************************************-- I_S2MM_SKID_FLUSH_SOF : entity axi_vdma_v6_2.axi_vdma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS ) port map( -- System Ports ACLK => s_axis_s2mm_aclk , ARST => s2mm_axis_linebuf_reset_out_inv , -- Shutdown control (assert for 1 clk pulse) skid_stop => '0' , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_tvalid , S_READY => s_axis_s2mm_tready , S_Data => s_axis_s2mm_tdata , --S_STRB => s_axis_s2mm_tkeep , S_STRB => (others => '1') , S_Last => s_axis_s2mm_tlast , S_User => s_axis_s2mm_tuser , -- Master Side (Stream Data Output) M_VALID => s_axis_s2mm_tvalid_signal , M_READY => s_axis_s2mm_tready_signal , M_Data => s_axis_s2mm_tdata_signal , M_STRB => s_axis_s2mm_tkeep_signal , M_Last => s_axis_s2mm_tlast_signal , M_User => s_axis_s2mm_tuser_signal ); end generate GEN_S2MM_DRE_OFF_SKID; GEN_FLUSH_SOF_TREADY : if ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and S2MM_SOF_ENABLE = 1 generate signal s2mm_fsize_less_err_flag_10 : std_logic := '0'; signal s2mm_fsize_less_err_flag_00_01 : std_logic := '0'; signal s_axis_s2mm_tuser_d1 : std_logic := '0'; signal s2mm_tuser_to_fsync_out : std_logic := '0'; signal d_tready_sof_late : std_logic := '0'; signal d_tready_sof_late_cmb : std_logic := '0'; signal s2mm_sof_late_err : std_logic := '0'; signal s2mm_prmtr_or_tail_ptr_updt_complete : std_logic := '0'; signal s2mm_prmtr_updt_complete_s : std_logic := '0'; signal s2mm_dmasr_halted_s : std_logic := '0'; signal d_tready_before_fsync_clr_flag1 : std_logic := '0'; signal d_tready_before_fsync : std_logic := '0'; signal d_tready_before_fsync_cmb : std_logic := '0'; signal d_tready_after_prmtr_updt : std_logic := '0'; signal d_tready_after_prmtr_updt_clrd_till_reset : std_logic := '0'; signal d_tready_after_prmtr_updt_clrd : std_logic := '0'; signal d_tready_sof_late_prmtr_updt : std_logic := '0'; signal d_tready_after_prmtr_updt_clrd_cmb : std_logic := '0'; signal s2mm_sof_late_err_prmtr_updt : std_logic := '0'; signal s2mm_fsync_src_select_s_d1 : std_logic_vector(1 downto 0) := (others => '0'); signal s2mm_dummy_tready_fsync_src_sel_00_or_01 : std_logic := '0'; signal s2mm_dummy_tready_fsync_src_sel_10 : std_logic := '0'; signal d_tready_before_fsync_clr_flag1_sel_00_01 : std_logic := '0'; signal d_tready_before_fsync_clrd_sel_00_01 : std_logic := '0'; signal d_tready_before_fsync_clr_sel_00_01 : std_logic := '0'; signal d_tready_before_fsync_sel_00_01 : std_logic := '0'; signal d_tready_before_fsync_cmb_sel_00_01 : std_logic := '0'; signal d_tready_after_vcount_sel_00_01 : std_logic := '0'; signal after_vcount_flag_sel_00_01 : std_logic := '0'; signal d_tready_after_fsize_less_err_flag_00_01 : std_logic := '0'; signal d_tready_after_fsize_less_err_00_01 : std_logic := '0'; signal s2mm_fsize_less_err_internal_tvalid_gating_10 : std_logic := '0'; signal s2mm_fsize_less_err_internal_tvalid_gating_00_01 : std_logic := '0'; begin no_fsync_before_vsize_sel_00_01 <= d_tready_before_fsync_clr_flag1_sel_00_01; s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid_signal and s2mm_chnl_ready ; s_axis_s2mm_tready_signal <= (s_axis_s2mm_tready_i_axis_dw_conv and s2mm_chnl_ready) or s2mm_dummy_tready; GEN_C_USE_S2MM_FSYNC_1 : if C_USE_S2MM_FSYNC = 1 generate begin s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_00_or_01; s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_00_01; end generate GEN_C_USE_S2MM_FSYNC_1; GEN_C_USE_S2MM_FSYNC_2 : if C_USE_S2MM_FSYNC = 2 generate begin s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_10; s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_10; end generate GEN_C_USE_S2MM_FSYNC_2; ---- FSYNC_SEL_TREADY_S2MM_S : process(s2mm_fsync_src_select_s_d1, ---- s2mm_dummy_tready, ---- s2mm_dummy_tready_fsync_src_sel_00_or_01, ---- s2mm_fsize_less_err_internal_tvalid_gating_10, ---- s2mm_fsize_less_err_internal_tvalid_gating_00_01, ---- s2mm_fsize_less_err_internal_tvalid_gating, ---- s2mm_dummy_tready_fsync_src_sel_10) ---- begin ---- case s2mm_fsync_src_select_s_d1 is ---- ---- when "00" => -- primary fsync (default) ---- s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_00_or_01; ---- s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_00_01; ---- when "01" => -- other channel fsync ---- s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_00_or_01; ---- s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_00_01; ---- when "10" => -- s2mm_tuser_fsync_top_d1 fsync ---- s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_10; ---- s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_10; ---- when others => ---- s2mm_dummy_tready <= '0'; ---- s2mm_fsize_less_err_internal_tvalid_gating <= '0'; ---- end case; ---- end process FSYNC_SEL_TREADY_S2MM_S; ---- ---- ---- ---- D1_S2MM_FSYNC_SRC_SEL_STRM : process(s_axis_s2mm_aclk) ---- begin ---- if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then ---- if(s2mm_axis_resetn = '0')then ---- s2mm_fsync_src_select_s_d1 <= (others => '0'); ---- else ---- s2mm_fsync_src_select_s_d1 <= s2mm_fsync_src_select_s; ---- end if; ---- end if; ---- end process D1_S2MM_FSYNC_SRC_SEL_STRM; ---- --------------------------------------------------TUSER Start------------------------------------------------------------------------------------------------------------------------- s2mm_dummy_tready_fsync_src_sel_10 <= d_tready_sof_late_cmb or d_tready_before_fsync_cmb ; d_tready_sof_late_cmb <= d_tready_sof_late when s2mm_tuser_fsync_top = '0' and s2mm_tuser_to_fsync_out = '0' and s2mm_chnl_ready = '0' else '0'; TUSER_TO_FSYNC_OUT_FLAG : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_axis_resetn = '0' or s2mm_fsync_out_i = '1' )then s2mm_tuser_to_fsync_out <= '0'; elsif(s2mm_tuser_fsync_top = '1' and d_tready_before_fsync_clr_flag1 = '0')then s2mm_tuser_to_fsync_out <= '1'; end if; end if; end process TUSER_TO_FSYNC_OUT_FLAG; s2mm_fsize_less_err_internal_tvalid_gating_10 <= '1' when s2mm_fsize_less_err_flag_10 = '1' and s2mm_tuser_fsync_top = '0' else '0'; FSIZE_LESS_ERR_FLAG_10 : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_axis_resetn = '0' or s2mm_tuser_fsync_top = '1')then s2mm_fsize_less_err_flag_10 <= '0'; elsif(s2mm_fsize_mismatch_err_s = '1')then s2mm_fsize_less_err_flag_10 <= '1'; end if; end if; end process FSIZE_LESS_ERR_FLAG_10; TOP_TUSER_RE_PROCESS : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_axis_resetn = '0')then s_axis_s2mm_tuser_d1 <= '0'; else s_axis_s2mm_tuser_d1 <= s_axis_s2mm_tuser_signal(0) and s_axis_s2mm_tvalid_signal; end if; end if; end process TOP_TUSER_RE_PROCESS; s2mm_tuser_fsync_top <= s_axis_s2mm_tuser_signal(0) and s_axis_s2mm_tvalid_signal and (not s_axis_s2mm_tuser_d1); SOF_LATE_ERR_PULSE_PROCESS : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_axis_resetn = '0' or s2mm_sof_late_err = '1' or s2mm_chnl_ready = '1' or d_tready_before_fsync_clr_flag1 = '1')then s2mm_sof_late_err <= '0'; d_tready_sof_late <= '0'; elsif((s2mm_chnl_ready = '0' or s2mm_fsize_less_err_internal_tvalid_gating_10 = '1') and s_axis_s2mm_tvalid_signal = '1' and s_axis_s2mm_tuser_signal(0) = '0' ) then s2mm_sof_late_err <= '1'; d_tready_sof_late <= '1'; end if; end if; end process SOF_LATE_ERR_PULSE_PROCESS; -------------------------------------------------------------------------------------------------------- d_tready_before_fsync_cmb <= d_tready_before_fsync and d_tready_before_fsync_clr_flag1; GEN_D_TREADY_BEFORE_FSYNC : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(d_tready_before_fsync_clr_flag1 = '0')then d_tready_before_fsync <= '0'; elsif(s2mm_axis_resetn = '1' or s2mm_dmasr_halted_s = '1')then d_tready_before_fsync <= '1'; end if; end if; end process GEN_D_TREADY_BEFORE_FSYNC; VALID_PRM_UPDT_FLAG_10 : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_axis_resetn = '0' or s2mm_dmasr_halted_s = '1')then d_tready_before_fsync_clr_flag1 <= '1'; elsif(s2mm_prmtr_updt_complete_s = '1')then d_tready_before_fsync_clr_flag1 <= '0'; end if; end if; end process VALID_PRM_UPDT_FLAG_10; --------------------------------------------------TUSER End------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------External Fsync Start----------------------------------------------------------------------------------------------------------------------- s2mm_dummy_tready_fsync_src_sel_00_or_01 <= d_tready_after_fsize_less_err_00_01 or d_tready_after_vcount_sel_00_01 or d_tready_before_fsync_cmb_sel_00_01; -------------------------------------------------------------------------------------------------------------- d_tready_after_fsize_less_err_00_01 <= '1' when d_tready_after_fsize_less_err_flag_00_01 = '1' and s2mm_fsync_core = '0' and hold_dummy_tready_low2 = '0' else '0'; TREADY_AFTER_FSIZE_LESS_ERR_FLAG_00_01 : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_axis_resetn = '0' or s2mm_fsync_core = '1' or hold_dummy_tready_low2 = '1')then d_tready_after_fsize_less_err_flag_00_01 <= '0'; elsif(s2mm_fsize_mismatch_err_s = '1')then d_tready_after_fsize_less_err_flag_00_01 <= '1'; end if; end if; end process TREADY_AFTER_FSIZE_LESS_ERR_FLAG_00_01; -------------------------------------------------------------------------------------------------------------- d_tready_after_vcount_sel_00_01 <= '1' when s2mm_fsync_core = '0' and after_vcount_flag_sel_00_01 = '1' and hold_dummy_tready_low = '0' else '0'; REG_S2MM_FSYNC_TO_FSYNC_OUT_FLAG_00_01 : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_axis_resetn = '0' or s2mm_fsync_core = '1' or hold_dummy_tready_low = '1')then after_vcount_flag_sel_00_01 <= '0'; elsif(s2mm_all_vount_rcvd = '1')then after_vcount_flag_sel_00_01 <= '1'; end if; end if; end process REG_S2MM_FSYNC_TO_FSYNC_OUT_FLAG_00_01; -------------------------------------------------------------------------------------------------------------- d_tready_before_fsync_cmb_sel_00_01 <= d_tready_before_fsync_sel_00_01 and d_tready_before_fsync_clr_sel_00_01; GEN_D_TREADY_BEFORE_FSYNC_00_01 : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_fsync_core = '1'and d_tready_before_fsync_clr_flag1_sel_00_01 = '1')then d_tready_before_fsync_sel_00_01 <= '0'; elsif(s2mm_axis_resetn = '1')then d_tready_before_fsync_sel_00_01 <= '1'; end if; end if; end process GEN_D_TREADY_BEFORE_FSYNC_00_01; d_tready_before_fsync_clr_sel_00_01 <= '0' when d_tready_before_fsync_clr_flag1_sel_00_01 = '1' and s2mm_fsync_core = '1' else d_tready_before_fsync_clrd_sel_00_01; REG_INITIAL_FRM_FLAG_00_01 : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_axis_resetn = '0' or s2mm_dmasr_halted_s = '1')then d_tready_before_fsync_clrd_sel_00_01 <= '1'; elsif(s2mm_fsync_core = '1'and d_tready_before_fsync_clr_flag1_sel_00_01 = '1')then d_tready_before_fsync_clrd_sel_00_01 <= '0'; end if; end if; end process REG_INITIAL_FRM_FLAG_00_01; VALID_PRM_UPDT_FLAG_00_01 : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_axis_resetn = '0' or s2mm_dmasr_halted_s = '1')then d_tready_before_fsync_clr_flag1_sel_00_01 <= '0'; elsif(s2mm_prmtr_updt_complete_s = '1')then d_tready_before_fsync_clr_flag1_sel_00_01 <= '1'; end if; end if; end process VALID_PRM_UPDT_FLAG_00_01; ----------------------------------------------------------------------------------- s2mm_fsize_less_err_internal_tvalid_gating_00_01 <= '1' when s2mm_fsize_less_err_flag_00_01 = '1' and s2mm_fsync_core = '0' else '0'; FSIZE_LESS_ERR_FLAG_00_01 : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then if(s2mm_axis_resetn = '0' or s2mm_fsync_core = '1')then s2mm_fsize_less_err_flag_00_01 <= '0'; elsif(s2mm_fsize_mismatch_err_s = '1')then s2mm_fsize_less_err_flag_00_01 <= '1'; end if; end if; end process FSIZE_LESS_ERR_FLAG_00_01; --------------------------------------------------External Fsync End------------------------------------------------------------------------------------------------------------------------- SG_INCLUDED : if C_INCLUDE_SG = 1 generate s2mm_prmtr_or_tail_ptr_updt_complete <= s2mm_tailpntr_updated; end generate SG_INCLUDED; SG_NOT_INCLUDED : if C_INCLUDE_SG = 0 generate s2mm_prmtr_or_tail_ptr_updt_complete <= s2mm_prmtr_updt_complete; end generate SG_NOT_INCLUDED; GEN_FOR_ASYNC_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 1 generate begin ---- S2MM_PRM_UPDT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc ---- generic map( ---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED , ---- C_VECTOR_WIDTH => 1 ---- ) ---- port map ( ---- prmry_aclk => m_axi_s2mm_aclk , ---- prmry_resetn => s2mm_prmry_resetn , ---- scndry_aclk => s_axis_s2mm_aclk , ---- scndry_resetn => s2mm_axis_resetn , ---- scndry_in => '0' , -- Not Used ---- prmry_out => open , -- Not Used ---- prmry_in => s2mm_prmtr_or_tail_ptr_updt_complete , ---- scndry_out => s2mm_prmtr_updt_complete_s , ---- scndry_vect_s_h => '0' , -- Not Used ---- scndry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used ---- prmry_vect_out => open , -- Not Used ---- prmry_vect_s_h => '0' , -- Not Used ---- prmry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used ---- scndry_vect_out => open -- Not Used ---- ); ---- S2MM_PRM_UPDT_CDC_I : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 0, C_FLOP_INPUT => 1, --valid only for level CDC C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => m_axi_s2mm_aclk, prmry_resetn => s2mm_prmry_resetn, prmry_in => s2mm_prmtr_or_tail_ptr_updt_complete, prmry_vect_in => (others => '0'), prmry_ack => open, scndry_aclk => s_axis_s2mm_aclk, scndry_resetn => s2mm_axis_resetn, scndry_out => s2mm_prmtr_updt_complete_s, scndry_vect_out => open ); ---- S2MM_HALTED_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc ---- generic map( ---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S , ---- C_VECTOR_WIDTH => 1 ---- ) ---- port map ( ---- prmry_aclk => m_axi_s2mm_aclk , ---- prmry_resetn => s2mm_prmry_resetn , ---- scndry_aclk => s_axis_s2mm_aclk , ---- scndry_resetn => s2mm_axis_resetn , ---- scndry_in => '0' , -- Not Used ---- prmry_out => open , -- Not Used ---- prmry_in => s2mm_dmasr(DMASR_HALTED_BIT) , ---- scndry_out => s2mm_dmasr_halted_s , ---- scndry_vect_s_h => '0' , -- Not Used ---- scndry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used ---- prmry_vect_out => open , -- Not Used ---- prmry_vect_s_h => '0' , -- Not Used ---- prmry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used ---- scndry_vect_out => open -- Not Used ---- ); ---- S2MM_HALTED_CDC_I : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_FLOP_INPUT => 1, --valid only for level CDC C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => m_axi_s2mm_aclk, prmry_resetn => s2mm_prmry_resetn, prmry_in => s2mm_dmasr(DMASR_HALTED_BIT), prmry_vect_in => (others => '0'), prmry_ack => open, scndry_aclk => s_axis_s2mm_aclk, scndry_resetn => s2mm_axis_resetn, scndry_out => s2mm_dmasr_halted_s, scndry_vect_out => open ); ---- SOF_LATE_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc ---- generic map( ---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P , ---- C_VECTOR_WIDTH => 1 ---- ) ---- port map ( ---- prmry_aclk => m_axi_s2mm_aclk , ---- prmry_resetn => s2mm_prmry_resetn , ---- scndry_aclk => s_axis_s2mm_aclk , ---- scndry_resetn => s2mm_axis_resetn , ---- scndry_in => s2mm_fsize_more_or_sof_late_s , -- Not Used ---- prmry_out => s2mm_fsize_more_or_sof_late , -- Not Used ---- prmry_in => '0' , ---- scndry_out => open , ---- scndry_vect_s_h => '0' , -- Not Used ---- scndry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used ---- prmry_vect_out => open , -- Not Used ---- prmry_vect_s_h => '0' , -- Not Used ---- prmry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used ---- scndry_vect_out => open -- Not Used ---- ); ---- SOF_LATE_CDC_I : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_FLOP_INPUT => 1, --valid only for level CDC C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => s_axis_s2mm_aclk, prmry_resetn => s2mm_axis_resetn, prmry_in => s2mm_fsize_more_or_sof_late_s, prmry_vect_in => (others => '0'), prmry_ack => open, scndry_aclk => m_axi_s2mm_aclk, scndry_resetn => s2mm_prmry_resetn, scndry_out => s2mm_fsize_more_or_sof_late, scndry_vect_out => open ); end generate GEN_FOR_ASYNC_FLUSH_SOF; GEN_FOR_SYNC_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 0 generate begin s2mm_dmasr_halted_s <= s2mm_dmasr(DMASR_HALTED_BIT); s2mm_prmtr_updt_complete_s <= s2mm_prmtr_or_tail_ptr_updt_complete; s2mm_fsize_more_or_sof_late <= s2mm_fsize_more_or_sof_late_s; end generate GEN_FOR_SYNC_FLUSH_SOF; --------------------------------------------------------------------------- end generate GEN_FLUSH_SOF_TREADY; ---------------------------------------------------------------------------------------------------------------------------------------------------------- GEN_FLUSH_NO_SOF_TREADY : if ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and S2MM_SOF_ENABLE = 0 generate begin --s_axis_s2mm_tdata_signal <= s_axis_s2mm_tdata; --s_axis_s2mm_tkeep_signal <= s_axis_s2mm_tkeep; --s_axis_s2mm_tuser_signal <= s_axis_s2mm_tuser; --s_axis_s2mm_tlast_signal <= s_axis_s2mm_tlast; --s_axis_s2mm_tvalid_signal <= s_axis_s2mm_tvalid; --s_axis_s2mm_tready <= s_axis_s2mm_tready_signal; s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid_signal; s_axis_s2mm_tready_signal <= s_axis_s2mm_tready_i_axis_dw_conv; s2mm_dummy_tready <= '0'; end generate GEN_FLUSH_NO_SOF_TREADY; GEN_NO_FLUSH_TREADY : if ENABLE_FLUSH_ON_S2MM_FSYNC = 0 generate begin --s_axis_s2mm_tdata_signal <= s_axis_s2mm_tdata; --s_axis_s2mm_tkeep_signal <= s_axis_s2mm_tkeep; --s_axis_s2mm_tuser_signal <= s_axis_s2mm_tuser; --s_axis_s2mm_tlast_signal <= s_axis_s2mm_tlast; --s_axis_s2mm_tvalid_signal <= s_axis_s2mm_tvalid; --s_axis_s2mm_tready <= s_axis_s2mm_tready_signal; s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid_signal; s_axis_s2mm_tready_signal <= s_axis_s2mm_tready_i_axis_dw_conv; s2mm_dummy_tready <= '0'; end generate GEN_NO_FLUSH_TREADY; GEN_AXIS_S2MM_DWIDTH_CONV : if C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED /= C_S_AXIS_S2MM_TDATA_WIDTH generate constant C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 : integer := C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8; constant C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 : integer := C_S_AXIS_S2MM_TDATA_WIDTH/8; signal s_axis_s2mm_dwidth_tuser_i : std_logic_vector -- (C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) := (others => '0'); -- signal s_axis_s2mm_dwidth_tuser : std_logic_vector -- (C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 downto 0) := (others => '0'); -- begin S2MM_TUSER_CNCT : for i in 0 to C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 generate begin s_axis_s2mm_dwidth_tuser(i) <= s_axis_s2mm_tuser_signal(0); end generate S2MM_TUSER_CNCT; s_axis_s2mm_tuser_i(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) <= s_axis_s2mm_dwidth_tuser_i(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0); AXIS_S2MM_DWIDTH_CONVERTER_I: entity axi_vdma_v6_2.axi_vdma_s2mm_axis_dwidth_converter generic map(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED , C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , --C_AXIS_SIGNAL_SET => 255 , C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 => C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 , C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 , C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE , ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC, C_AXIS_TID_WIDTH => 1 , C_AXIS_TDEST_WIDTH => 1 , C_FAMILY => C_ROOT_FAMILY ) port map( ACLK => s_axis_s2mm_aclk , ARESETN => s2mm_axis_linebuf_reset_out , --ARESETN => s2mm_axis_resetn , ACLKEN => '1' , s2mm_fsize_less_err_internal_tvalid_gating => s2mm_fsize_less_err_internal_tvalid_gating , -- : in std_logic ; fsync_out => s2mm_fsync_out_i , -- : in std_logic ; crnt_vsize_d2 => s2mm_crnt_vsize_d2 , -- : in std_logic_vector(VSIZE_DWIDTH-1 downto 0) ; chnl_ready_dwidth => s2mm_chnl_ready , -- : out std_logic; strm_not_finished_dwidth => s2mm_strm_not_finished , -- : out std_logic; strm_all_lines_rcvd_dwidth => s2mm_strm_all_lines_rcvd , -- : out std_logic; all_vount_rcvd_dwidth => s2mm_all_vount_rcvd , -- : out std_logic; S_AXIS_TVALID => s_axis_s2mm_tvalid_int , S_AXIS_TREADY => s_axis_s2mm_tready_i_axis_dw_conv , S_AXIS_TDATA => s_axis_s2mm_tdata_signal(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) , --S_AXIS_TSTRB => ZERO_VALUE(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) , S_AXIS_TSTRB => s_axis_s2mm_tkeep_signal(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) , S_AXIS_TKEEP => s_axis_s2mm_tkeep_signal(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) , S_AXIS_TLAST => s_axis_s2mm_tlast_signal , S_AXIS_TID => ZERO_VALUE(0 downto 0) , S_AXIS_TDEST => ZERO_VALUE(0 downto 0) , S_AXIS_TUSER => s_axis_s2mm_dwidth_tuser(C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 downto 0) , M_AXIS_TVALID => s_axis_s2mm_tvalid_i , M_AXIS_TREADY => s_axis_s2mm_tready_i , M_AXIS_TDATA => s_axis_s2mm_tdata_i(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0) , M_AXIS_TSTRB => open , M_AXIS_TKEEP => s_axis_s2mm_tkeep_i(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0) , M_AXIS_TLAST => s_axis_s2mm_tlast_i , M_AXIS_TID => open , M_AXIS_TDEST => open , M_AXIS_TUSER => s_axis_s2mm_dwidth_tuser_i(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) ) ; end generate GEN_AXIS_S2MM_DWIDTH_CONV; GEN_NO_AXIS_S2MM_DWIDTH_CONV_NO_FLUSH_SOF : if ((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED = C_S_AXIS_S2MM_TDATA_WIDTH) and (ENABLE_FLUSH_ON_S2MM_FSYNC = 0 or S2MM_SOF_ENABLE = 0) )generate begin s_axis_s2mm_tvalid_i <= s_axis_s2mm_tvalid_int; s_axis_s2mm_tdata_i <= s_axis_s2mm_tdata_signal; s_axis_s2mm_tkeep_i <= s_axis_s2mm_tkeep_signal; s_axis_s2mm_tlast_i <= s_axis_s2mm_tlast_signal; s_axis_s2mm_tuser_i <= s_axis_s2mm_tuser_signal; s_axis_s2mm_tready_i_axis_dw_conv <= s_axis_s2mm_tready_i; s2mm_chnl_ready <= '0' ; s2mm_strm_not_finished <= '0' ; s2mm_strm_all_lines_rcvd <= '0' ; s2mm_all_vount_rcvd <= '0' ; end generate GEN_NO_AXIS_S2MM_DWIDTH_CONV_NO_FLUSH_SOF; GEN_NO_AXIS_S2MM_DWIDTH_CONV : if ((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED = C_S_AXIS_S2MM_TDATA_WIDTH) and (ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and S2MM_SOF_ENABLE = 1) ) generate constant ZERO_VALUE : std_logic_vector(255 downto 0) := (others => '0'); constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := std_logic_vector(to_unsigned(1,VSIZE_DWIDTH)); constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); signal chnl_ready_no_dwidth : std_logic := '0'; signal strm_not_finished_no_dwidth : std_logic := '0'; signal strm_all_lines_rcvd_no_dwidth : std_logic := '0'; signal decr_vcount_no_dwidth : std_logic := '0'; signal vsize_counter_no_dwidth : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); signal all_vount_rcvd_no_dwidth : std_logic := '0'; begin s_axis_s2mm_tvalid_i <= s_axis_s2mm_tvalid_int; s_axis_s2mm_tdata_i <= s_axis_s2mm_tdata_signal; s_axis_s2mm_tkeep_i <= s_axis_s2mm_tkeep_signal; s_axis_s2mm_tlast_i <= s_axis_s2mm_tlast_signal; s_axis_s2mm_tuser_i <= s_axis_s2mm_tuser_signal; s_axis_s2mm_tready_i_axis_dw_conv <= s_axis_s2mm_tready_i; -- Decrement vertical count with each accept tlast decr_vcount_no_dwidth <= '1' when s_axis_s2mm_tlast_signal = '1' and s_axis_s2mm_tvalid_int = '1' and s_axis_s2mm_tready_i_axis_dw_conv = '1' else '0'; -- Drive ready at fsync out then de-assert once all lines have -- been accepted. NO_DWIDTH_VERT_COUNTER : process(s_axis_s2mm_aclk) begin if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then --if(s2mm_axis_linebuf_reset_out = '0' and s2mm_fsync_out_i = '0')then --if((s2mm_axis_linebuf_reset_out = '0' and s2mm_fsync_out_i = '0') or s2mm_fsize_less_err_flag = '1')then if((s2mm_axis_linebuf_reset_out = '0' and s2mm_fsync_out_i = '0') or s2mm_fsize_less_err_internal_tvalid_gating = '1')then vsize_counter_no_dwidth <= (others => '0'); chnl_ready_no_dwidth <= '0'; strm_not_finished_no_dwidth <= '0'; strm_all_lines_rcvd_no_dwidth <= '1'; all_vount_rcvd_no_dwidth <= '0'; elsif(s2mm_fsync_out_i = '1')then vsize_counter_no_dwidth <= s2mm_crnt_vsize_d2; chnl_ready_no_dwidth <= '1'; strm_not_finished_no_dwidth <= '1'; strm_all_lines_rcvd_no_dwidth <= '0'; all_vount_rcvd_no_dwidth <= '0'; elsif(decr_vcount_no_dwidth = '1' and vsize_counter_no_dwidth = VSIZE_ONE_VALUE)then vsize_counter_no_dwidth <= (others => '0'); chnl_ready_no_dwidth <= '0'; strm_not_finished_no_dwidth <= '0'; strm_all_lines_rcvd_no_dwidth <= '1'; all_vount_rcvd_no_dwidth <= '1'; elsif(decr_vcount_no_dwidth = '1' and vsize_counter_no_dwidth /= VSIZE_ZERO_VALUE)then vsize_counter_no_dwidth <= std_logic_vector(unsigned(vsize_counter_no_dwidth) - 1); chnl_ready_no_dwidth <= '1'; strm_not_finished_no_dwidth <= '1'; strm_all_lines_rcvd_no_dwidth <= '0'; all_vount_rcvd_no_dwidth <= '0'; else all_vount_rcvd_no_dwidth <= '0'; end if; end if; end process NO_DWIDTH_VERT_COUNTER; s2mm_chnl_ready <= chnl_ready_no_dwidth; s2mm_strm_not_finished <= strm_not_finished_no_dwidth; s2mm_strm_all_lines_rcvd <= strm_all_lines_rcvd_no_dwidth; s2mm_all_vount_rcvd <= all_vount_rcvd_no_dwidth; end generate GEN_NO_AXIS_S2MM_DWIDTH_CONV; --------------------------------------------------------------------------- -- S2MM Register Module --------------------------------------------------------------------------- S2MM_REGISTER_MODULE_I : entity axi_vdma_v6_2.axi_vdma_reg_module generic map( C_TOTAL_NUM_REGISTER => TOTAL_NUM_REGISTER , C_INCLUDE_SG => C_INCLUDE_SG , C_CHANNEL_IS_MM2S => CHANNEL_IS_S2MM , C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC , -- CR591965 C_ENABLE_VIDPRMTR_READS => C_ENABLE_VIDPRMTR_READS , C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE , C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION , C_NUM_FSTORES => C_NUM_FSTORES , --C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO , C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL , C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 , C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 , C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 , C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 , C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 , C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 , C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 , C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 , C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 , C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 , C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 , C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 , C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 , C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 , C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 , C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 , C_LINEBUFFER_THRESH => C_S2MM_LINEBUFFER_THRESH_INT , C_GENLOCK_MODE => C_S2MM_GENLOCK_MODE , C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH , C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH , C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ) port map( prmry_aclk => m_axi_s2mm_aclk , prmry_resetn => s2mm_prmry_resetn , -- Register to AXI Lite Interface axi2ip_wrce => s2mm_axi2ip_wrce , axi2ip_wrdata => s2mm_axi2ip_wrdata , axi2ip_rdaddr => s2mm_axi2ip_rdaddr , --axi2ip_rden => s2mm_axi2ip_rden , axi2ip_rden => '0' , ip2axi_rddata => s2mm_ip2axi_rddata , --ip2axi_rddata_valid => s2mm_ip2axi_rddata_valid , ip2axi_rddata_valid => open , ip2axi_frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref , ip2axi_frame_store => s2mm_ip2axi_frame_store , ip2axi_introut => s2mm_ip2axi_introut , -- Soft Reset soft_reset => s2mm_soft_reset , soft_reset_clr => s2mm_soft_reset_clr , -- DMA Control / Status Register Signals halted_clr => s2mm_halted_clr , halted_set => s2mm_halted_set , idle_set => s2mm_idle_set , idle_clr => s2mm_idle_clr , ioc_irq_set => s2mm_ioc_irq_set , dly_irq_set => s2mm_dly_irq_set , irqdelay_status => s2mm_irqdelay_status , irqthresh_status => s2mm_irqthresh_status , frame_sync => s2mm_frame_sync , fsync_mask => s2mm_mask_fsync_out , new_curdesc_wren => s2mm_new_curdesc_wren , new_curdesc => s2mm_new_curdesc , update_frmstore => s2mm_update_frmstore , new_frmstr => s2mm_frame_number , tstvect_fsync => s2mm_tstvect_fsync , valid_frame_sync => s2mm_valid_frame_sync , irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , dlyirq_dsble => s2mm_dlyirq_dsble , irqthresh_wren => s2mm_irqthresh_wren , irqdelay_wren => s2mm_irqdelay_wren , tailpntr_updated => s2mm_tailpntr_updated , -- Error Detection Control stop => s2mm_stop , dma_interr_set => s2mm_dma_interr_set , dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors , dma_slverr_set => s2mm_dma_slverr_set , dma_decerr_set => s2mm_dma_decerr_set , ftch_slverr_set => s2mm_ftch_slverr_set , ftch_decerr_set => s2mm_ftch_decerr_set , fsize_mismatch_err => s2mm_fsize_mismatch_err , lsize_mismatch_err => s2mm_lsize_mismatch_err , lsize_more_mismatch_err => s2mm_lsize_more_mismatch_err , s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late , -- VDMA Base Registers reg_index => s2mm_reg_index , dmacr => s2mm_dmacr , dmasr => s2mm_dmasr , curdesc => s2mm_curdesc , taildesc => s2mm_taildesc , num_frame_store => s2mm_num_frame_store , linebuf_threshold => s2mm_linebuf_threshold , -- Register Direct Support regdir_idle => s2mm_regdir_idle , prmtr_updt_complete => s2mm_prmtr_updt_complete , reg_module_vsize => s2mm_reg_module_vsize , reg_module_hsize => s2mm_reg_module_hsize , reg_module_stride => s2mm_reg_module_stride , reg_module_frmdly => s2mm_reg_module_frmdly , reg_module_strt_addr => s2mm_reg_module_strt_addr , -- Fetch/Update error addresses frmstr_err_addr => s2mm_frmstr_err_addr , ftch_err_addr => s2mm_ftch_err_addr ); --------------------------------------------------------------------------- -- S2MM DMA Controller --------------------------------------------------------------------------- I_S2MM_DMA_MNGR : entity axi_vdma_v6_2.axi_vdma_mngr generic map( C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH , C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_INCLUDE_SF => DM_S2MM_INCLUDE_SF , C_USE_FSYNC => C_USE_S2MM_FSYNC_01 , -- CR582182 C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC , -- CR591965 C_NUM_FSTORES => C_NUM_FSTORES , C_GENLOCK_MODE => C_S2MM_GENLOCK_MODE , C_GENLOCK_NUM_MASTERS => C_S2MM_GENLOCK_NUM_MASTERS , C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION , --C_GENLOCK_REPEAT_EN => C_S2MM_GENLOCK_REPEAT_EN , -- CR591965 --C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO , C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL , C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 , C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 , C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 , C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 , C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 , C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 , C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 , C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 , C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 , C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 , C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 , C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 , C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 , C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 , C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 , C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 , C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE , C_INCLUDE_SG => C_INCLUDE_SG , -- CR581800 C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH , C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_DM_STATUS_WIDTH => S2MM_DM_STATUS_WIDTH , -- CR608521 C_EXTEND_DM_COMMAND => S2MM_DM_CMD_EXTENDED , C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE, C_MM2S_SOF_ENABLE => 0 , C_INCLUDE_MM2S => 0 , C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_FAMILY => C_ROOT_FAMILY ) port map( -- Secondary Clock and Reset prmry_aclk => m_axi_s2mm_aclk , prmry_resetn => s2mm_prmry_resetn , soft_reset => s2mm_soft_reset , scndry_aclk => s_axis_s2mm_aclk , scndry_resetn => s2mm_axis_resetn , -- MM2S Control and Status run_stop => s2mm_dmacr(DMACR_RS_BIT) , dmacr_repeat_en => s2mm_dmacr(DMACR_REPEAT_EN_BIT) , dmasr_halt => s2mm_dmasr(DMASR_HALTED_BIT) , sync_enable => s2mm_dmacr(DMACR_SYNCEN_BIT) , regdir_idle => s2mm_regdir_idle , ftch_idle => s2mm_ftch_idle , halt => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , halted_clr => s2mm_halted_clr , halted_set => s2mm_halted_set , idle_set => s2mm_idle_set , idle_clr => s2mm_idle_clr , stop => s2mm_stop , s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late , s2mm_dmasr_lsize_less_err => s2mm_dmasr(DMASR_LSIZEERR_BIT) , all_idle => s2mm_all_idle , cmdsts_idle => s2mm_cmdsts_idle , ftchcmdsts_idle => s2mm_ftchcmdsts_idle , s2mm_fsync_out_m => s2mm_fsync_out_m_i , mm2s_fsync_out_m => '0' , -- CR616211 frame_sync => s2mm_frame_sync , update_frmstore => s2mm_update_frmstore , -- CR582182 frmstr_err_addr => s2mm_frmstr_err_addr , -- CR582182 frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref , frame_ptr_in => s2mm_s_frame_ptr_in , frame_ptr_out => s2mm_m_frame_ptr_out , internal_frame_ptr_in => mm2s_to_s2mm_frame_ptr_in , valid_frame_sync => s2mm_valid_frame_sync , valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb , valid_video_prmtrs => s2mm_valid_video_prmtrs , parameter_update => s2mm_parameter_update , circular_prk_mode => s2mm_dmacr(DMACR_CRCLPRK_BIT) , mstr_pntr_ref => s2mm_dmacr(DMACR_PNTR_NUM_MSB downto DMACR_PNTR_NUM_LSB) , genlock_select => s2mm_dmacr(DMACR_GENLOCK_SEL_BIT), line_buffer_empty => '1' , -- NOT Used by S2MM therefore tie off dwidth_fifo_pipe_empty => '1' , -- NOT Used by S2MM therefore tie off crnt_vsize => s2mm_crnt_vsize , -- CR575884 num_frame_store => s2mm_num_frame_store , all_lines_xfred => s2mm_all_lines_xfred , -- CR591965 all_lasts_rcvd => all_lasts_rcvd , mm2s_fsize_mismatch_err_m => '0' , -- Not Needed for MM2S channel mm2s_fsize_mismatch_err_s => '0' , -- Not Needed for MM2S channel s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s , -- Not Needed for MM2S channel drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err , s2mm_strm_all_lines_rcvd => s2mm_strm_all_lines_rcvd , -- : out std_logic; s2mm_fsync_core => s2mm_fsync_core , fsize_mismatch_err_flag => s2mm_fsize_mismatch_err_flag , -- CR591965 fsize_mismatch_err => s2mm_fsize_mismatch_err , -- CR591965 lsize_mismatch_err => s2mm_lsize_mismatch_err , -- CR591965 lsize_more_mismatch_err => s2mm_lsize_more_mismatch_err , -- CR591965 capture_hsize_at_uf_err => s2mm_capture_hsize_at_uf_err_sig , -- Register Direct Support prmtr_updt_complete => s2mm_prmtr_updt_complete , reg_module_vsize => s2mm_reg_module_vsize , reg_module_hsize => s2mm_reg_module_hsize , reg_module_stride => s2mm_reg_module_stride , reg_module_frmdly => s2mm_reg_module_frmdly , reg_module_strt_addr => s2mm_reg_module_strt_addr , -- Test vector signals tstvect_err => s2mm_tstvect_err , tstvect_fsync => s2mm_tstvect_fsync , tstvect_frame => s2mm_tstvect_frame , tstvect_frm_ptr_out => s2mm_tstvect_frm_ptr_out , mstrfrm_tstsync_out => s2mm_mstrfrm_tstsync , -- AXI Stream Timing packet_sof => s2mm_packet_sof , -- Primary DMA Errors dma_interr_set => s2mm_dma_interr_set , dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors , dma_slverr_set => s2mm_dma_slverr_set , dma_decerr_set => s2mm_dma_decerr_set , -- SG MM2S Descriptor Fetch AXI Stream In m_axis_ftch_tdata => m_axis_s2mm_ftch_tdata , m_axis_ftch_tvalid => m_axis_s2mm_ftch_tvalid , m_axis_ftch_tready => m_axis_s2mm_ftch_tready , m_axis_ftch_tlast => m_axis_s2mm_ftch_tlast , -- Currently Being Processed Descriptor/Frame frame_number => s2mm_frame_number , chnl_current_frame => s2mm_chnl_current_frame , genlock_pair_frame => s2mm_genlock_pair_frame , new_curdesc => s2mm_new_curdesc , new_curdesc_wren => s2mm_new_curdesc_wren , tailpntr_updated => s2mm_tailpntr_updated , -- User Command Interface Ports (AXI Stream) s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid , s_axis_cmd_tready => s_axis_s2mm_cmd_tready , s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_sts_tvalid => m_axis_s2mm_sts_tvalid , m_axis_sts_tready => m_axis_s2mm_sts_tready , m_axis_sts_tdata => m_axis_s2mm_sts_tdata , m_axis_sts_tkeep => m_axis_s2mm_sts_tkeep , err => s2mm_err , ftch_err => s2mm_ftch_err ); --------------------------------------------------------------------------- -- MM2S Frame sync generator --------------------------------------------------------------------------- S2MM_FSYNC_I : entity axi_vdma_v6_2.axi_vdma_fsync_gen generic map( C_USE_FSYNC => C_USE_S2MM_FSYNC_01 , ENABLE_FLUSH_ON_S2MM_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC , ENABLE_FLUSH_ON_MM2S_FSYNC => 0 , C_INCLUDE_S2MM => 1 , C_INCLUDE_MM2S => 0 , C_SOF_ENABLE => S2MM_SOF_ENABLE ) port map( prmry_aclk => m_axi_s2mm_aclk , prmry_resetn => s2mm_prmry_resetn , -- Frame Count Enable Support valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb , valid_video_prmtrs => s2mm_valid_video_prmtrs , frmcnt_ioc => s2mm_ioc_irq_set , dmacr_frmcnt_enbl => s2mm_dmacr(DMACR_FRMCNTEN_BIT) , dmasr_frmcnt_status => s2mm_irqthresh_status , mask_fsync_out => s2mm_mask_fsync_out , -- VDMA process status run_stop => s2mm_dmacr(DMACR_RS_BIT) , all_idle => s2mm_all_idle , parameter_update => s2mm_parameter_update , -- VDMA Frame Sync sources fsync => s2mm_cdc2dmac_fsync , tuser_fsync => s2mm_tuser_fsync , othrchnl_fsync => mm2s_to_s2mm_fsync , fsync_src_select => s2mm_dmacr(DMACR_FSYNCSEL_MSB downto DMACR_FSYNCSEL_LSB) , -- VDMA frame sync output to core frame_sync => s2mm_frame_sync , -- VDMA Frame Sync Output to ports frame_sync_out => s2mm_dmac2cdc_fsync_out , prmtr_update => s2mm_dmac2cdc_prmtr_update ); -- Clock Domain Crossing between m_axi_s2mm_aclk and s_axis_s2mm_aclk S2MM_VID_CDC_I : entity axi_vdma_v6_2.axi_vdma_vid_cdc generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_GENLOCK_MSTR_PTR_DWIDTH => NUM_FRM_STORE_WIDTH , C_GENLOCK_SLVE_PTR_DWIDTH => S2MM_GENLOCK_SLVE_PTR_DWIDTH , C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ) port map( prmry_aclk => m_axi_s2mm_aclk , prmry_resetn => s2mm_prmry_resetn , scndry_aclk => s_axis_s2mm_aclk , scndry_resetn => s2mm_axis_resetn , -- Genlock internal bus cdc othrchnl_aclk => m_axi_mm2s_aclk , othrchnl_resetn => mm2s_prmry_resetn , othrchnl2cdc_frame_ptr_out => mm2s_frame_ptr_out_i , cdc2othrchnl_frame_ptr_in => mm2s_to_s2mm_frame_ptr_in , cdc2othrchnl_fsync => s2mm_to_mm2s_fsync , -- GenLock Clock Domain Crossing dmac2cdc_frame_ptr_out => s2mm_m_frame_ptr_out , cdc2top_frame_ptr_out => s2mm_frame_ptr_out_i , top2cdc_frame_ptr_in => s2mm_frame_ptr_in , cdc2dmac_frame_ptr_in => s2mm_s_frame_ptr_in , dmac2cdc_mstrfrm_tstsync => s2mm_mstrfrm_tstsync , cdc2dmac_mstrfrm_tstsync => s2mm_mstrfrm_tstsync_out , -- SOF Detection Domain Crossing vid2cdc_packet_sof => s2mm_vid2cdc_packet_sof , cdc2dmac_packet_sof => s2mm_packet_sof , -- Frame Sync Generation Domain Crossing vid2cdc_fsync => s2mm_fsync_core , cdc2dmac_fsync => s2mm_cdc2dmac_fsync , dmac2cdc_fsync_out => s2mm_dmac2cdc_fsync_out , dmac2cdc_prmtr_update => s2mm_dmac2cdc_prmtr_update , cdc2vid_fsync_out => s2mm_fsync_out_i , cdc2vid_prmtr_update => s2mm_prmtr_update_i ); s2mm_fsync_out_sig <= s2mm_fsync_out_i; -- Start of Frame Detection - used for interrupt coalescing S2MM_SOF_I : entity axi_vdma_v6_2.axi_vdma_sof_gen port map( scndry_aclk => s_axis_s2mm_aclk , scndry_resetn => s2mm_axis_resetn , axis_tready => s_axis_s2mm_tready_i , axis_tvalid => s_axis_s2mm_tvalid_i , fsync => s2mm_fsync_out_i , -- CR622884 packet_sof => s2mm_vid2cdc_packet_sof ); ------------------------------------------------------------------------------- -- Primary S2MM Line Buffer ------------------------------------------------------------------------------- S2MM_LINEBUFFER_I : entity axi_vdma_v6_2.axi_vdma_s2mm_linebuf generic map( C_DATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED , C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE , C_USE_FSYNC => C_USE_S2MM_FSYNC_01 , C_USE_S2MM_FSYNC => C_USE_S2MM_FSYNC , C_S_AXIS_S2MM_TUSER_BITS => C_S_AXIS_S2MM_TUSER_BITS , C_INCLUDE_S2MM_DRE => C_S2MM_ENABLE_TKEEP , C_TOPLVL_LINEBUFFER_DEPTH => C_S2MM_LINEBUFFER_DEPTH , -- CR625142 --C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO , C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL , C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 , C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 , C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 , C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 , C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 , C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 , C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 , C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 , C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 , C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 , C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 , C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 , C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 , C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 , C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 , C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 , C_LINEBUFFER_DEPTH => S2MM_LINEBUFFER_DEPTH , C_LINEBUFFER_AF_THRESH => C_S2MM_LINEBUFFER_THRESH_INT , C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC, C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_FAMILY => C_ROOT_FAMILY ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- s_axis_aclk => s_axis_s2mm_aclk , s_axis_resetn => s2mm_axis_resetn , m_axis_aclk => m_axi_s2mm_aclk , m_axis_resetn => s2mm_prmry_resetn , s2mm_axis_linebuf_reset_out => s2mm_axis_linebuf_reset_out , -- Graceful shut down control run_stop => s2mm_dmacr(DMACR_RS_BIT) , dm_halt => s2mm_halt , -- CR591965 dm_halt_cmplt => s2mm_halt_cmplt , -- CR591965 capture_dm_done_vsize_counter => s2mm_capture_dm_done_vsize_counter_sig , s2mm_fsize_mismatch_err_flag => s2mm_fsize_mismatch_err_flag , s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s , s2mm_fsize_mismatch_err => s2mm_fsize_mismatch_err , drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err , no_fsync_before_vsize_sel_00_01 => no_fsync_before_vsize_sel_00_01 , hold_dummy_tready_low => hold_dummy_tready_low , hold_dummy_tready_low2 => hold_dummy_tready_low2 , mm2s_fsync => mm2s_fsync_fe , m_axis_mm2s_aclk => m_axis_mm2s_aclk , mm2s_axis_resetn => mm2s_axis_resetn , s2mm_fsync_core => s2mm_fsync_core , s2mm_fsync => s2mm_fsync_fe , s2mm_tuser_fsync_top => s2mm_tuser_fsync_top , s2mm_dmasr_fsize_less_err => s2mm_dmasr(DMASR_FSIZEERR_BIT) , fsync_src_select => s2mm_dmacr(DMACR_FSYNCSEL_MSB downto DMACR_FSYNCSEL_LSB) , fsync_src_select_s => s2mm_fsync_src_select_s , chnl_ready_external => s2mm_chnl_ready , strm_not_finished => s2mm_strm_not_finished , crnt_vsize_d2_s => s2mm_crnt_vsize_d2 , -- Line Tracking Control crnt_vsize => s2mm_crnt_vsize , fsync_out_m => s2mm_fsync_out_m_i , fsync_out => s2mm_fsync_out_i , frame_sync => s2mm_frame_sync , -- Threshold linebuf_threshold => s2mm_linebuf_threshold , -- Stream In s_axis_tdata => s_axis_s2mm_tdata_i , s_axis_tkeep => s_axis_s2mm_tkeep_i , s_axis_tlast => s_axis_s2mm_tlast_i , s_axis_tvalid => s_axis_s2mm_tvalid_i , s_axis_tready => s_axis_s2mm_tready_i , s_axis_tuser => s_axis_s2mm_tuser_i , -- Stream Out m_axis_tdata => linebuf2dm_s2mm_tdata , m_axis_tkeep => linebuf2dm_s2mm_tkeep , m_axis_tlast => linebuf2dm_s2mm_tlast , m_axis_tvalid => linebuf2dm_s2mm_tvalid , m_axis_tready => dm2linebuf_s2mm_tready , -- Fifo Status Flags s2mm_fifo_full => s2mm_buffer_full_i , s2mm_fifo_almost_full => s2mm_buffer_almost_full_i , s2mm_all_lines_xfred => s2mm_all_lines_xfred , -- CR591965 all_lasts_rcvd => all_lasts_rcvd , s2mm_tuser_fsync => s2mm_tuser_fsync ); end generate GEN_SPRT_FOR_S2MM; -- Do not generate support logic for S2MM GEN_NO_SPRT_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate begin -- Register Module Tie-Offs s2mm_ip2axi_rddata <= (others => '0'); --s2mm_ip2axi_rddata_valid <= '0'; s2mm_ip2axi_frame_ptr_ref <= (others => '0'); s2mm_ip2axi_frame_store <= (others => '0'); s2mm_ip2axi_introut <= '0'; s2mm_soft_reset <= '0'; s2mm_irqthresh_rstdsbl <= '0'; s2mm_dlyirq_dsble <= '0'; s2mm_irqthresh_wren <= '0'; s2mm_irqdelay_wren <= '0'; s2mm_tailpntr_updated <= '0'; s2mm_dmacr <= (others => '0'); s2mm_dmasr <= (others => '0'); s2mm_curdesc <= (others => '0'); s2mm_taildesc <= (others => '0'); s2mm_num_frame_store <= (others => '0'); s2mm_linebuf_threshold <= (others => '0'); s2mm_regdir_idle <= '0'; s2mm_prmtr_updt_complete <= '0'; s2mm_reg_module_vsize <= (others => '0'); s2mm_reg_module_hsize <= (others => '0'); s2mm_reg_module_stride <= (others => '0'); s2mm_reg_module_frmdly <= (others => '0'); s2mm_dummy_tready <= '0'; -- Must zero each element of an array of vectors to zero -- all vectors. GEN_S2MM_ZERO_STRT : for i in 0 to C_NUM_FSTORES-1 generate begin s2mm_reg_module_strt_addr(i) <= (others => '0'); end generate GEN_S2MM_ZERO_STRT; -- Line buffer Tie-Offs s_axis_s2mm_tready_i_axis_dw_conv <= '0'; s_axis_s2mm_tready_i <= '0'; s_axis_s2mm_tready <= '0'; s2mm_capture_dm_done_vsize_counter_sig <= (others => '0'); s2mm_capture_hsize_at_uf_err_sig <= (others => '0'); linebuf2dm_s2mm_tdata <= (others => '0'); linebuf2dm_s2mm_tkeep <= (others => '0'); linebuf2dm_s2mm_tlast <= '0'; linebuf2dm_s2mm_tvalid <= '0'; s2mm_buffer_full_i <= '0'; s2mm_buffer_almost_full_i <= '0'; s2mm_all_lines_xfred <= '0'; -- CR591965 s2mm_tuser_fsync <= '0'; -- Frame sync generator s2mm_frame_sync <= '0'; -- SOF/EOF generator s2mm_packet_sof <= '0'; -- DMA Controller s2mm_halted_clr <= '0'; s2mm_halted_set <= '1'; s2mm_idle_set <= '0'; s2mm_idle_clr <= '0'; s2mm_frame_number <= (others => '0'); s2mm_chnl_current_frame <= (others => '0'); s2mm_genlock_pair_frame <= (others => '0'); s2mm_new_curdesc_wren <= '0'; s2mm_new_curdesc <= (others => '0'); s2mm_stop <= '0'; s2mm_all_idle <= '1'; s2mm_cmdsts_idle <= '1'; s2mm_ftchcmdsts_idle <= '1'; m_axis_s2mm_ftch_tready <= '0'; s_axis_s2mm_cmd_tvalid <= '0'; s_axis_s2mm_cmd_tdata <= (others => '0'); m_axis_s2mm_sts_tready <= '0'; s2mm_frame_ptr_out_i <= (others => '0'); s2mm_m_frame_ptr_out <= (others => '0'); mm2s_to_s2mm_frame_ptr_in <= (others => '0'); s2mm_valid_frame_sync <= '0'; s2mm_valid_frame_sync_cmb <= '0'; s2mm_valid_video_prmtrs <= '0'; s2mm_parameter_update <= '0'; s2mm_tstvect_err <= '0'; s2mm_tstvect_fsync <= '0'; s2mm_tstvect_frame <= (others => '0'); s2mm_dma_interr_set <= '0'; s2mm_dma_interr_set_minus_frame_errors <= '0'; s2mm_dma_slverr_set <= '0'; s2mm_dma_decerr_set <= '0'; s2mm_fsize_mismatch_err <= '0'; s2mm_lsize_mismatch_err <= '0'; s2mm_lsize_more_mismatch_err <= '0'; -- Frame Sync generator s2mm_fsync_out_sig <= '0'; s2mm_prmtr_update_i <= '0'; s2mm_crnt_vsize <= (others => '0'); -- CR575884 s2mm_mask_fsync_out <= '0'; s2mm_mstrfrm_tstsync <= '0'; s2mm_mstrfrm_tstsync_out <= '0'; s2mm_tstvect_frm_ptr_out <= (others => '0'); s2mm_frmstr_err_addr <= (others => '0'); s2mm_to_mm2s_fsync <= '0'; end generate GEN_NO_SPRT_FOR_S2MM; ------------------------------------------------------------------------------- -- Primary MM2S and S2MM DataMover ------------------------------------------------------------------------------- I_PRMRY_DATAMOVER : entity axi_datamover_v5_1.axi_datamover generic map( C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE , C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED , C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO , C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => DM_CLOCK_SYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_ENABLE_MM2S_TKEEP => C_MM2S_ENABLE_TKEEP , C_MM2S_BURST_SIZE => C_MM2S_MAX_BURST_LENGTH , C_MM2S_BTT_USED => MM2S_DM_BTT_LENGTH_WIDTH , C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH , C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF , C_ENABLE_SKID_BUF => "11100" , C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE , C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED , C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO , C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => DM_CLOCK_SYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_ENABLE_S2MM_TKEEP => C_S2MM_ENABLE_TKEEP , C_S2MM_BURST_SIZE => C_S2MM_MAX_BURST_LENGTH , C_S2MM_BTT_USED => S2MM_DM_BTT_LENGTH_WIDTH , C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT , C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH , C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF , C_FAMILY => C_ROOT_FAMILY ) port map( -- MM2S Primary Clock / Reset input m_axi_mm2s_aclk => m_axi_mm2s_aclk , m_axi_mm2s_aresetn => mm2s_dm_prmry_resetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_allow_addr_req => ALWAYS_ALLOW , mm2s_addr_req_posted => open , mm2s_rd_xfer_cmplt => open , -- Memory Map to Stream Command FIFO and Status FIFO I/O -------------- m_axis_mm2s_cmdsts_aclk => m_axi_mm2s_aclk , m_axis_mm2s_cmdsts_aresetn => mm2s_dm_prmry_resetn , -- User Command Interface Ports (AXI Stream) s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid , s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready , s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid , m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready , m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata , m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep , m_axis_mm2s_sts_tlast => open , -- MM2S AXI Address Channel I/O -------------------------------------- m_axi_mm2s_arid => open , m_axi_mm2s_araddr => m_axi_mm2s_araddr , m_axi_mm2s_arlen => m_axi_mm2s_arlen , m_axi_mm2s_arsize => m_axi_mm2s_arsize , m_axi_mm2s_arburst => m_axi_mm2s_arburst , m_axi_mm2s_arprot => m_axi_mm2s_arprot , m_axi_mm2s_arcache => m_axi_mm2s_arcache , m_axi_mm2s_arvalid => m_axi_mm2s_arvalid , m_axi_mm2s_arready => m_axi_mm2s_arready , -- MM2S AXI MMap Read Data Channel I/O ------------------------------- m_axi_mm2s_rdata => m_axi_mm2s_rdata , m_axi_mm2s_rresp => m_axi_mm2s_rresp , m_axi_mm2s_rlast => m_axi_mm2s_rlast , m_axi_mm2s_rvalid => m_axi_mm2s_rvalid , m_axi_mm2s_rready => m_axi_mm2s_rready , -- MM2S AXI Master Stream Channel I/O -------------------------------- m_axis_mm2s_tdata => dm2linebuf_mm2s_tdata , m_axis_mm2s_tkeep => dm2linebuf_mm2s_tkeep , m_axis_mm2s_tlast => dm2linebuf_mm2s_tlast , m_axis_mm2s_tvalid => dm2linebuf_mm2s_tvalid , m_axis_mm2s_tready => linebuf2dm_mm2s_tready , -- Testing Support I/O mm2s_dbg_sel => (others => '0') , mm2s_dbg_data => open , -- Datamover v4_02_a addional signals not needed for VDMA --sg_ctl => (others => '0') , m_axi_mm2s_aruser => open , m_axi_s2mm_awuser => open , -- S2MM Primary Clock/Reset input m_axi_s2mm_aclk => m_axi_s2mm_aclk , m_axi_s2mm_aresetn => s2mm_dm_prmry_resetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_allow_addr_req => ALWAYS_ALLOW , s2mm_addr_req_posted => open , s2mm_wr_xfer_cmplt => open , s2mm_ld_nxt_len => open , s2mm_wr_len => open , -- Stream to Memory Map Command FIFO and Status FIFO I/O -------------- m_axis_s2mm_cmdsts_awclk => m_axi_s2mm_aclk , m_axis_s2mm_cmdsts_aresetn => s2mm_dm_prmry_resetn , -- User Command Interface Ports (AXI Stream) s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid , s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready , s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid , m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready , m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata , m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep , m_axis_s2mm_sts_tlast => open , -- S2MM AXI Address Channel I/O -------------------------------------- m_axi_s2mm_awid => open , m_axi_s2mm_awaddr => m_axi_s2mm_awaddr , m_axi_s2mm_awlen => m_axi_s2mm_awlen , m_axi_s2mm_awsize => m_axi_s2mm_awsize , m_axi_s2mm_awburst => m_axi_s2mm_awburst , m_axi_s2mm_awprot => m_axi_s2mm_awprot , m_axi_s2mm_awcache => m_axi_s2mm_awcache , m_axi_s2mm_awvalid => m_axi_s2mm_awvalid , m_axi_s2mm_awready => m_axi_s2mm_awready , -- S2MM AXI MMap Write Data Channel I/O ------------------------------ m_axi_s2mm_wdata => m_axi_s2mm_wdata , m_axi_s2mm_wstrb => m_axi_s2mm_wstrb , m_axi_s2mm_wlast => m_axi_s2mm_wlast , m_axi_s2mm_wvalid => m_axi_s2mm_wvalid , m_axi_s2mm_wready => m_axi_s2mm_wready , -- S2MM AXI MMap Write response Channel I/O -------------------------- m_axi_s2mm_bresp => m_axi_s2mm_bresp , m_axi_s2mm_bvalid => m_axi_s2mm_bvalid , m_axi_s2mm_bready => m_axi_s2mm_bready , -- S2MM AXI Slave Stream Channel I/O --------------------------------- s_axis_s2mm_tdata => linebuf2dm_s2mm_tdata , s_axis_s2mm_tkeep => linebuf2dm_s2mm_tkeep , s_axis_s2mm_tlast => linebuf2dm_s2mm_tlast , s_axis_s2mm_tvalid => linebuf2dm_s2mm_tvalid , s_axis_s2mm_tready => dm2linebuf_s2mm_tready , -- Testing Support I/O s2mm_dbg_sel => (others => '0') , s2mm_dbg_data => open ); end implementation;
gpl-2.0
freecores/t48
rtl/vhdl/dmem_ctrl.vhd
1
7210
------------------------------------------------------------------------------- -- -- The Data Memory control unit. -- All accesses to the Data Memory are managed here. -- -- $Id: dmem_ctrl.vhd,v 1.5 2006-06-20 01:07:16 arniml Exp $ -- -- Copyright (c) 2004, Arnim Laeuger ([email protected]) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- The latest version of this file can be found at: -- http://www.opencores.org/cvsweb.shtml/t48/ -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.t48_pack.dmem_addr_t; use work.t48_pack.word_t; use work.t48_dmem_ctrl_pack.dmem_addr_ident_t; entity t48_dmem_ctrl is port ( -- Global Interface ------------------------------------------------------- clk_i : in std_logic; res_i : in std_logic; en_clk_i : in boolean; -- Control Interface ------------------------------------------------------ data_i : in word_t; write_dmem_addr_i : in boolean; write_dmem_i : in boolean; read_dmem_i : in boolean; addr_type_i : in dmem_addr_ident_t; bank_select_i : in std_logic; data_o : out word_t; -- Data Memory Interface -------------------------------------------------- dmem_data_i : in word_t; dmem_addr_o : out dmem_addr_t; dmem_we_o : out std_logic; dmem_data_o : out word_t ); end t48_dmem_ctrl; library ieee; use ieee.numeric_std.all; use work.t48_pack.clk_active_c; use work.t48_pack.res_active_c; use work.t48_pack.bus_idle_level_c; use work.t48_pack.to_stdLogic; use work.t48_dmem_ctrl_pack.all; architecture rtl of t48_dmem_ctrl is signal dmem_addr_s, dmem_addr_q : dmem_addr_t; begin ----------------------------------------------------------------------------- -- Process addr_decode -- -- Purpose: -- Decode/multiplex the address information for the Data Memory. -- addr_decode: process (data_i, addr_type_i, bank_select_i, dmem_addr_q) variable stack_addr_v : unsigned(5 downto 0); begin -- default assignment dmem_addr_s <= dmem_addr_q; stack_addr_v := (others => '0'); case addr_type_i is when DM_PLAIN => dmem_addr_s <= data_i; when DM_REG => dmem_addr_s <= (others => '0'); dmem_addr_s(2 downto 0) <= data_i(2 downto 0); -- implement bank switching if bank_select_i = '1' then -- dmem address 24 - 31: access proper set dmem_addr_s(4 downto 3) <= "11"; end if; when DM_STACK => -- build address from stack pointer stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0)); -- dmem address 8 - 23 stack_addr_v := stack_addr_v + 8; dmem_addr_s <= (others => '0'); dmem_addr_s(5 downto 0) <= std_logic_vector(stack_addr_v); when DM_STACK_HIGH => dmem_addr_s(0) <= '1'; when others => -- do nothing -- pragma translate_off assert false report "Unknown address type identification for Data Memory controller!" severity error; -- pragma translate_on end case; end process addr_decode; -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Process dmem_addr_reg -- -- Purpose: -- Implements the Data Memory Address Register. -- This register is required to hold the address during a write operation -- as we cannot hold the address in the input register of the -- synchronous RAM (no clock suppression/gating). -- -- NOTE: May be obsoleted by clock enable feature of generic RTL RAM. -- dmem_addr_reg: process (res_i, clk_i) begin if res_i = res_active_c then dmem_addr_q <= (others => '0'); elsif clk_i'event and clk_i = clk_active_c then if en_clk_i then if write_dmem_addr_i then dmem_addr_q <= dmem_addr_s; end if; end if; end if; end process dmem_addr_reg; -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Output mapping. ----------------------------------------------------------------------------- dmem_addr_o <= dmem_addr_s when write_dmem_addr_i and en_clk_i else dmem_addr_q; -- data from bus is fed through dmem_data_o <= data_i; -- data to bus is enabled upon read request data_o <= dmem_data_i when read_dmem_i else (others => bus_idle_level_c); -- write enable to Data Memory is fed through dmem_we_o <= to_stdLogic(write_dmem_i); end rtl; ------------------------------------------------------------------------------- -- File History: -- -- $Log: not supported by cvs2svn $ -- Revision 1.4 2005/06/11 10:08:43 arniml -- introduce prefix 't48_' for all packages, entities and configurations -- -- Revision 1.3 2004/04/24 23:44:25 arniml -- move from std_logic_arith to numeric_std -- -- Revision 1.2 2004/04/18 18:58:29 arniml -- clean up sensitivity list -- -- Revision 1.1 2004/03/23 21:31:52 arniml -- initial check-in -- -------------------------------------------------------------------------------
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_iic_v2_0/30815c58/hdl/src/vhdl/axi_iic.vhd
2
13259
------------------------------------------------------------------------------- -- axi_iic.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- *************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2011 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- *************************************************************************** ------------------------------------------------------------------------------- -- Filename: axi_iic.vhd -- Version: v1.01.b -- Description: -- This file is the top level file that contains the IIC AXI -- Interface. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- axi_iic.vhd -- -- iic.vhd -- -- axi_ipif_ssp1.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- soft_reset.vhd -- -- reg_interface.vhd -- -- filter.vhd -- -- debounce.vhd -- -- iic_control.vhd -- -- upcnt_n.vhd -- -- shift8.vhd -- -- dynamic_master.vhd -- -- iic_pkg.vhd -- ------------------------------------------------------------------------------- -- Author: USM -- -- USM 10/15/09 -- ^^^^^^ -- - Initial release of v1.00.a -- ~~~~~~ -- -- USM 09/06/10 -- ^^^^^^ -- - Release of v1.01.a -- - Added function calc_tbuf in iic_control to calculate the TBUF delay -- ~~~~~~ -- -- NLR 01/07/11 -- ^^^^^^ -- - Fixed the CR#613282 and CR#613486 -- - Release of v1.01.b ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library axi_iic_v2_0; use axi_iic_v2_0.iic_pkg.all; ------------------------------------------------------------------------------- -- Definition of Generics: -- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz -- C_TEN_BIT_ADR -- 10 bit slave addressing -- C_GPO_WIDTH -- Width of General purpose output vector -- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency -- C_SCL_INERTIAL_DELAY -- SCL filtering -- C_SDA_INERTIAL_DELAY -- SDA filtering -- C_SDA_LEVEL -- SDA level -- C_SMBUS_PMBUS_HOST -- Acts as SMBus/PMBus host when enabled -- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits) -- C_FAMILY -- XILINX FPGA family ------------------------------------------------------------------------------- -- Definition of ports: -- -- System Signals -- s_axi_aclk -- AXI Clock -- s_axi_aresetn -- AXI Reset -- IP2INTC_Irpt -- System interrupt output -- --AXI signals -- s_axi_awaddr -- AXI Write address -- s_axi_awvalid -- Write address valid -- s_axi_awready -- Write address ready -- s_axi_wdata -- Write data -- s_axi_wstrb -- Write strobes -- s_axi_wvalid -- Write valid -- s_axi_wready -- Write ready -- s_axi_bresp -- Write response -- s_axi_bvalid -- Write response valid -- s_axi_bready -- Response ready -- s_axi_araddr -- Read address -- s_axi_arvalid -- Read address valid -- s_axi_arready -- Read address ready -- s_axi_rdata -- Read data -- s_axi_rresp -- Read response -- s_axi_rvalid -- Read valid -- s_axi_rready -- Read ready -- IIC Signals -- sda_i -- IIC serial data input -- sda_o -- IIC serial data output -- sda_t -- IIC seral data output enable -- scl_i -- IIC serial clock input -- scl_o -- IIC serial clock output -- scl_t -- IIC serial clock output enable -- gpo -- General purpose outputs -- ------------------------------------------------------------------------------- -- Entity section ------------------------------------------------------------------------------- entity axi_iic is generic ( -- FPGA Family Type specification C_FAMILY : string := "virtex7"; -- Select the target architecture type -- AXI Parameters --C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32; --9 C_S_AXI_ADDR_WIDTH : integer := 9; --9 C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; -- AXI IIC Feature generics C_IIC_FREQ : integer := 100E3; C_TEN_BIT_ADR : integer := 0; C_GPO_WIDTH : integer := 1; C_S_AXI_ACLK_FREQ_HZ : integer := 25E6; C_SCL_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds C_SDA_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds C_SDA_LEVEL : integer := 1; -- delay in nanoseconds C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF" ); port ( -- System signals s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic := '1'; iic2intc_irpt : out std_logic; -- AXI signals s_axi_awaddr : in std_logic_vector (8 downto 0); --(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector (31 downto 0); --(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector (3 downto 0); --((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(8 downto 0); --(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector (31 downto 0); --(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- IIC interface signals sda_i : in std_logic; sda_o : out std_logic; sda_t : out std_logic; scl_i : in std_logic; scl_o : out std_logic; scl_t : out std_logic; gpo : out std_logic_vector(C_GPO_WIDTH-1 downto 0) ); end entity axi_iic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture RTL of axi_iic is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes"; constant C_NUM_IIC_REGS : integer := 18; begin X_IIC: entity axi_iic_v2_0.iic generic map ( -- System Generics C_NUM_IIC_REGS => C_NUM_IIC_REGS, -- Number of IIC Registers --iic Generics to be set by user C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ => C_IIC_FREQ, -- default iic Serial 100KHz C_TEN_BIT_ADR => C_TEN_BIT_ADR, -- [integer] C_GPO_WIDTH => C_GPO_WIDTH, -- [integer] C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- delay in nanoseconds C_SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY, -- delay in nanoseconds C_SDA_LEVEL => C_SDA_LEVEL, C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST, -- Transmit FIFO Generic -- Removed as user input 10/08/01 -- Software will not be tested without FIFO's C_TX_FIFO_EXIST => TRUE, -- [boolean] -- Recieve FIFO Generic -- Removed as user input 10/08/01 -- Software will not be tested without FIFO's C_RC_FIFO_EXIST => TRUE, -- [boolean] -- AXI interface generics C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, -- [integer 9] -- width of the AXI Address Bus (in bits) C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, -- [integer range 32 to 32] -- Width of the AXI Data Bus (in bits) C_FAMILY => C_FAMILY, -- [string] C_DEFAULT_VALUE => C_DEFAULT_VALUE ) port map ( -- System signals S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, IIC2INTC_IRPT => iic2intc_iRPT, -- AXI Interface signals S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready, -- IIC Bus Signals SDA_I => sda_i, SDA_O => sda_o, SDA_T => sda_t, SCL_I => scl_i, SCL_O => scl_o, SCL_T => scl_t, GPO => gpo ); end architecture RTL;
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/lib_cdc_v1_0/d3fab4a1/hdl/src/vhdl/cdc_sync.vhd
21
47317
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
gpl-2.0
freecores/t48
bench/vhdl/tb_t8048_t8243-c.vhd
1
1057
------------------------------------------------------------------------------- -- -- The testbench for t8048 driving a t8243. -- -- $Id: tb_t8048_t8243-c.vhd,v 1.1 2006-07-13 22:55:10 arniml Exp $ -- -- Copyright (c) 2006, Arnim Laeuger ([email protected]) -- -- All rights reserved -- ------------------------------------------------------------------------------- configuration tb_t8048_t8243_behav_c0 of tb_t8048_t8243 is for behav for ext_ram_b : generic_ram_ena use configuration work.generic_ram_ena_rtl_c0; end for; for ext_rom_b : lpm_rom use configuration work.lpm_rom_c0; end for; for t8048_b : t8048 use configuration work.t8048_struct_c0; end for; for t8243_b : t8243 use configuration work.t8243_struct_c0; end for; end for; end tb_t8048_t8243_behav_c0; ------------------------------------------------------------------------------- -- File History: -- -- $Log: not supported by cvs2svn $ -------------------------------------------------------------------------------
gpl-2.0
nulldozer/purisc
Compute_Group/CORE/purisc_core.vhd
1
6794
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity purisc_core is port( clk, reset_n : in std_logic; r_addr_a, r_addr_b, r_addr_c, r_addr_0, r_addr_1 : out std_logic_vector(31 downto 0); w_data, w_addr : out std_logic_vector(31 downto 0); we : out std_logic; stall : in std_logic; id : in std_logic_vector(2 downto 0); r_data_a, r_data_b, r_data_c, r_data_0, r_data_1 : in std_logic_vector(31 downto 0) ); end entity; architecture arch of purisc_core is --top core signals signal start_address : std_logic_vector(31 downto 0); --ri output signals signal ri_a : std_logic_vector(31 downto 0); signal ri_b : std_logic_vector(31 downto 0); signal ri_c : std_logic_vector(31 downto 0); signal ri_next_pc : std_logic_vector(31 downto 0); --rd output signals signal rd_a : std_logic_vector(31 downto 0); signal rd_b : std_logic_vector(31 downto 0); signal rd_c : std_logic_vector(31 downto 0); signal rd_addr_a : std_logic_vector(31 downto 0); signal rd_addr_b : std_logic_vector(31 downto 0); signal rd_addr_c : std_logic_vector(31 downto 0); signal rd_next_pc : std_logic_vector(31 downto 0); signal rd_ubranch : std_logic; signal rd_noop : std_logic; --ex output signals signal ex_b : std_logic_vector(31 downto 0); --ex_b is another name for for ex_w_addr signal ex_db : std_logic_vector(31 downto 0); --ex_b is another name for for ex_w_data signal ex_cbranch : std_logic; signal ex_cbranch_addr : std_logic_vector(31 downto 0); signal ex_noop : std_logic; --ex input signals signal ex_da_in, ex_db_in : std_logic_vector(31 downto 0); --ex output signals signal ex_w_data, ex_w_addr : std_logic_vector(31 downto 0); signal ex_we : std_logic; --ri stage component read_instruction_stage is port( clk : in std_logic; reset_n : in std_logic; stall : in std_logic; start_address : in std_logic_vector(31 downto 0); cbranch : in std_logic; cbranch_addr : in std_logic_vector(31 downto 0); ubranch : in std_logic; ubranch_addr : in std_logic_vector(31 downto 0); --outputs next_pc : out std_logic_vector(31 downto 0); --memory r_addr_inst : out std_logic_vector(31 downto 0) ); end component; --rd stage component read_data_stage is port( clk : in std_logic; reset_n : in std_logic; stall : in std_logic; -- inputs start_address : in std_logic_vector(31 downto 0); ex_w_addr : in std_logic_vector(31 downto 0); ex_w_data : in std_logic_vector(31 downto 0); ex_we : in std_logic; a_in : in std_logic_vector(31 downto 0); b_in : in std_logic_vector(31 downto 0); c_in : in std_logic_vector(31 downto 0); addr_a : in std_logic_vector(31 downto 0); addr_b : in std_logic_vector(31 downto 0); addr_c : in std_logic_vector(31 downto 0); next_pc : in std_logic_vector(31 downto 0); ubranch_in : in std_logic; cbranch_in : in std_logic; --outputs a_out : out std_logic_vector(31 downto 0); b_out : out std_logic_vector(31 downto 0); c_out : out std_logic_vector(31 downto 0); addr_a_out : out std_logic_vector(31 downto 0); addr_b_out : out std_logic_vector(31 downto 0); addr_c_out : out std_logic_vector(31 downto 0); ubranch_out : out std_logic; noop_out : out std_logic; r_addr_0 : out std_logic_vector(31 downto 0); r_addr_1 : out std_logic_vector(31 downto 0); next_pc_out : out std_logic_vector(31 downto 0) ); end component; --ex stage component execute_stage is port( clk : in std_logic; reset_n : in std_logic; stall : in std_logic; noop_in : in std_logic; --inputs ubranch_in : in std_logic; cbranch_in : in std_logic; start_address : in std_logic_vector(31 downto 0); ex_w_addr : in std_logic_vector(31 downto 0); ex_w_data : in std_logic_vector(31 downto 0); ex_we : in std_logic; a_in : in std_logic_vector(31 downto 0); b_in : in std_logic_vector(31 downto 0); c_in : in std_logic_vector(31 downto 0); addr_a : in std_logic_vector(31 downto 0); addr_b : in std_logic_vector(31 downto 0); addr_c : in std_logic_vector(31 downto 0); next_pc : in std_logic_vector(31 downto 0); --outputs cbranch_out : out std_logic; cbranch_addr : out std_logic_vector(31 downto 0); -- memory da_in : in std_logic_vector(31 downto 0); db_in : in std_logic_vector(31 downto 0); w_data : out std_logic_vector(31 downto 0); w_addr : out std_logic_vector(31 downto 0); we_out : out std_logic ); end component; begin ri : read_instruction_stage port map ( --in clk => clk, reset_n => reset_n, stall => stall, start_address => start_address, cbranch => ex_cbranch, cbranch_addr => ex_cbranch_addr, ubranch => rd_ubranch, ubranch_addr => rd_c, next_pc => ri_next_pc, r_addr_inst => ri_a ); rd : read_data_stage port map ( clk => clk, reset_n => reset_n, stall => stall, -- inputs start_address => start_address, ex_w_addr => ex_w_addr, ex_w_data => ex_w_data, ex_we => ex_we, a_in => r_data_a, b_in => r_data_b, c_in => r_data_c, addr_a => ri_a, addr_b => ri_b, addr_c => ri_c, next_pc => ri_next_pc, ubranch_in => rd_ubranch, cbranch_in => ex_cbranch, --outputs a_out => rd_a, b_out => rd_b, c_out => rd_c, addr_a_out => rd_addr_a, addr_b_out => rd_addr_b, addr_c_out => rd_addr_c, ubranch_out => rd_ubranch, noop_out => rd_noop, r_addr_0 => r_addr_0, r_addr_1 => r_addr_1, next_pc_out => rd_next_pc ); ex : execute_stage port map ( clk => clk, reset_n => reset_n, stall => stall, noop_in => rd_noop, --inputs ubranch_in => rd_ubranch, cbranch_in => ex_cbranch, start_address => start_address, ex_w_addr => ex_w_addr, ex_w_data => ex_w_data, ex_we => ex_we, a_in => rd_a, b_in => rd_b, c_in => rd_c, addr_a => rd_addr_a, addr_b => rd_addr_b, addr_c => rd_addr_c, next_pc => rd_next_pc, --outputs cbranch_addr => ex_cbranch_addr, cbranch_out => ex_cbranch, -- memory da_in => r_data_0, db_in => r_data_1, w_data => ex_w_data, w_addr => ex_w_addr, we_out => ex_we ); -- hard coded start address offset (this should be half of local memory size) start_address <= "00000000000000000000000000000000" when id(0)='0' else "00000000000000000001000000000000"; --address calculation for cache ri_b <= std_logic_vector(unsigned(ri_a) + 1); ri_c <= std_logic_vector(unsigned(ri_a) + 2); --connecting modules to top level io w_data <= ex_w_data; w_addr <= ex_w_addr; we <= ex_we; --alternate names r_addr_a <= ri_a; r_addr_b <= ri_b; r_addr_c <= ri_c; end architecture;
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd
1
14890
------------------------------------------------------------------------------- -- axi_sg_ftch_noqueue ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_noqueue.vhd -- Description: This entity is the no queue version -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_sg.vhd -- axi_sg_pkg.vhd -- |- axi_sg_ftch_mngr.vhd -- | |- axi_sg_ftch_sm.vhd -- | |- axi_sg_ftch_pntr.vhd -- | |- axi_sg_ftch_cmdsts_if.vhd -- |- axi_sg_updt_mngr.vhd -- | |- axi_sg_updt_sm.vhd -- | |- axi_sg_updt_cmdsts_if.vhd -- |- axi_sg_ftch_q_mngr.vhd -- | |- axi_sg_ftch_queue.vhd -- | | |- proc_common_v4_0.sync_fifo_fg.vhd -- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd -- | |- axi_sg_ftch_noqueue.vhd -- |- axi_sg_updt_q_mngr.vhd -- | |- axi_sg_updt_queue.vhd -- | | |- proc_common_v4_0.sync_fifo_fg.vhd -- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd -- | |- axi_sg_updt_noqueue.vhd -- |- axi_sg_intrpt.vhd -- |- axi_datamover_v5_0.axi_datamover.vhd -- ------------------------------------------------------------------------------- -- Author: Gary Burch -- History: -- GAB 6/16/10 v4_03 -- ^^^^^^ -- - Initial Release -- ~~~~~~ ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_vdma_v6_2; use axi_vdma_v6_2.axi_sg_pkg.all; library lib_pkg_v1_0; library lib_fifo_v1_0; use lib_fifo_v1_0.sync_fifo_fg; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_ftch_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 -- Master AXI Stream Data Width ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel Control -- desc_flush : in std_logic ; -- ftch_active : in std_logic ; -- ftch_queue_empty : out std_logic ; -- ftch_queue_full : out std_logic ; -- -- writing_nxtdesc_in : in std_logic ; -- writing_curdesc_out : out std_logic ; -- -- DataMover Command -- ftch_cmnd_wr : in std_logic ; -- ftch_cmnd_data : in std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- MM2S Stream In from DataMover -- m_axis_mm2s_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_mm2s_tlast : in std_logic ; -- m_axis_mm2s_tvalid : in std_logic ; -- m_axis_mm2s_tready : out std_logic ; -- -- -- Channel 1 AXI Fetch Stream Out -- m_axis_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_ftch_tvalid : out std_logic ; -- m_axis_ftch_tready : in std_logic ; -- m_axis_ftch_tlast : out std_logic -- ); end axi_sg_ftch_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel 1 internal signals signal curdesc_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc_tvalid : std_logic := '0'; signal ftch_tvalid : std_logic := '0'; signal ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ftch_tlast : std_logic := '0'; signal ftch_tready : std_logic := '0'; -- Misc Signals signal writing_curdesc : std_logic := '0'; signal writing_nxtdesc : std_logic := '0'; signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0'); signal writing_lsb : std_logic := '0'; signal writing_msb : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- Write current descriptor to FIFO or out channel port --------------------------------------------------------------------------- WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then curdesc_tdata <= (others => '0'); curdesc_tvalid <= '0'; writing_lsb <= '0'; writing_msb <= '0'; -- Write LSB Address on command write elsif(ftch_cmnd_wr = '1' and ftch_active = '1')then curdesc_tdata <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST + DATAMOVER_CMD_ADDRLSB_BIT downto DATAMOVER_CMD_ADDRLSB_BIT); curdesc_tvalid <= '1'; writing_lsb <= '1'; writing_msb <= '0'; -- On ready write MSB address elsif(writing_lsb = '1' and ftch_tready = '1')then curdesc_tdata <= msb_curdesc; curdesc_tvalid <= '1'; writing_lsb <= '0'; writing_msb <= '1'; -- On MSB write and ready then clear all elsif(writing_msb = '1' and ftch_tready = '1')then curdesc_tdata <= (others => '0'); curdesc_tvalid <= '0'; writing_lsb <= '0'; writing_msb <= '0'; end if; end if; end process WRITE_CURDESC_PROCESS; --------------------------------------------------------------------------- -- TVALID MUX -- MUX tvalid out channel port --------------------------------------------------------------------------- TVALID_TDATA_MUX : process(writing_curdesc, writing_nxtdesc, ftch_active, curdesc_tvalid, curdesc_tdata, m_axis_mm2s_tvalid, m_axis_mm2s_tdata, m_axis_mm2s_tlast) begin -- Select current descriptor to drive out (Queue or Channel Port) if(writing_curdesc = '1')then ftch_tvalid <= curdesc_tvalid; ftch_tdata <= curdesc_tdata; ftch_tlast <= '0'; -- Deassert tvalid when capturing next descriptor pointer elsif(writing_nxtdesc = '1')then ftch_tvalid <= '0'; ftch_tdata <= (others => '0'); ftch_tlast <= '0'; -- Otherwise drive data from Datamover out (Queue or Channel Port) elsif(ftch_active = '1')then ftch_tvalid <= m_axis_mm2s_tvalid; ftch_tdata <= m_axis_mm2s_tdata; ftch_tlast <= m_axis_mm2s_tlast; else ftch_tvalid <= '0'; ftch_tdata <= (others => '0'); ftch_tlast <= '0'; end if; end process TVALID_TDATA_MUX; --------------------------------------------------------------------------- -- Map internal stream to external --------------------------------------------------------------------------- m_axis_ftch_tdata <= ftch_tdata; m_axis_ftch_tlast <= ftch_tlast; m_axis_ftch_tvalid <= ftch_tvalid; ftch_tready <= m_axis_ftch_tready; m_axis_mm2s_tready <= ftch_tready; --------------------------------------------------------------------------- -- generate psuedo empty flag for Idle generation --------------------------------------------------------------------------- Q_EMPTY_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then if(m_axi_sg_aresetn = '0' or desc_flush = '1')then ftch_queue_empty <= '1'; -- Else on valid and ready modify empty flag elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1')then -- On last mark as empty if(ftch_tlast = '1' )then ftch_queue_empty <= '1'; -- Otherwise mark as not empty else ftch_queue_empty <= '0'; end if; end if; end if; end process Q_EMPTY_PROCESS; -- do not need to indicate full to axi_sg_ftch_sm. Only -- needed for queue case to allow other channel to be serviced -- if it had queue room ftch_queue_full <= '0'; -- If writing curdesc out then flag for proper mux selection writing_curdesc <= curdesc_tvalid; -- Map intnal signal to port writing_curdesc_out <= writing_curdesc; -- Map port to internal signal writing_nxtdesc <= writing_nxtdesc_in; end implementation;
gpl-2.0
Caneda/Caneda
libraries/hdl/vhdl/asynchronous/adder.vhd
1
384
-- in1, in2 and the cin (carry) are inputs -- output is the sum output, cout is the carry out ENTITY adder IS port (in1, in2 : IN bit; cin : IN bit; output : OUT bit; cout : OUT bit); END adder; ARCHITECTURE rtl OF adder IS BEGIN output <= in1 xor in2 xor cin; cout <= (in1 and in2) or (in1 and cin) or (in2 and cin); END rtl;
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_iic_v2_0/30815c58/hdl/src/vhdl/dynamic_master.vhd
2
16342
------------------------------------------------------------------------------- -- dynamic_master.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- *************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2011 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- *************************************************************************** ------------------------------------------------------------------------------- -- Filename: dynamic_master.vhd -- Version: v1.01.b -- Description: -- This file contains the control logic for the dynamic master. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- axi_iic.vhd -- -- iic.vhd -- -- axi_ipif_ssp1.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- soft_reset.vhd -- -- reg_interface.vhd -- -- filter.vhd -- -- debounce.vhd -- -- iic_control.vhd -- -- upcnt_n.vhd -- -- shift8.vhd -- -- dynamic_master.vhd -- -- iic_pkg.vhd -- ------------------------------------------------------------------------------- -- Author: USM -- -- USM 10/15/09 -- ^^^^^^ -- - Initial release of v1.00.a -- ~~~~~~ -- -- USM 09/06/10 -- ^^^^^^ -- - Release of v1.01.a -- ~~~~~~ -- -- NLR 01/07/11 -- ^^^^^^ -- - Release of v1.01.b -- ~~~~~~ ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; ------------------------------------------------------------------------------- -- Definition of Ports: -- Clk -- System clock -- Rst -- System reset -- Dynamic_MSMS -- Dynamic master slave mode select -- Cr -- Control register -- Tx_fifo_rd_i -- Transmit FIFO read -- Tx_data_exists -- Trnasmit FIFO exists -- AckDataState -- Data ack acknowledge signal -- Tx_fifo_data -- Transmit FIFO read input -- EarlyAckHdr -- Ack_header state strobe signal -- EarlyAckDataState -- Data ack early acknowledge signal -- Bb -- Bus busy indicator -- Msms_rst_r -- MSMS reset indicator -- DynMsmsSet -- Dynamic MSMS set signal -- DynRstaSet -- Dynamic repeated start set signal -- Msms_rst -- MSMS reset signal -- TxFifoRd -- Transmit FIFO read output signal -- Txak -- Transmit ack signal -- Cr_txModeSelect_set -- Sets transmit mode select -- Cr_txModeSelect_clr -- Clears transmit mode select ------------------------------------------------------------------------------- -- Entity section ------------------------------------------------------------------------------- entity dynamic_master is port( Clk : in std_logic; Rst : in std_logic; Dynamic_MSMS : in std_logic_vector(0 to 1); Cr : in std_logic_vector(0 to 7); Tx_fifo_rd_i : in std_logic; Tx_data_exists : in std_logic; AckDataState : in std_logic; Tx_fifo_data : in std_logic_vector(0 to 7); EarlyAckHdr : in std_logic; EarlyAckDataState : in std_logic; Bb : in std_logic; Msms_rst_r : in std_logic; DynMsmsSet : out std_logic; DynRstaSet : out std_logic; Msms_rst : out std_logic; TxFifoRd : out std_logic; Txak : out std_logic; Cr_txModeSelect_set : out std_logic; Cr_txModeSelect_clr : out std_logic ); end dynamic_master; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture RTL of dynamic_master is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes"; ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal firstDynStartSeen : std_logic; -- used to detect re-start during -- dynamic start generation signal dynamic_MSMS_d : std_logic_vector(0 to 1); signal rxCntDone : std_logic; signal forceTxakHigh : std_logic; signal earlyAckDataState_d1: std_logic; signal ackDataState_d1 : std_logic; signal rdByteCntr : unsigned(0 to 7); signal rdCntrFrmTxFifo : std_logic; signal callingReadAccess : std_logic; signal dynamic_start : std_logic; signal dynamic_stop : std_logic; ------------------------------------------------------------------------------- begin -- In the case where the tx fifo only contains a single byte (the address) -- which contains both start and stop bits set the controller has to rely on -- the tx fifo data exists flag to qualify the fifo output. Otherwise the -- controller emits a continous stream of bytes. This fixes CR439857 dynamic_start <= Dynamic_MSMS(1) and Tx_data_exists; dynamic_stop <= Dynamic_MSMS(0) and Tx_data_exists; DynMsmsSet <= dynamic_start -- issue dynamic start by setting MSMS and not(Cr(5)) -- when MSMS is not already set and and not(Bb); -- bus isn't busy DynRstaSet <= dynamic_start -- issue repeated start when and Tx_fifo_rd_i and firstDynStartSeen; -- MSMS is already set Msms_rst <= (dynamic_stop and Tx_fifo_rd_i) or Msms_rst_r or rxCntDone; TxFifoRd <= Tx_fifo_rd_i or rdCntrFrmTxFifo; forceTxakHigh <= '1' when (EarlyAckDataState='1' and callingReadAccess='1' and rdByteCntr = 0) else '0'; Txak <= Cr(3) or forceTxakHigh; ----------------------------------------------------------------------------- -- PROCESS: DYN_MSMS_DLY_PROCESS -- purpose: Dynamic Master MSMS registering ----------------------------------------------------------------------------- DYN_MSMS_DLY_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then dynamic_MSMS_d <= (others => '0'); else dynamic_MSMS_d <= Dynamic_MSMS; end if; end if; end process DYN_MSMS_DLY_PROCESS; ----------------------------------------------------------------------------- -- PROCESS: DYN_START_PROCESS -- purpose: reset firstDynStartSeen if CR(5) MSMS is cleared ----------------------------------------------------------------------------- DYN_START_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then firstDynStartSeen <= '0'; else if(Cr(5) = '0') then firstDynStartSeen <= '0'; elsif(firstDynStartSeen = '0' and Tx_fifo_rd_i = '1' and dynamic_start = '1') then firstDynStartSeen <= '1'; end if; end if; end if; end process DYN_START_PROCESS; ----------------------------------------------------------------------------- -- PROCESS: DYN_RD_ACCESS_PROCESS -- purpose: capture access direction initiated via dynamic Start ----------------------------------------------------------------------------- DYN_RD_ACCESS_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then callingReadAccess <= '0'; else if(Tx_fifo_rd_i = '1' and dynamic_start = '1') then callingReadAccess <= Tx_fifo_data(7); end if; end if; end if; end process DYN_RD_ACCESS_PROCESS; ----------------------------------------------------------------------------- -- PROCESS: DYN_MODE_SELECT_SET_PROCESS -- purpose: Set the tx Mode Select bit in the CR register at the begining of -- each ack_header state ----------------------------------------------------------------------------- DYN_MODE_SELECT_SET_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then Cr_txModeSelect_set <= '0'; elsif(EarlyAckHdr='1' and firstDynStartSeen='1') then Cr_txModeSelect_set <= not callingReadAccess; else Cr_txModeSelect_set <= '0'; end if; end if; end process DYN_MODE_SELECT_SET_PROCESS; ----------------------------------------------------------------------------- -- PROCESS: DYN_MODE_SELECT_CLR_PROCESS -- purpose: Clear the tx Mode Select bit in the CR register at the begining of -- each ack_header state ----------------------------------------------------------------------------- DYN_MODE_SELECT_CLR_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then Cr_txModeSelect_clr <= '0'; elsif(EarlyAckHdr='1' and firstDynStartSeen='1') then Cr_txModeSelect_clr <= callingReadAccess; else Cr_txModeSelect_clr <= '0'; end if; end if; end process DYN_MODE_SELECT_CLR_PROCESS; ----------------------------------------------------------------------------- -- PROCESS: DYN_RD_CNTR_PROCESS -- purpose: If this iic cycle is generating a read access, create a read -- of the tx fifo to get the number of tx to process ----------------------------------------------------------------------------- DYN_RD_CNTR_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then rdCntrFrmTxFifo <= '0'; else if(EarlyAckHdr='1' and Tx_data_exists='1' and callingReadAccess='1') then rdCntrFrmTxFifo <= '1'; else rdCntrFrmTxFifo <= '0'; end if; end if; end if; end process DYN_RD_CNTR_PROCESS; ----------------------------------------------------------------------------- -- PROCESS: DYN_RD_BYTE_CNTR_PROCESS -- purpose: If this iic cycle is generating a read access, create a read -- of the tx fifo to get the number of rx bytes to process ----------------------------------------------------------------------------- DYN_RD_BYTE_CNTR_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then rdByteCntr <= (others => '0'); else if(rdCntrFrmTxFifo='1') then rdByteCntr <= unsigned(Tx_fifo_data); elsif(EarlyAckDataState='1' and earlyAckDataState_d1='0' and rdByteCntr /= 0) then rdByteCntr <= rdByteCntr - 1; end if; end if; end if; end process DYN_RD_BYTE_CNTR_PROCESS; ----------------------------------------------------------------------------- -- PROCESS: DYN_RD_BYTE_CNTR_PROCESS -- purpose: Initialize read byte counter in order to control master -- generation of ack to slave. ----------------------------------------------------------------------------- DYN_EARLY_DATA_ACK_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then earlyAckDataState_d1 <= '0'; else earlyAckDataState_d1 <= EarlyAckDataState; end if; end if; end process DYN_EARLY_DATA_ACK_PROCESS; ----------------------------------------------------------------------------- -- PROCESS: DYN_STATE_DATA_ACK_PROCESS -- purpose: Register ackdatastate ----------------------------------------------------------------------------- DYN_STATE_DATA_ACK_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then ackDataState_d1 <= '0'; else ackDataState_d1 <= AckDataState; end if; end if; end process DYN_STATE_DATA_ACK_PROCESS; ----------------------------------------------------------------------------- -- PROCESS: DYN_STATE_DATA_ACK_PROCESS -- purpose: Generation of receive count done to generate stop ----------------------------------------------------------------------------- DYN_RX_CNT_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then rxCntDone <= '0'; else if(AckDataState='1' and ackDataState_d1='0' and callingReadAccess='1' and rdByteCntr = 0) then rxCntDone <= '1'; else rxCntDone <= '0'; end if; end if; end if; end process DYN_RX_CNT_PROCESS; end architecture RTL;
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/v_tc_v6_1/51f55007/hdl/v_tc_v6_1_vh_rfs.vhd
1
449533
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gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_mm2s_axis_dwidth_converter.vhd
2
25192
------------------------------------------------------------------------------- -- axi_vdma_mm2s_axis_dwidth_converter ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_vdma_mm2s_axis_dwidth_converter.vhd -- Description: This entity is the descriptor fetch command and status inteface -- for the Scatter Gather Engine AXI DataMover. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_vdma.vhd -- |- axi_vdma_pkg.vhd -- |- axi_vdma_intrpt.vhd -- |- axi_vdma_rst_module.vhd -- | |- axi_vdma_reset.vhd (mm2s) -- | | |- axi_vdma_cdc.vhd -- | |- axi_vdma_reset.vhd (s2mm) -- | | |- axi_vdma_cdc.vhd -- | -- |- axi_vdma_reg_if.vhd -- | |- axi_vdma_lite_if.vhd -- | |- axi_vdma_cdc.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_vdma_sg_cdc.vhd (mm2s) -- |- axi_vdma_vid_cdc.vhd (mm2s) -- |- axi_vdma_fsync_gen.vhd (mm2s) -- |- axi_vdma_sof_gen.vhd (mm2s) -- |- axi_vdma_reg_module.vhd (mm2s) -- | |- axi_vdma_register.vhd (mm2s) -- | |- axi_vdma_regdirect.vhd (mm2s) -- |- axi_vdma_mngr.vhd (mm2s) -- | |- axi_vdma_sg_if.vhd (mm2s) -- | |- axi_vdma_sm.vhd (mm2s) -- | |- axi_vdma_cmdsts_if.vhd (mm2s) -- | |- axi_vdma_vidreg_module.vhd (mm2s) -- | | |- axi_vdma_sgregister.vhd (mm2s) -- | | |- axi_vdma_vregister.vhd (mm2s) -- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s) -- | | |- axi_vdma_blkmem.vhd (mm2s) -- | |- axi_vdma_genlock_mngr.vhd (mm2s) -- | |- axi_vdma_genlock_mux.vhd (mm2s) -- | |- axi_vdma_greycoder.vhd (mm2s) -- |- axi_vdma_mm2s_linebuf.vhd (mm2s) -- | |- axi_vdma_sfifo_autord.vhd (mm2s) -- | |- axi_vdma_afifo_autord.vhd (mm2s) -- | |- axi_vdma_skid_buf.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (mm2s) -- | -- |- axi_vdma_sg_cdc.vhd (s2mm) -- |- axi_vdma_vid_cdc.vhd (s2mm) -- |- axi_vdma_fsync_gen.vhd (s2mm) -- |- axi_vdma_sof_gen.vhd (s2mm) -- |- axi_vdma_reg_module.vhd (s2mm) -- | |- axi_vdma_register.vhd (s2mm) -- | |- axi_vdma_regdirect.vhd (s2mm) -- |- axi_vdma_mngr.vhd (s2mm) -- | |- axi_vdma_sg_if.vhd (s2mm) -- | |- axi_vdma_sm.vhd (s2mm) -- | |- axi_vdma_cmdsts_if.vhd (s2mm) -- | |- axi_vdma_vidreg_module.vhd (s2mm) -- | | |- axi_vdma_sgregister.vhd (s2mm) -- | | |- axi_vdma_vregister.vhd (s2mm) -- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm) -- | | |- axi_vdma_blkmem.vhd (s2mm) -- | |- axi_vdma_genlock_mngr.vhd (s2mm) -- | |- axi_vdma_genlock_mux.vhd (s2mm) -- | |- axi_vdma_greycoder.vhd (s2mm) -- |- axi_vdma_s2mm_linebuf.vhd (s2mm) -- | |- axi_vdma_sfifo_autord.vhd (s2mm) -- | |- axi_vdma_afifo_autord.vhd (s2mm) -- | |- axi_vdma_skid_buf.vhd (s2mm) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL) -- |- axi_sg_v3_00_a.axi_sg.vhd -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_vdma_v6_2; use axi_vdma_v6_2.axi_vdma_pkg.all; entity axi_vdma_mm2s_axis_dwidth_converter is generic ( C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED : integer := 32; C_M_AXIS_MM2S_TDATA_WIDTH : integer := 32; C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 : integer := 4; C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0; ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ; C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 : integer := 4; -- C_AXIS_SIGNAL_SET : integer := 255; C_AXIS_TID_WIDTH : integer := 1; C_AXIS_TDEST_WIDTH : integer := 1; C_FAMILY : string := "virtex7" ); port ( ACLK :in std_logic; ARESETN :in std_logic; ACLKEN :in std_logic; mm2s_vsize_cntr_clr_flag : in std_logic ; fsync_out : in std_logic ; dwidth_fifo_pipe_empty : out std_logic ; all_lines_xfred_s_dwidth : out std_logic ; stop_reg : in std_logic ; dm_halt_reg : in std_logic ; crnt_vsize_d2 : in std_logic_vector(VSIZE_DWIDTH-1 downto 0) ; S_AXIS_TVALID :in std_logic; S_AXIS_TREADY :out std_logic; S_AXIS_TDATA :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0); S_AXIS_TSTRB :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0); S_AXIS_TKEEP :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0); S_AXIS_TLAST :in std_logic; S_AXIS_TID :in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0); S_AXIS_TDEST :in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0); S_AXIS_TUSER :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0); M_AXIS_TVALID :out std_logic; M_AXIS_TREADY :in std_logic; M_AXIS_TDATA :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); M_AXIS_TSTRB :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0); M_AXIS_TKEEP :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0); M_AXIS_TLAST :out std_logic; M_AXIS_TID :out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0); M_AXIS_TDEST :out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0); M_AXIS_TUSER :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0) ); end axi_vdma_mm2s_axis_dwidth_converter; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_vdma_mm2s_axis_dwidth_converter is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant ZERO_VALUE : std_logic_vector(255 downto 0) := (others => '0'); -- Constants for line tracking logic constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := std_logic_vector(to_unsigned(1,VSIZE_DWIDTH)); constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Verilog module component declarations ------------------------------------------------------------------------------- component axi_vdma_v6_2_axis_dwidth_converter_v1_0_axis_dwidth_converter is generic ( C_S_AXIS_TDATA_WIDTH : integer := 32; C_M_AXIS_TDATA_WIDTH : integer := 32; C_AXIS_TID_WIDTH : integer := 1; C_AXIS_TDEST_WIDTH : integer := 1; C_S_AXIS_TUSER_WIDTH : integer := 4; C_M_AXIS_TUSER_WIDTH : integer := 4; --C_AXIS_SIGNAL_SET : integer := 255; C_FAMILY : string := "virtex7" ); port ( ACLK :in std_logic; ARESETN :in std_logic; ACLKEN :in std_logic; S_AXIS_TVALID :in std_logic; S_AXIS_TREADY :out std_logic; S_AXIS_TDATA :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0); S_AXIS_TSTRB :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0); S_AXIS_TKEEP :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0); S_AXIS_TLAST :in std_logic; S_AXIS_TID :in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0); S_AXIS_TDEST :in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0); S_AXIS_TUSER :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0); M_AXIS_TVALID :out std_logic; M_AXIS_TREADY :in std_logic; M_AXIS_TDATA :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); M_AXIS_TSTRB :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0); M_AXIS_TKEEP :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0); M_AXIS_TLAST :out std_logic; M_AXIS_TID :out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0); M_AXIS_TDEST :out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0); M_AXIS_TUSER :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0) ); end component; ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal M_AXIS_TREADY_D1 : std_logic := '0'; signal M_AXIS_TLAST_D1 : std_logic := '0'; signal M_AXIS_TVALID_D1 : std_logic := '0'; signal M_AXIS_TVALID_OUT : std_logic := '0'; signal M_AXIS_TLAST_OUT : std_logic := '0'; signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); signal all_lines_xfred : std_logic := '0'; --signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); signal decr_vcount : std_logic := '0'; --signal fifo_pipe_empty : std_logic := '0' --signal stop_reg : std_logic := '0' ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin GEN_DWIDTH_NO_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0 generate begin all_lines_xfred_s_dwidth <= all_lines_xfred; -- Pass out of core M_AXIS_TVALID <= M_AXIS_TVALID_OUT; M_AXIS_TLAST <= M_AXIS_TLAST_OUT; MM2S_AXIS_DWIDTH_CONVERTER_I : axi_vdma_v6_2_axis_dwidth_converter_v1_0_axis_dwidth_converter generic map( C_S_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED , C_M_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_AXIS_TID_WIDTH => C_AXIS_TID_WIDTH , C_S_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 , C_M_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 , C_AXIS_TDEST_WIDTH => C_AXIS_TDEST_WIDTH , --C_AXIS_SIGNAL_SET => C_AXIS_SIGNAL_SET , C_FAMILY => C_FAMILY ) port map( ACLK => ACLK , ARESETN => ARESETN , ACLKEN => ACLKEN , S_AXIS_TVALID => S_AXIS_TVALID , S_AXIS_TREADY => S_AXIS_TREADY , S_AXIS_TDATA => S_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) , S_AXIS_TSTRB => S_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) , S_AXIS_TKEEP => S_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) , S_AXIS_TLAST => S_AXIS_TLAST , S_AXIS_TID => S_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) , S_AXIS_TDEST => S_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) , S_AXIS_TUSER => S_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) , M_AXIS_TVALID => M_AXIS_TVALID_OUT , M_AXIS_TREADY => M_AXIS_TREADY , M_AXIS_TDATA => M_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0) , M_AXIS_TSTRB => M_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) , M_AXIS_TKEEP => M_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) , M_AXIS_TLAST => M_AXIS_TLAST_OUT , M_AXIS_TID => M_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) , M_AXIS_TDEST => M_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) , M_AXIS_TUSER => M_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0) ); -- Register to break long timing paths for use in -- transfer complete generation DWIDTH_REG_STRM_SIGS : process(ACLK) begin if(ACLK'EVENT and ACLK = '1')then if(ARESETN = '0')then M_AXIS_TLAST_D1 <= '0'; M_AXIS_TVALID_D1 <= '0'; M_AXIS_TREADY_D1 <= '0'; else M_AXIS_TLAST_D1 <= M_AXIS_TLAST_OUT; M_AXIS_TVALID_D1 <= M_AXIS_TVALID_OUT; M_AXIS_TREADY_D1 <= M_AXIS_TREADY; end if; end if; end process DWIDTH_REG_STRM_SIGS; --***************************************************************************** --** Vertical Line Tracking --***************************************************************************** -- Decrement vertical count with each accept tlast decr_vcount <= '1' when M_AXIS_TLAST_D1 = '1' and M_AXIS_TVALID_D1 = '1' and M_AXIS_TREADY_D1 = '1' else '0'; -- Drive ready at fsync out then de-assert once all lines have -- been accepted. DWIDTH_VERT_COUNTER : process(ACLK) begin if(ACLK'EVENT and ACLK = '1')then if(ARESETN = '0' and fsync_out = '0')then vsize_counter <= (others => '0'); all_lines_xfred <= '1'; elsif(fsync_out = '1')then vsize_counter <= crnt_vsize_d2; all_lines_xfred <= '0'; elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then vsize_counter <= (others => '0'); all_lines_xfred <= '1'; elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1); all_lines_xfred <= '0'; end if; end if; end process DWIDTH_VERT_COUNTER; dwidth_fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and M_AXIS_TVALID_OUT = '0') -- All data for frame transmitted or dm_halt_reg = '1' -- Commanded to Halt else '0'; end generate GEN_DWIDTH_NO_SOF; GEN_DWIDTH_SOF : if ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1 generate begin -- Pass out of core M_AXIS_TVALID <= M_AXIS_TVALID_OUT; M_AXIS_TLAST <= M_AXIS_TLAST_OUT; all_lines_xfred_s_dwidth <= all_lines_xfred; MM2S_AXIS_DWIDTH_CONVERTER_I : axi_vdma_v6_2_axis_dwidth_converter_v1_0_axis_dwidth_converter generic map( C_S_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED , C_M_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_AXIS_TID_WIDTH => C_AXIS_TID_WIDTH , C_S_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 , C_M_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 , C_AXIS_TDEST_WIDTH => C_AXIS_TDEST_WIDTH , --C_AXIS_SIGNAL_SET => C_AXIS_SIGNAL_SET , C_FAMILY => C_FAMILY ) port map( ACLK => ACLK , ARESETN => ARESETN , ACLKEN => ACLKEN , S_AXIS_TVALID => S_AXIS_TVALID , S_AXIS_TREADY => S_AXIS_TREADY , S_AXIS_TDATA => S_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) , S_AXIS_TSTRB => S_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) , S_AXIS_TKEEP => S_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) , S_AXIS_TLAST => S_AXIS_TLAST , S_AXIS_TID => S_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) , S_AXIS_TDEST => S_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) , S_AXIS_TUSER => S_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) , M_AXIS_TVALID => M_AXIS_TVALID_OUT , M_AXIS_TREADY => M_AXIS_TREADY , M_AXIS_TDATA => M_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0) , M_AXIS_TSTRB => M_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) , M_AXIS_TKEEP => M_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) , M_AXIS_TLAST => M_AXIS_TLAST_OUT , M_AXIS_TID => M_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) , M_AXIS_TDEST => M_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) , M_AXIS_TUSER => M_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0) ); -- Register to break long timing paths for use in -- transfer complete generation DWIDTH_REG_STRM_SIGS : process(ACLK) begin if(ACLK'EVENT and ACLK = '1')then if(ARESETN = '0')then M_AXIS_TLAST_D1 <= '0'; M_AXIS_TVALID_D1 <= '0'; M_AXIS_TREADY_D1 <= '0'; else M_AXIS_TLAST_D1 <= M_AXIS_TLAST_OUT; M_AXIS_TVALID_D1 <= M_AXIS_TVALID_OUT; M_AXIS_TREADY_D1 <= M_AXIS_TREADY; end if; end if; end process DWIDTH_REG_STRM_SIGS; --***************************************************************************** --** Vertical Line Tracking --***************************************************************************** -- Decrement vertical count with each accept tlast decr_vcount <= '1' when M_AXIS_TLAST_D1 = '1' and M_AXIS_TVALID_D1 = '1' and M_AXIS_TREADY_D1 = '1' else '0'; -- Drive ready at fsync out then de-assert once all lines have -- been accepted. DWIDTH_VERT_COUNTER : process(ACLK) begin if(ACLK'EVENT and ACLK = '1')then if((ARESETN = '0' and fsync_out = '0') or mm2s_vsize_cntr_clr_flag = '1')then vsize_counter <= (others => '0'); all_lines_xfred <= '1'; elsif(fsync_out = '1')then vsize_counter <= crnt_vsize_d2; all_lines_xfred <= '0'; elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then vsize_counter <= (others => '0'); all_lines_xfred <= '1'; elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1); all_lines_xfred <= '0'; end if; end if; end process DWIDTH_VERT_COUNTER; dwidth_fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and M_AXIS_TVALID_OUT = '0') -- All data for frame transmitted or dm_halt_reg = '1' -- Commanded to Halt else '0'; end generate GEN_DWIDTH_SOF; end implementation;
gpl-2.0
straywarrior/MadeCPUin21days
CPU_TEST.vhd
1
6386
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:37:46 11/22/2015 -- Design Name: -- Module Name: Z:/Downloads/VMware Shared Files/ComputerOrganization/MadeCPUin21days/CPU_TEST.vhd -- Project Name: MadeCPUin21days -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: CPU_TOP -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY CPU_TEST IS END CPU_TEST; ARCHITECTURE behavior OF CPU_TEST IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT CPU_TOP PORT( clock : IN std_logic; reset : IN std_logic; RAM1ADDR : OUT std_logic_vector(17 downto 0); RAM1DATA : INOUT std_logic_vector(15 downto 0); RAM1EN : OUT std_logic; RAM1OE : OUT std_logic; RAM1RW : OUT std_logic; RAM2ADDR : OUT std_logic_vector(17 downto 0); RAM2DATA : INOUT std_logic_vector(15 downto 0); RAM2EN : OUT std_logic; RAM2OE : OUT std_logic; RAM2RW : OUT std_logic; SERIAL_DATA_READY : IN std_logic; SERIAL_RDN : OUT std_logic; SERIAL_TBRE : IN std_logic; SERIAL_TSRE : IN std_logic; SERIAL_WRN : OUT std_logic; SW : IN std_logic_vector (15 downto 0); LED : OUT std_logic_vector(15 downto 0); DLED_RIGHT : out STD_LOGIC_VECTOR (6 downto 0) ); END COMPONENT; --Inputs signal clock : std_logic := '0'; signal reset : std_logic := '0'; signal SERIAL_DATA_READY : std_logic := '0'; signal SERIAL_TBRE : std_logic := '1'; signal SERIAL_TSRE : std_logic := '1'; --BiDirs signal RAM1DATA : std_logic_vector(15 downto 0); signal RAM2DATA : std_logic_vector(15 downto 0); --Outputs signal RAM1ADDR : std_logic_vector(17 downto 0); signal RAM1EN : std_logic; signal RAM1OE : std_logic; signal RAM1RW : std_logic; signal RAM2ADDR : std_logic_vector(17 downto 0); signal RAM2EN : std_logic; signal RAM2OE : std_logic; signal RAM2RW : std_logic; signal SERIAL_RDN : std_logic; signal SERIAL_WRN : std_logic; signal LED : std_logic_vector(15 downto 0); signal SW : std_logic_vector (15 downto 0); signal DLED_RIGHT : std_logic_vector (6 downto 0); -- Clock period definitions constant clock_period : time := 20 ns; constant clock_2t_period : time := 40 ns; constant clock_4t_period : time := 80 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: CPU_TOP PORT MAP ( clock => clock, reset => reset, RAM1ADDR => RAM1ADDR, RAM1DATA => RAM1DATA, RAM1EN => RAM1EN, RAM1OE => RAM1OE, RAM1RW => RAM1RW, RAM2ADDR => RAM2ADDR, RAM2DATA => RAM2DATA, RAM2EN => RAM2EN, RAM2OE => RAM2OE, RAM2RW => RAM2RW, SERIAL_DATA_READY => SERIAL_DATA_READY, SERIAL_RDN => SERIAL_RDN, SERIAL_TBRE => SERIAL_TBRE, SERIAL_TSRE => SERIAL_TSRE, SERIAL_WRN => SERIAL_WRN, SW => SW, LED => LED, DLED_RIGHT => DLED_RIGHT ); -- Clock process definitions clock_process :process begin clock <= '0'; wait for clock_period/2; clock <= '1'; wait for clock_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state. reset <= '0'; sw <= "0000000001000111"; wait for 10 ns; reset <= '1'; -- NOP RAM2DATA <= "0000100000000000"; wait for clock_4t_period; RAM2DATA <= x"0800"; wait for clock_4t_period; RAM2DATA <= x"0800"; wait for clock_4t_period; RAM2DATA <= x"6D40"; wait for clock_4t_period; RAM2DATA <= x"35A0"; wait for clock_4t_period; RAM2DATA <= x"6880"; wait for clock_4t_period; RAM2DATA <= x"3000"; wait for clock_4t_period; RAM2DATA <= x"DD00"; wait for clock_4t_period; RAM2DATA <= x"68EF"; wait for clock_4t_period; RAM2DATA <= (others => 'Z'); wait for clock_4t_period; RAM2DATA <= x"3000"; wait for clock_4t_period; RAM2DATA <= x"DD01"; wait for clock_4t_period; RAM2DATA <= x"0800"; wait for clock_4t_period; RAM2DATA <= x"0800"; wait for clock_4t_period; -- NOP RAM2DATA <= "0000100000000000"; wait for clock_4t_period; -- B 0x31 RAM2DATA <= "0001000001100001"; wait for clock_4t_period; -- R0 <= x"FF" RAM2DATA <= "0110100011111111"; wait for clock_4t_period; -- SW R0 R1 1 RAM2DATA <= "1101100000100001"; wait for clock_4t_period; -- SLL R0 R0 RAM2DATA <= "0011000000000000"; wait for clock_4t_period; -- R1 <= x"0F" RAM2DATA <= "0110100000001111"; wait for clock_4t_period; -- NOP RAM2DATA <= "0000100000000000"; wait for clock_4t_period; -- SW R0 R1 1 RAM2DATA <= "1101100000100001"; wait for clock_4t_period; -- SLL R0 R0 RAM2DATA <= "0011000000000000"; -- ADDU R0 R1 R2 RAM2DATA <= "1110000000101001"; wait for clock_4t_period; -- NOP RAM2DATA <= "0000100000000000"; wait for clock_4t_period; -- SW R0 R1 0 RAM2DATA <= "1101100000100000"; wait for clock_4t_period; -- insert stimulus here wait; end process; END;
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_addr_cntl.vhd
6
41576
---------------------------------------------------------------------------- -- axi_datamover_addr_cntl.vhd ---------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_addr_cntl.vhd -- -- Description: -- This file implements the axi_datamover Master Address Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; Use axi_datamover_v5_1.axi_datamover_fifo; ------------------------------------------------------------------------------- entity axi_datamover_addr_cntl is generic ( C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4; -- sets the depth of the Command Queue FIFO C_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Sets the address bus width C_ADDR_ID : Integer range 0 to 255 := 0; -- Sets the value to be on the AxID output C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the AxID output C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Command Tag field width C_FAMILY : String := "virtex7" -- Specifies the target FPGA family ); port ( -- Clock input --------------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------ -- AXI Address Channel I/O -------------------------------------------- addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- addr2axi_alen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- addr2axi_asize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- addr2axi_aburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- addr2axi_acache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel BURST output -- -- addr2axi_auser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel BURST output -- -- addr2axi_aprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- addr2axi_avalid : out std_logic; -- -- AXI Address Channel VALID output -- -- axi2addr_aready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------ -- Currently unsupported AXI Address Channel output signals ------- -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- Command Calculation Interface ----------------------------------------- mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- The next command address to put on the AXI MMap ADDR -- -- mstr2addr_len : In std_logic_vector(7 downto 0); -- -- The next command length to put on the AXI MMap LEN -- -- Sized to support 256 data beat bursts -- -- mstr2addr_size : In std_logic_vector(2 downto 0); -- -- The next command size to put on the AXI MMap SIZE -- -- mstr2addr_burst : In std_logic_vector(1 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cache : In std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_user : In std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cmd_cmplt : In std_logic; -- -- The indication to the Address Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2addr_calc_error : In std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2addr_cmd_valid : in std_logic; -- -- The next command valid indication to the Address Channel -- -- Controller for the AXI MMap -- -- addr2mstr_cmd_ready : out std_logic; -- -- Indication to the Command Calculator that the -- -- command is being accepted -- -------------------------------------------------------------------------- -- Halted Indication to Reset Module ------------------------------ addr2rst_stop_cmplt : out std_logic; -- -- Output flag indicating the address controller has stopped -- -- posting commands to the Address Channel due to a stop -- -- request vai the data2addr_stop_req input port -- ------------------------------------------------------------------ -- Address Generation Control --------------------------------------- allow_addr_req : in std_logic; -- -- Input used to enable/stall the posting of address requests. -- -- 0 = stall address request generation. -- -- 1 = Enable Address request geneartion -- -- addr_req_posted : out std_logic; -- -- Indication from the Address Channel Controller to external -- -- User logic that an address has been posted to the -- -- AXI Address Channel. -- --------------------------------------------------------------------- -- Data Channel Interface --------------------------------------------- addr2data_addr_posted : Out std_logic; -- -- Indication from the Address Channel Controller to the -- -- Data Controller that an address has been posted to the -- -- AXI Address Channel. -- -- data2addr_data_rdy : In std_logic; -- -- Indication that the Data Channel is ready to send the first -- -- databeat of the next command on the write data channel. -- -- This is used for the "wait for data" feature which keeps the -- -- address controller from issuing a transfer requset until the -- -- corresponding data is ready. This is expected to be held in -- -- the asserted state until the addr2data_addr_posted signal is -- -- asserted. -- -- data2addr_stop_req : In std_logic; -- -- Indication that the Data Channel has encountered an error -- -- or a soft shutdown request and needs the Address Controller -- -- to stop posting commands to the AXI Address channel -- ----------------------------------------------------------------------- -- Status Module Interface --------------------------------------- addr2stat_calc_error : out std_logic; -- -- Indication to the Status Module that the Addr Cntl FIFO -- -- is loaded with a Calc error -- -- addr2stat_cmd_fifo_empty : out std_logic -- -- Indication to the Status Module that the Addr Cntl FIFO -- -- is empty -- ------------------------------------------------------------------ ); end entity axi_datamover_addr_cntl; architecture implementation of axi_datamover_addr_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Constant Declarations -------------------------------------------- Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0'); --'0' & -- bit 2, Normal Access --'0' & -- bit 1, Nonsecure Access --'0'; -- bit 0, Data Access Constant LEN_WIDTH : integer := 8; Constant SIZE_WIDTH : integer := 3; Constant BURST_WIDTH : integer := 2; Constant CMD_CMPLT_WIDTH : integer := 1; Constant CALC_ERROR_WIDTH : integer := 1; Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width C_ADDR_WIDTH + -- Cmd Address field width LEN_WIDTH + -- Cmd Len field width SIZE_WIDTH + -- Cmd Size field width BURST_WIDTH + -- Cmd Burst field width CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width CALC_ERROR_WIDTH + -- Cmd Calc Error flag 8; -- Cmd Cache, user fields Constant USE_SYNC_FIFO : integer := 0; Constant REG_FIFO_PRIM : integer := 0; Constant BRAM_FIFO_PRIM : integer := 1; Constant SRL_FIFO_PRIM : integer := 2; Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM; -- Signal Declarations -------------------------------------------- signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0'); signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0'); signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0'); signal sig_axi_avalid : std_logic := '0'; signal sig_axi_aready : std_logic := '0'; signal sig_addr_posted : std_logic := '0'; signal sig_calc_error : std_logic := '0'; signal sig_cmd_fifo_empty : std_logic := '0'; Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0'); Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_fifo_next_cmd_cmplt : std_logic := '0'; signal sig_fifo_calc_error : std_logic := '0'; signal sig_fifo_wr_cmd_valid : std_logic := '0'; signal sig_fifo_wr_cmd_ready : std_logic := '0'; signal sig_fifo_rd_cmd_valid : std_logic := '0'; signal sig_fifo_rd_cmd_ready : std_logic := '0'; signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0'); signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0'); signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0'); signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0'); signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0'); signal sig_next_cmd_cmplt_reg : std_logic := '0'; signal sig_addr_valid_reg : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_pop_addr_reg : std_logic := '0'; signal sig_push_addr_reg : std_logic := '0'; signal sig_addr_reg_empty : std_logic := '0'; signal sig_addr_reg_full : std_logic := '0'; signal sig_posted_to_axi : std_logic := '0'; -- obsoleted signal sig_set_wfd_flop : std_logic := '0'; -- obsoleted signal sig_clr_wfd_flop : std_logic := '0'; -- obsoleted signal sig_wait_for_data : std_logic := '0'; -- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0'; signal sig_allow_addr_req : std_logic := '0'; signal sig_posted_to_axi_2 : std_logic := '0'; signal new_cmd_in : std_logic; signal first_addr_valid : std_logic; signal first_addr_valid_del : std_logic; signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0); signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0); signal addr2axi_cache_int : std_logic_vector (7 downto 0); signal addr2axi_cache_int1 : std_logic_vector (7 downto 0); signal last_one : std_logic; signal latch : std_logic; signal first_one : std_logic; signal latch_n : std_logic; signal latch_n_del : std_logic; signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0); -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no"; begin --(architecture implementation) -- AXI I/O Port assignments addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH)); addr2axi_aaddr <= sig_axi_addr ; addr2axi_alen <= sig_axi_alen ; addr2axi_asize <= sig_axi_asize ; addr2axi_aburst <= sig_axi_aburst; addr2axi_acache <= sig_axi_acache; addr2axi_auser <= sig_axi_auser; addr2axi_aprot <= APROT_VALUE ; addr2axi_avalid <= sig_axi_avalid; sig_axi_aready <= axi2addr_aready; -- Command Calculator Handshake output sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ; addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; -- Data Channel Controller synchro pulse output addr2data_addr_posted <= sig_addr_posted; -- Status Module Interface outputs addr2stat_calc_error <= sig_calc_error ; addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and sig_cmd_fifo_empty; -- Flag Indicating the Address Controller has completed a Stop addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case sig_addr_reg_empty) or (data2addr_stop_req and -- shutdown after error trap sig_calc_error); -- Assign the address posting control and status sig_allow_addr_req <= allow_addr_req ; addr_req_posted <= sig_posted_to_axi_2 ; -- Internal logic ------------------------------ ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_FIFO -- -- If Generate Description: -- Implements the case where the cmd qualifier depth is -- greater than 1. -- ------------------------------------------------------------ GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate begin -- Format the input FIFO data word sig_aq_fifo_data_in <= mstr2addr_cache & mstr2addr_user & mstr2addr_calc_error & mstr2addr_cmd_cmplt & mstr2addr_burst & mstr2addr_size & mstr2addr_len & mstr2addr_addr & mstr2addr_tag ; -- Rip fields from FIFO output data word sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH + 7) downto (C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH + 4) ); sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH + 3) downto (C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH) ); sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH)-1); sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH)-1); sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH)-1 downto C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH) ; sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH)-1 downto C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH) ; sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH)-1 downto C_ADDR_WIDTH + C_TAG_WIDTH) ; sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH)-1 downto C_TAG_WIDTH) ; sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_ADDR_QUAL_FIFO -- -- Description: -- Instance for the Address/Qualifier FIFO -- ------------------------------------------------------------ I_ADDR_QUAL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => ADDR_QUAL_WIDTH , C_DEPTH => C_ADDR_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_fifo_wr_cmd_valid , fifo_wr_tready => sig_fifo_wr_cmd_ready , fifo_wr_tdata => sig_aq_fifo_data_in , fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_fifo_rd_cmd_valid , fifo_rd_tready => sig_fifo_rd_cmd_ready , fifo_rd_tdata => sig_aq_fifo_data_out , fifo_rd_empty => sig_cmd_fifo_empty ); end generate GEN_ADDR_FIFO; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_ADDR_FIFO -- -- If Generate Description: -- Implements the case where no additional FIFOing is needed -- on the input command address/qualifiers. -- ------------------------------------------------------------ GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate begin -- Bypass FIFO sig_fifo_next_tag <= mstr2addr_tag ; sig_fifo_next_addr <= mstr2addr_addr ; sig_fifo_next_len <= mstr2addr_len ; sig_fifo_next_size <= mstr2addr_size ; sig_fifo_next_burst <= mstr2addr_burst ; sig_fifo_next_cache <= mstr2addr_cache ; sig_fifo_next_user <= mstr2addr_user ; sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ; sig_fifo_calc_error <= mstr2addr_calc_error ; sig_cmd_fifo_empty <= sig_addr_reg_empty ; sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ; sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ; end generate GEN_NO_ADDR_FIFO; -- Output Register Logic ------------------------------------------- sig_axi_addr <= sig_next_addr_reg ; sig_axi_alen <= sig_next_len_reg ; sig_axi_asize <= sig_next_size_reg ; sig_axi_aburst <= sig_next_burst_reg ; sig_axi_acache <= sig_next_cache_reg ; sig_axi_auser <= sig_next_user_reg ; sig_axi_avalid <= sig_addr_valid_reg ; sig_calc_error <= sig_calc_error_reg ; sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and sig_allow_addr_req and -- obsoleted not(sig_wait_for_data) and not(data2addr_stop_req); sig_addr_posted <= sig_posted_to_axi ; -- Internal signals sig_push_addr_reg <= sig_addr_reg_empty and sig_fifo_rd_cmd_valid and sig_allow_addr_req and -- obsoleted not(sig_wait_for_data) and not(data2addr_stop_req); sig_pop_addr_reg <= not(sig_calc_error_reg) and sig_axi_aready and sig_addr_reg_full; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_FIFO_REG -- -- Process Description: -- This process implements a register for the Address -- Control FIFO that operates like a 1 deep Sync FIFO. -- ------------------------------------------------------------- IMP_ADDR_FIFO_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_addr_reg = '1') then sig_next_tag_reg <= (others => '0') ; sig_next_addr_reg <= (others => '0') ; sig_next_len_reg <= (others => '0') ; sig_next_size_reg <= (others => '0') ; sig_next_burst_reg <= (others => '0') ; sig_next_cache_reg <= (others => '0') ; sig_next_user_reg <= (others => '0') ; sig_next_cmd_cmplt_reg <= '0' ; sig_addr_valid_reg <= '0' ; sig_calc_error_reg <= '0' ; sig_addr_reg_empty <= '1' ; sig_addr_reg_full <= '0' ; elsif (sig_push_addr_reg = '1') then sig_next_tag_reg <= sig_fifo_next_tag ; sig_next_addr_reg <= sig_fifo_next_addr ; sig_next_len_reg <= sig_fifo_next_len ; sig_next_size_reg <= sig_fifo_next_size ; sig_next_burst_reg <= sig_fifo_next_burst ; sig_next_cache_reg <= sig_fifo_next_cache ; sig_next_user_reg <= sig_fifo_next_user ; sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ; sig_addr_valid_reg <= not(sig_fifo_calc_error); sig_calc_error_reg <= sig_fifo_calc_error ; sig_addr_reg_empty <= '0' ; sig_addr_reg_full <= '1' ; else null; -- don't change state end if; end if; end process IMP_ADDR_FIFO_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_POSTED_FLAG -- -- Process Description: -- This implements a FLOP that creates a 1 clock wide pulse -- indicating a new address/qualifier set has been posted to -- the AXI Addres Channel outputs. This is used to synchronize -- the Data Channel Controller. -- ------------------------------------------------------------- IMP_POSTED_FLAG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_posted_to_axi <= '0'; sig_posted_to_axi_2 <= '0'; elsif (sig_push_addr_reg = '1') then sig_posted_to_axi <= '1'; sig_posted_to_axi_2 <= '1'; else sig_posted_to_axi <= '0'; sig_posted_to_axi_2 <= '0'; end if; end if; end process IMP_POSTED_FLAG; -- PROC_CMD_DETECT : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- first_addr_valid_del <= '0'; -- elsif (primary_aclk'event and primary_aclk = '1') then -- first_addr_valid_del <= first_addr_valid; -- end if; -- end process PROC_CMD_DETECT; -- -- PROC_ADDR_DET : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- first_addr_valid <= '0'; -- first_addr_int <= (others => '0'); -- last_addr_int <= (others => '0'); -- elsif (primary_aclk'event and primary_aclk = '1') then -- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then -- first_addr_valid <= '1'; -- first_addr_int <= mstr2addr_addr; -- last_addr_int <= last_addr_int; -- elsif (mstr2addr_cmd_cmplt = '1') then -- first_addr_valid <= '0'; -- first_addr_int <= first_addr_int; -- last_addr_int <= mstr2addr_addr; -- end if; -- end if; -- end process PROC_ADDR_DET; -- -- latch <= first_addr_valid and (not first_addr_valid_del); -- latch_n <= (not first_addr_valid) and first_addr_valid_del; -- -- PROC_CACHE1 : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- mstr2addr_cache_info_int <= (others => '0'); -- latch_n_del <= '0'; -- elsif (primary_aclk'event and primary_aclk = '1') then -- if (latch_n = '1') then -- mstr2addr_cache_info_int <= mstr2addr_cache_info; -- end if; -- latch_n_del <= latch_n; -- end if; -- end process PROC_CACHE1; -- -- -- PROC_CACHE : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- addr2axi_cache_int1 <= (others => '0'); -- first_one <= '0'; -- elsif (primary_aclk'event and primary_aclk = '1') then -- first_one <= '0'; ---- if (latch = '1' and first_one = '0') then -- first one -- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then -- addr2axi_cache_int1 <= mstr2addr_cache_info; ---- first_one <= '1'; ---- elsif (latch_n_del = '1') then ---- addr2axi_cache_int <= mstr2addr_cache_info_int; -- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then -- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4); -- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then -- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4); -- end if; -- end if; -- end process PROC_CACHE; -- -- -- PROC_CACHE2 : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- addr2axi_cache_int <= (others => '0'); -- elsif (primary_aclk'event and primary_aclk = '1') then -- addr2axi_cache_int <= addr2axi_cache_int1; -- end if; -- end process PROC_CACHE2; -- --addr2axi_cache <= addr2axi_cache_int (3 downto 0); --addr2axi_user <= addr2axi_cache_int (7 downto 4); -- end implementation;
gpl-2.0
sukinull/hls_stream
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_sof_gen.vhd
6
10626
------------------------------------------------------------------------------- -- axi_vdma_sofeof_mngr ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_vdma_sof_gen.vhd -- Description: This entity manages SOF detection, EOF detection not used for -- axi_vdma. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_vdma.vhd -- |- axi_vdma_pkg.vhd -- |- axi_vdma_intrpt.vhd -- |- axi_vdma_rst_module.vhd -- | |- axi_vdma_reset.vhd (mm2s) -- | | |- axi_vdma_cdc.vhd -- | |- axi_vdma_reset.vhd (s2mm) -- | | |- axi_vdma_cdc.vhd -- | -- |- axi_vdma_reg_if.vhd -- | |- axi_vdma_lite_if.vhd -- | |- axi_vdma_cdc.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_vdma_sg_cdc.vhd (mm2s) -- |- axi_vdma_vid_cdc.vhd (mm2s) -- |- axi_vdma_fsync_gen.vhd (mm2s) -- |- axi_vdma_sof_gen.vhd (mm2s) -- |- axi_vdma_reg_module.vhd (mm2s) -- | |- axi_vdma_register.vhd (mm2s) -- | |- axi_vdma_regdirect.vhd (mm2s) -- |- axi_vdma_mngr.vhd (mm2s) -- | |- axi_vdma_sg_if.vhd (mm2s) -- | |- axi_vdma_sm.vhd (mm2s) -- | |- axi_vdma_cmdsts_if.vhd (mm2s) -- | |- axi_vdma_vidreg_module.vhd (mm2s) -- | | |- axi_vdma_sgregister.vhd (mm2s) -- | | |- axi_vdma_vregister.vhd (mm2s) -- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s) -- | | |- axi_vdma_blkmem.vhd (mm2s) -- | |- axi_vdma_genlock_mngr.vhd (mm2s) -- | |- axi_vdma_genlock_mux.vhd (mm2s) -- | |- axi_vdma_greycoder.vhd (mm2s) -- |- axi_vdma_mm2s_linebuf.vhd (mm2s) -- | |- axi_vdma_sfifo_autord.vhd (mm2s) -- | |- axi_vdma_afifo_autord.vhd (mm2s) -- | |- axi_vdma_skid_buf.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (mm2s) -- | -- |- axi_vdma_sg_cdc.vhd (s2mm) -- |- axi_vdma_vid_cdc.vhd (s2mm) -- |- axi_vdma_fsync_gen.vhd (s2mm) -- |- axi_vdma_sof_gen.vhd (s2mm) -- |- axi_vdma_reg_module.vhd (s2mm) -- | |- axi_vdma_register.vhd (s2mm) -- | |- axi_vdma_regdirect.vhd (s2mm) -- |- axi_vdma_mngr.vhd (s2mm) -- | |- axi_vdma_sg_if.vhd (s2mm) -- | |- axi_vdma_sm.vhd (s2mm) -- | |- axi_vdma_cmdsts_if.vhd (s2mm) -- | |- axi_vdma_vidreg_module.vhd (s2mm) -- | | |- axi_vdma_sgregister.vhd (s2mm) -- | | |- axi_vdma_vregister.vhd (s2mm) -- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm) -- | | |- axi_vdma_blkmem.vhd (s2mm) -- | |- axi_vdma_genlock_mngr.vhd (s2mm) -- | |- axi_vdma_genlock_mux.vhd (s2mm) -- | |- axi_vdma_greycoder.vhd (s2mm) -- |- axi_vdma_s2mm_linebuf.vhd (s2mm) -- | |- axi_vdma_sfifo_autord.vhd (s2mm) -- | |- axi_vdma_afifo_autord.vhd (s2mm) -- | |- axi_vdma_skid_buf.vhd (s2mm) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL) -- |- axi_sg_v3_00_a.axi_sg.vhd -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; ------------------------------------------------------------------------------- entity axi_vdma_sof_gen is port ( ----------------------------------------------------------------------- -- AXI System Signals ----------------------------------------------------------------------- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- AXI Stream -- axis_tready : in std_logic ; -- axis_tvalid : in std_logic ; -- -- fsync : in std_logic ; -- CR622884 -- Detected SOF -- packet_sof : out std_logic -- ); end axi_vdma_sof_gen; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_vdma_sof_gen is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal s_valid : std_logic := '0'; signal s_valid_d1 : std_logic := '0'; signal packet_sof_i : std_logic := '0'; signal hold_sof : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- Generate Packet EOF and SOF --------------------------------------------------------------------------- packet_sof <= packet_sof_i; -- Generate rising edge pulse on valid to use for -- smaple and hold register REG_FOR_RE : process(scndry_aclk) begin if(scndry_aclk'EVENT and scndry_aclk = '1')then if(scndry_resetn = '0')then s_valid <= '0'; s_valid_d1 <= '0'; else -- CR573962 qualify with tready --s_valid <= axis_tvalid; s_valid <= axis_tvalid and axis_tready; s_valid_d1 <= s_valid; end if; end if; end process REG_FOR_RE; packet_sof_i <= s_valid and not s_valid_d1 and not hold_sof; -- CR622884 -- CR622884 -- Generate only 1 SOF (all that is needed) to prevent lockups -- on CDC module with sof pulses being too close together. SOF_HOLD_REG : process(scndry_aclk) begin if(scndry_aclk'EVENT and scndry_aclk = '1')then if(scndry_resetn = '0' or fsync = '1')then hold_sof <= '0'; elsif(packet_sof_i = '1')then hold_sof <= '1'; end if; end if; end process SOF_HOLD_REG; end implementation;
gpl-2.0
huukit/logicsynth
ex1_tutorial/vhd/tb_lock.vhd
1
5152
------------------------------------------------------------------------------- -- Title : tb_lock -- Project : ------------------------------------------------------------------------------- -- File : tb_lock.vhd -- Author : <alhonena@BUMMALO> -- Company : -- Last update: 2008/06/18 -- Platform : ------------------------------------------------------------------------------- -- Description: Testbench for lock. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2008/06/18 1.0 alhonena Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.lock_pkg.all; entity tb_lock is -- Entity with no ports; clock and reset is generated in the testbench. -- Remember that this kind of clock generation works only in the simulation. end tb_lock; architecture testbench of tb_lock is signal clk, rst_n : std_logic := '0'; constant clock_period_c : time := 20 ns; type intarray is array (0 to 3) of integer range 0 to 9; constant correct_sequence_c : intarray := (4,1,6,9); type state_type is (send1, send2, send3, send4, increment); signal state_r : state_type; signal current_value_r : intarray; component lock port ( clk : IN STD_LOGIC; rst_n : IN STD_LOGIC; keys_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); lock_out : OUT STD_LOGIC); end component; signal simulated_keys_r : std_logic_vector(3 downto 0); signal lock_status : std_logic; begin -- testbench clk <= not clk after clock_period_c; rst_n <= '1' after clock_period_c*2; -- instantiation of the DUV, device under verification. lock_inst: lock port map ( clk => clk, rst_n => rst_n, keys_in => simulated_keys_r, lock_out => lock_status); -- All possible sequences are tried in this FSM. FSM: process (clk, rst_n) begin -- process FSM if rst_n = '0' then -- asynchronous reset (active low) state_r <= send1; current_value_r <= (others => 0); elsif clk'event and clk = '1' then -- rising clock edge case state_r is when send1 => simulated_keys_r <= std_logic_vector(to_unsigned(current_value_r(0),4)); state_r <= send2; when send2 => simulated_keys_r <= std_logic_vector(to_unsigned(current_value_r(1),4)); state_r <= send3; when send3 => simulated_keys_r <= std_logic_vector(to_unsigned(current_value_r(2),4)); state_r <= send4; when send4 => simulated_keys_r <= std_logic_vector(to_unsigned(current_value_r(3),4)); state_r <= increment; when increment => if current_value_r(0) = 9 then current_value_r(0) <= 0; if current_value_r(1) = 9 then current_value_r(1) <= 0; if current_value_r(2) = 9 then current_value_r(2) <= 0; if current_value_r(3) = 9 then -- the last one assert false report "Simulation completed succesfully!" severity failure; else current_value_r(3) <= current_value_r(3) + 1; end if; else current_value_r(2) <= current_value_r(2) + 1; end if; else current_value_r(1) <= current_value_r(1) + 1; end if; else current_value_r(0) <= current_value_r(0) + 1; end if; state_r <= send1; when others => null; end case; end if; end process FSM; -- Process that checks if the door opens with a wrong sequence or if -- the door doesn't open with the correct sequence. check: process (clk, rst_n) begin -- process check if rst_n = '0' then -- asynchronous reset (active low) elsif clk'event and clk = '1' then -- rising clock edge if lock_status = '1' then assert current_value_r = correct_sequence_c report "Lock opens with a wrong sequence!" severity failure; end if; -- The DUV should open the door after the fourth digit was -- sent, that is, when the state_r is 'increment'. if current_value_r = correct_sequence_c and state_r = increment then assert lock_status = '1' report "Lock does not open with the correct sequence!" severity failure; end if; end if; end process check; end testbench;
gpl-2.0
sh-chris110/chris
FPGA/HPS/Qsys/hps_design/hps_design_inst.vhd
1
3271
component hps_design is port ( clk_clk : in std_logic := 'X'; -- clk hps_ddr3_mem_a : out std_logic_vector(14 downto 0); -- mem_a hps_ddr3_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba hps_ddr3_mem_ck : out std_logic; -- mem_ck hps_ddr3_mem_ck_n : out std_logic; -- mem_ck_n hps_ddr3_mem_cke : out std_logic; -- mem_cke hps_ddr3_mem_cs_n : out std_logic; -- mem_cs_n hps_ddr3_mem_ras_n : out std_logic; -- mem_ras_n hps_ddr3_mem_cas_n : out std_logic; -- mem_cas_n hps_ddr3_mem_we_n : out std_logic; -- mem_we_n hps_ddr3_mem_reset_n : out std_logic; -- mem_reset_n hps_ddr3_mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq hps_ddr3_mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs hps_ddr3_mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n hps_ddr3_mem_odt : out std_logic; -- mem_odt hps_ddr3_mem_dm : out std_logic_vector(1 downto 0); -- mem_dm hps_ddr3_oct_rzqin : in std_logic := 'X'; -- oct_rzqin ledr_export : out std_logic -- export ); end component hps_design; u0 : component hps_design port map ( clk_clk => CONNECTED_TO_clk_clk, -- clk.clk hps_ddr3_mem_a => CONNECTED_TO_hps_ddr3_mem_a, -- hps_ddr3.mem_a hps_ddr3_mem_ba => CONNECTED_TO_hps_ddr3_mem_ba, -- .mem_ba hps_ddr3_mem_ck => CONNECTED_TO_hps_ddr3_mem_ck, -- .mem_ck hps_ddr3_mem_ck_n => CONNECTED_TO_hps_ddr3_mem_ck_n, -- .mem_ck_n hps_ddr3_mem_cke => CONNECTED_TO_hps_ddr3_mem_cke, -- .mem_cke hps_ddr3_mem_cs_n => CONNECTED_TO_hps_ddr3_mem_cs_n, -- .mem_cs_n hps_ddr3_mem_ras_n => CONNECTED_TO_hps_ddr3_mem_ras_n, -- .mem_ras_n hps_ddr3_mem_cas_n => CONNECTED_TO_hps_ddr3_mem_cas_n, -- .mem_cas_n hps_ddr3_mem_we_n => CONNECTED_TO_hps_ddr3_mem_we_n, -- .mem_we_n hps_ddr3_mem_reset_n => CONNECTED_TO_hps_ddr3_mem_reset_n, -- .mem_reset_n hps_ddr3_mem_dq => CONNECTED_TO_hps_ddr3_mem_dq, -- .mem_dq hps_ddr3_mem_dqs => CONNECTED_TO_hps_ddr3_mem_dqs, -- .mem_dqs hps_ddr3_mem_dqs_n => CONNECTED_TO_hps_ddr3_mem_dqs_n, -- .mem_dqs_n hps_ddr3_mem_odt => CONNECTED_TO_hps_ddr3_mem_odt, -- .mem_odt hps_ddr3_mem_dm => CONNECTED_TO_hps_ddr3_mem_dm, -- .mem_dm hps_ddr3_oct_rzqin => CONNECTED_TO_hps_ddr3_oct_rzqin, -- .oct_rzqin ledr_export => CONNECTED_TO_ledr_export -- ledr.export );
gpl-2.0
huukit/logicsynth
ex1_tutorial/vhd/lock.vhd
1
2628
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE work.lock_pkg.ALL; ENTITY lock IS PORT ( clk : IN STD_LOGIC; rst_n : IN STD_LOGIC; keys_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); lock_out : OUT STD_LOGIC ); END lock; ARCHITECTURE RTL OF lock IS SIGNAL curr_state_r : state_type; SIGNAL next_state : state_type; SIGNAL reset_counter_r : BOOLEAN; BEGIN -- RTL --------------------------------------------------------------------- -- purpose: State Transitions -- type : combinational -- inputs : curr_state_r -- outputs: lock_out --------------------------------------------------------------------- STTRAN : PROCESS (curr_state_r, keys_in, reset_counter_r) VARIABLE count_v : INTEGER; BEGIN -- PROCESS STTRAN -- Default output lock_out <= '0'; IF (reset_counter_r = TRUE) THEN count_v := 0; ELSE count_v := count_v; END IF; CASE (curr_state_r) IS WHEN init => IF (to_integer(UNSIGNED(keys_in)) = first_c) THEN next_state <= code_1; ELSE next_state <= init; END IF; WHEN code_1 => IF (to_integer(UNSIGNED(keys_in)) = second_c) THEN next_state <= code_2; ELSE next_state <= init; END IF; WHEN code_2 => IF (to_integer(UNSIGNED(keys_in)) = third_c) THEN next_state <= code_3; ELSE next_state <= init; END IF; WHEN code_3 => IF (to_integer(UNSIGNED(keys_in)) = fourth_c) THEN lock_out <= '1'; count_v := count_v + 1; ELSE lock_out <= '0'; END IF; next_state <= init; WHEN OTHERS => next_state <= init; END CASE; END PROCESS STTRAN; --------------------------------------------------------------------- -- purpose: State Registers -- type : sequential -- inputs : clk, rst_n -- outputs: curr_state_r --------------------------------------------------------------------- STREG : PROCESS (clk, rst_n) BEGIN -- PROCESS STREG IF (rst_n = '0') THEN -- asynchronous reset (active low) curr_state_r <= init; reset_counter_r <= TRUE; ELSIF (clk'EVENT AND clk = '1') THEN -- rising clock edge curr_state_r <= next_state; reset_counter_r <= FALSE; END IF; END PROCESS STREG; END RTL;
gpl-2.0
purisc-group/purisc
Compute_Group/Compute_Group_tb.vhd
2
3163
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Compute_Group_tb is end; architecture testing of Compute_Group_tb is component Compute_Group PORT ( ADDRESS_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_W : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0); IO_ENABLE : IN STD_LOGIC; DATA_TO_W : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); W_EN : OUT STD_LOGIC; CLK : IN STD_LOGIC; RESET_n : IN STD_LOGIC; GLOBAL_EN : OUT STD_LOGIC; IDENT_IN : IN STD_LOGIC_VECTOR (1 DOWNTO 0); DATA_OUT_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); STALL_GLOB : IN STD_LOGIC ); end component; signal ADDRESS_A : STD_LOGIC_VECTOR (31 DOWNTO 0); signal ADDRESS_B : STD_LOGIC_VECTOR (31 DOWNTO 0); signal ADDRESS_C : STD_LOGIC_VECTOR (31 DOWNTO 0); signal ADDRESS_0 : STD_LOGIC_VECTOR (31 DOWNTO 0); signal ADDRESS_1 : STD_LOGIC_VECTOR (31 DOWNTO 0); signal ADDRESS_W : STD_LOGIC_VECTOR (31 DOWNTO 0); signal DATA_TO_W : STD_LOGIC_VECTOR (31 DOWNTO 0); signal W_EN : STD_LOGIC; signal CLK : STD_LOGIC := '1'; signal RESET_n : STD_LOGIC := '0'; signal DATA_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0); signal DATA_OUT_B : STD_LOGIC_VECTOR (31 DOWNTO 0); signal DATA_OUT_C : STD_LOGIC_VECTOR (31 DOWNTO 0); signal DATA_OUT_0 : STD_LOGIC_VECTOR (31 DOWNTO 0); signal DATA_OUT_1 : STD_LOGIC_VECTOR (31 DOWNTO 0); signal ADDRESS_IO : STD_LOGIC_VECTOR (31 DOWNTO 0); signal DATA_IO : STD_LOGIC_VECTOR (31 DOWNTO 0); signal IO_ENABLE : STD_LOGIC := '0'; signal GLOBAL_EN : STD_LOGIC; signal IDENT_IN : STD_LOGIC_VECTOR (1 downto 0); signal STALL_GLOB : STD_LOGIC; constant clk_period : time := 20ns; begin uut : Compute_Group PORT MAP ( ADDRESS_A, ADDRESS_B, ADDRESS_C, ADDRESS_0, ADDRESS_1, ADDRESS_W, ADDRESS_IO, DATA_IO, IO_ENABLE, DATA_TO_W, W_EN, CLK, RESET_n, GLOBAL_EN, IDENT_IN, DATA_OUT_A, DATA_OUT_B, DATA_OUT_C, DATA_OUT_0, DATA_OUT_1, STALL_GLOB ); clk_process : process begin CLK <= '1'; wait for clk_period/2; CLK <= '0'; wait for clk_period/2; end process; stim_process : process begin wait for clk_period; IO_ENABLE <= '0'; IDENT_IN <= "00"; STALL_GLOB <= '0'; ADDRESS_IO <= "00000000000000000000000011111111"; DATA_IO <= "00000000000000000000000011111111"; wait for clk_period; RESET_n <= '1'; wait; end process; end;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/mmu_icache.vhd
1
28774
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: mmu_icache -- File: mmu_icache.vhd -- Author: Jiri Gaisler - Gaisler Research -- Modified: Edvin Catovic - Gaisler Research -- Description: This unit implements the instruction cache controller. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.config_types.all; use grlib.config.all; use grlib.stdlib.all; library gaisler; use gaisler.libiu.all; use gaisler.libcache.all; use gaisler.mmuconfig.all; use gaisler.mmuiface.all; use gaisler.leon3.all; entity mmu_icache is generic ( icen : integer range 0 to 1 := 0; irepl : integer range 0 to 3 := 0; isets : integer range 1 to 4 := 1; ilinesize : integer range 4 to 8 := 4; isetsize : integer range 1 to 256 := 1; isetlock : integer range 0 to 1 := 0; lram : integer range 0 to 1 := 0; lramsize : integer range 1 to 512 := 1; lramstart : integer range 0 to 255 := 16#8e#; mmuen : integer range 0 to 1 := 0); port ( rst : in std_ulogic; clk : in std_ulogic; ici : in icache_in_type; ico : out icache_out_type; dci : in dcache_in_type; dco : in dcache_out_type; mcii : out memory_ic_in_type; mcio : in memory_ic_out_type; icrami : out icram_in_type; icramo : in icram_out_type; fpuholdn : in std_ulogic; mmudci : in mmudc_in_type; mmuici : out mmuic_in_type; mmuico : in mmuic_out_type ); end; architecture rtl of mmu_icache is constant M_EN : boolean := (mmuen = 1); constant ILINE_BITS : integer := log2(ilinesize); constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS; constant TAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2; constant OFFSET_HIGH : integer := TAG_LOW - 1; constant OFFSET_LOW : integer := ILINE_BITS + 2; constant LINE_HIGH : integer := OFFSET_LOW - 1; constant LINE_LOW : integer := 2; constant LRR_BIT : integer := TAG_HIGH + 1; constant lline : std_logic_vector((ILINE_BITS -1) downto 0) := (others => '1'); constant fline : std_logic_vector((ILINE_BITS -1) downto 0) := (others => '0'); constant SETBITS : integer := log2x(ISETS); constant ILRUBITS : integer := lru_table(ISETS); constant LRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8); constant LRAM_BITS : integer := log2(lramsize) + 10; constant LRAMCS_EN : boolean := false; subtype lru_type is std_logic_vector(ILRUBITS-1 downto 0); type lru_array is array (0 to 2**IOFFSET_BITS-1) of lru_type; -- lru registers type rdatatype is (itag, idata, memory); -- sources during cache read type lru_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0); type lru_table_type is array (0 to 2**IOFFSET_BITS-1) of lru_table_vector_type; type valid_type is array (0 to ISETS-1) of std_logic_vector(ilinesize - 1 downto 0); subtype lock_type is std_logic_vector(0 to ISETS-1); function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is variable xlru : std_logic_vector(4 downto 0); variable set : std_logic_vector(SETBITS-1 downto 0); variable xset : std_logic_vector(1 downto 0); variable unlocked : integer range 0 to ISETS-1; begin set := (others => '0'); xlru := (others => '0'); xset := (others => '0'); xlru(ILRUBITS-1 downto 0) := lru; if isetlock = 1 then unlocked := ISETS-1; for i in ISETS-1 downto 0 loop if lock(i) = '0' then unlocked := i; end if; end loop; end if; case ISETS is when 2 => if isetlock = 1 then if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if; else xset(0) := xlru(0); end if; when 3 => if isetlock = 1 then xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2); else -- xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2); xset := xlru(2) & (xlru(1) and not xlru(2)); end if; when 4 => if isetlock = 1 then xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2); else -- xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2); xset := xlru(4 downto 3); end if; when others => end case; set := xset(SETBITS-1 downto 0); return(set); end; function lru_calc (lru : lru_type; xset : std_logic_vector) return lru_type is variable new_lru : lru_type; variable xnew_lru: std_logic_vector(4 downto 0); variable xlru : std_logic_vector(4 downto 0); variable vset : std_logic_vector(SETBITS-1 downto 0); variable set: integer; begin vset := xset; set := conv_integer(vset); new_lru := (others => '0'); xnew_lru := (others => '0'); xlru := (others => '0'); xlru(ILRUBITS-1 downto 0) := lru; case ISETS is when 2 => if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if; when 3 => xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set); when 4 => xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set); xnew_lru(SETBITS-1 downto 0) := vset; when others => end case; new_lru := xnew_lru(ILRUBITS-1 downto 0); return(new_lru); end; type istatetype is (idle, trans, streaming, stop); type icache_control_type is record -- all registers req, burst, holdn : std_ulogic; overrun : std_ulogic; underrun : std_ulogic; istate : istatetype; -- FSM vector waddress : std_logic_vector(31 downto 2); -- write address buffer vaddress : std_logic_vector(31 downto 2); -- virtual address buffer valid : valid_type; --std_logic_vector(ilinesize-1 downto 0); -- valid bits hit : std_ulogic; su : std_ulogic; flush : std_ulogic; -- flush in progress flush2 : std_ulogic; -- flush in progress faddr : std_logic_vector(IOFFSET_BITS - 1 downto 0); -- flush address diagrdy : std_ulogic; rndcnt : std_logic_vector(log2x(ISETS)-1 downto 0); -- replace counter lrr : std_ulogic; setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace diagset : std_logic_vector(log2x(ISETS)-1 downto 0); lock : std_ulogic; pflush : std_logic; pflushr : std_logic; pflushaddr : std_logic_vector(VA_I_U downto VA_I_D); pflushtyp : std_logic; cache : std_logic; trans_op : std_logic; end record; type lru_reg_type is record write : std_ulogic; waddr : std_logic_vector(IOFFSET_BITS-1 downto 0); set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to ISETS-1; lru : lru_array; end record; constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; constant RRES : icache_control_type := ( req => '0', burst => '0', holdn => '1', overrun => '0', underrun => '0', istate => idle, waddress => (others => '0'), -- has special handling vaddress => (others => '0'), -- has special handling valid => (others => (others => '0')), hit => '0', su => '0', flush => '0', flush2 => '0', faddr => (others => '0'), diagrdy => '0', rndcnt => (others => '0'), lrr => '0', setrepl => (others => '0'), diagset => (others => '0'), lock => '0', pflush => '0', pflushr => '0', pflushaddr => (others => '0'), pflushtyp => '0', cache => '0', trans_op => '0' ); constant LRES : lru_reg_type := ( write => '0', waddr => (others => '0'), set => (others => '0'), lru => (others => (others => '0')) ); signal r, c : icache_control_type; -- r is registers, c is combinational signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational constant icfg : std_logic_vector(31 downto 0) := cache_cfg(irepl, isets, ilinesize, isetsize, isetlock, 0, lram, lramsize, lramstart, mmuen); begin ictrl : process(rst, r, rl, mcio, ici, dci, dco, icramo, fpuholdn, mmuico, mmudci) variable rdatasel : rdatatype; variable twrite, diagen, dwrite : std_ulogic; variable taddr : std_logic_vector(TAG_HIGH downto LINE_LOW); -- tag address variable wtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- write tag value variable ddatain : std_logic_vector(31 downto 0); variable rdata : cdatatype; variable diagdata : std_logic_vector(31 downto 0); variable vmaskraw : std_logic_vector((ilinesize -1) downto 0); variable vmask : valid_type; variable xaddr_inc : std_logic_vector((ILINE_BITS -1) downto 0); variable lastline, nlastline, nnlastline : std_ulogic; variable enable : std_ulogic; variable error : std_ulogic; variable whit, hit, valid : std_ulogic; variable cacheon : std_ulogic; variable v : icache_control_type; variable branch : std_ulogic; variable eholdn : std_ulogic; variable mds, write : std_ulogic; variable memaddr : std_logic_vector(31 downto 2); variable set : integer range 0 to MAXSETS-1; variable setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace variable ctwrite, cdwrite, validv : std_logic_vector(0 to MAXSETS-1); variable wlrr : std_ulogic; variable vl : lru_reg_type; variable vdiagset, rdiagset : integer range 0 to ISETS-1; variable lock : std_logic_vector(0 to ISETS-1); variable wlock : std_ulogic; variable tag : cdatatype; variable lramacc, ilramwr, lramcs : std_ulogic; variable pftag : std_logic_vector(31 downto 2); variable mmuici_trans_op : std_logic; variable mmuici_su : std_logic; begin -- init local variables v := r; vl := rl; vl.write := '0'; vl.set := r.setrepl; vl.waddr := r.waddress(OFFSET_HIGH downto OFFSET_LOW); mds := '1'; dwrite := '0'; twrite := '0'; diagen := '0'; error := '0'; write := mcio.ready; v.diagrdy := '0'; v.holdn := '1'; if icen /= 0 then cacheon := dco.icdiag.cctrl.ics(0) and not (r.flush ); else cacheon := '0'; end if; enable := '1'; branch := '0'; eholdn := dco.hold and fpuholdn; rdatasel := idata; -- read data from cache as default ddatain := mcio.data; -- load full word from memory wtag(TAG_HIGH downto TAG_LOW) := r.vaddress(TAG_HIGH downto TAG_LOW); wlrr := r.lrr; wlock := r.lock; set := 0; ctwrite := (others => '0'); cdwrite := (others => '0'); vdiagset := 0; rdiagset := 0; lock := (others => '0'); ilramwr := '0'; lramacc := '0'; lramcs := '0'; vdiagset := 0; rdiagset := 0; lock := (others => '0'); pftag := (others => '0'); validv := (others => '0'); v.trans_op := r.trans_op and (not mmuico.grant); mmuici_trans_op := r.trans_op; mmuici_su := ici.su; -- random replacement counter if ISETS > 1 then if conv_integer(r.rndcnt) = (ISETS - 1) then v.rndcnt := (others => '0'); else v.rndcnt := r.rndcnt + 1; end if; end if; -- generate lock bits if isetlock = 1 then for i in 0 to ISETS-1 loop lock(i) := icramo.tag(i)(CTAG_LOCKPOS); end loop; end if; --local ram access if (lram = 1) and (ici.fpc(31 downto 24) = LRAM_START) then lramacc := '1'; end if; -- generate cache hit and valid bits hit := '0'; if irepl = dir then set := conv_integer(ici.fpc(OFFSET_HIGH + SETBITS downto OFFSET_HIGH+1)); if (icramo.tag(set)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW)) and ((icramo.ctx(set) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0') or not M_EN) then hit := not r.flush; end if; validv(set) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW), icramo.tag(set)(ilinesize -1 downto 0)); else for i in ISETS-1 downto 0 loop if (icramo.tag(i)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW)) and ((icramo.ctx(i) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0') or not M_EN) then hit := not r.flush; set := i; end if; validv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW), icramo.tag(i)(ilinesize -1 downto 0)); end loop; end if; if (lramacc = '1') and (ISETS > 1) then set := 1; end if; if ici.fpc(LINE_HIGH downto LINE_LOW) = lline then lastline := '1'; else lastline := '0'; end if; if r.waddress(LINE_HIGH downto LINE_LOW) = lline((ILINE_BITS -1) downto 0) then nlastline := '1'; else nlastline := '0'; end if; if r.waddress(LINE_HIGH downto LINE_LOW+1) = lline((ILINE_BITS -1) downto 1) then nnlastline := '1'; else nnlastline := '0'; end if; valid := validv(set); xaddr_inc := r.waddress(LINE_HIGH downto LINE_LOW) + 1; if mcio.ready = '1' then v.waddress(LINE_HIGH downto LINE_LOW) := xaddr_inc; end if; xaddr_inc := r.vaddress(LINE_HIGH downto LINE_LOW) + 1; if mcio.ready = '1' then v.vaddress(LINE_HIGH downto LINE_LOW) := xaddr_inc; end if; taddr := ici.rpc(TAG_HIGH downto LINE_LOW); -- main state machine case r.istate is when idle => -- main state and cache hit for i in 0 to ISETS-1 loop v.valid(i) := icramo.tag(i)(ilinesize-1 downto 0); end loop; --v.hit := '0'; v.hit := hit; v.su := ici.su; -- if (ici.inull or eholdn) = '0' then if eholdn = '0' then taddr := ici.fpc(TAG_HIGH downto LINE_LOW); else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if; v.burst := dco.icdiag.cctrl.burst and not lastline; if (eholdn and not (ici.inull or lramacc)) = '1' then if not (cacheon and hit and valid) = '1' then v.istate := streaming; v.holdn := '0'; v.overrun := '1'; if M_EN and (mmudci.mmctrl1.e = '1') then v.istate := trans; mmuici_trans_op := '1'; v.trans_op := not mmuico.grant; v.cache := '0'; --v.req := '0'; else v.req := '1'; v.cache := '1'; end if; else if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if; end if; v.waddress := ici.fpc(31 downto 2); v.vaddress := ici.fpc(31 downto 2); end if; if dco.icdiag.enable = '1' then diagen := '1'; end if; ddatain := dci.maddress; if (ISETS > 1) then if (irepl = lru) then vl.set := conv_std_logic_vector(set, SETBITS); vl.waddr := ici.fpc(OFFSET_HIGH downto OFFSET_LOW); end if; v.setrepl := conv_std_logic_vector(set, SETBITS); if (((not hit) and (not r.flush)) = '1') then case irepl is when rnd => if isetlock = 1 then if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt; else v.setrepl := conv_std_logic_vector(ISETS-1, SETBITS); for i in ISETS-1 downto 0 loop if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then v.setrepl := conv_std_logic_vector(i, SETBITS); end if; end loop; end if; else v.setrepl := r.rndcnt; end if; when dir => v.setrepl := ici.fpc(OFFSET_HIGH+SETBITS downto OFFSET_HIGH+1); when lru => v.setrepl := lru_set(rl.lru(conv_integer(ici.fpc(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to ISETS-1)); when lrr => v.setrepl := (others => '0'); if isetlock = 1 then if lock(0) = '1' then v.setrepl(0) := '1'; else v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS); end if; else v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS); end if; if v.setrepl(0) = '0' then v.lrr := not icramo.tag(0)(CTAG_LRRPOS); else v.lrr := icramo.tag(0)(CTAG_LRRPOS); end if; end case; end if; if (isetlock = 1) then if (hit and lock(set)) = '1' then v.lock := '1'; else v.lock := '0'; end if; end if; end if; when trans => if M_EN then v.holdn := '0'; if (mmuico.transdata.finish = '1') then if (mmuico.transdata.accexc) = '1' and ((mmudci.mmctrl1.nf) /= '1' or (r.su) = '1') then -- if su then always do mexc error := '1'; mds := '0'; v.holdn := '0'; v.istate := stop; v.burst := '0'; else v.cache := mmuico.transdata.cache; v.waddress := mmuico.transdata.data(31 downto 2); v.istate := streaming; v.req := '1'; end if; end if; end if; when streaming => -- streaming: update cache and send data to IU rdatasel := memory; taddr(TAG_HIGH downto LINE_LOW) := r.vaddress(TAG_HIGH downto LINE_LOW); branch := (ici.fbranch and r.overrun) or (ici.rbranch and (not r.overrun)); v.underrun := r.underrun or (write and ((ici.inull or not eholdn) and (mcio.ready and not (r.overrun and not r.underrun)))); v.overrun := (r.overrun or (eholdn and not ici.inull)) and not (write or r.underrun); if mcio.ready = '1' then -- mds := not (v.overrun and not r.underrun); mds := not (r.overrun and not r.underrun); -- v.req := r.burst; v.burst := v.req and not (nnlastline and mcio.ready); end if; if mcio.grant = '1' then v.req := dco.icdiag.cctrl.burst and r.burst and (not (nnlastline and mcio.ready)) and (dco.icdiag.cctrl.burst or (not branch)) and not (v.underrun and not cacheon); v.burst := v.req and not (nnlastline and mcio.ready); end if; v.underrun := (v.underrun or branch) and not v.overrun; v.holdn := not (v.overrun or v.underrun); if (mcio.ready = '1') and (r.req = '0') then --(v.burst = '0') then v.underrun := '0'; v.overrun := '0'; v.istate := stop; v.holdn := '0'; end if; when stop => -- return to main taddr := ici.fpc(TAG_HIGH downto LINE_LOW); v.istate := idle; v.flush := r.flush2; when others => v.istate := idle; end case; if mcio.retry = '1' then v.req := '1'; end if; if lram = 1 then if LRAMCS_EN then if taddr(31 downto 24) = LRAM_START then lramcs := '1'; else lramcs := '0'; end if; else lramcs := '1'; end if; end if; -- Generate new valid bits write strobe vmaskraw := decode(r.waddress(LINE_HIGH downto LINE_LOW)); twrite := write; if cacheon = '0' then twrite := '0'; vmask := (others => (others => '0')); elsif (dco.icdiag.cctrl.ics = "01") then twrite := twrite and r.hit; for i in 0 to ISETS-1 loop vmask(i) := icramo.tag(i)(ilinesize-1 downto 0) or vmaskraw; end loop; else for i in 0 to ISETS-1 loop if r.hit = '1' then vmask(i) := r.valid(i) or vmaskraw; else vmask(i) := vmaskraw; end if; end loop; end if; if (mcio.mexc or not mcio.cache) = '1' then twrite := '0'; dwrite := '0'; else dwrite := twrite; end if; if twrite = '1' then v.valid := vmask; v.hit := '1'; if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if; end if; if (ISETS > 1) and (irepl = lru) and (rl.write = '1') then vl.lru(conv_integer(rl.waddr)) := lru_calc(rl.lru(conv_integer(rl.waddr)), rl.set); end if; -- cache write signals if ISETS > 1 then setrepl := r.setrepl; else setrepl := (others => '0'); end if; if twrite = '1' then ctwrite(conv_integer(setrepl)) := '1'; end if; if dwrite = '1' then cdwrite(conv_integer(setrepl)) := '1'; end if; -- diagnostic cache access if diagen = '1' then if (ISETS /= 1) then if (dco.icdiag.ilramen = '1') and (lram = 1) then v.diagset := conv_std_logic_vector(1, SETBITS); else v.diagset := dco.icdiag.addr(SETBITS -1 + TAG_LOW downto TAG_LOW); end if; end if; end if; case ISETS is when 1 => vdiagset := 0; rdiagset := 0; when 3 => if conv_integer(v.diagset) < 3 then vdiagset := conv_integer(v.diagset); end if; if conv_integer(r.diagset) < 3 then rdiagset := conv_integer(r.diagset); end if; when others => vdiagset := conv_integer(v.diagset); rdiagset := conv_integer(r.diagset); end case; diagdata := icramo.data(rdiagset); if diagen = '1' then -- diagnostic or local ram access taddr(TAG_HIGH downto LINE_LOW) := dco.icdiag.addr(TAG_HIGH downto LINE_LOW); wtag(TAG_HIGH downto TAG_LOW) := dci.maddress(TAG_HIGH downto TAG_LOW); wlrr := dci.maddress(CTAG_LRRPOS); wlock := dci.maddress(CTAG_LOCKPOS); if (dco.icdiag.ilramen = '1') and (lram = 1) then ilramwr := not dco.icdiag.read; elsif dco.icdiag.tag = '1' then twrite := not dco.icdiag.read; dwrite := '0'; ctwrite := (others => '0'); cdwrite := (others => '0'); ctwrite(vdiagset) := not dco.icdiag.read; diagdata := icramo.tag(rdiagset); else dwrite := not dco.icdiag.read; twrite := '0'; cdwrite := (others => '0'); cdwrite(vdiagset) := not dco.icdiag.read; ctwrite := (others => '0'); end if; vmask := (others => dci.maddress(ilinesize -1 downto 0)); v.diagrdy := '1'; end if; -- select data to return on read access rdata := icramo.data; case rdatasel is when memory => rdata(0) := mcio.data; set := 0; when others => end case; -- cache flush if ((ici.flush or dco.icdiag.flush) = '1') and (icen /= 0) then v.flush := '1'; v.flush2 := '1'; v.faddr := (others => '0'); v.pflush := dco.icdiag.pflush; wtag := (others => '0'); v.pflushr := '1'; v.pflushaddr := dco.icdiag.pflushaddr; v.pflushtyp := dco.icdiag.pflushtyp; end if; if (r.flush2 = '1') and (icen /= 0) then twrite := '1'; ctwrite := (others => '1'); vmask := (others => (others => '0')); v.faddr := r.faddr + 1; taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr; wlrr := '0'; wlock := '0'; wtag := (others => '0'); v.lrr := '0'; if ((r.faddr(IOFFSET_BITS -1) and not v.faddr(IOFFSET_BITS -1)) ) = '1' then v.flush2 := '0'; end if; -- precise flush, ASI_FLUSH_PAGE & ASI_FLUSH_CTX if M_EN then if r.pflush = '1' then twrite := '0'; ctwrite := (others => '0'); v.pflushr := not r.pflushr; if r.pflushr = '0' then for i in ISETS-1 downto 0 loop pftag(OFFSET_HIGH downto OFFSET_LOW) := r.faddr; pftag(TAG_HIGH downto TAG_LOW) := icramo.tag(i)(TAG_HIGH downto TAG_LOW); --icramo.itramout(i).tag; --if (icramo.itramout(i).ctx = mmudci.mmctrl1.ctx) and -- ((pftag(VA_I_U downto VA_I_D) = r.pflushaddr(VA_I_U downto VA_I_D)) or -- (r.pflushtyp = '1')) then ctwrite(i) := '1'; --end if; end loop; end if; end if; end if; end if; -- reset if (not RESET_ALL) and (rst = '0') then v.istate := idle; v.req := '0'; v.burst := '0'; v.holdn := '1'; v.flush := '0'; v.flush2 := '0'; v.overrun := '0'; v.underrun := '0'; v.rndcnt := (others => '0'); v.lrr := '0'; v.setrepl := (others => '0'); v.diagset := (others => '0'); v.lock := '0'; v.waddress := ici.fpc(31 downto 2); v.vaddress := ici.fpc(31 downto 2); v.trans_op := '0'; end if; if (not RESET_ALL and rst = '0') or (r.flush = '1') then vl.lru := (others => (others => '0')); end if; -- Drive signals c <= v; -- register inputs cl <= vl; -- lru register inputs -- tag ram inputs enable := enable and not dco.icdiag.scanen; for i in 0 to ISETS-1 loop tag(i) := (others => '0'); tag(i)(ilinesize-1 downto 0) := vmask(i); tag(i)(TAG_HIGH downto TAG_LOW) := wtag; tag(i)(CTAG_LRRPOS) := wlrr; tag(i)(CTAG_LOCKPOS) := wlock; end loop; icrami.tag <= tag; icrami.tenable <= enable; icrami.twrite <= ctwrite; icrami.flush <= r.flush2; icrami.ctx <= mmudci.mmctrl1.ctx; -- data ram inputs icrami.denable <= enable; icrami.address <= taddr(19+LINE_LOW downto LINE_LOW); icrami.data <= ddatain; icrami.dwrite <= cdwrite; -- local ram inputs icrami.ldramin.enable <= (dco.icdiag.ilramen or lramcs or lramacc) and not dco.icdiag.scanen; icrami.ldramin.read <= dco.icdiag.ilramen or lramacc; icrami.ldramin.write <= ilramwr; -- memory controller inputs mcii.address(31 downto 2) <= r.waddress(31 downto 2); mcii.address(1 downto 0) <= "00"; mcii.su <= r.su; mcii.burst <= r.burst and r.req; mcii.req <= r.req; mcii.flush <= r.flush; -- mmu <-> icache mmuici.trans_op <= mmuici_trans_op; mmuici.transdata.data <= r.waddress(31 downto 2) & "00"; mmuici.transdata.su <= r.su; mmuici.transdata.isid <= id_icache; mmuici.transdata.read <= '1'; mmuici.transdata.wb_data <= (others => '0'); -- IU data cache inputs ico.data <= rdata; ico.mexc <= mcio.mexc or error; ico.hold <= r.holdn; ico.mds <= mds; ico.flush <= r.flush; ico.diagdata <= diagdata; ico.diagrdy <= r.diagrdy; ico.set <= conv_std_logic_vector(set, 2); ico.cfg <= icfg; ico.cstat <= cstat_none; if r.istate = idle then ico.idle <= '1'; else ico.idle <= '0'; end if; end process; -- Local registers regs1 : process(clk) begin if rising_edge(clk) then r <= c; if RESET_ALL and (rst = '0') then r <= RRES; r.waddress <= ici.fpc(31 downto 2); r.vaddress <= ici.fpc(31 downto 2); end if; end if; end process; regs2 : if (ISETS > 1) and (irepl = lru) generate regs2 : process(clk) begin if rising_edge(clk) then rl <= cl; if RESET_ALL and (rst = '0') then rl <= LRES; end if; end if; end process; end generate; nolru : if (ISETS = 1) or (irepl /= lru) generate rl.write <= '0'; rl.waddr <= (others => '0'); rl.set <= (others => '0'); rl.lru <= (others => (others => '0')); end generate; -- pragma translate_off chk : process begin assert not ((ISETS > 2) and (irepl = lrr)) report "Wrong instruction cache configuration detected: LRR replacement requires 2 sets" severity failure; wait; end process; -- pragma translate_on end ;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/libcache.vhd
1
22736
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: libcache -- File: libcache.vhd -- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research -- Description: Cache-related types and components ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.libiu.all; use gaisler.mmuconfig.all; use gaisler.mmuiface.all; package libcache is constant TAG_HIGH : integer := 31; constant CTAG_LRRPOS : integer := 9; constant CTAG_LOCKPOS : integer := 8; constant MAXSETS : integer := 4; -- 3-way set permutations -- s012 => set 0 - least recently used -- set 2 - most recently used constant s012 : std_logic_vector(2 downto 0) := "000"; constant s021 : std_logic_vector(2 downto 0) := "001"; constant s102 : std_logic_vector(2 downto 0) := "010"; constant s120 : std_logic_vector(2 downto 0) := "011"; constant s201 : std_logic_vector(2 downto 0) := "100"; constant s210 : std_logic_vector(2 downto 0) := "101"; -- 4-way set permutations -- s0123 => set 0 - least recently used -- set 3 - most recently used -- bits assigned so bits 4:3 is LRU and 1:0 is MRU -- middle bit is 0 for 01 02 03 12 13 23, 1 for 10 20 30 21 31 32 constant s0123 : std_logic_vector(4 downto 0) := "00011"; constant s0132 : std_logic_vector(4 downto 0) := "00010"; constant s0213 : std_logic_vector(4 downto 0) := "00111"; constant s0231 : std_logic_vector(4 downto 0) := "00001"; constant s0312 : std_logic_vector(4 downto 0) := "00110"; constant s0321 : std_logic_vector(4 downto 0) := "00101"; constant s1023 : std_logic_vector(4 downto 0) := "01011"; constant s1032 : std_logic_vector(4 downto 0) := "01010"; constant s1203 : std_logic_vector(4 downto 0) := "01111"; constant s1230 : std_logic_vector(4 downto 0) := "01000"; constant s1302 : std_logic_vector(4 downto 0) := "01110"; constant s1320 : std_logic_vector(4 downto 0) := "01100"; constant s2013 : std_logic_vector(4 downto 0) := "10011"; constant s2031 : std_logic_vector(4 downto 0) := "10001"; constant s2103 : std_logic_vector(4 downto 0) := "10111"; constant s2130 : std_logic_vector(4 downto 0) := "10000"; constant s2301 : std_logic_vector(4 downto 0) := "10101"; constant s2310 : std_logic_vector(4 downto 0) := "10100"; constant s3012 : std_logic_vector(4 downto 0) := "11010"; constant s3021 : std_logic_vector(4 downto 0) := "11001"; constant s3102 : std_logic_vector(4 downto 0) := "11110"; constant s3120 : std_logic_vector(4 downto 0) := "11000"; constant s3201 : std_logic_vector(4 downto 0) := "11101"; constant s3210 : std_logic_vector(4 downto 0) := "11100"; type lru_3set_table_vector_type is array(0 to 2) of std_logic_vector(2 downto 0); type lru_3set_table_type is array (0 to 7) of lru_3set_table_vector_type; constant lru_3set_table : lru_3set_table_type := ( (s120, s021, s012), -- s012 (s210, s021, s012), -- s021 (s120, s021, s102), -- s102 (s120, s201, s102), -- s120 (s210, s201, s012), -- s201 (s210, s201, s102), -- s210 (s210, s201, s102), -- dummy (s210, s201, s102) -- dummy ); type lru_4set_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0); type lru_4set_table_type is array(0 to 31) of lru_4set_table_vector_type; constant lru_4set_table : lru_4set_table_type := ( (s2310, s0231, s0312, s0213), -- "00000" (s0231/reset) (s2310, s0231, s0312, s0213), -- "00001" s0231 (s1320, s0321, s0132, s0123), -- "00010" s0132 (s1230, s0231, s0132, s0123), -- "00011" s0123 (s3210, s0321, s0312, s0213), -- "00100" (s0321) (s3210, s0321, s0312, s0213), -- "00101" s0321 (s3120, s0321, s0312, s0123), -- "00110" s0312 (s2130, s0231, s0132, s0213), -- "00111" s0213 (s1230, s2301, s1302, s1203), -- "01000" s1230 (s1230, s2301, s1302, s1203), -- "01001" (s1230) (s1320, s0321, s1032, s1023), -- "01010" s1032 (s1230, s0231, s1032, s1023), -- "01011" s1023 (s1320, s3201, s1302, s1203), -- "01100" s1320 (s1320, s3201, s1302, s1203), -- "01101" (s1320) (s1320, s3021, s1302, s1023), -- "01110" s1302 (s1230, s2031, s1032, s1203), -- "01111" s1203 (s2130, s2301, s1302, s2103), -- "10000" s2130 (s2310, s2031, s0312, s2013), -- "10001" s2031 (s2130, s2031, s0132, s2013), -- "10010" (s2013) (s2130, s2031, s0132, s2013), -- "10011" s2013 (s2310, s2301, s3102, s2103), -- "10100" s2310 (s2310, s2301, s3012, s2013), -- "10101" s2301 (s2130, s2031, s1032, s2103), -- "10110" (s2103) (s2130, s2031, s1032, s2103), -- "10111" s2103 (s3120, s3201, s3102, s1203), -- "11000" s3120 (s3210, s3021, s3012, s0213), -- "11001" s3021 (s3120, s3021, s3012, s0123), -- "11010" s3012 (s3120, s3021, s3012, s0123), -- "11011" (s3012) (s3210, s3201, s3102, s2103), -- "11100" s3210 (s3210, s3201, s3012, s2013), -- "11101" s3201 (s3120, s3021, s3102, s1023), -- "11110" s3102 (s3120, s3021, s3102, s1023) -- "11111" (s3102) ); type lru3_repl_table_single_type is array(0 to 2) of integer range 0 to 2; type lru3_repl_table_type is array(0 to 7) of lru3_repl_table_single_type; constant lru3_repl_table : lru3_repl_table_type := ( (0, 1, 2), -- s012 (0, 2, 2), -- s021 (1, 1, 2), -- s102 (1, 1, 2), -- s120 (2, 2, 2), -- s201 (2, 2, 2), -- s210 (2, 2, 2), -- dummy (2, 2, 2) -- dummy ); type lru4_repl_table_single_type is array(0 to 3) of integer range 0 to 3; type lru4_repl_table_type is array(0 to 31) of lru4_repl_table_single_type; constant lru4_repl_table : lru4_repl_table_type := ( (0, 2, 2, 3), -- (s0231/reset) (0, 2, 2, 3), -- s0231 (0, 1, 3, 3), -- s0132 (0, 1, 2, 3), -- s0123 (0, 3, 3, 3), -- (s0321) (0, 3, 3, 3), -- s0321 (0, 3, 3, 3), -- s0312 (0, 2, 2, 3), -- s0213 (1, 1, 2, 3), -- s1230 (1, 1, 2, 3), -- (s1230) (1, 1, 3, 3), -- s1032 (1, 1, 2, 3), -- s1023 (1, 1, 3, 3), -- s1320 (1, 1, 3, 3), -- (s1320) (1, 1, 3, 3), -- s1302 (1, 1, 2, 3), -- s1203 (2, 2, 2, 3), -- s2130 (2, 2, 2, 3), -- s2031 (2, 2, 2, 3), -- (s2013) (2, 2, 2, 3), -- s2013 (2, 2, 2, 3), -- s2310 (2, 2, 2, 3), -- s2301 (2, 2, 2, 3), -- (s2103) (2, 2, 2, 3), -- s2103 (3, 3, 3, 3), -- s3120 (3, 3, 3, 3), -- s3021 (3, 3, 3, 3), -- s3012 (3, 3, 3, 3), -- (s3012) (3, 3, 3, 3), -- s3210 (3, 3, 3, 3), -- s3201 (3, 3, 3, 3), -- s3102 (3, 3, 3, 3) -- (s3102) ); type ildram_in_type is record enable : std_ulogic; read : std_ulogic; write : std_ulogic; end record; subtype ctxword is std_logic_vector(M_CTX_SZ-1 downto 0); type ctxdatatype is array (0 to 3) of ctxword; type icram_in_type is record address : std_logic_vector(19 downto 0); tag : cdatatype; twrite : std_logic_vector(0 to 3); tenable : std_ulogic; flush : std_ulogic; data : std_logic_vector(31 downto 0); denable : std_ulogic; dwrite : std_logic_vector(0 to 3); ldramin : ildram_in_type; ctx : std_logic_vector(M_CTX_SZ-1 downto 0); end record; type icram_out_type is record tag : cdatatype; data : cdatatype; ctx : ctxdatatype; end record; type ldram_in_type is record address : std_logic_vector(23 downto 2); enable : std_ulogic; read : std_ulogic; write : std_ulogic; end record; type dcram_in_type is record address : std_logic_vector(19 downto 0); tag : cdatatype; --std_logic_vector(31 downto 0); ptag : cdatatype; --std_logic_vector(31 downto 0); twrite : std_logic_vector(0 to 3); tpwrite : std_logic_vector(0 to 3); tenable : std_logic_vector(0 to 3); flush : std_ulogic; data : cdatatype; denable : std_logic_vector(0 to 3); dwrite : std_logic_vector(0 to 3); senable : std_logic_vector(0 to 3); swrite : std_logic_vector(0 to 3); saddress : std_logic_vector(19 downto 0); faddress : std_logic_vector(19 downto 0); ldramin : ldram_in_type; ctx : ctxdatatype; tdiag : std_logic_vector(3 downto 0); ddiag : std_logic_vector(3 downto 0); sdiag : std_logic_vector(3 downto 0); end record; type dcram_out_type is record tag : cdatatype; data : cdatatype; stag : cdatatype; ctx : ctxdatatype; end record; type cram_in_type is record icramin : icram_in_type; dcramin : dcram_in_type; end record; type cram_out_type is record icramo : icram_out_type; dcramo : dcram_out_type; end record; type memory_ic_in_type is record address : std_logic_vector(31 downto 0); -- memory address burst : std_ulogic; -- burst request req : std_ulogic; -- memory cycle request su : std_ulogic; -- supervisor address space flush : std_ulogic; -- flush in progress end record; type memory_ic_out_type is record data : std_logic_vector(31 downto 0); -- memory data ready : std_ulogic; -- cycle ready grant : std_ulogic; -- retry : std_ulogic; -- mexc : std_ulogic; -- memory exception cache : std_ulogic; -- cacheable data scanen : std_ulogic; end record; type memory_dc_in_type is record address : std_logic_vector(31 downto 0); data : std_logic_vector(31 downto 0); asi : std_logic_vector(3 downto 0); -- ASI for load/store size : std_logic_vector(1 downto 0); burst : std_ulogic; read : std_ulogic; req : std_ulogic; lock : std_ulogic; cache : std_ulogic; end record; type memory_dc_out_type is record data : std_logic_vector(31 downto 0); -- memory data ready : std_ulogic; -- cycle ready grant : std_ulogic; retry : std_ulogic; mexc : std_ulogic; -- memory exception werr : std_ulogic; -- memory write error cache : std_ulogic; -- cacheable data ba : std_ulogic; -- bus active (used for snooping) bg : std_ulogic; -- bus grant (used for snooping) scanen : std_ulogic; testen : std_ulogic; end record; constant dir : integer := 3; constant rnd : integer := 2; constant lrr : integer := 1; constant lru : integer := 0; type cache_replalgbits_type is array (0 to 3) of integer; constant creplalg_tbl : cache_replalgbits_type := (0, 1, 0, 0); type lru_bits_type is array(1 to 4) of integer; constant lru_table : lru_bits_type := (1,1,3,5); component cachemem generic ( tech : integer range 0 to NTECH := 0; icen : integer range 0 to 1 := 0; irepl : integer range 0 to 3 := 0; isets : integer range 1 to 4 := 1; ilinesize : integer range 4 to 8 := 4; isetsize : integer range 1 to 256 := 1; isetlock : integer range 0 to 1 := 0; dcen : integer range 0 to 1 := 0; drepl : integer range 0 to 3 := 0; dsets : integer range 1 to 4 := 1; dlinesize : integer range 4 to 8 := 4; dsetsize : integer range 1 to 256 := 1; dsetlock : integer range 0 to 1 := 0; dsnoop : integer range 0 to 6 := 0; ilram : integer range 0 to 1 := 0; ilramsize : integer range 1 to 512 := 1; dlram : integer range 0 to 1 := 0; dlramsize : integer range 1 to 512 := 1; mmuen : integer range 0 to 1 := 0; testen : integer range 0 to 3 := 0 ); port ( clk : in std_ulogic; crami : in cram_in_type; cramo : out cram_out_type; sclk : in std_ulogic ); end component; -- mmu versions component mmu_acache generic ( hindex : integer range 0 to NAHBMST-1 := 0; ilinesize : integer range 4 to 8 := 4; cached : integer := 0; clk2x : integer := 0; scantest : integer := 0 ); port ( rst : in std_logic; clk : in std_logic; mcii : in memory_ic_in_type; mcio : out memory_ic_out_type; mcdi : in memory_dc_in_type; mcdo : out memory_dc_out_type; mcmmi : in memory_mm_in_type; mcmmo : out memory_mm_out_type; ahbi : in ahb_mst_in_type; ahbo : out ahb_mst_out_type; ahbso : in ahb_slv_out_vector; hclken : in std_ulogic ); end component; component mmu_icache generic ( icen : integer range 0 to 1 := 0; irepl : integer range 0 to 3 := 0; isets : integer range 1 to 4 := 1; ilinesize : integer range 4 to 8 := 4; isetsize : integer range 1 to 256 := 1; isetlock : integer range 0 to 1 := 0; lram : integer range 0 to 1 := 0; lramsize : integer range 1 to 512 := 1; lramstart : integer range 0 to 255 := 16#8e#; mmuen : integer := 0 ); port ( rst : in std_logic; clk : in std_logic; ici : in icache_in_type; ico : out icache_out_type; dci : in dcache_in_type; dco : in dcache_out_type; mcii : out memory_ic_in_type; mcio : in memory_ic_out_type; icrami : out icram_in_type; icramo : in icram_out_type; fpuholdn : in std_logic; mmudci : in mmudc_in_type; mmuici : out mmuic_in_type; mmuico : in mmuic_out_type ); end component; component mmu_dcache generic ( dsu : integer range 0 to 1 := 0; dcen : integer range 0 to 1 := 0; drepl : integer range 0 to 3 := 0; dsets : integer range 1 to 4 := 1; dlinesize : integer range 4 to 8 := 4; dsetsize : integer range 1 to 256 := 1; dsetlock : integer range 0 to 1 := 0; dsnoop : integer range 0 to 6 := 0; dlram : integer range 0 to 1 := 0; dlramsize : integer range 1 to 512 := 1; dlramstart : integer range 0 to 255 := 16#8f#; ilram : integer range 0 to 1 := 0; ilramstart : integer range 0 to 255 := 16#8e#; itlbnum : integer range 2 to 64 := 8; dtlbnum : integer range 2 to 64 := 8; tlb_type : integer range 0 to 3 := 1; memtech : integer range 0 to NTECH := 0; cached : integer := 0; mmupgsz : integer range 0 to 5 := 0; smp : integer := 0; mmuen : integer := 0 ); port ( rst : in std_logic; clk : in std_logic; dci : in dcache_in_type; dco : out dcache_out_type; ico : in icache_out_type; mcdi : out memory_dc_in_type; mcdo : in memory_dc_out_type; ahbsi : in ahb_slv_in_type; dcrami : out dcram_in_type; dcramo : in dcram_out_type; fpuholdn : in std_logic; mmudci : out mmudc_in_type; mmudco : in mmudc_out_type; sclk : in std_ulogic; ahbso : in ahb_slv_out_vector ); end component; component mmu_cache generic ( hindex : integer := 0; memtech : integer range 0 to NTECH := 0; dsu : integer range 0 to 1 := 0; icen : integer range 0 to 1 := 0; irepl : integer range 0 to 3 := 0; isets : integer range 1 to 4 := 1; ilinesize : integer range 4 to 8 := 4; isetsize : integer range 1 to 256 := 1; isetlock : integer range 0 to 1 := 0; dcen : integer range 0 to 1 := 0; drepl : integer range 0 to 3 := 0; dsets : integer range 1 to 4 := 1; dlinesize : integer range 4 to 8 := 4; dsetsize : integer range 1 to 256 := 1; dsetlock : integer range 0 to 1 := 0; dsnoop : integer range 0 to 6 := 0; ilram : integer range 0 to 1 := 0; ilramsize : integer range 1 to 512 := 1; ilramstart : integer range 0 to 255 := 16#8e#; dlram : integer range 0 to 1 := 0; dlramsize : integer range 1 to 512 := 1; dlramstart : integer range 0 to 255 := 16#8f#; itlbnum : integer range 2 to 64 := 8; dtlbnum : integer range 2 to 64 := 8; tlb_type : integer range 0 to 3 := 1; tlb_rep : integer range 0 to 1 := 0; cached : integer := 0; clk2x : integer := 0; scantest : integer := 0; mmupgsz : integer range 0 to 5 := 0; smp : integer := 0; mmuen : integer range 0 to 1 := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; ici : in icache_in_type; ico : out icache_out_type; dci : in dcache_in_type; dco : out dcache_out_type; ahbi : in ahb_mst_in_type; ahbo : out ahb_mst_out_type; ahbsi : in ahb_slv_in_type; ahbso : in ahb_slv_out_vector; crami : out cram_in_type; cramo : in cram_out_type; fpuholdn : in std_ulogic; hclk, sclk : in std_ulogic; hclken : in std_ulogic ); end component; component clk2xqual port ( rst : in std_ulogic; clk : in std_ulogic; clk2 : in std_ulogic; clken : out std_ulogic); end component; component clk2xsync generic ( hindex : integer := 0; clk2x : integer := 1); port ( rst : in std_ulogic; hclk : in std_ulogic; clk : in std_ulogic; ahbi : in ahb_mst_in_type; ahbi2 : out ahb_mst_in_type; ahbo : in ahb_mst_out_type; ahbo2 : out ahb_mst_out_type; ahbsi : in ahb_slv_in_type; ahbsi2 : out ahb_slv_in_type; mcii : in memory_ic_in_type; mcdi : in memory_dc_in_type; mcdo : in memory_dc_out_type; mmreq : in std_ulogic; mmgrant : in std_ulogic; hclken : in std_ulogic ); end component; function cache_cfg(repl, sets, linesize, setsize, lock, snoop, lram, lramsize, lramstart, mmuen : integer) return std_logic_vector; end; package body libcache is function cache_cfg(repl, sets, linesize, setsize, lock, snoop, lram, lramsize, lramstart, mmuen : integer) return std_logic_vector is variable cfg : std_logic_vector(31 downto 0); begin cfg := (others => '0'); cfg(31 downto 31) := conv_std_logic_vector(lock, 1); cfg(30 downto 28) := conv_std_logic_vector(repl+1, 3); if snoop /= 0 then cfg(27) := '1'; end if; cfg(26 downto 24) := conv_std_logic_vector(sets-1, 3); cfg(23 downto 20) := conv_std_logic_vector(log2(setsize), 4); cfg(19 downto 19) := conv_std_logic_vector(lram, 1); cfg(18 downto 16) := conv_std_logic_vector(log2(linesize), 3); cfg(15 downto 12) := conv_std_logic_vector(log2(lramsize), 4); cfg(11 downto 4) := conv_std_logic_vector(lramstart, 8); cfg(3 downto 3) := conv_std_logic_vector(mmuen, 1); return(cfg); end; end;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/lib/techmap/stratixiii/alt/adqsin.vhd
6
1455
library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library stratixiii; use stratixiii.all; entity adqsin is port( dqs_pad : in std_logic; -- DQS pad dqsn_pad : in std_logic; -- DQSN pad dqs : out std_logic ); end; architecture rtl of adqsin is component stratixiii_io_ibuf IS generic ( differential_mode : string := "false"; bus_hold : string := "false"; simulate_z_as : string := "z"; lpm_type : string := "stratixiii_io_ibuf" ); port ( i : in std_logic := '0'; ibar : in std_logic := '0'; o : out std_logic ); end component; signal vcc : std_logic; signal gnd : std_logic_vector(13 downto 0); signal dqs_buf : std_logic; begin vcc <= '1'; gnd <= (others => '0'); -- In buffer (DQS, DQSN) ------------------------------------------------------------ dqs_buf0 : stratixiii_io_ibuf generic map( differential_mode => "true", bus_hold => "false", simulate_z_as => "z", lpm_type => "stratixiii_io_ibuf" ) port map( i => dqs_pad, ibar => dqsn_pad, o => dqs_buf ); dqs <= dqs_buf; end;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/lib/tech/ec/orca/orcacomp.vhd
5
74888
-- -------------------------------------------------------------------- -- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -- -------------------------------------------------------------------- -- Copyright (c) 2005 by Lattice Semiconductor Corporation -- -------------------------------------------------------------------- -- -- -- Lattice Semiconductor Corporation -- 5555 NE Moore Court -- Hillsboro, OR 97214 -- U.S.A. -- -- TEL: 1-800-Lattice (USA and Canada) -- 1-408-826-6000 (other locations) -- -- web: http://www.latticesemi.com/ -- email: [email protected] -- -- -------------------------------------------------------------------- -- -- Simulation Library File for EC/XP -- -- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCACOMP.vhd,v 1.1 2005/12/06 13:00:22 tame Exp $ -- --- LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE components IS function str2std(L: string) return std_logic_vector; function Str2int( L : string) return integer; function Str2real( L : string) return REAL; -----functions for Multipliers (for ECP)---------- function INT2VEC(INT: INTEGER; BWIDTH: INTEGER) RETURN STD_LOGIC_VECTOR; function VEC2INT(v: std_logic_vector) return integer; function ADDVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; function SUBVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; function TSCOMP(VECT: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; function BITX (VECT: std_logic) return boolean; function VECX (VECT: std_logic_vector) return boolean; -- COMPONENT ageb2 PORT( a0, a1: IN std_logic := 'X'; b0, b1: IN std_logic := 'X'; ci: IN std_logic := 'X'; ge: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT aleb2 PORT( a0, a1: IN std_logic := 'X'; b0, b1: IN std_logic := 'X'; ci: IN std_logic := 'X'; le: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT aneb2 PORT( a0, a1: IN std_logic := 'X'; b0, b1: IN std_logic := 'X'; ci: IN std_logic := 'X'; ne: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT and2 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT and3 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT and4 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT and5 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; e: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT cd2 PORT( ci : IN std_logic := 'X'; pc0, pc1 : IN std_logic := 'X'; co : OUT std_logic := 'X'; nc0, nc1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT cu2 PORT( ci : IN std_logic := 'X'; pc0, pc1 : IN std_logic := 'X'; co : OUT std_logic := 'X'; nc0, nc1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT cb2 PORT( ci : IN std_logic := 'X'; pc0, pc1 : IN std_logic := 'X'; con: IN std_logic := 'X'; co : OUT std_logic := 'X'; nc0, nc1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb2p3ax GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb2p3ay GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb2p3bx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb2p3dx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb2p3ix GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb2p3jx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb4p3ax GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb4p3ay GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb4p3bx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb4p3dx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb4p3ix GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lb4p3jx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; con: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld2p3ax GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld2p3ay GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld2p3bx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld2p3dx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld2p3ix GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld2p3jx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu2p3ax GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu2p3ay GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu2p3bx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu2p3dx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu2p3ix GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu2p3jx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld4p3ax GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld4p3ay GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld4p3bx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld4p3dx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld4p3ix GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ld4p3jx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu4p3ax GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu4p3ay GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu4p3bx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu4p3dx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu4p3ix GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT lu4p3jx GENERIC (gsr : String := "ENABLED"); PORT( d0, d1, d2, d3 : IN std_logic := 'X'; ci: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; co: OUT std_logic := 'X'; q0, q1, q2, q3 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fadd2 PORT( a0, a1 : IN std_logic := 'X'; b0, b1 : IN std_logic := 'X'; ci: IN std_logic := 'X'; cout0, cout1 : OUT std_logic := 'X'; s0, s1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fsub2 PORT( a0, a1 : IN std_logic := 'X'; b0, b1 : IN std_logic := 'X'; bi: IN std_logic := 'X'; bout0, bout1 : OUT std_logic := 'X'; s0, s1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fadsu2 PORT( a0, a1 : IN std_logic := 'X'; b0, b1 : IN std_logic := 'X'; bci: IN std_logic := 'X'; con: IN std_logic := 'X'; bco: OUT std_logic := 'X'; s0, s1 : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s1a GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s1ay GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s1b GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s1d GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s1i GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s1j GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1p3ax GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1p3ay GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1p3bx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1p3dx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1p3ix GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1p3jx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s3ax GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s3ay GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s3bx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s3dx GENERIC (gsr : String := "ENABLED"); PORT( d: IN std_logic := 'X'; ck: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s3ix GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fd1s3jx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; ck: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1p3az GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1p3ay GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1p3bx GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1p3dx GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1p3iy GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1p3jy GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1s1a GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1s1ay GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1s1b GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1s1d GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1s1i GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1s1j GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1s3ax GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT fl1s3ay GENERIC (gsr : String := "ENABLED"); PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; ck: IN std_logic := 'X'; sd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT gsr PORT( gsr: IN std_logic := 'X' ); END COMPONENT; -- COMPONENT inv PORT( a: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ifs1p3bx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp : IN std_logic := 'X'; sclk: IN std_logic := 'X'; pd : IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ifs1p3dx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp : IN std_logic := 'X'; sclk: IN std_logic := 'X'; cd : IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ifs1p3ix GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp : IN std_logic := 'X'; sclk: IN std_logic := 'X'; cd : IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ifs1p3jx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp : IN std_logic := 'X'; sclk: IN std_logic := 'X'; pd : IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ifs1s1b GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sclk: IN std_logic := 'X'; pd : IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ifs1s1d GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sclk: IN std_logic := 'X'; cd : IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ifs1s1i GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sclk: IN std_logic := 'X'; cd : IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ifs1s1j GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sclk: IN std_logic := 'X'; pd : IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT mux21 PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; sd: IN std_logic := 'X'; z : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT l6mux21 PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; sd: IN std_logic := 'X'; z : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT mux41 PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; d2: IN std_logic := 'X'; d3: IN std_logic := 'X'; sd1: IN std_logic := 'X'; sd2: IN std_logic := 'X'; z : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT mux81 PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; d2: IN std_logic := 'X'; d3: IN std_logic := 'X'; d4: IN std_logic := 'X'; d5: IN std_logic := 'X'; d6: IN std_logic := 'X'; d7: IN std_logic := 'X'; sd1: IN std_logic := 'X'; sd2: IN std_logic := 'X'; sd3: IN std_logic := 'X'; z : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT mux161 PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; d2: IN std_logic := 'X'; d3: IN std_logic := 'X'; d4: IN std_logic := 'X'; d5: IN std_logic := 'X'; d6: IN std_logic := 'X'; d7: IN std_logic := 'X'; d8: IN std_logic := 'X'; d9: IN std_logic := 'X'; d10: IN std_logic := 'X'; d11: IN std_logic := 'X'; d12: IN std_logic := 'X'; d13: IN std_logic := 'X'; d14: IN std_logic := 'X'; d15: IN std_logic := 'X'; sd1: IN std_logic := 'X'; sd2: IN std_logic := 'X'; sd3: IN std_logic := 'X'; sd4: IN std_logic := 'X'; z : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT mux321 PORT( d0: IN std_logic := 'X'; d1: IN std_logic := 'X'; d2: IN std_logic := 'X'; d3: IN std_logic := 'X'; d4: IN std_logic := 'X'; d5: IN std_logic := 'X'; d6: IN std_logic := 'X'; d7: IN std_logic := 'X'; d8: IN std_logic := 'X'; d9: IN std_logic := 'X'; d10: IN std_logic := 'X'; d11: IN std_logic := 'X'; d12: IN std_logic := 'X'; d13: IN std_logic := 'X'; d14: IN std_logic := 'X'; d15: IN std_logic := 'X'; d16: IN std_logic := 'X'; d17: IN std_logic := 'X'; d18: IN std_logic := 'X'; d19: IN std_logic := 'X'; d20: IN std_logic := 'X'; d21: IN std_logic := 'X'; d22: IN std_logic := 'X'; d23: IN std_logic := 'X'; d24: IN std_logic := 'X'; d25: IN std_logic := 'X'; d26: IN std_logic := 'X'; d27: IN std_logic := 'X'; d28: IN std_logic := 'X'; d29: IN std_logic := 'X'; d30: IN std_logic := 'X'; d31: IN std_logic := 'X'; sd1: IN std_logic := 'X'; sd2: IN std_logic := 'X'; sd3: IN std_logic := 'X'; sd4: IN std_logic := 'X'; sd5: IN std_logic := 'X'; z : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT nd2 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT nd3 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT nd4 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT nd5 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; e: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT nr2 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT nr3 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT nr4 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT nr5 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; e: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ofe1p3bx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; eclk: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ofe1p3dx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; eclk: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ofe1p3ix GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; eclk: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ofe1p3jx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; eclk: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ofs1p3bx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; sclk: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ofs1p3dx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; sclk: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ofs1p3ix GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; sclk: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT ofs1p3jx GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; sclk: IN std_logic := 'X'; pd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT or2 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT or3 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT or4 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT or5 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; e: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT pfumx PORT( alut: IN std_logic := 'X'; blut: IN std_logic := 'X'; c0 : IN std_logic := 'X'; z : OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT pur PORT( pur: IN std_logic := 'X' ); END COMPONENT; -- COMPONENT rom32x1 GENERIC( initval : string := "0x00000000" ); PORT( ad0, ad1, ad2, ad3, ad4: IN std_logic := 'X'; do0: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT rom16x1 GENERIC( initval : string := "0x0000" ); PORT( ad0, ad1, ad2, ad3: IN std_logic := 'X'; do0: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT rom64x1 GENERIC( initval : string := "0x0000000000000000" ); PORT( ad0, ad1, ad2, ad3, ad4, ad5 : IN std_logic := 'X'; do0: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT rom128x1 GENERIC( initval : string := "0x00000000000000000000000000000000" ); PORT( ad0, ad1, ad2, ad3, ad4, ad5, ad6 : IN std_logic := 'X'; do0: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT rom256x1 GENERIC( initval : string := "0x0000000000000000000000000000000000000000000000000000000000000000" ); PORT( ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7 : IN std_logic := 'X'; do0: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT strtup PORT( uclk : IN std_logic := 'X' ); END COMPONENT; -- COMPONENT tsall PORT( tsall: IN std_logic := 'X' ); END COMPONENT; -- COMPONENT vhi PORT( z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT vlo PORT( z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT xor2 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT xor3 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT xor4 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT xor5 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; e: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT xor11 PORT( a, b, c, d, e, f, g, h, i, j, k: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT xor21 PORT( a, b, c, d, e, f, g, h, i, j, k: IN std_logic := 'X'; l, m, n, o, p, q, r, s, t, u: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT xnor2 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT xnor3 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT xnor4 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT xnor5 PORT( a: IN std_logic := 'X'; b: IN std_logic := 'X'; c: IN std_logic := 'X'; d: IN std_logic := 'X'; e: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT bufba PORT( a: IN std_logic := 'X'; z: OUT std_logic := 'X' ); END COMPONENT; -- COMPONENT dp8ka GENERIC( DATA_WIDTH_A : in Integer := 18; DATA_WIDTH_B : in Integer := 18; REGMODE_A : String := "NOREG"; REGMODE_B : String := "NOREG"; RESETMODE : String := "ASYNC"; CSDECODE_A : String := "000"; CSDECODE_B : String := "000"; WRITEMODE_A : String := "NORMAL"; WRITEMODE_B : String := "NORMAL"; GSR : String := "ENABLED"; initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ); PORT( dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X'; dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X'; ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X'; ada9, ada10, ada11, ada12 : in std_logic := 'X'; cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X'; dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X'; dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X'; adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X'; adb9, adb10, adb11, adb12 : in std_logic := 'X'; ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X'; doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X'; doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X'; dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X'; dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X' ); END COMPONENT; -- COMPONENT pdp8ka GENERIC( DATA_WIDTH_W : in Integer := 18; DATA_WIDTH_R : in Integer := 18; REGMODE : String := "NOREG"; RESETMODE : String := "ASYNC"; CSDECODE_W : String := "000"; CSDECODE_R : String := "000"; GSR : String := "ENABLED"; initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ); PORT( di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X'; di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X'; di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X'; di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X'; adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X'; adw9, adw10, adw11, adw12 : in std_logic := 'X'; cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X'; adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X'; adr9, adr10, adr11, adr12 : in std_logic := 'X'; cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X'; do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X'; do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'; do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X'; do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X' ); END COMPONENT; -- COMPONENT sp8ka GENERIC( DATA_WIDTH : in Integer := 18; REGMODE : String := "NOREG"; RESETMODE : String := "ASYNC"; CSDECODE : String := "000"; WRITEMODE : String := "NORMAL"; GSR : String := "ENABLED"; initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ); PORT( di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X'; di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X'; ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X'; ad9, ad10, ad11, ad12 : in std_logic := 'X'; ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X'; do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X'; do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X' ); END COMPONENT; -- COMPONENT bbw PORT( b: INOUT std_logic := 'X'; i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT obw PORT( i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT ilvds PORT( a : IN std_logic := 'X'; an: IN std_logic := 'X'; z : OUT std_logic ); END COMPONENT; -- COMPONENT olvds PORT( a : IN std_logic := 'X'; z : OUT std_logic ; zn : OUT std_logic ); END COMPONENT; -- COMPONENT bb PORT( b: INOUT std_logic := 'X'; i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT bbpd PORT( b: INOUT std_logic := 'X'; i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT bbpu PORT( b: INOUT std_logic := 'X'; i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT ib PORT( i: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT ibpd PORT( i: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT ibpu PORT( i: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT ob PORT( i: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT obz PORT( i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT obzpd PORT( i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT obzpu PORT( i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic); END COMPONENT; -- COMPONENT dcs GENERIC( DCSMODE : String := "POS"); PORT( clk0 : IN std_logic; clk1 : IN std_logic; sel : IN std_logic; dcsout : OUT std_logic); END COMPONENT; -- component EPLLB generic( FIN : string := "100.0"; CLKI_DIV : string := "1"; CLKOP_DIV : string := "8"; CLKFB_DIV : string := "1"; FDEL : string := "1"; FB_MODE : string := "CLOCKTREE"; WAKE_ON_LOCK : string := "off"); port( CLKI : in STD_ULOGIC; RST : in STD_ULOGIC; CLKFB : in STD_ULOGIC; CLKOP : out STD_ULOGIC; LOCK : out STD_ULOGIC ); end component; -- component EHXPLLB generic( FIN : string := "100.0"; CLKI_DIV : string := "1"; CLKOP_DIV : string := "1"; CLKFB_DIV : string := "1"; FDEL : string := "1"; FB_MODE : string := "CLOCKTREE"; CLKOK_DIV : string := "2"; WAKE_ON_LOCK : string := "off"; DELAY_CNTL : string := "STATIC"; PHASEADJ : string := "0"; DUTY : string := "4"); port( CLKI : in STD_ULOGIC; CLKFB : in STD_ULOGIC; RST : in STD_ULOGIC := '0'; DDAMODE : in STD_ULOGIC; DDAIZR : in STD_ULOGIC; DDAILAG : in STD_ULOGIC; DDAIDEL0 : in STD_ULOGIC; DDAIDEL1 : in STD_ULOGIC; DDAIDEL2 : in STD_ULOGIC; CLKOP : out STD_ULOGIC; CLKOS : out STD_ULOGIC; CLKOK : out STD_ULOGIC; LOCK : out STD_ULOGIC; DDAOZR : out STD_ULOGIC; DDAOLAG : out STD_ULOGIC; DDAODEL0 : out STD_ULOGIC; DDAODEL1 : out STD_ULOGIC; DDAODEL2 : out STD_ULOGIC ); end component; -- ------Component ORCALUT4------ component ORCALUT4 generic( INIT : bit_vector); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Z : out STD_ULOGIC ); end component; ------Component ORCALUT5------ component ORCALUT5 generic( INIT : bit_vector); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Z : out STD_ULOGIC ); end component; ------Component ORCALUT6------ component ORCALUT6 generic( INIT : bit_vector); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; F : in STD_ULOGIC; Z : out STD_ULOGIC ); end component; ------Component ORCALUT7------ component ORCALUT7 generic( INIT : bit_vector); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; F : in STD_ULOGIC; G : in STD_ULOGIC; Z : out STD_ULOGIC ); end component; ------Component ORCALUT8------ component ORCALUT8 generic( INIT : bit_vector); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; F : in STD_ULOGIC; G : in STD_ULOGIC; H : in STD_ULOGIC; Z : out STD_ULOGIC ); end component; -- component MULT2 port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; B0 : in STD_ULOGIC; B1 : in STD_ULOGIC; B2 : in STD_ULOGIC; B3 : in STD_ULOGIC; CI : in STD_ULOGIC; P0 : out STD_ULOGIC; P1 : out STD_ULOGIC; CO : out STD_ULOGIC); end component; -- component IDDRXB generic( REGSET : string := "RESET"); port( D : in STD_LOGIC; ECLK : in STD_LOGIC; SCLK : in STD_LOGIC; LSR : in STD_LOGIC; CE : in STD_LOGIC; DDRCLKPOL : in STD_LOGIC; QA : out STD_LOGIC; QB : out STD_LOGIC ); end component; -- component ODDRXB generic( REGSET : string := "RESET"); port( DA : in STD_LOGIC; DB : in STD_LOGIC; CLK : in STD_LOGIC; LSR : in STD_LOGIC; Q : out STD_LOGIC ); end component; -- component CCU2 generic ( inject1_0 : string := "YES"; inject1_1 : string := "YES"; init0: string := "0x0000"; init1: string := "0x0000" ); port ( A0,A1 : in std_ulogic; B0,B1 : in std_ulogic; C0,C1 : in std_ulogic; D0,D1 : in std_ulogic; CIN : in std_ulogic; S0,S1 : out std_ulogic; COUT0,COUT1 : out std_ulogic ); end component; -- component DQSBUFB generic(DEL_ADJ : string := "PLUS"; DEL_VAL : string := "0"); port( DQSI : in STD_LOGIC; CLK : in STD_LOGIC; READ : in STD_LOGIC; DQSDEL : in STD_LOGIC; DQSO : out STD_LOGIC; DDRCLKPOL : out STD_LOGIC; DQSC : out STD_LOGIC; PRMBDET : out STD_LOGIC ); end component; -- component DQSDLL generic(DEL_ADJ : string := "PLUS"; DEL_VAL : string := "0"; LOCK_SENSITIVITY : string := "LOW"); port( CLK : in STD_ULOGIC; RST : in STD_ULOGIC; UDDCNTL : in STD_ULOGIC; LOCK : out STD_ULOGIC; DQSDEL : out STD_ULOGIC ); end component; -- -- 18x18 MULT for ECP component MULT18X18 generic( REG_INPUTA_CLK : string := "NONE"; REG_INPUTA_CE : string := "CE0"; REG_INPUTA_RST : string := "RST0"; REG_INPUTB_CLK : string := "NONE"; REG_INPUTB_CE : string := "CE0"; REG_INPUTB_RST : string := "RST0"; REG_PIPELINE_CLK : string := "NONE"; REG_PIPELINE_CE : string := "CE0"; REG_PIPELINE_RST : string := "RST0"; REG_OUTPUT_CLK : string := "NONE"; REG_OUTPUT_CE : string := "CE0"; REG_OUTPUT_RST : string := "RST0"; REG_SIGNEDAB_0_CLK : string := "NONE"; REG_SIGNEDAB_0_CE : string := "CE0"; REG_SIGNEDAB_0_RST : string := "RST0"; REG_SIGNEDAB_1_CLK : string := "NONE"; REG_SIGNEDAB_1_CE : string := "CE0"; REG_SIGNEDAB_1_RST : string := "RST0"; SHIFT_IN_A : string := "FALSE"; SHIFT_IN_B : string := "FALSE"; GSR : string := "ENABLED"); port ( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; A6 : in STD_ULOGIC; A7 : in STD_ULOGIC; A8 : in STD_ULOGIC; A9 : in STD_ULOGIC; A10 : in STD_ULOGIC; A11 : in STD_ULOGIC; A12 : in STD_ULOGIC; A13 : in STD_ULOGIC; A14 : in STD_ULOGIC; A15 : in STD_ULOGIC; A16 : in STD_ULOGIC; A17 : in STD_ULOGIC; SRIA0 : in STD_ULOGIC; SRIA1 : in STD_ULOGIC; SRIA2 : in STD_ULOGIC; SRIA3 : in STD_ULOGIC; SRIA4 : in STD_ULOGIC; SRIA5 : in STD_ULOGIC; SRIA6 : in STD_ULOGIC; SRIA7 : in STD_ULOGIC; SRIA8 : in STD_ULOGIC; SRIA9 : in STD_ULOGIC; SRIA10 : in STD_ULOGIC; SRIA11 : in STD_ULOGIC; SRIA12 : in STD_ULOGIC; SRIA13 : in STD_ULOGIC; SRIA14 : in STD_ULOGIC; SRIA15 : in STD_ULOGIC; SRIA16 : in STD_ULOGIC; SRIA17 : in STD_ULOGIC; B0 : in STD_ULOGIC; B1 : in STD_ULOGIC; B2 : in STD_ULOGIC; B3 : in STD_ULOGIC; B4 : in STD_ULOGIC; B5 : in STD_ULOGIC; B6 : in STD_ULOGIC; B7 : in STD_ULOGIC; B8 : in STD_ULOGIC; B9 : in STD_ULOGIC; B10 : in STD_ULOGIC; B11 : in STD_ULOGIC; B12 : in STD_ULOGIC; B13 : in STD_ULOGIC; B14 : in STD_ULOGIC; B15 : in STD_ULOGIC; B16 : in STD_ULOGIC; B17 : in STD_ULOGIC; SRIB0 : in STD_ULOGIC; SRIB1 : in STD_ULOGIC; SRIB2 : in STD_ULOGIC; SRIB3 : in STD_ULOGIC; SRIB4 : in STD_ULOGIC; SRIB5 : in STD_ULOGIC; SRIB6 : in STD_ULOGIC; SRIB7 : in STD_ULOGIC; SRIB8 : in STD_ULOGIC; SRIB9 : in STD_ULOGIC; SRIB10 : in STD_ULOGIC; SRIB11 : in STD_ULOGIC; SRIB12 : in STD_ULOGIC; SRIB13 : in STD_ULOGIC; SRIB14 : in STD_ULOGIC; SRIB15 : in STD_ULOGIC; SRIB16 : in STD_ULOGIC; SRIB17 : in STD_ULOGIC; SIGNEDAB : in STD_ULOGIC; CE0 : in STD_ULOGIC; CE1 : in STD_ULOGIC; CE2 : in STD_ULOGIC; CE3 : in STD_ULOGIC; CLK0 : in STD_ULOGIC; CLK1 : in STD_ULOGIC; CLK2 : in STD_ULOGIC; CLK3 : in STD_ULOGIC; RST0 : in STD_ULOGIC; RST1 : in STD_ULOGIC; RST2 : in STD_ULOGIC; RST3 : in STD_ULOGIC; SROA0 : out STD_ULOGIC; SROA1 : out STD_ULOGIC; SROA2 : out STD_ULOGIC; SROA3 : out STD_ULOGIC; SROA4 : out STD_ULOGIC; SROA5 : out STD_ULOGIC; SROA6 : out STD_ULOGIC; SROA7 : out STD_ULOGIC; SROA8 : out STD_ULOGIC; SROA9 : out STD_ULOGIC; SROA10 : out STD_ULOGIC; SROA11 : out STD_ULOGIC; SROA12 : out STD_ULOGIC; SROA13 : out STD_ULOGIC; SROA14 : out STD_ULOGIC; SROA15 : out STD_ULOGIC; SROA16 : out STD_ULOGIC; SROA17 : out STD_ULOGIC; SROB0 : out STD_ULOGIC; SROB1 : out STD_ULOGIC; SROB2 : out STD_ULOGIC; SROB3 : out STD_ULOGIC; SROB4 : out STD_ULOGIC; SROB5 : out STD_ULOGIC; SROB6 : out STD_ULOGIC; SROB7 : out STD_ULOGIC; SROB8 : out STD_ULOGIC; SROB9 : out STD_ULOGIC; SROB10 : out STD_ULOGIC; SROB11 : out STD_ULOGIC; SROB12 : out STD_ULOGIC; SROB13 : out STD_ULOGIC; SROB14 : out STD_ULOGIC; SROB15 : out STD_ULOGIC; SROB16 : out STD_ULOGIC; SROB17 : out STD_ULOGIC; P0 : out STD_ULOGIC; P1 : out STD_ULOGIC; P2 : out STD_ULOGIC; P3 : out STD_ULOGIC; P4 : out STD_ULOGIC; P5 : out STD_ULOGIC; P6 : out STD_ULOGIC; P7 : out STD_ULOGIC; P8 : out STD_ULOGIC; P9 : out STD_ULOGIC; P10 : out STD_ULOGIC; P11 : out STD_ULOGIC; P12 : out STD_ULOGIC; P13 : out STD_ULOGIC; P14 : out STD_ULOGIC; P15 : out STD_ULOGIC; P16 : out STD_ULOGIC; P17 : out STD_ULOGIC; P18 : out STD_ULOGIC; P19 : out STD_ULOGIC; P20 : out STD_ULOGIC; P21 : out STD_ULOGIC; P22 : out STD_ULOGIC; P23 : out STD_ULOGIC; P24 : out STD_ULOGIC; P25 : out STD_ULOGIC; P26 : out STD_ULOGIC; P27 : out STD_ULOGIC; P28 : out STD_ULOGIC; P29 : out STD_ULOGIC; P30 : out STD_ULOGIC; P31 : out STD_ULOGIC; P32 : out STD_ULOGIC; P33 : out STD_ULOGIC; P34 : out STD_ULOGIC; P35 : out STD_ULOGIC ); end component; end Components; package body Components is function str2std(L: string) return std_logic_vector is variable vpos : integer := 0; -- Index of last valid bit in val. variable lpos : integer; -- Index of next unused char in L. variable val : std_logic_vector(1 to L'right); -- lenth of the vector. begin lpos := L'left; while lpos <= L'right and vpos < VAL'length loop if L(lpos) = '0' then vpos := vpos + 1; val(vpos) := '0'; elsif L(lpos) = '1' then vpos := vpos + 1; val(vpos) := '1'; else exit; -- Bit values must be '0' or '1'. end if; lpos := lpos + 1; end loop; return val; end str2std; function str2int( L : string) return integer is variable ok: boolean; variable pos: integer:=1; variable sign: integer := 1; variable rval: integer := 0; variable value: integer := 0; begin ok := FALSE; if pos < L'right and (L(pos) = '-' or L(pos) = '+') then if L(pos) = '-' then sign := -1; end if; pos := pos + 1; end if; -- Once the optional leading sign is removed, an integer can -- contain only the digits '0' through '9' and the '_' -- (underscore) character. VHDL disallows two successive -- underscores, and leading or trailing underscores. if pos <= L'right and L(pos) >= '0' and L(pos) <= '9' then while pos <= L'right loop if L(pos) >= '0' and L(pos) <= '9' then rval := rval * 10 + character'pos(L(pos)) - character'pos('0'); ok := TRUE; elsif L(pos) = '_' then if pos = L'right or L(pos + 1) < '0' or L(pos + 1) > '9' then ok := FALSE; exit; end if; else exit; end if; pos := pos + 1; end loop; end if; value := sign * rval; RETURN(value); end str2int; function str2real( L: string) return real is variable pos: integer; variable value: real; variable ok: boolean; variable sign: real := 1.0; variable rval: real := 0.0; variable powerten: real := 0.1; begin pos := L'left; if (pos <= L'right) and (L(pos) = '-') then sign := -1.0; pos := pos + 1; end if; ok := FALSE; rval := 0.0; if pos <= L'right and L(pos) >= '0' and L(pos) <= '9' then while pos <= L'right and L(pos) /= '.' and L(pos) /= ' ' and L(pos) /= HT loop if L(pos) >= '0' and L(pos) <= '9' then rval := rval*10.0 + real(character'pos(L(pos)) - character'pos('0')); pos := pos+1; ok := true; else ok := false; exit; end if; end loop; end if; if ok and pos <= L'right and L(pos) = '.' then pos := pos + 1; end if; if pos <= L'right then while pos <= L'right and ((L(pos) >= '0' and L(pos) <= '9') or L(pos) = '_') loop rval := rval + (real(character'pos(L(pos))-character'pos('0'))*powerten); powerten := powerten*0.1; pos := pos+1; ok := true; end loop; end if; if ok then value := rval * sign; end if; return (value); end str2real; function INT2VEC(INT: INTEGER; BWIDTH: INTEGER) RETURN STD_LOGIC_VECTOR is variable result : STD_LOGIC_VECTOR (BWIDTH-1 downto 0); variable tmp : integer := INT; begin tmp := INT; for i in 0 to BWIDTH-1 loop if (tmp mod 2) = 1 then result(i) := '1'; else result(i) := '0'; end if; if tmp > 0 then tmp := tmp /2 ; elsif (tmp > integer'low) then tmp := (tmp-1) / 2; else tmp := tmp / 2; end if; end loop; return result; end; function VEC2INT(v: std_logic_vector) return integer is variable result: integer := 0; variable addition: integer := 1; begin for b in v'reverse_range loop if v(b) = '1' then result := result + addition; end if; addition := addition * 2; end loop; return result; end VEC2INT; function VECX (VECT: std_logic_vector) return boolean is begin for b in VECT'range loop if bitX (VECT (b)) then return true; end if; end loop; return false; end VECX; function TSCOMP(VECT: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is variable result : STD_LOGIC_VECTOR (VECT'left downto 0); variable is1 : std_ulogic := '0'; begin for i in 0 to VECT'left loop if (is1 = '0') then result(i) := VECT(i); if (VECT(i) = '1' ) then is1 := '1'; end if; else result(i) := NOT VECT(i); end if; end loop; return result; end; function ADDVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is variable cout: STD_ULOGIC; variable BVect, result: STD_LOGIC_VECTOR(A'left downto 0); begin for i in 0 to A'left loop if (A(i) = 'X') then result := (others => 'X'); return(result); end if; end loop; for i in 0 to B'left loop if (B(i) = 'X') then result := (others => 'X'); return(result); end if; end loop; cout := '0'; BVEct := B; for i in 0 to A'left loop result(i) := A(i) xor BVect(i) xor cout; cout := (A(i) and BVect(i)) or (A(i) and cout) or (cout and BVect(i)); end loop; return result; end; function SUBVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is variable cout: STD_ULOGIC; variable result: STD_LOGIC_VECTOR(A'left downto 0); begin for i in 0 to A'left loop if (A(i) = 'X') then result := (others => 'X'); return(result); end if; end loop; for i in 0 to B'left loop if (B(i) = 'X') then result := (others => 'X'); return(result); end if; end loop; cout := '1'; for i in 0 to A'left loop result(i) := A(i) xor not B(i) xor cout; cout := (A(i) and not B(i)) or (A(i) and cout) or (cout and not B(i)); end loop; return result; end; function BITX (VECT: std_logic) return boolean is begin case VECT is when 'X' => return true; when others => return false; end case; end BITX; END components;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de0-nano/leon3mp.vhd
1
20867
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- LEON3 Demonstration design -- Copyright (C) 2012 Aeroflex Gaisler ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib, techmap; use grlib.amba.all; use grlib.devices.all; use grlib.stdlib.all; use techmap.gencomp.all; library gaisler; use gaisler.memctrl.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.jtag.all; use gaisler.i2c.all; use gaisler.spi.all; -- pragma translate_off use gaisler.sim.all; -- pragma translate_on use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; dbguart : integer := CFG_DUART; pclow : integer := CFG_PCLOW ); port ( clock_50 : in std_logic; led : inout std_logic_vector(7 downto 0); key : in std_logic_vector(1 downto 0); sw : in std_logic_vector(3 downto 0); dram_ba : out std_logic_vector(1 downto 0); dram_dqm : out std_logic_vector(1 downto 0); dram_ras_n : out std_ulogic; dram_cas_n : out std_ulogic; dram_cke : out std_ulogic; dram_clk : out std_ulogic; dram_we_n : out std_ulogic; dram_cs_n : out std_ulogic; dram_dq : inout std_logic_vector(15 downto 0); dram_addr : out std_logic_vector(12 downto 0); epcs_data0 : in std_ulogic; epcs_dclk : out std_ulogic; epcs_ncso : out std_ulogic; epcs_asdo : out std_ulogic; i2c_sclk : inout std_logic; i2c_sdat : inout std_logic; g_sensor_cs_n : out std_ulogic; g_sensor_int : in std_ulogic; adc_cs_n : out std_ulogic; adc_saddr : out std_ulogic; adc_sclk : out std_ulogic; adc_sdat : in std_ulogic; gpio_2 : inout std_logic_vector(12 downto 0); gpio_2_in : in std_logic_vector(2 downto 0); gpio_1_in : in std_logic_vector(1 downto 0); gpio_1 : inout std_logic_vector(33 downto 0); gpio_0_in : in std_logic_vector(1 downto 0); gpio_0 : inout std_logic_vector(33 downto 0) ); end; architecture rtl of leon3mp is signal vcc, gnd : std_logic_vector(4 downto 0); signal clkm, rstn, rstraw, sdclkl, lclk, rst, clklck : std_ulogic; signal sdi : sdctrl_in_type; signal sdo : sdctrl_out_type; signal spmi : spimctrl_in_type; signal spmo : spimctrl_out_type; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal u1i, dui : uart_in_type; signal u1o, duo : uart_out_type; signal irqi : irq_in_vector(0 to CFG_NCPU-1); signal irqo : irq_out_vector(0 to CFG_NCPU-1); signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal fpi : grfpu_in_vector_type; signal fpo : grfpu_out_vector_type; signal stati : ahbstat_in_type; signal gpti : gptimer_in_type; signal i2ci : i2c_in_type; signal i2co : i2c_out_type; signal spii : spi_in_type; signal spio : spi_out_type; signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0); signal gpio0i, gpio1i, gpio2i : gpio_in_type; signal gpio0o, gpio1o, gpio2o : gpio_out_type; signal dsubren : std_ulogic; signal tck, tms, tdi, tdo : std_logic; constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz, used in clkgen constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; constant IOAEN : integer := 1; constant OEPOL : integer := padoen_polarity(padtech); begin ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); clk_pad : clkpad generic map (tech => padtech) port map (clock_50, lclk); clkgen0 : entity work.clkgen_de0 generic map (clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV, clk_freq => BOARD_FREQ, sdramen => CFG_SDCTRL) port map (inclk0 => lclk, c0 => clkm, c0_2x => open, e0 => sdclkl, locked => clklck); sdclk_pad : outpad generic map (tech => padtech, slew => 1) port map (dram_clk, sdclkl); resetn_pad : inpad generic map (tech => padtech) port map (key(0), rst); rst0 : rstgen -- reset generator (reset is active LOW) port map (rst, clkm, clklck, rstn, rstraw); ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN, nahbm => CFG_NCPU+CFG_AHB_JTAG, nahbs => 6) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- ----- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- cpu : for i in 0 to CFG_NCPU-1 generate nosh : if CFG_GRFPUSH = 0 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0, CFG_MMU_PAGE, CFG_BP) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; end generate; sh : if CFG_GRFPUSH = 1 generate cpu : for i in 0 to CFG_NCPU-1 generate u0 : leon3sh -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0, CFG_MMU_PAGE, CFG_BP) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i)); end generate; grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech) port map (clkm, rstn, fpi, fpo); end generate; errorn_pad : outpad generic map (tech => padtech) port map (led(6), dbgo(0).error); dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsuen_pad : inpad generic map (tech => padtech) port map (sw(0), dsui.enable); dsubre_pad : inpad generic map (tech => padtech) port map (key(1), dsubren); dsui.break <= not dsubren; dsuact_pad : outpad generic map (tech => padtech) port map (led(7), dsuo.active); end generate; nodsu : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU) port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- Memory controllers ---------------------------------------------- ---------------------------------------------------------------------- sdctrl0 : if CFG_SDCTRL = 1 generate -- 16-bit SDRAM controller sdc : entity work.sdctrl16 generic map (hindex => 3, haddr => 16#400#, hmask => 16#FE0#, ioaddr => 1, fast => 0, pwron => 0, invclk => 0, sdbits => 16, pageburst => 2) port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo); sa_pad : outpadv generic map (width => 13, tech => padtech) port map (dram_addr, sdo.address(14 downto 2)); ba0_pad : outpadv generic map (tech => padtech, width => 2) port map (dram_ba, sdo.address(16 downto 15)); sd_pad : iopadvv generic map (width => 16, tech => padtech, oepol => OEPOL) port map (dram_dq(15 downto 0), sdo.data(15 downto 0), sdo.vbdrive(15 downto 0), sdi.data(15 downto 0)); sdcke_pad : outpad generic map (tech => padtech) port map (dram_cke, sdo.sdcke(0)); sdwen_pad : outpad generic map (tech => padtech) port map (dram_we_n, sdo.sdwen); sdcsn_pad : outpad generic map (tech => padtech) port map (dram_cs_n, sdo.sdcsn(0)); sdras_pad : outpad generic map (tech => padtech) port map (dram_ras_n, sdo.rasn); sdcas_pad : outpad generic map (tech => padtech) port map (dram_cas_n, sdo.casn); sddqm_pad : outpadv generic map (tech => padtech, width => 2) port map (dram_dqm, sdo.dqm(1 downto 0)); end generate; spimctrl0: if CFG_SPIMCTRL /= 0 generate -- SPI Memory Controller spimc : spimctrl generic map (hindex => 0, hirq => 10, faddr => 16#000#, fmask => 16#f00#, ioaddr => 16#002#, iomask => 16#fff#, spliten => CFG_SPLIT, oepol => OEPOL,sdcard => CFG_SPIMCTRL_SDCARD, readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE, dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER, altscaler => CFG_SPIMCTRL_ASCALER, pwrupcnt => CFG_SPIMCTRL_PWRUPCNT, offset => CFG_SPIMCTRL_OFFSET) port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo); end generate; nospimctrl0 : if CFG_SPIMCTRL = 0 generate spmo <= spimctrl_out_none; end generate; miso_pad : inpad generic map (tech => padtech) port map (epcs_data0, spmi.miso); mosi_pad : outpad generic map (tech => padtech) port map (epcs_asdo, spmo.mosi); sck_pad : outpad generic map (tech => padtech) port map (epcs_dclk, spmo.sck); slvsel0_pad : outpad generic map (tech => padtech) port map (epcs_ncso, spmo.csn); ---------------------------------------------------------------------- --- AHB ROM --------------------------------------------------------- ---------------------------------------------------------------------- bpromgen : if CFG_AHBROMEN /= 0 and CFG_SPIMCTRL = 0 generate brom : entity work.ahbrom generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map (rstn, clkm, ahbsi, ahbso(0)); end generate; noprom : if CFG_AHBROMEN = 0 and CFG_SPIMCTRL = 0 generate ahbso(0) <= ahbs_none; end generate; ---------------------------------------------------------------------- --- APB Bridge and various peripherals ------------------------------ ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); apbo(0) <= apb_none; -- Typically occupied by memory controller ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, flow => 0, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.extclk <= '0'; u1i.rxd <= '1'; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; end generate; notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master i2c0 : i2cmst generic map (pindex => 4, paddr => 4, pmask => 16#FFF#, pirq => 3, filter => 3, dynfilt => 1) port map (rstn, clkm, apbi, apbo(4), i2ci, i2co); end generate; noi2cm: if CFG_I2C_ENABLE = 0 generate i2co.scloen <= '1'; i2co.sdaoen <= '1'; i2co.scl <= '0'; i2co.sda <= '0'; end generate; i2c_scl_pad : iopad generic map (tech => padtech) port map (i2c_sclk, i2co.scl, i2co.scloen, i2ci.scl); i2c_sda_pad : iopad generic map (tech => padtech) port map (i2c_sdat, i2co.sda, i2co.sdaoen, i2ci.sda); spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller spi1 : spictrl generic map (pindex => 5, paddr => 5, pmask => 16#fff#, pirq => 5, fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG, slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0, syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT) port map (rstn, clkm, apbi, apbo(5), spii, spio, slvsel); spii.spisel <= '1'; -- Master only spii.astart <= '0'; miso_pad : inpad generic map (tech => padtech) port map (adc_sdat, spii.miso); mosi_pad : outpad generic map (tech => padtech) port map (adc_saddr, spio.mosi); sck_pad : outpad generic map (tech => padtech) port map (adc_sclk, spio.sck); slvsel_pad : outpad generic map (tech => padtech) port map (adc_cs_n, slvsel(0)); end generate spic; nospi: if CFG_SPICTRL_ENABLE = 0 generate miso_pad : inpad generic map (tech => padtech) port map (adc_sdat, spii.miso); mosi_pad : outpad generic map (tech => padtech) port map (adc_saddr, vcc(0)); sck_pad : outpad generic map (tech => padtech) port map (adc_sclk, gnd(0)); slvsel_pad : outpad generic map (tech => padtech) port map (adc_cs_n, vcc(0)); end generate; gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GRGPIO0 port grgpio0: grgpio generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH) port map( rstn, clkm, apbi, apbo(9), gpio0i, gpio0o); pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate pio_pad : iopad generic map (tech => padtech) port map (gpio_0(i), gpio0o.dout(i), gpio0o.oen(i), gpio0i.din(i)); end generate; end generate; nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none; end generate; gpio1 : if CFG_GRGPIO2_ENABLE /= 0 generate -- GRGPIO1 port grgpio1: grgpio generic map( pindex => 10, paddr => 10, imask => CFG_GRGPIO2_IMASK, nbits => CFG_GRGPIO2_WIDTH) port map( rstn, clkm, apbi, apbo(10), gpio1i, gpio1o); pio_pads : for i in 0 to CFG_GRGPIO2_WIDTH-1 generate pio_pad : iopad generic map (tech => padtech) port map (gpio_1(i), gpio1o.dout(i), gpio1o.oen(i), gpio1i.din(i)); end generate; end generate; nogpio1: if CFG_GRGPIO2_ENABLE = 0 generate apbo(10) <= apb_none; end generate; grgpio2: grgpio -- GRGPIO2 port generic map( pindex => 11, paddr => 11, imask => 2**30, nbits => 31) port map( rstn, clkm, apbi, apbo(11), gpio2i, gpio2o); gpio_2_pads : iopadvv generic map (tech => padtech, width => 13) port map (gpio_2(12 downto 0), gpio2o.dout(12 downto 0), gpio2o.oen(12 downto 0), gpio2i.din(12 downto 0)); gpio_2_inpads : inpadv generic map (tech => padtech, width => 3) port map (gpio_2_in, gpio2i.din(15 downto 13)); gpio_0_pads : iopadvv generic map (tech => padtech, width => 2) port map (gpio_0(33 downto 32), gpio2o.dout(17 downto 16), gpio2o.oen(17 downto 16), gpio2i.din(17 downto 16)); gpio_0_inpads : inpadv generic map (tech => padtech, width => 2) port map (gpio_0_in, gpio2i.din(19 downto 18)); gpio_1_pads : iopadvv generic map (tech => padtech, width => 2) port map (gpio_1(33 downto 32), gpio2o.dout(21 downto 20), gpio2o.oen(21 downto 20), gpio2i.din(21 downto 20)); gpio_1_inpads : inpadv generic map (tech => padtech, width => 2) port map (gpio_1_in, gpio2i.din(23 downto 22)); led_pads : iopadvv generic map (tech => padtech, width => 6) port map (led(5 downto 0), gpio2o.dout(29 downto 24), gpio2o.oen(29 downto 24), gpio2i.din(29 downto 24)); g_sensor_int_pad : inpad generic map (tech => padtech) port map (g_sensor_int, gpio2i.din(30)); -- g_sensor_cs_n_pad : outpad generic map (tech => padtech) -- port map (g_sensor_cs_n, gpio2o.dout(31)); g_sensor_cs_n <= '1'; -- gpio2i.din(31) <= gpio2o.dout(31); ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1, nftslv => CFG_AHBSTATN) port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15)); end generate; nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ocram : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) port map (rstn, clkm, ahbsi, ahbso(4)); end generate; nram : if CFG_AHBRAMEN = 0 generate ahbso(4) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- Test report module ---------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off test0 : ahbrep generic map (hindex => 5, haddr => 16#200#) port map (rstn, clkm, ahbsi, ahbso(5)); -- pragma translate_on ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 Altera DE0-EP4CE22 Demonstration design", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on end;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys2/config.vhd
1
5271
----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench configuration -- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------ library techmap; use techmap.gencomp.all; package config is -- Technology and synthesis options constant CFG_FABTECH : integer := spartan3e; constant CFG_MEMTECH : integer := spartan3e; constant CFG_PADTECH : integer := spartan3e; constant CFG_NOASYNC : integer := 0; constant CFG_SCAN : integer := 0; -- Clock generator constant CFG_CLKTECH : integer := spartan3e; constant CFG_CLKMUL : integer := (6); constant CFG_CLKDIV : integer := (5); constant CFG_OCLKDIV : integer := 1; constant CFG_OCLKBDIV : integer := 0; constant CFG_OCLKCDIV : integer := 0; constant CFG_PCIDLL : integer := 0; constant CFG_PCISYSCLK: integer := 0; constant CFG_CLK_NOFB : integer := 0; -- LEON3 processor core constant CFG_LEON3 : integer := 1; constant CFG_NCPU : integer := (1); constant CFG_NWIN : integer := (8); constant CFG_V8 : integer := 16#32# + 4*0; constant CFG_MAC : integer := 0; constant CFG_BP : integer := 1; constant CFG_SVT : integer := 0; constant CFG_RSTADDR : integer := 16#00000#; constant CFG_LDDEL : integer := (1); constant CFG_NOTAG : integer := 0; constant CFG_NWP : integer := (0); constant CFG_PWD : integer := 0*2; constant CFG_FPU : integer := 0 + 16*0 + 32*0; constant CFG_GRFPUSH : integer := 0; constant CFG_ICEN : integer := 1; constant CFG_ISETS : integer := 2; constant CFG_ISETSZ : integer := 4; constant CFG_ILINE : integer := 8; constant CFG_IREPL : integer := 2; constant CFG_ILOCK : integer := 0; constant CFG_ILRAMEN : integer := 0; constant CFG_ILRAMADDR: integer := 16#8E#; constant CFG_ILRAMSZ : integer := 1; constant CFG_DCEN : integer := 1; constant CFG_DSETS : integer := 2; constant CFG_DSETSZ : integer := 4; constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; constant CFG_DSNOOP : integer := 0 + 0 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; constant CFG_DLRAMSZ : integer := 1; constant CFG_MMUEN : integer := 0; constant CFG_ITLBNUM : integer := 2; constant CFG_DTLBNUM : integer := 2; constant CFG_TLB_TYPE : integer := 1 + 0*2; constant CFG_TLB_REP : integer := 1; constant CFG_MMU_PAGE : integer := 0; constant CFG_DSU : integer := 1; constant CFG_ITBSZ : integer := 2; constant CFG_ATBSZ : integer := 2; constant CFG_LEON3FT_EN : integer := 0; constant CFG_IUFT_EN : integer := 0; constant CFG_FPUFT_EN : integer := 0; constant CFG_RF_ERRINJ : integer := 0; constant CFG_CACHE_FT_EN : integer := 0; constant CFG_CACHE_ERRINJ : integer := 0; constant CFG_LEON3_NETLIST: integer := 0; constant CFG_DISAS : integer := 0 + 0; constant CFG_PCLOW : integer := 2; -- AMBA settings constant CFG_DEFMST : integer := (0); constant CFG_RROBIN : integer := 1; constant CFG_SPLIT : integer := 0; constant CFG_FPNPEN : integer := 0; constant CFG_AHBIO : integer := 16#FFF#; constant CFG_APBADDR : integer := 16#800#; constant CFG_AHB_MON : integer := 0; constant CFG_AHB_MONERR : integer := 0; constant CFG_AHB_MONWAR : integer := 0; constant CFG_AHB_DTRACE : integer := 0; -- JTAG based DSU interface constant CFG_AHB_JTAG : integer := 1; -- LEON2 memory controller constant CFG_MCTRL_LEON2 : integer := 1; constant CFG_MCTRL_RAM8BIT : integer := 0; constant CFG_MCTRL_RAM16BIT : integer := 1; constant CFG_MCTRL_5CS : integer := 0; constant CFG_MCTRL_SDEN : integer := 0; constant CFG_MCTRL_SEPBUS : integer := 0; constant CFG_MCTRL_INVCLK : integer := 0; constant CFG_MCTRL_SD64 : integer := 0; constant CFG_MCTRL_PAGE : integer := 0 + 0; -- AHB ROM constant CFG_AHBROMEN : integer := 1; constant CFG_AHBROPIP : integer := 1; constant CFG_AHBRODDR : integer := 16#000#; constant CFG_ROMADDR : integer := 16#100#; constant CFG_ROMMASK : integer := 16#E00# + 16#100#; -- AHB RAM constant CFG_AHBRAMEN : integer := 0; constant CFG_AHBRSZ : integer := 1; constant CFG_AHBRADDR : integer := 16#A00#; constant CFG_AHBRPIPE : integer := 0; -- UART 1 constant CFG_UART1_ENABLE : integer := 1; constant CFG_UART1_FIFO : integer := 1; -- LEON3 interrupt controller constant CFG_IRQ3_ENABLE : integer := 0; constant CFG_IRQ3_NSEC : integer := 0; -- Modular timer constant CFG_GPT_ENABLE : integer := 1; constant CFG_GPT_NTIM : integer := (2); constant CFG_GPT_SW : integer := (8); constant CFG_GPT_TW : integer := (32); constant CFG_GPT_IRQ : integer := (8); constant CFG_GPT_SEPIRQ : integer := 1; constant CFG_GPT_WDOGEN : integer := 0; constant CFG_GPT_WDOG : integer := 16#0#; -- GPIO port constant CFG_GRGPIO_ENABLE : integer := 1; constant CFG_GRGPIO_IMASK : integer := 16#00F0#; constant CFG_GRGPIO_WIDTH : integer := (18); -- VGA and PS2/ interface constant CFG_KBD_ENABLE : integer := 1; constant CFG_VGA_ENABLE : integer := 1; constant CFG_SVGA_ENABLE : integer := 0; -- GRLIB debugging constant CFG_DUART : integer := 0; end;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/lib/techmap/maps/syncram64.vhd
1
7449
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: syncram64 -- File: syncram64.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: 64-bit syncronous 1-port ram with 32-bit write strobes -- and tech selection ------------------------------------------------------------------------------ library ieee; library techmap; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allmem.all; library grlib; use grlib.config.all; use grlib.config_types.all; use grlib.stdlib.all; entity syncram64 is generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; paren : integer := 0; custombits : integer := 1); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63+8*paren downto 0); dataout : out std_logic_vector (63+8*paren downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0); testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none; customclk: in std_ulogic := '0'; customin : in std_logic_vector(2*custombits-1 downto 0) := (others => '0'); customout:out std_logic_vector(2*custombits-1 downto 0)); end; architecture rtl of syncram64 is component unisim_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; component artisan_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; component custom1_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; component smic13_syncram64 generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (63 downto 0); dataout : out std_logic_vector (63 downto 0); enable : in std_logic_vector (1 downto 0); write : in std_logic_vector (1 downto 0) ); end component; signal dinp, doutp : std_logic_vector(71 downto 0); signal xenable : std_logic_vector(1 downto 0); signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0); begin xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else "00"; custominx(custominx'high downto custombits) <= (others => '0'); custominx(custombits-1 downto 0) <= customin(custombits-1 downto 0); nocust: if syncram_has_customif(tech)=0 or has_sram64(tech)=0 or paren=1 generate customoutx <= (others => '0'); end generate; nopar : if paren = 0 generate s64 : if has_sram64(tech) = 1 generate xc2v : if (is_unisim(tech) = 1) generate x0 : unisim_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; arti : if tech = memartisan generate x0 : artisan_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; cust1: if tech = custom1 generate x0 : custom1_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; smic: if tech = smic013 generate x0 : smic13_syncram64 generic map (abits) port map (clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; n2x : if tech = easic45 generate x0 : n2x_syncram_we generic map (abits => abits, dbits => 64) port map(clk, address, datain(63 downto 0), dataout(63 downto 0), xenable, write); end generate; customout(2*custombits-1 downto custombits) <= (others => '0'); customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0); -- pragma translate_off dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate x : process begin assert false report "syncram64: " & tost(2**abits) & "x64" & " (" & tech_table(tech) & ")" severity note; wait; end process; end generate; -- pragma translate_on end generate; nos64 : if has_sram64(tech) = 0 generate x0 : syncram generic map (tech, abits, 32, testen, custombits) port map (clk, address, datain(63 downto 32), dataout(63 downto 32), enable(1), write(1), testin, customclk, customin(2*custombits-1 downto custombits), customout(2*custombits-1 downto custombits)); x1 : syncram generic map (tech, abits, 32, testen, custombits) port map (clk, address, datain(31 downto 0), dataout(31 downto 0), enable(0), write(0), testin, customclk, customin(custombits-1 downto 0), customout(custombits-1 downto 0)); end generate; end generate; par : if paren = 1 generate dinp <= datain(63+8*paren downto 60+8*paren) & datain(63 downto 32) & datain(63+4*paren downto 60+4*paren) & datain(31 downto 0); dataout <= doutp(71 downto 68) & doutp(35 downto 32) & doutp(67 downto 36) & doutp(31-8+8*paren downto 0); x0 : syncram generic map (tech, abits, 36, testen, custombits) port map (clk, address, dinp(71 downto 36), doutp(71 downto 36), enable(1), write(1), testin, customclk, customin(2*custombits-1 downto custombits), customout(2*custombits-1 downto custombits)); x1 : syncram generic map (tech, abits, 36, testen, custombits) port map (clk, address, dinp(35 downto 0), doutp(35 downto 0), enable(0), write(0), testin, customclk, customin(custombits-1 downto 0), customout(custombits-1 downto 0)); end generate; end;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ddr2spax.vhd
1
8952
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: ddr2spax -- File: ddr2spax.vhd -- Author: Magnus Hjorth - Aeroflex Gaisler -- Description: DDR2 memory controller with asynch AHB interface -- Based on ddr2sp(16/32/64)a, generalized and expanded -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library grlib; use grlib.stdlib.all; use grlib.amba.all; use grlib.devices.all; library gaisler; use gaisler.ddrpkg.all; use gaisler.ddrintpkg.all; library techmap; use techmap.gencomp.ddr2phy_has_datavalid; use techmap.gencomp.ddr2phy_ptctrl; entity ddr2spax is generic ( memtech : integer := 0; phytech : integer := 0; hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#f00#; ioaddr : integer := 16#000#; iomask : integer := 16#fff#; ddrbits : integer := 32; burstlen : integer := 8; MHz : integer := 100; TRFC : integer := 130; col : integer := 9; Mbyte : integer := 8; pwron : integer := 0; oepol : integer := 0; readdly : integer := 1; odten : integer := 0; octen : integer := 0; -- dqsgating : integer := 0; nosync : integer := 0; dqsgating : integer := 0; eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4 dqsse : integer range 0 to 1 := 0; -- single ended DQS ddr_syncrst: integer range 0 to 1 := 0; ahbbits : integer := ahbdw; ft : integer range 0 to 1 := 0; bigmem : integer range 0 to 1 := 0; raspipe : integer range 0 to 1 := 0; hwidthen : integer range 0 to 1 := 0; rstdel : integer := 200; scantest : integer := 0 ); port ( ddr_rst : in std_ulogic; ahb_rst : in std_ulogic; clk_ddr : in std_ulogic; clk_ahb : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; sdi : in ddrctrl_in_type; sdo : out ddrctrl_out_type; hwidth : in std_ulogic ); end ddr2spax; architecture rtl of ddr2spax is constant REVISION : integer := 1; constant ramwt: integer := 0; constant l2blen: integer := log2(burstlen)+log2(32); constant l2ddrw: integer := log2(ddrbits*2); function pick(choice: boolean; t,f: integer) return integer is begin if choice then return t; else return f; end if; end; constant xahbw: integer := pick(ft/=0 and ahbbits<64, 64, ahbbits); constant l2ahbw: integer := log2(xahbw); -- For non-FT, write buffer has room for two write bursts and is addressable -- down to 32-bit level on write (AHB) side. -- For FT, the write buffer has room for one write burst and is addressable -- down to 64-bit level on write side. -- Write buffer dimensions constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw; constant wbuf_rabits_r: integer := wbuf_rabits_s-FT; constant wbuf_rdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits); constant wbuf_wabits: integer := pick(ft/=0, l2blen-6, 1+l2blen-5); constant wbuf_wdbits: integer := pick(ft/=0, xahbw+xahbw/2, xahbw); -- Read buffer dimensions constant rbuf_rabits: integer := l2blen-l2ahbw; constant rbuf_rdbits: integer := wbuf_wdbits; constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits)); constant rbuf_wdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits); signal request : ddr_request_type; signal start_tog : std_logic; signal response : ddr_response_type; signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0); signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0); signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0); signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0); signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0); signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0); signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0); signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0); signal wbwrite,wbwritebig,rbwrite: std_logic; attribute keep : boolean; attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute keep of rbwdata : signal is true; attribute syn_keep of rbwdata : signal is true; attribute syn_preserve of rbwdata : signal is true; signal vcc: std_ulogic; signal sdox: ddrctrl_out_type; signal ce: std_logic; begin vcc <= '1'; gft0: if ft=0 generate ahbc : ddr2spax_ahb generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask, nosync => nosync, burstlen => burstlen, ahbbits => xahbw, revision => revision, ddrbits => ddrbits, regarea => 0) port map (ahb_rst, clk_ahb, ahbsi, ahbso, request, start_tog, response, wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, hwidth, FTFE_BEID_DDR2); ce <= '0'; end generate; gft1: if ft/=0 generate ftc: ft_ddr2spax_ahb generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask, nosync => nosync, burstlen => burstlen, ahbbits => xahbw, bufbits => xahbw+xahbw/2, ddrbits => ddrbits, hwidthen => hwidthen, devid => GAISLER_DDR2SP, revision => revision) port map (ahb_rst, clk_ahb, ahbsi, ahbso, ce, request, start_tog, response, wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, hwidth, '0', open, open, FTFE_BEID_DDR2); end generate; ddrc : ddr2spax_ddr generic map (ddrbits => ddrbits, pwron => pwron, MHz => MHz, TRFC => TRFC, col => col, Mbyte => Mbyte, readdly => readdly, odten => odten, octen => octen, dqsgating => dqsgating, nosync => nosync, eightbanks => eightbanks, dqsse => dqsse, burstlen => burstlen, chkbits => ft*ddrbits/2, bigmem => bigmem, raspipe => raspipe, hwidthen => hwidthen, phytech => phytech, hasdqvalid => ddr2phy_has_datavalid(phytech), rstdel => rstdel, phyptctrl => ddr2phy_ptctrl(phytech), scantest => scantest, ddr_syncrst => ddr_syncrst) port map (ddr_rst, clk_ddr, request, start_tog, response, sdi, sdox, wbraddr, wbrdata, rbwaddr, rbwdata, rbwrite, hwidth, '0', ddr_request_none, open, ahbsi.testen, ahbsi.testrst, ahbsi.testoen); sdoproc: process(sdox,ce) variable o: ddrctrl_out_type; begin o := sdox; o.ce := ce; sdo <= o; end process; wbuf: ddr2buf generic map (tech => memtech, wabits => wbuf_wabits, wdbits => wbuf_wdbits, rabits => wbuf_rabits_r, rdbits => wbuf_rdbits, sepclk => 1, wrfst => ramwt) port map ( rclk => clk_ddr, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0), dataout => wbrdata, wclk => clk_ahb, write => wbwrite, writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata); rbuf: ddr2buf generic map (tech => memtech, wabits => rbuf_wabits, wdbits => rbuf_wdbits, rabits => rbuf_rabits, rdbits => rbuf_rdbits, sepclk => 1, wrfst => ramwt) port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr, dataout => rbrdata, wclk => clk_ddr, write => rbwrite, writebig => '0', waddress => rbwaddr, datain => rbwdata); -- pragma translate_off bootmsg : report_version generic map ( msg1 => "ddr2spa: DDR2 controller rev " & tost(REVISION) & ", " & tost(ddrbits) & " bit width, " & tost(Mbyte) & " Mbyte, " & tost(MHz) & " MHz DDR clock"); -- pragma translate_on end;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/lib/techmap/atc18/pads_atc18.vhd
1
10099
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Package: atcpads_gen -- File: atcpads_gen.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: Atmel ATC18 pad wrappers ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; package atcpads is -- input pad component pc33d00z port (pad : in std_logic; cin : out std_logic); end component; -- input pad with pull-up component pc33d00uz port (pad : in std_logic; cin : out std_logic); end component; -- schmitt input pad component pc33d20z port (pad : in std_logic; cin : out std_logic); end component; -- schmitt input pad with pull-up component pt33d20uz port (pad : inout std_logic; cin : out std_logic); end component; -- output pads component pt33o01z port (i : in std_logic; pad : out std_logic); end component; component pt33o02z port (i : in std_logic; pad : out std_logic); end component; component pt33o04z port (i : in std_logic; pad : out std_logic); end component; component pt33o08z port (i : in std_logic; pad : out std_logic); end component; -- tri-state output pads component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component; component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component; component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component; component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component; -- tri-state output pads with pull-up component pt33t01uz port (i, oen : in std_logic; pad : out std_logic); end component; component pt33t02uz port (i, oen : in std_logic; pad : out std_logic); end component; component pt33t04uz port (i, oen : in std_logic; pad : out std_logic); end component; component pt33t08uz port (i, oen : in std_logic; pad : out std_logic); end component; -- bidirectional pads component pt33b01z port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pt33b02z port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pt33b08z port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pt33b04z port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; -- bidirectional pads with pull-up component pt33b01uz port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pt33b02uz port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pt33b08uz port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pt33b04uz port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; --PCI pads component pp33o01z port (i : in std_logic; pad : out std_logic); end component; component pp33b01z port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pp33t01z port (i, oen : in std_logic; pad : out std_logic); end component; end; library ieee; library techmap; use ieee.std_logic_1164.all; use techmap.gencomp.all; -- pragma translate_off library atc18; use atc18.pc33d00z; -- pragma translate_on entity atc18_inpad is generic (level : integer := 0; voltage : integer := 0); port (pad : in std_logic; o : out std_logic); end; architecture rtl of atc18_inpad is component pc33d00z port (pad : in std_logic; cin : out std_logic); end component; begin pci0 : if level = pci33 generate ip : pc33d00z port map (pad => pad, cin => o); end generate; gen0 : if level /= pci33 generate ip : pc33d00z port map (pad => pad, cin => o); end generate; end; library ieee; use ieee.std_logic_1164.all; library techmap; use techmap.gencomp.all; -- pragma translate_off library atc18; use atc18.pp33b01z; use atc18.pt33b01z; use atc18.pt33b02z; use atc18.pt33b08z; use atc18.pt33b04z; -- pragma translate_on entity atc18_iopad is generic (level : integer := 0; slew : integer := 0; voltage : integer := 0; strength : integer := 0); port (pad : inout std_logic; i, en : in std_logic; o : out std_logic); end ; architecture rtl of atc18_iopad is component pp33b01z port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pt33b01z port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pt33b02z port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pt33b08z port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; component pt33b04z port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end component; begin pci0 : if level = pci33 generate op : pp33b01z port map (i => i, oen => en, pad => pad, cin => o); end generate; gen0 : if level /= pci33 generate f1 : if (strength <= 4) generate op : pt33b01z port map (i => i, oen => en, pad => pad, cin => o); end generate; f2 : if (strength > 4) and (strength <= 8) generate op : pt33b02z port map (i => i, oen => en, pad => pad, cin => o); end generate; f3 : if (strength > 8) and (strength <= 16) generate op : pt33b04z port map (i => i, oen => en, pad => pad, cin => o); end generate; f4 : if (strength > 16) generate op : pt33b08z port map (i => i, oen => en, pad => pad, cin => o); end generate; end generate; end; library ieee; use ieee.std_logic_1164.all; library techmap; use techmap.gencomp.all; -- pragma translate_off library atc18; use atc18.pp33t01z; use atc18.pt33o01z; use atc18.pt33o02z; use atc18.pt33o04z; use atc18.pt33o08z; -- pragma translate_on entity atc18_outpad is generic (level : integer := 0; slew : integer := 0; voltage : integer := 0; strength : integer := 0); port (pad : out std_logic; i : in std_logic); end ; architecture rtl of atc18_outpad is component pp33t01z port (i, oen : in std_logic; pad : out std_logic); end component; component pt33o01z port (i : in std_logic; pad : out std_logic); end component; component pt33o02z port (i : in std_logic; pad : out std_logic); end component; component pt33o04z port (i : in std_logic; pad : out std_logic); end component; component pt33o08z port (i : in std_logic; pad : out std_logic); end component; signal gnd : std_logic; begin gnd <= '0'; pci0 : if level = pci33 generate op : pp33t01z port map (i => i, oen => gnd, pad => pad); end generate; gen0 : if level /= pci33 generate f4 : if (strength <= 4) generate op : pt33o01z port map (i => i, pad => pad); end generate; f8 : if (strength > 4) and (strength <= 8) generate op : pt33o02z port map (i => i, pad => pad); end generate; f16 : if (strength > 8) and (strength <= 16) generate op : pt33o04z port map (i => i, pad => pad); end generate; f32 : if (strength > 16) generate op : pt33o08z port map (i => i, pad => pad); end generate; end generate; end; library ieee; use ieee.std_logic_1164.all; library techmap; use techmap.gencomp.all; -- pragma translate_off library atc18; use atc18.pp33t01z; use atc18.pt33t01z; use atc18.pt33t02z; use atc18.pt33t04z; use atc18.pt33t08z; -- pragma translate_on entity atc18_toutpad is generic (level : integer := 0; slew : integer := 0; voltage : integer := 0; strength : integer := 0); port (pad : out std_logic; i, en : in std_logic); end ; architecture rtl of atc18_toutpad is component pp33t01z port (i, oen : in std_logic; pad : out std_logic); end component; component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component; component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component; component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component; component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component; begin pci0 : if level = pci33 generate op : pp33t01z port map (i => i, oen => en, pad => pad); end generate; gen0 : if level /= pci33 generate f4 : if (strength <= 4) generate op : pt33t01z port map (i => i, oen => en, pad => pad); end generate; f8 : if (strength > 4) and (strength <= 8) generate op : pt33t02z port map (i => i, oen => en, pad => pad); end generate; f16 : if (strength > 8) and (strength <= 16) generate op : pt33t04z port map (i => i, oen => en, pad => pad); end generate; f32 : if (strength > 16) generate op : pt33t08z port map (i => i, oen => en, pad => pad); end generate; end generate; end; library ieee; use ieee.std_logic_1164.all; entity atc18_clkpad is generic (level : integer := 0; voltage : integer := 0); port (pad : in std_logic; o : out std_logic); end; architecture rtl of atc18_clkpad is begin o <= pad; end;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/lib/techmap/saed32/clkgen_saed32.vhd
1
5004
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: clkgen_saed32 -- File: clkgen_saed32.vhd -- Author: Fredrik Ringhage - Aeroflex Gaisler AB -- Description: Clock generator for SAED32 ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library techmap; use techmap.gencomp.all; entity clkgen_saed32 is port ( clkin : in std_logic; clk : out std_logic; -- main clock clk2x : out std_logic; -- 2x clock sdclk : out std_logic; -- SDRAM clock pciclk : out std_logic; -- PCI clock cgi : in clkgen_in_type; cgo : out clkgen_out_type; clk4x : out std_logic; -- 4x clock clk1xu : out std_logic; -- unscaled 1X clock clk2xu : out std_logic); -- unscaled 2X clock end; architecture struct of clkgen_saed32 is component PLL port ( -- VDD25 : in std_logic; -- DVDD : inout std_logic; -- VSSA : in std_logic; -- AVDD : inout std_logic; REF_CLK : in std_logic; FB_CLK : in std_logic; FB_MODE : in std_logic; PLL_BYPASS : in std_logic; CLK_4X : out std_logic; CLK_2X : out std_logic; CLK_1X : out std_logic); end component; ----------------------------------------------------------------------------- -- attributes ----------------------------------------------------------------------------- attribute DONT_TOUCH : Boolean; attribute DONT_TOUCH of pll0 : label is True; begin pll0 : PLL port map ( -- VDD25 => '1', -- DVDD => open, -- VSSA => '0', -- AVDD => open, REF_CLK => clkin, FB_CLK => cgi.pllref, FB_MODE => cgi.pllctrl(1), PLL_BYPASS => cgi.pllctrl(0), CLK_4X => clk4x, CLK_2X => clk2x, CLK_1X => clk ); cgo.clklock <= '1'; sdclk <= '0'; pciclk <= '0'; cgo.pcilock <= '1'; clk1xu <= '0'; clk2xu <= '0'; end; library ieee; use ieee.std_logic_1164.all; -- pragma translate_off --library saed32; --use saed32.CGLPPSX4_LVT; -- pragma translate_on entity clkand_saed32 is port ( i : in std_ulogic; en : in std_ulogic; o : out std_ulogic; tsten : in std_ulogic := '0'); end clkand_saed32; architecture rtl of clkand_saed32 is component CGLPPSX4_LVT port ( GCLK : out std_ulogic; CLK : in std_ulogic; EN : in std_ulogic; SE : in std_ulogic ); end component; attribute DONT_TOUCH : Boolean; attribute DONT_TOUCH of gate : label is True; begin gate: CGLPPSX4_LVT port map (GCLK => o , CLK => i , EN => en, SE => tsten); end rtl; library ieee; use ieee.std_logic_1164.all; -- pragma translate_off --library saed32; --use saed32.MUX21X1_LVT; -- pragma translate_on entity clkmux_saed32 is port ( i0 : in std_ulogic; i1 : in std_ulogic; sel : in std_ulogic; o : out std_ulogic); end clkmux_saed32; architecture rtl of clkmux_saed32 is component MUX21X1_LVT port ( Y : out std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; S0 : in std_ulogic ); end component; attribute DONT_TOUCH : Boolean; attribute DONT_TOUCH of m0 : label is True; begin m0: MUX21X1_LVT port map (A1 => i0 , A2 => i1 , S0 => sel, Y => o); end rtl; library ieee; use ieee.std_logic_1164.all; -- pragma translate_off --library saed32; --use saed32.INVX4_LVT; -- pragma translate_on entity clkinv_saed32 is port ( i : in std_ulogic; o : out std_ulogic); end clkinv_saed32; architecture rtl of clkinv_saed32 is component INVX4_LVT port ( Y : out std_ulogic; A : in std_ulogic ); end component; attribute DONT_TOUCH : Boolean; attribute DONT_TOUCH of gate : label is True; begin gate: INVX4_LVT port map (A => i , Y => o); end rtl;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/designs/leon3mp/config.vhd
1
7709
----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench configuration -- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------ library techmap; use techmap.gencomp.all; package config is -- Technology and synthesis options constant CFG_FABTECH : integer := inferred; constant CFG_MEMTECH : integer := inferred; constant CFG_PADTECH : integer := inferred; constant CFG_NOASYNC : integer := 0; constant CFG_SCAN : integer := 0; -- Clock generator constant CFG_CLKTECH : integer := inferred; constant CFG_CLKMUL : integer := 2; constant CFG_CLKDIV : integer := 2; constant CFG_OCLKDIV : integer := 1; constant CFG_OCLKBDIV : integer := 0; constant CFG_OCLKCDIV : integer := 0; constant CFG_PCIDLL : integer := 0; constant CFG_PCISYSCLK: integer := 0; constant CFG_CLK_NOFB : integer := 0; -- LEON3 processor core constant CFG_LEON3 : integer := 1; constant CFG_NCPU : integer := (1); constant CFG_NWIN : integer := (8); constant CFG_V8 : integer := 0 + 4*0; constant CFG_MAC : integer := 0; constant CFG_BP : integer := 0; constant CFG_SVT : integer := 0; constant CFG_RSTADDR : integer := 16#00000#; constant CFG_LDDEL : integer := (1); constant CFG_NOTAG : integer := 0; constant CFG_NWP : integer := (0); constant CFG_PWD : integer := 0*2; constant CFG_FPU : integer := 0 + 16*0 + 32*0; constant CFG_GRFPUSH : integer := 0; constant CFG_ICEN : integer := 1; constant CFG_ISETS : integer := 1; constant CFG_ISETSZ : integer := 4; constant CFG_ILINE : integer := 8; constant CFG_IREPL : integer := 0; constant CFG_ILOCK : integer := 0; constant CFG_ILRAMEN : integer := 0; constant CFG_ILRAMADDR: integer := 16#8E#; constant CFG_ILRAMSZ : integer := 1; constant CFG_DCEN : integer := 1; constant CFG_DSETS : integer := 1; constant CFG_DSETSZ : integer := 4; constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; constant CFG_DSNOOP : integer := 0 + 0 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; constant CFG_DLRAMSZ : integer := 1; constant CFG_MMUEN : integer := 1; constant CFG_ITLBNUM : integer := 8; constant CFG_DTLBNUM : integer := 8; constant CFG_TLB_TYPE : integer := 0 + 1*2; constant CFG_TLB_REP : integer := 1; constant CFG_MMU_PAGE : integer := 0; constant CFG_DSU : integer := 0; constant CFG_ITBSZ : integer := 0; constant CFG_ATBSZ : integer := 0; constant CFG_LEON3FT_EN : integer := 0; constant CFG_IUFT_EN : integer := 0; constant CFG_FPUFT_EN : integer := 0; constant CFG_RF_ERRINJ : integer := 0; constant CFG_CACHE_FT_EN : integer := 0; constant CFG_CACHE_ERRINJ : integer := 0; constant CFG_LEON3_NETLIST: integer := 0; constant CFG_DISAS : integer := 0 + 0; constant CFG_PCLOW : integer := 2; -- AMBA settings constant CFG_DEFMST : integer := (0); constant CFG_RROBIN : integer := 1; constant CFG_SPLIT : integer := 0; constant CFG_FPNPEN : integer := 0; constant CFG_AHBIO : integer := 16#FFF#; constant CFG_APBADDR : integer := 16#800#; constant CFG_AHB_MON : integer := 0; constant CFG_AHB_MONERR : integer := 0; constant CFG_AHB_MONWAR : integer := 0; constant CFG_AHB_DTRACE : integer := 0; -- DSU UART constant CFG_AHB_UART : integer := 1; -- JTAG based DSU interface constant CFG_AHB_JTAG : integer := 0; -- Ethernet DSU constant CFG_DSU_ETH : integer := 0 + 0 + 0; constant CFG_ETH_BUF : integer := 1; constant CFG_ETH_IPM : integer := 16#C0A8#; constant CFG_ETH_IPL : integer := 16#0033#; constant CFG_ETH_ENM : integer := 16#020000#; constant CFG_ETH_ENL : integer := 16#000009#; -- PROM/SRAM controller constant CFG_SRCTRL : integer := 0; constant CFG_SRCTRL_PROMWS : integer := 0; constant CFG_SRCTRL_RAMWS : integer := 0; constant CFG_SRCTRL_IOWS : integer := 0; constant CFG_SRCTRL_RMW : integer := 0; constant CFG_SRCTRL_8BIT : integer := 0; constant CFG_SRCTRL_SRBANKS : integer := 1; constant CFG_SRCTRL_BANKSZ : integer := 0; constant CFG_SRCTRL_ROMASEL : integer := 0; -- LEON2 memory controller constant CFG_MCTRL_LEON2 : integer := 1; constant CFG_MCTRL_RAM8BIT : integer := 0; constant CFG_MCTRL_RAM16BIT : integer := 0; constant CFG_MCTRL_5CS : integer := 0; constant CFG_MCTRL_SDEN : integer := 1; constant CFG_MCTRL_SEPBUS : integer := 0; constant CFG_MCTRL_INVCLK : integer := 0; constant CFG_MCTRL_SD64 : integer := 0; constant CFG_MCTRL_PAGE : integer := 1 + 0; -- SDRAM controller constant CFG_SDCTRL : integer := 0; constant CFG_SDCTRL_INVCLK : integer := 0; constant CFG_SDCTRL_SD64 : integer := 0; constant CFG_SDCTRL_PAGE : integer := 0 + 0; -- AHB ROM constant CFG_AHBROMEN : integer := 0; constant CFG_AHBROPIP : integer := 0; constant CFG_AHBRODDR : integer := 16#000#; constant CFG_ROMADDR : integer := 16#000#; constant CFG_ROMMASK : integer := 16#E00# + 16#000#; -- AHB RAM constant CFG_AHBRAMEN : integer := 0; constant CFG_AHBRSZ : integer := 1; constant CFG_AHBRADDR : integer := 16#A00#; constant CFG_AHBRPIPE : integer := 0; -- Gaisler Ethernet core constant CFG_GRETH : integer := 0; constant CFG_GRETH1G : integer := 0; constant CFG_ETH_FIFO : integer := 8; -- CAN 2.0 interface constant CFG_CAN : integer := 0; constant CFG_CANIO : integer := 16#0#; constant CFG_CANIRQ : integer := 0; constant CFG_CANLOOP : integer := 0; constant CFG_CAN_SYNCRST : integer := 0; constant CFG_CANFT : integer := 0; -- PCI interface constant CFG_PCI : integer := 0; constant CFG_PCIVID : integer := 16#0#; constant CFG_PCIDID : integer := 16#0#; constant CFG_PCIDEPTH : integer := 8; constant CFG_PCI_MTF : integer := 1; -- PCI arbiter constant CFG_PCI_ARB : integer := 0; constant CFG_PCI_ARBAPB : integer := 0; constant CFG_PCI_ARB_NGNT : integer := 4; -- PCI trace buffer constant CFG_PCITBUFEN: integer := 0; constant CFG_PCITBUF : integer := 256; -- Spacewire interface constant CFG_SPW_EN : integer := 0; constant CFG_SPW_NUM : integer := 1; constant CFG_SPW_AHBFIFO : integer := 4; constant CFG_SPW_RXFIFO : integer := 16; constant CFG_SPW_RMAP : integer := 0; constant CFG_SPW_RMAPBUF : integer := 4; constant CFG_SPW_RMAPCRC : integer := 0; constant CFG_SPW_NETLIST : integer := 0; constant CFG_SPW_FT : integer := 0; constant CFG_SPW_GRSPW : integer := 2; constant CFG_SPW_RXUNAL : integer := 0; constant CFG_SPW_DMACHAN : integer := 1; constant CFG_SPW_PORTS : integer := 1; constant CFG_SPW_INPUT : integer := 2; constant CFG_SPW_OUTPUT : integer := 0; constant CFG_SPW_RTSAME : integer := 0; -- UART 1 constant CFG_UART1_ENABLE : integer := 1; constant CFG_UART1_FIFO : integer := 4; -- UART 2 constant CFG_UART2_ENABLE : integer := 0; constant CFG_UART2_FIFO : integer := 1; -- LEON3 interrupt controller constant CFG_IRQ3_ENABLE : integer := 1; constant CFG_IRQ3_NSEC : integer := 0; -- Modular timer constant CFG_GPT_ENABLE : integer := 1; constant CFG_GPT_NTIM : integer := (2); constant CFG_GPT_SW : integer := (8); constant CFG_GPT_TW : integer := (32); constant CFG_GPT_IRQ : integer := (8); constant CFG_GPT_SEPIRQ : integer := 1; constant CFG_GPT_WDOGEN : integer := 1; constant CFG_GPT_WDOG : integer := 16#FFFF#; -- GPIO port constant CFG_GRGPIO_ENABLE : integer := 1; constant CFG_GRGPIO_IMASK : integer := 16#0000#; constant CFG_GRGPIO_WIDTH : integer := (8); -- GRLIB debugging constant CFG_DUART : integer := 0; end;
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/lib/gaisler/pci/ptf/pt_pci_monitor.vhd
1
14767
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: pcitb_monitor -- File: pcitb_monitor.vhd -- Author: -- Description: PCI Monitor. ------------------------------------------------------------------------------ -- pragma translate_off library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.pt_pkg.all; library grlib; use grlib.stdlib.xorv; entity pt_pci_monitor is generic (dbglevel : integer := 1); port (pciin : in pci_type); end pt_pci_monitor; architecture tb of pt_pci_monitor is constant T_O : integer := 9; type pci_array_type is array(0 to 2) of pci_type; type reg_type is record pci : pci_array_type; frame_deass : boolean; m_wait_data_phase : boolean; t_wait_data_phase : boolean; stop_asserted : boolean; device_sel : boolean; first : boolean; current_master : integer; master_cnt : integer; irdy_cnt : integer; trdy_cnt : integer; end record; signal r,rin : reg_type; signal init_done : boolean := false; begin init : process begin if init_done = false then wait until pciin.syst.rst = '0'; wait until pciin.syst.rst = '1'; init_done <= true; else wait until pciin.syst.rst = '0'; init_done <= false; end if; end process; comb : process(pciin) variable i : integer; variable v : reg_type; begin v := r; v.pci(0) := pciin; v.pci(1) := r.pci(0); v.pci(2) := r.pci(1); if r.pci(0).ifc.frame = 'H' then v.frame_deass := false; elsif (r.pci(0).ifc.frame and not r.pci(1).ifc.frame) = '1' then v.frame_deass := true; end if; if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.m_wait_data_phase := false; elsif r.pci(0).ifc.irdy = '0' then v.m_wait_data_phase := true; end if; if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.t_wait_data_phase := false; elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.t_wait_data_phase := true; end if; if r.pci(0).ifc.frame = '0' and r.pci(1).ifc.frame = 'H' then for i in 0 to 20 loop if r.pci(0).arb.gnt(i) = '0' then v.current_master := i; end if; end loop; end if; if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy) = '0' then if (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '1' then v.master_cnt := r.master_cnt+1; else v.master_cnt := 0; end if; else v.master_cnt := 0; end if; if (r.pci(0).ifc.irdy and not r.pci(0).ifc.frame) = '1' then v.irdy_cnt := r.irdy_cnt+1; else v.irdy_cnt := 0; end if; if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then v.trdy_cnt := r.trdy_cnt+1; else v.trdy_cnt := 0; end if; if r.pci(0).ifc.devsel = '0' then v.device_sel := true; elsif (to_x01(r.pci(1).ifc.devsel) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then v.device_sel := false; end if; if r.pci(0).ifc.stop = '0' then v.stop_asserted := true; elsif r.pci(0).ifc.frame = '0' then v.stop_asserted := false; end if; if (r.pci(1).ifc.frame = 'H' and r.pci(0).ifc.frame = '0') then v.first := true; elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.first := false; end if; rin <= v; end process; clkprc : process(pciin.syst) begin if rising_edge(pciin.syst.clk) then r <= rin; if init_done then if (r.pci(0).ifc.frame = '0' and r.frame_deass = true) then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: FRAME# was reasserted during the same transaction."); end if; end if; if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy and not r.pci(1).ifc.frame) = '1' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: FRAME# was deasserted without IRDY# asserted."); end if; end if; if (r.m_wait_data_phase and r.device_sel) then if (r.pci(0).ifc.frame /= r.pci(1).ifc.frame) or (r.pci(0).ifc.irdy /= r.pci(1).ifc.irdy) then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Current master changed IRDY# or FRAME# before current data phase was completed."); end if; end if; end if; if ((r.pci(1).ifc.irdy and r.pci(1).ifc.frame and not r.pci(2).ifc.irdy) = '1' and r.stop_asserted = true) then if not ((r.pci(1).arb.req(r.current_master) and (r.pci(0).arb.req(r.current_master) or r.pci(2).arb.req(r.current_master))) = '1') then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Current master at slot %d did not release its REQ# when the bus returned to idle state.",r.current_master); end if; end if; end if; if (r.pci(0).ifc.stop and not r.pci(1).ifc.stop and not r.pci(0).ifc.frame) = '1' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Target did not keep STOP# asserted until FRAME# was deasserted."); end if; end if; if (r.pci(0).ifc.frame and r.pci(1).ifc.frame and not r.pci(0).ifc.stop and not r.pci(1).ifc.stop) = '1' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Target did not release STOP# after FRAME# was deasserted."); end if; end if; if r.t_wait_data_phase = true then if (r.pci(0).ifc.devsel /= r.pci(1).ifc.devsel) or (r.pci(0).ifc.trdy /= r.pci(1).ifc.trdy) or (r.pci(0).ifc.stop /= r.pci(1).ifc.stop) then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Current target changed DEVSEL#, STOP# or TRDY# before current data phase was completed."); end if; end if; end if; if (r.pci(0).ifc.frame and r.pci(0).ifc.stop and not r.pci(1).ifc.frame and not r.pci(1).ifc.stop) = '1' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Target did not keep STOP# asserted until the last data phase."); end if; end if; if (r.pci(2).ifc.frame and not (r.pci(2).ifc.trdy and r.pci(2).ifc.stop)) = '1' then if r.pci(1).ifc.irdy = '0' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Master kept IRDY# asserted after last data phase."); end if; end if; if r.pci(1).ifc.trdy = '0' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Target kept TRDY# asserted after last data phase."); end if; end if; if r.pci(1).ifc.stop = '0' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Target kept STOP# asserted after last data phase."); end if; end if; if r.pci(1).ifc.frame /= 'H' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Master did not tri-state FRAME# after turn-around cycle."); end if; end if; if r.pci(0).ifc.irdy /= 'H' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Master did not tri-state IRDY# after turn-around cycle."); end if; end if; if r.pci(0).ifc.trdy /= 'H' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Target did not tri-state TRDY# after turn-around cycle."); end if; end if; if r.pci(0).ifc.stop /= 'H' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Target did not tri-state STOP# after turn-around cycle."); end if; end if; end if; if (r.master_cnt > 16 and r.first = true) then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Target did not complete its initial data phase in 16 clkc."); end if; end if; if r.irdy_cnt > 8 then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Master did not complete its initial data phase in 8 clkc."); end if; end if; if (r.trdy_cnt > 8 and r.device_sel = true and r.first = false) then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Target did not complete a data phase in 8 clkc."); end if; end if; if not r.device_sel then if (r.pci(0).ifc.irdy and not r.pci(1).ifc.irdy) = '1' then if dbglevel > 0 then assert false report "**" severity note; printf("PCI_MONITOR: Master abort detected."); end if; end if; end if; if ((r.pci(1).ifc.irdy = 'H' and r.pci(1).ifc.frame = '0') or (r.pci(1).ifc.irdy or r.pci(1).ifc.trdy) = '0') then if r.pci(0).ad.par = 'Z' then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Current Master/Target is not generating parity during a data phase."); end if; elsif r.pci(0).ad.par /= xorv(r.pci(1).ad.ad & r.pci(1).ad.cbe) then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: Parity error detected."); end if; end if; end if; end if; end if; end process; adchk : process(pciin.ad) begin if init_done then -- for i in 0 to 31 loop -- if pciin.ad.ad(i) = 'X' then -- if dbglevel > 0 then -- assert false -- report " **" -- severity warning; -- printf("PCI_MONITOR: AD lines have multiple drivers."); -- end if; -- end if; -- end loop; for i in 0 to 3 loop if pciin.ad.cbe(i) = 'X' then if dbglevel > 0 then assert false report " **" severity warning; printf("PCI_MONITOR: CBE# lines have multiple drivers."); end if; end if; end loop; -- if pciin.ad.par = 'X' then -- if dbglevel > 0 then -- assert false -- report " **" -- severity warning; -- printf("PCI_MONITOR: PAR line has multiple drivers."); -- end if; -- end if; end if; end process; ifcchk : process(pciin.ifc) begin if init_done then if pciin.ifc.frame = 'X' then if dbglevel > 0 then assert false report " **" severity warning; printf("PCI_MONITOR: FRAME# line has multiple drivers."); end if; end if; if pciin.ifc.irdy = 'X' then if dbglevel > 0 then assert false report " **" severity warning; printf("PCI_MONITOR: IRDY# line has multiple drivers."); end if; end if; if pciin.ifc.trdy = 'X' then if dbglevel > 0 then assert false report " **" severity warning; printf("PCI_MONITOR: TRDY# line has multiple drivers."); end if; end if; if pciin.ifc.stop = 'X' then if dbglevel > 0 then assert false report " **" severity warning; printf("PCI_MONITOR: STOP# line has multiple drivers."); end if; end if; if pciin.ifc.devsel = 'X' then if dbglevel > 0 then assert false report " **" severity warning; printf("PCI_MONITOR: DEVSEL# line has multiple drivers."); end if; end if; end if; end process; arbchk : process(pciin.arb) variable gnt_set : boolean; begin gnt_set := false; if init_done then for i in 0 to 20 loop if pciin.arb.gnt(i) = '0' then if gnt_set then if dbglevel > 0 then assert false report "***PCI ERROR***" severity warning; printf("PCI_MONITOR: GNT# is asserted for more than one PCI master."); end if; else gnt_set := true; end if; end if; end loop; end if; end process; end; -- pragma translate_on
gpl-2.0
marco-c/leon-nexys2
grlib-gpl-1.3.4-b4140/lib/esa/pci/pciarb.vhd
3
5162
------------------------------------------------------------------------------ -- Entity: esa_pciarb -- File: esa_pciarb.vhd -- Author: Marko Isomaki -- Description: GRLIB wrapper for the ESA PCI arbiter ------------------------------------------------------------------------------ library ieee; library grlib; library gaisler; library esa; library techmap; use ieee.std_logic_1164.all; use grlib.stdlib.all; use grlib.amba.all; use grlib.devices.all; use techmap.gencomp.all; use techmap.netcomp.all; use esa.pci_arb_pkg.all; --pragma translate_off use std.textio.all; --pragma translate_on entity pciarb is generic( pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#FFF#; nb_agents : integer := 4; apb_en : integer := 1; netlist : integer := 0; tech : integer := axcel; reg : integer := 0); port( clk : in std_ulogic; rst_n : in std_ulogic; req_n : in std_logic_vector(0 to nb_agents-1); frame_n : in std_logic; gnt_n : out std_logic_vector(0 to nb_agents-1); pclk : in std_ulogic; prst_n : in std_ulogic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type ); end entity; architecture rtl of pciarb is component pci_arb is generic( NB_AGENTS : integer := 4; ARB_SIZE : integer := 2; APB_EN : integer := 1 ); port( clk : in clk_type; -- clock rst_n : in std_logic; -- async reset active low req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request frame_n : in std_logic; gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant pclk : in clk_type; -- APB clock prst_n : in std_logic; -- APB reset pbi : in EAPB_Slv_In_Type; -- APB inputs pbo : out EAPB_Slv_Out_Type -- APB outputs ); end component; component pci_arb_net is generic ( nb_agents : integer := 4; arb_size : integer := 2; apb_en : integer := 1; tech : integer := axcel ); port ( clk : in std_logic; -- clock rst_n : in std_logic; -- async reset active low req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request frame_n : in std_logic; gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant pclk : in std_logic; -- APB clock prst_n : in std_logic; -- APB reset pbi_psel : in std_ulogic; -- slave select pbi_penable: in std_ulogic; -- strobe pbi_paddr : in std_logic_vector(31 downto 0); -- address bus (byte) pbi_pwrite : in std_ulogic; -- write pbi_pwdata : in std_logic_vector(31 downto 0); -- write data bus pbo_prdata : out std_logic_vector(31 downto 0) -- read data bus ); end component; signal pbi : eapb_slv_in_type; signal pbo : eapb_slv_out_type; -- Added to latch frame and req in registers signal frame_n_int : std_logic; signal req_n_int : std_logic_vector(0 to NB_AGENTS-1); constant REVISION : integer := 0; constant pconfig : apb_config_type := ( 0 => ahb_device_reg ( VENDOR_ESA, ESA_PCIARB, 0, REVISION, 0), 1 => apb_iobar(paddr, pmask)); begin reg0 : if reg /= 0 generate process(clk) begin if rising_edge(clk) then frame_n_int <= frame_n; req_n_int <= req_n; end if; end process; end generate; noreg0 : if reg = 0 generate frame_n_int <= frame_n; req_n_int <= req_n; end generate; rtl0 : if netlist = 0 generate arb : pci_arb generic map( NB_AGENTS => nb_agents, ARB_SIZE => log2(nb_agents), APB_EN => apb_en) port map( clk => clk, rst_n => rst_n, req_n => req_n_int, frame_n => frame_n_int, gnt_n => gnt_n, pclk => pclk, prst_n => prst_n, pbi => pbi, pbo => pbo); end generate; net0 : if netlist /= 0 generate arb : pci_arb_net generic map( NB_AGENTS => nb_agents, ARB_SIZE => log2(nb_agents), APB_EN => apb_en, tech => tech) port map( clk => clk, rst_n => rst_n, req_n => req_n_int, frame_n => frame_n_int, gnt_n => gnt_n, pclk => pclk, prst_n => prst_n, pbi_psel => pbi.psel, pbi_penable => pbi.penable, pbi_paddr => pbi.paddr, pbi_pwrite => pbi.pwrite, pbi_pwdata => pbi.pwdata, pbo_prdata => pbo.prdata); end generate; apb_en1: if apb_en /= 0 generate apbo.prdata <= pbo.prdata; apbo.pindex <= pindex; apbo.pconfig <= pconfig; apbo.pirq <= (others => '0'); end generate apb_en1; pbi.psel <= apbi.psel(pindex); pbi.penable <= apbi.penable; pbi.paddr <= apbi.paddr; pbi.pwrite <= apbi.pwrite; pbi.pwdata <= apbi.pwdata; -- boot message -- pragma translate_off bootmsg : report_version generic map ("pciarb" & tost(pindex) & ": PCI arbiter, " & tost(nb_agents) & " masters"); -- pragma translate_on end architecture;
gpl-2.0
KimSJ/HDLC_chip
arduinointerface.vhd
1
4336
-- arduinointerface.vhd -- -- takes 8-bit parallel data and sends frame -- Frame ends when data value is written with "rxLast" set. -- connect data to low 4 bits of port -- connect strb to b4 of port (configured as output) -- connect RnW to b5 of port (configured as output) -- to read this peripheral: -- (assuming strb is left high between accesses) -- set port low bits to input -- set RmW, strb to 1, 0 (10 = command "read low-nibble") -- read the value of b3..b0 -- set strb 1 (11 = command "read high-nibble) -- read the value of b7..b4 in the low bits of the data you read. -- for multi-byte reads, repeat last four steps -- Note: always read the low nibble first, because the high nibble is latched at the same time -- make sure you wait at least three cycles between writes and reads: -- OUT <port>, <regA> -- ORI <regA>, 0x10 // take the opportunity to set up next out value -- NOP -- IN <regB>, <port> // read the low nibble -- OUT <port>, <regA> // set up hi nibble read -- ANDI <regB>, 0x0F // extract low nibble -- ANDI <regA>, 0xEF // take the opportunity to set up next out value -- IN <regC>, <port> // read the high nibble -- ANDI <regC>, 0x0F -- SWAP -- OR <RegC>, <RegB> // build the byte -- <store it> -- <check for more data available, then loop> -- this code should be able to input about one byte/microsecond with 16MHz processor. -- to write this peripheral: -- (assuming strb is left high between accesses) -- set RnW to 0 (strb no change, so no write yet; output buffers now disabled) -- set port low bits to output -- write the lo-nibble value, with b5, b4 = 00 -- write the hi-nibble value, with b5, b4 = 01 -- for multi-byte writes, repeat last two steps library IEEE; use IEEE.STD_LOGIC_1164.All; use IEEE.NUMERIC_STD.all; -- debug libraries use std.textio.all; use ieee.std_logic_textio.all; entity arduinointerface is port ( -- arduino pins data: inout Std_Logic_Vector (3 downto 0); strb: in Std_Logic; RnW: in Std_Logic; clk: in Std_Logic; rst: in Std_Logic; -- io pins rd, wr: out Std_Logic := '0'; q: out Std_Logic_Vector (7 downto 0); i: in Std_Logic_Vector (7 downto 0) ); end arduinointerface; architecture behavioural of arduinointerface is signal RnWin : Std_Logic_Vector (2 downto 0); -- metastability chain -> shifting down (low bit is "last" value) signal strbin : Std_Logic_Vector (2 downto 0); -- metastability chain -> shifting down (low bit is "last" value) signal dout : Std_Logic_Vector (3 downto 0); -- latch for high nibble when low nibble is read begin process (clk, strb, RnW, rst) begin if rst = '1' then wr <= '0'; rd <= '0'; RnWin <= (others => '0'); strbin <= (others => '0'); q <= (others => '0'); dout <= (others => '0'); elsif rising_edge(clk) then -- strobes output for use by peripheral, indicating a read or write has taken place. wr <= (strbin(1) and not strbin(0)) and not RnWin(1); -- positive-going write pulse edge generated when second nibble written rd <= (strbin(1) and not strbin(0)) and RnWin(1); -- poistive-going read pulse generated when host requests second nibble -- shift the metastability chains down RnWin <= RnW & RnWin (RnWin'length-1 downto 1); strbin <= strb & strbin (strbin'length-1 downto 1); -- deal with strobe events if strbin(1) /= strbin(0) then -- we have a strobe event if RnWin(1) = '0' then -- we are being written if strbin(1) = '1' then -- latch the high nibble q(7 downto 4) <= data; else -- latch the low nibble q(3 downto 0) <= data; end if; else if strbin(1) = '0' then -- we're reading the low nibble, so... dout <= i(7 downto 4); -- ... latch the high nibble at the same time end if; end if; end if; end if; end process; tristate : process (RnWin(1), strbin(1), data) -- Behavioral representation of tri-states. begin -- pattern from http://www.altera.co.uk/support/examples/vhdl/v_bidir.html if RnWin(1) = '1' then -- we are being read if strbin(1) = '0' then -- read the low nibble data <= i(3 downto 0); else -- read the high nibble data <= dout; end if; else -- we are being written data <= "ZZZZ"; end if; end process; end behavioural;
gpl-3.0
jobisoft/jTDC
modules/VFB6/bus_interface_vfb6.vhdl
1
4671
------------------------------------------------------------------------- ---- ---- ---- Engineer: A. Winnebeck ---- ---- Company: ELB-Elektroniklaboratorien Bonn UG ---- ---- (haftungsbeschränkt) ---- ---- ---- ------------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2015 ELB ---- ---- ---- ---- This program is free software; you can redistribute it and/or ---- ---- modify it under the terms of the GNU General Public License as ---- ---- published by the Free Software Foundation; either version 3 of ---- ---- the License, or (at your option) any later version. ---- ---- ---- ---- This program is distributed in the hope that it will be useful, ---- ---- but WITHOUT ANY WARRANTY; without even the implied warranty of ---- ---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ---- ---- GNU General Public License for more details. ---- ---- ---- ---- You should have received a copy of the GNU General Public ---- ---- License along with this program; if not, see ---- ---- <http://www.gnu.org/licenses>. ---- ---- ---- ------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity bus_interface_vfb6 is Port ( board_databus : inout STD_LOGIC_VECTOR(31 downto 0); board_address : in STD_LOGIC_VECTOR(15 downto 0); board_read : in STD_LOGIC; board_write : in STD_LOGIC; board_dtack : out STD_LOGIC := '0'; CLK : in STD_LOGIC; statusregister : in STD_LOGIC_VECTOR(31 downto 0); internal_databus : inout STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); internal_address : out STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); internal_read : out STD_LOGIC := '0'; internal_write : out STD_LOGIC := '0'); end bus_interface_vfb6; architecture Behavioral of bus_interface_vfb6 is ---- Signals for VME-Interface ---- signal test_register : STD_LOGIC_VECTOR(31 downto 0):=X"DEADBEEF"; signal le_write_int : STD_LOGIC; signal board_read_sync : STD_LOGIC; signal board_read_pre_sync : STD_LOGIC; ---- Component declaration ---- COMPONENT leading_edge_clipper PORT( input : IN std_logic; CLK : IN std_logic; output : OUT std_logic ); END COMPONENT; begin ---- Instantiation of Pulseclipper ---- le_w_int: leading_edge_clipper PORT MAP( input => board_write, CLK => CLK, output => le_write_int); ---- Sync board read synchronize_read_int: Process (CLK) is begin if rising_edge(CLK) then board_read_pre_sync <= board_read; board_read_sync <= board_read_pre_sync; end if; end process; process (CLK) is begin if rising_edge(CLK) then if (le_write_int = '1') then case board_address is when X"0014" => test_register <= board_databus; when others => NULL; end case; elsif (board_read_sync = '1') then case board_address is when X"0010" => board_databus <= statusregister; when X"0014" => board_databus <= test_register; when others => board_databus <= (others => 'Z'); end case; else board_databus <= (others=>'Z'); end if; end if; end process; dtack_process: process (CLK) is begin if rising_edge(CLK) then -- generate Data Acknowlege, if Module is addressed, but CPLD registers are not addressed if ((board_read_sync = '1' OR board_write = '1') AND (NOT(board_address = X"0000" OR board_address = X"0004" OR board_address = X"0008")))then board_dtack <= '1'; else board_dtack <= '0'; end if; end if; end process; internal_write <= le_write_int; internal_read <= board_read_sync; internal_address <= board_address(15 downto 2) & "00"; internal_databus <= board_databus; end Behavioral;
gpl-3.0
SWORDfpga/ComputerOrganizationDesign
labs/lab07/lab07/ipcore_dir/ROM_D/simulation/ROM_D_tb_pkg.vhd
8
5838
-------------------------------------------------------------------------------- -- -- DIST MEM GEN Core - Testbench Package -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: ROM_D_tb_pkg.vhd -- -- Description: -- DMG Testbench Package files -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; PACKAGE ROM_D_TB_PKG IS FUNCTION DIVROUNDUP ( DATA_VALUE : INTEGER; DIVISOR : INTEGER) RETURN INTEGER; ------------------------ FUNCTION IF_THEN_ELSE ( CONDITION : BOOLEAN; TRUE_CASE : STD_LOGIC_VECTOR; FALSE_CASE : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; ------------------------ FUNCTION IF_THEN_ELSE ( CONDITION : BOOLEAN; TRUE_CASE : STRING; FALSE_CASE :STRING) RETURN STRING; ------------------------ FUNCTION IF_THEN_ELSE ( CONDITION : BOOLEAN; TRUE_CASE : STD_LOGIC; FALSE_CASE :STD_LOGIC) RETURN STD_LOGIC; ------------------------ FUNCTION IF_THEN_ELSE ( CONDITION : BOOLEAN; TRUE_CASE : INTEGER; FALSE_CASE : INTEGER) RETURN INTEGER; ------------------------ FUNCTION LOG2ROUNDUP ( DATA_VALUE : INTEGER) RETURN INTEGER; END ROM_D_TB_PKG; PACKAGE BODY ROM_D_TB_PKG IS FUNCTION DIVROUNDUP ( DATA_VALUE : INTEGER; DIVISOR : INTEGER) RETURN INTEGER IS VARIABLE DIV : INTEGER; BEGIN DIV := DATA_VALUE/DIVISOR; IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN DIV := DIV+1; END IF; RETURN DIV; END DIVROUNDUP; --------------------------------- FUNCTION IF_THEN_ELSE ( CONDITION : BOOLEAN; TRUE_CASE : STD_LOGIC_VECTOR; FALSE_CASE : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS BEGIN IF NOT CONDITION THEN RETURN FALSE_CASE; ELSE RETURN TRUE_CASE; END IF; END IF_THEN_ELSE; --------------------------------- FUNCTION IF_THEN_ELSE ( CONDITION : BOOLEAN; TRUE_CASE : STD_LOGIC; FALSE_CASE : STD_LOGIC) RETURN STD_LOGIC IS BEGIN IF NOT CONDITION THEN RETURN FALSE_CASE; ELSE RETURN TRUE_CASE; END IF; END IF_THEN_ELSE; --------------------------------- FUNCTION IF_THEN_ELSE ( CONDITION : BOOLEAN; TRUE_CASE : INTEGER; FALSE_CASE : INTEGER) RETURN INTEGER IS VARIABLE RETVAL : INTEGER := 0; BEGIN IF CONDITION=FALSE THEN RETVAL:=FALSE_CASE; ELSE RETVAL:=TRUE_CASE; END IF; RETURN RETVAL; END IF_THEN_ELSE; --------------------------------- FUNCTION IF_THEN_ELSE ( CONDITION : BOOLEAN; TRUE_CASE : STRING; FALSE_CASE : STRING) RETURN STRING IS BEGIN IF NOT CONDITION THEN RETURN FALSE_CASE; ELSE RETURN TRUE_CASE; END IF; END IF_THEN_ELSE; ------------------------------- FUNCTION LOG2ROUNDUP ( DATA_VALUE : INTEGER) RETURN INTEGER IS VARIABLE WIDTH : INTEGER := 0; VARIABLE CNT : INTEGER := 1; BEGIN IF (DATA_VALUE <= 1) THEN WIDTH := 1; ELSE WHILE (CNT < DATA_VALUE) LOOP WIDTH := WIDTH + 1; CNT := CNT *2; END LOOP; END IF; RETURN WIDTH; END LOG2ROUNDUP; END ROM_D_TB_PKG;
gpl-3.0
malkolmalburquenque/PipelinedProcessor
VHDL/signextender_tb.vhd
1
1502
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY signextender_tb IS END signextender_tb; ARCHITECTURE Behavioral OF signextender_tb IS COMPONENT signextender IS PORT ( clock: IN STD_LOGIC; immediate_in: IN STD_LOGIC_VECTOR (15 DOWNTO 0); immediate_out: OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); END COMPONENT; SIGNAL clock: STD_LOGIC := '0'; CONSTANT clock_period : time := 1 ns; SIGNAL immediate_in: STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL immediate_out: STD_LOGIC_VECTOR (31 DOWNTO 0); BEGIN -- map component to/=> signals sx: signextender PORT MAP( clock => clock, immediate_in => immediate_in, immediate_out => immediate_out ); clock_process : PROCESS BEGIN clock <= '1'; wait for clock_period/2; clock <= '0'; wait for clock_period/2; END PROCESS; test_process : PROCESS BEGIN wait for clock_period; -- test 1 immediate_in <= "0000000000000000"; wait for clock_period; -- test 2 immediate_in <= "1111111111111111"; wait for clock_period; -- test 3 immediate_in <= "1111111111111001"; wait for clock_period; -- test 4 immediate_in <= "0000111111111111"; wait for clock_period; -- test 5 immediate_in <= "1010101010101010"; WAIT; END PROCESS; END Behavioral;
gpl-3.0
malkolmalburquenque/PipelinedProcessor
VHDL/mux_2to1.vhd
1
389
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux_2to1 is Port ( SEL : in STD_LOGIC; A : in STD_LOGIC_VECTOR (31 downto 0); B : in STD_LOGIC_VECTOR (31 downto 0); X : out STD_LOGIC_VECTOR (31 downto 0)); end mux_2to1; architecture Behavioral of mux_2to1 is begin X <= A when (SEL = '1') else B; end Behavioral;
gpl-3.0
malkolmalburquenque/PipelinedProcessor
VHDL/cpuPipeline_tb.vhd
1
1146
library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity cpuPipeline_tb is end cpuPipeline_tb; architecture cpuPipeline_tb_arch of cpuPipeline_tb is component cpuPipeline is port ( clk : in std_logic; reset : in std_logic; four : INTEGER; writeToRegisterFile : in std_logic; writeToMemoryFile : in std_logic ); end component; constant clk_period : time := 1 ns; signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal fourInt : INTEGER := 4; signal writeToRegisterFile : std_logic := '0'; signal writeToMemoryFile : std_logic := '0'; begin pipeline : cpuPipeline port map( clk => clk, reset => rst, four => fourInt, writeToMemoryFile => writeToRegisterFile, writeToRegisterFile => writeToMemoryFile ); clk_process : process BEGIN clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; test_process : process BEGIN wait for clk_period; report "STARTING SIMULATION \n"; wait for 10000* clk_period; writeToRegisterFile <= '1'; writeToMemoryFile <= '1'; wait; end process; end cpuPipeline_tb_arch;
gpl-3.0
LarbiBekka34/miniproject-vhdl
Kogge_Stone_Adder/carry_op.vhd
1
1775
------------------------------------------------------- --Copyright 2014 Larbi Bekka, Walid Belhadj, Oussama Hemchi ------------------------------------------------------- ------------------------------------------------------- --This file is part of 64-bit Kogge-Stone adder. --64-bit Kogge-Stone adder is free hardware design: you can redistribute it and/or modify --it under the terms of the GNU General Public License as published by --the Free Software Foundation, either version 3 of the License, or --(at your option) any later version. --64-bit Kogge-Stone adder is distributed in the hope that it will be useful, --but WITHOUT ANY WARRANTY; without even the implied warranty of --MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --GNU General Public License for more details. --You should have received a copy of the GNU General Public License --along with 64-bit Kogge-Stone adder. If not, see <http://www.gnu.org/licenses/>. -------------------------------------------------------- ------------------------------------------------------- -- Project : Computer arithmetic, fast adders (3rd year mini project) -- Author : Larbi Bekka, Walid Belhadj, Oussama Hemchi -- Date : 10-05-2014 -- File : carry_op.vhd -- Design : 64-bit Kogge-Stone adder ------------------------------------------------------ -- Description : a carry operator unit ------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY carry_op IS PORT( g1 : IN std_logic; p1 : IN std_logic; g2 : IN std_logic; p2 : IN std_logic; go : OUT std_logic; po : OUT std_logic ); END carry_op; ARCHITECTURE arch OF carry_op IS BEGIN go <= g2 OR (g1 AND p2); po <= P2 AND p1; END arch;
gpl-3.0
timofonic/1541UltimateII
fpga/6502/vhdl_sim/tb_proc_control.vhd
5
7221
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; library work; use work.pkg_6502_defs.all; use work.pkg_6502_decode.all; use work.pkg_6502_opcodes.all; entity tb_proc_control is end tb_proc_control; architecture tb of tb_proc_control is signal clock : std_logic := '0'; signal clock_en : std_logic; signal reset : std_logic; signal inst : std_logic_vector(7 downto 0); signal force_sync : std_logic; signal index_carry : std_logic := '1'; signal pc_carry : std_logic := '1'; signal branch_taken : boolean := true; signal latch_dreg : std_logic; signal reg_update : std_logic; signal copy_d2p : std_logic; signal dummy_cycle : std_logic; signal sync : std_logic; signal rwn : std_logic; signal a_mux : t_amux; signal pc_oper : t_pc_oper; signal s_oper : t_sp_oper; signal adl_oper : t_adl_oper; signal adh_oper : t_adh_oper; signal dout_mux : t_dout_mux; signal opcode : string(1 to 13); signal s_is_absolute : boolean; signal s_is_abs_jump : boolean; signal s_is_immediate : boolean; signal s_is_implied : boolean; signal s_is_stack : boolean; signal s_is_push : boolean; signal s_is_zeropage : boolean; signal s_is_indirect : boolean; signal s_is_relative : boolean; signal s_is_load : boolean; signal s_is_store : boolean; signal s_is_rmw : boolean; signal s_is_jump : boolean; signal s_is_postindexed : boolean; signal s_store_a_from_alu : boolean; signal s_load_x : boolean; signal s_load_y : boolean; signal i_reg : std_logic_vector(7 downto 0); signal adh, adl : std_logic_vector(7 downto 0) := X"00"; signal pch, pcl : std_logic_vector(7 downto 0) := X"11"; signal addr : std_logic_vector(15 downto 0); signal sp : std_logic_vector(7 downto 0) := X"FF"; signal dreg : std_logic_vector(7 downto 0) := X"FF"; signal databus : std_logic_vector(7 downto 0); signal dout : std_logic_vector(7 downto 0); begin s_is_absolute <= is_absolute(i_reg); s_is_abs_jump <= is_abs_jump(i_reg); s_is_immediate <= is_immediate(i_reg); s_is_implied <= is_implied(i_reg); s_is_stack <= is_stack(i_reg); s_is_push <= is_push(i_reg); s_is_zeropage <= is_zeropage(i_reg); s_is_indirect <= is_indirect(i_reg); s_is_relative <= is_relative(i_reg); s_is_load <= is_load(i_reg); s_is_store <= is_store(i_reg); s_is_rmw <= is_rmw(i_reg); s_is_jump <= is_jump(i_reg); s_is_postindexed <= is_postindexed(i_reg); s_store_a_from_alu <= store_a_from_alu(i_reg); s_load_x <= load_x(i_reg); s_load_y <= load_y(i_reg); mut: entity work.proc_control port map ( clock => clock, clock_en => clock_en, reset => reset, interrupt => '0', i_reg => i_reg, index_carry => index_carry, pc_carry => pc_carry, branch_taken => branch_taken, sync => sync, dummy_cycle => dummy_cycle, latch_dreg => latch_dreg, reg_update => reg_update, copy_d2p => copy_d2p, rwn => rwn, a_mux => a_mux, dout_mux => dout_mux, pc_oper => pc_oper, s_oper => s_oper, adl_oper => adl_oper, adh_oper => adh_oper ); clock <= not clock after 50 ns; clock_en <= '1'; reset <= '1', '0' after 500 ns; test: process begin inst <= X"00"; force_sync <= '0'; wait until reset='0'; for i in 0 to 255 loop inst <= conv_std_logic_vector(i, 8); wait until sync='1' for 2 us; if sync='0' then wait until clock='1'; force_sync <= '1'; wait until clock='1'; force_sync <= '0'; else wait until sync='0'; end if; end loop; wait; end process; opcode <= opcode_array(conv_integer(i_reg)); process(clock) begin if rising_edge(clock) and clock_en='1' then if latch_dreg='1' then dreg <= databus; end if; if sync='1' or force_sync='1' then i_reg <= databus; end if; case pc_oper is when increment => if pcl = X"FF" then pch <= pch + 1; end if; pcl <= pcl + 1; when copy => pcl <= dreg; pch <= databus; when from_alu => pcl <= pcl + 40; when others => null; end case; case adl_oper is when increment => adl <= adl + 1; when add_idx => adl <= adl + 5; when load_bus => adl <= databus; when copy_dreg => adl <= dreg; when others => null; end case; case adh_oper is when increment => adh <= adh + 1; when clear => adh <= (others => '0'); when load_bus => adh <= databus; when others => null; end case; case s_oper is when increment => sp <= sp + 1; when decrement => sp <= sp - 1; when others => null; end case; end if; end process; with a_mux select addr <= X"FFFF" when 0, adh & adl when 1, X"01" & sp when 2, pch & pcl when 3; with dout_mux select dout <= dreg when reg_d, X"11" when reg_axy, X"22" when reg_flags, pcl when reg_pcl, pch when reg_pch, X"33" when shift_res, X"FF" when others; databus <= inst when (sync='1' or force_sync='1') else X"D" & addr(3 downto 0); end tb;
gpl-3.0
timofonic/1541UltimateII
fpga/io/mem_ctrl/vhdl_source/sram_8bit32.vhd
5
4391
------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 - Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Asynchronous SRAM Controller ------------------------------------------------------------------------------- -- File : sram_8bit32.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This module implements a simple, single access sram controller, -- using an external 32-bit sram, and an internal 8 bit bus. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity sram_8bit32 is generic ( tag_width : integer := 2; SRAM_WR_ASU : integer := 0; SRAM_WR_Pulse : integer := 1; -- 2 cycles in total SRAM_WR_Hold : integer := 1; SRAM_RD_ASU : integer := 0; SRAM_RD_Pulse : integer := 1; SRAM_RD_Hold : integer := 1 ); -- recovery time (bus turnaround) port ( clock : in std_logic := '0'; reset : in std_logic := '0'; req : in std_logic; req_tag : in std_logic_vector(1 to tag_width) := (others => '0'); readwriten : in std_logic; address : in std_logic_vector(19 downto 0); rack : out std_logic; dack : out std_logic; rack_tag : out std_logic_vector(1 to tag_width); dack_tag : out std_logic_vector(1 to tag_width); wdata : in std_logic_vector(7 downto 0); rdata : out std_logic_vector(7 downto 0); -- SRAM_A : out std_logic_vector(17 downto 0); SRAM_OEn : out std_logic; SRAM_WEn : out std_logic; SRAM_CSn : out std_logic; SRAM_D : inout std_logic_vector(31 downto 0) := (others => 'Z'); SRAM_BEn : out std_logic_vector(3 downto 0) ); end sram_8bit32; architecture mux of sram_8bit32 is signal rdata_i : std_logic_vector(31 downto 0); signal wdata_i : std_logic_vector(31 downto 0); signal wdata_mask : std_logic_vector(3 downto 0); signal a_low : std_logic_vector(1 downto 0); signal rack_i : std_logic; signal dack_i : std_logic; begin ctrl: entity work.simple_sram generic map ( SRAM_Byte_Lanes => 4, SRAM_Data_Width => 32, SRAM_WR_ASU => SRAM_WR_ASU, SRAM_WR_Pulse => SRAM_WR_Pulse, SRAM_WR_Hold => SRAM_WR_Hold, SRAM_RD_ASU => SRAM_RD_ASU, SRAM_RD_Pulse => SRAM_RD_Pulse, SRAM_RD_Hold => SRAM_RD_Hold, SRAM_A_Width => 18 ) port map ( clock => clock, reset => reset, req => req, req_tag => req_tag, readwriten => readwriten, address => address(19 downto 2), rack => rack_i, dack => dack_i, rack_tag => rack_tag, dack_tag => dack_tag, wdata => wdata_i, wdata_mask => wdata_mask, rdata => rdata_i, -- SRAM_A => SRAM_A, SRAM_OEn => SRAM_OEn, SRAM_WEn => SRAM_WEn, SRAM_CSn => SRAM_CSn, SRAM_D => SRAM_D, SRAM_BEn => SRAM_BEn ); wdata_i <= wdata & wdata & wdata & wdata; -- muxing: process(clock) variable hold : std_logic; begin if rising_edge(clock) then if rack_i='1' then hold := '1'; end if; if dack_i='1' then hold := '0'; end if; if hold='0' then a_low <= address(1 downto 0); end if; if reset='1' then hold := '0'; a_low <= "00"; end if; end if; end process; process(address) begin case address(1 downto 0) is when "00" => wdata_mask <= "0001"; when "01" => wdata_mask <= "0010"; when "10" => wdata_mask <= "0100"; when "11" => wdata_mask <= "1000"; when others => wdata_mask <= "0000"; end case; end process; with a_low select rdata <= rdata_i(07 downto 00) when "00", rdata_i(15 downto 08) when "01", rdata_i(23 downto 16) when "10", rdata_i(31 downto 24) when others; dack <= dack_i; rack <= rack_i; end mux;
gpl-3.0
timofonic/1541UltimateII
target/simulation/vhdl_bfm/dram_model_8.vhd
5
6461
------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 - Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : DRAM model ------------------------------------------------------------------------------- -- File : dram_model_8.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This simple DRAM model uses the flat memory model package. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tl_flat_memory_model_pkg.all; use work.tl_string_util_pkg.all; entity dram_model_8 is generic ( g_given_name : string; g_cas_latency : positive := 2; g_burst_len_r : positive := 1; g_burst_len_w : positive := 1; g_column_bits : positive := 10; g_row_bits : positive := 13; g_bank_bits : positive := 2 ); port ( CLK : in std_logic; CKE : in std_logic; A : in std_logic_vector(g_row_bits-1 downto 0); BA : in std_logic_vector(g_bank_bits-1 downto 0); CSn : in std_logic; RASn : in std_logic; CASn : in std_logic; WEn : in std_logic; DQM : in std_logic; DQ : inout std_logic_vector(7 downto 0) ); end dram_model_8; architecture bfm of dram_model_8 is shared variable this : h_mem_object; signal bound : boolean := false; signal command : std_logic_vector(2 downto 0); constant c_banks : integer := 2 ** g_bank_bits; type t_row_array is array(0 to c_banks-1) of std_logic_vector(g_row_bits-1 downto 0); signal bank_rows : t_row_array; signal bank : integer; type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0); signal r_queue : t_byte_array(0 to g_cas_latency + g_burst_len_r) := (others => (others => 'Z')); -- constant c_col : integer := 0; -- constant c_bank : integer := g_column_bits; -- constant c_row : integer := g_column_bits + g_bank_bits; begin bind: process begin register_mem_model(dram_model_8'path_name, g_given_name, this); bound <= true; wait; end process; command <= WEn & CASn & RASn; bank <= to_integer(unsigned(BA)); DQ <= transport r_queue(0) after 6 ns; process(CLK) variable raddr : std_logic_vector(31 downto 0) := (others => '0'); variable waddr : std_logic_vector(31 downto 0) := (others => '0'); variable more_writes : integer := 0; function map_address(bank_bits : std_logic_vector(g_bank_bits-1 downto 0); row_bits : std_logic_vector(g_row_bits-1 downto 0); col_bits : std_logic_vector(g_column_bits-1 downto 0) ) return std_logic_vector is variable ret : std_logic_vector(31 downto 0) := (others => '0'); begin -- mapping used in v5_sdr --addr_bank <= address_fifo(3 downto 2); --addr_row <= address_fifo(24 downto 12); --addr_column <= address_fifo(11 downto 4) & address_fifo(1 downto 0); ret(g_bank_bits+1 downto 2) := bank_bits; ret(1 downto 0) := col_bits(1 downto 0); ret(g_column_bits+g_bank_bits-1 downto g_bank_bits+2) := col_bits(g_column_bits-1 downto 2); ret(g_bank_bits+g_column_bits+g_row_bits-1 downto g_bank_bits+g_column_bits) := row_bits; return ret; end function; begin if rising_edge(CLK) then if bound and CKE='1' then r_queue <= r_queue(1 to r_queue'high) & ("ZZZZZZZZ"); if more_writes > 0 then waddr := std_logic_vector(unsigned(waddr) + 1); if to_integer(unsigned(waddr)) mod g_burst_len_w = 0 then waddr := std_logic_vector(unsigned(waddr) - g_burst_len_w); end if; if DQM='0' then write_memory_8(this, waddr, DQ); end if; more_writes := more_writes - 1; end if; if CSn='0' then case command is when "110" => -- RAS, register bank address bank_rows(bank) <= A(g_row_bits-1 downto 0); when "101" => -- CAS, start read burst raddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0)); --raddr(c_bank+g_bank_bits-1 downto c_bank) := BA; --raddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank); --raddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0); --report hstr(BA) & " " & hstr(bank_rows(bank)) & " " & hstr(A) & ": " & hstr(raddr); for i in 0 to g_burst_len_r-1 loop r_queue(g_cas_latency-1 + i) <= read_memory_8(this, raddr); raddr := std_logic_vector(unsigned(raddr) + 1); if to_integer(unsigned(raddr)) mod g_burst_len_r = 0 then raddr := std_logic_vector(unsigned(raddr) - g_burst_len_r); end if; end loop; when "001" => -- CAS & WE, start write burst waddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0)); --waddr(c_bank+g_bank_bits-1 downto c_bank) := BA; --waddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank); --waddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0); more_writes := g_burst_len_w - 1; if DQM='0' then write_memory_8(this, waddr, DQ); end if; when others => null; end case; end if; end if; end if; end process; end bfm;
gpl-3.0
timofonic/1541UltimateII
target/simulation/packages/vhdl_source/tl_flat_memory_model_pkg.vhd
4
25706
------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2004 Gideon's Logic Architectures' -- ------------------------------------------------------------------------------- -- Title : Flat Memory Model package -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This package implements a memory model that can be used -- as or in bus functional models. It implements different -- banks, such that only one package is needed for all memories -- in the whole project. These banks are dynamic, just like -- the contents of the memories. Internally, this memory model -- is 32-bit, but can be accessed by means of functions and -- procedures that exist in various widths. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library std; use std.textio.all; library work; use work.tl_file_io_pkg.all; use work.tl_string_util_pkg.all; package tl_flat_memory_model_pkg is constant c_fm_max_bank : integer := 255; constant c_fm_max_sector : integer := 65535; constant c_fm_sector_size : integer := 16384; subtype t_byte is std_logic_vector(7 downto 0); type flat_mem_sector_t is array(0 to c_fm_sector_size-1) of integer; -- each sector is 64kB type flat_mem_sector_p is access flat_mem_sector_t; type flat_mem_bank_t is array(0 to c_fm_max_sector) of flat_mem_sector_p; -- there are 64k sectors (4 GB) type flat_mem_bank_p is access flat_mem_bank_t; -- we need to use a handle rather than a pointer, because we can't pass pointers in function calls -- Hence, we don't use a linked list, but an array. type flat_mem_object_t is record path : string(1 to 256); name : string(1 to 128); bank : flat_mem_bank_p; end record; type flat_mem_object_p is access flat_mem_object_t; type flat_mem_array_t is array(1 to c_fm_max_bank) of flat_mem_object_p; subtype h_mem_object is integer range 0 to c_fm_max_bank; --------------------------------------------------------------------------- shared variable flat_memories : flat_mem_array_t := (others => null); --------------------------------------------------------------------------- procedure register_mem_model( path : string; named : string; variable handle : out h_mem_object); procedure bind_mem_model ( named : string; variable handle : out h_mem_object); --------------------------------------------------------------------------- -- Low level calls impure function read_memory( bank : integer; sector : integer; entry : integer) return integer; procedure write_memory( bank : integer; sector : integer; entry : integer; data : integer); procedure clear_memory( bank : integer); procedure clean_up; -- 32-bit address/data access calls impure function read_memory_32( bank : integer; address : std_logic_vector(31 downto 0)) return std_logic_vector; procedure write_memory_32( bank : integer; address : std_logic_vector(31 downto 0); data : std_logic_vector(31 downto 0)); procedure write_memory_be( bank : integer; address : std_logic_vector(31 downto 0); data : std_logic_vector(31 downto 0); be : std_logic_vector(3 downto 0)); -- 16-bit address/data access calls impure function read_memory_16( bank : integer; address : std_logic_vector(31 downto 0)) return std_logic_vector; procedure write_memory_16( bank : integer; address : std_logic_vector(31 downto 0); data : std_logic_vector(15 downto 0)); -- 8-bit address/data access calls impure function read_memory_8( bank : integer; address : std_logic_vector(31 downto 0)) return std_logic_vector; procedure write_memory_8( bank : integer; address : std_logic_vector(31 downto 0); data : std_logic_vector(7 downto 0)); -- integer direct access calls impure function read_memory_int( bank : integer; address : integer ) return integer; procedure write_memory_int( bank : integer; address : integer; data : integer ); -- File Access Procedures procedure load_memory( filename : string; bank : integer; address : std_logic_vector(31 downto 0)); procedure save_memory( filename : string; bank : integer; address : std_logic_vector(31 downto 0); length : integer); procedure load_memory_hex( filename : string; bank : integer); procedure save_memory_hex( filename : string; bank : integer; address : std_logic_vector(31 downto 0); length : integer); end package; package body tl_flat_memory_model_pkg is -- Memory model module registration into array procedure register_mem_model( path : string; named : string; variable handle : out h_mem_object) is begin handle := 0; L1 : for i in flat_memories'range loop if flat_memories(i) = null then -- report "my name is "& named; handle := i; flat_memories(i) := new flat_mem_object_t; flat_memories(i).path(path'range) := path; flat_memories(i).name(named'range) := named; flat_memories(i).bank := new flat_mem_bank_t; exit L1; end if; end loop; end procedure register_mem_model; -- Memory model module binding procedure bind_mem_model ( named : string; variable handle : out h_mem_object) is begin handle := 0; wait for 1 ns; L1 : for i in flat_memories'range loop if flat_memories(i) /= null then if flat_memories(i).name(named'range) = named or flat_memories(i).path(named'range) = named then handle := i; return; end if; end if; end loop; report "Can't find memory model '"&named&"'." severity failure; end procedure bind_mem_model; -- Base calls impure function read_memory( bank : integer; sector : integer; entry : integer) return integer is begin if flat_memories(bank) = null then return 0; end if; if flat_memories(bank).bank(sector) = null then return 0; end if; return flat_memories(bank).bank(sector).all(entry); end function read_memory; procedure write_memory( bank : integer; sector : integer; entry : integer; data : integer) is begin if flat_memories(bank) = null then flat_memories(bank) := new flat_mem_object_t; flat_memories(bank).bank(0 to c_fm_max_sector) := (others => null); end if; if flat_memories(bank).bank(sector) = null then flat_memories(bank).bank(sector) := new flat_mem_sector_t; flat_memories(bank).bank(sector).all(0 to c_fm_sector_size-1) := (others => 0); end if; flat_memories(bank).bank(sector).all(entry) := data; end procedure write_memory; procedure clear_memory(bank : integer) is begin if flat_memories(bank) /= null then for i in flat_memories(bank).bank'range loop if flat_memories(bank).bank(i) /= null then deallocate(flat_memories(bank).bank(i)); end if; end loop; deallocate(flat_memories(bank)); flat_memories(bank) := null; end if; end procedure clear_memory; procedure clean_up is begin for i in flat_memories'range loop clear_memory(i); end loop; end procedure clean_up; -- 32-bit address/data access calls impure function read_memory_32( bank : integer; address : std_logic_vector(31 downto 0)) return std_logic_vector is variable sector_idx : integer; variable entry_idx : integer; begin sector_idx := to_integer(unsigned(address(31 downto 16))); entry_idx := to_integer(unsigned(address(15 downto 2))); return std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32)); end function read_memory_32; procedure write_memory_32( bank : integer; address : std_logic_vector(31 downto 0); data : std_logic_vector(31 downto 0)) is variable sector_idx : integer; variable entry_idx : integer; begin sector_idx := to_integer(unsigned(address(31 downto 16))); entry_idx := to_integer(unsigned(address(15 downto 2))); write_memory(bank, sector_idx, entry_idx, to_integer(signed(data))); end procedure write_memory_32; procedure write_memory_be( bank : integer; address : std_logic_vector(31 downto 0); data : std_logic_vector(31 downto 0); be : std_logic_vector(3 downto 0)) is variable sector_idx : integer; variable entry_idx : integer; variable read_data : std_logic_vector(31 downto 0); variable L : line; begin --write_s(L, "Writing " & vec_to_hex(data, 8) & " to location " & vec_to_hex(address, 8)); --writeline(output, L); sector_idx := to_integer(unsigned(address(31 downto 16))); entry_idx := to_integer(unsigned(address(15 downto 2))); read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32)); for i in be'range loop if to_x01(be(i)) = '1' then read_data(7+8*i downto 8*i) := data(7+8*i downto 8*i); end if; end loop; write_memory(bank, sector_idx, entry_idx, to_integer(signed(read_data))); end procedure write_memory_be; -- 16-bit address/data access calls impure function read_memory_16( bank : integer; address : std_logic_vector(31 downto 0)) return std_logic_vector is variable sector_idx : integer; variable entry_idx : integer; variable read_data : std_logic_vector(31 downto 0); begin sector_idx := to_integer(unsigned(address(31 downto 16))); entry_idx := to_integer(unsigned(address(15 downto 2))); read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32)); if address(1) = '0' then return read_data(15 downto 0); else return read_data(31 downto 16); end if; end function read_memory_16; procedure write_memory_16( bank : integer; address : std_logic_vector(31 downto 0); data : std_logic_vector(15 downto 0)) is variable be_temp : std_logic_vector(3 downto 0); variable write_data : std_logic_vector(31 downto 0); begin write_data := data & data; be_temp := address(1) & address(1) & not address(1) & not address(1); write_memory_be(bank, address, write_data, be_temp); end procedure write_memory_16; -- 8-bit address/data access calls impure function read_memory_8( bank : integer; address : std_logic_vector(31 downto 0)) return std_logic_vector is variable sector_idx : integer; variable entry_idx : integer; variable read_data : std_logic_vector(31 downto 0); begin sector_idx := to_integer(unsigned(address(31 downto 16))); entry_idx := to_integer(unsigned(address(15 downto 2))); read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32)); case address(1 downto 0) is when "11" => return read_data(31 downto 24); when "01" => return read_data(15 downto 8); when "10" => return read_data(23 downto 16); when others => return read_data(7 downto 0); end case; end function read_memory_8; procedure write_memory_8( bank : integer; address : std_logic_vector(31 downto 0); data : std_logic_vector(7 downto 0)) is variable be_temp : std_logic_vector(3 downto 0) := (others => '0'); variable write_data : std_logic_vector(31 downto 0); begin write_data := data & data & data & data; be_temp(to_integer(unsigned(address(1 downto 0)))) := '1'; write_memory_be(bank, address, write_data, be_temp); end procedure write_memory_8; -- Integer direct procedures impure function read_memory_int( bank : integer; address : integer ) return integer is variable sect, index : integer; begin sect := address / c_fm_sector_size; index := address mod c_fm_sector_size; return read_memory(bank, sect, index); end function read_memory_int; procedure write_memory_int( bank : integer; address : integer; data : integer ) is variable sect, index : integer; begin sect := address / c_fm_sector_size; index := address mod c_fm_sector_size; write_memory(bank, sect, index, data); end procedure write_memory_int; -- File access procedures -- not a public procedure. procedure read_binary_file( file myfile : t_binary_file; bank : integer; startaddr : std_logic_vector(31 downto 0); variable myrec : inout t_binary_file_rec) is variable addr : unsigned(31 downto 0); variable data : std_logic_vector(7 downto 0); variable i : integer; variable sector_idx : integer; variable entry_idx : integer; begin addr := unsigned(startaddr); if startaddr(1 downto 0) = "00" then sector_idx := to_integer(addr(31 downto 16)); entry_idx := to_integer(addr(15 downto 2)); aligned : while true loop if EndFile(myfile) then exit aligned; end if; read(myfile, i); write_memory(bank, sector_idx, entry_idx, i); if entry_idx = c_fm_sector_size-1 then entry_idx := 0; if sector_idx = c_fm_max_sector then sector_idx := 0; else sector_idx := sector_idx + 1; end if; else entry_idx := entry_idx + 1; end if; end loop; else unaligned : while true loop if EndFile(myfile) and myrec.Offset = 0 then exit unaligned; end if; read_byte(myfile, data, myrec); write_memory_8(bank, std_logic_vector(addr), data); addr := addr + 1; end loop; end if; end read_binary_file; -- not a public procedure procedure read_hex_file ( file myfile : text; bank : integer) is variable L : line; variable addr : unsigned(31 downto 0) := (others => '0'); variable c : character; variable data : t_byte; variable sum : unsigned(7 downto 0); variable rectype : t_byte; variable tmp_addr : std_logic_vector(15 downto 0); variable fileend : boolean; variable linenr : integer := 0; variable len : integer; begin outer : while true loop if EndFile(myfile) then report "Missing end of file record." severity warning; return; end if; -- search for lines starting with ':' start : while true loop readline(myfile, L); linenr := linenr + 1; read(L, c); if c = ':' then exit start; end if; end loop; -- parse the rest of the line sum := X"00"; get_byte_from_file(myfile, L, fileend, data); len := to_integer(unsigned(data)); get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8)); get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0)); get_byte_from_file(myfile, L, fileend, rectype); sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype)); case rectype is when X"00" => -- data record addr(15 downto 0) := unsigned(tmp_addr); for i in 0 to len-1 loop get_byte_from_file(myfile, L, fileend, data); sum := sum - unsigned(data); write_memory_8(bank, std_logic_vector(addr), data); addr := addr + 1; end loop; when X"01" => -- end of file record return; when X"04" => -- extended linear address record get_byte_from_file(myfile, L, fileend, data); addr(31 downto 24) := unsigned(data); sum := sum - addr(31 downto 24); get_byte_from_file(myfile, L, fileend, data); addr(23 downto 16) := unsigned(data); sum := sum - addr(23 downto 16); when others => report "Unexpected record type " & vec_to_hex(rectype, 2) severity warning; return; end case; -- check checksum get_byte_from_file(myfile, L, fileend, data); assert sum = unsigned(data) report "Warning: Checksum incorrect at line: " & integer'image(linenr) severity warning; end loop; end read_hex_file; -- public procedure: procedure load_memory( filename : string; bank : integer; address : std_logic_vector(31 downto 0)) is variable stat : file_open_status; file myfile : t_binary_file; variable myrec : t_binary_file_rec; begin -- open file file_open(stat, myfile, filename, read_mode); assert (stat = open_ok) report "Could not open file " & filename & " for reading." severity failure; init_record(myrec); read_binary_file (myfile, bank, address, myrec); file_close(myfile); end load_memory; -- public procedure: procedure load_memory_hex( filename : string; bank : integer) is variable stat : file_open_status; file myfile : text; begin -- open file file_open(stat, myfile, filename, read_mode); assert (stat = open_ok) report "Could not open file " & filename & " for reading." severity failure; read_hex_file (myfile, bank); file_close(myfile); end load_memory_hex; -- not a public procedure. procedure write_binary_file( file myfile : t_binary_file; bank : integer; startaddr : std_logic_vector(31 downto 0); length : integer; variable myrec : inout t_binary_file_rec) is variable addr : unsigned(31 downto 0); variable data : std_logic_vector(7 downto 0); variable i : integer; variable sector_idx : integer; variable entry_idx : integer; variable remaining : integer; begin addr := unsigned(startaddr); if startaddr(1 downto 0) = "00" then sector_idx := to_integer(addr(31 downto 16)); entry_idx := to_integer(addr(15 downto 2)); remaining := (length + 3) / 4; aligned : while remaining > 0 loop i := read_memory(bank, sector_idx, entry_idx); write(myfile, i); remaining := remaining - 1; if entry_idx = c_fm_sector_size-1 then if sector_idx = c_fm_max_sector then sector_idx := 0; else sector_idx := sector_idx + 1; end if; else entry_idx := entry_idx + 1; end if; end loop; else remaining := length; unaligned : while remaining > 0 loop data := read_memory_8(bank, std_logic_vector(addr)); write_byte(myfile, data, myrec); addr := addr + 1; remaining := remaining - 1; end loop; purge(myfile, myrec); end if; end write_binary_file; -- not a public procedure. procedure write_hex_file( file myfile : text; bank : integer; startaddr : std_logic_vector(31 downto 0); length : integer) is variable addr : std_logic_vector(31 downto 0); variable data : std_logic_vector(7 downto 0); variable sector_idx : integer; variable entry_idx : integer; variable remaining : integer; variable maxlen : integer; variable sum : unsigned(7 downto 0); variable L : line; variable prev_hi : std_logic_vector(31 downto 16) := (others => '-'); begin addr := startaddr; remaining := length; unaligned : while remaining > 0 loop -- check if we need to write a new extended address record if addr(31 downto 16) /= prev_hi then write_string(L, ":02000004"); write(L, vec_to_hex(addr(31 downto 16), 4)); write(L, vec_to_hex(std_logic_vector(X"FA" - unsigned(addr(31 downto 24)) - unsigned(addr(23 downto 16))), 2)); writeline(myfile, L); prev_hi := addr(31 downto 16); end if; -- check for maximum length (until 64k boundary) maxlen := to_integer(X"10000" - unsigned(X"0" & addr(15 downto 0))); if maxlen > 16 then maxlen := 16; end if; -- create data record sum := X"00"; write(L, ':'); write(L, vec_to_hex(std_logic_vector(to_unsigned(maxlen, 8)), 2)); write(L, vec_to_hex(addr(15 downto 0), 4)); write_string(L, "00"); sum := sum - maxlen; sum := sum - unsigned(addr(15 downto 8)); sum := sum - unsigned(addr(7 downto 0)); for i in 1 to maxlen loop data := read_memory_8(bank, addr); sum := sum - unsigned(data); write(L, vec_to_hex(data, 2)); addr := std_logic_vector(unsigned(addr) + 1); end loop; remaining := remaining - maxlen; write(L, vec_to_hex(std_logic_vector(sum), 2)); writeline(myfile, L); end loop; write_string(L, ":00000001"); writeline(myfile, L); end write_hex_file; -- public procedure: procedure save_memory( filename : string; bank : integer; address : std_logic_vector(31 downto 0); length : integer) is variable stat : file_open_status; file myfile : t_binary_file; variable myrec : t_binary_file_rec; begin -- open file file_open(stat, myfile, filename, write_mode); assert (stat = open_ok) report "Could not open file " & filename & " for writing." severity failure; init_record(myrec); write_binary_file (myfile, bank, address, length, myrec); file_close(myfile); end save_memory; -- public procedure: procedure save_memory_hex( filename : string; bank : integer; address : std_logic_vector(31 downto 0); length : integer) is variable stat : file_open_status; file myfile : text; begin -- open file file_open(stat, myfile, filename, write_mode); assert (stat = open_ok) report "Could not open file " & filename & " for writing." severity failure; write_hex_file (myfile, bank, address, length); file_close(myfile); end save_memory_hex; end;
gpl-3.0
timofonic/1541UltimateII
fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v2.vhd
5
15718
------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 - Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : External Memory controller for SRAM / FLASH / SDRAM (no burst) ------------------------------------------------------------------------------- -- File : ext_mem_ctrl.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This module implements a simple, single access memory controller. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity ext_mem_ctrl_v2 is generic ( tag_width : integer := 2; SRAM_Byte_Lanes : integer := 1; SRAM_Data_Width : integer := 8; SRAM_WR_ASU : integer := 0; SRAM_WR_Pulse : integer := 1; -- 2 cycles in total SRAM_WR_Hold : integer := 1; SRAM_RD_ASU : integer := 0; SRAM_RD_Pulse : integer := 1; SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround) ETH_Acc_Time : integer := 9; FLASH_ASU : integer := 0; FLASH_Pulse : integer := 3; FLASH_Hold : integer := 1; -- bus turn around A_Width : integer := 23; SDRAM_Refr_period : integer := 375 ); port ( clock : in std_logic := '0'; clk_shifted : in std_logic := '0'; reset : in std_logic := '0'; inhibit : in std_logic; is_idle : out std_logic; req : in std_logic; req_tag : in std_logic_vector(1 to tag_width) := (others => '0'); readwriten : in std_logic; address : in std_logic_vector(25 downto 0); -- 64M Space rack : out std_logic; dack : out std_logic; rack_tag : out std_logic_vector(1 to tag_width); dack_tag : out std_logic_vector(1 to tag_width); wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0); wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0'); rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0); slot_req : in std_logic := '0'; dma_addr : out std_logic_vector(15 downto 0); dma_rdata : in std_logic_vector(7 downto 0); dma_wdata : out std_logic_vector(7 downto 0); dma_req : out std_logic; dma_rwn : out std_logic; dma_ack : in std_logic := '0'; enable_refr : in std_logic := '0'; enable_sdram: in std_logic := '0'; SDRAM_CLK : out std_logic; SDRAM_CKE : out std_logic; SDRAM_CSn : out std_logic := '1'; SDRAM_RASn : out std_logic := '1'; SDRAM_CASn : out std_logic := '1'; SDRAM_WEn : out std_logic := '1'; ETH_CSn : out std_logic := '1'; SRAM_CSn : out std_logic; FLASH_CSn : out std_logic; MEM_A : out std_logic_vector(A_Width-1 downto 0); MEM_OEn : out std_logic; MEM_WEn : out std_logic; MEM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z'); MEM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) ); end ext_mem_ctrl_v2; -- ADDR: 25 24 23 ... -- 0 0 0 ... SRAM -- 0 0 1 ... C64 DMA -- 0 1 0 ... Flash -- 0 1 1 ... SDRAM command -- 1 X X ... SDRAM (32MB) architecture Gideon of ext_mem_ctrl_v2 is type t_state is (idle, setup, pulse, hold, dma_access, sd_cas, sd_wait, eth_pulse); signal state : t_state; signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1'); signal sram_d_t : std_logic := '0'; signal delay : integer range 0 to 15; signal inhibit_d : std_logic; signal rwn_i : std_logic; signal tag : std_logic_vector(1 to tag_width); signal memsel : std_logic_vector(1 downto 0); signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0'); signal col_addr : std_logic_vector(9 downto 0) := (others => '0'); signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1; signal do_refresh : std_logic := '0'; signal not_clock : std_logic; signal reg_out : integer range 0 to 3 := 0; signal rdata_i : std_logic_vector(7 downto 0) := (others => '0'); signal dout_sel : std_logic := '0'; signal dma_rdata_c : std_logic_vector(7 downto 0) := (others => '0'); signal refr_delay : integer range 0 to 3; signal suspend_dma : std_logic; signal dma_tag : std_logic_vector(tag'range); -- signal counter : std_logic_vector(7 downto 0) := X"00"; -- attribute fsm_encoding : string; -- attribute fsm_encoding of state : signal is "sequential"; -- attribute register_duplication : string; -- attribute register_duplication of mem_a_i : signal is "no"; attribute iob : string; attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB begin assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure; -- assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure; assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure; assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure; assert FLASH_Pulse > 0 report "Flash cmd pulse time should be greater than 0." severity failure; assert FLASH_Hold > 0 report "Flash hold time should be greater than 0." severity failure; is_idle <= '1' when state = idle else '0'; rdata <= rdata_i when dout_sel='0' else dma_rdata_c; process(clock) procedure send_refresh_cmd is begin do_refresh <= '0'; SDRAM_CSn <= '0'; SDRAM_RASn <= '0'; SDRAM_CASn <= '0'; SDRAM_WEn <= '1'; -- Auto Refresh refr_delay <= 3; end procedure; procedure accept_req is begin rack <= '1'; rack_tag <= req_tag; tag <= req_tag; rwn_i <= readwriten; mem_a_i <= address(MEM_A'range); memsel <= address(25 downto 24); sram_d_t <= not readwriten; sram_d_o <= wdata; dma_wdata <= wdata; SRAM_CSn <= address(25) or address(24) or address(23); -- should be all '0' for CSn to become active FLASH_CSn <= address(25) or not address(24) or address(23) or address(22); -- '0' when A25..23 = 010 ETH_CSn <= address(25) or not address(24) or address(23) or not address(22); -- '1' when A25..22 = 0101 if address(25)='1' then mem_a_i(12 downto 0) <= address(24 downto 12); -- 13 row bits mem_a_i(17 downto 16) <= address(11 downto 10); -- 2 bank bits col_addr <= address( 9 downto 0); -- 10 column bits SDRAM_CSn <= '0'; SDRAM_RASn <= '0'; SDRAM_CASn <= '1'; SDRAM_WEn <= '1'; -- Command = ACTIVE sram_d_t <= '0'; -- no data yet delay <= 1; state <= sd_cas; elsif address(24 downto 22)="100" then -- Flash if FLASH_ASU=0 then state <= pulse; delay <= FLASH_Pulse; else delay <= FLASH_ASU; state <= setup; end if; if readwriten='0' then -- write MEM_BEn <= not wdata_mask; MEM_WEn <= '0'; MEM_OEn <= '1'; else -- read MEM_BEn <= (others => '0'); MEM_OEn <= '0'; MEM_WEn <= '1'; end if; elsif address(24 downto 22)="101" then -- Ethernet delay <= ETH_Acc_Time; state <= eth_pulse; elsif address(24 downto 23)="11" then -- sdram command SDRAM_CSn <= '0'; SDRAM_RASn <= address(13); SDRAM_CASn <= address(14); SDRAM_WEn <= address(15); dack <= '1'; dack_tag <= req_tag; state <= idle; elsif address(24 downto 23)="01" then -- DMA MEM_BEn <= (others => '1'); MEM_OEn <= '1'; MEM_WEn <= '1'; dma_req <= '1'; state <= dma_access; else -- SRAM if readwriten='0' then -- write MEM_BEn <= not wdata_mask; if SRAM_WR_ASU=0 then state <= pulse; MEM_WEn <= '0'; delay <= SRAM_WR_Pulse; else delay <= SRAM_WR_ASU; state <= setup; end if; else -- read MEM_BEn <= (others => '0'); MEM_OEn <= '0'; if SRAM_RD_ASU=0 then state <= pulse; delay <= SRAM_RD_Pulse; else delay <= SRAM_RD_ASU; state <= setup; end if; end if; end if; end procedure; begin if rising_edge(clock) then rack <= '0'; dack <= '0'; rack_tag <= (others => '0'); dack_tag <= (others => '0'); dout_sel <= '0'; dma_rdata_c <= dma_rdata; inhibit_d <= inhibit; rdata_i <= MEM_D; -- clock in SDRAM_CSn <= '1'; SDRAM_CKE <= enable_sdram; if refr_delay /= 0 then refr_delay <= refr_delay - 1; end if; case state is when idle => if suspend_dma='1' then tag <= dma_tag; state <= dma_access; -- first cycle after inhibit goes 0, do not do refresh -- this enables putting cartridge images in sdram elsif do_refresh='1' and not (inhibit_d='1' and inhibit='0') then send_refresh_cmd; elsif inhibit='0' then dma_req <= '0'; if req='1' and (refr_delay=0 or address(25)='0') then accept_req; end if; end if; when sd_cas => mem_a_i(10) <= '1'; -- auto precharge mem_a_i(9 downto 0) <= col_addr; sram_d_t <= '1'; if delay = 0 then -- read or write with auto precharge SDRAM_CSn <= '0'; SDRAM_RASn <= '1'; SDRAM_CASn <= '0'; SDRAM_WEn <= rwn_i; if rwn_i='0' then -- write delay <= 2; else delay <= 1; end if; state <= sd_wait; else delay <= delay - 1; end if; when sd_wait => sram_d_t <= '0'; if delay=0 then dack <= '1'; dack_tag <= tag; state <= idle; else delay <= delay - 1; end if; when setup => if delay = 1 then state <= pulse; if memsel(0)='0' then -- SRAM if rwn_i='0' then delay <= SRAM_WR_Pulse; MEM_WEn <= '0'; else delay <= SRAM_RD_Pulse; MEM_OEn <= '0'; end if; else delay <= FLASH_Pulse; if rwn_i='0' then MEM_WEn <= '0'; else MEM_OEn <= '0'; end if; end if; else delay <= delay - 1; end if; when pulse => if delay = 1 then MEM_OEn <= '1'; MEM_WEn <= '1'; dack <= '1'; dack_tag <= tag; if memsel(0)='0' then -- SRAM if rwn_i='0' and SRAM_WR_Hold > 0 then delay <= SRAM_WR_Hold; state <= hold; elsif rwn_i='1' and SRAM_RD_Hold > 0 then state <= hold; delay <= SRAM_RD_Hold; else sram_d_t <= '0'; SRAM_CSn <= '1'; FLASH_CSn <= '1'; state <= idle; end if; else -- Flash if rwn_i='0' and FLASH_Hold > 0 then -- for writes, add hold cycles delay <= FLASH_Hold; state <= hold; else sram_d_t <= '0'; SRAM_CSn <= '1'; FLASH_CSn <= '1'; state <= idle; end if; end if; else delay <= delay - 1; end if; when eth_pulse => delay <= delay - 1; case delay is when 2 => dack <= '1'; dack_tag <= tag; -- rdata_i <= counter; -- counter <= counter + 1; MEM_WEn <= '1'; MEM_OEn <= '1'; when 1 => sram_d_t <= '0'; ETH_CSn <= '1'; state <= idle; when others => MEM_WEn <= rwn_i; MEM_OEn <= not rwn_i; end case; when hold => if delay = 1 then sram_d_t <= '0'; SRAM_CSn <= '1'; FLASH_CSn <= '1'; state <= idle; else delay <= delay - 1; end if; when dma_access => suspend_dma <= '0'; dma_tag <= tag; if dma_ack='1' then dma_req <= '0'; sram_d_t <= '0'; dack <= '1'; dack_tag <= tag; dout_sel <= '1'; state <= idle; elsif slot_req='1' then suspend_dma <= '1'; accept_req; -- exits this state, does an access and returns to idle. end if; when others => null; end case; if refresh_cnt = SDRAM_Refr_period-1 then do_refresh <= enable_refr; refresh_cnt <= 0; else refresh_cnt <= refresh_cnt + 1; end if; if reset='1' then state <= idle; dma_req <= '0'; ETH_CSn <= '1'; SRAM_CSn <= '1'; FLASH_CSn <= '1'; MEM_BEn <= (others => '1'); -- sram_d_o <= (others => '1'); sram_d_t <= '0'; MEM_OEn <= '1'; MEM_WEn <= '1'; delay <= 0; tag <= (others => '0'); do_refresh <= '0'; suspend_dma <= '0'; end if; end if; end process; dma_rwn <= rwn_i; MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z'); MEM_A <= mem_a_i; dma_addr <= mem_a_i(15 downto 0); not_clock <= not clk_shifted; clkout: FDDRRSE port map ( CE => '1', C0 => clk_shifted, C1 => not_clock, D0 => '0', D1 => enable_sdram, Q => SDRAM_CLK, R => '0', S => '0' ); end Gideon;
gpl-3.0
timofonic/1541UltimateII
fpga/ip/busses/vhdl_bfm/mem_bus_slave_bfm.vhd
5
1640
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mem_bus_pkg.all; use work.tl_flat_memory_model_pkg.all; entity mem_bus_slave_bfm is generic ( g_name : string; g_latency : positive := 2 ); port ( clock : in std_logic; req : in t_mem_req; resp : out t_mem_resp ); end mem_bus_slave_bfm; architecture bfm of mem_bus_slave_bfm is shared variable mem : h_mem_object; signal bound : boolean := false; signal pipe : t_mem_req_array(0 to g_latency-1) := (others => c_mem_req_init); begin -- this process registers this instance of the bfm to the server package bind: process begin register_mem_model(mem_bus_slave_bfm'path_name, g_name, mem); bound <= true; wait; end process; resp.rack <= '1' when bound and req.request='1' else '0'; resp.rack_tag <= req.tag when bound and req.request='1' else (others => '0'); process(clock) begin if rising_edge(clock) then pipe(0 to g_latency-2) <= pipe(1 to g_latency-1); pipe(g_latency-1) <= req; resp.dack_tag <= (others => '0'); resp.data <= (others => '0'); if bound then if pipe(0).request='1' then if pipe(0).read_writen='1' then resp.dack_tag <= pipe(0).tag; resp.data <= read_memory_8(mem, "000000" & std_logic_vector(pipe(0).address)); else write_memory_8(mem, "000000" & std_logic_vector(pipe(0).address), pipe(0).data); end if; end if; end if; end if; end process; end bfm;
gpl-3.0
timofonic/1541UltimateII
fpga/1541/vhdl_bfm/iec_bus_bfm.vhd
4
17537
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; library std; use std.textio.all; package iec_bus_bfm_pkg is type t_iec_bus_bfm_object; type p_iec_bus_bfm_object is access t_iec_bus_bfm_object; type t_iec_status is (ok, no_devices, no_response, timeout, no_eoi_ack); type t_iec_state is (idle, talker, listener); type t_iec_command is (none, send_atn, send_msg, atn_to_listen); type t_iec_data is array(natural range <>) of std_logic_vector(7 downto 0); type t_iec_message is record data : t_iec_data(0 to 256); len : integer; end record; type t_iec_to_bfm is record command : t_iec_command; end record; type t_iec_from_bfm is record busy : boolean; end record; constant c_iec_to_bfm_init : t_iec_to_bfm := ( command => none ); constant c_iec_from_bfm_init : t_iec_from_bfm := ( busy => false ); type t_iec_bus_bfm_object is record next_bfm : p_iec_bus_bfm_object; name : string(1 to 256); -- interface to the user status : t_iec_status; state : t_iec_state; stopped : boolean; sample_time : time; -- buffer msg_buf : t_iec_message; -- internal to bfm to_bfm : t_iec_to_bfm; -- internal from bfm from_bfm : t_iec_from_bfm; end record; constant c_atn_to_ckl : time := 5 us; constant c_atn_resp_max : time := 1000 us; constant c_non_eoi : time := 40 us; constant c_clk_low : time := 50 us; constant c_clk_high : time := 50 us; constant c_frame_hs_max : time := 1000 us; constant c_frame_release : time := 20 us; constant c_byte_to_byte : time := 100 us; constant c_eoi_min : time := 200 us; constant c_eoi : time := 500 us; -- was 250 constant c_eoi_hold : time := 60 us; constant c_tlkr_resp_dly : time := 60 us; -- max constant c_talk_atn_rel : time := 30 us; constant c_talk_atn_ack : time := 250 us; -- ? ------------------------------------------------------------------------------------ shared variable iec_bus_bfms : p_iec_bus_bfm_object := null; ------------------------------------------------------------------------------------ procedure register_iec_bus_bfm(named : string; variable pntr: inout p_iec_bus_bfm_object); procedure bind_iec_bus_bfm(named : string; variable pntr: inout p_iec_bus_bfm_object); ------------------------------------------------------------------------------------ procedure iec_stop(variable bfm : inout p_iec_bus_bfm_object); procedure iec_talk(variable bfm : inout p_iec_bus_bfm_object); procedure iec_listen(variable bfm : inout p_iec_bus_bfm_object); procedure iec_send_atn(variable bfm : inout p_iec_bus_bfm_object; byte : std_logic_vector(7 downto 0)); procedure iec_turnaround(variable bfm : inout p_iec_bus_bfm_object); procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object; msg: t_iec_message); procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object; msg: string); procedure iec_get_message(variable bfm : inout p_iec_bus_bfm_object; variable msg : inout t_iec_message); procedure iec_print_message(variable msg : inout t_iec_message); end iec_bus_bfm_pkg; package body iec_bus_bfm_pkg is procedure register_iec_bus_bfm(named : string; variable pntr : inout p_iec_bus_bfm_object) is begin -- Allocate a new BFM object in memory pntr := new t_iec_bus_bfm_object; -- Initialize object pntr.next_bfm := null; pntr.name(named'range) := named; pntr.status := ok; pntr.state := idle; pntr.stopped := false; -- active; pntr.sample_time := 1 us; pntr.to_bfm := c_iec_to_bfm_init; pntr.from_bfm := c_iec_from_bfm_init; -- add this pointer to the head of the linked list if iec_bus_bfms = null then -- first entry iec_bus_bfms := pntr; else -- insert new entry pntr.next_bfm := iec_bus_bfms; iec_bus_bfms := pntr; end if; end register_iec_bus_bfm; procedure bind_iec_bus_bfm(named : string; variable pntr : inout p_iec_bus_bfm_object) is variable p : p_iec_bus_bfm_object; begin pntr := null; wait for 1 ns; -- needed to make sure that binding takes place after registration p := iec_bus_bfms; -- start at the root L1: while p /= null loop if p.name(named'range) = named then pntr := p; exit L1; else p := p.next_bfm; end if; end loop; end bind_iec_bus_bfm; ------------------------------------------------------------------------------ procedure iec_stop(variable bfm : inout p_iec_bus_bfm_object) is begin bfm.stopped := true; end procedure; procedure iec_talk(variable bfm : inout p_iec_bus_bfm_object) is begin bfm.state := talker; end procedure; procedure iec_listen(variable bfm : inout p_iec_bus_bfm_object) is begin bfm.state := listener; end procedure; procedure iec_send_atn(variable bfm : inout p_iec_bus_bfm_object; byte : std_logic_vector(7 downto 0)) is begin bfm.msg_buf.data(0) := byte; bfm.msg_buf.len := 1; bfm.to_bfm.command := send_atn; wait for bfm.sample_time; wait for bfm.sample_time; while bfm.from_bfm.busy loop wait for bfm.sample_time; end loop; end procedure; procedure iec_turnaround(variable bfm : inout p_iec_bus_bfm_object) is begin bfm.to_bfm.command := atn_to_listen; wait for bfm.sample_time; wait for bfm.sample_time; while bfm.from_bfm.busy loop wait for bfm.sample_time; end loop; end procedure; procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object; msg: t_iec_message) is begin bfm.msg_buf := msg; bfm.to_bfm.command := send_msg; wait for bfm.sample_time; wait for bfm.sample_time; while bfm.from_bfm.busy loop wait for bfm.sample_time; end loop; end procedure; procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object; msg: string) is variable leng : integer; begin leng := msg'length; for i in 1 to leng loop bfm.msg_buf.data(i-1) := conv_std_logic_vector(character'pos(msg(i)), 8); end loop; bfm.msg_buf.len := leng; iec_send_message(bfm, bfm.msg_buf); end procedure; procedure iec_get_message(variable bfm : inout p_iec_bus_bfm_object; variable msg : inout t_iec_message) is begin wait for bfm.sample_time; wait for bfm.sample_time; while bfm.state = listener loop wait for bfm.sample_time; end loop; msg := bfm.msg_buf; end procedure; procedure iec_print_message(variable msg : inout t_iec_message) is variable L : line; variable c : character; begin for i in 0 to msg.len-1 loop c := character'val(conv_integer(msg.data(i))); write(L, c); end loop; writeline(output, L); end procedure; end; ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith; library work; use work.iec_bus_bfm_pkg.all; library std; use std.textio.all; entity iec_bus_bfm is port ( iec_clock : inout std_logic; iec_data : inout std_logic; iec_atn : inout std_logic ); end iec_bus_bfm; architecture bfm of iec_bus_bfm is shared variable this : p_iec_bus_bfm_object := null; signal bound : boolean := false; signal clk_i : std_logic; signal clk_o : std_logic; signal data_i : std_logic; signal data_o : std_logic; signal atn_i : std_logic; signal atn_o : std_logic; begin -- this process registers this instance of the bfm to the server package bind: process begin register_iec_bus_bfm(iec_bus_bfm'path_name, this); bound <= true; wait; end process; -- open collector logic clk_i <= iec_clock and '1'; data_i <= iec_data and '1'; atn_i <= iec_atn and '1'; iec_clock <= '0' when clk_o='0' else 'H'; iec_data <= '0' when data_o='0' else 'H'; iec_atn <= '0' when atn_o='0' else 'H'; -- |<--------- Byte sent under attention (to devices) ------------>| -- -- ___ ____ _____ _____ -- ATN |________________________________________________________| -- : : -- ___ ______ ________ ___ ___ ___ ___ ___ ___ ___ ___ : -- CLK : |_____| |_| |_| |_| |_| |_| |_| |_| |_| |______________ _____ -- : : : : : -- : Tat : :Th: Tne : : Tf : Tr : -- ____ ________ : : :___________________________________:____: -- DATA ___|\\\\\__:__| |__||__||__||__||__||__||__||__| |_________ _____ -- : 0 1 2 3 4 5 6 7 : -- : LSB MSB : -- : : : -- : : Data Valid Listener: Data Accepted -- : Listener READY-FOR-DATA protocol: process procedure do_send_atn is begin atn_o <= '0'; wait for c_atn_to_ckl; clk_o <= '0'; if data_i='1' then wait until data_i='0' for c_atn_resp_max; end if; if data_i='1' then this.status := no_devices; return; end if; clk_o <= '1'; wait until data_i='1'; -- for... (listener hold-off could be infinite) wait for c_non_eoi; for i in 0 to 7 loop clk_o <= '0'; data_o <= this.msg_buf.data(0)(i); wait for c_clk_low; clk_o <= '1'; wait for c_clk_high; end loop; clk_o <= '0'; data_o <= '1'; wait until data_i='0' for c_frame_hs_max; if data_i='1' then this.status := no_response; else this.status := ok; end if; wait for c_frame_release; atn_o <= '1'; end procedure; procedure send_byte(byte : std_logic_vector(7 downto 0)) is begin clk_o <= '1'; wait until data_i='1'; -- for... (listener hold-off could be infinite) wait for c_non_eoi; for i in 0 to 7 loop clk_o <= '0'; data_o <= byte(i); wait for c_clk_low; clk_o <= '1'; wait for c_clk_high; end loop; clk_o <= '0'; data_o <= '1'; wait until data_i='0' for c_frame_hs_max; if data_i='1' then this.status := no_response; else this.status := ok; end if; wait for c_byte_to_byte; end procedure; procedure end_handshake(byte : std_logic_vector(7 downto 0)) is begin clk_o <= '1'; wait until data_i='1'; -- for... (listener hold-off could be infinite) -- wait for c_eoi; -- data_o <= '0'; -- wait for c_eoi_hold; -- data_o <= '1'; wait until data_i='0' for c_eoi; -- wait for 250 µs to see that listener has acked eoi if data_i='1' then this.status := no_eoi_ack; return; end if; wait until data_i='1'; -- wait for listener to be ready again wait for c_tlkr_resp_dly; for i in 0 to 7 loop clk_o <= '0'; data_o <= byte(i); wait for c_clk_low; clk_o <= '1'; wait for c_clk_high; end loop; clk_o <= '0'; data_o <= '1'; wait until data_i='0' for c_frame_hs_max; if data_i='1' then this.status := no_response; else this.status := ok; end if; end procedure; procedure talk_atn_turnaround is begin wait for c_talk_atn_rel; clk_o <= '1'; data_o <= '0'; wait for c_talk_atn_rel; wait until clk_i = '0'; this.state := listener; this.msg_buf.len := 0; -- clear buffer for incoming data end procedure; procedure receive_byte is variable b : std_logic_vector(7 downto 0); variable eoi : boolean; variable c : character; variable L : LINE; begin eoi := false; if clk_i='0' then wait until clk_i='1'; end if; wait for c_clk_low; -- dummy data_o <= '1'; -- check for end of message handshake (data pulses low after >200 µs for >60 µs) wait until clk_i = '0' for c_eoi_min; if clk_i='1' then -- eoi timeout eoi := true; -- ack eoi data_o <= '0'; wait for c_eoi_hold; data_o <= '1'; end if; for i in 0 to 7 loop wait until clk_i='1'; b(i) := data_i; end loop; -- c := character'val(conv_integer(b)); -- write(L, c); -- writeline(output, L); -- this.msg_buf.data(this.msg_buf.len) := b; this.msg_buf.len := this.msg_buf.len + 1; wait until clk_i='0'; if eoi then this.state := idle; data_o <= '1'; else data_o <= '0'; end if; end procedure; begin atn_o <= '1'; data_o <= '1'; clk_o <= '1'; wait until bound; while not this.stopped loop wait for this.sample_time; case this.to_bfm.command is when none => null; when send_atn => this.from_bfm.busy := true; do_send_atn; this.from_bfm.busy := false; when send_msg => this.from_bfm.busy := true; if this.msg_buf.len > 1 then L1: for i in 0 to this.msg_buf.len-2 loop send_byte(this.msg_buf.data(i)); if this.status /= ok then exit L1; end if; end loop; end if; assert this.status = ok report "Sending data message failed." severity error; end_handshake(this.msg_buf.data(this.msg_buf.len-1)); assert this.status = ok report "Sending data message failed (Last Byte)." severity error; this.from_bfm.busy := false; when atn_to_listen => this.from_bfm.busy := true; talk_atn_turnaround; this.from_bfm.busy := false; end case; this.to_bfm.command := none; if this.state = listener then receive_byte; end if; end loop; wait; end process; -- if in idle state, and atn_i becomes '0', then become device and listen -- but that is only needed for devices... (not for the controller) -- if listener (means that I am addressed), listen to all bytes -- if end of message is detected, switch back to idle state. end bfm;
gpl-3.0
J-Rios/VHDL_Modules
2.Secuencial/Counter_pload.vhd
1
2355
---------------------------------------------------------------------------------- -- ------------------- -- -- | | -- -- RST ---------| RST | -- -- ENP ---------| ENP | -- -- LOAD ---------| LOAD | -- -- | | -- -- P[BITS-1:0] ---------| P Q |--------- Q[BITS-1:0] -- -- | | -- -- | | -- -- | | -- -- CLK ---------| CLK | -- -- | | -- -- ------------------- -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; ---------------------------------------------------------------------------------- entity COUNTER_PLoad is Generic ( BITS : INTEGER := 4 ); Port ( CLK : in STD_LOGIC; LOAD : in STD_LOGIC; ENP : in STD_LOGIC; RST : in STD_LOGIC; P : in STD_LOGIC_VECTOR (BITS-1 downto 0); Q : inout STD_LOGIC_VECTOR (BITS-1 downto 0) ); end COUNTER_PLoad; ---------------------------------------------------------------------------------- architecture Behavioral of COUNTER_PLoad is signal Count : UNSIGNED (BITS-1 downto 0) := (others => '0'); begin process(CLK, RST, LOAD, ENP) begin if (RST = '1') then Count <= (others => '0'); elsif (CLK'event and CLK = '1') then if (LOAD = '0' and ENP = '-') then Count <= unsigned(P); elsif (LOAD = '1' and ENP = '0') then Count <= Count; elsif (LOAD = '1' and ENP = '1') then Count <= Count + 1; end if; end if; end process; Q <= std_logic_vector(Count); end Behavioral;
gpl-3.0
J-Rios/VHDL_Modules
1.Combinational/Gate_AND.vhd
1
431
library IEEE; use IEEE.STD_LOGIC_1164.ALL; ---------------------------------------------------------------------------------- entity Gate_AND is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Z : out STD_LOGIC ); end Gate_AND; ---------------------------------------------------------------------------------- architecture Behavioral of Gate_AND is begin Z <= A and B; end Behavioral;
gpl-3.0
timofonic/1541UltimateII
fpga/ip/busses/vhdl_source/slot_bus_pkg.vhd
4
1974
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package slot_bus_pkg is type t_slot_req is record bus_address : unsigned(15 downto 0); -- for async reads and direct bus writes bus_write : std_logic; io_address : unsigned(15 downto 0); -- for late reads/writes io_read : std_logic; io_read_early : std_logic; io_write : std_logic; late_write : std_logic; data : std_logic_vector(7 downto 0); end record; type t_slot_resp is record data : std_logic_vector(7 downto 0); reg_output : std_logic; irq : std_logic; end record; constant c_slot_req_init : t_slot_req := ( bus_address => X"0000", bus_write => '0', io_read_early => '0', io_address => X"0000", io_read => '0', io_write => '0', late_write => '0', data => X"00" ); constant c_slot_resp_init : t_slot_resp := ( data => X"00", reg_output => '0', irq => '0' ); type t_slot_req_array is array(natural range <>) of t_slot_req; type t_slot_resp_array is array(natural range <>) of t_slot_resp; function or_reduce(ar: t_slot_resp_array) return t_slot_resp; end package; package body slot_bus_pkg is function or_reduce(ar: t_slot_resp_array) return t_slot_resp is variable ret : t_slot_resp; begin ret := c_slot_resp_init; for i in ar'range loop ret.reg_output := ret.reg_output or ar(i).reg_output; if ar(i).reg_output='1' then ret.data := ret.data or ar(i).data; end if; ret.irq := ret.irq or ar(i).irq; end loop; return ret; end function or_reduce; end package body;
gpl-3.0
timofonic/1541UltimateII
fpga/6502/vhdl_source/proc_control.vhd
2
17181
library ieee; use ieee.std_logic_1164.all; library work; use work.pkg_6502_defs.all; use work.pkg_6502_decode.all; entity proc_control is port ( clock : in std_logic; clock_en : in std_logic; ready : in std_logic; reset : in std_logic; interrupt : in std_logic; vect_sel : in std_logic_vector(2 downto 1); i_reg : in std_logic_vector(7 downto 0); index_carry : in std_logic; pc_carry : in std_logic; branch_taken : in boolean; sync : out std_logic; dummy_cycle : out std_logic; latch_dreg : out std_logic; copy_d2p : out std_logic; reg_update : out std_logic; rwn : out std_logic; vect_addr : out std_logic_vector(3 downto 0); irq_done : out std_logic; vectoring : out std_logic; a16 : out std_logic; a_mux : out t_amux := c_amux_pc; dout_mux : out t_dout_mux; pc_oper : out t_pc_oper; s_oper : out t_sp_oper; adl_oper : out t_adl_oper; adh_oper : out t_adh_oper ); end proc_control; architecture gideon of proc_control is type t_state is (fetch, decode, absolute, abs_hi, abs_fix, branch, branch_fix, indir1, indir2, jump_sub, jump, retrn, rmw1, rmw2, vector, startup, zp, zp_idx, zp_indir, push1, push2, push3, pull1, pull2, pull3, pre_irq ); signal state : t_state; signal next_state : t_state; signal rwn_i : std_logic; signal next_cp_p : std_logic; signal next_rwn : std_logic; signal next_dreg : std_logic; signal next_amux : t_amux; signal next_dout : t_dout_mux; signal next_dummy : std_logic; signal vectoring_i : std_logic; signal vect_bit_i : std_logic; signal vect_reg : std_logic_vector(2 downto 1); signal sync_i : std_logic; signal interrupt_d : std_logic := '0'; signal interrupt_dd : std_logic := '0'; signal trigger_upd : boolean; signal ready_d : std_logic := '1'; begin -- combinatroial process process(state, i_reg, index_carry, pc_carry, branch_taken, interrupt, vectoring_i, interrupt_d) variable v_stack_idx : std_logic_vector(1 downto 0); procedure check_irq is begin if interrupt='1' then pc_oper <= keep; next_state <= pre_irq; else pc_oper <= increment; next_state <= decode; sync_i <= '1'; end if; end procedure; begin -- defaults sync_i <= '0'; pc_oper <= increment; next_amux <= c_amux_pc; next_rwn <= '1'; next_state <= state; adl_oper <= keep; adh_oper <= keep; s_oper <= keep; next_dreg <= '1'; next_cp_p <= '0'; next_dout <= reg_d; next_dummy <= '0'; v_stack_idx := stack_idx(i_reg); case state is when fetch => check_irq; when pre_irq => pc_oper <= keep; next_rwn <= '0'; next_dout <= reg_pch; next_state <= push1; next_amux <= c_amux_stack; when decode => adl_oper <= load_bus; adh_oper <= clear; if is_absolute(i_reg) then if is_abs_jump(i_reg) then next_state <= jump; else next_state <= absolute; end if; elsif is_implied(i_reg) then pc_oper <= keep; if is_stack(i_reg) then -- PHP, PLP, PHA, PLA next_amux <= c_amux_stack; case v_stack_idx is when "00" => -- PHP next_state <= push3; next_rwn <= '0'; next_dout <= reg_flags; when "10" => -- PHA next_state <= push3; next_rwn <= '0'; next_dout <= reg_accu; when others => next_state <= pull1; end case; else next_state <= fetch; end if; elsif is_zeropage(i_reg) then next_amux <= c_amux_addr; if is_indirect(i_reg) then if is_postindexed(i_reg) then next_state <= zp_indir; else next_state <= zp; next_dummy <= '1'; end if; else next_state <= zp; if is_store(i_reg) and not is_postindexed(i_reg) then next_rwn <= '0'; next_dout <= reg_axy; end if; end if; elsif is_relative(i_reg) then next_state <= branch; elsif is_stack(i_reg) then -- non-implied stack operations like BRK, JSR, RTI and RTS next_amux <= c_amux_stack; case v_stack_idx is when c_stack_idx_brk => next_rwn <= '0'; next_dout <= reg_pch; next_state <= push1; when c_stack_idx_jsr => next_dreg <= '0'; next_dout <= reg_pch; next_state <= jump_sub; when c_stack_idx_rti => next_state <= pull1; when c_stack_idx_rts => next_state <= pull2; when others => null; end case; elsif is_immediate(i_reg) then next_state <= fetch; end if; when absolute => next_state <= abs_hi; next_amux <= c_amux_addr; adh_oper <= load_bus; if is_postindexed(i_reg) then adl_oper <= add_idx; elsif not is_zeropage(i_reg) then if is_store(i_reg) then next_rwn <='0'; next_dout <= reg_axy; end if; end if; if is_zeropage(i_reg) then pc_oper <= keep; else pc_oper <= increment; end if; when abs_hi => pc_oper <= keep; if is_postindexed(i_reg) then if is_load(i_reg) and index_carry='0' then next_amux <= c_amux_pc; next_state <= fetch; else next_amux <= c_amux_addr; next_state <= abs_fix; if index_carry='1' then adh_oper <= increment; end if; end if; if is_store(i_reg) then next_rwn <= '0'; next_dout <= reg_axy; end if; else -- not post-indexed if is_jump(i_reg) then next_amux <= c_amux_addr; next_state <= jump; adl_oper <= increment; elsif is_rmw(i_reg) then next_rwn <= '0'; next_dout <= reg_d; next_dummy <= '1'; next_state <= rmw1; next_amux <= c_amux_addr; else next_state <= fetch; next_amux <= c_amux_pc; end if; end if; when abs_fix => pc_oper <= keep; if is_rmw(i_reg) then next_state <= rmw1; next_amux <= c_amux_addr; next_rwn <= '0'; next_dout <= reg_d; next_dummy <= '1'; else next_state <= fetch; next_amux <= c_amux_pc; end if; when branch => next_amux <= c_amux_pc; if branch_taken then pc_oper <= from_alu; -- add offset next_state <= branch_fix; else check_irq; -- correct end if; when branch_fix => next_amux <= c_amux_pc; if pc_carry='1' then next_state <= fetch; pc_oper <= keep; -- this will fix the PCH, since the carry is set else if interrupt_d='1' then check_irq; else pc_oper <= increment; next_state <= decode; sync_i <= '1'; end if; end if; when indir1 => pc_oper <= keep; next_state <= indir2; next_amux <= c_amux_addr; adl_oper <= copy_dreg; adh_oper <= load_bus; if is_store(i_reg) then next_rwn <= '0'; next_dout <= reg_axy; end if; when indir2 => pc_oper <= keep; if is_rmw(i_reg) then next_dummy <= '1'; next_rwn <= '0'; next_dout <= reg_d; next_state <= rmw1; next_amux <= c_amux_addr; else next_state <= fetch; next_amux <= c_amux_pc; end if; when jump_sub => next_state <= push1; pc_oper <= keep; next_dout <= reg_pch; next_rwn <= '0'; next_dreg <= '0'; next_amux <= c_amux_stack; when jump => pc_oper <= copy; next_amux <= c_amux_pc; if is_stack(i_reg) and v_stack_idx=c_stack_idx_rts and vectoring_i='0' then next_state <= retrn; else next_state <= fetch; end if; when retrn => pc_oper <= increment; next_state <= fetch; when pull1 => s_oper <= increment; next_state <= pull2; next_amux <= c_amux_stack; pc_oper <= keep; when pull2 => pc_oper <= keep; if is_implied(i_reg) then next_state <= fetch; next_amux <= c_amux_pc; next_cp_p <= not v_stack_idx(1); -- only for PLP else -- it was a stack operation, but not implied (RTS/RTI) s_oper <= increment; next_state <= pull3; next_amux <= c_amux_stack; next_cp_p <= not v_stack_idx(0); -- only for RTI end if; when pull3 => pc_oper <= keep; s_oper <= increment; next_state <= jump; next_amux <= c_amux_stack; when push1 => pc_oper <= keep; s_oper <= decrement; next_state <= push2; next_amux <= c_amux_stack; next_rwn <= '0'; next_dreg <= '0'; next_dout <= reg_pcl; when push2 => pc_oper <= keep; s_oper <= decrement; if (v_stack_idx=c_stack_idx_jsr) and vectoring_i='0' then next_state <= jump; next_amux <= c_amux_pc; else next_state <= push3; next_rwn <= '0'; next_dout <= reg_flags; next_amux <= c_amux_stack; end if; when push3 => pc_oper <= keep; s_oper <= decrement; if is_implied(i_reg) and vectoring_i='0' then -- PHP, PHA next_amux <= c_amux_pc; next_state <= fetch; else next_state <= vector; next_amux <= c_amux_vector; end if; when rmw1 => pc_oper <= keep; next_state <= rmw2; next_amux <= c_amux_addr; next_rwn <= '0'; next_dout <= shift_res; when rmw2 => pc_oper <= keep; next_state <= fetch; next_amux <= c_amux_pc; when vector => next_state <= jump; pc_oper <= keep; next_amux <= c_amux_vector; when startup => next_state <= vector; pc_oper <= keep; next_amux <= c_amux_vector; when zp => pc_oper <= keep; if is_postindexed(i_reg) or is_indirect(i_reg) then adl_oper <= add_idx; next_state <= zp_idx; next_amux <= c_amux_addr; if is_postindexed(i_reg) and is_store(i_reg) then next_rwn <= '0'; next_dout <= reg_axy; end if; elsif is_rmw(i_reg) then next_dummy <= '1'; next_state <= rmw1; next_amux <= c_amux_addr; next_rwn <= '0'; next_dout <= reg_d; else next_state <= fetch; next_amux <= c_amux_pc; end if; when zp_idx => pc_oper <= keep; if is_indirect(i_reg) then next_state <= indir1; adl_oper <= increment; next_amux <= c_amux_addr; elsif is_rmw(i_reg) then next_state <= rmw1; next_amux <= c_amux_addr; next_rwn <= '0'; next_dout <= reg_d; else next_state <= fetch; next_amux <= c_amux_pc; end if; when zp_indir => pc_oper <= keep; next_state <= absolute; next_amux <= c_amux_addr; adl_oper <= increment; when others => null; end case; end process; reg_update <= '1' when (state = fetch) and vectoring_i='0' and trigger_upd else '0'; irq_done <= '1' when state = vector else '0'; vect_bit_i <= '0' when state = vector else '1'; vect_addr <= '1' & vect_reg & vect_bit_i; process(clock) begin if rising_edge(clock) then if clock_en='1' then ready_d <= ready; if ready='1' or rwn_i='0' then state <= next_state; a_mux <= next_amux; dout_mux <= next_dout; rwn_i <= next_rwn; latch_dreg <= next_dreg and next_rwn; -- disable dreg latch for writes copy_d2p <= next_cp_p; dummy_cycle <= next_dummy; interrupt_d <= interrupt;-- and ready_d; interrupt_dd <= interrupt_d; trigger_upd <= affect_registers(i_reg); if next_amux = c_amux_vector or next_amux = c_amux_pc then a16 <= '1'; else a16 <= '0'; end if; if sync_i='1' then vectoring_i <= '0'; elsif state = pre_irq then vectoring_i <= '1'; vect_reg <= vect_sel; end if; end if; end if; if reset='1' then a16 <= '1'; state <= startup; --vector; vect_reg <= vect_sel; a_mux <= c_amux_vector; rwn_i <= '1'; latch_dreg <= '1'; dout_mux <= reg_d; copy_d2p <= '0'; vectoring_i <= '0'; dummy_cycle <= '0'; end if; end if; end process; vectoring <= vectoring_i; sync <= sync_i; rwn <= rwn_i; end gideon;
gpl-3.0
J-Rios/VHDL_Modules
2.Secuencial/Counter_updown.vhd
1
1583
---------------------------------------------------------------------------------- -- ------------------- -- -- | | -- -- UP ---------| UP | -- -- | Q |--------- Q[BITS-1:0] -- -- CLK ---------| CLK | -- -- | | -- -- ------------------- -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; ---------------------------------------------------------------------------------- entity COUNTER_UpDw is Generic ( BITS : INTEGER := 4 ); Port ( CLK : in STD_LOGIC; UP : in STD_LOGIC; Q : inout STD_LOGIC_VECTOR (BITS-1 downto 0) ); end COUNTER_UpDw; ---------------------------------------------------------------------------------- architecture Behavioral of COUNTER_UpDw is signal Count : UNSIGNED (BITS-1 downto 0) := (others => '0'); begin process(UP, CLK) begin if (CLK'event and CLK = '1') then if (UP = '1') then Count <= Count + 1; else Count <= Count - 1; end if; end if; end process; Q <= std_logic_vector(Count); end Behavioral;
gpl-3.0
timofonic/1541UltimateII
fpga/1541/vhdl_source/via6522.vhd
2
26510
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity via6522 is port ( clock : in std_logic; clock_en : in std_logic; -- for counters and stuff reset : in std_logic; addr : in std_logic_vector(3 downto 0); wen : in std_logic; ren : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); -- pio -- port_a_o : out std_logic_vector(7 downto 0); port_a_t : out std_logic_vector(7 downto 0); port_a_i : in std_logic_vector(7 downto 0); port_b_o : out std_logic_vector(7 downto 0); port_b_t : out std_logic_vector(7 downto 0); port_b_i : in std_logic_vector(7 downto 0); -- handshake pins ca1_i : in std_logic; ca2_o : out std_logic; ca2_i : in std_logic; ca2_t : out std_logic; cb1_o : out std_logic; cb1_i : in std_logic; cb1_t : out std_logic; cb2_o : out std_logic; cb2_i : in std_logic; cb2_t : out std_logic; irq : out std_logic ); end via6522; architecture Gideon of via6522 is type pio_t is record pra : std_logic_vector(7 downto 0); ddra : std_logic_vector(7 downto 0); prb : std_logic_vector(7 downto 0); ddrb : std_logic_vector(7 downto 0); end record; constant pio_default : pio_t := (others => (others => '0')); constant latch_reset_pattern : std_logic_vector(15 downto 0) := X"01AA"; signal pio_i : pio_t; signal irq_mask : std_logic_vector(6 downto 0) := (others => '0'); signal irq_flags : std_logic_vector(6 downto 0) := (others => '0'); signal irq_events : std_logic_vector(6 downto 0) := (others => '0'); signal irq_out : std_logic; signal timer_a_latch : std_logic_vector(15 downto 0) := latch_reset_pattern; signal timer_b_latch : std_logic_vector(7 downto 0) := latch_reset_pattern(7 downto 0); signal timer_a_count : std_logic_vector(15 downto 0) := latch_reset_pattern; signal timer_b_count : std_logic_vector(15 downto 0) := latch_reset_pattern; signal timer_a_out : std_logic; signal timer_b_tick : std_logic; signal acr, pcr : std_logic_vector(7 downto 0) := X"00"; signal shift_reg : std_logic_vector(7 downto 0) := X"00"; signal serport_en : std_logic; signal ser_cb2_o : std_logic; signal hs_cb2_o : std_logic; alias ca2_event : std_logic is irq_events(0); alias ca1_event : std_logic is irq_events(1); alias serial_event : std_logic is irq_events(2); alias cb2_event : std_logic is irq_events(3); alias cb1_event : std_logic is irq_events(4); alias timer_b_event : std_logic is irq_events(5); alias timer_a_event : std_logic is irq_events(6); alias ca2_flag : std_logic is irq_flags(0); alias ca1_flag : std_logic is irq_flags(1); alias serial_flag : std_logic is irq_flags(2); alias cb2_flag : std_logic is irq_flags(3); alias cb1_flag : std_logic is irq_flags(4); alias timer_b_flag : std_logic is irq_flags(5); alias timer_a_flag : std_logic is irq_flags(6); alias tmr_a_output_en : std_logic is acr(7); alias tmr_a_freerun : std_logic is acr(6); alias tmr_b_count_mode : std_logic is acr(5); alias shift_dir : std_logic is acr(4); alias shift_clk_sel : std_logic_vector(1 downto 0) is acr(3 downto 2); alias shift_mode_control : std_logic_vector(2 downto 0) is acr(4 downto 2); alias pb_latch_en : std_logic is acr(1); alias pa_latch_en : std_logic is acr(0); alias cb2_is_output : std_logic is pcr(7); alias cb2_edge_select : std_logic is pcr(6); -- for when CB2 is input alias cb2_no_irq_clr : std_logic is pcr(5); -- for when CB2 is input alias cb2_out_mode : std_logic_vector(1 downto 0) is pcr(6 downto 5); alias cb1_edge_select : std_logic is pcr(4); alias ca2_is_output : std_logic is pcr(3); alias ca2_edge_select : std_logic is pcr(2); -- for when CA2 is input alias ca2_no_irq_clr : std_logic is pcr(1); -- for when CA2 is input alias ca2_out_mode : std_logic_vector(1 downto 0) is pcr(2 downto 1); alias ca1_edge_select : std_logic is pcr(0); signal ira, irb : std_logic_vector(7 downto 0) := (others => '0'); signal pb_latch_ready : std_logic := '0'; signal pa_latch_ready : std_logic := '0'; signal write_t1c_h : std_logic; signal write_t2c_h : std_logic; signal write_acr : std_logic; signal write_t1_latch_l : std_logic; signal write_t1_latch_h : std_logic; signal write_t2_latch_l : std_logic; signal ca1_c, ca2_c : std_logic; signal cb1_c, cb2_c : std_logic; signal ca1_d, ca2_d : std_logic; signal cb1_d, cb2_d : std_logic; signal set_ca2_low : std_logic; signal set_cb2_low : std_logic; begin irq <= irq_out; irq_out <= '0' when (irq_flags and irq_mask) = "0000000" else '1'; write_t1c_h <= '1' when addr = X"5" and wen='1' else '0'; write_t2c_h <= '1' when addr = X"9" and wen='1' else '0'; write_acr <= '1' when addr = X"B" and wen='1' else '0'; write_t1_latch_l <= '1' when (addr = X"4" or addr = X"6") and wen='1' else '0'; write_t1_latch_h <= '1' when (addr = X"5" or addr = X"7") and wen='1' else '0'; write_t2_latch_l <= '1' when addr = X"8" and wen='1' else '0'; -- input latches ira <= port_a_i when pa_latch_ready='0'; irb <= port_b_i when pb_latch_ready='0'; pa_latch_ready <= '1' when (ca1_event='1') and (pa_latch_en='1') and (pa_latch_ready='0') else '0' when (pa_latch_en='0') or (ren='1' and addr=X"1"); pb_latch_ready <= '1' when (cb1_event='1') and (pb_latch_en='1') and (pb_latch_ready='0') else '0' when (pb_latch_en='0') or (ren='1' and addr=X"0"); ca1_event <= (ca1_c xor ca1_d) and (ca1_d xor ca1_edge_select); ca2_event <= (ca2_c xor ca2_d) and (ca2_d xor ca2_edge_select); cb1_event <= (cb1_c xor cb1_d) and (cb1_d xor cb1_edge_select); cb2_event <= (cb2_c xor cb2_d) and (cb2_d xor cb2_edge_select); ca2_t <= ca2_is_output; cb2_t <= cb2_is_output when serport_en='0' else shift_dir; cb2_o <= hs_cb2_o when serport_en='0' else ser_cb2_o; process(clock) begin if rising_edge(clock) then -- CA1/CA2/CB1/CB2 edge detect flip flops ca1_c <= To_X01(ca1_i); ca2_c <= To_X01(ca2_i); cb1_c <= To_X01(cb1_i); cb2_c <= To_X01(cb2_i); ca1_d <= ca1_c; ca2_d <= ca2_c; cb1_d <= cb1_c; cb2_d <= cb2_c; -- CA2 output logic case ca2_out_mode is when "00" => if ca1_event='1' then ca2_o <= '1'; elsif (ren='1' or wen='1') and addr=X"1" then ca2_o <= '0'; end if; when "01" => if clock_en='1' then ca2_o <= not set_ca2_low; set_ca2_low <= '0'; end if; if (ren='1' or wen='1') and addr=X"1" then if clock_en='1' then ca2_o <= '0'; else set_ca2_low <= '1'; end if; end if; when "10" => ca2_o <= '0'; when "11" => ca2_o <= '1'; when others => null; end case; -- CB2 output logic case cb2_out_mode is when "00" => if cb1_event='1' then hs_cb2_o <= '1'; elsif (ren='1' or wen='1') and addr=X"0" then hs_cb2_o <= '0'; end if; when "01" => if clock_en='1' then hs_cb2_o <= not set_cb2_low; set_cb2_low <= '0'; end if; if (ren='1' or wen='1') and addr=X"0" then if clock_en='1' then hs_cb2_o <= '0'; else set_cb2_low <= '1'; end if; end if; when "10" => hs_cb2_o <= '0'; when "11" => hs_cb2_o <= '1'; when others => null; end case; -- Interrupt logic irq_flags <= irq_flags or irq_events; -- Writes -- if wen='1' then case addr is when X"0" => -- ORB pio_i.prb <= data_in; if cb2_no_irq_clr='0' then cb2_flag <= '0'; end if; cb1_flag <= '0'; when X"1" => -- ORA pio_i.pra <= data_in; if ca2_no_irq_clr='0' then ca2_flag <= '0'; end if; ca1_flag <= '0'; when X"2" => -- DDRB pio_i.ddrb <= data_in; when X"3" => -- DDRA pio_i.ddra <= data_in; when X"4" => -- TA LO counter (write=latch) timer_a_latch(7 downto 0) <= data_in; when X"5" => -- TA HI counter timer_a_latch(15 downto 8) <= data_in; timer_a_flag <= '0'; when X"6" => -- TA LO latch timer_a_latch(7 downto 0) <= data_in; when X"7" => -- TA HI latch timer_a_latch(15 downto 8) <= data_in; timer_a_flag <= '0'; when X"8" => -- TB LO latch timer_b_latch(7 downto 0) <= data_in; when X"9" => -- TB HI counter timer_b_flag <= '0'; when X"A" => -- Serial port serial_flag <= '0'; when X"B" => -- ACR (Auxiliary Control Register) acr <= data_in; when X"C" => -- PCR (Peripheral Control Register) pcr <= data_in; when X"D" => -- IFR irq_flags <= irq_flags and not data_in(6 downto 0); when X"E" => -- IER if data_in(7)='1' then -- set irq_mask <= irq_mask or data_in(6 downto 0); else -- clear irq_mask <= irq_mask and not data_in(6 downto 0); end if; when X"F" => -- ORA no handshake pio_i.pra <= data_in; if ca2_no_irq_clr='0' then ca2_flag <= '0'; end if; ca1_flag <= '0'; when others => null; end case; end if; -- Reads -- case addr is when X"0" => -- ORB --Port B reads its own output register for pins set to output. data_out(0) <= (pio_i.prb(0) and pio_i.ddrb(0)) or (irb(0) and not pio_i.ddrb(0)); data_out(1) <= (pio_i.prb(1) and pio_i.ddrb(1)) or (irb(1) and not pio_i.ddrb(1)); data_out(2) <= (pio_i.prb(2) and pio_i.ddrb(2)) or (irb(2) and not pio_i.ddrb(2)); data_out(3) <= (pio_i.prb(3) and pio_i.ddrb(3)) or (irb(3) and not pio_i.ddrb(3)); data_out(4) <= (pio_i.prb(4) and pio_i.ddrb(4)) or (irb(4) and not pio_i.ddrb(4)); data_out(5) <= (pio_i.prb(5) and pio_i.ddrb(5)) or (irb(5) and not pio_i.ddrb(5)); data_out(6) <= (pio_i.prb(6) and pio_i.ddrb(6)) or (irb(6) and not pio_i.ddrb(6)); data_out(7) <= (((pio_i.prb(7) and pio_i.ddrb(7)) or (irb(7) and not pio_i.ddrb(7))) and (not tmr_a_output_en)) or (tmr_a_output_en and timer_a_out); if cb2_no_irq_clr='0' and ren='1' then cb2_flag <= '0'; end if; if ren='1' then cb1_flag <= '0'; end if; when X"1" => -- ORA data_out <= ira; if ca2_no_irq_clr='0' and ren='1' then ca2_flag <= '0'; end if; if ren='1' then ca1_flag <= '0'; end if; when X"2" => -- DDRB data_out <= pio_i.ddrb; when X"3" => -- DDRA data_out <= pio_i.ddrb; when X"4" => -- TA LO counter data_out <= timer_a_count(7 downto 0); if ren='1' then timer_a_flag <= '0'; end if; when X"5" => -- TA HI counter data_out <= timer_a_count(15 downto 8); when X"6" => -- TA LO latch data_out <= timer_a_latch(7 downto 0); when X"7" => -- TA HI latch data_out <= timer_a_latch(15 downto 8); when X"8" => -- TA LO counter data_out <= timer_b_count(7 downto 0); if ren='1' then timer_b_flag <= '0'; end if; when X"9" => -- TA HI counter data_out <= timer_b_count(15 downto 8); when X"A" => -- SR data_out <= shift_reg; if ren='1' then serial_flag <= '0'; end if; when X"B" => -- ACR data_out <= acr; when X"C" => -- PCR data_out <= pcr; when X"D" => -- IFR data_out <= irq_out & irq_flags; when X"E" => -- IER data_out <= '0' & irq_mask; when X"F" => -- ORA data_out <= ira; when others => null; end case; if reset='1' then pio_i <= pio_default; irq_mask <= (others => '0'); irq_flags <= (others => '0'); acr <= (others => '0'); pcr <= (others => '0'); ca2_o <= '1'; hs_cb2_o <= '1'; set_ca2_low <= '0'; set_cb2_low <= '0'; timer_a_latch <= latch_reset_pattern; timer_b_latch <= latch_reset_pattern(7 downto 0); end if; end if; end process; -- PIO Out select -- --PB7 in timer out mode: When acr bit 7 is 1 then the CPU always reads the timer output on port b reads of bit 7, however if the pin is in input mode then the pin PB7 will not be driven by the timer but will output a 1 as normal for pins set to input. port_a_o <= pio_i.pra; port_b_o(6 downto 0) <= pio_i.prb(6 downto 0); port_b_o(7) <= pio_i.prb(7) when tmr_a_output_en='0' or pio_i.ddrb(7)='0' else timer_a_out; port_a_t <= pio_i.ddra; port_b_t <= pio_i.ddrb; -- Timer A tmr_a: block signal timer_a_reload : std_logic; signal timer_a_post_oneshot : std_logic; begin process(clock) begin if rising_edge(clock) then timer_a_event <= '0'; if clock_en='1' then -- Always count, or load if timer_a_reload = '1' then -- Handle case where the latch is written by the CPU in the clock before reloading. if write_t1_latch_l = '1' then timer_a_count <= timer_a_latch(15 downto 8) & data_in; elsif write_t1_latch_h = '1' then timer_a_count <= data_in & timer_a_latch(7 downto 0); else timer_a_count <= timer_a_latch; end if; timer_a_reload <= '0'; else if timer_a_count = X"0000" then -- Generate an event if we were triggered -- Timer a reloads in both free run and one shot timer_a_reload <= '1'; if tmr_a_freerun = '1' and timer_a_post_oneshot = '0' then timer_a_event <= '1'; -- toggle output timer_a_out <= not timer_a_out; else if (timer_a_post_oneshot = '0') then timer_a_post_oneshot <= '1'; timer_a_event <= '1'; -- Toggle output timer_a_out <= not timer_a_out; end if; end if; end if; -- Timer continues to count in both free run and one shot. timer_a_count <= timer_a_count - X"0001"; end if; end if; if write_t1c_h = '1' then timer_a_count <= data_in & timer_a_latch(7 downto 0); timer_a_reload <= '0'; timer_a_post_oneshot <= '0'; end if; if write_acr = '1' or write_t1c_h = '1' then timer_a_out <= not tmr_a_output_en; end if; if reset='1' then timer_a_out <= '0'; timer_a_count <= latch_reset_pattern; timer_a_reload <= '0'; timer_a_post_oneshot <= '0'; end if; end if; end process; end block tmr_a; -- Timer B tmr_b: block signal timer_b_reload : std_logic; signal timer_b_post_oneshot : std_logic; signal pb6_c, pb6_d : std_logic; begin process(clock) variable timer_b_decrement : std_logic; begin if rising_edge(clock) then timer_b_event <= '0'; timer_b_tick <= '0'; pb6_c <= port_b_i(6); timer_b_decrement := '0'; if clock_en='1' then pb6_d <= pb6_c; if timer_b_reload = '1' then -- Handle case where the latch is written by the CPU in the clock before reloading. if write_t2_latch_l = '1' then timer_b_count <= X"00" & data_in; else timer_b_count <= X"00" & timer_b_latch(7 downto 0); end if; timer_b_reload <= '0'; else if tmr_b_count_mode = '1' then if (pb6_d='0' and pb6_c='1') then timer_b_decrement := '1'; end if; else -- one shot or used for shift register timer_b_decrement := '1'; end if; if timer_b_decrement = '1' then if timer_b_count = X"0000" then if (timer_b_post_oneshot = '0') then timer_b_post_oneshot <= '1'; timer_b_event <= '1'; end if; timer_b_tick <= '1'; case shift_mode_control is when "001" | "101" | "100" => timer_b_reload <= '1'; when others => null; end case; end if; timer_b_count <= timer_b_count - X"0001"; end if; end if; end if; if write_t2c_h = '1' then timer_b_count <= data_in & timer_b_latch(7 downto 0); timer_b_reload <= '0'; timer_b_post_oneshot <= '0'; end if; if reset='1' then timer_b_count <= latch_reset_pattern; timer_b_reload <= '0'; timer_b_post_oneshot <= '0'; end if; end if; end process; end block tmr_b; ser: block signal shift_clock_d : std_logic; signal shift_clock : std_logic; signal shift_tick_r : std_logic; signal shift_tick_f : std_logic; signal cb1_c, cb2_c : std_logic; signal mpu_write : std_logic; signal mpu_read : std_logic; signal bit_cnt : integer range 0 to 7; signal shift_active : std_logic; begin process(clock) begin if rising_edge(clock) then case shift_clk_sel is when "10" => if shift_active='0' then shift_clock <= '1'; elsif clock_en='1' then shift_clock <= not shift_clock; end if; when "00"|"01" => if shift_active='0' then shift_clock <= '1'; elsif timer_b_tick='1' then shift_clock <= not shift_clock; end if; when others => -- "11" shift_clock <= To_X01(cb1_i); end case; shift_clock_d <= shift_clock; end if; end process; shift_tick_r <= not shift_clock_d and shift_clock; shift_tick_f <= shift_clock_d and not shift_clock; cb1_t <= '0' when shift_clk_sel="11" else serport_en; cb1_o <= shift_clock; mpu_write <= wen when addr=X"A" else '0'; mpu_read <= ren when addr=X"A" else '0'; serport_en <= shift_dir or shift_clk_sel(1) or shift_clk_sel(0); process(clock) begin if rising_edge(clock) then cb1_c <= To_X01(cb1_i); cb2_c <= To_X01(cb2_i); if shift_clk_sel = "00" then bit_cnt <= 7; if shift_dir='0' then -- disabled mode shift_active <= '0'; end if; end if; if mpu_read='1' or mpu_write='1' then bit_cnt <= 7; shift_active <= '1'; if mpu_write='1' then shift_reg <= data_in; end if; end if; serial_event <= '0'; if shift_active='1' then if shift_tick_f='1' then ser_cb2_o <= shift_reg(7); end if; if shift_tick_r='1' then if shift_dir='1' then -- output shift_reg <= shift_reg(6 downto 0) & shift_reg(7); else shift_reg <= shift_reg(6 downto 0) & cb2_c; end if; if bit_cnt=0 then serial_event <= '1'; shift_active <= '0'; else bit_cnt <= bit_cnt - 1; end if; end if; end if; if reset='1' then shift_reg <= (others => '1'); shift_active <= '0'; bit_cnt <= 0; ser_cb2_o <= '1'; end if; end if; end process; end block ser; end Gideon;
gpl-3.0
timofonic/1541UltimateII
fpga/cart_slot/vhdl_source/cart_slot_pkg.vhd
3
2562
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package cart_slot_pkg is constant c_cart_c64_mode : unsigned(3 downto 0) := X"0"; constant c_cart_c64_stop : unsigned(3 downto 0) := X"1"; constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2"; constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3"; constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4"; constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5"; constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6"; constant c_cart_kernal_enable : unsigned(3 downto 0) := X"7"; constant c_cart_reu_enable : unsigned(3 downto 0) := X"8"; constant c_cart_reu_size : unsigned(3 downto 0) := X"9"; constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A"; constant c_cart_timing : unsigned(3 downto 0) := X"B"; constant c_cart_phi2_recover : unsigned(3 downto 0) := X"C"; constant c_cart_sampler_enable : unsigned(3 downto 0) := X"E"; constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F"; type t_cart_control is record c64_reset : std_logic; c64_nmi : std_logic; c64_ultimax : std_logic; c64_stop : std_logic; c64_stop_mode : std_logic_vector(1 downto 0); cartridge_type : std_logic_vector(3 downto 0); cartridge_kill : std_logic; kernal_enable : std_logic; reu_enable : std_logic; reu_size : std_logic_vector(2 downto 0); eth_enable : std_logic; sampler_enable : std_logic; swap_buttons : std_logic; timing_addr_valid : unsigned(2 downto 0); phi2_edge_recover : std_logic; end record; type t_cart_status is record c64_stopped : std_logic; clock_detect : std_logic; end record; constant c_cart_control_init : t_cart_control := ( c64_nmi => '0', c64_reset => '0', c64_ultimax => '0', c64_stop => '0', c64_stop_mode => "00", cartridge_type => X"0", cartridge_kill => '0', kernal_enable => '0', reu_enable => '0', reu_size => "111", eth_enable => '0', sampler_enable => '0', timing_addr_valid => "100", phi2_edge_recover => '1', swap_buttons => '1' ); end cart_slot_pkg;
gpl-3.0
timofonic/1541UltimateII
fpga/zpu/vhdl_source/zpu_exec.vhd
5
25864
------------------------------------------------------------------------------ ---- ---- ---- ZPU Exec ---- ---- ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Description: ---- ---- ZPU is a 32 bits small stack cpu. This is a modified version of ---- ---- the zpu_small implementation. This one has a third (8-bit) port for ---- ---- fetching instructions. This modification reduces the LUT size by ---- ---- approximately 10% and increases the performance with 21%. ---- ---- Needs external dual ported memory, plus single cycle external ---- ---- program memory. It also requires a different linker script to ---- ---- place the text segment on a logically different address to stick to ---- ---- the single-, flat memory model programming paradigm. ---- ---- ---- ---- To Do: ---- ---- Add a 'ready' for the external code memory ---- ---- More thorough testing, cleanup code a bit more ---- ---- ---- ---- Author: ---- ---- - Øyvind Harboe, oyvind.harboe zylin.com ---- ---- - Salvador E. Tropea, salvador inti.gob.ar ---- ---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- ---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- ---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- ---- ---- ---- Distributed under the BSD license ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Design unit: zpu_exec(Behave) (Entity and architecture) ---- ---- File name: zpu_exec.vhdl ---- ---- Note: None ---- ---- Limitations: None known ---- ---- Errors: None known ---- ---- Library: work ---- ---- Dependencies: ieee.std_logic_1164 ---- ---- ieee.numeric_std ---- ---- work.zpupkg ---- ---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ---- ---- Language: VHDL ---- ---- Wishbone: No ---- ---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ---- ---- Simulation tools: Modelsim ---- ---- Text editor: UltraEdit 11.00a+ ---- ---- ---- ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.zpupkg.all; entity zpu_exec is generic( g_addr_size : integer := 16; -- Total address space width (incl. I/O) g_stack_size : integer := 12; -- Memory (stack+data) width g_prog_size : integer := 14; -- Program size g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0' port( clk_i : in std_logic; -- System Clock reset_i : in std_logic; -- Synchronous Reset interrupt_i : in std_logic; -- Interrupt break_o : out std_logic; -- Breakpoint opcode executed dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) -- BRAM (data, bss and stack) a_we_o : out std_logic; -- BRAM A port Write Enable a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port a_i : in unsigned(31 downto 0); -- Data from BRAM A port b_we_o : out std_logic; -- BRAM B port Write Enable b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port b_i : in unsigned(31 downto 0); -- Data from BRAM B port -- BRAM (text) c_addr_o : out unsigned(g_prog_size-1 downto 0) := (others => '0'); -- BRAM code address c_i : in unsigned(c_opcode_width-1 downto 0); -- Memory mapped I/O mem_busy_i : in std_logic; data_i : in unsigned(31 downto 0); data_o : out unsigned(31 downto 0); addr_o : out unsigned(g_addr_size-1 downto 0); write_en_o : out std_logic; read_en_o : out std_logic); end entity zpu_exec; architecture Behave of zpu_exec is constant c_max_addr_bit : integer:=g_addr_size-1; -- Stack Pointer initial value: BRAM size-8 constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size); constant SP_START : unsigned(g_stack_size-1 downto 2):= SP_START_1(g_stack_size-1 downto 2); constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O -- Program counter signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0'); -- Stack pointer signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START; signal idim_r : std_logic:='0'; -- BRAM (text, some data, bss and stack) -- a_r is a register for the top of the stack [SP] -- Note: as this is a stack CPU this is a very important register. signal a_we_r : std_logic:='0'; signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0'); signal a_r : unsigned(31 downto 0):=(others => '0'); -- b_r is a register for the next value in the stack [SP+1] -- We also use the B port to fetch instructions. signal b_we_r : std_logic:='0'; signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0'); signal b_r : unsigned(31 downto 0):=(others => '0'); signal posted_wr_a : std_logic; -- State machine. type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or, st_and, st_store, st_read_io, st_write_io, st_add_sp, st_decode, st_resync); signal state : state_t:=st_resync; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "one-hot"; -- Decoded Opcode type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp, dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add, dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store, dec_pop_sp, dec_interrupt); signal d_opcode_r : decode_t; signal d_opcode : decode_t; signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered -- IRQ flag signal in_irq_r : std_logic:='0'; -- I/O space address signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0'); begin -- Dual ported memory interface a_we_o <= a_we_r; a_addr_o <= a_addr_r(g_stack_size-1 downto 2); a_o <= a_r; b_we_o <= b_we_r; b_addr_o <= b_addr_r(g_stack_size-1 downto 2); b_o <= b_r; opcode <= c_i; c_addr_o <= pc_r(g_prog_size-1 downto 0); -- c_addr_o(g_prog_size-1 downto 2) <= pc_r(g_prog_size-1 downto 2); -- c_addr_o(1 downto 0) <= not pc_r(1 downto 0); -- fix big endianess ------------------------- -- Instruction Decoder -- ------------------------- -- Note: We use a separate memory port to fetch opcodes. decode_control: process(opcode) begin if (opcode(7 downto 7)=OPCODE_IM) then d_opcode <= dec_im; elsif (opcode(7 downto 5)=OPCODE_STORESP) then d_opcode <= dec_store_sp; elsif (opcode(7 downto 5)=OPCODE_LOADSP) then d_opcode <= dec_load_sp; elsif (opcode(7 downto 5)=OPCODE_EMULATE) then d_opcode <= dec_emulate; elsif (opcode(7 downto 4)=OPCODE_ADDSP) then d_opcode <= dec_add_sp; else -- OPCODE_SHORT case opcode(3 downto 0) is when OPCODE_BREAK => d_opcode <= dec_break; when OPCODE_PUSHSP => d_opcode <= dec_push_sp; when OPCODE_POPPC => d_opcode <= dec_pop_pc; when OPCODE_ADD => d_opcode <= dec_add; when OPCODE_OR => d_opcode <= dec_or; when OPCODE_AND => d_opcode <= dec_and; when OPCODE_LOAD => d_opcode <= dec_load; when OPCODE_NOT => d_opcode <= dec_not; when OPCODE_FLIP => d_opcode <= dec_flip; when OPCODE_STORE => d_opcode <= dec_store; when OPCODE_POPSP => d_opcode <= dec_pop_sp; when others => -- OPCODE_NOP and others d_opcode <= dec_nop; end case; end if; end process decode_control; data_o <= b_i; opcode_control: process (clk_i) variable sp_offset : unsigned(4 downto 0); begin if rising_edge(clk_i) then break_o <= '0'; write_en_o <= '0'; read_en_o <= '0'; dbg_o.b_inst <= '0'; posted_wr_a <= '0'; if reset_i='1' then state <= st_resync; sp_r <= SP_START; pc_r <= (others => '0'); idim_r <= '0'; a_addr_r <= (others => '0'); b_addr_r <= (others => '0'); a_we_r <= '0'; b_we_r <= '0'; a_r <= (others => '0'); b_r <= (others => '0'); in_irq_r <= '0'; addr_r <= (others => '0'); else -- reset_i/='1' a_we_r <= '0'; b_we_r <= '0'; -- This saves LUTs, by explicitly declaring that the -- a_o can be left at whatever value if a_we_r is -- not set. a_r <= (others => g_dont_care); b_r <= (others => g_dont_care); sp_offset:=(others => g_dont_care); a_addr_r <= (others => g_dont_care); b_addr_r <= (others => g_dont_care); addr_r <= a_i(g_addr_size-1 downto 0); d_opcode_r <= d_opcode; opcode_r <= opcode; if interrupt_i='0' then in_irq_r <= '0'; -- no longer in an interrupt end if; case state is when st_execute => state <= st_fetch; -- At this point: -- b_i contains opcode word -- a_i contains top of stack pc_r <= pc_r+1; -- Debug info (Trace) dbg_o.b_inst <= '1'; dbg_o.pc <= (others => '0'); dbg_o.pc(g_addr_size-1 downto 0) <= pc_r; dbg_o.opcode <= opcode_r; dbg_o.sp <= (others => '0'); dbg_o.sp(g_stack_size-1 downto 2) <= sp_r; dbg_o.stk_a <= a_i; dbg_o.stk_b <= b_i; -- During the next cycle we'll be reading the next opcode sp_offset(4):=not opcode_r(4); sp_offset(3 downto 0):=opcode_r(3 downto 0); idim_r <= '0'; -------------------- -- Execution Unit -- -------------------- case d_opcode_r is when dec_interrupt => -- Not a real instruction, but an interrupt -- Push(PC); PC=32 sp_r <= sp_r-1; a_addr_r <= sp_r-1; a_we_r <= '1'; a_r <= (others => g_dont_care); a_r(c_max_addr_bit downto 0) <= pc_r; -- Jump to ISR pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address --report "ZPU jumped to interrupt!" severity note; when dec_im => idim_r <= '1'; a_we_r <= '1'; if idim_r='0' then -- First IM -- Push the 7 bits (extending the sign) sp_r <= sp_r-1; a_addr_r <= sp_r-1; a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32)); else -- Next IMs, shift the word and put the new value in the lower -- bits a_addr_r <= sp_r; a_r(31 downto 7) <= a_i(24 downto 0); a_r(6 downto 0) <= opcode_r(6 downto 0); end if; when dec_store_sp => -- [SP+Offset]=Pop() b_we_r <= '1'; b_addr_r <= sp_r+sp_offset; b_r <= a_i; sp_r <= sp_r+1; state <= st_resync; when dec_load_sp => -- Push([SP+Offset]) sp_r <= sp_r-1; a_addr_r <= sp_r+sp_offset; posted_wr_a <= '1'; state <= st_resync; when dec_emulate => -- Push(PC+1), PC=Opcode[4:0]*32 sp_r <= sp_r-1; a_we_r <= '1'; a_addr_r <= sp_r-1; a_r <= (others => g_dont_care); a_r(c_max_addr_bit downto 0) <= pc_r+1; -- Jump to NUM*32 -- The emulate address is: -- 98 7654 3210 -- 0000 00aa aaa0 0000 pc_r <= (others => '0'); pc_r(9 downto 5) <= opcode_r(4 downto 0); when dec_add_sp => -- Push(Pop()+[SP+Offset]) a_addr_r <= sp_r; b_addr_r <= sp_r+sp_offset; state <= st_add_sp; when dec_break => --report "Break instruction encountered" severity failure; break_o <= '1'; when dec_push_sp => -- Push(SP) sp_r <= sp_r-1; a_we_r <= '1'; a_addr_r <= sp_r-1; a_r <= (others => '0'); a_r(sp_r'range) <= sp_r; when dec_pop_pc => -- Pop(PC) pc_r <= a_i(pc_r'range); sp_r <= sp_r+1; state <= st_resync; when dec_add => -- Push(Pop()+Pop()) sp_r <= sp_r+1; state <= st_add; when dec_or => -- Push(Pop() or Pop()) sp_r <= sp_r+1; state <= st_or; when dec_and => -- Push(Pop() and Pop()) sp_r <= sp_r+1; state <= st_and; when dec_load => -- Push([Pop()]) if a_i(IO_BIT)='1' then addr_r <= a_i(g_addr_size-1 downto 0); read_en_o <= '1'; state <= st_read_io; else a_addr_r <= a_i(a_addr_r'range); posted_wr_a <= '1'; state <= st_resync; end if; when dec_not => -- Push(not(Pop())) a_addr_r <= sp_r; a_we_r <= '1'; a_r <= not a_i; when dec_flip => -- Push(flip(Pop())) a_addr_r <= sp_r; a_we_r <= '1'; for i in 0 to 31 loop a_r(i) <= a_i(31-i); end loop; when dec_store => -- a=Pop(), b=Pop(), [a]=b b_addr_r <= sp_r+1; sp_r <= sp_r+1; if a_i(IO_BIT)='1' then state <= st_write_io; else state <= st_store; end if; when dec_pop_sp => -- SP=Pop() sp_r <= a_i(g_stack_size-1 downto 2); state <= st_resync; when dec_nop => -- Default, keep addressing to of the stack (A) a_addr_r <= sp_r; when others => null; end case; when st_read_io => -- Wait until memory I/O isn't busy a_addr_r <= sp_r; a_r <= data_i; if mem_busy_i='0' then state <= st_fetch; a_we_r <= '1'; end if; when st_write_io => -- [A]=B sp_r <= sp_r+1; write_en_o <= '1'; addr_r <= a_i(g_addr_size-1 downto 0); state <= st_write_io_done; when st_write_io_done => -- Wait until memory I/O isn't busy if mem_busy_i='0' then state <= st_resync; end if; when st_fetch => -- We need to resync. During this cycle -- we'll fetch the opcode @ pc and thus it will -- be available for st_execute in the next cycle -- At this point a_i contains the value that is from the top of the stack -- or that was fetched from the stack with an offset (loadsp) a_we_r <= posted_wr_a; a_r <= a_i; a_addr_r <= sp_r; b_addr_r <= sp_r+1; state <= st_decode; when st_decode => if interrupt_i='1' and in_irq_r='0' and idim_r='0' then -- We got an interrupt, execute interrupt instead of next instruction in_irq_r <= '1'; d_opcode_r <= dec_interrupt; end if; -- during the st_execute cycle we'll be fetching SP+1 a_addr_r <= sp_r; b_addr_r <= sp_r+1; state <= st_execute; when st_store => sp_r <= sp_r+1; a_we_r <= '1'; a_addr_r <= a_i(g_stack_size-1 downto 2); a_r <= b_i; state <= st_resync; when st_add_sp => state <= st_add; when st_add => a_addr_r <= sp_r; a_we_r <= '1'; a_r <= a_i+b_i; state <= st_fetch; when st_or => a_addr_r <= sp_r; a_we_r <= '1'; a_r <= a_i or b_i; state <= st_fetch; when st_and => a_addr_r <= sp_r; a_we_r <= '1'; a_r <= a_i and b_i; state <= st_fetch; when st_resync => a_addr_r <= sp_r; state <= st_fetch; posted_wr_a <= posted_wr_a; -- keep when others => null; end case; end if; -- else reset_i/='1' end if; -- rising_edge(clk_i) end process opcode_control; addr_o <= addr_r; end architecture Behave; -- Entity: zpu_exec
gpl-3.0
timofonic/1541UltimateII
fpga/io/sigma_delta_dac/vhdl_sim/sine_osc_tb.vhd
5
931
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sine_osc_tb is end sine_osc_tb; architecture tb of sine_osc_tb is signal clock : std_logic := '0'; signal reset : std_logic; signal sine : signed(15 downto 0); signal cosine : signed(15 downto 0); begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; osc: entity work.sine_osc port map ( clock => clock, reset => reset, sine => sine, cosine => cosine ); process variable n: time; variable p: integer; begin wait until reset='0'; n := now; while true loop wait until sine(15)='1'; p := (now - n) / 20 ns; n := now; report "Period: " & integer'image(p) & " samples" severity note; end loop; end process; end tb;
gpl-3.0
timofonic/1541UltimateII
target/simulation/packages/vhdl_bfm/wave_pkg.vhd
5
5471
------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 - Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Wave package ------------------------------------------------------------------------------- -- File : wave_pkg.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This package provides ways to write (and maybe in future read) -- .wav files. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tl_flat_memory_model_pkg.all; use work.tl_file_io_pkg.all; package wave_pkg is type t_wave_channel is record number_of_samples : integer; memory : h_mem_object; end record; type t_wave_channel_array is array(natural range <>) of t_wave_channel; procedure open_channel(chan : out t_wave_channel); procedure push_sample(chan : inout t_wave_channel; sample : integer); procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array); end package; package body wave_pkg is procedure open_channel(chan : out t_wave_channel) is variable ch : t_wave_channel; begin register_mem_model("path", "channel", ch.memory); ch.number_of_samples := 0; chan := ch; end procedure; procedure push_sample(chan : inout t_wave_channel; sample : integer) is variable s : integer; begin s := sample; if s > 32767 then s := 32767; end if; if s < -32768 then s := -32768; end if; write_memory_int(chan.memory, chan.number_of_samples, s); chan.number_of_samples := chan.number_of_samples + 1; end procedure; procedure write_vector_le(x : std_logic_vector; file f : t_binary_file; r : inout t_binary_file_rec) is variable bytes : integer := (x'length + 7) / 8; variable xa : std_logic_vector(7+bytes*8 downto 0); begin xa := (others => '0'); xa(x'length-1 downto 0) := x; for i in 0 to bytes-1 loop write_byte(f, xa(i*8+7 downto i*8), r); end loop; end procedure; procedure write_int_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is variable x_slv : std_logic_vector(31 downto 0); begin x_slv := std_logic_vector(to_signed(x, 32)); write_vector_le(x_slv, f, r); end procedure; procedure write_short_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is variable x_slv : std_logic_vector(15 downto 0); begin x_slv := std_logic_vector(to_signed(x, 16)); write_vector_le(x_slv, f, r); end procedure; procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array) is file myfile : t_binary_file; variable myrec : t_binary_file_rec; variable stat : file_open_status; variable file_size : integer; variable data_size : integer; variable max_length : integer; begin -- open file file_open(stat, myfile, name, write_mode); assert (stat = open_ok) report "Could not open file " & name & " for writing." severity failure; init_record(myrec); max_length := 0; for i in channels'range loop if channels(i).number_of_samples > max_length then max_length := channels(i).number_of_samples; end if; end loop; data_size := (max_length * channels'length * 2); file_size := 12 + 16 + 8 + data_size; -- header write_vector_le(X"46464952", myfile, myrec); -- "RIFF" write_int_le (file_size-8, myfile, myrec); write_vector_le(X"45564157", myfile, myrec); -- "WAVE" -- chunk header write_vector_le(X"20746D66", myfile, myrec); -- "fmt " write_int_le (16, myfile, myrec); write_short_le (1, myfile, myrec); -- compression code = uncompressed write_short_le (channels'length, myfile, myrec); write_int_le (rate, myfile, myrec); -- sample rate write_int_le (rate * channels'length * 2, myfile, myrec); -- Bps write_short_le (channels'length * 2, myfile, myrec); -- alignment write_short_le (16, myfile, myrec); -- bits per sample write_vector_le(X"61746164", myfile, myrec); -- "data" write_int_le (data_size, myfile, myrec); -- now write out all data! for i in 0 to max_length-1 loop for j in channels'range loop write_short_le(read_memory_int(channels(j).memory, i), myfile, myrec); end loop; end loop; purge(myfile, myrec); file_close(myfile); end procedure; end;
gpl-3.0
timofonic/1541UltimateII
fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_v4.vhd
5
14070
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tl_flat_memory_model_pkg.all; use work.mem_bus_pkg.all; use work.cart_slot_pkg.all; use work.io_bus_pkg.all; use work.io_bus_bfm_pkg.all; use work.command_if_pkg.all; entity harness_v4 is end harness_v4; architecture tb of harness_v4 is constant c_uart_divisor : natural := 434; signal PHI2 : std_logic := '0'; signal RSTn : std_logic := 'H'; signal DOTCLK : std_logic := '1'; signal BUFFER_ENn : std_logic := '1'; signal LB_ADDR : std_logic_vector(14 downto 0); signal LB_DATA : std_logic_vector(7 downto 0) := X"00"; signal BA : std_logic := '0'; signal DMAn : std_logic := '1'; signal EXROMn : std_logic; signal GAMEn : std_logic; signal ROMHn : std_logic := '1'; signal ROMLn : std_logic := '1'; signal IO1n : std_logic := '1'; signal IO2n : std_logic := '1'; signal IRQn : std_logic := '1'; signal NMIn : std_logic := '1'; signal MEM_WEn : std_logic; signal MEM_OEn : std_logic; signal SDRAM_CSn : std_logic; signal SDRAM_RASn : std_logic; signal SDRAM_CASn : std_logic; signal SDRAM_WEn : std_logic; signal SDRAM_CKE : std_logic; signal SDRAM_CLK : std_logic; signal SDRAM_DQM : std_logic; signal PWM_OUT : std_logic_vector(1 downto 0); signal IEC_ATN : std_logic := '1'; signal IEC_DATA : std_logic := '1'; signal IEC_CLOCK : std_logic := '1'; signal IEC_RESET : std_logic := '1'; signal IEC_SRQ_IN : std_logic := '1'; signal DISK_ACTn : std_logic; -- activity LED signal CART_LEDn : std_logic; signal SDACT_LEDn : std_logic; signal MOTOR_LEDn : std_logic; signal UART_TXD : std_logic; signal UART_RXD : std_logic := '1'; signal SD_SSn : std_logic; signal SD_CLK : std_logic; signal SD_MOSI : std_logic; signal SD_MISO : std_logic := '1'; signal SD_WP : std_logic := '1'; signal SD_CARDDETn : std_logic := '1'; signal BUTTON : std_logic_vector(2 downto 0) := "000"; signal SLOT_ADDR : std_logic_vector(15 downto 0); signal SLOT_DATA : std_logic_vector(7 downto 0); signal RWn : std_logic := '1'; signal CAS_MOTOR : std_logic := '1'; signal CAS_SENSE : std_logic := '0'; signal CAS_READ : std_logic := '0'; signal CAS_WRITE : std_logic := '0'; signal RTC_CS : std_logic; signal RTC_SCK : std_logic; signal RTC_MOSI : std_logic; signal RTC_MISO : std_logic := '1'; signal FLASH_CSn : std_logic; signal FLASH_SCK : std_logic; signal FLASH_MOSI : std_logic; signal FLASH_MISO : std_logic := '1'; signal ULPI_CLOCK : std_logic := '0'; signal ULPI_RESET : std_logic := '0'; signal ULPI_NXT : std_logic := '0'; signal ULPI_STP : std_logic; signal ULPI_DIR : std_logic := '0'; signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H'); signal sys_clock : std_logic := '0'; signal sys_reset : std_logic := '0'; signal sys_shifted : std_logic := '0'; signal rx_char : std_logic_vector(7 downto 0); signal rx_char_d : std_logic_vector(7 downto 0); signal rx_ack : std_logic; signal tx_char : std_logic_vector(7 downto 0) := X"00"; signal tx_done : std_logic; signal do_tx : std_logic := '0'; shared variable dram : h_mem_object; shared variable ram : h_mem_object; -- shared variable rom : h_mem_object; -- shared variable bram : h_mem_object; -- memory controller interconnect signal memctrl_inhibit : std_logic; signal mem_req : t_mem_req; signal mem_resp : t_mem_resp; signal io_req : t_io_req; signal io_resp : t_io_resp; begin mut: entity work.ultimate_logic generic map ( g_simulation => true ) port map ( sys_clock => sys_clock, sys_reset => sys_reset, PHI2 => PHI2, DOTCLK => DOTCLK, RSTn => RSTn, BUFFER_ENn => BUFFER_ENn, SLOT_ADDR => SLOT_ADDR, SLOT_DATA => SLOT_DATA, RWn => RWn, BA => BA, DMAn => DMAn, EXROMn => EXROMn, GAMEn => GAMEn, ROMHn => ROMHn, ROMLn => ROMLn, IO1n => IO1n, IO2n => IO2n, IRQn => IRQn, NMIn => NMIn, -- local bus side mem_inhibit => memctrl_inhibit, --memctrl_idle => memctrl_idle, mem_req => mem_req, mem_resp => mem_resp, -- io bus for simulation sim_io_req => io_req, sim_io_resp => io_resp, -- PWM outputs (for audio) PWM_OUT => PWM_OUT, -- IEC bus IEC_ATN => IEC_ATN, IEC_DATA => IEC_DATA, IEC_CLOCK => IEC_CLOCK, IEC_RESET => IEC_RESET, IEC_SRQ_IN => IEC_SRQ_IN, DISK_ACTn => DISK_ACTn, -- activity LED CART_LEDn => CART_LEDn, SDACT_LEDn => SDACT_LEDn, MOTOR_LEDn => MOTOR_LEDn, -- Debug UART UART_TXD => UART_TXD, UART_RXD => UART_RXD, -- SD Card Interface SD_SSn => SD_SSn, SD_CLK => SD_CLK, SD_MOSI => SD_MOSI, SD_MISO => SD_MISO, SD_CARDDETn => SD_CARDDETn, -- Cassette Interface CAS_MOTOR => CAS_MOTOR, CAS_SENSE => CAS_SENSE, CAS_READ => CAS_READ, CAS_WRITE => CAS_WRITE, -- RTC Interface RTC_CS => RTC_CS, RTC_SCK => RTC_SCK, RTC_MOSI => RTC_MOSI, RTC_MISO => RTC_MISO, -- Flash Interface FLASH_CSn => FLASH_CSn, FLASH_SCK => FLASH_SCK, FLASH_MOSI => FLASH_MOSI, FLASH_MISO => FLASH_MISO, -- USB Interface (ULPI) ULPI_CLOCK => ULPI_CLOCK, ULPI_RESET => ULPI_RESET, ULPI_NXT => ULPI_NXT, ULPI_STP => ULPI_STP, ULPI_DIR => ULPI_DIR, ULPI_DATA => ULPI_DATA, -- Buttons BUTTON => BUTTON ); i_memctrl: entity work.ext_mem_ctrl_v4 generic map ( g_simulation => true, A_Width => 15 ) port map ( clock => sys_clock, clk_shifted => sys_shifted, reset => sys_reset, inhibit => memctrl_inhibit, is_idle => open, --memctrl_idle, req => mem_req, resp => mem_resp, SDRAM_CSn => SDRAM_CSn, SDRAM_RASn => SDRAM_RASn, SDRAM_CASn => SDRAM_CASn, SDRAM_WEn => SDRAM_WEn, SDRAM_CKE => SDRAM_CKE, SDRAM_CLK => SDRAM_CLK, MEM_A => LB_ADDR, MEM_D => LB_DATA ); sys_clock <= not sys_clock after 10 ns; -- 50 MHz sys_reset <= '1', '0' after 100 ns; sys_shifted <= transport sys_clock after 3 ns; ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz ULPI_RESET <= '1', '0' after 100 ns; PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us; i_ulpi_phy: entity work.ulpi_phy_bfm generic map ( g_rx_interval => 100000 ) port map ( clock => ULPI_CLOCK, reset => ULPI_RESET, ULPI_DATA => ULPI_DATA, ULPI_DIR => ULPI_DIR, ULPI_NXT => ULPI_NXT, ULPI_STP => ULPI_STP ); i_io_bfm: entity work.io_bus_bfm generic map ( g_name => "io_bfm" ) port map ( clock => sys_clock, req => io_req, resp => io_resp ); process begin bind_mem_model("intram", ram); bind_mem_model("dram", dram); load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000"); -- 1st boot will try to load the 2nd bootloader and application from flash. In simulation this is a cumbersome -- process. It would work with a good model of the serial spi flash, but since it is not included in the public -- archive, you need to create a special boot image that just jumps to 0x20000 and load the application here to dram: load_memory("../../software/ultimate/result/ultimate.bin", dram, X"00020000"); wait; end process; SLOT_DATA <= (others => 'H'); ROMHn <= '1'; ROMLn <= not PHI2 after 50 ns; IO1n <= '1'; IO2n <= '1'; process begin SLOT_ADDR <= X"D400"; RWn <= '1'; while true loop wait until PHI2 = '0'; --SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1); SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1); RWn <= '1'; wait until PHI2 = '0'; RWn <= '0'; end loop; end process; process begin BA <= '1'; for i in 0 to 100 loop wait until PHI2='0'; end loop; BA <= '0'; for i in 0 to 10 loop wait until PHI2='0'; end loop; end process; dram_bfm: entity work.dram_model_8 generic map( g_given_name => "dram", g_cas_latency => 2, g_burst_len_r => 1, g_burst_len_w => 1, g_column_bits => 10, g_row_bits => 13, g_bank_bits => 2 ) port map ( CLK => SDRAM_CLK, CKE => SDRAM_CKE, A => LB_ADDR(12 downto 0), BA => LB_ADDR(14 downto 13), CSn => SDRAM_CSn, RASn => SDRAM_RASn, CASn => SDRAM_CASn, WEn => SDRAM_WEn, DQM => SDRAM_DQM, DQ => LB_DATA); i_rx: entity work.rx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, rxd => UART_TXD, rxchar => rx_char, rx_ack => rx_ack ); i_tx: entity work.tx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, dotx => do_tx, txchar => tx_char, done => tx_done, txd => UART_RXD ); process(sys_clock) begin if rising_edge(sys_clock) then if rx_ack='1' then rx_char_d <= rx_char; end if; end if; end process; -- procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object); -- procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object); -- procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)); -- procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)); -- constant c_cart_c64_mode : unsigned(3 downto 0) := X"0"; -- constant c_cart_c64_stop : unsigned(3 downto 0) := X"1"; -- constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2"; -- constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3"; -- constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4"; -- constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5"; -- constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6"; -- constant c_cart_reu_enable : unsigned(3 downto 0) := X"8"; -- constant c_cart_reu_size : unsigned(3 downto 0) := X"9"; -- constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A"; -- constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F"; process variable io : p_io_bus_bfm_object; begin wait until sys_reset='0'; wait until sys_clock='1'; bind_io_bus_bfm("io_bfm", io); io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset io_write(io, X"44000" + c_cif_io_slot_base, X"7E"); io_write(io, X"44000" + c_cif_io_slot_enable, X"01"); wait for 6 us; wait until sys_clock='1'; io_write(io, X"42002", X"42"); wait; end process; process procedure send_char(i: std_logic_vector(7 downto 0)) is begin if tx_done /= '1' then wait until tx_done = '1'; end if; wait until sys_clock='1'; tx_char <= i; do_tx <= '1'; wait until tx_done = '0'; wait until sys_clock='1'; do_tx <= '0'; end procedure; procedure send_string(i : string) is variable b : std_logic_vector(7 downto 0); begin for n in i'range loop b := std_logic_vector(to_unsigned(character'pos(i(n)), 8)); send_char(b); end loop; send_char(X"0d"); send_char(X"0a"); end procedure; begin wait for 2 ms; --send_string("wd 4005000 12345678"); send_string("run"); -- send_string("m 100000"); -- send_string("w 400000F 4"); wait; end process; -- check timing data process(PHI2) begin if falling_edge(PHI2) then assert SLOT_DATA'last_event >= 189 ns report "Timing error on C64 bus." severity error; end if; end process; end tb;
gpl-3.0
etingi01/MIPS_with_multiplier-VHDL-
My_32bitAdder_948282.vhd
1
2674
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:53:44 11/17/2013 -- Design Name: -- Module Name: My_32bitAdder_948282 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity My_32bitAdder_948282 is Port ( A_reg : in STD_LOGIC_VECTOR (31 downto 0); B_reg : in STD_LOGIC_VECTOR (31 downto 0); CarryIn : in STD_LOGIC; CarryOut : out STD_LOGIC; Result : out STD_LOGIC_VECTOR (31 downto 0)); end My_32bitAdder_948282; architecture Behavioral of My_32bitAdder_948282 is component My_4bitAdder_948282 is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); R : out STD_LOGIC_VECTOR (3 downto 0); Carry_In : in STD_LOGIC; Carry_Out : out STD_LOGIC); end component; signal sig1: std_logic; signal sig2, sig3, sig4, sig5, sig6, sig7: std_logic; begin u0: My_4bitAdder_948282 port map (A=>A_reg(3 downto 0), B=>B_reg(3 downto 0), Carry_In=>CarryIn, Carry_Out=>sig1, R=>Result(3 downto 0)); u1: My_4bitAdder_948282 port map (A=>A_reg(7 downto 4), B=>B_reg(7 downto 4), Carry_In=>sig1, Carry_Out=>sig2, R=>Result(7 downto 4)); u2: My_4bitAdder_948282 port map (A=>A_reg(11 downto 8), B=>B_reg(11 downto 8), Carry_In=>sig2, Carry_Out=>sig3, R=>Result(11 downto 8)); u3: My_4bitAdder_948282 port map (A=>A_reg(15 downto 12), B=>B_reg(15 downto 12), Carry_In=>sig3, Carry_Out=>sig4, R=>Result(15 downto 12)); u4: My_4bitAdder_948282 port map (A=>A_reg(19 downto 16), B=>B_reg(19 downto 16), Carry_In=>sig4, Carry_Out=>sig5, R=>Result(19 downto 16)); u5: My_4bitAdder_948282 port map (A=>A_reg(23 downto 20), B=>B_reg(23 downto 20), Carry_In=>sig5, Carry_Out=>sig6, R=>Result(23 downto 20)); u6: My_4bitAdder_948282 port map (A=>A_reg(27 downto 24), B=>B_reg(27 downto 24), Carry_In=>sig6, Carry_Out=>sig7, R=>Result(27 downto 24)); u7: My_4bitAdder_948282 port map (A=>A_reg(31 downto 28), B=>B_reg(31 downto 28), Carry_In=>sig7, Carry_Out=>CarryOut, R=>Result(31 downto 28)); end Behavioral;
gpl-3.0
etingi01/MIPS_with_multiplier-VHDL-
myPCRegister.vhd
1
1337
---------------------------------------------------------------------------------- -- Company: University of Cyprus, Department of Computer Science -- Engineer: Dr. Petros Panayi -- -- Create Date: 23:20:47 03/23/2007 -- Design Name: -- Module Name: myPCRegister - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity myPCRegister is Port ( PC_INPUT : in STD_LOGIC_VECTOR (9 downto 0); PC_OUTPUT : out STD_LOGIC_VECTOR (9 downto 0); clk : in STD_LOGIC; RESET : in STD_LOGIC); end myPCRegister; architecture Behavioral of myPCRegister is signal TEMP_PC: STD_LOGIC_VECTOR (9 downto 0); begin process (clk, RESET) begin if RESET = '1' then TEMP_PC <= B"0000000000"; else if RISING_EDGE(clk) then TEMP_PC <= PC_INPUT; end if; end if; end process; PC_OUTPUT <= TEMP_PC; end Behavioral;
gpl-3.0
etingi01/MIPS_with_multiplier-VHDL-
My_ALU_tb_948282.vhd
1
2652
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:46:09 11/19/2013 -- Design Name: -- Module Name: C:/Users/etingi01/Mips32_948282_19.11.2013/My_ALU_tb_948282.vhd -- Project Name: Mips32_948282_19.11.2013 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: My_ALU_948282 -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY My_ALU_tb_948282 IS END My_ALU_tb_948282; ARCHITECTURE behavior OF My_ALU_tb_948282 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT My_ALU_948282 PORT( Alu0 : IN std_logic; Alu1 : IN std_logic; A_alu : IN std_logic_vector(31 downto 0); B_alu : IN std_logic_vector(31 downto 0); B_Inv : IN std_logic; Result_alu : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs signal Alu0 : std_logic := '0'; signal Alu1 : std_logic := '0'; signal B_Inv : std_logic := '0'; signal A_alu : std_logic_vector(31 downto 0) := (others => '0'); signal B_alu : std_logic_vector(31 downto 0) := (others => '0'); --Outputs signal Result_alu : std_logic_vector(31 downto 0); -- No clocks detected in port list. Replace <clock> below with -- appropriate port name constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: My_ALU_948282 PORT MAP ( Alu0 => Alu0, Alu1 => Alu1, A_alu => A_alu, B_alu => B_alu, B_Inv => B_Inv, Result_alu => Result_alu ); -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clk_period*10; Alu0<='0'; Alu1<='1'; A_alu<="00000000000000000000000000001000"; B_alu<="00000000000000000000000000000011"; B_Inv<='1'; wait; end process; END;
gpl-3.0
etingi01/MIPS_with_multiplier-VHDL-
My_4x1Mux_948282.vhd
1
2478
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:25:38 11/17/2013 -- Design Name: -- Module Name: My_4x1Mux_948282 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity My_4x1Mux_948282 is Port ( Sel1 : in STD_LOGIC; Sel2 : in STD_LOGIC; A_mux : in STD_LOGIC; B_mux : in STD_LOGIC; C_mux : in STD_LOGIC; D_mux : in STD_LOGIC; Result : out STD_LOGIC); end My_4x1Mux_948282; architecture Behavioral of My_4x1Mux_948282 is component My_And_948282 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; R : out STD_LOGIC); end component; component My_Or_948282 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; R : out STD_LOGIC); end component; component myNOT_948282 is Port ( i1 : in STD_LOGIC; o1 : out STD_LOGIC); end component; signal sig1: std_logic; signal sig2, sig3, sig4, sig5, sig6, sig7, sig8, sig9, sig10, sig11, sig12, sig13: std_logic; begin u0: MyNOT_948282 port map (i1=>Sel1, o1=>sig1); u1: MyNOT_948282 port map (i1=>Sel2, o1=>sig2); u2: My_And_948282 port map (A=>A_mux, B=>sig1, R=>sig3); u3: My_And_948282 port map (A=>sig3, B=>sig2, R=>sig4);-- sig4 First in or u4: My_And_948282 port map (A=>B_mux, B=>sig1, R=>sig5); u5: My_And_948282 port map (A=>sig5, B=>Sel2, R=>sig6);--sig5 in or u6: My_And_948282 port map (A=>C_mux, B=>Sel1, R=>sig7); u7: My_And_948282 port map (A=>sig7, B=>sig2, R=>sig8);--sig8 in or u8: My_And_948282 port map (A=>D_mux, B=>Sel1, R=>sig9); u9: My_And_948282 port map (A=>sig9, B=>Sel2, R=>sig10); --sig10 in or u10: My_Or_948282 port map (A=>sig4, B=>sig6, R=>sig11); --sig11 u11: My_Or_948282 port map (A=>sig8, B=>sig10, R=>sig12);--sig12 u12: My_Or_948282 port map (A=>sig11, B=>sig12, R=>Result); end Behavioral;
gpl-3.0
kuruoujou/ECE-337-USB-Data-Sniffer
source/tb_computerInterceptor.vhd
1
4316
-- $Id: $ -- File name: tb_computerInterceptor.vhd -- Created: 4/19/2012 -- Author: John Wyant -- Lab Section: 337-02 -- Version: 1.0 Initial Test Bench library ieee; --library gold_lib; --UNCOMMENT if you're using a GOLD model use ieee.std_logic_1164.all; use ieee.numeric_std.all; --use gold_lib.all; --UNCOMMENT if you're using a GOLD model entity tb_computerInterceptor is generic (Period : Time := 70 ns); end tb_computerInterceptor; architecture TEST of tb_computerInterceptor is function UINT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER ) return STD_LOGIC_VECTOR is begin return std_logic_vector(to_unsigned(X, NumBits)); end; function STD_LOGIC_TO_UINT( X: std_logic_vector) return integer is begin return to_integer(unsigned(x)); end; component computerInterceptor PORT( usbClk : in std_logic; rst : in std_logic; computerDataPlus : in std_logic; computerDataMinus : in std_logic; computerDataPlusOutput : out std_logic; computerDataMinusOutput : out std_logic; computerLock : out std_logic ); end component; -- Insert signals Declarations here signal usbClk : std_logic; signal rst : std_logic; signal computerDataPlus : std_logic; signal computerDataMinus : std_logic; signal computerDataPlusOutput : std_logic; signal computerDataMinusOutput : std_logic; signal computerLock : std_logic; -- signal <name> : <type>; begin CLKGEN: process variable usbClk_tmp: std_logic := '0'; begin usbClk_tmp := not usbClk_tmp; usbClk <= usbClk_tmp; wait for Period/2; end process; DUT: computerInterceptor port map( usbClk => usbClk, rst => rst, computerDataPlus => computerDataPlus, computerDataMinus => computerDataMinus, computerDataPlusOutput => computerDataPlusOutput, computerDataMinusOutput => computerDataMinusOutput, computerLock => computerLock ); -- GOLD: <GOLD_NAME> port map(<put mappings here>); process begin -- Insert TEST BENCH Code Here rst <= '1'; computerDataPlus <= '1'; computerDataMinus <= '1'; wait for 70 ns; rst <= '0'; wait for 70 ns; rst <= '1'; computerDataPlus <= '0'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 140 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; computerDataMinus <= '0'; wait for 70 ns; computerDataPlus <= '0'; computerDataMinus <= '1'; wait for 70 ns; computerDataPlus <= '1'; wait for 700 ns; end process; end TEST;
gpl-3.0
etingi01/MIPS_with_multiplier-VHDL-
myHiLoRegister_tb.vhd
1
2457
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:02:22 11/04/2008 -- Design Name: myHiLoRegister -- Module Name: C:/temp/VHDLFall2008/MIPS32Mult/myHiLoRegister_tb.vhd -- Project Name: MIPS32Mult -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: myHiLoRegister -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY myHiLoRegister_tb_vhd IS END myHiLoRegister_tb_vhd; ARCHITECTURE behavior OF myHiLoRegister_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT myHiLoRegister PORT( INPUT : IN std_logic_vector(63 downto 0); writeData : IN std_logic; clk : IN std_logic; RESET : IN std_logic; OUTPUT : OUT std_logic_vector(63 downto 0) ); END COMPONENT; --Inputs SIGNAL writeData : std_logic := '0'; SIGNAL clk : std_logic := '0'; SIGNAL RESET : std_logic := '0'; SIGNAL INPUT : std_logic_vector(63 downto 0) := (others=>'0'); --Outputs SIGNAL OUTPUT : std_logic_vector(63 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: myHiLoRegister PORT MAP( INPUT => INPUT, OUTPUT => OUTPUT, writeData => writeData, clk => clk, RESET => RESET ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; -- Place stimulus here -- Write the data into the HiLo Register INPUT <= X"AA55AA55AA55AA55"; writeData <= '1'; clk <= '1'; wait for 100 ns; -- The data are still available even after many clock cycles INPUT <= X"0000000000000000"; writeData <= '0'; clk <= '0'; wait for 100 ns; clk <= '1'; wait for 100 ns; clk <= '0'; wait for 100 ns; clk <= '1'; wait for 100 ns; clk <= '0'; wait for 100 ns; clk <= '1'; wait for 100 ns; wait; -- will wait forever END PROCESS; END;
gpl-3.0
kuruoujou/ECE-337-USB-Data-Sniffer
source/SpiClkDivide.vhd
1
2754
-- $Id: $ -- File name: clk_divide -- Created: 2/19/2012 -- Author: David Kauer -- Lab Section: 2 -- Version: 1.0 Initial Design Entry -- Description: System Clock Divider LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity SpiClkDivide is generic( spiDivSlow : std_logic_vector(8 downto 0) := "101100101"; -- 357, clocks downto 400 kHz spiDivFast : std_logic_vector(1 downto 0) := "11"; -- 3, clocks downto 28 MHz-ish sclPol : integer := 0; sclPha : integer := 0 ); port ( clk : in std_logic; resetN : in std_logic; sclEnable : in std_logic; sclSpeed : in std_logic; tsrEnable : out std_logic; scl : out std_logic ); end SpiClkDivide; architecture SpiClkDivide_arch of SpiClkDivide is signal count,nextcount : std_logic_vector(8 downto 0); signal prevSclEnable,nextPrevSclEnable : std_logic; signal nextSclReg,sclReg : std_logic; begin nextPrevSclEnable <= sclEnable; scl <= sclReg; process(clk,resetN) begin if resetN = '0' then count <= (others => '0'); prevSclEnable <= '0'; sclReg <= '0'; elsif rising_edge(clk) then count <= nextcount; prevSclEnable <= nextPrevSclEnable; sclReg <= nextSclReg; end if; end process; process(count,sclEnable,sclSpeed,sclReg) begin tsrEnable <= '0'; nextSclReg <= '0'; -- Polarity = 0 if sclEnable = '1' then -- scl if sclSpeed = '0' then --slow mode if (conv_integer(count) >= 0) and (conv_integer(count) < conv_integer(spiDivSlow)/2) then nextSclReg <= '1'; elsif conv_integer(count) >= conv_integer(spiDivSlow)/2 then nextSclReg <= '0'; end if; else --fast mode if (conv_integer(count) >= 0) and (conv_integer(count) < conv_integer(spiDivFast)/2) then nextSclReg <= '1'; elsif conv_integer(count) >= conv_integer(spiDivFast)/2 then nextSclReg <= '0'; end if; end if; end if; -- Phase = 0; if sclEnable = '1' then -- tsrEnable logic if sclSpeed = '0' then --slow mode if conv_integer(count) = (conv_integer(spiDivSlow))/2 then tsrEnable <= '1'; end if; else --fast mode if conv_integer(count) = (conv_integer(spiDivFast))/2 then tsrEnable <= '1'; end if; end if; end if; end process; nextcount <= (others => '0') when sclEnable = '0' else (others => '0') when count >= (spiDivSlow-1) and sclSpeed = '0' else (others => '0') when count >= (spiDivFast-1) and sclSpeed = '1' else (count + 1); end SpiClkDivide_arch;
gpl-3.0
kuruoujou/ECE-337-USB-Data-Sniffer
source/tb_SpiClkDivide.vhd
1
1532
-- $Id: $ -- File name: tb_ClkDivide.vhd -- Created: 2/29/2012 -- Author: David Kauer -- Lab Section: 2 -- Version: 1.0 Initial Test Bench library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tb_SpiClkDivide is generic( CLK_PERIOD : Time := 10 ns ); end tb_SpiClkDivide; architecture TEST of tb_SpiClkDivide is function UINT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER ) return STD_LOGIC_VECTOR is begin return std_logic_vector(to_unsigned(X, NumBits)); end; function STD_LOGIC_TO_UINT( X: std_logic_vector) return integer is begin return to_integer(unsigned(x)); end; component SpiClkDivide PORT( clk : in std_logic; resetN : in std_logic; sclEnable : in std_logic; tsrEnable : out std_logic; scl : out std_logic ); end component; signal clk : std_logic; signal resetN : std_logic; signal sclEnable : std_logic; signal tsrEnable : std_logic; signal scl : std_logic; begin process begin clk <= '1'; wait for CLK_PERIOD/2; clk <= '0'; wait for CLK_PERIOD/2; end process; DUT: SpiClkDivide port map( clk => clk, resetN => resetN, tsrEnable => tsrEnable, sclEnable => sclEnable, scl => scl ); process begin sclEnable <= '1'; -- run for 1000 ns resetN <= '0'; wait for 10 ns; resetN <= '1'; wait; end process; end TEST;
gpl-3.0
etingi01/MIPS_with_multiplier-VHDL-
My_Top_outs_tb_948282.vhd
1
13350
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:15:52 11/21/2013 -- Design Name: -- Module Name: C:/Users/etingi01/EPL221_FALL2013_MIPS32DSPprocessorID_948282/My_TOP_outs_tb_948282.vhd -- Project Name: EPL221_FALL2013_MIPS32DSPprocessorID_948282 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: My_TOP_948282 -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY My_TOP_outs_tb_948282 IS END My_TOP_outs_tb_948282; ARCHITECTURE behavior OF My_TOP_outs_tb_948282 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT My_TOP_948282 PORT( Clock : IN std_logic; Reset : IN std_logic; InstrAddress : OUT std_logic_vector(9 downto 0); InstructionNum : OUT std_logic_vector(31 downto 0); RFReadRegister1 : OUT std_logic_vector(4 downto 0); RFReadRegister2 : OUT std_logic_vector(4 downto 0); RFWriteRegister : OUT std_logic_vector(4 downto 0); RFWriteData : OUT std_logic_vector(31 downto 0); RFRegWrite : OUT std_logic; RFclk : OUT std_logic; RFReset : OUT std_logic; RFReadData1 : OUT std_logic_vector(31 downto 0); RFReadData2 : OUT std_logic_vector(31 downto 0); RFReadData3 : OUT std_logic_vector(31 downto 0); CUOp_Code : OUT std_logic_vector(5 downto 0); CUFun_Code : OUT std_logic_vector(5 downto 0); CUMemToRead : OUT std_logic; CURegDist : OUT std_logic; CURegWrite : OUT std_logic; CUMemWrite : OUT std_logic; CUAlu1 : OUT std_logic; CUCarryIn : OUT std_logic; CUAlu0 : OUT std_logic; CUMemRead : OUT std_logic; InAlu0 : OUT std_logic; InAlu1 : OUT std_logic; InA : OUT std_logic_vector(31 downto 0); InB : OUT std_logic_vector(31 downto 0); InB_Inv : OUT std_logic; OutResult_alu : OUT std_logic_vector(31 downto 0); RAMDataAddress : OUT std_logic_vector(9 downto 0); RAMclk : OUT std_logic; RAMreadData : OUT std_logic; RAMwriteData : OUT std_logic; RAMDataIn : OUT std_logic_vector(31 downto 0); RAMDataOut : OUT std_logic_vector(31 downto 0); beforeRF_A : OUT std_logic_vector(4 downto 0); beforeRF_B : OUT std_logic_vector(4 downto 0); beforeRF_Op : OUT std_logic; beforeRF_result : OUT std_logic_vector(4 downto 0); Select1_secMux : OUT std_logic; A_secMux : OUT std_logic_vector(31 downto 0); B_secMux : OUT std_logic_vector(31 downto 0); out_secMux : OUT std_logic_vector(31 downto 0); Select1_thirdMux : OUT std_logic; A_thirdMux : OUT std_logic_vector(31 downto 0); B_thirdMux : OUT std_logic_vector(31 downto 0); out_thirdMux : OUT std_logic_vector(31 downto 0); Select1_fourthMux : OUT std_logic; A_fourthMux : OUT std_logic_vector(31 downto 0); B_fourthMux : OUT std_logic_vector(31 downto 0); out_fourthMux : OUT std_logic_vector(31 downto 0); Select1_lastMux : OUT std_logic; Select2_lastMux : OUT std_logic; A_lastMux : OUT std_logic_vector(31 downto 0); B_lastMux : OUT std_logic_vector(31 downto 0); C_lastMux : OUT std_logic_vector(31 downto 0); D_lastMux : OUT std_logic_vector(31 downto 0); R_lastMux : OUT std_logic_vector(31 downto 0); RF2_ReadRegister1 : OUT std_logic_vector(4 downto 0); RF2_ReadRegister2 : OUT std_logic_vector(4 downto 0); RF2_WriteRegister : OUT std_logic_vector(4 downto 0); RF2_WriteData : OUT std_logic_vector(31 downto 0); RF2_RegWrite : OUT std_logic; RF2_clk : OUT std_logic; RF2_Reset : OUT std_logic; RF2_ReadData1 : OUT std_logic_vector(31 downto 0); RF2_ReadData2 : OUT std_logic_vector(31 downto 0); RF2_ReadData3 : OUT std_logic_vector(31 downto 0); address : OUT std_logic_vector(9 downto 0) ); END COMPONENT; --Inputs signal Clock : std_logic := '0'; signal Reset : std_logic := '0'; --Outputs signal InstrAddress : std_logic_vector(9 downto 0); signal InstructionNum : std_logic_vector(31 downto 0); signal RFReadRegister1 : std_logic_vector(4 downto 0); signal RFReadRegister2 : std_logic_vector(4 downto 0); signal RFWriteRegister : std_logic_vector(4 downto 0); signal RFWriteData : std_logic_vector(31 downto 0); signal RFRegWrite : std_logic; signal RFclk : std_logic; signal RFReset : std_logic; signal RFReadData1 : std_logic_vector(31 downto 0); signal RFReadData2 : std_logic_vector(31 downto 0); signal RFReadData3 : std_logic_vector(31 downto 0); signal CUOp_Code : std_logic_vector(5 downto 0); signal CUFun_Code : std_logic_vector(5 downto 0); signal CUMemToRead : std_logic; signal CURegDist : std_logic; signal CURegWrite : std_logic; signal CUMemWrite : std_logic; signal CUAlu1 : std_logic; signal CUCarryIn : std_logic; signal CUAlu0 : std_logic; signal CUMemRead : std_logic; signal InAlu0 : std_logic; signal InAlu1 : std_logic; signal InA : std_logic_vector(31 downto 0); signal InB : std_logic_vector(31 downto 0); signal InB_Inv : std_logic; signal OutResult_alu : std_logic_vector(31 downto 0); signal RAMDataAddress : std_logic_vector(9 downto 0); signal RAMclk : std_logic; signal RAMreadData : std_logic; signal RAMwriteData : std_logic; signal RAMDataIn : std_logic_vector(31 downto 0); signal RAMDataOut : std_logic_vector(31 downto 0); signal beforeRF_A : std_logic_vector(4 downto 0); signal beforeRF_B : std_logic_vector(4 downto 0); signal beforeRF_Op : std_logic; signal beforeRF_result : std_logic_vector(4 downto 0); signal Select1_secMux : std_logic; signal A_secMux : std_logic_vector(31 downto 0); signal B_secMux : std_logic_vector(31 downto 0); signal out_secMux : std_logic_vector(31 downto 0); signal Select1_thirdMux : std_logic; signal A_thirdMux : std_logic_vector(31 downto 0); signal B_thirdMux : std_logic_vector(31 downto 0); signal out_thirdMux : std_logic_vector(31 downto 0); signal Select1_fourthMux : std_logic; signal A_fourthMux : std_logic_vector(31 downto 0); signal B_fourthMux : std_logic_vector(31 downto 0); signal out_fourthMux : std_logic_vector(31 downto 0); signal Select1_lastMux : std_logic; signal Select2_lastMux : std_logic; signal A_lastMux : std_logic_vector(31 downto 0); signal B_lastMux : std_logic_vector(31 downto 0); signal C_lastMux : std_logic_vector(31 downto 0); signal D_lastMux : std_logic_vector(31 downto 0); signal R_lastMux : std_logic_vector(31 downto 0); signal RF2_ReadRegister1 : std_logic_vector(4 downto 0); signal RF2_ReadRegister2 : std_logic_vector(4 downto 0); signal RF2_WriteRegister : std_logic_vector(4 downto 0); signal RF2_WriteData : std_logic_vector(31 downto 0); signal RF2_RegWrite : std_logic; signal RF2_clk : std_logic; signal RF2_Reset : std_logic; signal RF2_ReadData1 : std_logic_vector(31 downto 0); signal RF2_ReadData2 : std_logic_vector(31 downto 0); signal RF2_ReadData3 : std_logic_vector(31 downto 0); signal address : std_logic_vector(9 downto 0); -- Clock period definitions constant Clock_period : time := 10 ns; constant RFclk_period : time := 10 ns; constant RAMclk_period : time := 10 ns; constant RF2_clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: My_TOP_948282 PORT MAP ( Clock => Clock, Reset => Reset, InstrAddress => InstrAddress, InstructionNum => InstructionNum, RFReadRegister1 => RFReadRegister1, RFReadRegister2 => RFReadRegister2, RFWriteRegister => RFWriteRegister, RFWriteData => RFWriteData, RFRegWrite => RFRegWrite, RFclk => RFclk, RFReset => RFReset, RFReadData1 => RFReadData1, RFReadData2 => RFReadData2, RFReadData3 => RFReadData3, CUOp_Code => CUOp_Code, CUFun_Code => CUFun_Code, CUMemToRead => CUMemToRead, CURegDist => CURegDist, CURegWrite => CURegWrite, CUMemWrite => CUMemWrite, CUAlu1 => CUAlu1, CUCarryIn => CUCarryIn, CUAlu0 => CUAlu0, CUMemRead => CUMemRead, InAlu0 => InAlu0, InAlu1 => InAlu1, InA => InA, InB => InB, InB_Inv => InB_Inv, OutResult_alu => OutResult_alu, RAMDataAddress => RAMDataAddress, RAMclk => RAMclk, RAMreadData => RAMreadData, RAMwriteData => RAMwriteData, RAMDataIn => RAMDataIn, RAMDataOut => RAMDataOut, beforeRF_A => beforeRF_A, beforeRF_B => beforeRF_B, beforeRF_Op => beforeRF_Op, beforeRF_result => beforeRF_result, Select1_secMux => Select1_secMux, A_secMux => A_secMux, B_secMux => B_secMux, out_secMux => out_secMux, Select1_thirdMux => Select1_thirdMux, A_thirdMux => A_thirdMux, B_thirdMux => B_thirdMux, out_thirdMux => out_thirdMux, Select1_fourthMux => Select1_fourthMux, A_fourthMux => A_fourthMux, B_fourthMux => B_fourthMux, out_fourthMux => out_fourthMux, Select1_lastMux => Select1_lastMux, Select2_lastMux => Select2_lastMux, A_lastMux => A_lastMux, B_lastMux => B_lastMux, C_lastMux => C_lastMux, D_lastMux => D_lastMux, R_lastMux => R_lastMux, RF2_ReadRegister1 => RF2_ReadRegister1, RF2_ReadRegister2 => RF2_ReadRegister2, RF2_WriteRegister => RF2_WriteRegister, RF2_WriteData => RF2_WriteData, RF2_RegWrite => RF2_RegWrite, RF2_clk => RF2_clk, RF2_Reset => RF2_Reset, RF2_ReadData1 => RF2_ReadData1, RF2_ReadData2 => RF2_ReadData2, RF2_ReadData3 => RF2_ReadData3, address => address ); -- Clock process definitions Clock_process :process begin Clock <= '0'; wait for Clock_period/2; Clock <= '1'; wait for Clock_period/2; end process; RFclk_process :process begin RFclk <= '0'; wait for RFclk_period/2; RFclk <= '1'; wait for RFclk_period/2; end process; RAMclk_process :process begin RAMclk <= '0'; wait for RAMclk_period/2; RAMclk <= '1'; wait for RAMclk_period/2; end process; RF2_clk_process :process begin RF2_clk <= '0'; wait for RF2_clk_period/2; RF2_clk <= '1'; wait for RF2_clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for Clock_period*10; Reset<='1'; Clock<='1'; wait for 100 ns; Clock<='0'; Reset<='0'; wait for 100 ns; --Reset<='1'; Clock<='1'; wait for 100 ns; Clock<='0'; --Reset<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; Clock<='1'; wait for 100 ns; Clock<='0'; wait for 100 ns; wait; end process; END;
gpl-3.0
etingi01/MIPS_with_multiplier-VHDL-
Control_Unit_tb_948282.vhd
1
3056
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:48:07 11/22/2013 -- Design Name: -- Module Name: C:/Users/etingi01/Downloads/EPL221_FALL2013_MIPS32DSPprocessorID_948282/EPL221_FALL2013_MIPS32DSPprocessorID_948282/Control_Unit_tb_948282.vhd -- Project Name: EPL221_FALL2013_MIPS32DSPprocessorID_948282 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Control_Unit_948282 -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Control_Unit_tb_948282 IS END Control_Unit_tb_948282; ARCHITECTURE behavior OF Control_Unit_tb_948282 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Control_Unit_948282 PORT( Op_Code : IN std_logic_vector(5 downto 0); Fun_Code : IN std_logic_vector(5 downto 0); MemToRead : OUT std_logic; RegDist : OUT std_logic; RegWrite : OUT std_logic; MemRead : OUT std_logic; MemWrite : OUT std_logic; Alu1 : OUT std_logic; CarryIn : OUT std_logic; Alu0 : OUT std_logic ); END COMPONENT; --Inputs signal Op_Code : std_logic_vector(5 downto 0) := (others => '0'); signal Fun_Code : std_logic_vector(5 downto 0) := (others => '0'); --Outputs signal MemToRead : std_logic; signal RegDist : std_logic; signal RegWrite : std_logic; signal MemRead : std_logic; signal MemWrite : std_logic; signal Alu1 : std_logic; signal CarryIn : std_logic; signal Alu0 : std_logic; -- No clocks detected in port list. Replace <clock> below with -- appropriate port name constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Control_Unit_948282 PORT MAP ( Op_Code => Op_Code, Fun_Code => Fun_Code, MemToRead => MemToRead, RegDist => RegDist, RegWrite => RegWrite, MemRead => MemRead, MemWrite => MemWrite, Alu1 => Alu1, CarryIn => CarryIn, Alu0 => Alu0 ); -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clk_period*10; Op_Code<="000000"; Fun_Code<="100010"; wait; end process; END;
gpl-3.0
etingi01/MIPS_with_multiplier-VHDL-
My_TOP_948282.vhd
1
14453
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 20:20:07 11/19/2013 -- Design Name: -- Module Name: My_TOP_948282 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity My_TOP_948282 is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; --eisodoi instruction rom: InstrAddress: out std_logic_vector (9 downto 0); InstructionNum: out std_logic_vector (31 downto 0); -- --eisodoi Register File RFReadRegister1 : out STD_LOGIC_VECTOR (4 downto 0); RFReadRegister2 : out STD_LOGIC_VECTOR (4 downto 0); RFWriteRegister : out STD_LOGIC_VECTOR (4 downto 0); RFWriteData : out STD_LOGIC_VECTOR (31 downto 0); RFRegWrite : out STD_LOGIC; --eksodoi register File RFReadData1 : out STD_LOGIC_VECTOR (31 downto 0); RFReadData2 : out STD_LOGIC_VECTOR (31 downto 0); RFReadData3 : out STD_LOGIC_VECTOR (31 downto 0); -- -- --eisodoi Control Unit CUOp_Code : out STD_LOGIC_VECTOR (5 downto 0); CUFun_Code : out STD_LOGIC_VECTOR (5 downto 0); --eksodoi Control Unit CUMemToRead : out STD_LOGIC; CURegDist : out STD_LOGIC; CURegWrite : out STD_LOGIC; CUMemWrite : out STD_LOGIC; CUAlu1 : out STD_LOGIC; CUCarryIn : out STD_LOGIC; CUAlu0 : out STD_LOGIC; CUMemRead : out STD_LOGIC; -- -- --eisodoi ALU InAlu0 : out STD_LOGIC; InAlu1 : out STD_LOGIC; InA : out STD_LOGIC_VECTOR (31 downto 0); InB: out STD_LOGIC_VECTOR (31 downto 0); InB_Inv : out STD_LOGIC; --Eksodos alu OutResult_alu : out STD_LOGIC_VECTOR (31 downto 0); -- -- --Eisodoi DataRam RAMDataAddress : out STD_LOGIC_VECTOR (9 downto 0); RAMreadData : out STD_LOGIC; RAMwriteData : out STD_LOGIC; RAMDataIn : out STD_LOGIC_VECTOR (31 downto 0); --Eksodoi DataRam RAMDataOut : out STD_LOGIC_VECTOR (31 downto 0); -- -- --Eisodoi prwtou mux prin to Register File beforeRF_A : out STD_LOGIC_VECTOR (4 downto 0); beforeRF_B : out STD_LOGIC_VECTOR (4 downto 0); beforeRF_Op : out STD_LOGIC; --eksodos prwtou mux prin to register File beforeRF_result : out STD_LOGIC_VECTOR (4 downto 0); -- -- --Eisodoi defterou mux meta to Register File Select1_secMux : out STD_LOGIC; A_secMux : out STD_LOGIC_VECTOR (31 downto 0); B_secMux : out STD_LOGIC_VECTOR (31 downto 0); --eksodos defterou mux meta to register File out_secMux : out STD_LOGIC_VECTOR (31 downto 0); -- -- --Eisodoi tritou mux meta to register File Select1_thirdMux : out STD_LOGIC; A_thirdMux : out STD_LOGIC_VECTOR (31 downto 0); B_thirdMux : out STD_LOGIC_VECTOR (31 downto 0); --eksodos tritou mux meta to register File out_thirdMux : out STD_LOGIC_VECTOR (31 downto 0); -- -- --Eisodos tetartou mux prin to ALU Select1_fourthMux : out STD_LOGIC; A_fourthMux : out STD_LOGIC_VECTOR (31 downto 0); B_fourthMux : out STD_LOGIC_VECTOR (31 downto 0); --eksodos tetartou mux prin to alu out_fourthMux : out STD_LOGIC_VECTOR (31 downto 0); -- -- --Eisodos pemptou mux prin to Register File Select1_lastMux : out STD_LOGIC; Select2_lastMux : out STD_LOGIC; A_lastMux : out STD_LOGIC_VECTOR (31 downto 0); B_lastMux : out STD_LOGIC_VECTOR (31 downto 0); C_lastMux : out STD_LOGIC_VECTOR (31 downto 0); D_lastMux : out STD_LOGIC_VECTOR (31 downto 0); --Eksodos pemptou mux prin to Register File R_lastMux : out STD_LOGIC_VECTOR (31 downto 0); -- -- --SecondTimeRegisterFile-eisodoi RF2_ReadRegister1 : out STD_LOGIC_VECTOR (4 downto 0); RF2_ReadRegister2 : out STD_LOGIC_VECTOR (4 downto 0); RF2_WriteRegister : out STD_LOGIC_VECTOR (4 downto 0); RF2_WriteData : out STD_LOGIC_VECTOR (31 downto 0); RF2_RegWrite : out STD_LOGIC; --SecondTimeRegisterFile-eksodoi RF2_ReadData1 : out STD_LOGIC_VECTOR (31 downto 0); RF2_ReadData2 : out STD_LOGIC_VECTOR (31 downto 0); RF2_ReadData3 : out STD_LOGIC_VECTOR (31 downto 0); -- address: out STD_LOGIC_VECTOR(9 downto 0)); end My_TOP_948282; architecture Behavioral of My_TOP_948282 is component InstructionsROM is Port ( InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0); Instruction : out STD_LOGIC_VECTOR (31 downto 0)); end component; component My_PC_Adder_948282 is Port ( Address_In : in STD_LOGIC_VECTOR (9 downto 0); Address_Next : out STD_LOGIC_VECTOR (9 downto 0)); end component; component My_SignExtend_948282 is Port ( Sign_In : in STD_LOGIC_VECTOR (15 downto 0); Sign_Out : out STD_LOGIC_VECTOR (31 downto 0)); end component; component myPCRegister is Port ( PC_INPUT : in STD_LOGIC_VECTOR (9 downto 0); PC_OUTPUT : out STD_LOGIC_VECTOR (9 downto 0); clk : in STD_LOGIC; RESET : in STD_LOGIC); end component; component My_32bit2x1Mux_948282 is Port ( B_inv : in STD_LOGIC; B : in STD_LOGIC_VECTOR (31 downto 0); B_comp : in STD_LOGIC_VECTOR (31 downto 0); B_out : out STD_LOGIC_VECTOR (31 downto 0)); end component; component my32BitRegistersFile is Port ( ReadRegister1 : in STD_LOGIC_VECTOR (4 downto 0); ReadRegister2 : in STD_LOGIC_VECTOR (4 downto 0); WriteRegister : in STD_LOGIC_VECTOR (4 downto 0); WriteData : in STD_LOGIC_VECTOR (31 downto 0); ReadData1 : out STD_LOGIC_VECTOR (31 downto 0); ReadData2 : out STD_LOGIC_VECTOR (31 downto 0); ReadData3 : out STD_LOGIC_VECTOR (31 downto 0); RegWrite : in STD_LOGIC; clk : in STD_LOGIC; Reset : in STD_LOGIC); end component; component My_ALU_948282 is Port ( Alu0 : in STD_LOGIC; Alu1 : in STD_LOGIC; A_alu : in STD_LOGIC_VECTOR (31 downto 0); B_alu: in STD_LOGIC_VECTOR (31 downto 0); B_Inv : in STD_LOGIC; Result_alu : out STD_LOGIC_VECTOR (31 downto 0)); end component; component DataRAM is Port ( DataAddress : in STD_LOGIC_VECTOR (9 downto 0); clk : in STD_LOGIC; readData : in STD_LOGIC; writeData : in STD_LOGIC; DataIn : in STD_LOGIC_VECTOR (31 downto 0); DataOut : out STD_LOGIC_VECTOR (31 downto 0)); end component; component My_16bitMult_948282 is Port ( A_inputM : in STD_LOGIC_VECTOR (15 downto 0); B_inputM : in STD_LOGIC_VECTOR (15 downto 0); Hi_out : out STD_LOGIC_VECTOR (15 downto 0); Lo_out : out STD_LOGIC_VECTOR (15 downto 0)); end component; component myMux2X1_948282 is Port ( A : in STD_LOGIC_VECTOR (4 downto 0); B : in STD_LOGIC_VECTOR (4 downto 0); Op : in STD_LOGIC; result : out STD_LOGIC_VECTOR (4 downto 0)); end component; component Control_Unit_948282 is Port ( Op_Code : in STD_LOGIC_VECTOR (5 downto 0); Fun_Code : in STD_LOGIC_VECTOR (5 downto 0); MemToRead : out STD_LOGIC; RegDist : out STD_LOGIC; RegWrite : out STD_LOGIC; MemWrite : out STD_LOGIC; Alu1 : out STD_LOGIC; CarryIn : out STD_LOGIC; Alu0 : out STD_LOGIC; MemRead : out STD_LOGIC); end component; component My_32bit4x1Mux_948282 is Port ( Select1 : in STD_LOGIC; Select2 : in STD_LOGIC; A : in STD_LOGIC_VECTOR (31 downto 0); B : in STD_LOGIC_VECTOR (31 downto 0); C : in STD_LOGIC_VECTOR (31 downto 0); D : in STD_LOGIC_VECTOR (31 downto 0); R : out STD_LOGIC_VECTOR (31 downto 0)); end component; --signal address: std_logic_vector(9 downto 0) :="0000000000"; signal addressTemp: std_logic_vector(9 downto 0):="0000000000"; signal addressS: std_logic_vector(9 downto 0); signal instruction: std_logic_vector(31 downto 0); signal firstMux: std_logic_vector(4 downto 0); signal regDist, memToRead, regWrite, memRead, memWrite, alu0, alu1, bInv: std_logic; signal Rdata1, Rdata2, Rdata3, SignExtendR: std_logic_vector(31 downto 0); signal multResult, aluResult, dataRamResult, Mux4Result: std_logic_vector(31 downto 0); signal hi, lo: std_logic_vector(15 downto 0); signal MuxSec, MuxThird, MuxFourth: std_logic_vector (31 downto 0); signal ZERO: std_logic_vector(31 downto 0):="00000000000000000000000000000000"; signal ZERO1: std_logic_vector(31 downto 0):="00000000000000000000000000000000"; signal ZERO2: std_logic_vector(31 downto 0):="00000000000000000000000000000000"; signal ZERO3: std_logic_vector(31 downto 0):="00000000000000000000000000000000"; signal WRITE_DATA: std_logic_vector(31 downto 0):="00000000000000000000000000000000"; signal writeRegister: std_logic_vector(4 downto 0):="00000"; signal WriteReg: std_logic :='0'; begin instr1: myPCRegister port map (PC_INPUT=>addressTemp, PC_OUTPUT=>addressS, clk=>Clock, RESET=>Reset); instr2: address<=addressS; simul1: InstrAddress<=AddressS; instr3: InstructionsROM port map (InstructionAddress=>addressS, Instruction=>instruction); simul2: InstructionNum<=instruction; instr4: Control_Unit_948282 port map (Op_Code=>instruction(31 downto 26), Fun_Code=>instruction(5 downto 0), MemToRead=>memToRead, RegDist=>regDist, RegWrite=>regWrite, MemWrite=>memWrite, Alu1=>alu1, Alu0=>alu0, CarryIn=>bInv, MemRead=>memRead); simul3: CUOp_Code<=instruction(31 downto 26); simul4: CUFun_Code<=instruction(5 downto 0); simul5: CUMemToRead<=memToRead; simul6: CURegDist<=regDist; simul7: CURegWrite<=regWrite; simul8: CUMemWrite<=memWrite; simul9: CUAlu1<=alu1; simul10: CUCarryIn<=bInv; simul11: CUAlu0<=alu0; simul12: CUMemRead<=memRead; instr5: My_PC_Adder_948282 port map (Address_In=>addressS, Address_Next=>addressTemp); instr7: myMux2X1_948282 port map (Op=>regDist, A=>instruction(15 downto 11), B=>instruction(20 downto 16), result=>firstMux); simul13: beforeRF_A<=instruction(15 downto 11); simul14: beforeRF_B<=instruction(20 downto 16); simul15: beforeRF_Op<=regDist; simul16: beforeRF_result<=firstMux; instr8: my32BitRegistersFile port map (ReadRegister1=>instruction(25 downto 21), ReadRegister2=>instruction(20 downto 16), WriteRegister=>firstMux, WriteData=>Mux4Result, RegWrite=>regWrite, clk=>Clock, Reset=>Reset, ReadData1=>Rdata1, ReadData2=>Rdata2, ReadData3=>Rdata3); simul17: RFReadRegister1<=instruction(25 downto 21); simul18: RFReadRegister2<=instruction (20 downto 16); simul19: RFWriteRegister<=firstMux; simul20: RFWriteData<=ZERO; simul21: RFRegWrite<='0'; simul24: RFReadData1<=Rdata1; simul25: RFReadData2<=Rdata2; simul26: RFReadData3<=Rdata3; instr9: My_16bitMult_948282 port map (A_inputM=>Rdata1(15 downto 0), B_inputM=>Rdata2(15 downto 0), Hi_out=>hi, Lo_out=>lo); instr10: multResult(31 downto 16) <= hi; instr11: multResult(15 downto 0)<= lo; instr12: My_32bit2x1Mux_948282 port map (B=>Rdata1, B_comp=>multResult, B_inv=>instruction(10), B_out=>MuxSec);--MuxSec in alu simul27: Select1_secMux<=instruction(10); simul28: A_secMux<=Rdata1; simul29: B_secMux<=multResult; simul30: out_secMux<=MuxSec; instr13: My_32bit2x1Mux_948282 port map (B=>Rdata2, B_comp=>Rdata3, B_inv=>instruction(10), B_out=>MuxThird); simul31: Select1_thirdMux<=instruction(10); simul32: A_thirdMux<=Rdata2; simul33: B_thirdMux<=Rdata3; simul34: out_thirdMux<=MuxThird; instr14: My_SignExtend_948282 port map (Sign_In=>instruction(15 downto 0), Sign_Out=>SignExtendR); instr15: My_32bit2x1Mux_948282 port map (B=>SignExtendR, B_comp=>MuxSec, B_inv=>regDist, B_out=>MuxFourth);--muxFourth in alu simul35: Select1_fourthMux<=regDist; simul36: A_fourthMux<=SignExtendR; simul37: B_fourthMux<=MuxSec; simul39: out_fourthMux<=MuxFourth; instr16: My_ALU_948282 port map (Alu0=>alu0, Alu1=>alu1, A_alu=>MuxThird, B_alu=>MuxFourth, B_Inv=>bInv, Result_alu=>aluResult); --slu result in multiplexer simul40: InAlu0<=alu0; simul41: InAlu1<=alu1; simul42: InA<=MuxThird; simul43: InB<=MuxFourth; simul44: InB_Inv<=bInv ; simul45: OutResult_alu<=aluResult; instr17: DataRAM port map (DataAddress=>aluResult(9 downto 0), clk=>Clock, readData=>memRead, writeData=>memWrite, DataIn=>Rdata2, DataOut=>dataRamResult); simul46: RAMDataAddress<=aluResult(9 downto 0); simul48: RAMreadData <=memRead; simul49: RAMwriteData<=memWrite; simul50: RAMDataIn<=Rdata2; simul51: RAMDataOut<=dataRamResult; instr18: My_32bit4x1Mux_948282 port map (Select1=>MemToRead, Select2=>instruction(4), A=>aluResult, B=>multResult, C=>dataRamResult, D=>dataRamResult, R=>Mux4Result); simul52: Select1_lastMux<=MemToRead; simul53: Select2_lastMux<=instruction(4); simul54: A_lastMux<=aluResult; simul55: B_lastMux<=multResult; simul56: C_lastMux <=dataRamResult; simul57: D_lastMux <=dataRamResult; simul58: R_lastMux <=Mux4Result; --instr19: my32BitRegistersFile port map (ReadRegister1=>instruction(25 downto 21), ReadRegister2=>instruction(20 downto 16), WriteRegister=>firstMux, WriteData=>Mux4Result, RegWrite=>regWrite, clk=>Clock, Reset=>Reset, ReadData1=>ZERO1, ReadData2=>ZERO2, ReadData3=>ZERO3); simul59: RF2_ReadRegister1<=instruction(25 downto 21); simul60: RF2_ReadRegister2<=instruction(20 downto 16); simul61: RF2_WriteRegister<=firstMux; simul62: RF2_WriteData<=Mux4Result; simul63: RF2_RegWrite<=regWrite; simul66: RF2_ReadData1 <=ZERO1; simul67: RF2_ReadData2<=ZERO2; simul68: RF2_ReadData3 <=ZERO3; end Behavioral;
gpl-3.0
kuruoujou/ECE-337-USB-Data-Sniffer
source/FifoWrite.vhd
1
1270
-- $Id: $ -- File name: SpiSlaveFifoWrite -- Created: 3/17/2012 -- Author: David Kauer -- Lab Section: -- Version: 1.0 Initial Design Entry -- Description: SPI Slave Fifo Write Counter LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity FifoWrite is generic ( gregLength : integer := 16; addrSize : integer := 4 -- 2^addrSize = gregLength ); port ( clk : in std_logic; resetN : in std_logic; wEnable : in std_logic; fifoFull : in std_logic; wSel : out std_logic_vector(addrSize-1 downto 0) ); end FifoWrite; architecture FifoWrite_arch of FifoWrite is signal count,nextCount : std_logic_vector(addrSize-1 downto 0); begin process(clk,resetN) begin if resetN = '0' then count <= (others => '0'); elsif rising_edge(clk) then count <= nextCount; end if; end process; nextCount <= count when fifoFull = '1' -- cannot write if fifo is full else (others => '0') when ((conv_integer(count) = gregLength-1) and wEnable = '1') else (count + 1) when wEnable = '1' else count; wSel <= count; end FifoWrite_arch;
gpl-3.0
kuruoujou/ECE-337-USB-Data-Sniffer
source/interceptor.vhd
1
6358
-- VHDL Entity My_Lib.interceptor.symbol -- -- Created: -- by - mg55.bin (srge02.ecn.purdue.edu) -- at - 14:37:58 04/21/12 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2010.2a (Build 7) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY interceptor IS PORT( clk : IN std_logic; eop : IN std_logic; intercept : IN std_logic; inst : IN std_logic_vector (3 DOWNTO 0); rst : IN std_logic; usbclk : IN std_logic; dataPlus : OUT std_logic; dataMinus : OUT std_logic; computerMinus : INOUT std_logic; computerPlus : INOUT std_logic; usbMinus : INOUT std_logic; usbPlus : INOUT std_logic ); -- Declarations END interceptor ; -- -- VHDL Architecture My_Lib.interceptor.struct -- -- Created: -- by - mg55.bin (srge02.ecn.purdue.edu) -- at - 14:37:58 04/21/12 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2010.2a (Build 7) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; ARCHITECTURE struct OF interceptor IS -- Architecture declarations -- Internal signal declarations SIGNAL computerDataMinus : std_logic; SIGNAL computerDataMinusOutput : std_logic; SIGNAL computerDataPlus : std_logic; SIGNAL computerDataPlusOutput : std_logic; SIGNAL computerLock : std_logic; SIGNAL usbDataMinus : std_logic; SIGNAL usbDataMinusOutput : std_logic; SIGNAL usbDataPlus : std_logic; SIGNAL usbDataPlusOutput : std_logic; SIGNAL usbLock : std_logic; -- Component Declarations COMPONENT computerInterceptor PORT ( clk : IN std_logic; computerDataMinus : IN std_logic; computerDataPlus : IN std_logic; computerLock : IN std_logic; eop : in std_logic; rst : IN std_logic; usbClk : IN std_logic; computerDataMinusOutput : OUT std_logic; computerDataPlusOutput : OUT std_logic ); END COMPONENT; COMPONENT lockingDetector PORT ( clk : IN std_logic; endOfPacket : IN std_logic; inst : IN std_logic_vector ( 3 DOWNTO 0 ); rst : IN std_logic; computerLock : OUT std_logic; usbLock : OUT std_logic ); END COMPONENT; COMPONENT tristate PORT ( interceptorOutput : IN std_logic; lock : IN std_logic; interceptorInput : OUT std_logic; dataLine : INOUT std_logic ); END COMPONENT; COMPONENT usbInterceptor PORT ( clk : IN std_logic; intercept : IN std_logic; rst : IN std_logic; usbClk : IN std_logic; eop : in std_logic; usbDataMinus : IN std_logic; usbDataPlus : IN std_logic; usbLock : IN std_logic; usbDataMinusOutput : OUT std_logic; usbDataPlusOutput : OUT std_logic ); END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off -- pragma synthesis_on BEGIN -- Instance port mappings. U_0 : computerInterceptor PORT MAP ( usbClk => usbclk, rst => rst, computerDataPlus => computerDataPlus, computerDataMinus => computerDataMinus, computerLock => computerLock, clk => clk, eop => eop, computerDataPlusOutput => computerDataPlusOutput, computerDataMinusOutput => computerDataMinusOutput ); U_1 : lockingDetector PORT MAP ( endOfPacket => eop, rst => rst, clk => clk, inst => inst, usbLock => usbLock, computerLock => computerLock ); U_2 : tristate -- D- usb to computer PORT MAP ( lock => computerLock, interceptorOutput => computerDataMinusOutput, interceptorInput => usbDataMinus, dataLine => usbMinus ); U_3 : tristate -- D+ computer to USB PORT MAP ( lock => usbLock, interceptorOutput => usbDataPlusOutput, interceptorInput => computerDataPlus, dataLine => computerPlus ); U_5 : tristate -- D+ usb PORT MAP ( lock => computerLock, interceptorOutput => computerDataPlusOutput, interceptorInput => usbDataPlus, dataLine => usbPlus ); U_6 : tristate -- D- computer PORT MAP ( lock => usbLock, interceptorOutput => usbDataMinusOutput, interceptorInput => computerDataMinus, dataLine => computerMinus ); U_4 : usbInterceptor PORT MAP ( usbClk => usbclk, rst => rst, intercept => intercept, usbDataPlus => usbDataPlus, eop => eop, usbDataMinus => usbDataMinus, usbLock => usbLock, clk => clk, usbDataPlusOutput => usbDataPlusOutput, usbDataMinusOutput => usbDataMinusOutput ); dataPlus <= usbPlus when usbLock = '1' -- logic for the output to the detector for the D+ line else computerPlus when computerLock = '1' else '1'; dataMinus <= usbMinus when usbLock = '1' -- logic for the output to the detector for the D- line else computerMinus when computerLock = '1' else '1'; END struct;
gpl-3.0
kuruoujou/ECE-337-USB-Data-Sniffer
source/tristate.vhd
1
896
-- $Id: $ -- File name: tristate.vhd -- Created: 4/8/2012 -- Author: John Wyant -- Lab Section: 337-02 -- Version: 1.0 Initial Design Entry -- Description: Runs the tristate for the bidirectional wires between the usb -- and intercept and between the computer and interceptor. LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.std_logic_unsigned.ALL; entity tristate is port ( lock, interceptorOutput : in std_logic; interceptorInput : out std_logic; dataLine : inout std_logic); end tristate; architecture behavioral of tristate is begin -- output to bus logic dataLine <= interceptorOutput when lock = '1' else 'Z'; -- input from bus logic interceptorInput <= '1' when (dataLine = '1' and lock = '0') or lock = '1' else '0'; end architecture;
gpl-3.0
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_01_a/hdl/vhdl/sg_2d_fir.vhd
1
303279
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_48bcbc42a6774592.vhd when simulating -- the core, addsb_11_0_48bcbc42a6774592. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_48bcbc42a6774592 IS PORT ( a : IN STD_LOGIC_VECTOR(20 DOWNTO 0); b : IN STD_LOGIC_VECTOR(20 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(20 DOWNTO 0) ); END addsb_11_0_48bcbc42a6774592; ARCHITECTURE addsb_11_0_48bcbc42a6774592_a OF addsb_11_0_48bcbc42a6774592 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_48bcbc42a6774592 PORT ( a : IN STD_LOGIC_VECTOR(20 DOWNTO 0); b : IN STD_LOGIC_VECTOR(20 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(20 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_48bcbc42a6774592 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 21, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 0, c_b_value => "000000000000000000000", c_b_width => 21, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 1, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 1, c_out_width => 21, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_48bcbc42a6774592 PORT MAP ( a => a, b => b, clk => clk, ce => ce, s => s ); -- synthesis translate_on END addsb_11_0_48bcbc42a6774592_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_da33f2d4b3b54185.vhd when simulating -- the core, addsb_11_0_da33f2d4b3b54185. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_da33f2d4b3b54185 IS PORT ( a : IN STD_LOGIC_VECTOR(19 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); END addsb_11_0_da33f2d4b3b54185; ARCHITECTURE addsb_11_0_da33f2d4b3b54185_a OF addsb_11_0_da33f2d4b3b54185 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_da33f2d4b3b54185 PORT ( a : IN STD_LOGIC_VECTOR(19 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_da33f2d4b3b54185 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 20, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 0, c_b_value => "00000000000000000000", c_b_width => 20, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 1, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 1, c_out_width => 20, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_da33f2d4b3b54185 PORT MAP ( a => a, b => b, clk => clk, ce => ce, s => s ); -- synthesis translate_on END addsb_11_0_da33f2d4b3b54185_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_e7b4231f2ca96446.vhd when simulating -- the core, addsb_11_0_e7b4231f2ca96446. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_e7b4231f2ca96446 IS PORT ( a : IN STD_LOGIC_VECTOR(21 DOWNTO 0); b : IN STD_LOGIC_VECTOR(21 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) ); END addsb_11_0_e7b4231f2ca96446; ARCHITECTURE addsb_11_0_e7b4231f2ca96446_a OF addsb_11_0_e7b4231f2ca96446 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_e7b4231f2ca96446 PORT ( a : IN STD_LOGIC_VECTOR(21 DOWNTO 0); b : IN STD_LOGIC_VECTOR(21 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_e7b4231f2ca96446 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 22, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 0, c_b_value => "0000000000000000000000", c_b_width => 22, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 1, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 1, c_out_width => 22, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_e7b4231f2ca96446 PORT MAP ( a => a, b => b, clk => clk, ce => ce, s => s ); -- synthesis translate_on END addsb_11_0_e7b4231f2ca96446_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file bmg_62_05852d43925e39b8.vhd when simulating -- the core, bmg_62_05852d43925e39b8. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY bmg_62_05852d43925e39b8 IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(4 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END bmg_62_05852d43925e39b8; ARCHITECTURE bmg_62_05852d43925e39b8_a OF bmg_62_05852d43925e39b8 IS -- synthesis translate_off COMPONENT wrapped_bmg_62_05852d43925e39b8 PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(4 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_bmg_62_05852d43925e39b8 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) GENERIC MAP ( c_addra_width => 12, c_addrb_width => 12, c_algorithm => 0, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_family => "spartan6", c_has_axi_id => 0, c_has_ena => 1, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file_name => "bmg_62_05852d43925e39b8.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 2, c_read_depth_a => 4096, c_read_depth_b => 4096, c_read_width_a => 5, c_read_width_b => 5, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 4096, c_write_depth_b => 4096, c_write_mode_a => "READ_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 5, c_write_width_b => 5, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_bmg_62_05852d43925e39b8 PORT MAP ( clka => clka, ena => ena, wea => wea, addra => addra, dina => dina, douta => douta ); -- synthesis translate_on END bmg_62_05852d43925e39b8_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file bmg_62_54b11b852dca329b.vhd when simulating -- the core, bmg_62_54b11b852dca329b. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY bmg_62_54b11b852dca329b IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END bmg_62_54b11b852dca329b; ARCHITECTURE bmg_62_54b11b852dca329b_a OF bmg_62_54b11b852dca329b IS -- synthesis translate_off COMPONENT wrapped_bmg_62_54b11b852dca329b PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_bmg_62_54b11b852dca329b USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) GENERIC MAP ( c_addra_width => 12, c_addrb_width => 12, c_algorithm => 0, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_family => "spartan6", c_has_axi_id => 0, c_has_ena => 1, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file_name => "bmg_62_54b11b852dca329b.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 2, c_read_depth_a => 4096, c_read_depth_b => 4096, c_read_width_a => 8, c_read_width_b => 8, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 4096, c_write_depth_b => 4096, c_write_mode_a => "READ_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 8, c_write_width_b => 8, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_bmg_62_54b11b852dca329b PORT MAP ( clka => clka, ena => ena, wea => wea, addra => addra, dina => dina, douta => douta ); -- synthesis translate_on END bmg_62_54b11b852dca329b_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file cntr_11_0_862f833518f4973a.vhd when simulating -- the core, cntr_11_0_862f833518f4973a. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY cntr_11_0_862f833518f4973a IS PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END cntr_11_0_862f833518f4973a; ARCHITECTURE cntr_11_0_862f833518f4973a_a OF cntr_11_0_862f833518f4973a IS -- synthesis translate_off COMPONENT wrapped_cntr_11_0_862f833518f4973a PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_cntr_11_0_862f833518f4973a USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral) GENERIC MAP ( c_ainit_val => "0", c_ce_overrides_sync => 0, c_count_by => "1", c_count_mode => 0, c_count_to => "1", c_fb_latency => 0, c_has_ce => 1, c_has_load => 0, c_has_sclr => 0, c_has_sinit => 1, c_has_sset => 0, c_has_thresh0 => 0, c_implementation => 0, c_latency => 1, c_load_low => 0, c_restrict_count => 0, c_sclr_overrides_sset => 1, c_sinit_val => "0", c_thresh0_value => "1", c_verbosity => 0, c_width => 5, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_cntr_11_0_862f833518f4973a PORT MAP ( clk => clk, ce => ce, sinit => sinit, q => q ); -- synthesis translate_on END cntr_11_0_862f833518f4973a_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file cntr_11_0_e859c6662c373192.vhd when simulating -- the core, cntr_11_0_e859c6662c373192. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY cntr_11_0_e859c6662c373192 IS PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END cntr_11_0_e859c6662c373192; ARCHITECTURE cntr_11_0_e859c6662c373192_a OF cntr_11_0_e859c6662c373192 IS -- synthesis translate_off COMPONENT wrapped_cntr_11_0_e859c6662c373192 PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_cntr_11_0_e859c6662c373192 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral) GENERIC MAP ( c_ainit_val => "0", c_ce_overrides_sync => 0, c_count_by => "1", c_count_mode => 0, c_count_to => "1", c_fb_latency => 0, c_has_ce => 1, c_has_load => 0, c_has_sclr => 0, c_has_sinit => 1, c_has_sset => 0, c_has_thresh0 => 0, c_implementation => 0, c_latency => 1, c_load_low => 0, c_restrict_count => 0, c_sclr_overrides_sset => 1, c_sinit_val => "0", c_thresh0_value => "1", c_verbosity => 0, c_width => 3, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_cntr_11_0_e859c6662c373192 PORT MAP ( clk => clk, ce => ce, sinit => sinit, q => q ); -- synthesis translate_on END cntr_11_0_e859c6662c373192_a; -------------------------------------------------------------------------------- -- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- -------------------------------------------------------------------------------- -- Generated from component ID: xilinx.com:ip:fir_compiler:5.0 -- You must compile the wrapper file fr_cmplr_v5_0_0d2261239884a389.vhd when simulating -- the core, fr_cmplr_v5_0_0d2261239884a389. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY fr_cmplr_v5_0_0d2261239884a389 IS port ( clk: in std_logic; ce: in std_logic; nd: in std_logic; coef_ld: in std_logic; coef_we: in std_logic; coef_din: in std_logic_vector(6 downto 0); rfd: out std_logic; rdy: out std_logic; din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(18 downto 0)); END fr_cmplr_v5_0_0d2261239884a389; ARCHITECTURE fr_cmplr_v5_0_0d2261239884a389_a OF fr_cmplr_v5_0_0d2261239884a389 IS -- synthesis translate_off component wrapped_fr_cmplr_v5_0_0d2261239884a389 port ( clk: in std_logic; ce: in std_logic; nd: in std_logic; coef_ld: in std_logic; coef_we: in std_logic; coef_din: in std_logic_vector(6 downto 0); rfd: out std_logic; rdy: out std_logic; din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(18 downto 0)); end component; -- Configuration specification for all : wrapped_fr_cmplr_v5_0_0d2261239884a389 use entity XilinxCoreLib.fir_compiler_v5_0(behavioral) generic map( coef_width => 7, c_has_sclr => 0, datapath_memtype => 0, c_component_name => "fr_cmplr_v5_0_0d2261239884a389", c_family => "spartan6", round_mode => 0, output_width => 19, sclr_deterministic => 0, col_config => "5", coef_memtype => 0, clock_freq => 1, symmetry => 0, col_pipe_len => 4, c_latency => 11, chan_sel_width => 1, c_xdevicefamily => "spartan6", c_has_nd => 1, allow_approx => 0, num_channels => 1, data_width => 8, filter_sel_width => 1, sample_freq => 1, coef_reload => 1, neg_symmetry => 0, filter_type => 0, data_type => 1, accum_width => 19, rate_change_type => 0, ipbuff_memtype => 0, c_optimization => 1, output_reg => 1, data_memtype => 0, c_has_data_valid => 0, decim_rate => 1, coef_type => 0, filter_arch => 1, interp_rate => 1, num_taps => 5, c_mem_init_file => "fr_cmplr_v5_0_0d2261239884a389.mif", zero_packing_factor => 1, num_paths => 1, num_filts => 1, col_mode => 0, c_has_ce => 1, chan_in_adv => 0, opbuff_memtype => 0, odd_symmetry => 1); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fr_cmplr_v5_0_0d2261239884a389 port map ( clk => clk, ce => ce, nd => nd, coef_ld => coef_ld, coef_we => coef_we, coef_din => coef_din, rfd => rfd, rdy => rdy, din => din, dout => dout); -- synthesis translate_on END fr_cmplr_v5_0_0d2261239884a389_a; -------------------------------------------------------------------------------- -- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- -------------------------------------------------------------------------------- -- Generated from component ID: xilinx.com:ip:fir_compiler:5.0 -- You must compile the wrapper file fr_cmplr_v5_0_983c85a69a3a58e7.vhd when simulating -- the core, fr_cmplr_v5_0_983c85a69a3a58e7. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY fr_cmplr_v5_0_983c85a69a3a58e7 IS port ( clk: in std_logic; ce: in std_logic; nd: in std_logic; coef_ld: in std_logic; coef_we: in std_logic; coef_din: in std_logic_vector(6 downto 0); rfd: out std_logic; rdy: out std_logic; din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(18 downto 0)); END fr_cmplr_v5_0_983c85a69a3a58e7; ARCHITECTURE fr_cmplr_v5_0_983c85a69a3a58e7_a OF fr_cmplr_v5_0_983c85a69a3a58e7 IS -- synthesis translate_off component wrapped_fr_cmplr_v5_0_983c85a69a3a58e7 port ( clk: in std_logic; ce: in std_logic; nd: in std_logic; coef_ld: in std_logic; coef_we: in std_logic; coef_din: in std_logic_vector(6 downto 0); rfd: out std_logic; rdy: out std_logic; din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(18 downto 0)); end component; -- Configuration specification for all : wrapped_fr_cmplr_v5_0_983c85a69a3a58e7 use entity XilinxCoreLib.fir_compiler_v5_0(behavioral) generic map( coef_width => 7, c_has_sclr => 0, datapath_memtype => 0, c_component_name => "fr_cmplr_v5_0_983c85a69a3a58e7", c_family => "spartan6", round_mode => 0, output_width => 19, sclr_deterministic => 0, col_config => "5", coef_memtype => 0, clock_freq => 1, symmetry => 0, col_pipe_len => 4, c_latency => 11, chan_sel_width => 1, c_xdevicefamily => "spartan6", c_has_nd => 1, allow_approx => 0, num_channels => 1, data_width => 8, filter_sel_width => 1, sample_freq => 1, coef_reload => 1, neg_symmetry => 0, filter_type => 0, data_type => 1, accum_width => 19, rate_change_type => 0, ipbuff_memtype => 0, c_optimization => 1, output_reg => 1, data_memtype => 0, c_has_data_valid => 0, decim_rate => 1, coef_type => 0, filter_arch => 1, interp_rate => 1, num_taps => 5, c_mem_init_file => "fr_cmplr_v5_0_983c85a69a3a58e7.mif", zero_packing_factor => 1, num_paths => 1, num_filts => 1, col_mode => 0, c_has_ce => 1, chan_in_adv => 0, opbuff_memtype => 0, odd_symmetry => 1); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fr_cmplr_v5_0_983c85a69a3a58e7 port map ( clk => clk, ce => ce, nd => nd, coef_ld => coef_ld, coef_we => coef_we, coef_din => coef_din, rfd => rfd, rdy => rdy, din => din, dout => dout); -- synthesis translate_on END fr_cmplr_v5_0_983c85a69a3a58e7_a; -------------------------------------------------------------------------------- -- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- -------------------------------------------------------------------------------- -- Generated from component ID: xilinx.com:ip:fir_compiler:5.0 -- You must compile the wrapper file fr_cmplr_v5_0_bc5286c4b0615582.vhd when simulating -- the core, fr_cmplr_v5_0_bc5286c4b0615582. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY fr_cmplr_v5_0_bc5286c4b0615582 IS port ( clk: in std_logic; ce: in std_logic; nd: in std_logic; coef_ld: in std_logic; coef_we: in std_logic; coef_din: in std_logic_vector(6 downto 0); rfd: out std_logic; rdy: out std_logic; din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(18 downto 0)); END fr_cmplr_v5_0_bc5286c4b0615582; ARCHITECTURE fr_cmplr_v5_0_bc5286c4b0615582_a OF fr_cmplr_v5_0_bc5286c4b0615582 IS -- synthesis translate_off component wrapped_fr_cmplr_v5_0_bc5286c4b0615582 port ( clk: in std_logic; ce: in std_logic; nd: in std_logic; coef_ld: in std_logic; coef_we: in std_logic; coef_din: in std_logic_vector(6 downto 0); rfd: out std_logic; rdy: out std_logic; din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(18 downto 0)); end component; -- Configuration specification for all : wrapped_fr_cmplr_v5_0_bc5286c4b0615582 use entity XilinxCoreLib.fir_compiler_v5_0(behavioral) generic map( coef_width => 7, c_has_sclr => 0, datapath_memtype => 0, c_component_name => "fr_cmplr_v5_0_bc5286c4b0615582", c_family => "spartan6", round_mode => 0, output_width => 19, sclr_deterministic => 0, col_config => "5", coef_memtype => 0, clock_freq => 1, symmetry => 0, col_pipe_len => 4, c_latency => 11, chan_sel_width => 1, c_xdevicefamily => "spartan6", c_has_nd => 1, allow_approx => 0, num_channels => 1, data_width => 8, filter_sel_width => 1, sample_freq => 1, coef_reload => 1, neg_symmetry => 0, filter_type => 0, data_type => 1, accum_width => 19, rate_change_type => 0, ipbuff_memtype => 0, c_optimization => 1, output_reg => 1, data_memtype => 0, c_has_data_valid => 0, decim_rate => 1, coef_type => 0, filter_arch => 1, interp_rate => 1, num_taps => 5, c_mem_init_file => "fr_cmplr_v5_0_bc5286c4b0615582.mif", zero_packing_factor => 1, num_paths => 1, num_filts => 1, col_mode => 0, c_has_ce => 1, chan_in_adv => 0, opbuff_memtype => 0, odd_symmetry => 1); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fr_cmplr_v5_0_bc5286c4b0615582 port map ( clk => clk, ce => ce, nd => nd, coef_ld => coef_ld, coef_we => coef_we, coef_din => coef_din, rfd => rfd, rdy => rdy, din => din, dout => dout); -- synthesis translate_on END fr_cmplr_v5_0_bc5286c4b0615582_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file mult_11_2_fe92ad55b7635191.vhd when simulating -- the core, mult_11_2_fe92ad55b7635191. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY mult_11_2_fe92ad55b7635191 IS PORT ( clk : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR(22 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); ce : IN STD_LOGIC; sclr : IN STD_LOGIC; p : OUT STD_LOGIC_VECTOR(42 DOWNTO 0) ); END mult_11_2_fe92ad55b7635191; ARCHITECTURE mult_11_2_fe92ad55b7635191_a OF mult_11_2_fe92ad55b7635191 IS -- synthesis translate_off COMPONENT wrapped_mult_11_2_fe92ad55b7635191 PORT ( clk : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR(22 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); ce : IN STD_LOGIC; sclr : IN STD_LOGIC; p : OUT STD_LOGIC_VECTOR(42 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_mult_11_2_fe92ad55b7635191 USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 23, c_b_type => 1, c_b_value => "10000001", c_b_width => 20, c_ccm_imp => 0, c_ce_overrides_sclr => 1, c_has_ce => 1, c_has_sclr => 1, c_has_zero_detect => 0, c_latency => 4, c_model_type => 0, c_mult_type => 1, c_optimize_goal => 1, c_out_high => 42, c_out_low => 0, c_round_output => 0, c_round_pt => 0, c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_mult_11_2_fe92ad55b7635191 PORT MAP ( clk => clk, a => a, b => b, ce => ce, sclr => sclr, p => p ); -- synthesis translate_on END mult_11_2_fe92ad55b7635191_a; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package conv_pkg is constant simulating : boolean := false -- synopsys translate_off or true -- synopsys translate_on ; constant xlUnsigned : integer := 1; constant xlSigned : integer := 2; constant xlFloat : integer := 3; constant xlWrap : integer := 1; constant xlSaturate : integer := 2; constant xlTruncate : integer := 1; constant xlRound : integer := 2; constant xlRoundBanker : integer := 3; constant xlAddMode : integer := 1; constant xlSubMode : integer := 2; attribute black_box : boolean; attribute syn_black_box : boolean; attribute fpga_dont_touch: string; attribute box_type : string; attribute keep : string; attribute syn_keep : boolean; function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; function std_logic_vector_to_signed(inp : std_logic_vector) return signed; function signed_to_std_logic_vector(inp : signed) return std_logic_vector; function unsigned_to_signed(inp : unsigned) return signed; function signed_to_unsigned(inp : signed) return unsigned; function pos(inp : std_logic_vector; arith : INTEGER) return boolean; function all_same(inp: std_logic_vector) return boolean; function all_zeros(inp: std_logic_vector) return boolean; function is_point_five(inp: std_logic_vector) return boolean; function all_ones(inp: std_logic_vector) return boolean; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function max_signed(width : INTEGER) return std_logic_vector; function min_signed(width : INTEGER) return std_logic_vector; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width: integer) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width, arith : integer) return std_logic_vector; function max(L, R: INTEGER) return INTEGER; function min(L, R: INTEGER) return INTEGER; function "="(left,right: STRING) return boolean; function boolean_to_signed (inp : boolean; width: integer) return signed; function boolean_to_unsigned (inp : boolean; width: integer) return unsigned; function boolean_to_vector (inp : boolean) return std_logic_vector; function std_logic_to_vector (inp : std_logic) return std_logic_vector; function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer; function std_logic_to_integer(constant inp : std_logic := '0') return integer; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector; function hex_string_to_std_logic_vector (inp : string; width : integer) return std_logic_vector; function makeZeroBinStr (width : integer) return STRING; function and_reduce(inp: std_logic_vector) return std_logic; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean; function is_binary_string_undefined (inp : string) return boolean; function is_XorU(inp : std_logic_vector) return boolean; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector; function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector; constant display_precision : integer := 20; function real_to_string (inp : real) return string; function valid_bin_string(inp : string) return boolean; function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; function std_logic_to_bin_string(inp : std_logic) return string; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string; type stdlogic_to_char_t is array(std_logic) of character; constant to_char : stdlogic_to_char_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'); -- synopsys translate_on end conv_pkg; package body conv_pkg is function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned is begin return unsigned (inp); end; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector is begin return std_logic_vector(inp); end; function std_logic_vector_to_signed(inp : std_logic_vector) return signed is begin return signed (inp); end; function signed_to_std_logic_vector(inp : signed) return std_logic_vector is begin return std_logic_vector(inp); end; function unsigned_to_signed (inp : unsigned) return signed is begin return signed(std_logic_vector(inp)); end; function signed_to_unsigned (inp : signed) return unsigned is begin return unsigned(std_logic_vector(inp)); end; function pos(inp : std_logic_vector; arith : INTEGER) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; if arith = xlUnsigned then return true; else if vec(width-1) = '0' then return true; else return false; end if; end if; return true; end; function max_signed(width : INTEGER) return std_logic_vector is variable ones : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin ones := (others => '1'); result(width-1) := '0'; result(width-2 downto 0) := ones; return result; end; function min_signed(width : INTEGER) return std_logic_vector is variable zeros : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin zeros := (others => '0'); result(width-1) := '1'; result(width-2 downto 0) := zeros; return result; end; function and_reduce(inp: std_logic_vector) return std_logic is variable result: std_logic; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := vec(0); if width > 1 then for i in 1 to width-1 loop result := result and vec(i); end loop; end if; return result; end; function all_same(inp: std_logic_vector) return boolean is variable result: boolean; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := true; if width > 0 then for i in 1 to width-1 loop if vec(i) /= vec(0) then result := false; end if; end loop; end if; return result; end; function all_zeros(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable zero : std_logic_vector(width-1 downto 0); variable result : boolean; begin zero := (others => '0'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then result := true; else result := false; end if; return result; end; function is_point_five(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (width > 1) then if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then result := true; else result := false; end if; else if (vec(width-1) = '1') then result := true; else result := false; end if; end if; return result; end; function all_ones(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable one : std_logic_vector(width-1 downto 0); variable result : boolean; begin one := (others => '1'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then result := true; else result := false; end if; return result; end; function full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable result : integer; begin result := old_width + 2; return result; end; function quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable right_of_dp, left_of_dp, result : integer; begin right_of_dp := max(new_bin_pt, old_bin_pt); left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); result := (old_width + 2) + (new_bin_pt - old_bin_pt); return result; end; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector is constant fp_width : integer := full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant fp_bin_pt : integer := old_bin_pt; constant fp_arith : integer := old_arith; variable full_precision_result : std_logic_vector(fp_width-1 downto 0); constant q_width : integer := quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant q_bin_pt : integer := new_bin_pt; constant q_arith : integer := old_arith; variable quantized_result : std_logic_vector(q_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin result := (others => '0'); full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, fp_arith); if (quantization = xlRound) then quantized_result := round_towards_inf(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); elsif (quantization = xlRoundBanker) then quantized_result := round_towards_even(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); else quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); end if; if (overflow = xlSaturate) then result := saturation_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); else result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); end if; return result; end; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; constant left_of_dp : integer := (new_width - new_bin_pt) - (old_width - old_bin_pt); constant right_of_dp : integer := (new_bin_pt - old_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable j : integer; begin vec := inp; for i in new_width-1 downto 0 loop j := i - right_of_dp; if ( j > old_width-1) then if (new_arith = xlUnsigned) then result(i) := '0'; else result(i) := vec(old_width-1); end if; elsif ( j >= 0) then result(i) := vec(j); else result(i) := '0'; end if; end loop; return result; end; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant q_width : integer := quotient'length; constant f_width : integer := fraction'length; constant vec_MSB : integer := q_width+f_width-1; constant result_MSB : integer := q_width+fraction_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := ( quotient & fraction ); if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant inp_width : integer := inp'length; constant vec_MSB : integer := inp_width-1; constant result_MSB : integer := result_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := inp; if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector is begin return inp(upper downto lower); end; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); end; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); end; function boolean_to_signed (inp : boolean; width : integer) return signed is variable result : signed(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_unsigned (inp : boolean; width : integer) return unsigned is variable result : unsigned(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_vector (inp : boolean) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function std_logic_to_vector (inp : std_logic) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result(0) := inp; return result; end; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then result := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else result := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; return result; end; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (new_arith = xlSigned) then if (vec(old_width-1) = '0') then one_or_zero(0) := '1'; end if; if (right_of_dp >= 2) and (right_of_dp <= old_width) then if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then one_or_zero(0) := '1'; end if; end if; if (right_of_dp >= 1) and (right_of_dp <= old_width) then if vec(right_of_dp-1) = '0' then one_or_zero(0) := '0'; end if; else one_or_zero(0) := '0'; end if; else if (right_of_dp >= 1) and (right_of_dp <= old_width) then one_or_zero(0) := vec(right_of_dp-1); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (right_of_dp >= 1) and (right_of_dp <= old_width) then if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then one_or_zero(0) := vec(right_of_dp-1); else one_or_zero(0) := vec(right_of_dp); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant left_of_dp : integer := (old_width - old_bin_pt) - (new_width - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable overflow : boolean; begin vec := inp; overflow := true; result := (others => '0'); if (new_width >= old_width) then overflow := false; end if; if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if (old_arith = xlSigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then if (vec(new_width-1) = '0') then overflow := false; end if; end if; end if; end if; if (old_arith = xlUnsigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then overflow := false; end if; end if; end if; if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if overflow then if new_arith = xlSigned then if vec(old_width-1) = '0' then result := max_signed(new_width); else result := min_signed(new_width); end if; else if ((old_arith = xlSigned) and vec(old_width-1) = '1') then result := (others => '0'); else result := (others => '1'); end if; end if; else if (old_arith = xlSigned) and (new_arith = xlUnsigned) then if (vec(old_width-1) = '1') then vec := (others => '0'); end if; end if; if new_width <= old_width then result := vec(new_width-1 downto 0); else if new_arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; end if; end if; return result; end; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); variable result_arith : integer; begin if (old_arith = xlSigned) and (new_arith = xlUnsigned) then result_arith := xlSigned; end if; result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); return result; end; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is begin return max(a_bin_pt, b_bin_pt); end; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER is begin return max(a_width - a_bin_pt, b_width - b_bin_pt); end; function pad_LSB(inp : std_logic_vector; new_width: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; constant pad_pos : integer := new_width - orig_width - 1; begin vec := inp; pos := new_width-1; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pad_pos >= 0 then for i in pad_pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := vec(old_width-1); end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := '0'; end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); begin result(0) := inp; for i in new_width-1 downto 1 loop result(i) := '0'; end loop; return result; end; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; return result; end; function pad_LSB(inp : std_logic_vector; new_width, arith: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; begin vec := inp; pos := new_width-1; if (arith = xlUnsigned) then result(pos) := '0'; pos := pos - 1; else result(pos) := vec(orig_width-1); pos := pos - 1; end if; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pos >= 0 then for i in pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector is variable vec : std_logic_vector(old_width-1 downto 0); variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if delta > 0 then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; function max(L, R: INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; function "="(left,right: STRING) return boolean is begin if (left'length /= right'length) then return false; else test : for i in 1 to left'length loop if left(i) /= right(i) then return false; end if; end loop test; return true; end if; end; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'X' ) then result := true; end if; end loop; return result; end; function is_binary_string_undefined (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'U' ) then result := true; end if; end loop; return result; end; function is_XorU(inp : std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; result := false; for i in 0 to width-1 loop if (vec(i) = 'U') or (vec(i) = 'X') then result := true; end if; end loop; return result; end; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real is variable vec : std_logic_vector(inp'length-1 downto 0); variable result, shift_val, undefined_real : real; variable neg_num : boolean; begin vec := inp; result := 0.0; neg_num := false; if vec(inp'length-1) = '1' then neg_num := true; end if; for i in 0 to inp'length-1 loop if vec(i) = 'U' or vec(i) = 'X' then return undefined_real; end if; if arith = xlSigned then if neg_num then if vec(i) = '0' then result := result + 2.0**i; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; end loop; if arith = xlSigned then if neg_num then result := result + 1.0; result := result * (-1.0); end if; end if; shift_val := 2.0**(-1*bin_pt); result := result * shift_val; return result; end; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real is variable result : real := 0.0; begin if inp = '1' then result := 1.0; end if; if arith = xlSigned then assert false report "It doesn't make sense to convert a 1 bit number to a signed real."; end if; return result; end; -- synopsys translate_on function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); begin if (arith = xlSigned) then signed_val := to_signed(inp, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(inp, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer is constant width : integer := inp'length; variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); variable result : integer; begin if (arith = xlSigned) then signed_val := std_logic_vector_to_signed(inp); result := to_integer(signed_val); else unsigned_val := std_logic_vector_to_unsigned(inp); result := to_integer(unsigned_val); end if; return result; end; function std_logic_to_integer(constant inp : std_logic := '0') return integer is begin if inp = '1' then return 1; else return 0; end if; end; function makeZeroBinStr (width : integer) return STRING is variable result : string(1 to width+3); begin result(1) := '0'; result(2) := 'b'; for i in 3 to width+2 loop result(i) := '0'; end loop; result(width+3) := '.'; return result; end; -- synopsys translate_off function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); begin result := (others => '0'); return result; end; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector is variable real_val : real; variable int_val : integer; variable result : std_logic_vector(width-1 downto 0) := (others => '0'); variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); variable signed_val : signed(width-1 downto 0) := (others => '0'); begin real_val := inp; int_val := integer(real_val * 2.0**(bin_pt)); if (arith = xlSigned) then signed_val := to_signed(int_val, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(int_val, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; -- synopsys translate_on function valid_bin_string (inp : string) return boolean is variable vec : string(1 to inp'length); begin vec := inp; if (vec(1) = '0' and vec(2) = 'b') then return true; else return false; end if; end; function hex_string_to_std_logic_vector(inp: string; width : integer) return std_logic_vector is constant strlen : integer := inp'LENGTH; variable result : std_logic_vector(width-1 downto 0); variable bitval : std_logic_vector((strlen*4)-1 downto 0); variable posn : integer; variable ch : character; variable vec : string(1 to strlen); begin vec := inp; result := (others => '0'); posn := (strlen*4)-1; for i in 1 to strlen loop ch := vec(i); case ch is when '0' => bitval(posn downto posn-3) := "0000"; when '1' => bitval(posn downto posn-3) := "0001"; when '2' => bitval(posn downto posn-3) := "0010"; when '3' => bitval(posn downto posn-3) := "0011"; when '4' => bitval(posn downto posn-3) := "0100"; when '5' => bitval(posn downto posn-3) := "0101"; when '6' => bitval(posn downto posn-3) := "0110"; when '7' => bitval(posn downto posn-3) := "0111"; when '8' => bitval(posn downto posn-3) := "1000"; when '9' => bitval(posn downto posn-3) := "1001"; when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; when others => bitval(posn downto posn-3) := "XXXX"; -- synopsys translate_off ASSERT false REPORT "Invalid hex value" SEVERITY ERROR; -- synopsys translate_on end case; posn := posn - 4; end loop; if (width <= strlen*4) then result := bitval(width-1 downto 0); else result((strlen*4)-1 downto 0) := bitval; end if; return result; end; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector is variable pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(inp'length-1 downto 0); begin vec := inp; pos := inp'length-1; result := (others => '0'); for i in 1 to vec'length loop -- synopsys translate_off if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then assert false report "Input string is larger than output std_logic_vector. Truncating output."; return result; end if; -- synopsys translate_on if vec(i) = '0' then result(pos) := '0'; pos := pos - 1; end if; if vec(i) = '1' then result(pos) := '1'; pos := pos - 1; end if; -- synopsys translate_off if (vec(i) = 'X' or vec(i) = 'U') then result(pos) := 'U'; pos := pos - 1; end if; -- synopsys translate_on end loop; return result; end; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector is constant str_width : integer := width + 4; constant inp_len : integer := inp'length; constant num_elements : integer := (inp_len + 1)/str_width; constant reverse_index : integer := (num_elements-1) - index; variable left_pos : integer; variable right_pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(width-1 downto 0); begin vec := inp; result := (others => '0'); if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := 1; right_pos := width + 3; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := (reverse_index * str_width) + 1; right_pos := left_pos + width + 2; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; return result; end; -- synopsys translate_off function std_logic_vector_to_bin_string(inp : std_logic_vector) return string is variable vec : std_logic_vector(1 to inp'length); variable result : string(vec'range); begin vec := inp; for i in vec'range loop result(i) := to_char(vec(i)); end loop; return result; end; function std_logic_to_bin_string(inp : std_logic) return string is variable result : string(1 to 3); begin result(1) := '0'; result(2) := 'b'; result(3) := to_char(inp); return result; end; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string is variable width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable str_pos : integer; variable result : string(1 to width+3); begin vec := inp; str_pos := 1; result(str_pos) := '0'; str_pos := 2; result(str_pos) := 'b'; str_pos := 3; for i in width-1 downto 0 loop if (((width+3) - bin_pt) = str_pos) then result(str_pos) := '.'; str_pos := str_pos + 1; end if; result(str_pos) := to_char(vec(i)); str_pos := str_pos + 1; end loop; if (bin_pt = 0) then result(str_pos) := '.'; end if; return result; end; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string is variable result : string(1 to width); variable vec : std_logic_vector(width-1 downto 0); begin vec := real_to_std_logic_vector(inp, width, bin_pt, arith); result := std_logic_vector_to_bin_string(vec); return result; end; function real_to_string (inp : real) return string is variable result : string(1 to display_precision) := (others => ' '); begin result(real'image(inp)'range) := real'image(inp); return result; end; -- synopsys translate_on end conv_pkg; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity srl17e is generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end srl17e; architecture structural of srl17e is component SRL16E port (D : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; Q : out STD_ULOGIC); end component; attribute syn_black_box of SRL16E : component is true; attribute fpga_dont_touch of SRL16E : component is "true"; component FDE port( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC); end component; attribute syn_black_box of FDE : component is true; attribute fpga_dont_touch of FDE : component is "true"; constant a : std_logic_vector(4 downto 0) := integer_to_std_logic_vector(latency-2,5,xlSigned); signal d_delayed : std_logic_vector(width-1 downto 0); signal srl16_out : std_logic_vector(width-1 downto 0); begin d_delayed <= d after 200 ps; reg_array : for i in 0 to width-1 generate srl16_used: if latency > 1 generate u1 : srl16e port map(clk => clk, d => d_delayed(i), q => srl16_out(i), ce => ce, a0 => a(0), a1 => a(1), a2 => a(2), a3 => a(3)); end generate; srl16_not_used: if latency <= 1 generate srl16_out(i) <= d_delayed(i); end generate; fde_used: if latency /= 0 generate u2 : fde port map(c => clk, d => srl16_out(i), q => q(i), ce => ce); end generate; fde_not_used: if latency = 0 generate q(i) <= srl16_out(i); end generate; end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg; architecture structural of synth_reg is component srl17e generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end component; function calc_num_srl17es (latency : integer) return integer is variable remaining_latency : integer; variable result : integer; begin result := latency / 17; remaining_latency := latency - (result * 17); if (remaining_latency /= 0) then result := result + 1; end if; return result; end; constant complete_num_srl17es : integer := latency / 17; constant num_srl17es : integer := calc_num_srl17es(latency); constant remaining_latency : integer := latency - (complete_num_srl17es * 17); type register_array is array (num_srl17es downto 0) of std_logic_vector(width-1 downto 0); signal z : register_array; begin z(0) <= i; complete_ones : if complete_num_srl17es > 0 generate srl17e_array: for i in 0 to complete_num_srl17es-1 generate delay_comp : srl17e generic map (width => width, latency => 17) port map (clk => clk, ce => ce, d => z(i), q => z(i+1)); end generate; end generate; partial_one : if remaining_latency > 0 generate last_srl17e : srl17e generic map (width => width, latency => remaining_latency) port map (clk => clk, ce => ce, d => z(num_srl17es-1), q => z(num_srl17es)); end generate; o <= z(num_srl17es); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg_reg; architecture behav of synth_reg_reg is type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0); signal reg_bank : reg_array_type := (others => (others => '0')); signal reg_bank_in : reg_array_type := (others => (others => '0')); attribute syn_allow_retiming : boolean; attribute syn_srlstyle : string; attribute syn_allow_retiming of reg_bank : signal is true; attribute syn_allow_retiming of reg_bank_in : signal is true; attribute syn_srlstyle of reg_bank : signal is "registers"; attribute syn_srlstyle of reg_bank_in : signal is "registers"; begin latency_eq_0: if latency = 0 generate o <= i; end generate latency_eq_0; latency_gt_0: if latency >= 1 generate o <= reg_bank(latency-1); reg_bank_in(0) <= i; loop_gen: for idx in latency-2 downto 0 generate reg_bank_in(idx+1) <= reg_bank(idx); end generate loop_gen; sync_loop: for sync_idx in latency-1 downto 0 generate sync_proc: process (clk) begin if clk'event and clk = '1' then if clr = '1' then reg_bank_in <= (others => (others => '0')); elsif ce = '1' then reg_bank(sync_idx) <= reg_bank_in(sync_idx); end if; end if; end process sync_proc; end generate sync_loop; end generate latency_gt_0; end behav; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity single_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end single_reg_w_init; architecture structural of single_reg_w_init is function build_init_const(width: integer; init_index: integer; init_value: bit_vector) return std_logic_vector is variable result: std_logic_vector(width - 1 downto 0); begin if init_index = 0 then result := (others => '0'); elsif init_index = 1 then result := (others => '0'); result(0) := '1'; else result := to_stdlogicvector(init_value); end if; return result; end; component fdre port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; r: in std_ulogic ); end component; attribute syn_black_box of fdre: component is true; attribute fpga_dont_touch of fdre: component is "true"; component fdse port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; s: in std_ulogic ); end component; attribute syn_black_box of fdse: component is true; attribute fpga_dont_touch of fdse: component is "true"; constant init_const: std_logic_vector(width - 1 downto 0) := build_init_const(width, init_index, init_value); begin fd_prim_array: for index in 0 to width - 1 generate bit_is_0: if (init_const(index) = '0') generate fdre_comp: fdre port map ( c => clk, d => i(index), q => o(index), ce => ce, r => clr ); end generate; bit_is_1: if (init_const(index) = '1') generate fdse_comp: fdse port map ( c => clk, d => i(index), q => o(index), ce => ce, s => clr ); end generate; end generate; end architecture structural; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000"; latency: integer := 1 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end synth_reg_w_init; architecture structural of synth_reg_w_init is component single_reg_w_init generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); signal dly_clr: std_logic; begin latency_eq_0: if (latency = 0) generate o <= i; end generate; latency_gt_0: if (latency >= 1) generate dly_i((latency + 1) * width - 1 downto latency * width) <= i after 200 ps; dly_clr <= clr after 200 ps; fd_array: for index in latency downto 1 generate reg_comp: single_reg_w_init generic map ( width => width, init_index => init_index, init_value => init_value ) port map ( clk => clk, i => dly_i((index + 1) * width - 1 downto index * width), o => dly_i(index * width - 1 downto (index - 1) * width), ce => ce, clr => dly_clr ); end generate; o <= dly_i(width - 1 downto 0); end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mux_029cd20aa9 is port ( sel : in std_logic_vector((1 - 1) downto 0); d0 : in std_logic_vector((22 - 1) downto 0); d1 : in std_logic_vector((23 - 1) downto 0); y : out std_logic_vector((23 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mux_029cd20aa9; architecture behavior of mux_029cd20aa9 is signal sel_1_20: std_logic_vector((1 - 1) downto 0); signal d0_1_24: std_logic_vector((22 - 1) downto 0); signal d1_1_27: std_logic_vector((23 - 1) downto 0); type array_type_pipe_16_22 is array (0 to (1 - 1)) of std_logic_vector((23 - 1) downto 0); signal pipe_16_22: array_type_pipe_16_22 := ( 0 => "00000000000000000000000"); signal pipe_16_22_front_din: std_logic_vector((23 - 1) downto 0); signal pipe_16_22_back: std_logic_vector((23 - 1) downto 0); signal pipe_16_22_push_front_pop_back_en: std_logic; signal unregy_join_6_1: std_logic_vector((23 - 1) downto 0); begin sel_1_20 <= sel; d0_1_24 <= d0; d1_1_27 <= d1; pipe_16_22_back <= pipe_16_22(0); proc_pipe_16_22: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (pipe_16_22_push_front_pop_back_en = '1')) then pipe_16_22(0) <= pipe_16_22_front_din; end if; end if; end process proc_pipe_16_22; proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20) is begin case sel_1_20 is when "0" => unregy_join_6_1 <= cast(d0_1_24, 0, 23, 0, xlSigned); when others => unregy_join_6_1 <= d1_1_27; end case; end process proc_switch_6_1; pipe_16_22_front_din <= unregy_join_6_1; pipe_16_22_push_front_pop_back_en <= '1'; y <= pipe_16_22_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity negate_142bd36a06 is port ( ip : in std_logic_vector((22 - 1) downto 0); op : out std_logic_vector((23 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end negate_142bd36a06; architecture behavior of negate_142bd36a06 is signal ip_18_25: signed((22 - 1) downto 0); type array_type_op_mem_42_20 is array (0 to (1 - 1)) of signed((23 - 1) downto 0); signal op_mem_42_20: array_type_op_mem_42_20 := ( 0 => "00000000000000000000000"); signal op_mem_42_20_front_din: signed((23 - 1) downto 0); signal op_mem_42_20_back: signed((23 - 1) downto 0); signal op_mem_42_20_push_front_pop_back_en: std_logic; signal cast_30_16: signed((23 - 1) downto 0); signal internal_ip_30_1_neg: signed((23 - 1) downto 0); begin ip_18_25 <= std_logic_vector_to_signed(ip); op_mem_42_20_back <= op_mem_42_20(0); proc_op_mem_42_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_42_20_push_front_pop_back_en = '1')) then op_mem_42_20(0) <= op_mem_42_20_front_din; end if; end if; end process proc_op_mem_42_20; cast_30_16 <= s2s_cast(ip_18_25, 0, 23, 0); internal_ip_30_1_neg <= -cast_30_16; op_mem_42_20_front_din <= internal_ip_30_1_neg; op_mem_42_20_push_front_pop_back_en <= '1'; op <= signed_to_std_logic_vector(op_mem_42_20_back); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlregister is generic (d_width : integer := 5; init_value : bit_vector := b"00"); port (d : in std_logic_vector (d_width-1 downto 0); rst : in std_logic_vector(0 downto 0) := "0"; en : in std_logic_vector(0 downto 0) := "1"; ce : in std_logic; clk : in std_logic; q : out std_logic_vector (d_width-1 downto 0)); end xlregister; architecture behavior of xlregister is component synth_reg_w_init generic (width : integer; init_index : integer; init_value : bit_vector; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; -- synopsys translate_off signal real_d, real_q : real; -- synopsys translate_on signal internal_clr : std_logic; signal internal_ce : std_logic; begin internal_clr <= rst(0) and ce; internal_ce <= en(0) and ce; synth_reg_inst : synth_reg_w_init generic map (width => d_width, init_index => 2, init_value => init_value, latency => 1) port map (i => d, ce => internal_ce, clr => internal_clr, clk => clk, o => q); end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlslice is generic ( new_msb : integer := 9; new_lsb : integer := 1; x_width : integer := 16; y_width : integer := 8); port ( x : in std_logic_vector (x_width-1 downto 0); y : out std_logic_vector (y_width-1 downto 0)); end xlslice; architecture behavior of xlslice is begin y <= x(new_msb downto new_lsb); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_822933f89b is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_822933f89b; architecture behavior of constant_822933f89b is begin op <= "000"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_a1c496ea88 is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_a1c496ea88; architecture behavior of constant_a1c496ea88 is begin op <= "001"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_1f5cc32f1e is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_1f5cc32f1e; architecture behavior of constant_1f5cc32f1e is begin op <= "010"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_0f59f02ba5 is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_0f59f02ba5; architecture behavior of constant_0f59f02ba5 is begin op <= "011"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_469094441c is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_469094441c; architecture behavior of constant_469094441c is begin op <= "100"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity logical_80f90b97d0 is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end logical_80f90b97d0; architecture behavior of logical_80f90b97d0 is signal d0_1_24: std_logic; signal d1_1_27: std_logic; signal fully_2_1_bit: std_logic; begin d0_1_24 <= d0(0); d1_1_27 <= d1(0); fully_2_1_bit <= d0_1_24 and d1_1_27; y <= std_logic_to_vector(fully_2_1_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_8fc7f5539b is port ( a : in std_logic_vector((3 - 1) downto 0); b : in std_logic_vector((3 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_8fc7f5539b; architecture behavior of relational_8fc7f5539b is signal a_1_31: unsigned((3 - 1) downto 0); signal b_1_34: unsigned((3 - 1) downto 0); signal result_12_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); result_12_3_rel <= a_1_31 = b_1_34; op <= boolean_to_vector(result_12_3_rel); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity xlcounter_limit is generic ( core_name0: string := ""; op_width: integer := 5; op_arith: integer := xlSigned; cnt_63_48: integer:= 0; cnt_47_32: integer:= 0; cnt_31_16: integer:= 0; cnt_15_0: integer:= 0; count_limited: integer := 0 ); port ( ce: in std_logic; clr: in std_logic; clk: in std_logic; op: out std_logic_vector(op_width - 1 downto 0); up: in std_logic_vector(0 downto 0) := (others => '0'); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0) ); end xlcounter_limit ; architecture behavior of xlcounter_limit is signal high_cnt_to: std_logic_vector(31 downto 0); signal low_cnt_to: std_logic_vector(31 downto 0); signal cnt_to: std_logic_vector(63 downto 0); signal core_sinit, op_thresh0, core_ce: std_logic; signal rst_overrides_en: std_logic; signal op_net: std_logic_vector(op_width - 1 downto 0); -- synopsys translate_off signal real_op : real; -- synopsys translate_on function equals(op, cnt_to : std_logic_vector; width, arith : integer) return std_logic is variable signed_op, signed_cnt_to : signed (width - 1 downto 0); variable unsigned_op, unsigned_cnt_to : unsigned (width - 1 downto 0); variable result : std_logic; begin -- synopsys translate_off if ((is_XorU(op)) or (is_XorU(cnt_to)) ) then result := '0'; return result; end if; -- synopsys translate_on if (op = cnt_to) then result := '1'; else result := '0'; end if; return result; end; component cntr_11_0_e859c6662c373192 port ( clk: in std_logic; ce: in std_logic; SINIT: in std_logic; q: out std_logic_vector(op_width - 1 downto 0) ); end component; attribute syn_black_box of cntr_11_0_e859c6662c373192: component is true; attribute fpga_dont_touch of cntr_11_0_e859c6662c373192: component is "true"; attribute box_type of cntr_11_0_e859c6662c373192: component is "black_box"; component cntr_11_0_862f833518f4973a port ( clk: in std_logic; ce: in std_logic; SINIT: in std_logic; q: out std_logic_vector(op_width - 1 downto 0) ); end component; attribute syn_black_box of cntr_11_0_862f833518f4973a: component is true; attribute fpga_dont_touch of cntr_11_0_862f833518f4973a: component is "true"; attribute box_type of cntr_11_0_862f833518f4973a: component is "black_box"; -- synopsys translate_off constant zeroVec : std_logic_vector(op_width - 1 downto 0) := (others => '0'); constant oneVec : std_logic_vector(op_width - 1 downto 0) := (others => '1'); constant zeroStr : string(1 to op_width) := std_logic_vector_to_bin_string(zeroVec); constant oneStr : string(1 to op_width) := std_logic_vector_to_bin_string(oneVec); -- synopsys translate_on begin -- synopsys translate_off -- synopsys translate_on cnt_to(63 downto 48) <= integer_to_std_logic_vector(cnt_63_48, 16, op_arith); cnt_to(47 downto 32) <= integer_to_std_logic_vector(cnt_47_32, 16, op_arith); cnt_to(31 downto 16) <= integer_to_std_logic_vector(cnt_31_16, 16, op_arith); cnt_to(15 downto 0) <= integer_to_std_logic_vector(cnt_15_0, 16, op_arith); op <= op_net; core_ce <= ce and en(0); rst_overrides_en <= rst(0) or en(0); limit : if (count_limited = 1) generate eq_cnt_to : process (op_net, cnt_to) begin op_thresh0 <= equals(op_net, cnt_to(op_width - 1 downto 0), op_width, op_arith); end process; core_sinit <= (op_thresh0 or clr or rst(0)) and ce and rst_overrides_en; end generate; no_limit : if (count_limited = 0) generate core_sinit <= (clr or rst(0)) and ce and rst_overrides_en; end generate; comp0: if ((core_name0 = "cntr_11_0_e859c6662c373192")) generate core_instance0: cntr_11_0_e859c6662c373192 port map ( clk => clk, ce => core_ce, SINIT => core_sinit, q => op_net ); end generate; comp1: if ((core_name0 = "cntr_11_0_862f833518f4973a")) generate core_instance1: cntr_11_0_862f833518f4973a port map ( clk => clk, ce => core_ce, SINIT => core_sinit, q => op_net ); end generate; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity inverter_e5b38cca3b is port ( ip : in std_logic_vector((1 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end inverter_e5b38cca3b; architecture behavior of inverter_e5b38cca3b is signal ip_1_26: boolean; type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean; signal op_mem_22_20: array_type_op_mem_22_20 := ( 0 => false); signal op_mem_22_20_front_din: boolean; signal op_mem_22_20_back: boolean; signal op_mem_22_20_push_front_pop_back_en: std_logic; signal internal_ip_12_1_bitnot: boolean; begin ip_1_26 <= ((ip) = "1"); op_mem_22_20_back <= op_mem_22_20(0); proc_op_mem_22_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then op_mem_22_20(0) <= op_mem_22_20_front_din; end if; end if; end process proc_op_mem_22_20; internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1"); op_mem_22_20_push_front_pop_back_en <= '0'; op <= boolean_to_vector(internal_ip_12_1_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity xlfir_compiler_d885873ecd26cf15cdb95a5d10c7a292 is port( ce:in std_logic; ce_logic_1:in std_logic; clk:in std_logic; clk_logic_1:in std_logic; coef_din:in std_logic_vector(6 downto 0); coef_ld:in std_logic; coef_we:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(18 downto 0); rdy:out std_logic; rfd:out std_logic; src_ce:in std_logic; src_clk:in std_logic ); end xlfir_compiler_d885873ecd26cf15cdb95a5d10c7a292; architecture behavior of xlfir_compiler_d885873ecd26cf15cdb95a5d10c7a292 is component fr_cmplr_v5_0_0d2261239884a389 port( ce:in std_logic; clk:in std_logic; coef_din:in std_logic_vector(6 downto 0); coef_ld:in std_logic; coef_we:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(18 downto 0); nd:in std_logic; rdy:out std_logic; rfd:out std_logic ); end component; begin fr_cmplr_v5_0_0d2261239884a389_instance : fr_cmplr_v5_0_0d2261239884a389 port map( ce=>ce, clk=>clk, coef_din=>coef_din, coef_ld=>coef_ld, coef_we=>coef_we, din=>din, dout=>dout, nd=>ce_logic_1, rdy=>rdy, rfd=>rfd ); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity xlfir_compiler_1e4b453df468e83a1cea0a55c8d9b90f is port( ce:in std_logic; ce_logic_1:in std_logic; clk:in std_logic; clk_logic_1:in std_logic; coef_din:in std_logic_vector(6 downto 0); coef_ld:in std_logic; coef_we:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(18 downto 0); rdy:out std_logic; rfd:out std_logic; src_ce:in std_logic; src_clk:in std_logic ); end xlfir_compiler_1e4b453df468e83a1cea0a55c8d9b90f; architecture behavior of xlfir_compiler_1e4b453df468e83a1cea0a55c8d9b90f is component fr_cmplr_v5_0_983c85a69a3a58e7 port( ce:in std_logic; clk:in std_logic; coef_din:in std_logic_vector(6 downto 0); coef_ld:in std_logic; coef_we:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(18 downto 0); nd:in std_logic; rdy:out std_logic; rfd:out std_logic ); end component; begin fr_cmplr_v5_0_983c85a69a3a58e7_instance : fr_cmplr_v5_0_983c85a69a3a58e7 port map( ce=>ce, clk=>clk, coef_din=>coef_din, coef_ld=>coef_ld, coef_we=>coef_we, din=>din, dout=>dout, nd=>ce_logic_1, rdy=>rdy, rfd=>rfd ); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity xlfir_compiler_5077ad6f33cdc3f379ad80845501c286 is port( ce:in std_logic; ce_logic_1:in std_logic; clk:in std_logic; clk_logic_1:in std_logic; coef_din:in std_logic_vector(6 downto 0); coef_ld:in std_logic; coef_we:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(18 downto 0); rdy:out std_logic; rfd:out std_logic; src_ce:in std_logic; src_clk:in std_logic ); end xlfir_compiler_5077ad6f33cdc3f379ad80845501c286; architecture behavior of xlfir_compiler_5077ad6f33cdc3f379ad80845501c286 is component fr_cmplr_v5_0_bc5286c4b0615582 port( ce:in std_logic; clk:in std_logic; coef_din:in std_logic_vector(6 downto 0); coef_ld:in std_logic; coef_we:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(18 downto 0); nd:in std_logic; rdy:out std_logic; rfd:out std_logic ); end component; begin fr_cmplr_v5_0_bc5286c4b0615582_instance : fr_cmplr_v5_0_bc5286c4b0615582 port map( ce=>ce, clk=>clk, coef_din=>coef_din, coef_ld=>coef_ld, coef_we=>coef_we, din=>din, dout=>dout, nd=>ce_logic_1, rdy=>rdy, rfd=>rfd ); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xladdsub is generic ( core_name0: string := ""; a_width: integer := 16; a_bin_pt: integer := 4; a_arith: integer := xlUnsigned; c_in_width: integer := 16; c_in_bin_pt: integer := 4; c_in_arith: integer := xlUnsigned; c_out_width: integer := 16; c_out_bin_pt: integer := 4; c_out_arith: integer := xlUnsigned; b_width: integer := 8; b_bin_pt: integer := 2; b_arith: integer := xlUnsigned; s_width: integer := 17; s_bin_pt: integer := 4; s_arith: integer := xlUnsigned; rst_width: integer := 1; rst_bin_pt: integer := 0; rst_arith: integer := xlUnsigned; en_width: integer := 1; en_bin_pt: integer := 0; en_arith: integer := xlUnsigned; full_s_width: integer := 17; full_s_arith: integer := xlUnsigned; mode: integer := xlAddMode; extra_registers: integer := 0; latency: integer := 0; quantization: integer := xlTruncate; overflow: integer := xlWrap; c_latency: integer := 0; c_output_width: integer := 17; c_has_c_in : integer := 0; c_has_c_out : integer := 0 ); port ( a: in std_logic_vector(a_width - 1 downto 0); b: in std_logic_vector(b_width - 1 downto 0); c_in : in std_logic_vector (0 downto 0) := "0"; ce: in std_logic; clr: in std_logic := '0'; clk: in std_logic; rst: in std_logic_vector(rst_width - 1 downto 0) := "0"; en: in std_logic_vector(en_width - 1 downto 0) := "1"; c_out : out std_logic_vector (0 downto 0); s: out std_logic_vector(s_width - 1 downto 0) ); end xladdsub; architecture behavior of xladdsub is component synth_reg generic ( width: integer := 16; latency: integer := 5 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function format_input(inp: std_logic_vector; old_width, delta, new_arith, new_width: integer) return std_logic_vector is variable vec: std_logic_vector(old_width-1 downto 0); variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0); variable result: std_logic_vector(new_width-1 downto 0); begin vec := inp; if (delta > 0) then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt); constant full_a_width: integer := full_s_width; constant full_b_width: integer := full_s_width; signal full_a: std_logic_vector(full_a_width - 1 downto 0); signal full_b: std_logic_vector(full_b_width - 1 downto 0); signal core_s: std_logic_vector(full_s_width - 1 downto 0); signal conv_s: std_logic_vector(s_width - 1 downto 0); signal temp_cout : std_logic; signal internal_clr: std_logic; signal internal_ce: std_logic; signal extra_reg_ce: std_logic; signal override: std_logic; signal logic1: std_logic_vector(0 downto 0); component addsb_11_0_e7b4231f2ca96446 port ( a: in std_logic_vector(22 - 1 downto 0); clk: in std_logic:= '0'; ce: in std_logic:= '0'; s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(22 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_e7b4231f2ca96446: component is true; attribute fpga_dont_touch of addsb_11_0_e7b4231f2ca96446: component is "true"; attribute box_type of addsb_11_0_e7b4231f2ca96446: component is "black_box"; component addsb_11_0_da33f2d4b3b54185 port ( a: in std_logic_vector(20 - 1 downto 0); clk: in std_logic:= '0'; ce: in std_logic:= '0'; s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(20 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_da33f2d4b3b54185: component is true; attribute fpga_dont_touch of addsb_11_0_da33f2d4b3b54185: component is "true"; attribute box_type of addsb_11_0_da33f2d4b3b54185: component is "black_box"; component addsb_11_0_48bcbc42a6774592 port ( a: in std_logic_vector(21 - 1 downto 0); clk: in std_logic:= '0'; ce: in std_logic:= '0'; s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(21 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_48bcbc42a6774592: component is true; attribute fpga_dont_touch of addsb_11_0_48bcbc42a6774592: component is "true"; attribute box_type of addsb_11_0_48bcbc42a6774592: component is "black_box"; begin internal_clr <= (clr or (rst(0))) and ce; internal_ce <= ce and en(0); logic1(0) <= '1'; addsub_process: process (a, b, core_s) begin full_a <= format_input (a, a_width, b_bin_pt - a_bin_pt, a_arith, full_a_width); full_b <= format_input (b, b_width, a_bin_pt - b_bin_pt, b_arith, full_b_width); conv_s <= convert_type (core_s, full_s_width, full_s_bin_pt, full_s_arith, s_width, s_bin_pt, s_arith, quantization, overflow); end process addsub_process; comp0: if ((core_name0 = "addsb_11_0_e7b4231f2ca96446")) generate core_instance0: addsb_11_0_e7b4231f2ca96446 port map ( a => full_a, clk => clk, ce => internal_ce, s => core_s, b => full_b ); end generate; comp1: if ((core_name0 = "addsb_11_0_da33f2d4b3b54185")) generate core_instance1: addsb_11_0_da33f2d4b3b54185 port map ( a => full_a, clk => clk, ce => internal_ce, s => core_s, b => full_b ); end generate; comp2: if ((core_name0 = "addsb_11_0_48bcbc42a6774592")) generate core_instance2: addsb_11_0_48bcbc42a6774592 port map ( a => full_a, clk => clk, ce => internal_ce, s => core_s, b => full_b ); end generate; latency_test: if (extra_registers > 0) generate override_test: if (c_latency > 1) generate override_pipe: synth_reg generic map ( width => 1, latency => c_latency ) port map ( i => logic1, ce => internal_ce, clr => internal_clr, clk => clk, o(0) => override); extra_reg_ce <= ce and en(0) and override; end generate override_test; no_override: if ((c_latency = 0) or (c_latency = 1)) generate extra_reg_ce <= ce and en(0); end generate no_override; extra_reg: synth_reg generic map ( width => s_width, latency => extra_registers ) port map ( i => conv_s, ce => extra_reg_ce, clr => internal_clr, clk => clk, o => s ); cout_test: if (c_has_c_out = 1) generate c_out_extra_reg: synth_reg generic map ( width => 1, latency => extra_registers ) port map ( i(0) => temp_cout, ce => extra_reg_ce, clr => internal_clr, clk => clk, o => c_out ); end generate cout_test; end generate; latency_s: if ((latency = 0) or (extra_registers = 0)) generate s <= conv_s; end generate latency_s; latency0: if (((latency = 0) or (extra_registers = 0)) and (c_has_c_out = 1)) generate c_out(0) <= temp_cout; end generate latency0; tie_dangling_cout: if (c_has_c_out = 0) generate c_out <= "0"; end generate tie_dangling_cout; end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlpassthrough is generic ( din_width : integer := 16; dout_width : integer := 16 ); port ( din : in std_logic_vector (din_width-1 downto 0); dout : out std_logic_vector (dout_width-1 downto 0)); end xlpassthrough; architecture passthrough_arch of xlpassthrough is begin dout <= din; end passthrough_arch; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity convert_func_call is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end convert_func_call; architecture behavior of convert_func_call is begin result <= convert_type(din, din_width, din_bin_pt, din_arith, dout_width, dout_bin_pt, dout_arith, quantization, overflow); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlconvert is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; en_width : integer := 1; en_bin_pt : integer := 0; en_arith : integer := xlUnsigned; bool_conversion : integer :=0; latency : integer := 0; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); en : in std_logic_vector (en_width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; dout : out std_logic_vector (dout_width-1 downto 0)); end xlconvert; architecture behavior of xlconvert is component synth_reg generic (width : integer; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; component convert_func_call generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end component; -- synopsys translate_off -- synopsys translate_on signal result : std_logic_vector(dout_width-1 downto 0); signal internal_ce : std_logic; begin -- synopsys translate_off -- synopsys translate_on internal_ce <= ce and en(0); bool_conversion_generate : if (bool_conversion = 1) generate result <= din; end generate; std_conversion_generate : if (bool_conversion = 0) generate convert : convert_func_call generic map ( din_width => din_width, din_bin_pt => din_bin_pt, din_arith => din_arith, dout_width => dout_width, dout_bin_pt => dout_bin_pt, dout_arith => dout_arith, quantization => quantization, overflow => overflow) port map ( din => din, result => result); end generate; latency_test : if (latency > 0) generate reg : synth_reg generic map ( width => dout_width, latency => latency ) port map ( i => result, ce => internal_ce, clr => clr, clk => clk, o => dout ); end generate; latency0 : if (latency = 0) generate dout <= result; end generate latency0; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlmult is generic ( core_name0: string := ""; a_width: integer := 4; a_bin_pt: integer := 2; a_arith: integer := xlSigned; b_width: integer := 4; b_bin_pt: integer := 1; b_arith: integer := xlSigned; p_width: integer := 8; p_bin_pt: integer := 2; p_arith: integer := xlSigned; rst_width: integer := 1; rst_bin_pt: integer := 0; rst_arith: integer := xlUnsigned; en_width: integer := 1; en_bin_pt: integer := 0; en_arith: integer := xlUnsigned; quantization: integer := xlTruncate; overflow: integer := xlWrap; extra_registers: integer := 0; c_a_width: integer := 7; c_b_width: integer := 7; c_type: integer := 0; c_a_type: integer := 0; c_b_type: integer := 0; c_pipelined: integer := 1; c_baat: integer := 4; multsign: integer := xlSigned; c_output_width: integer := 16 ); port ( a: in std_logic_vector(a_width - 1 downto 0); b: in std_logic_vector(b_width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; core_ce: in std_logic := '0'; core_clr: in std_logic := '0'; core_clk: in std_logic := '0'; rst: in std_logic_vector(rst_width - 1 downto 0); en: in std_logic_vector(en_width - 1 downto 0); p: out std_logic_vector(p_width - 1 downto 0) ); end xlmult; architecture behavior of xlmult is component synth_reg generic ( width: integer := 16; latency: integer := 5 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; component mult_11_2_fe92ad55b7635191 port ( b: in std_logic_vector(c_b_width - 1 downto 0); p: out std_logic_vector(c_output_width - 1 downto 0); clk: in std_logic; ce: in std_logic; sclr: in std_logic; a: in std_logic_vector(c_a_width - 1 downto 0) ); end component; attribute syn_black_box of mult_11_2_fe92ad55b7635191: component is true; attribute fpga_dont_touch of mult_11_2_fe92ad55b7635191: component is "true"; attribute box_type of mult_11_2_fe92ad55b7635191: component is "black_box"; signal tmp_a: std_logic_vector(c_a_width - 1 downto 0); signal conv_a: std_logic_vector(c_a_width - 1 downto 0); signal tmp_b: std_logic_vector(c_b_width - 1 downto 0); signal conv_b: std_logic_vector(c_b_width - 1 downto 0); signal tmp_p: std_logic_vector(c_output_width - 1 downto 0); signal conv_p: std_logic_vector(p_width - 1 downto 0); -- synopsys translate_off signal real_a, real_b, real_p: real; -- synopsys translate_on signal rfd: std_logic; signal rdy: std_logic; signal nd: std_logic; signal internal_ce: std_logic; signal internal_clr: std_logic; signal internal_core_ce: std_logic; begin -- synopsys translate_off -- synopsys translate_on internal_ce <= ce and en(0); internal_core_ce <= core_ce and en(0); internal_clr <= (clr or rst(0)) and ce; nd <= internal_ce; input_process: process (a,b) begin tmp_a <= zero_ext(a, c_a_width); tmp_b <= zero_ext(b, c_b_width); end process; output_process: process (tmp_p) begin conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign, p_width, p_bin_pt, p_arith, quantization, overflow); end process; comp0: if ((core_name0 = "mult_11_2_fe92ad55b7635191")) generate core_instance0: mult_11_2_fe92ad55b7635191 port map ( a => tmp_a, clk => clk, ce => internal_ce, sclr => internal_clr, p => tmp_p, b => tmp_b ); end generate; latency_gt_0: if (extra_registers > 0) generate reg: synth_reg generic map ( width => p_width, latency => extra_registers ) port map ( i => conv_p, ce => internal_ce, clr => internal_clr, clk => clk, o => p ); end generate; latency_eq_0: if (extra_registers = 0) generate p <= conv_p; end generate; end architecture behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_6293007044 is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_6293007044; architecture behavior of constant_6293007044 is begin op <= "1"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_23f848c85b is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_23f848c85b; architecture behavior of delay_23f848c85b is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000000", "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(1); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 1 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_9565135955 is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_9565135955; architecture behavior of delay_9565135955 is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (3 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000000", "00000000", "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(2); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 2 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_fb08f2e938 is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_fb08f2e938; architecture behavior of delay_fb08f2e938 is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (4 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000000", "00000000", "00000000", "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(3); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 3 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_ebec135d8a is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_ebec135d8a; architecture behavior of delay_ebec135d8a is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlspram is generic ( core_name0: string := ""; c_width: integer := 12; c_address_width: integer := 4; latency: integer := 1 ); port ( data_in: in std_logic_vector(c_width - 1 downto 0); addr: in std_logic_vector(c_address_width - 1 downto 0); we: in std_logic_vector(0 downto 0); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0); ce: in std_logic; clk: in std_logic; data_out: out std_logic_vector(c_width - 1 downto 0) ); end xlspram ; architecture behavior of xlspram is component synth_reg generic ( width: integer; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal core_data_out, dly_data_out: std_logic_vector(c_width - 1 downto 0); signal core_we, core_ce, sinit: std_logic; component bmg_62_54b11b852dca329b port ( addra: in std_logic_vector(c_address_width - 1 downto 0); clka: in std_logic; dina: in std_logic_vector(c_width - 1 downto 0); wea: in std_logic_vector(0 downto 0); ena: in std_logic; douta: out std_logic_vector(c_width - 1 downto 0) ); end component; attribute syn_black_box of bmg_62_54b11b852dca329b: component is true; attribute fpga_dont_touch of bmg_62_54b11b852dca329b: component is "true"; attribute box_type of bmg_62_54b11b852dca329b: component is "black_box"; component bmg_62_05852d43925e39b8 port ( addra: in std_logic_vector(c_address_width - 1 downto 0); clka: in std_logic; dina: in std_logic_vector(c_width - 1 downto 0); wea: in std_logic_vector(0 downto 0); ena: in std_logic; douta: out std_logic_vector(c_width - 1 downto 0) ); end component; attribute syn_black_box of bmg_62_05852d43925e39b8: component is true; attribute fpga_dont_touch of bmg_62_05852d43925e39b8: component is "true"; attribute box_type of bmg_62_05852d43925e39b8: component is "black_box"; begin data_out <= dly_data_out; core_we <= we(0); core_ce <= ce and en(0); sinit <= rst(0) and ce; comp0: if ((core_name0 = "bmg_62_54b11b852dca329b")) generate core_instance0: bmg_62_54b11b852dca329b port map ( addra => addr, clka => clk, dina => data_in, wea(0) => core_we, ena => core_ce, douta => core_data_out ); end generate; comp1: if ((core_name0 = "bmg_62_05852d43925e39b8")) generate core_instance1: bmg_62_05852d43925e39b8 port map ( addra => addr, clka => clk, dina => data_in, wea(0) => core_we, ena => core_ce, douta => core_data_out ); end generate; latency_test: if (latency > 1) generate reg: synth_reg generic map ( width => c_width, latency => latency - 1 ) port map ( i => core_data_out, ce => core_ce, clr => '0', clk => clk, o => dly_data_out ); end generate; latency_1: if (latency <= 1) generate dly_data_out <= core_data_out; end generate; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_38f665f8aa is port ( d : in std_logic_vector((5 - 1) downto 0); q : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_38f665f8aa; architecture behavior of delay_38f665f8aa is signal d_1_22: std_logic_vector((5 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((5 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000", "00000"); signal op_mem_20_24_front_din: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(1); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 1 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_2b3acb49f4 is port ( in0 : in std_logic_vector((1 - 1) downto 0); in1 : in std_logic_vector((1 - 1) downto 0); in2 : in std_logic_vector((1 - 1) downto 0); in3 : in std_logic_vector((1 - 1) downto 0); in4 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_2b3acb49f4; architecture behavior of concat_2b3acb49f4 is signal in0_1_23: unsigned((1 - 1) downto 0); signal in1_1_27: unsigned((1 - 1) downto 0); signal in2_1_31: unsigned((1 - 1) downto 0); signal in3_1_35: unsigned((1 - 1) downto 0); signal in4_1_39: unsigned((1 - 1) downto 0); signal y_2_1_concat: unsigned((5 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); in2_1_31 <= std_logic_vector_to_unsigned(in2); in3_1_35 <= std_logic_vector_to_unsigned(in3); in4_1_39 <= std_logic_vector_to_unsigned(in4); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_4714bdf2a7 is port ( d : in std_logic_vector((5 - 1) downto 0); q : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_4714bdf2a7; architecture behavior of delay_4714bdf2a7 is signal d_1_22: std_logic_vector((5 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (26 - 1)) of std_logic_vector((5 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000"); signal op_mem_20_24_front_din: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(25); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 25 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_fdce3802d7 is port ( op : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_fdce3802d7; architecture behavior of constant_fdce3802d7 is begin op <= "11001"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_963ed6358a is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_963ed6358a; architecture behavior of constant_963ed6358a is begin op <= "0"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_7244cd602b is port ( op : out std_logic_vector((7 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_7244cd602b; architecture behavior of constant_7244cd602b is begin op <= "0000000"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_1e33fcde03 is port ( a : in std_logic_vector((1 - 1) downto 0); b : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_1e33fcde03; architecture behavior of expr_1e33fcde03 is signal a_1_24: unsigned((1 - 1) downto 0); signal b_1_27: unsigned((1 - 1) downto 0); signal bitnot_5_35: unsigned((1 - 1) downto 0); signal fulldout_5_2_bit: unsigned((1 - 1) downto 0); begin a_1_24 <= std_logic_vector_to_unsigned(a); b_1_27 <= std_logic_vector_to_unsigned(b); bitnot_5_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(a_1_24)); fulldout_5_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(b_1_27) and unsigned_to_std_logic_vector(bitnot_5_35)); dout <= unsigned_to_std_logic_vector(fulldout_5_2_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity inverter_e2b989a05e is port ( ip : in std_logic_vector((1 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end inverter_e2b989a05e; architecture behavior of inverter_e2b989a05e is signal ip_1_26: unsigned((1 - 1) downto 0); type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0); signal op_mem_22_20: array_type_op_mem_22_20 := ( 0 => "0"); signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0); signal op_mem_22_20_back: unsigned((1 - 1) downto 0); signal op_mem_22_20_push_front_pop_back_en: std_logic; signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0); begin ip_1_26 <= std_logic_vector_to_unsigned(ip); op_mem_22_20_back <= op_mem_22_20(0); proc_op_mem_22_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then op_mem_22_20(0) <= op_mem_22_20_front_din; end if; end if; end process proc_op_mem_22_20; internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26)); op_mem_22_20_push_front_pop_back_en <= '0'; op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_dc5bc996c9 is port ( a : in std_logic_vector((5 - 1) downto 0); b : in std_logic_vector((5 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_dc5bc996c9; architecture behavior of relational_dc5bc996c9 is signal a_1_31: unsigned((5 - 1) downto 0); signal b_1_34: unsigned((5 - 1) downto 0); signal result_14_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); result_14_3_rel <= a_1_31 /= b_1_34; op <= boolean_to_vector(result_14_3_rel); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity addsub_ba7fff8397 is port ( a : in std_logic_vector((13 - 1) downto 0); b : in std_logic_vector((12 - 1) downto 0); s : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end addsub_ba7fff8397; architecture behavior of addsub_ba7fff8397 is signal a_17_32: signed((13 - 1) downto 0); signal b_17_35: unsigned((12 - 1) downto 0); type array_type_op_mem_91_20 is array (0 to (1 - 1)) of unsigned((12 - 1) downto 0); signal op_mem_91_20: array_type_op_mem_91_20 := ( 0 => "000000000000"); signal op_mem_91_20_front_din: unsigned((12 - 1) downto 0); signal op_mem_91_20_back: unsigned((12 - 1) downto 0); signal op_mem_91_20_push_front_pop_back_en: std_logic; type array_type_cout_mem_92_22 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0); signal cout_mem_92_22: array_type_cout_mem_92_22 := ( 0 => "0"); signal cout_mem_92_22_front_din: unsigned((1 - 1) downto 0); signal cout_mem_92_22_back: unsigned((1 - 1) downto 0); signal cout_mem_92_22_push_front_pop_back_en: std_logic; signal prev_mode_93_22_next: unsigned((3 - 1) downto 0); signal prev_mode_93_22: unsigned((3 - 1) downto 0); signal prev_mode_93_22_reg_i: std_logic_vector((3 - 1) downto 0); signal prev_mode_93_22_reg_o: std_logic_vector((3 - 1) downto 0); signal cast_69_18: signed((14 - 1) downto 0); signal cast_69_22: signed((14 - 1) downto 0); signal internal_s_69_5_addsub: signed((14 - 1) downto 0); signal cast_internal_s_83_3_convert: unsigned((12 - 1) downto 0); begin a_17_32 <= std_logic_vector_to_signed(a); b_17_35 <= std_logic_vector_to_unsigned(b); op_mem_91_20_back <= op_mem_91_20(0); proc_op_mem_91_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_91_20_push_front_pop_back_en = '1')) then op_mem_91_20(0) <= op_mem_91_20_front_din; end if; end if; end process proc_op_mem_91_20; cout_mem_92_22_back <= cout_mem_92_22(0); proc_cout_mem_92_22: process (clk) is variable i_x_000000: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (cout_mem_92_22_push_front_pop_back_en = '1')) then cout_mem_92_22(0) <= cout_mem_92_22_front_din; end if; end if; end process proc_cout_mem_92_22; prev_mode_93_22_reg_i <= unsigned_to_std_logic_vector(prev_mode_93_22_next); prev_mode_93_22 <= std_logic_vector_to_unsigned(prev_mode_93_22_reg_o); prev_mode_93_22_reg_inst: entity work.synth_reg_w_init generic map ( init_index => 2, init_value => b"010", latency => 1, width => 3) port map ( ce => ce, clk => clk, clr => clr, i => prev_mode_93_22_reg_i, o => prev_mode_93_22_reg_o); cast_69_18 <= s2s_cast(a_17_32, 0, 14, 0); cast_69_22 <= u2s_cast(b_17_35, 0, 14, 0); internal_s_69_5_addsub <= cast_69_18 + cast_69_22; cast_internal_s_83_3_convert <= s2u_cast(internal_s_69_5_addsub, 0, 12, 0); op_mem_91_20_push_front_pop_back_en <= '0'; cout_mem_92_22_push_front_pop_back_en <= '0'; prev_mode_93_22_next <= std_logic_vector_to_unsigned("000"); s <= unsigned_to_std_logic_vector(cast_internal_s_83_3_convert); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_9b805894ff is port ( op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_9b805894ff; architecture behavior of constant_9b805894ff is begin op <= "111111111111"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_7c91b1b314 is port ( op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_7c91b1b314; architecture behavior of constant_7c91b1b314 is begin op <= "000000000001"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_be6eece885 is port ( op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_be6eece885; architecture behavior of constant_be6eece885 is begin op <= "111111111101"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_f50101e101 is port ( reset : in std_logic_vector((1 - 1) downto 0); tc : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_f50101e101; architecture behavior of expr_f50101e101 is signal reset_1_24: boolean; signal tc_1_31: boolean; signal bit_5_25: boolean; signal fulldout_5_2_bitnot: boolean; begin reset_1_24 <= ((reset) = "1"); tc_1_31 <= ((tc) = "1"); bit_5_25 <= ((boolean_to_vector(reset_1_24) or boolean_to_vector(tc_1_31)) = "1"); fulldout_5_2_bitnot <= ((not boolean_to_vector(bit_5_25)) = "1"); dout <= boolean_to_vector(fulldout_5_2_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mux_b53670f063 is port ( sel : in std_logic_vector((1 - 1) downto 0); d0 : in std_logic_vector((12 - 1) downto 0); d1 : in std_logic_vector((13 - 1) downto 0); y : out std_logic_vector((13 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mux_b53670f063; architecture behavior of mux_b53670f063 is signal sel_1_20: std_logic; signal d0_1_24: std_logic_vector((12 - 1) downto 0); signal d1_1_27: std_logic_vector((13 - 1) downto 0); signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0); signal unregy_join_6_1: std_logic_vector((13 - 1) downto 0); begin sel_1_20 <= sel(0); d0_1_24 <= d0; d1_1_27 <= d1; sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned); proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert) is begin case sel_internal_2_1_convert is when "0" => unregy_join_6_1 <= cast(d0_1_24, 0, 13, 0, xlSigned); when others => unregy_join_6_1 <= d1_1_27; end case; end process proc_switch_6_1; y <= unregy_join_6_1; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_d36fe12c1c is port ( a : in std_logic_vector((12 - 1) downto 0); b : in std_logic_vector((12 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_d36fe12c1c; architecture behavior of relational_d36fe12c1c is signal a_1_31: unsigned((12 - 1) downto 0); signal b_1_34: unsigned((12 - 1) downto 0); signal result_12_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); result_12_3_rel <= a_1_31 = b_1_34; op <= boolean_to_vector(result_12_3_rel); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_9f02caa990 is port ( d : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_9f02caa990; architecture behavior of delay_9f02caa990 is signal d_1_22: std_logic; type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic; signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => '0'); signal op_mem_20_24_front_din: std_logic; signal op_mem_20_24_back: std_logic; signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d(0); op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= std_logic_to_vector(op_mem_20_24_back); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_5753e4c658 is port ( d : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_5753e4c658; architecture behavior of delay_5753e4c658 is signal d_1_22: std_logic_vector((1 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "0"); signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_305312c97b is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); rst : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_305312c97b; architecture behavior of expr_305312c97b is signal d0_1_24: unsigned((1 - 1) downto 0); signal d1_1_28: unsigned((1 - 1) downto 0); signal rst_1_32: unsigned((1 - 1) downto 0); signal bitnot_6_54: unsigned((1 - 1) downto 0); signal bit_6_37: unsigned((1 - 1) downto 0); signal fulldout_6_2_bit: unsigned((1 - 1) downto 0); begin d0_1_24 <= std_logic_vector_to_unsigned(d0); d1_1_28 <= std_logic_vector_to_unsigned(d1); rst_1_32 <= std_logic_vector_to_unsigned(rst); bitnot_6_54 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(d0_1_24)); bit_6_37 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(d1_1_28) and unsigned_to_std_logic_vector(bitnot_6_54)); fulldout_6_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rst_1_32) or unsigned_to_std_logic_vector(bit_6_37)); dout <= unsigned_to_std_logic_vector(fulldout_6_2_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_f4d0462e0e is port ( plbrst : in std_logic_vector((1 - 1) downto 0); plbabus : in std_logic_vector((32 - 1) downto 0); plbpavalid : in std_logic_vector((1 - 1) downto 0); plbrnw : in std_logic_vector((1 - 1) downto 0); plbwrdbus : in std_logic_vector((32 - 1) downto 0); rddata : in std_logic_vector((32 - 1) downto 0); addrpref : in std_logic_vector((20 - 1) downto 0); wrdbusreg : out std_logic_vector((32 - 1) downto 0); addrack : out std_logic_vector((1 - 1) downto 0); rdcomp : out std_logic_vector((1 - 1) downto 0); wrdack : out std_logic_vector((1 - 1) downto 0); bankaddr : out std_logic_vector((2 - 1) downto 0); rnwreg : out std_logic_vector((1 - 1) downto 0); rddack : out std_logic_vector((1 - 1) downto 0); rddbus : out std_logic_vector((32 - 1) downto 0); linearaddr : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_f4d0462e0e; architecture behavior of mcode_block_f4d0462e0e is signal plbrst_1_110: unsigned((1 - 1) downto 0); signal plbabus_1_118: unsigned((32 - 1) downto 0); signal plbpavalid_1_127: unsigned((1 - 1) downto 0); signal plbrnw_1_139: unsigned((1 - 1) downto 0); signal plbwrdbus_1_147: unsigned((32 - 1) downto 0); signal rddata_1_158: unsigned((32 - 1) downto 0); signal addrpref_1_166: unsigned((20 - 1) downto 0); signal plbrstreg_12_24_next: boolean; signal plbrstreg_12_24: boolean := false; signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0); signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal plbpavalidreg_14_28_next: boolean; signal plbpavalidreg_14_28: boolean := false; signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0); signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0"; signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0); signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal avalidreg_28_23_next: boolean; signal avalidreg_28_23: boolean := false; signal ps1reg_39_20_next: boolean; signal ps1reg_39_20: boolean := false; signal psreg_47_19_next: boolean; signal psreg_47_19: boolean := false; type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0); signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := ( "0", "0", "0"); signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_push_front_pop_back_en: std_logic; signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0); signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0"; signal rddackreg_66_23_next: unsigned((1 - 1) downto 0); signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0"; signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0); signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0"; signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0); signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0); signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0); signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0); signal rel_33_4: boolean; signal ps1_join_33_1: boolean; signal ps_42_1_bit: boolean; signal bitnot_49_49: boolean; signal bitnot_49_73: boolean; signal bit_49_49: boolean; signal addrack_49_1_convert: unsigned((1 - 1) downto 0); signal bit_55_43: unsigned((1 - 1) downto 0); signal bitnot_72_35: unsigned((1 - 1) downto 0); signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0); signal rdsel_76_1_bit: unsigned((1 - 1) downto 0); signal rel_78_4: boolean; signal rddbus1_join_78_1: unsigned((32 - 1) downto 0); signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0); signal plbrstreg_12_24_next_x_000000: boolean; signal plbpavalidreg_14_28_next_x_000000: boolean; begin plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst); plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus); plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid); plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw); plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus); rddata_1_158 <= std_logic_vector_to_unsigned(rddata); addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref); proc_plbrstreg_12_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrstreg_12_24 <= plbrstreg_12_24_next; end if; end if; end process proc_plbrstreg_12_24; proc_plbabusreg_13_25: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbabusreg_13_25 <= plbabusreg_13_25_next; end if; end if; end process proc_plbabusreg_13_25; proc_plbpavalidreg_14_28: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbpavalidreg_14_28 <= plbpavalidreg_14_28_next; end if; end if; end process proc_plbpavalidreg_14_28; proc_plbrnwreg_15_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrnwreg_15_24 <= plbrnwreg_15_24_next; end if; end if; end process proc_plbrnwreg_15_24; proc_plbwrdbusreg_16_27: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next; end if; end if; end process proc_plbwrdbusreg_16_27; proc_avalidreg_28_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then avalidreg_28_23 <= avalidreg_28_23_next; end if; end if; end process proc_avalidreg_28_23; proc_ps1reg_39_20: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then ps1reg_39_20 <= ps1reg_39_20_next; end if; end if; end process proc_ps1reg_39_20; proc_psreg_47_19: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then psreg_47_19 <= psreg_47_19_next; end if; end if; end process proc_psreg_47_19; rdcompdelay_58_25_back <= rdcompdelay_58_25(2); proc_rdcompdelay_58_25: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then for i in 2 downto 1 loop rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1); end loop; rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din; end if; end if; end process proc_rdcompdelay_58_25; proc_rdcompreg_62_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rdcompreg_62_23 <= rdcompreg_62_23_next; end if; end if; end process proc_rdcompreg_62_23; proc_rddackreg_66_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddackreg_66_23 <= rddackreg_66_23_next; end if; end if; end process proc_rddackreg_66_23; proc_wrdackreg_70_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then wrdackreg_70_23 <= wrdackreg_70_23_next; end if; end if; end process proc_wrdackreg_70_23; proc_rddbusreg_84_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddbusreg_84_23 <= rddbusreg_84_23_next; end if; end if; end process proc_rddbusreg_84_23; bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10); linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2); addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12); rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166; proc_if_33_1: process (rel_33_4) is begin if rel_33_4 then ps1_join_33_1 <= true; else ps1_join_33_1 <= false; end if; end process proc_if_33_1; ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1"); bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1"); bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1"); bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1"); addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0); bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24)); bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24)); wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35)); rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23)); rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1"); proc_if_78_1: process (rddata_1_158, rel_78_4) is begin if rel_78_4 then rddbus1_join_78_1 <= rddata_1_158; else rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); end if; end process proc_if_78_1; plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0); plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0"); plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000; plbabusreg_13_25_next <= plbabus_1_118; plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0"); plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000; plbrnwreg_15_24_next <= plbrnw_1_139; plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice; avalidreg_28_23_next <= plbpavalidreg_14_28; ps1reg_39_20_next <= ps1_join_33_1; psreg_47_19_next <= ps_42_1_bit; rdcompdelay_58_25_front_din <= bit_55_43; rdcompdelay_58_25_push_front_pop_back_en <= '1'; rdcompreg_62_23_next <= rdcompdelay_58_25_back; rddackreg_66_23_next <= rdcompreg_62_23; wrdackreg_70_23_next <= wrdackreg_72_1_bit; rddbusreg_84_23_next <= rddbus1_join_78_1; wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27); addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert); rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23); wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23); bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice); rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24); rddack <= unsigned_to_std_logic_vector(rddackreg_66_23); rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23); linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_6fff803424 is port ( wrdbus : in std_logic_vector((32 - 1) downto 0); bankaddr : in std_logic_vector((2 - 1) downto 0); linearaddr : in std_logic_vector((8 - 1) downto 0); rnwreg : in std_logic_vector((1 - 1) downto 0); addrack : in std_logic_vector((1 - 1) downto 0); sm_coef_update : in std_logic_vector((1 - 1) downto 0); sm_coef_gain : in std_logic_vector((20 - 1) downto 0); sm_coef_buffer : in std_logic_vector((7 - 1) downto 0); read_bank_out : out std_logic_vector((32 - 1) downto 0); sm_coef_update_din : out std_logic_vector((1 - 1) downto 0); sm_coef_update_en : out std_logic_vector((1 - 1) downto 0); sm_coef_gain_din : out std_logic_vector((20 - 1) downto 0); sm_coef_gain_en : out std_logic_vector((1 - 1) downto 0); sm_coef_buffer_addr : out std_logic_vector((5 - 1) downto 0); sm_coef_buffer_din : out std_logic_vector((7 - 1) downto 0); sm_coef_buffer_we : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_6fff803424; architecture behavior of mcode_block_6fff803424 is signal wrdbus_1_173: unsigned((32 - 1) downto 0); signal bankaddr_1_181: unsigned((2 - 1) downto 0); signal linearaddr_1_191: unsigned((8 - 1) downto 0); signal rnwreg_1_203: unsigned((1 - 1) downto 0); signal addrack_1_211: unsigned((1 - 1) downto 0); signal sm_coef_update_1_220: unsigned((1 - 1) downto 0); signal sm_coef_gain_1_236: unsigned((20 - 1) downto 0); signal sm_coef_buffer_1_250: signed((7 - 1) downto 0); signal reg_bank_out_reg_25_30_next: unsigned((32 - 1) downto 0); signal reg_bank_out_reg_25_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal ram_bank_out_reg_49_30_next: unsigned((32 - 1) downto 0); signal ram_bank_out_reg_49_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal sm_coef_buffer_we_reg_62_35_next: boolean; signal sm_coef_buffer_we_reg_62_35: boolean := false; signal sm_coef_buffer_addr_reg_74_1_next: unsigned((5 - 1) downto 0); signal sm_coef_buffer_addr_reg_74_1: unsigned((5 - 1) downto 0) := "00000"; signal read_bank_out_reg_112_31_next: unsigned((32 - 1) downto 0); signal read_bank_out_reg_112_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_reg_115_26_next: unsigned((2 - 1) downto 0); signal bankaddr_reg_115_26: unsigned((2 - 1) downto 0) := "00"; signal sm_coef_buffer_bus_19_1_force: unsigned((7 - 1) downto 0); signal rel_28_4: boolean; signal rel_30_8: boolean; signal reg_bank_out_reg_join_28_1: unsigned((32 - 1) downto 0); signal opcode_42_1_concat: unsigned((12 - 1) downto 0); signal slice_56_39: unsigned((7 - 1) downto 0); signal sm_coef_buffer_din_56_1_force: signed((7 - 1) downto 0); signal opcode_sm_coef_buffer_64_1_concat: unsigned((4 - 1) downto 0); signal rel_65_4: boolean; signal sm_coef_buffer_we_reg_join_65_1: boolean; signal rel_83_4: boolean; signal sm_coef_update_en_join_83_1: boolean; signal rel_89_4: boolean; signal sm_coef_gain_en_join_89_1: boolean; signal slice_104_39: unsigned((1 - 1) downto 0); signal slice_107_37: unsigned((20 - 1) downto 0); signal rel_117_4: boolean; signal rel_120_8: boolean; signal rel_123_8: boolean; signal rel_126_8: boolean; signal read_bank_out_reg_join_117_1: unsigned((32 - 1) downto 0); signal cast_ram_bank_out_reg_49_30_next: unsigned((32 - 1) downto 0); signal cast_sm_coef_buffer_addr_reg_74_1_next: unsigned((5 - 1) downto 0); begin wrdbus_1_173 <= std_logic_vector_to_unsigned(wrdbus); bankaddr_1_181 <= std_logic_vector_to_unsigned(bankaddr); linearaddr_1_191 <= std_logic_vector_to_unsigned(linearaddr); rnwreg_1_203 <= std_logic_vector_to_unsigned(rnwreg); addrack_1_211 <= std_logic_vector_to_unsigned(addrack); sm_coef_update_1_220 <= std_logic_vector_to_unsigned(sm_coef_update); sm_coef_gain_1_236 <= std_logic_vector_to_unsigned(sm_coef_gain); sm_coef_buffer_1_250 <= std_logic_vector_to_signed(sm_coef_buffer); proc_reg_bank_out_reg_25_30: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then reg_bank_out_reg_25_30 <= reg_bank_out_reg_25_30_next; end if; end if; end process proc_reg_bank_out_reg_25_30; proc_ram_bank_out_reg_49_30: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then ram_bank_out_reg_49_30 <= ram_bank_out_reg_49_30_next; end if; end if; end process proc_ram_bank_out_reg_49_30; proc_sm_coef_buffer_we_reg_62_35: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then sm_coef_buffer_we_reg_62_35 <= sm_coef_buffer_we_reg_62_35_next; end if; end if; end process proc_sm_coef_buffer_we_reg_62_35; proc_sm_coef_buffer_addr_reg_74_1: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then sm_coef_buffer_addr_reg_74_1 <= sm_coef_buffer_addr_reg_74_1_next; end if; end if; end process proc_sm_coef_buffer_addr_reg_74_1; proc_read_bank_out_reg_112_31: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then read_bank_out_reg_112_31 <= read_bank_out_reg_112_31_next; end if; end if; end process proc_read_bank_out_reg_112_31; proc_bankaddr_reg_115_26: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then bankaddr_reg_115_26 <= bankaddr_reg_115_26_next; end if; end if; end process proc_bankaddr_reg_115_26; sm_coef_buffer_bus_19_1_force <= signed_to_unsigned(sm_coef_buffer_1_250); rel_28_4 <= linearaddr_1_191 = std_logic_vector_to_unsigned("00000000"); rel_30_8 <= linearaddr_1_191 = std_logic_vector_to_unsigned("00000001"); proc_if_28_1: process (reg_bank_out_reg_25_30, rel_28_4, rel_30_8, sm_coef_gain_1_236, sm_coef_update_1_220) is begin if rel_28_4 then reg_bank_out_reg_join_28_1 <= u2u_cast(sm_coef_update_1_220, 0, 32, 0); elsif rel_30_8 then reg_bank_out_reg_join_28_1 <= u2u_cast(sm_coef_gain_1_236, 0, 32, 0); else reg_bank_out_reg_join_28_1 <= reg_bank_out_reg_25_30; end if; end process proc_if_28_1; opcode_42_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_211) & unsigned_to_std_logic_vector(rnwreg_1_203) & unsigned_to_std_logic_vector(bankaddr_1_181) & unsigned_to_std_logic_vector(linearaddr_1_191)); slice_56_39 <= u2u_slice(wrdbus_1_173, 6, 0); sm_coef_buffer_din_56_1_force <= unsigned_to_signed(slice_56_39); opcode_sm_coef_buffer_64_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_211) & unsigned_to_std_logic_vector(rnwreg_1_203) & unsigned_to_std_logic_vector(bankaddr_1_181)); rel_65_4 <= opcode_sm_coef_buffer_64_1_concat = std_logic_vector_to_unsigned("1000"); proc_if_65_1: process (rel_65_4) is begin if rel_65_4 then sm_coef_buffer_we_reg_join_65_1 <= true; else sm_coef_buffer_we_reg_join_65_1 <= false; end if; end process proc_if_65_1; rel_83_4 <= opcode_42_1_concat = std_logic_vector_to_unsigned("101000000000"); proc_if_83_1: process (rel_83_4) is begin if rel_83_4 then sm_coef_update_en_join_83_1 <= true; else sm_coef_update_en_join_83_1 <= false; end if; end process proc_if_83_1; rel_89_4 <= opcode_42_1_concat = std_logic_vector_to_unsigned("101000000001"); proc_if_89_1: process (rel_89_4) is begin if rel_89_4 then sm_coef_gain_en_join_89_1 <= true; else sm_coef_gain_en_join_89_1 <= false; end if; end process proc_if_89_1; slice_104_39 <= u2u_slice(wrdbus_1_173, 0, 0); slice_107_37 <= u2u_slice(wrdbus_1_173, 19, 0); rel_117_4 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("00"); rel_120_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("01"); rel_123_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("10"); rel_126_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("11"); proc_if_117_1: process (ram_bank_out_reg_49_30, read_bank_out_reg_112_31, reg_bank_out_reg_25_30, rel_117_4, rel_120_8, rel_123_8, rel_126_8) is begin if rel_117_4 then read_bank_out_reg_join_117_1 <= ram_bank_out_reg_49_30; elsif rel_120_8 then read_bank_out_reg_join_117_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_123_8 then read_bank_out_reg_join_117_1 <= reg_bank_out_reg_25_30; elsif rel_126_8 then read_bank_out_reg_join_117_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); else read_bank_out_reg_join_117_1 <= read_bank_out_reg_112_31; end if; end process proc_if_117_1; reg_bank_out_reg_25_30_next <= reg_bank_out_reg_join_28_1; cast_ram_bank_out_reg_49_30_next <= u2u_cast(sm_coef_buffer_bus_19_1_force, 0, 32, 0); ram_bank_out_reg_49_30_next <= cast_ram_bank_out_reg_49_30_next; sm_coef_buffer_we_reg_62_35_next <= sm_coef_buffer_we_reg_join_65_1; cast_sm_coef_buffer_addr_reg_74_1_next <= u2u_cast(linearaddr_1_191, 0, 5, 0); sm_coef_buffer_addr_reg_74_1_next <= cast_sm_coef_buffer_addr_reg_74_1_next; read_bank_out_reg_112_31_next <= read_bank_out_reg_join_117_1; bankaddr_reg_115_26_next <= bankaddr_1_181; read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_112_31); sm_coef_update_din <= unsigned_to_std_logic_vector(slice_104_39); sm_coef_update_en <= boolean_to_vector(sm_coef_update_en_join_83_1); sm_coef_gain_din <= unsigned_to_std_logic_vector(slice_107_37); sm_coef_gain_en <= boolean_to_vector(sm_coef_gain_en_join_89_1); sm_coef_buffer_addr <= unsigned_to_std_logic_vector(sm_coef_buffer_addr_reg_74_1); sm_coef_buffer_din <= signed_to_std_logic_vector(sm_coef_buffer_din_56_1_force); sm_coef_buffer_we <= boolean_to_vector(sm_coef_buffer_we_reg_62_35); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_d0d1b9533e is port ( in0 : in std_logic_vector((8 - 1) downto 0); in1 : in std_logic_vector((8 - 1) downto 0); in2 : in std_logic_vector((8 - 1) downto 0); y : out std_logic_vector((24 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_d0d1b9533e; architecture behavior of concat_d0d1b9533e is signal in0_1_23: unsigned((8 - 1) downto 0); signal in1_1_27: unsigned((8 - 1) downto 0); signal in2_1_31: unsigned((8 - 1) downto 0); signal y_2_1_concat: unsigned((24 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); in2_1_31 <= std_logic_vector_to_unsigned(in2); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/ABS" entity abs_entity_9ef2dfe1e8 is port ( ce_1: in std_logic; clk_1: in std_logic; in1: in std_logic_vector(21 downto 0); out1: out std_logic_vector(22 downto 0) ); end abs_entity_9ef2dfe1e8; architecture structural of abs_entity_9ef2dfe1e8 is signal addsub15_s_net_x0: std_logic_vector(21 downto 0); signal ce_1_sg_x0: std_logic; signal clk_1_sg_x0: std_logic; signal mux_y_net_x0: std_logic_vector(22 downto 0); signal negate_op_net: std_logic_vector(22 downto 0); signal register1_q_net: std_logic_vector(21 downto 0); signal register2_q_net: std_logic; signal slice_y_net: std_logic; begin ce_1_sg_x0 <= ce_1; clk_1_sg_x0 <= clk_1; addsub15_s_net_x0 <= in1; out1 <= mux_y_net_x0; mux: entity work.mux_029cd20aa9 port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', d0 => register1_q_net, d1 => negate_op_net, sel(0) => register2_q_net, y => mux_y_net_x0 ); negate: entity work.negate_142bd36a06 port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', ip => addsub15_s_net_x0, op => negate_op_net ); register1: entity work.xlregister generic map ( d_width => 22, init_value => b"0000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => addsub15_s_net_x0, en => "1", rst => "0", q => register1_q_net ); register2: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => slice_y_net, en => "1", rst => "0", q(0) => register2_q_net ); slice: entity work.xlslice generic map ( new_lsb => 21, new_msb => 21, x_width => 22, y_width => 1 ) port map ( x => addsub15_s_net_x0, y(0) => slice_y_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/load_sequencer" entity load_sequencer_entity_8724dffd75 is port ( ce_1: in std_logic; clk_1: in std_logic; load: in std_logic; load_1: out std_logic; load_2: out std_logic; load_3: out std_logic; load_4: out std_logic; load_5: out std_logic ); end load_sequencer_entity_8724dffd75; architecture structural of load_sequencer_entity_8724dffd75 is signal ce_1_sg_x1: std_logic; signal clk_1_sg_x1: std_logic; signal constant1_op_net: std_logic_vector(2 downto 0); signal constant2_op_net: std_logic_vector(2 downto 0); signal constant3_op_net: std_logic_vector(2 downto 0); signal constant4_op_net: std_logic_vector(2 downto 0); signal constant5_op_net: std_logic_vector(2 downto 0); signal constant7_op_net: std_logic_vector(2 downto 0); signal counter_op_net: std_logic_vector(2 downto 0); signal index_count_op_net: std_logic_vector(2 downto 0); signal logical1_y_net_x0: std_logic; signal logical2_y_net_x0: std_logic; signal logical3_y_net_x0: std_logic; signal logical4_y_net_x0: std_logic; signal logical5_y_net: std_logic; signal logical_y_net_x0: std_logic; signal relational1_op_net: std_logic; signal relational2_op_net: std_logic; signal relational3_op_net: std_logic; signal relational3_op_net_x1: std_logic; signal relational4_op_net: std_logic; signal relational5_op_net: std_logic; signal relational6_op_net: std_logic; signal relational_op_net: std_logic; begin ce_1_sg_x1 <= ce_1; clk_1_sg_x1 <= clk_1; relational3_op_net_x1 <= load; load_1 <= logical_y_net_x0; load_2 <= logical1_y_net_x0; load_3 <= logical2_y_net_x0; load_4 <= logical3_y_net_x0; load_5 <= logical4_y_net_x0; constant1: entity work.constant_822933f89b port map ( ce => '0', clk => '0', clr => '0', op => constant1_op_net ); constant2: entity work.constant_a1c496ea88 port map ( ce => '0', clk => '0', clr => '0', op => constant2_op_net ); constant3: entity work.constant_1f5cc32f1e port map ( ce => '0', clk => '0', clr => '0', op => constant3_op_net ); constant4: entity work.constant_0f59f02ba5 port map ( ce => '0', clk => '0', clr => '0', op => constant4_op_net ); constant5: entity work.constant_469094441c port map ( ce => '0', clk => '0', clr => '0', op => constant5_op_net ); constant7: entity work.constant_469094441c port map ( ce => '0', clk => '0', clr => '0', op => constant7_op_net ); counter: entity work.xlcounter_limit generic map ( cnt_15_0 => 4, cnt_31_16 => 0, cnt_47_32 => 0, cnt_63_48 => 0, core_name0 => "cntr_11_0_e859c6662c373192", count_limited => 1, op_arith => xlUnsigned, op_width => 3 ) port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', en(0) => relational3_op_net_x1, rst(0) => relational6_op_net, op => counter_op_net ); index_count: entity work.xlcounter_limit generic map ( cnt_15_0 => 4, cnt_31_16 => 0, cnt_47_32 => 0, cnt_63_48 => 0, core_name0 => "cntr_11_0_e859c6662c373192", count_limited => 1, op_arith => xlUnsigned, op_width => 3 ) port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', en(0) => relational6_op_net, rst(0) => logical5_y_net, op => index_count_op_net ); logical: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational1_op_net, d1(0) => relational3_op_net_x1, y(0) => logical_y_net_x0 ); logical1: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational2_op_net, d1(0) => relational3_op_net_x1, y(0) => logical1_y_net_x0 ); logical2: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational3_op_net, d1(0) => relational3_op_net_x1, y(0) => logical2_y_net_x0 ); logical3: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational4_op_net, d1(0) => relational3_op_net_x1, y(0) => logical3_y_net_x0 ); logical4: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational5_op_net, d1(0) => relational3_op_net_x1, y(0) => logical4_y_net_x0 ); logical5: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational_op_net, d1(0) => relational6_op_net, y(0) => logical5_y_net ); relational: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant7_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational_op_net ); relational1: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant1_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational1_op_net ); relational2: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant2_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational2_op_net ); relational3: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant3_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational3_op_net ); relational4: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant4_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational4_op_net ); relational5: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant5_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational5_op_net ); relational6: entity work.relational_8fc7f5539b port map ( a => counter_op_net, b => constant7_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational6_op_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/n-tap FIR Compiler Filter/Rising Edge Detector1" entity rising_edge_detector1_entity_0d24c36d60 is port ( ce_1: in std_logic; clk_1: in std_logic; din: in std_logic; dout: out std_logic ); end rising_edge_detector1_entity_0d24c36d60; architecture structural of rising_edge_detector1_entity_0d24c36d60 is signal ce_1_sg_x2: std_logic; signal clk_1_sg_x2: std_logic; signal inverter_op_net: std_logic; signal logical_y_net_x1: std_logic; signal logical_y_net_x2: std_logic; signal register1_q_net: std_logic; begin ce_1_sg_x2 <= ce_1; clk_1_sg_x2 <= clk_1; logical_y_net_x1 <= din; dout <= logical_y_net_x2; inverter: entity work.inverter_e5b38cca3b port map ( ce => ce_1_sg_x2, clk => clk_1_sg_x2, clr => '0', ip(0) => register1_q_net, op(0) => inverter_op_net ); logical: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => logical_y_net_x1, d1(0) => inverter_op_net, y(0) => logical_y_net_x2 ); register1: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x2, clk => clk_1_sg_x2, d(0) => logical_y_net_x1, en => "1", rst => "0", q(0) => register1_q_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/n-tap FIR Compiler Filter" entity n_tap_fir_compiler_filter_entity_7d40670988 is port ( ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; coef: in std_logic_vector(6 downto 0); din: in std_logic_vector(7 downto 0); load: in std_logic; out_x0: out std_logic_vector(18 downto 0) ); end n_tap_fir_compiler_filter_entity_7d40670988; architecture structural of n_tap_fir_compiler_filter_entity_7d40670988 is signal ce_1_sg_x3: std_logic; signal ce_logic_1_sg_x0: std_logic; signal clk_1_sg_x3: std_logic; signal fir_compiler_5_0_dout_net: std_logic_vector(18 downto 0); signal fir_compiler_5_0_rdy_net: std_logic; signal l1_x0: std_logic_vector(7 downto 0); signal logical_y_net_x2: std_logic; signal logical_y_net_x3: std_logic; signal register2_q_net: std_logic; signal register_q_net_x0: std_logic_vector(18 downto 0); signal shared_memory_data_out_net_x0: std_logic_vector(6 downto 0); begin ce_1_sg_x3 <= ce_1; ce_logic_1_sg_x0 <= ce_logic_1; clk_1_sg_x3 <= clk_1; shared_memory_data_out_net_x0 <= coef; l1_x0 <= din; logical_y_net_x3 <= load; out_x0 <= register_q_net_x0; fir_compiler_5_0: entity work.xlfir_compiler_d885873ecd26cf15cdb95a5d10c7a292 port map ( ce => ce_1_sg_x3, ce_logic_1 => ce_logic_1_sg_x0, clk => clk_1_sg_x3, clk_logic_1 => clk_1_sg_x3, coef_din => shared_memory_data_out_net_x0, coef_ld => logical_y_net_x2, coef_we => register2_q_net, din => l1_x0, src_ce => ce_1_sg_x3, src_clk => clk_1_sg_x3, dout => fir_compiler_5_0_dout_net, rdy => fir_compiler_5_0_rdy_net ); register2: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x3, clk => clk_1_sg_x3, d(0) => logical_y_net_x3, en => "1", rst => "0", q(0) => register2_q_net ); register_x0: entity work.xlregister generic map ( d_width => 19, init_value => b"0000000000000000000" ) port map ( ce => ce_1_sg_x3, clk => clk_1_sg_x3, d => fir_compiler_5_0_dout_net, en(0) => fir_compiler_5_0_rdy_net, rst => "0", q => register_q_net_x0 ); rising_edge_detector1_0d24c36d60: entity work.rising_edge_detector1_entity_0d24c36d60 port map ( ce_1 => ce_1_sg_x3, clk_1 => clk_1_sg_x3, din => logical_y_net_x3, dout => logical_y_net_x2 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/n-tap FIR Compiler Filter1" entity n_tap_fir_compiler_filter1_entity_b6187dc1dd is port ( ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; coef: in std_logic_vector(6 downto 0); din: in std_logic_vector(7 downto 0); load: in std_logic; out_x0: out std_logic_vector(18 downto 0) ); end n_tap_fir_compiler_filter1_entity_b6187dc1dd; architecture structural of n_tap_fir_compiler_filter1_entity_b6187dc1dd is signal ce_1_sg_x5: std_logic; signal ce_logic_1_sg_x1: std_logic; signal clk_1_sg_x5: std_logic; signal fir_compiler_5_0_dout_net: std_logic_vector(18 downto 0); signal fir_compiler_5_0_rdy_net: std_logic; signal l2_x0: std_logic_vector(7 downto 0); signal logical1_y_net_x2: std_logic; signal logical_y_net_x0: std_logic; signal register2_q_net: std_logic; signal register_q_net_x0: std_logic_vector(18 downto 0); signal shared_memory_data_out_net_x1: std_logic_vector(6 downto 0); begin ce_1_sg_x5 <= ce_1; ce_logic_1_sg_x1 <= ce_logic_1; clk_1_sg_x5 <= clk_1; shared_memory_data_out_net_x1 <= coef; l2_x0 <= din; logical1_y_net_x2 <= load; out_x0 <= register_q_net_x0; fir_compiler_5_0: entity work.xlfir_compiler_1e4b453df468e83a1cea0a55c8d9b90f port map ( ce => ce_1_sg_x5, ce_logic_1 => ce_logic_1_sg_x1, clk => clk_1_sg_x5, clk_logic_1 => clk_1_sg_x5, coef_din => shared_memory_data_out_net_x1, coef_ld => logical_y_net_x0, coef_we => register2_q_net, din => l2_x0, src_ce => ce_1_sg_x5, src_clk => clk_1_sg_x5, dout => fir_compiler_5_0_dout_net, rdy => fir_compiler_5_0_rdy_net ); register2: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x5, clk => clk_1_sg_x5, d(0) => logical1_y_net_x2, en => "1", rst => "0", q(0) => register2_q_net ); register_x0: entity work.xlregister generic map ( d_width => 19, init_value => b"0000000000000000000" ) port map ( ce => ce_1_sg_x5, clk => clk_1_sg_x5, d => fir_compiler_5_0_dout_net, en(0) => fir_compiler_5_0_rdy_net, rst => "0", q => register_q_net_x0 ); rising_edge_detector1_a171a70c77: entity work.rising_edge_detector1_entity_0d24c36d60 port map ( ce_1 => ce_1_sg_x5, clk_1 => clk_1_sg_x5, din => logical1_y_net_x2, dout => logical_y_net_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/n-tap FIR Compiler Filter2" entity n_tap_fir_compiler_filter2_entity_92eb71d873 is port ( ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; coef: in std_logic_vector(6 downto 0); din: in std_logic_vector(7 downto 0); load: in std_logic; out_x0: out std_logic_vector(18 downto 0) ); end n_tap_fir_compiler_filter2_entity_92eb71d873; architecture structural of n_tap_fir_compiler_filter2_entity_92eb71d873 is signal ce_1_sg_x7: std_logic; signal ce_logic_1_sg_x2: std_logic; signal clk_1_sg_x7: std_logic; signal fir_compiler_5_0_dout_net: std_logic_vector(18 downto 0); signal fir_compiler_5_0_rdy_net: std_logic; signal l3_x0: std_logic_vector(7 downto 0); signal logical2_y_net_x2: std_logic; signal logical_y_net_x0: std_logic; signal register2_q_net: std_logic; signal register_q_net_x0: std_logic_vector(18 downto 0); signal shared_memory_data_out_net_x2: std_logic_vector(6 downto 0); begin ce_1_sg_x7 <= ce_1; ce_logic_1_sg_x2 <= ce_logic_1; clk_1_sg_x7 <= clk_1; shared_memory_data_out_net_x2 <= coef; l3_x0 <= din; logical2_y_net_x2 <= load; out_x0 <= register_q_net_x0; fir_compiler_5_0: entity work.xlfir_compiler_5077ad6f33cdc3f379ad80845501c286 port map ( ce => ce_1_sg_x7, ce_logic_1 => ce_logic_1_sg_x2, clk => clk_1_sg_x7, clk_logic_1 => clk_1_sg_x7, coef_din => shared_memory_data_out_net_x2, coef_ld => logical_y_net_x0, coef_we => register2_q_net, din => l3_x0, src_ce => ce_1_sg_x7, src_clk => clk_1_sg_x7, dout => fir_compiler_5_0_dout_net, rdy => fir_compiler_5_0_rdy_net ); register2: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x7, clk => clk_1_sg_x7, d(0) => logical2_y_net_x2, en => "1", rst => "0", q(0) => register2_q_net ); register_x0: entity work.xlregister generic map ( d_width => 19, init_value => b"0000000000000000000" ) port map ( ce => ce_1_sg_x7, clk => clk_1_sg_x7, d => fir_compiler_5_0_dout_net, en(0) => fir_compiler_5_0_rdy_net, rst => "0", q => register_q_net_x0 ); rising_edge_detector1_858d3eaa96: entity work.rising_edge_detector1_entity_0d24c36d60 port map ( ce_1 => ce_1_sg_x7, clk_1 => clk_1_sg_x7, din => logical2_y_net_x2, dout => logical_y_net_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter" entity x5x5_filter_entity_e192f59c95 is port ( ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; coef: in std_logic_vector(6 downto 0); gain: in std_logic_vector(19 downto 0); line1: in std_logic_vector(7 downto 0); line2: in std_logic_vector(7 downto 0); line3: in std_logic_vector(7 downto 0); line4: in std_logic_vector(7 downto 0); line5: in std_logic_vector(7 downto 0); load: in std_logic; dout: out std_logic_vector(7 downto 0) ); end x5x5_filter_entity_e192f59c95; architecture structural of x5x5_filter_entity_e192f59c95 is signal addsub15_s_net_x0: std_logic_vector(21 downto 0); signal addsub2_s_net: std_logic_vector(19 downto 0); signal addsub3_s_net: std_logic_vector(19 downto 0); signal addsub4_s_net: std_logic_vector(20 downto 0); signal assert_dout_net: std_logic_vector(19 downto 0); signal ce_1_sg_x12: std_logic; signal ce_logic_1_sg_x5: std_logic; signal clk_1_sg_x12: std_logic; signal coef_gain_q_net: std_logic_vector(19 downto 0); signal convert1_dout_net_x0: std_logic_vector(7 downto 0); signal from_register_data_out_net_x0: std_logic_vector(19 downto 0); signal l1_x1: std_logic_vector(7 downto 0); signal l2_x1: std_logic_vector(7 downto 0); signal l3_x1: std_logic_vector(7 downto 0); signal l4_x1: std_logic_vector(7 downto 0); signal l5_x1: std_logic_vector(7 downto 0); signal logical1_y_net_x2: std_logic; signal logical2_y_net_x2: std_logic; signal logical3_y_net_x2: std_logic; signal logical4_y_net_x2: std_logic; signal logical_y_net_x3: std_logic; signal mult_p_net: std_logic_vector(42 downto 0); signal mux_y_net_x0: std_logic_vector(22 downto 0); signal register1_q_net: std_logic_vector(18 downto 0); signal register2_q_net: std_logic_vector(18 downto 0); signal register_q_net_x0: std_logic_vector(18 downto 0); signal register_q_net_x1: std_logic_vector(18 downto 0); signal register_q_net_x2: std_logic_vector(18 downto 0); signal register_q_net_x3: std_logic_vector(18 downto 0); signal register_q_net_x4: std_logic_vector(18 downto 0); signal relational3_op_net_x2: std_logic; signal shared_memory_data_out_net_x5: std_logic_vector(6 downto 0); begin ce_1_sg_x12 <= ce_1; ce_logic_1_sg_x5 <= ce_logic_1; clk_1_sg_x12 <= clk_1; shared_memory_data_out_net_x5 <= coef; from_register_data_out_net_x0 <= gain; l1_x1 <= line1; l2_x1 <= line2; l3_x1 <= line3; l4_x1 <= line4; l5_x1 <= line5; relational3_op_net_x2 <= load; dout <= convert1_dout_net_x0; abs_9ef2dfe1e8: entity work.abs_entity_9ef2dfe1e8 port map ( ce_1 => ce_1_sg_x12, clk_1 => clk_1_sg_x12, in1 => addsub15_s_net_x0, out1 => mux_y_net_x0 ); addsub15: entity work.xladdsub generic map ( a_arith => xlSigned, a_bin_pt => 0, a_width => 21, b_arith => xlSigned, b_bin_pt => 0, b_width => 19, c_has_c_out => 0, c_latency => 1, c_output_width => 22, core_name0 => "addsb_11_0_e7b4231f2ca96446", extra_registers => 0, full_s_arith => 2, full_s_width => 22, latency => 1, overflow => 1, quantization => 1, s_arith => xlSigned, s_bin_pt => 0, s_width => 22 ) port map ( a => addsub4_s_net, b => register2_q_net, ce => ce_1_sg_x12, clk => clk_1_sg_x12, clr => '0', en => "1", s => addsub15_s_net_x0 ); addsub2: entity work.xladdsub generic map ( a_arith => xlSigned, a_bin_pt => 0, a_width => 19, b_arith => xlSigned, b_bin_pt => 0, b_width => 19, c_has_c_out => 0, c_latency => 1, c_output_width => 20, core_name0 => "addsb_11_0_da33f2d4b3b54185", extra_registers => 0, full_s_arith => 2, full_s_width => 20, latency => 1, overflow => 1, quantization => 1, s_arith => xlSigned, s_bin_pt => 0, s_width => 20 ) port map ( a => register_q_net_x0, b => register_q_net_x1, ce => ce_1_sg_x12, clk => clk_1_sg_x12, clr => '0', en => "1", s => addsub2_s_net ); addsub3: entity work.xladdsub generic map ( a_arith => xlSigned, a_bin_pt => 0, a_width => 19, b_arith => xlSigned, b_bin_pt => 0, b_width => 19, c_has_c_out => 0, c_latency => 1, c_output_width => 20, core_name0 => "addsb_11_0_da33f2d4b3b54185", extra_registers => 0, full_s_arith => 2, full_s_width => 20, latency => 1, overflow => 1, quantization => 1, s_arith => xlSigned, s_bin_pt => 0, s_width => 20 ) port map ( a => register_q_net_x2, b => register_q_net_x3, ce => ce_1_sg_x12, clk => clk_1_sg_x12, clr => '0', en => "1", s => addsub3_s_net ); addsub4: entity work.xladdsub generic map ( a_arith => xlSigned, a_bin_pt => 0, a_width => 20, b_arith => xlSigned, b_bin_pt => 0, b_width => 20, c_has_c_out => 0, c_latency => 1, c_output_width => 21, core_name0 => "addsb_11_0_48bcbc42a6774592", extra_registers => 0, full_s_arith => 2, full_s_width => 21, latency => 1, overflow => 1, quantization => 1, s_arith => xlSigned, s_bin_pt => 0, s_width => 21 ) port map ( a => addsub2_s_net, b => addsub3_s_net, ce => ce_1_sg_x12, clk => clk_1_sg_x12, clr => '0', en => "1", s => addsub4_s_net ); assert_x0: entity work.xlpassthrough generic map ( din_width => 20, dout_width => 20 ) port map ( din => from_register_data_out_net_x0, dout => assert_dout_net ); coef_gain: entity work.xlregister generic map ( d_width => 20, init_value => b"11111111111111111111" ) port map ( ce => ce_1_sg_x12, clk => clk_1_sg_x12, d => assert_dout_net, en(0) => logical4_y_net_x2, rst => "0", q => coef_gain_q_net ); convert1: entity work.xlconvert generic map ( bool_conversion => 0, din_arith => 2, din_bin_pt => 17, din_width => 43, dout_arith => 1, dout_bin_pt => 0, dout_width => 8, latency => 1, overflow => xlSaturate, quantization => xlTruncate ) port map ( ce => ce_1_sg_x12, clk => clk_1_sg_x12, clr => '0', din => mult_p_net, en => "1", dout => convert1_dout_net_x0 ); load_sequencer_8724dffd75: entity work.load_sequencer_entity_8724dffd75 port map ( ce_1 => ce_1_sg_x12, clk_1 => clk_1_sg_x12, load => relational3_op_net_x2, load_1 => logical_y_net_x3, load_2 => logical1_y_net_x2, load_3 => logical2_y_net_x2, load_4 => logical3_y_net_x2, load_5 => logical4_y_net_x2 ); mult: entity work.xlmult generic map ( a_arith => xlSigned, a_bin_pt => 0, a_width => 23, b_arith => xlUnsigned, b_bin_pt => 17, b_width => 20, c_a_type => 0, c_a_width => 23, c_b_type => 1, c_b_width => 20, c_baat => 23, c_output_width => 43, c_type => 0, core_name0 => "mult_11_2_fe92ad55b7635191", extra_registers => 0, multsign => 2, overflow => 1, p_arith => xlSigned, p_bin_pt => 17, p_width => 43, quantization => 1 ) port map ( a => mux_y_net_x0, b => coef_gain_q_net, ce => ce_1_sg_x12, clk => clk_1_sg_x12, clr => '0', core_ce => ce_1_sg_x12, core_clk => clk_1_sg_x12, core_clr => '1', en => "1", rst => "0", p => mult_p_net ); n_tap_fir_compiler_filter1_b6187dc1dd: entity work.n_tap_fir_compiler_filter1_entity_b6187dc1dd port map ( ce_1 => ce_1_sg_x12, ce_logic_1 => ce_logic_1_sg_x5, clk_1 => clk_1_sg_x12, coef => shared_memory_data_out_net_x5, din => l2_x1, load => logical1_y_net_x2, out_x0 => register_q_net_x1 ); n_tap_fir_compiler_filter2_92eb71d873: entity work.n_tap_fir_compiler_filter2_entity_92eb71d873 port map ( ce_1 => ce_1_sg_x12, ce_logic_1 => ce_logic_1_sg_x5, clk_1 => clk_1_sg_x12, coef => shared_memory_data_out_net_x5, din => l3_x1, load => logical2_y_net_x2, out_x0 => register_q_net_x2 ); n_tap_fir_compiler_filter3_5fb9ad894d: entity work.n_tap_fir_compiler_filter1_entity_b6187dc1dd port map ( ce_1 => ce_1_sg_x12, ce_logic_1 => ce_logic_1_sg_x5, clk_1 => clk_1_sg_x12, coef => shared_memory_data_out_net_x5, din => l4_x1, load => logical3_y_net_x2, out_x0 => register_q_net_x3 ); n_tap_fir_compiler_filter4_91b51287e2: entity work.n_tap_fir_compiler_filter_entity_7d40670988 port map ( ce_1 => ce_1_sg_x12, ce_logic_1 => ce_logic_1_sg_x5, clk_1 => clk_1_sg_x12, coef => shared_memory_data_out_net_x5, din => l5_x1, load => logical4_y_net_x2, out_x0 => register_q_net_x4 ); n_tap_fir_compiler_filter_7d40670988: entity work.n_tap_fir_compiler_filter_entity_7d40670988 port map ( ce_1 => ce_1_sg_x12, ce_logic_1 => ce_logic_1_sg_x5, clk_1 => clk_1_sg_x12, coef => shared_memory_data_out_net_x5, din => l1_x1, load => logical_y_net_x3, out_x0 => register_q_net_x0 ); register1: entity work.xlregister generic map ( d_width => 19, init_value => b"0000000000000000000" ) port map ( ce => ce_1_sg_x12, clk => clk_1_sg_x12, d => register_q_net_x4, en => "1", rst => "0", q => register1_q_net ); register2: entity work.xlregister generic map ( d_width => 19, init_value => b"0000000000000000000" ) port map ( ce => ce_1_sg_x12, clk => clk_1_sg_x12, d => register1_q_net, en => "1", rst => "0", q => register2_q_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/Line_Buffer" entity line_buffer_entity_edde027544 is port ( addr: in std_logic_vector(11 downto 0); ce_1: in std_logic; clk_1: in std_logic; data: in std_logic_vector(7 downto 0); l1: out std_logic_vector(7 downto 0); l2: out std_logic_vector(7 downto 0); l3: out std_logic_vector(7 downto 0); l4: out std_logic_vector(7 downto 0); l5: out std_logic_vector(7 downto 0) ); end line_buffer_entity_edde027544; architecture structural of line_buffer_entity_edde027544 is signal blue_x0: std_logic_vector(7 downto 0); signal ce_1_sg_x13: std_logic; signal clk_1_sg_x13: std_logic; signal constant6_op_net: std_logic; signal delay9_q_net: std_logic_vector(7 downto 0); signal l1_x2: std_logic_vector(7 downto 0); signal l2_x2: std_logic_vector(7 downto 0); signal l3_x2: std_logic_vector(7 downto 0); signal l4_x2: std_logic_vector(7 downto 0); signal l5_x2: std_logic_vector(7 downto 0); signal rctr_q_net_x0: std_logic_vector(11 downto 0); signal single_port_ram2_data_out_net: std_logic_vector(7 downto 0); signal single_port_ram3_data_out_net: std_logic_vector(7 downto 0); signal single_port_ram_data_out_net: std_logic_vector(7 downto 0); begin rctr_q_net_x0 <= addr; ce_1_sg_x13 <= ce_1; clk_1_sg_x13 <= clk_1; blue_x0 <= data; l1 <= l1_x2; l2 <= l2_x2; l3 <= l3_x2; l4 <= l4_x2; l5 <= l5_x2; constant6: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant6_op_net ); delay1: entity work.delay_23f848c85b port map ( ce => ce_1_sg_x13, clk => clk_1_sg_x13, clr => '0', d => single_port_ram2_data_out_net, q => l3_x2 ); delay2: entity work.delay_9565135955 port map ( ce => ce_1_sg_x13, clk => clk_1_sg_x13, clr => '0', d => single_port_ram3_data_out_net, q => l4_x2 ); delay7: entity work.delay_fb08f2e938 port map ( ce => ce_1_sg_x13, clk => clk_1_sg_x13, clr => '0', d => delay9_q_net, q => l5_x2 ); delay8: entity work.delay_ebec135d8a port map ( ce => ce_1_sg_x13, clk => clk_1_sg_x13, clr => '0', d => single_port_ram_data_out_net, q => l2_x2 ); delay9: entity work.delay_23f848c85b port map ( ce => ce_1_sg_x13, clk => clk_1_sg_x13, clr => '0', d => blue_x0, q => delay9_q_net ); single_port_ram: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x13, clk => clk_1_sg_x13, data_in => single_port_ram2_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram_data_out_net ); single_port_ram1: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x13, clk => clk_1_sg_x13, data_in => single_port_ram_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => l1_x2 ); single_port_ram2: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x13, clk => clk_1_sg_x13, data_in => single_port_ram3_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram2_data_out_net ); single_port_ram3: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x13, clk => clk_1_sg_x13, data_in => delay9_q_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram3_data_out_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter" entity blue_filter_entity_d29ca0c8b1 is port ( addr: in std_logic_vector(11 downto 0); ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; coef: in std_logic_vector(6 downto 0); din: in std_logic_vector(7 downto 0); gain: in std_logic_vector(19 downto 0); load: in std_logic; dout: out std_logic_vector(7 downto 0) ); end blue_filter_entity_d29ca0c8b1; architecture structural of blue_filter_entity_d29ca0c8b1 is signal blue_x1: std_logic_vector(7 downto 0); signal ce_1_sg_x14: std_logic; signal ce_logic_1_sg_x6: std_logic; signal clk_1_sg_x14: std_logic; signal convert1_dout_net_x1: std_logic_vector(7 downto 0); signal from_register_data_out_net_x1: std_logic_vector(19 downto 0); signal l1_x2: std_logic_vector(7 downto 0); signal l2_x2: std_logic_vector(7 downto 0); signal l3_x2: std_logic_vector(7 downto 0); signal l4_x2: std_logic_vector(7 downto 0); signal l5_x2: std_logic_vector(7 downto 0); signal rctr_q_net_x1: std_logic_vector(11 downto 0); signal relational3_op_net_x3: std_logic; signal shared_memory_data_out_net_x6: std_logic_vector(6 downto 0); begin rctr_q_net_x1 <= addr; ce_1_sg_x14 <= ce_1; ce_logic_1_sg_x6 <= ce_logic_1; clk_1_sg_x14 <= clk_1; shared_memory_data_out_net_x6 <= coef; blue_x1 <= din; from_register_data_out_net_x1 <= gain; relational3_op_net_x3 <= load; dout <= convert1_dout_net_x1; line_buffer_edde027544: entity work.line_buffer_entity_edde027544 port map ( addr => rctr_q_net_x1, ce_1 => ce_1_sg_x14, clk_1 => clk_1_sg_x14, data => blue_x1, l1 => l1_x2, l2 => l2_x2, l3 => l3_x2, l4 => l4_x2, l5 => l5_x2 ); x5x5_filter_e192f59c95: entity work.x5x5_filter_entity_e192f59c95 port map ( ce_1 => ce_1_sg_x14, ce_logic_1 => ce_logic_1_sg_x6, clk_1 => clk_1_sg_x14, coef => shared_memory_data_out_net_x6, gain => from_register_data_out_net_x1, line1 => l1_x2, line2 => l2_x2, line3 => l3_x2, line4 => l4_x2, line5 => l5_x2, load => relational3_op_net_x3, dout => convert1_dout_net_x1 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Ctrl_Delay/Line_Buffer" entity line_buffer_entity_d14b7609fd is port ( addr: in std_logic_vector(11 downto 0); ce_1: in std_logic; clk_1: in std_logic; data: in std_logic_vector(4 downto 0); l3_x0: out std_logic_vector(4 downto 0) ); end line_buffer_entity_d14b7609fd; architecture structural of line_buffer_entity_d14b7609fd is signal ce_1_sg_x15: std_logic; signal clk_1_sg_x15: std_logic; signal concat_y_net_x0: std_logic_vector(4 downto 0); signal constant6_op_net: std_logic; signal delay9_q_net: std_logic_vector(4 downto 0); signal l3_x1: std_logic_vector(4 downto 0); signal rctr_q_net_x2: std_logic_vector(11 downto 0); signal single_port_ram2_data_out_net: std_logic_vector(4 downto 0); signal single_port_ram3_data_out_net: std_logic_vector(4 downto 0); begin rctr_q_net_x2 <= addr; ce_1_sg_x15 <= ce_1; clk_1_sg_x15 <= clk_1; concat_y_net_x0 <= data; l3_x0 <= l3_x1; constant6: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant6_op_net ); delay1: entity work.delay_38f665f8aa port map ( ce => ce_1_sg_x15, clk => clk_1_sg_x15, clr => '0', d => single_port_ram2_data_out_net, q => l3_x1 ); delay9: entity work.delay_38f665f8aa port map ( ce => ce_1_sg_x15, clk => clk_1_sg_x15, clr => '0', d => concat_y_net_x0, q => delay9_q_net ); single_port_ram2: entity work.xlspram generic map ( c_address_width => 12, c_width => 5, core_name0 => "bmg_62_05852d43925e39b8", latency => 1 ) port map ( addr => rctr_q_net_x2, ce => ce_1_sg_x15, clk => clk_1_sg_x15, data_in => single_port_ram3_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram2_data_out_net ); single_port_ram3: entity work.xlspram generic map ( c_address_width => 12, c_width => 5, core_name0 => "bmg_62_05852d43925e39b8", latency => 1 ) port map ( addr => rctr_q_net_x2, ce => ce_1_sg_x15, clk => clk_1_sg_x15, data_in => delay9_q_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram3_data_out_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Ctrl_Delay" entity ctrl_delay_entity_b2aeac3e46 is port ( addr: in std_logic_vector(11 downto 0); av_i: in std_logic; ce_1: in std_logic; clk_1: in std_logic; hb_i: in std_logic; hs_i: in std_logic; vb_i: in std_logic; vs_i: in std_logic; av_o: out std_logic; hb_o: out std_logic; hs_o: out std_logic; vb_o: out std_logic; vs_o: out std_logic ); end ctrl_delay_entity_b2aeac3e46; architecture structural of ctrl_delay_entity_b2aeac3e46 is signal active_video_i_net_x0: std_logic; signal bit0_y_net_x0: std_logic; signal bit1_y_net_x0: std_logic; signal bit2_y_net_x0: std_logic; signal bit3_y_net_x0: std_logic; signal bit4_y_net_x0: std_logic; signal ce_1_sg_x16: std_logic; signal clk_1_sg_x16: std_logic; signal concat_y_net_x0: std_logic_vector(4 downto 0); signal delay7_q_net: std_logic_vector(4 downto 0); signal hblank_i_net_x0: std_logic; signal hsync_i_net_x0: std_logic; signal l3_x1: std_logic_vector(4 downto 0); signal rctr_q_net_x3: std_logic_vector(11 downto 0); signal vblank_i_net_x0: std_logic; signal vsync_i_net_x0: std_logic; begin rctr_q_net_x3 <= addr; active_video_i_net_x0 <= av_i; ce_1_sg_x16 <= ce_1; clk_1_sg_x16 <= clk_1; hblank_i_net_x0 <= hb_i; hsync_i_net_x0 <= hs_i; vblank_i_net_x0 <= vb_i; vsync_i_net_x0 <= vs_i; av_o <= bit4_y_net_x0; hb_o <= bit0_y_net_x0; hs_o <= bit2_y_net_x0; vb_o <= bit1_y_net_x0; vs_o <= bit3_y_net_x0; bit0: entity work.xlslice generic map ( new_lsb => 0, new_msb => 0, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit0_y_net_x0 ); bit1: entity work.xlslice generic map ( new_lsb => 1, new_msb => 1, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit1_y_net_x0 ); bit2: entity work.xlslice generic map ( new_lsb => 2, new_msb => 2, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit2_y_net_x0 ); bit3: entity work.xlslice generic map ( new_lsb => 3, new_msb => 3, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit3_y_net_x0 ); bit4: entity work.xlslice generic map ( new_lsb => 4, new_msb => 4, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit4_y_net_x0 ); concat: entity work.concat_2b3acb49f4 port map ( ce => '0', clk => '0', clr => '0', in0(0) => active_video_i_net_x0, in1(0) => vsync_i_net_x0, in2(0) => hsync_i_net_x0, in3(0) => vblank_i_net_x0, in4(0) => hblank_i_net_x0, y => concat_y_net_x0 ); delay7: entity work.delay_4714bdf2a7 port map ( ce => ce_1_sg_x16, clk => clk_1_sg_x16, clr => '0', d => l3_x1, q => delay7_q_net ); line_buffer_d14b7609fd: entity work.line_buffer_entity_d14b7609fd port map ( addr => rctr_q_net_x3, ce_1 => ce_1_sg_x16, clk_1 => clk_1_sg_x16, data => concat_y_net_x0, l3_x0 => l3_x1 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/coefficient_memory" entity coefficient_memory_entity_d275723ee2 is port ( ce_1: in std_logic; clk_1: in std_logic; from_register1: in std_logic; vsync: in std_logic; constant1_x0: out std_logic; constant2_x0: out std_logic_vector(6 downto 0); counter_x0: out std_logic_vector(4 downto 0); load: out std_logic ); end coefficient_memory_entity_d275723ee2; architecture structural of coefficient_memory_entity_d275723ee2 is signal ce_1_sg_x47: std_logic; signal clk_1_sg_x47: std_logic; signal constant1_op_net_x0: std_logic; signal constant2_op_net_x0: std_logic_vector(6 downto 0); signal constant_op_net: std_logic_vector(4 downto 0); signal convert1_dout_net: std_logic; signal convert_dout_net: std_logic; signal counter_op_net_x0: std_logic_vector(4 downto 0); signal expression_dout_net: std_logic; signal from_register1_data_out_net_x0: std_logic; signal inverter_op_net: std_logic; signal register1_q_net: std_logic; signal register_q_net: std_logic; signal relational3_op_net_x10: std_logic; signal vsync_i_net_x1: std_logic; begin ce_1_sg_x47 <= ce_1; clk_1_sg_x47 <= clk_1; from_register1_data_out_net_x0 <= from_register1; vsync_i_net_x1 <= vsync; constant1_x0 <= constant1_op_net_x0; constant2_x0 <= constant2_op_net_x0; counter_x0 <= counter_op_net_x0; load <= relational3_op_net_x10; constant1: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant1_op_net_x0 ); constant2: entity work.constant_7244cd602b port map ( ce => '0', clk => '0', clr => '0', op => constant2_op_net_x0 ); constant_x0: entity work.constant_fdce3802d7 port map ( ce => '0', clk => '0', clr => '0', op => constant_op_net ); convert: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x47, clk => clk_1_sg_x47, clr => '0', din(0) => register1_q_net, en => "1", dout(0) => convert_dout_net ); convert1: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x47, clk => clk_1_sg_x47, clr => '0', din(0) => inverter_op_net, en => "1", dout(0) => convert1_dout_net ); counter: entity work.xlcounter_limit generic map ( cnt_15_0 => 25, cnt_31_16 => 0, cnt_47_32 => 0, cnt_63_48 => 0, core_name0 => "cntr_11_0_862f833518f4973a", count_limited => 1, op_arith => xlUnsigned, op_width => 5 ) port map ( ce => ce_1_sg_x47, clk => clk_1_sg_x47, clr => '0', en(0) => relational3_op_net_x10, rst(0) => convert_dout_net, op => counter_op_net_x0 ); expression: entity work.expr_1e33fcde03 port map ( a(0) => vsync_i_net_x1, b(0) => register_q_net, ce => '0', clk => '0', clr => '0', dout(0) => expression_dout_net ); inverter: entity work.inverter_e2b989a05e port map ( ce => ce_1_sg_x47, clk => clk_1_sg_x47, clr => '0', ip(0) => from_register1_data_out_net_x0, op(0) => inverter_op_net ); register1: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x47, clk => clk_1_sg_x47, d(0) => expression_dout_net, en => "1", rst(0) => convert1_dout_net, q(0) => register1_q_net ); register_x0: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x47, clk => clk_1_sg_x47, d(0) => vsync_i_net_x1, en => "1", rst => "0", q(0) => register_q_net ); relational3: entity work.relational_dc5bc996c9 port map ( a => constant_op_net, b => counter_op_net_x0, ce => '0', clk => '0', clr => '0', op(0) => relational3_op_net_x10 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/line_ctrs/loop_ctr" entity loop_ctr_entity_861427efa6 is port ( ce_1: in std_logic; clk_1: in std_logic; reset: in std_logic; count: out std_logic_vector(11 downto 0) ); end loop_ctr_entity_861427efa6; architecture structural of loop_ctr_entity_861427efa6 is signal addsub1_s_net: std_logic_vector(11 downto 0); signal bool2_dout_net: std_logic_vector(12 downto 0); signal bool_dout_net: std_logic; signal ce_1_sg_x48: std_logic; signal clk_1_sg_x48: std_logic; signal constant1_op_net: std_logic_vector(11 downto 0); signal constant6_op_net: std_logic_vector(11 downto 0); signal constant7_op_net: std_logic_vector(11 downto 0); signal expression_dout_net_x0: std_logic; signal expression_dout_net_x1: std_logic; signal mux_y_net: std_logic_vector(12 downto 0); signal rctr_q_net_x8: std_logic_vector(11 downto 0); signal relational5_op_net: std_logic; signal tcfb1_q_net: std_logic; signal tcfb2_q_net: std_logic; begin ce_1_sg_x48 <= ce_1; clk_1_sg_x48 <= clk_1; expression_dout_net_x1 <= reset; count <= rctr_q_net_x8; addsub1: entity work.addsub_ba7fff8397 port map ( a => mux_y_net, b => constant6_op_net, ce => ce_1_sg_x48, clk => clk_1_sg_x48, clr => '0', s => addsub1_s_net ); bool: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x48, clk => clk_1_sg_x48, clr => '0', din(0) => expression_dout_net_x1, en => "1", dout(0) => bool_dout_net ); bool2: entity work.xlconvert generic map ( bool_conversion => 0, din_arith => 1, din_bin_pt => 0, din_width => 12, dout_arith => 2, dout_bin_pt => 0, dout_width => 13, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x48, clk => clk_1_sg_x48, clr => '0', din => rctr_q_net_x8, en => "1", dout => bool2_dout_net ); constant1: entity work.constant_9b805894ff port map ( ce => '0', clk => '0', clr => '0', op => constant1_op_net ); constant6: entity work.constant_7c91b1b314 port map ( ce => '0', clk => '0', clr => '0', op => constant6_op_net ); constant7: entity work.constant_be6eece885 port map ( ce => '0', clk => '0', clr => '0', op => constant7_op_net ); expression: entity work.expr_f50101e101 port map ( ce => '0', clk => '0', clr => '0', reset(0) => tcfb2_q_net, tc(0) => tcfb1_q_net, dout(0) => expression_dout_net_x0 ); mux: entity work.mux_b53670f063 port map ( ce => '0', clk => '0', clr => '0', d0 => constant1_op_net, d1 => bool2_dout_net, sel(0) => expression_dout_net_x0, y => mux_y_net ); rctr: entity work.xlregister generic map ( d_width => 12, init_value => b"000000000000" ) port map ( ce => ce_1_sg_x48, clk => clk_1_sg_x48, d => addsub1_s_net, en => "1", rst => "0", q => rctr_q_net_x8 ); relational5: entity work.relational_d36fe12c1c port map ( a => rctr_q_net_x8, b => constant7_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational5_op_net ); tcfb1: entity work.delay_9f02caa990 port map ( ce => ce_1_sg_x48, clk => clk_1_sg_x48, clr => '0', d(0) => relational5_op_net, q(0) => tcfb1_q_net ); tcfb2: entity work.delay_9f02caa990 port map ( ce => ce_1_sg_x48, clk => clk_1_sg_x48, clr => '0', d(0) => bool_dout_net, q(0) => tcfb2_q_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/line_ctrs" entity line_ctrs_entity_8878c4bf27 is port ( ce_1: in std_logic; clk_1: in std_logic; h: in std_logic; rst: in std_logic; addr: out std_logic_vector(11 downto 0) ); end line_ctrs_entity_8878c4bf27; architecture structural of line_ctrs_entity_8878c4bf27 is signal ce_1_sg_x49: std_logic; signal clk_1_sg_x49: std_logic; signal delay_q_net: std_logic; signal expression_dout_net_x1: std_logic; signal hsync_i_net_x1: std_logic; signal rctr_q_net_x9: std_logic_vector(11 downto 0); signal reset_net_x0: std_logic; begin ce_1_sg_x49 <= ce_1; clk_1_sg_x49 <= clk_1; hsync_i_net_x1 <= h; reset_net_x0 <= rst; addr <= rctr_q_net_x9; delay: entity work.delay_5753e4c658 port map ( ce => ce_1_sg_x49, clk => clk_1_sg_x49, clr => '0', d(0) => hsync_i_net_x1, q(0) => delay_q_net ); expression: entity work.expr_305312c97b port map ( ce => '0', clk => '0', clr => '0', d0(0) => hsync_i_net_x1, d1(0) => delay_q_net, rst(0) => reset_net_x0, dout(0) => expression_dout_net_x1 ); loop_ctr_861427efa6: entity work.loop_ctr_entity_861427efa6 port map ( ce_1 => ce_1_sg_x49, clk_1 => clk_1_sg_x49, reset => expression_dout_net_x1, count => rctr_q_net_x9 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters" entity x5x5_filters_entity_1ec75b0e3e is port ( av_i: in std_logic; b: in std_logic_vector(7 downto 0); ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; from_register: in std_logic_vector(19 downto 0); from_register1: in std_logic; g: in std_logic_vector(7 downto 0); hb_i: in std_logic; hs_i: in std_logic; r: in std_logic_vector(7 downto 0); rst: in std_logic; shared_memory: in std_logic_vector(6 downto 0); vb_i: in std_logic; vs_i: in std_logic; b_o: out std_logic_vector(7 downto 0); coefficient_memory: out std_logic; coefficient_memory_x0: out std_logic_vector(6 downto 0); coefficient_memory_x1: out std_logic_vector(4 downto 0); de_o: out std_logic; g_o: out std_logic_vector(7 downto 0); hb_o: out std_logic; hs_o: out std_logic; r_o: out std_logic_vector(7 downto 0); vb_o: out std_logic; vs_o: out std_logic ); end x5x5_filters_entity_1ec75b0e3e; architecture structural of x5x5_filters_entity_1ec75b0e3e is signal active_video_i_net_x1: std_logic; signal bit0_y_net_x1: std_logic; signal bit1_y_net_x1: std_logic; signal bit2_y_net_x1: std_logic; signal bit3_y_net_x1: std_logic; signal bit4_y_net_x1: std_logic; signal blue_x2: std_logic_vector(7 downto 0); signal ce_1_sg_x50: std_logic; signal ce_logic_1_sg_x21: std_logic; signal clk_1_sg_x50: std_logic; signal constant1_op_net_x1: std_logic; signal constant2_op_net_x1: std_logic_vector(6 downto 0); signal convert1_dout_net_x4: std_logic_vector(7 downto 0); signal convert1_dout_net_x5: std_logic_vector(7 downto 0); signal convert1_dout_net_x6: std_logic_vector(7 downto 0); signal counter_op_net_x1: std_logic_vector(4 downto 0); signal from_register1_data_out_net_x1: std_logic; signal from_register_data_out_net_x6: std_logic_vector(19 downto 0); signal green_x2: std_logic_vector(7 downto 0); signal hblank_i_net_x1: std_logic; signal hsync_i_net_x2: std_logic; signal rctr_q_net_x9: std_logic_vector(11 downto 0); signal red_x2: std_logic_vector(7 downto 0); signal relational3_op_net_x10: std_logic; signal reset_net_x1: std_logic; signal shared_memory_data_out_net_x21: std_logic_vector(6 downto 0); signal vblank_i_net_x1: std_logic; signal vsync_i_net_x2: std_logic; begin active_video_i_net_x1 <= av_i; blue_x2 <= b; ce_1_sg_x50 <= ce_1; ce_logic_1_sg_x21 <= ce_logic_1; clk_1_sg_x50 <= clk_1; from_register_data_out_net_x6 <= from_register; from_register1_data_out_net_x1 <= from_register1; green_x2 <= g; hblank_i_net_x1 <= hb_i; hsync_i_net_x2 <= hs_i; red_x2 <= r; reset_net_x1 <= rst; shared_memory_data_out_net_x21 <= shared_memory; vblank_i_net_x1 <= vb_i; vsync_i_net_x2 <= vs_i; b_o <= convert1_dout_net_x4; coefficient_memory <= constant1_op_net_x1; coefficient_memory_x0 <= constant2_op_net_x1; coefficient_memory_x1 <= counter_op_net_x1; de_o <= bit4_y_net_x1; g_o <= convert1_dout_net_x5; hb_o <= bit0_y_net_x1; hs_o <= bit2_y_net_x1; r_o <= convert1_dout_net_x6; vb_o <= bit1_y_net_x1; vs_o <= bit3_y_net_x1; blue_filter_d29ca0c8b1: entity work.blue_filter_entity_d29ca0c8b1 port map ( addr => rctr_q_net_x9, ce_1 => ce_1_sg_x50, ce_logic_1 => ce_logic_1_sg_x21, clk_1 => clk_1_sg_x50, coef => shared_memory_data_out_net_x21, din => blue_x2, gain => from_register_data_out_net_x6, load => relational3_op_net_x10, dout => convert1_dout_net_x4 ); coefficient_memory_d275723ee2: entity work.coefficient_memory_entity_d275723ee2 port map ( ce_1 => ce_1_sg_x50, clk_1 => clk_1_sg_x50, from_register1 => from_register1_data_out_net_x1, vsync => vsync_i_net_x2, constant1_x0 => constant1_op_net_x1, constant2_x0 => constant2_op_net_x1, counter_x0 => counter_op_net_x1, load => relational3_op_net_x10 ); ctrl_delay_b2aeac3e46: entity work.ctrl_delay_entity_b2aeac3e46 port map ( addr => rctr_q_net_x9, av_i => active_video_i_net_x1, ce_1 => ce_1_sg_x50, clk_1 => clk_1_sg_x50, hb_i => hblank_i_net_x1, hs_i => hsync_i_net_x2, vb_i => vblank_i_net_x1, vs_i => vsync_i_net_x2, av_o => bit4_y_net_x1, hb_o => bit0_y_net_x1, hs_o => bit2_y_net_x1, vb_o => bit1_y_net_x1, vs_o => bit3_y_net_x1 ); green_filter_dc51fce7d5: entity work.blue_filter_entity_d29ca0c8b1 port map ( addr => rctr_q_net_x9, ce_1 => ce_1_sg_x50, ce_logic_1 => ce_logic_1_sg_x21, clk_1 => clk_1_sg_x50, coef => shared_memory_data_out_net_x21, din => green_x2, gain => from_register_data_out_net_x6, load => relational3_op_net_x10, dout => convert1_dout_net_x5 ); line_ctrs_8878c4bf27: entity work.line_ctrs_entity_8878c4bf27 port map ( ce_1 => ce_1_sg_x50, clk_1 => clk_1_sg_x50, h => hsync_i_net_x2, rst => reset_net_x1, addr => rctr_q_net_x9 ); red_filter_078d79d78e: entity work.blue_filter_entity_d29ca0c8b1 port map ( addr => rctr_q_net_x9, ce_1 => ce_1_sg_x50, ce_logic_1 => ce_logic_1_sg_x21, clk_1 => clk_1_sg_x50, coef => shared_memory_data_out_net_x21, din => red_x2, gain => from_register_data_out_net_x6, load => relational3_op_net_x10, dout => convert1_dout_net_x6 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/EDK Processor" entity edk_processor_entity_45d14a6139 is port ( plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); shared_memory: in std_logic_vector(6 downto 0); splb_rst: in std_logic; to_register: in std_logic; to_register1: in std_logic_vector(19 downto 0); constant5_x0: out std_logic; plb_decode_x0: out std_logic; plb_decode_x1: out std_logic; plb_decode_x2: out std_logic; plb_decode_x3: out std_logic; plb_decode_x4: out std_logic_vector(31 downto 0); plb_memmap_x0: out std_logic; plb_memmap_x1: out std_logic; plb_memmap_x2: out std_logic_vector(19 downto 0); plb_memmap_x3: out std_logic; plb_memmap_x4: out std_logic_vector(4 downto 0); plb_memmap_x5: out std_logic_vector(6 downto 0); plb_memmap_x6: out std_logic ); end edk_processor_entity_45d14a6139; architecture structural of edk_processor_entity_45d14a6139 is signal bankaddr: std_logic_vector(1 downto 0); signal coef_buffer_addr_x0: std_logic_vector(4 downto 0); signal coef_buffer_din_x0: std_logic_vector(6 downto 0); signal coef_buffer_dout_x0: std_logic_vector(6 downto 0); signal coef_buffer_we_x0: std_logic; signal coef_gain_din_x0: std_logic_vector(19 downto 0); signal coef_gain_dout_x0: std_logic_vector(19 downto 0); signal coef_gain_en_x0: std_logic; signal coef_update_din_x0: std_logic; signal coef_update_dout_x0: std_logic; signal coef_update_en_x0: std_logic; signal linearaddr: std_logic_vector(7 downto 0); signal plb_abus_net_x0: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x0: std_logic; signal plb_clk_1_sg_x0: std_logic; signal plb_pavalid_net_x0: std_logic; signal plb_rnw_net_x0: std_logic; signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0); signal rddata: std_logic_vector(31 downto 0); signal rnwreg: std_logic; signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0); signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_rddbus_x0: std_logic_vector(31 downto 0); signal sl_wait_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_net_x0: std_logic; signal wrdbusreg: std_logic_vector(31 downto 0); begin plb_abus_net_x0 <= plb_abus; plb_ce_1_sg_x0 <= plb_ce_1; plb_clk_1_sg_x0 <= plb_clk_1; plb_pavalid_net_x0 <= plb_pavalid; plb_rnw_net_x0 <= plb_rnw; plb_wrdbus_net_x0 <= plb_wrdbus; sg_plb_addrpref_net_x0 <= sg_plb_addrpref; coef_buffer_dout_x0 <= shared_memory; splb_rst_net_x0 <= splb_rst; coef_update_dout_x0 <= to_register; coef_gain_dout_x0 <= to_register1; constant5_x0 <= sl_wait_x0; plb_decode_x0 <= sl_addrack_x0; plb_decode_x1 <= sl_rdcomp_x0; plb_decode_x2 <= sl_wrdack_x0; plb_decode_x3 <= sl_rddack_x0; plb_decode_x4 <= sl_rddbus_x0; plb_memmap_x0 <= coef_update_din_x0; plb_memmap_x1 <= coef_update_en_x0; plb_memmap_x2 <= coef_gain_din_x0; plb_memmap_x3 <= coef_gain_en_x0; plb_memmap_x4 <= coef_buffer_addr_x0; plb_memmap_x5 <= coef_buffer_din_x0; plb_memmap_x6 <= coef_buffer_we_x0; constant5: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => sl_wait_x0 ); plb_decode: entity work.mcode_block_f4d0462e0e port map ( addrpref => sg_plb_addrpref_net_x0, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', plbabus => plb_abus_net_x0, plbpavalid(0) => plb_pavalid_net_x0, plbrnw(0) => plb_rnw_net_x0, plbrst(0) => splb_rst_net_x0, plbwrdbus => plb_wrdbus_net_x0, rddata => rddata, addrack(0) => sl_addrack_x0, bankaddr => bankaddr, linearaddr => linearaddr, rdcomp(0) => sl_rdcomp_x0, rddack(0) => sl_rddack_x0, rddbus => sl_rddbus_x0, rnwreg(0) => rnwreg, wrdack(0) => sl_wrdack_x0, wrdbusreg => wrdbusreg ); plb_memmap: entity work.mcode_block_6fff803424 port map ( addrack(0) => sl_addrack_x0, bankaddr => bankaddr, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', linearaddr => linearaddr, rnwreg(0) => rnwreg, sm_coef_buffer => coef_buffer_dout_x0, sm_coef_gain => coef_gain_dout_x0, sm_coef_update(0) => coef_update_dout_x0, wrdbus => wrdbusreg, read_bank_out => rddata, sm_coef_buffer_addr => coef_buffer_addr_x0, sm_coef_buffer_din => coef_buffer_din_x0, sm_coef_buffer_we(0) => coef_buffer_we_x0, sm_coef_gain_din => coef_gain_din_x0, sm_coef_gain_en(0) => coef_gain_en_x0, sm_coef_update_din(0) => coef_update_din_x0, sm_coef_update_en(0) => coef_update_en_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir" entity sg_2d_fir is port ( active_video_i: in std_logic; ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; data_out: in std_logic_vector(19 downto 0); data_out_x0: in std_logic; data_out_x1: in std_logic_vector(6 downto 0); data_out_x2: in std_logic_vector(6 downto 0); dout: in std_logic; dout_x0: in std_logic_vector(19 downto 0); hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); reset: in std_logic; sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(23 downto 0); vsync_i: in std_logic; active_video_o: out std_logic; addr: out std_logic_vector(4 downto 0); addr_x0: out std_logic_vector(4 downto 0); data_in: out std_logic_vector(6 downto 0); data_in_x0: out std_logic_vector(6 downto 0); data_in_x1: out std_logic; data_in_x2: out std_logic_vector(19 downto 0); en: out std_logic; en_x0: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(23 downto 0); vsync_o: out std_logic; we: out std_logic; we_x0: out std_logic ); end sg_2d_fir; architecture structural of sg_2d_fir is attribute core_generation_info: string; attribute core_generation_info of structural : architecture is "sg_2d_fir,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=669,xilinx_adder_subtracter_block=13,xilinx_arithmetic_relational_operator_block=23,xilinx_assert_block=3,xilinx_bit_slice_extractor_block=11,xilinx_bitwise_expression_evaluator_block=3,xilinx_bus_concatenator_block=2,xilinx_bus_multiplexer_block=4,xilinx_constant_block_block=29,xilinx_counter_block=7,xilinx_delay_block=25,xilinx_edk_processor_block=1,xilinx_fir_compiler_5_0_block=15,xilinx_gateway_in_block=13,xilinx_gateway_out_block=13,xilinx_inverter_block=16,xilinx_logical_block_block=33,xilinx_mcode_block_block=2,xilinx_multiplier_block=3,xilinx_negate_block_block=3,xilinx_register_block=63,xilinx_shared_memory_based_from_register_block=2,xilinx_shared_memory_based_to_register_block=2,xilinx_shared_memory_random_access_memory_block=2,xilinx_single_port_random_access_memory_block=16,xilinx_system_generator_block=1,xilinx_type_converter_block=7,}"; signal active_video_i_net: std_logic; signal active_video_o_net: std_logic; signal addr_net: std_logic_vector(4 downto 0); signal addr_x0_net: std_logic_vector(4 downto 0); signal blue_x2: std_logic_vector(7 downto 0); signal ce_1_sg_x51: std_logic; signal ce_logic_1_sg_x22: std_logic; signal clk_1_sg_x51: std_logic; signal convert1_dout_net_x4: std_logic_vector(7 downto 0); signal convert1_dout_net_x5: std_logic_vector(7 downto 0); signal convert1_dout_net_x6: std_logic_vector(7 downto 0); signal data_in_net: std_logic_vector(6 downto 0); signal data_in_x0_net: std_logic_vector(6 downto 0); signal data_in_x1_net: std_logic; signal data_in_x2_net: std_logic_vector(19 downto 0); signal data_out_net: std_logic_vector(19 downto 0); signal data_out_x0_net: std_logic; signal data_out_x1_net: std_logic_vector(6 downto 0); signal data_out_x2_net: std_logic_vector(6 downto 0); signal dout_net: std_logic; signal dout_x0_net: std_logic_vector(19 downto 0); signal en_net: std_logic; signal en_x0_net: std_logic; signal green_x2: std_logic_vector(7 downto 0); signal hblank_i_net: std_logic; signal hblank_o_net: std_logic; signal hsync_i_net: std_logic; signal hsync_o_net: std_logic; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal red_x2: std_logic_vector(7 downto 0); signal reset_net: std_logic; signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal splb_rst_net: std_logic; signal vblank_i_net: std_logic; signal vblank_o_net: std_logic; signal video_data_i_net: std_logic_vector(23 downto 0); signal video_data_o_net: std_logic_vector(23 downto 0); signal vsync_i_net: std_logic; signal vsync_o_net: std_logic; signal we_net: std_logic; signal we_x0_net: std_logic; begin active_video_i_net <= active_video_i; ce_1_sg_x51 <= ce_1; ce_logic_1_sg_x22 <= ce_logic_1; clk_1_sg_x51 <= clk_1; data_out_net <= data_out; data_out_x0_net <= data_out_x0; data_out_x1_net <= data_out_x1; data_out_x2_net <= data_out_x2; dout_net <= dout; dout_x0_net <= dout_x0; hblank_i_net <= hblank_i; hsync_i_net <= hsync_i; plb_abus_net <= plb_abus; plb_ce_1_sg_x1 <= plb_ce_1; plb_clk_1_sg_x1 <= plb_clk_1; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; reset_net <= reset; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; vblank_i_net <= vblank_i; video_data_i_net <= video_data_i; vsync_i_net <= vsync_i; active_video_o <= active_video_o_net; addr <= addr_net; addr_x0 <= addr_x0_net; data_in <= data_in_net; data_in_x0 <= data_in_x0_net; data_in_x1 <= data_in_x1_net; data_in_x2 <= data_in_x2_net; en <= en_net; en_x0 <= en_x0_net; hblank_o <= hblank_o_net; hsync_o <= hsync_o_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x1; sl_wrdack <= sl_wrdack_x1; vblank_o <= vblank_o_net; video_data_o <= video_data_o_net; vsync_o <= vsync_o_net; we <= we_net; we_x0 <= we_x0_net; concat: entity work.concat_d0d1b9533e port map ( ce => '0', clk => '0', clr => '0', in0 => convert1_dout_net_x6, in1 => convert1_dout_net_x5, in2 => convert1_dout_net_x4, y => video_data_o_net ); edk_processor_45d14a6139: entity work.edk_processor_entity_45d14a6139 port map ( plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, shared_memory => data_out_x2_net, splb_rst => splb_rst_net, to_register => dout_net, to_register1 => dout_x0_net, constant5_x0 => sl_wait_net, plb_decode_x0 => sl_addrack_net, plb_decode_x1 => sl_rdcomp_net, plb_decode_x2 => sl_wrdack_x1, plb_decode_x3 => sl_rddack_net, plb_decode_x4 => sl_rddbus_net, plb_memmap_x0 => data_in_x1_net, plb_memmap_x1 => en_net, plb_memmap_x2 => data_in_x2_net, plb_memmap_x3 => en_x0_net, plb_memmap_x4 => addr_x0_net, plb_memmap_x5 => data_in_x0_net, plb_memmap_x6 => we_x0_net ); slice15downto8: entity work.xlslice generic map ( new_lsb => 8, new_msb => 15, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => green_x2 ); slice23downto16: entity work.xlslice generic map ( new_lsb => 16, new_msb => 23, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => red_x2 ); slice7downto0: entity work.xlslice generic map ( new_lsb => 0, new_msb => 7, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => blue_x2 ); x5x5_filters_1ec75b0e3e: entity work.x5x5_filters_entity_1ec75b0e3e port map ( av_i => active_video_i_net, b => blue_x2, ce_1 => ce_1_sg_x51, ce_logic_1 => ce_logic_1_sg_x22, clk_1 => clk_1_sg_x51, from_register => data_out_net, from_register1 => data_out_x0_net, g => green_x2, hb_i => hblank_i_net, hs_i => hsync_i_net, r => red_x2, rst => reset_net, shared_memory => data_out_x1_net, vb_i => vblank_i_net, vs_i => vsync_i_net, b_o => convert1_dout_net_x4, coefficient_memory => we_net, coefficient_memory_x0 => data_in_net, coefficient_memory_x1 => addr_net, de_o => active_video_o_net, g_o => convert1_dout_net_x5, hb_o => hblank_o_net, hs_o => hsync_o_net, r_o => convert1_dout_net_x6, vb_o => vblank_o_net, vs_o => vsync_o_net ); end structural;
gpl-3.0
mcoughli/root_of_trust
operational_os/hls/contact_discovery_axi_one_db_load/solution1/syn/vhdl/contact_discovery_AXILiteS_s_axi.vhd
3
34997
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity contact_discovery_AXILiteS_s_axi is generic ( C_S_AXI_ADDR_WIDTH : INTEGER := 15; C_S_AXI_DATA_WIDTH : INTEGER := 32); port ( -- axi4 lite slave signals ACLK :in STD_LOGIC; ARESET :in STD_LOGIC; ACLK_EN :in STD_LOGIC; AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); AWVALID :in STD_LOGIC; AWREADY :out STD_LOGIC; WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0); WVALID :in STD_LOGIC; WREADY :out STD_LOGIC; BRESP :out STD_LOGIC_VECTOR(1 downto 0); BVALID :out STD_LOGIC; BREADY :in STD_LOGIC; ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); ARVALID :in STD_LOGIC; ARREADY :out STD_LOGIC; RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); RRESP :out STD_LOGIC_VECTOR(1 downto 0); RVALID :out STD_LOGIC; RREADY :in STD_LOGIC; interrupt :out STD_LOGIC; -- user signals ap_start :out STD_LOGIC; ap_done :in STD_LOGIC; ap_ready :in STD_LOGIC; ap_idle :in STD_LOGIC; operation :out STD_LOGIC_VECTOR(31 downto 0); operation_ap_vld :out STD_LOGIC; contact_in_address0 :in STD_LOGIC_VECTOR(5 downto 0); contact_in_ce0 :in STD_LOGIC; contact_in_q0 :out STD_LOGIC_VECTOR(7 downto 0); database_in_address0 :in STD_LOGIC_VECTOR(5 downto 0); database_in_ce0 :in STD_LOGIC; database_in_q0 :out STD_LOGIC_VECTOR(7 downto 0); matched_out_address0 :in STD_LOGIC_VECTOR(12 downto 0); matched_out_ce0 :in STD_LOGIC; matched_out_we0 :in STD_LOGIC; matched_out_d0 :in STD_LOGIC_VECTOR(0 downto 0); matched_finished :in STD_LOGIC_VECTOR(31 downto 0); error_out :in STD_LOGIC_VECTOR(31 downto 0); database_size_out :in STD_LOGIC_VECTOR(31 downto 0); contacts_size_out :in STD_LOGIC_VECTOR(31 downto 0) ); end entity contact_discovery_AXILiteS_s_axi; -- ------------------------Address Info------------------- -- 0x0000 : Control signals -- bit 0 - ap_start (Read/Write/COH) -- bit 1 - ap_done (Read/COR) -- bit 2 - ap_idle (Read) -- bit 3 - ap_ready (Read) -- bit 7 - auto_restart (Read/Write) -- others - reserved -- 0x0004 : Global Interrupt Enable Register -- bit 0 - Global Interrupt Enable (Read/Write) -- others - reserved -- 0x0008 : IP Interrupt Enable Register (Read/Write) -- bit 0 - Channel 0 (ap_done) -- bit 1 - Channel 1 (ap_ready) -- others - reserved -- 0x000c : IP Interrupt Status Register (Read/TOW) -- bit 0 - Channel 0 (ap_done) -- bit 1 - Channel 1 (ap_ready) -- others - reserved -- 0x0010 : Data signal of operation -- bit 31~0 - operation[31:0] (Read/Write) -- 0x0014 : Control signal of operation -- bit 0 - operation_ap_vld (Read/Write/SC) -- others - reserved -- 0x4000 : Data signal of matched_finished -- bit 31~0 - matched_finished[31:0] (Read) -- 0x4004 : reserved -- 0x4008 : Data signal of error_out -- bit 31~0 - error_out[31:0] (Read) -- 0x400c : reserved -- 0x4010 : Data signal of database_size_out -- bit 31~0 - database_size_out[31:0] (Read) -- 0x4014 : reserved -- 0x4018 : Data signal of contacts_size_out -- bit 31~0 - contacts_size_out[31:0] (Read) -- 0x401c : reserved -- 0x0040 ~ -- 0x007f : Memory 'contact_in' (64 * 8b) -- Word n : bit [ 7: 0] - contact_in[4n] -- bit [15: 8] - contact_in[4n+1] -- bit [23:16] - contact_in[4n+2] -- bit [31:24] - contact_in[4n+3] -- 0x0080 ~ -- 0x00bf : Memory 'database_in' (64 * 8b) -- Word n : bit [ 7: 0] - database_in[4n] -- bit [15: 8] - database_in[4n+1] -- bit [23:16] - database_in[4n+2] -- bit [31:24] - database_in[4n+3] -- 0x2000 ~ -- 0x3fff : Memory 'matched_out' (7500 * 1b) -- Word n : bit [ 0: 0] - matched_out[4n] -- bit [ 8: 8] - matched_out[4n+1] -- bit [16:16] - matched_out[4n+2] -- bit [24:24] - matched_out[4n+3] -- others - reserved -- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) architecture behave of contact_discovery_AXILiteS_s_axi is type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states signal wstate : states := wrreset; signal rstate : states := rdreset; signal wnext, rnext: states; constant ADDR_AP_CTRL : INTEGER := 16#0000#; constant ADDR_GIE : INTEGER := 16#0004#; constant ADDR_IER : INTEGER := 16#0008#; constant ADDR_ISR : INTEGER := 16#000c#; constant ADDR_OPERATION_DATA_0 : INTEGER := 16#0010#; constant ADDR_OPERATION_CTRL : INTEGER := 16#0014#; constant ADDR_MATCHED_FINISHED_DATA_0 : INTEGER := 16#4000#; constant ADDR_MATCHED_FINISHED_CTRL : INTEGER := 16#4004#; constant ADDR_ERROR_OUT_DATA_0 : INTEGER := 16#4008#; constant ADDR_ERROR_OUT_CTRL : INTEGER := 16#400c#; constant ADDR_DATABASE_SIZE_OUT_DATA_0 : INTEGER := 16#4010#; constant ADDR_DATABASE_SIZE_OUT_CTRL : INTEGER := 16#4014#; constant ADDR_CONTACTS_SIZE_OUT_DATA_0 : INTEGER := 16#4018#; constant ADDR_CONTACTS_SIZE_OUT_CTRL : INTEGER := 16#401c#; constant ADDR_CONTACT_IN_BASE : INTEGER := 16#0040#; constant ADDR_CONTACT_IN_HIGH : INTEGER := 16#007f#; constant ADDR_DATABASE_IN_BASE : INTEGER := 16#0080#; constant ADDR_DATABASE_IN_HIGH : INTEGER := 16#00bf#; constant ADDR_MATCHED_OUT_BASE : INTEGER := 16#2000#; constant ADDR_MATCHED_OUT_HIGH : INTEGER := 16#3fff#; constant ADDR_BITS : INTEGER := 15; signal waddr : UNSIGNED(ADDR_BITS-1 downto 0); signal wmask : UNSIGNED(31 downto 0); signal aw_hs : STD_LOGIC; signal w_hs : STD_LOGIC; signal rdata_data : UNSIGNED(31 downto 0); signal ar_hs : STD_LOGIC; signal raddr : UNSIGNED(ADDR_BITS-1 downto 0); signal AWREADY_t : STD_LOGIC; signal WREADY_t : STD_LOGIC; signal ARREADY_t : STD_LOGIC; signal RVALID_t : STD_LOGIC; -- internal registers signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_done : STD_LOGIC := '0'; signal int_ap_start : STD_LOGIC := '0'; signal int_auto_restart : STD_LOGIC := '0'; signal int_gie : STD_LOGIC := '0'; signal int_ier : UNSIGNED(1 downto 0) := (others => '0'); signal int_isr : UNSIGNED(1 downto 0) := (others => '0'); signal int_operation : UNSIGNED(31 downto 0) := (others => '0'); signal int_operation_ap_vld : STD_LOGIC := '0'; signal int_matched_finished : UNSIGNED(31 downto 0) := (others => '0'); signal int_error_out : UNSIGNED(31 downto 0) := (others => '0'); signal int_database_size_out : UNSIGNED(31 downto 0) := (others => '0'); signal int_contacts_size_out : UNSIGNED(31 downto 0) := (others => '0'); -- memory signals signal int_contact_in_address0 : UNSIGNED(3 downto 0); signal int_contact_in_ce0 : STD_LOGIC; signal int_contact_in_we0 : STD_LOGIC; signal int_contact_in_be0 : UNSIGNED(3 downto 0); signal int_contact_in_d0 : UNSIGNED(31 downto 0); signal int_contact_in_q0 : UNSIGNED(31 downto 0); signal int_contact_in_address1 : UNSIGNED(3 downto 0); signal int_contact_in_ce1 : STD_LOGIC; signal int_contact_in_we1 : STD_LOGIC; signal int_contact_in_be1 : UNSIGNED(3 downto 0); signal int_contact_in_d1 : UNSIGNED(31 downto 0); signal int_contact_in_q1 : UNSIGNED(31 downto 0); signal int_contact_in_read : STD_LOGIC; signal int_contact_in_write : STD_LOGIC; signal int_contact_in_shift : UNSIGNED(1 downto 0); signal int_database_in_address0 : UNSIGNED(3 downto 0); signal int_database_in_ce0 : STD_LOGIC; signal int_database_in_we0 : STD_LOGIC; signal int_database_in_be0 : UNSIGNED(3 downto 0); signal int_database_in_d0 : UNSIGNED(31 downto 0); signal int_database_in_q0 : UNSIGNED(31 downto 0); signal int_database_in_address1 : UNSIGNED(3 downto 0); signal int_database_in_ce1 : STD_LOGIC; signal int_database_in_we1 : STD_LOGIC; signal int_database_in_be1 : UNSIGNED(3 downto 0); signal int_database_in_d1 : UNSIGNED(31 downto 0); signal int_database_in_q1 : UNSIGNED(31 downto 0); signal int_database_in_read : STD_LOGIC; signal int_database_in_write : STD_LOGIC; signal int_database_in_shift : UNSIGNED(1 downto 0); signal int_matched_out_address0 : UNSIGNED(10 downto 0); signal int_matched_out_ce0 : STD_LOGIC; signal int_matched_out_we0 : STD_LOGIC; signal int_matched_out_be0 : UNSIGNED(3 downto 0); signal int_matched_out_d0 : UNSIGNED(31 downto 0); signal int_matched_out_q0 : UNSIGNED(31 downto 0); signal int_matched_out_address1 : UNSIGNED(10 downto 0); signal int_matched_out_ce1 : STD_LOGIC; signal int_matched_out_we1 : STD_LOGIC; signal int_matched_out_be1 : UNSIGNED(3 downto 0); signal int_matched_out_d1 : UNSIGNED(31 downto 0); signal int_matched_out_q1 : UNSIGNED(31 downto 0); signal int_matched_out_read : STD_LOGIC; signal int_matched_out_write : STD_LOGIC; signal int_matched_out_shift : UNSIGNED(1 downto 0); component contact_discovery_AXILiteS_s_axi_ram is generic ( BYTES : INTEGER :=4; DEPTH : INTEGER :=256; AWIDTH : INTEGER :=8); port ( clk0 : in STD_LOGIC; address0: in UNSIGNED(AWIDTH-1 downto 0); ce0 : in STD_LOGIC; we0 : in STD_LOGIC; be0 : in UNSIGNED(BYTES-1 downto 0); d0 : in UNSIGNED(BYTES*8-1 downto 0); q0 : out UNSIGNED(BYTES*8-1 downto 0); clk1 : in STD_LOGIC; address1: in UNSIGNED(AWIDTH-1 downto 0); ce1 : in STD_LOGIC; we1 : in STD_LOGIC; be1 : in UNSIGNED(BYTES-1 downto 0); d1 : in UNSIGNED(BYTES*8-1 downto 0); q1 : out UNSIGNED(BYTES*8-1 downto 0)); end component contact_discovery_AXILiteS_s_axi_ram; function log2 (x : INTEGER) return INTEGER is variable n, m : INTEGER; begin n := 1; m := 2; while m < x loop n := n + 1; m := m * 2; end loop; return n; end function log2; begin -- ----------------------- Instantiation------------------ -- int_contact_in int_contact_in : contact_discovery_AXILiteS_s_axi_ram generic map ( BYTES => 4, DEPTH => 16, AWIDTH => log2(16)) port map ( clk0 => ACLK, address0 => int_contact_in_address0, ce0 => int_contact_in_ce0, we0 => int_contact_in_we0, be0 => int_contact_in_be0, d0 => int_contact_in_d0, q0 => int_contact_in_q0, clk1 => ACLK, address1 => int_contact_in_address1, ce1 => int_contact_in_ce1, we1 => int_contact_in_we1, be1 => int_contact_in_be1, d1 => int_contact_in_d1, q1 => int_contact_in_q1); -- int_database_in int_database_in : contact_discovery_AXILiteS_s_axi_ram generic map ( BYTES => 4, DEPTH => 16, AWIDTH => log2(16)) port map ( clk0 => ACLK, address0 => int_database_in_address0, ce0 => int_database_in_ce0, we0 => int_database_in_we0, be0 => int_database_in_be0, d0 => int_database_in_d0, q0 => int_database_in_q0, clk1 => ACLK, address1 => int_database_in_address1, ce1 => int_database_in_ce1, we1 => int_database_in_we1, be1 => int_database_in_be1, d1 => int_database_in_d1, q1 => int_database_in_q1); -- int_matched_out int_matched_out : contact_discovery_AXILiteS_s_axi_ram generic map ( BYTES => 4, DEPTH => 1875, AWIDTH => log2(1875)) port map ( clk0 => ACLK, address0 => int_matched_out_address0, ce0 => int_matched_out_ce0, we0 => int_matched_out_we0, be0 => int_matched_out_be0, d0 => int_matched_out_d0, q0 => int_matched_out_q0, clk1 => ACLK, address1 => int_matched_out_address1, ce1 => int_matched_out_ce1, we1 => int_matched_out_we1, be1 => int_matched_out_be1, d1 => int_matched_out_d1, q1 => int_matched_out_q1); -- ----------------------- AXI WRITE --------------------- AWREADY_t <= '1' when wstate = wridle else '0'; AWREADY <= AWREADY_t; WREADY_t <= '1' when wstate = wrdata else '0'; WREADY <= WREADY_t; BRESP <= "00"; -- OKAY BVALID <= '1' when wstate = wrresp else '0'; wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0)); aw_hs <= AWVALID and AWREADY_t; w_hs <= WVALID and WREADY_t; -- write FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then wstate <= wrreset; elsif (ACLK_EN = '1') then wstate <= wnext; end if; end if; end process; process (wstate, AWVALID, WVALID, BREADY) begin case (wstate) is when wridle => if (AWVALID = '1') then wnext <= wrdata; else wnext <= wridle; end if; when wrdata => if (WVALID = '1') then wnext <= wrresp; else wnext <= wrdata; end if; when wrresp => if (BREADY = '1') then wnext <= wridle; else wnext <= wrresp; end if; when others => wnext <= wridle; end case; end process; waddr_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (aw_hs = '1') then waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)); end if; end if; end if; end process; -- ----------------------- AXI READ ---------------------- ARREADY_t <= '1' when (rstate = rdidle) else '0'; ARREADY <= ARREADY_t; RDATA <= STD_LOGIC_VECTOR(rdata_data); RRESP <= "00"; -- OKAY RVALID_t <= '1' when (rstate = rddata) and (int_contact_in_read = '0') and (int_database_in_read = '0') and (int_matched_out_read = '0') else '0'; RVALID <= RVALID_t; ar_hs <= ARVALID and ARREADY_t; raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0)); -- read FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then rstate <= rdreset; elsif (ACLK_EN = '1') then rstate <= rnext; end if; end if; end process; process (rstate, ARVALID, RREADY, RVALID_t) begin case (rstate) is when rdidle => if (ARVALID = '1') then rnext <= rddata; else rnext <= rdidle; end if; when rddata => if (RREADY = '1' and RVALID_t = '1') then rnext <= rdidle; else rnext <= rddata; end if; when others => rnext <= rdidle; end case; end process; rdata_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (ar_hs = '1') then case (TO_INTEGER(raddr)) is when ADDR_AP_CTRL => rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0'); when ADDR_GIE => rdata_data <= (0 => int_gie, others => '0'); when ADDR_IER => rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0'); when ADDR_ISR => rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0'); when ADDR_OPERATION_DATA_0 => rdata_data <= RESIZE(int_operation(31 downto 0), 32); when ADDR_OPERATION_CTRL => rdata_data <= (0 => int_operation_ap_vld, others => '0'); when ADDR_MATCHED_FINISHED_DATA_0 => rdata_data <= RESIZE(int_matched_finished(31 downto 0), 32); when ADDR_ERROR_OUT_DATA_0 => rdata_data <= RESIZE(int_error_out(31 downto 0), 32); when ADDR_DATABASE_SIZE_OUT_DATA_0 => rdata_data <= RESIZE(int_database_size_out(31 downto 0), 32); when ADDR_CONTACTS_SIZE_OUT_DATA_0 => rdata_data <= RESIZE(int_contacts_size_out(31 downto 0), 32); when others => rdata_data <= (others => '0'); end case; elsif (int_contact_in_read = '1') then rdata_data <= int_contact_in_q1; elsif (int_database_in_read = '1') then rdata_data <= int_database_in_q1; elsif (int_matched_out_read = '1') then rdata_data <= int_matched_out_q1; end if; end if; end if; end process; -- ----------------------- Register logic ---------------- interrupt <= int_gie and (int_isr(0) or int_isr(1)); ap_start <= int_ap_start; int_ap_idle <= ap_idle; int_ap_ready <= ap_ready; operation <= STD_LOGIC_VECTOR(int_operation); operation_ap_vld <= int_operation_ap_vld; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_start <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_ap_start <= '1'; elsif (int_ap_ready = '1') then int_ap_start <= int_auto_restart; -- clear on handshake/auto restart end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_done <= '0'; elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_done <= '1'; elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then int_ap_done <= '0'; -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_auto_restart <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then int_auto_restart <= WDATA(7); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_gie <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then int_gie <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ier <= "00"; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then int_ier <= UNSIGNED(WDATA(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(0) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(0) = '1' and ap_done = '1') then int_isr(0) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(1) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(1) = '1' and ap_ready = '1') then int_isr(1) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_OPERATION_DATA_0) then int_operation(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_operation(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_operation_ap_vld <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_OPERATION_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_operation_ap_vld <= '1'; else int_operation_ap_vld <= '0'; -- self clear end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_matched_finished <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_matched_finished <= UNSIGNED(matched_finished); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_error_out <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_error_out <= UNSIGNED(error_out); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_database_size_out <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_database_size_out <= UNSIGNED(database_size_out); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_contacts_size_out <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_contacts_size_out <= UNSIGNED(contacts_size_out); -- clear on read end if; end if; end if; end process; -- ----------------------- Memory logic ------------------ -- contact_in int_contact_in_address0 <= SHIFT_RIGHT(UNSIGNED(contact_in_address0), 2)(3 downto 0); int_contact_in_ce0 <= contact_in_ce0; int_contact_in_we0 <= '0'; int_contact_in_be0 <= (others => '0'); int_contact_in_d0 <= (others => '0'); contact_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_contact_in_q0, TO_INTEGER(int_contact_in_shift) * 8)(7 downto 0)); int_contact_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2); int_contact_in_ce1 <= '1' when ar_hs = '1' or (int_contact_in_write = '1' and WVALID = '1') else '0'; int_contact_in_we1 <= '1' when int_contact_in_write = '1' and WVALID = '1' else '0'; int_contact_in_be1 <= UNSIGNED(WSTRB); int_contact_in_d1 <= UNSIGNED(WDATA); -- database_in int_database_in_address0 <= SHIFT_RIGHT(UNSIGNED(database_in_address0), 2)(3 downto 0); int_database_in_ce0 <= database_in_ce0; int_database_in_we0 <= '0'; int_database_in_be0 <= (others => '0'); int_database_in_d0 <= (others => '0'); database_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_database_in_q0, TO_INTEGER(int_database_in_shift) * 8)(7 downto 0)); int_database_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2); int_database_in_ce1 <= '1' when ar_hs = '1' or (int_database_in_write = '1' and WVALID = '1') else '0'; int_database_in_we1 <= '1' when int_database_in_write = '1' and WVALID = '1' else '0'; int_database_in_be1 <= UNSIGNED(WSTRB); int_database_in_d1 <= UNSIGNED(WDATA); -- matched_out int_matched_out_address0 <= SHIFT_RIGHT(UNSIGNED(matched_out_address0), 2)(10 downto 0); int_matched_out_ce0 <= matched_out_ce0; int_matched_out_we0 <= matched_out_we0; int_matched_out_be0 <= SHIFT_LEFT(TO_UNSIGNED(1, 4), TO_INTEGER(UNSIGNED(matched_out_address0(1 downto 0)))); int_matched_out_d0 <= UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)); int_matched_out_address1 <= raddr(12 downto 2) when ar_hs = '1' else waddr(12 downto 2); int_matched_out_ce1 <= '1' when ar_hs = '1' or (int_matched_out_write = '1' and WVALID = '1') else '0'; int_matched_out_we1 <= '1' when int_matched_out_write = '1' and WVALID = '1' else '0'; int_matched_out_be1 <= UNSIGNED(WSTRB); int_matched_out_d1 <= UNSIGNED(WDATA); process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_contact_in_read <= '0'; elsif (ACLK_EN = '1') then if (ar_hs = '1' and raddr >= ADDR_CONTACT_IN_BASE and raddr <= ADDR_CONTACT_IN_HIGH) then int_contact_in_read <= '1'; else int_contact_in_read <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_contact_in_write <= '0'; elsif (ACLK_EN = '1') then if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_CONTACT_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_CONTACT_IN_HIGH) then int_contact_in_write <= '1'; elsif (WVALID = '1') then int_contact_in_write <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (contact_in_ce0 = '1') then int_contact_in_shift <= UNSIGNED(contact_in_address0(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_database_in_read <= '0'; elsif (ACLK_EN = '1') then if (ar_hs = '1' and raddr >= ADDR_DATABASE_IN_BASE and raddr <= ADDR_DATABASE_IN_HIGH) then int_database_in_read <= '1'; else int_database_in_read <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_database_in_write <= '0'; elsif (ACLK_EN = '1') then if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_DATABASE_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_DATABASE_IN_HIGH) then int_database_in_write <= '1'; elsif (WVALID = '1') then int_database_in_write <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (database_in_ce0 = '1') then int_database_in_shift <= UNSIGNED(database_in_address0(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_matched_out_read <= '0'; elsif (ACLK_EN = '1') then if (ar_hs = '1' and raddr >= ADDR_MATCHED_OUT_BASE and raddr <= ADDR_MATCHED_OUT_HIGH) then int_matched_out_read <= '1'; else int_matched_out_read <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_matched_out_write <= '0'; elsif (ACLK_EN = '1') then if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_MATCHED_OUT_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_MATCHED_OUT_HIGH) then int_matched_out_write <= '1'; elsif (WVALID = '1') then int_matched_out_write <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (matched_out_ce0 = '1') then int_matched_out_shift <= UNSIGNED(matched_out_address0(1 downto 0)); end if; end if; end if; end process; end architecture behave; library IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all; entity contact_discovery_AXILiteS_s_axi_ram is generic ( BYTES : INTEGER :=4; DEPTH : INTEGER :=256; AWIDTH : INTEGER :=8); port ( clk0 : in STD_LOGIC; address0: in UNSIGNED(AWIDTH-1 downto 0); ce0 : in STD_LOGIC; we0 : in STD_LOGIC; be0 : in UNSIGNED(BYTES-1 downto 0); d0 : in UNSIGNED(BYTES*8-1 downto 0); q0 : out UNSIGNED(BYTES*8-1 downto 0); clk1 : in STD_LOGIC; address1: in UNSIGNED(AWIDTH-1 downto 0); ce1 : in STD_LOGIC; we1 : in STD_LOGIC; be1 : in UNSIGNED(BYTES-1 downto 0); d1 : in UNSIGNED(BYTES*8-1 downto 0); q1 : out UNSIGNED(BYTES*8-1 downto 0)); end entity contact_discovery_AXILiteS_s_axi_ram; architecture behave of contact_discovery_AXILiteS_s_axi_ram is signal address0_tmp : UNSIGNED(AWIDTH-1 downto 0); signal address1_tmp : UNSIGNED(AWIDTH-1 downto 0); type RAM_T is array (0 to DEPTH - 1) of UNSIGNED(BYTES*8 - 1 downto 0); shared variable mem : RAM_T := (others => (others => '0')); begin process (address0) begin address0_tmp <= address0; --synthesis translate_off if (address0 > DEPTH-1) then address0_tmp <= (others => '0'); else address0_tmp <= address0; end if; --synthesis translate_on end process; process (address1) begin address1_tmp <= address1; --synthesis translate_off if (address1 > DEPTH-1) then address1_tmp <= (others => '0'); else address1_tmp <= address1; end if; --synthesis translate_on end process; --read port 0 process (clk0) begin if (clk0'event and clk0 = '1') then if (ce0 = '1') then q0 <= mem(to_integer(address0_tmp)); end if; end if; end process; --read port 1 process (clk1) begin if (clk1'event and clk1 = '1') then if (ce1 = '1') then q1 <= mem(to_integer(address1_tmp)); end if; end if; end process; gen_write : for i in 0 to BYTES - 1 generate begin --write port 0 process (clk0) begin if (clk0'event and clk0 = '1') then if (ce0 = '1' and we0 = '1' and be0(i) = '1') then mem(to_integer(address0_tmp))(8*i+7 downto 8*i) := d0(8*i+7 downto 8*i); end if; end if; end process; --write port 1 process (clk1) begin if (clk1'event and clk1 = '1') then if (ce1 = '1' and we1 = '1' and be1(i) = '1') then mem(to_integer(address1_tmp))(8*i+7 downto 8*i) := d1(8*i+7 downto 8*i); end if; end if; end process; end generate; end architecture behave;
gpl-3.0
mcoughli/root_of_trust
operational_os/hls/contact_discovery_axi/solution1/impl/ip/hdl/vhdl/contact_discovery_AXILiteS_s_axi.vhd
3
34912
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity contact_discovery_AXILiteS_s_axi is generic ( C_S_AXI_ADDR_WIDTH : INTEGER := 11; C_S_AXI_DATA_WIDTH : INTEGER := 32); port ( -- axi4 lite slave signals ACLK :in STD_LOGIC; ARESET :in STD_LOGIC; ACLK_EN :in STD_LOGIC; AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); AWVALID :in STD_LOGIC; AWREADY :out STD_LOGIC; WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0); WVALID :in STD_LOGIC; WREADY :out STD_LOGIC; BRESP :out STD_LOGIC_VECTOR(1 downto 0); BVALID :out STD_LOGIC; BREADY :in STD_LOGIC; ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); ARVALID :in STD_LOGIC; ARREADY :out STD_LOGIC; RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); RRESP :out STD_LOGIC_VECTOR(1 downto 0); RVALID :out STD_LOGIC; RREADY :in STD_LOGIC; interrupt :out STD_LOGIC; -- user signals ap_start :out STD_LOGIC; ap_done :in STD_LOGIC; ap_ready :in STD_LOGIC; ap_idle :in STD_LOGIC; operation :out STD_LOGIC_VECTOR(31 downto 0); operation_ap_vld :out STD_LOGIC; contact_in_address0 :in STD_LOGIC_VECTOR(5 downto 0); contact_in_ce0 :in STD_LOGIC; contact_in_q0 :out STD_LOGIC_VECTOR(7 downto 0); database_in_address0 :in STD_LOGIC_VECTOR(5 downto 0); database_in_ce0 :in STD_LOGIC; database_in_q0 :out STD_LOGIC_VECTOR(7 downto 0); matched_out_address0 :in STD_LOGIC_VECTOR(8 downto 0); matched_out_ce0 :in STD_LOGIC; matched_out_we0 :in STD_LOGIC; matched_out_d0 :in STD_LOGIC_VECTOR(0 downto 0); matched_finished :in STD_LOGIC_VECTOR(31 downto 0); error_out :in STD_LOGIC_VECTOR(31 downto 0); database_size_out :in STD_LOGIC_VECTOR(31 downto 0); contacts_size_out :in STD_LOGIC_VECTOR(31 downto 0) ); end entity contact_discovery_AXILiteS_s_axi; -- ------------------------Address Info------------------- -- 0x000 : Control signals -- bit 0 - ap_start (Read/Write/COH) -- bit 1 - ap_done (Read/COR) -- bit 2 - ap_idle (Read) -- bit 3 - ap_ready (Read) -- bit 7 - auto_restart (Read/Write) -- others - reserved -- 0x004 : Global Interrupt Enable Register -- bit 0 - Global Interrupt Enable (Read/Write) -- others - reserved -- 0x008 : IP Interrupt Enable Register (Read/Write) -- bit 0 - Channel 0 (ap_done) -- bit 1 - Channel 1 (ap_ready) -- others - reserved -- 0x00c : IP Interrupt Status Register (Read/TOW) -- bit 0 - Channel 0 (ap_done) -- bit 1 - Channel 1 (ap_ready) -- others - reserved -- 0x010 : Data signal of operation -- bit 31~0 - operation[31:0] (Read/Write) -- 0x014 : Control signal of operation -- bit 0 - operation_ap_vld (Read/Write/SC) -- others - reserved -- 0x400 : Data signal of matched_finished -- bit 31~0 - matched_finished[31:0] (Read) -- 0x404 : reserved -- 0x408 : Data signal of error_out -- bit 31~0 - error_out[31:0] (Read) -- 0x40c : reserved -- 0x410 : Data signal of database_size_out -- bit 31~0 - database_size_out[31:0] (Read) -- 0x414 : reserved -- 0x418 : Data signal of contacts_size_out -- bit 31~0 - contacts_size_out[31:0] (Read) -- 0x41c : reserved -- 0x040 ~ -- 0x07f : Memory 'contact_in' (64 * 8b) -- Word n : bit [ 7: 0] - contact_in[4n] -- bit [15: 8] - contact_in[4n+1] -- bit [23:16] - contact_in[4n+2] -- bit [31:24] - contact_in[4n+3] -- 0x080 ~ -- 0x0bf : Memory 'database_in' (64 * 8b) -- Word n : bit [ 7: 0] - database_in[4n] -- bit [15: 8] - database_in[4n+1] -- bit [23:16] - database_in[4n+2] -- bit [31:24] - database_in[4n+3] -- 0x200 ~ -- 0x3ff : Memory 'matched_out' (300 * 1b) -- Word n : bit [ 0: 0] - matched_out[4n] -- bit [ 8: 8] - matched_out[4n+1] -- bit [16:16] - matched_out[4n+2] -- bit [24:24] - matched_out[4n+3] -- others - reserved -- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) architecture behave of contact_discovery_AXILiteS_s_axi is type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states signal wstate : states := wrreset; signal rstate : states := rdreset; signal wnext, rnext: states; constant ADDR_AP_CTRL : INTEGER := 16#000#; constant ADDR_GIE : INTEGER := 16#004#; constant ADDR_IER : INTEGER := 16#008#; constant ADDR_ISR : INTEGER := 16#00c#; constant ADDR_OPERATION_DATA_0 : INTEGER := 16#010#; constant ADDR_OPERATION_CTRL : INTEGER := 16#014#; constant ADDR_MATCHED_FINISHED_DATA_0 : INTEGER := 16#400#; constant ADDR_MATCHED_FINISHED_CTRL : INTEGER := 16#404#; constant ADDR_ERROR_OUT_DATA_0 : INTEGER := 16#408#; constant ADDR_ERROR_OUT_CTRL : INTEGER := 16#40c#; constant ADDR_DATABASE_SIZE_OUT_DATA_0 : INTEGER := 16#410#; constant ADDR_DATABASE_SIZE_OUT_CTRL : INTEGER := 16#414#; constant ADDR_CONTACTS_SIZE_OUT_DATA_0 : INTEGER := 16#418#; constant ADDR_CONTACTS_SIZE_OUT_CTRL : INTEGER := 16#41c#; constant ADDR_CONTACT_IN_BASE : INTEGER := 16#040#; constant ADDR_CONTACT_IN_HIGH : INTEGER := 16#07f#; constant ADDR_DATABASE_IN_BASE : INTEGER := 16#080#; constant ADDR_DATABASE_IN_HIGH : INTEGER := 16#0bf#; constant ADDR_MATCHED_OUT_BASE : INTEGER := 16#200#; constant ADDR_MATCHED_OUT_HIGH : INTEGER := 16#3ff#; constant ADDR_BITS : INTEGER := 11; signal waddr : UNSIGNED(ADDR_BITS-1 downto 0); signal wmask : UNSIGNED(31 downto 0); signal aw_hs : STD_LOGIC; signal w_hs : STD_LOGIC; signal rdata_data : UNSIGNED(31 downto 0); signal ar_hs : STD_LOGIC; signal raddr : UNSIGNED(ADDR_BITS-1 downto 0); signal AWREADY_t : STD_LOGIC; signal WREADY_t : STD_LOGIC; signal ARREADY_t : STD_LOGIC; signal RVALID_t : STD_LOGIC; -- internal registers signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_done : STD_LOGIC := '0'; signal int_ap_start : STD_LOGIC := '0'; signal int_auto_restart : STD_LOGIC := '0'; signal int_gie : STD_LOGIC := '0'; signal int_ier : UNSIGNED(1 downto 0) := (others => '0'); signal int_isr : UNSIGNED(1 downto 0) := (others => '0'); signal int_operation : UNSIGNED(31 downto 0) := (others => '0'); signal int_operation_ap_vld : STD_LOGIC := '0'; signal int_matched_finished : UNSIGNED(31 downto 0) := (others => '0'); signal int_error_out : UNSIGNED(31 downto 0) := (others => '0'); signal int_database_size_out : UNSIGNED(31 downto 0) := (others => '0'); signal int_contacts_size_out : UNSIGNED(31 downto 0) := (others => '0'); -- memory signals signal int_contact_in_address0 : UNSIGNED(3 downto 0); signal int_contact_in_ce0 : STD_LOGIC; signal int_contact_in_we0 : STD_LOGIC; signal int_contact_in_be0 : UNSIGNED(3 downto 0); signal int_contact_in_d0 : UNSIGNED(31 downto 0); signal int_contact_in_q0 : UNSIGNED(31 downto 0); signal int_contact_in_address1 : UNSIGNED(3 downto 0); signal int_contact_in_ce1 : STD_LOGIC; signal int_contact_in_we1 : STD_LOGIC; signal int_contact_in_be1 : UNSIGNED(3 downto 0); signal int_contact_in_d1 : UNSIGNED(31 downto 0); signal int_contact_in_q1 : UNSIGNED(31 downto 0); signal int_contact_in_read : STD_LOGIC; signal int_contact_in_write : STD_LOGIC; signal int_contact_in_shift : UNSIGNED(1 downto 0); signal int_database_in_address0 : UNSIGNED(3 downto 0); signal int_database_in_ce0 : STD_LOGIC; signal int_database_in_we0 : STD_LOGIC; signal int_database_in_be0 : UNSIGNED(3 downto 0); signal int_database_in_d0 : UNSIGNED(31 downto 0); signal int_database_in_q0 : UNSIGNED(31 downto 0); signal int_database_in_address1 : UNSIGNED(3 downto 0); signal int_database_in_ce1 : STD_LOGIC; signal int_database_in_we1 : STD_LOGIC; signal int_database_in_be1 : UNSIGNED(3 downto 0); signal int_database_in_d1 : UNSIGNED(31 downto 0); signal int_database_in_q1 : UNSIGNED(31 downto 0); signal int_database_in_read : STD_LOGIC; signal int_database_in_write : STD_LOGIC; signal int_database_in_shift : UNSIGNED(1 downto 0); signal int_matched_out_address0 : UNSIGNED(6 downto 0); signal int_matched_out_ce0 : STD_LOGIC; signal int_matched_out_we0 : STD_LOGIC; signal int_matched_out_be0 : UNSIGNED(3 downto 0); signal int_matched_out_d0 : UNSIGNED(31 downto 0); signal int_matched_out_q0 : UNSIGNED(31 downto 0); signal int_matched_out_address1 : UNSIGNED(6 downto 0); signal int_matched_out_ce1 : STD_LOGIC; signal int_matched_out_we1 : STD_LOGIC; signal int_matched_out_be1 : UNSIGNED(3 downto 0); signal int_matched_out_d1 : UNSIGNED(31 downto 0); signal int_matched_out_q1 : UNSIGNED(31 downto 0); signal int_matched_out_read : STD_LOGIC; signal int_matched_out_write : STD_LOGIC; signal int_matched_out_shift : UNSIGNED(1 downto 0); component contact_discovery_AXILiteS_s_axi_ram is generic ( BYTES : INTEGER :=4; DEPTH : INTEGER :=256; AWIDTH : INTEGER :=8); port ( clk0 : in STD_LOGIC; address0: in UNSIGNED(AWIDTH-1 downto 0); ce0 : in STD_LOGIC; we0 : in STD_LOGIC; be0 : in UNSIGNED(BYTES-1 downto 0); d0 : in UNSIGNED(BYTES*8-1 downto 0); q0 : out UNSIGNED(BYTES*8-1 downto 0); clk1 : in STD_LOGIC; address1: in UNSIGNED(AWIDTH-1 downto 0); ce1 : in STD_LOGIC; we1 : in STD_LOGIC; be1 : in UNSIGNED(BYTES-1 downto 0); d1 : in UNSIGNED(BYTES*8-1 downto 0); q1 : out UNSIGNED(BYTES*8-1 downto 0)); end component contact_discovery_AXILiteS_s_axi_ram; function log2 (x : INTEGER) return INTEGER is variable n, m : INTEGER; begin n := 1; m := 2; while m < x loop n := n + 1; m := m * 2; end loop; return n; end function log2; begin -- ----------------------- Instantiation------------------ -- int_contact_in int_contact_in : contact_discovery_AXILiteS_s_axi_ram generic map ( BYTES => 4, DEPTH => 16, AWIDTH => log2(16)) port map ( clk0 => ACLK, address0 => int_contact_in_address0, ce0 => int_contact_in_ce0, we0 => int_contact_in_we0, be0 => int_contact_in_be0, d0 => int_contact_in_d0, q0 => int_contact_in_q0, clk1 => ACLK, address1 => int_contact_in_address1, ce1 => int_contact_in_ce1, we1 => int_contact_in_we1, be1 => int_contact_in_be1, d1 => int_contact_in_d1, q1 => int_contact_in_q1); -- int_database_in int_database_in : contact_discovery_AXILiteS_s_axi_ram generic map ( BYTES => 4, DEPTH => 16, AWIDTH => log2(16)) port map ( clk0 => ACLK, address0 => int_database_in_address0, ce0 => int_database_in_ce0, we0 => int_database_in_we0, be0 => int_database_in_be0, d0 => int_database_in_d0, q0 => int_database_in_q0, clk1 => ACLK, address1 => int_database_in_address1, ce1 => int_database_in_ce1, we1 => int_database_in_we1, be1 => int_database_in_be1, d1 => int_database_in_d1, q1 => int_database_in_q1); -- int_matched_out int_matched_out : contact_discovery_AXILiteS_s_axi_ram generic map ( BYTES => 4, DEPTH => 75, AWIDTH => log2(75)) port map ( clk0 => ACLK, address0 => int_matched_out_address0, ce0 => int_matched_out_ce0, we0 => int_matched_out_we0, be0 => int_matched_out_be0, d0 => int_matched_out_d0, q0 => int_matched_out_q0, clk1 => ACLK, address1 => int_matched_out_address1, ce1 => int_matched_out_ce1, we1 => int_matched_out_we1, be1 => int_matched_out_be1, d1 => int_matched_out_d1, q1 => int_matched_out_q1); -- ----------------------- AXI WRITE --------------------- AWREADY_t <= '1' when wstate = wridle else '0'; AWREADY <= AWREADY_t; WREADY_t <= '1' when wstate = wrdata else '0'; WREADY <= WREADY_t; BRESP <= "00"; -- OKAY BVALID <= '1' when wstate = wrresp else '0'; wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0)); aw_hs <= AWVALID and AWREADY_t; w_hs <= WVALID and WREADY_t; -- write FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then wstate <= wrreset; elsif (ACLK_EN = '1') then wstate <= wnext; end if; end if; end process; process (wstate, AWVALID, WVALID, BREADY) begin case (wstate) is when wridle => if (AWVALID = '1') then wnext <= wrdata; else wnext <= wridle; end if; when wrdata => if (WVALID = '1') then wnext <= wrresp; else wnext <= wrdata; end if; when wrresp => if (BREADY = '1') then wnext <= wridle; else wnext <= wrresp; end if; when others => wnext <= wridle; end case; end process; waddr_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (aw_hs = '1') then waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)); end if; end if; end if; end process; -- ----------------------- AXI READ ---------------------- ARREADY_t <= '1' when (rstate = rdidle) else '0'; ARREADY <= ARREADY_t; RDATA <= STD_LOGIC_VECTOR(rdata_data); RRESP <= "00"; -- OKAY RVALID_t <= '1' when (rstate = rddata) and (int_contact_in_read = '0') and (int_database_in_read = '0') and (int_matched_out_read = '0') else '0'; RVALID <= RVALID_t; ar_hs <= ARVALID and ARREADY_t; raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0)); -- read FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then rstate <= rdreset; elsif (ACLK_EN = '1') then rstate <= rnext; end if; end if; end process; process (rstate, ARVALID, RREADY, RVALID_t) begin case (rstate) is when rdidle => if (ARVALID = '1') then rnext <= rddata; else rnext <= rdidle; end if; when rddata => if (RREADY = '1' and RVALID_t = '1') then rnext <= rdidle; else rnext <= rddata; end if; when others => rnext <= rdidle; end case; end process; rdata_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (ar_hs = '1') then case (TO_INTEGER(raddr)) is when ADDR_AP_CTRL => rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0'); when ADDR_GIE => rdata_data <= (0 => int_gie, others => '0'); when ADDR_IER => rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0'); when ADDR_ISR => rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0'); when ADDR_OPERATION_DATA_0 => rdata_data <= RESIZE(int_operation(31 downto 0), 32); when ADDR_OPERATION_CTRL => rdata_data <= (0 => int_operation_ap_vld, others => '0'); when ADDR_MATCHED_FINISHED_DATA_0 => rdata_data <= RESIZE(int_matched_finished(31 downto 0), 32); when ADDR_ERROR_OUT_DATA_0 => rdata_data <= RESIZE(int_error_out(31 downto 0), 32); when ADDR_DATABASE_SIZE_OUT_DATA_0 => rdata_data <= RESIZE(int_database_size_out(31 downto 0), 32); when ADDR_CONTACTS_SIZE_OUT_DATA_0 => rdata_data <= RESIZE(int_contacts_size_out(31 downto 0), 32); when others => rdata_data <= (others => '0'); end case; elsif (int_contact_in_read = '1') then rdata_data <= int_contact_in_q1; elsif (int_database_in_read = '1') then rdata_data <= int_database_in_q1; elsif (int_matched_out_read = '1') then rdata_data <= int_matched_out_q1; end if; end if; end if; end process; -- ----------------------- Register logic ---------------- interrupt <= int_gie and (int_isr(0) or int_isr(1)); ap_start <= int_ap_start; int_ap_idle <= ap_idle; int_ap_ready <= ap_ready; operation <= STD_LOGIC_VECTOR(int_operation); operation_ap_vld <= int_operation_ap_vld; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_start <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_ap_start <= '1'; elsif (int_ap_ready = '1') then int_ap_start <= int_auto_restart; -- clear on handshake/auto restart end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_done <= '0'; elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_done <= '1'; elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then int_ap_done <= '0'; -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_auto_restart <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then int_auto_restart <= WDATA(7); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_gie <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then int_gie <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ier <= "00"; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then int_ier <= UNSIGNED(WDATA(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(0) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(0) = '1' and ap_done = '1') then int_isr(0) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(1) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(1) = '1' and ap_ready = '1') then int_isr(1) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_OPERATION_DATA_0) then int_operation(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_operation(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_operation_ap_vld <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_OPERATION_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_operation_ap_vld <= '1'; else int_operation_ap_vld <= '0'; -- self clear end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_matched_finished <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_matched_finished <= UNSIGNED(matched_finished); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_error_out <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_error_out <= UNSIGNED(error_out); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_database_size_out <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_database_size_out <= UNSIGNED(database_size_out); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_contacts_size_out <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_contacts_size_out <= UNSIGNED(contacts_size_out); -- clear on read end if; end if; end if; end process; -- ----------------------- Memory logic ------------------ -- contact_in int_contact_in_address0 <= SHIFT_RIGHT(UNSIGNED(contact_in_address0), 2)(3 downto 0); int_contact_in_ce0 <= contact_in_ce0; int_contact_in_we0 <= '0'; int_contact_in_be0 <= (others => '0'); int_contact_in_d0 <= (others => '0'); contact_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_contact_in_q0, TO_INTEGER(int_contact_in_shift) * 8)(7 downto 0)); int_contact_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2); int_contact_in_ce1 <= '1' when ar_hs = '1' or (int_contact_in_write = '1' and WVALID = '1') else '0'; int_contact_in_we1 <= '1' when int_contact_in_write = '1' and WVALID = '1' else '0'; int_contact_in_be1 <= UNSIGNED(WSTRB); int_contact_in_d1 <= UNSIGNED(WDATA); -- database_in int_database_in_address0 <= SHIFT_RIGHT(UNSIGNED(database_in_address0), 2)(3 downto 0); int_database_in_ce0 <= database_in_ce0; int_database_in_we0 <= '0'; int_database_in_be0 <= (others => '0'); int_database_in_d0 <= (others => '0'); database_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_database_in_q0, TO_INTEGER(int_database_in_shift) * 8)(7 downto 0)); int_database_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2); int_database_in_ce1 <= '1' when ar_hs = '1' or (int_database_in_write = '1' and WVALID = '1') else '0'; int_database_in_we1 <= '1' when int_database_in_write = '1' and WVALID = '1' else '0'; int_database_in_be1 <= UNSIGNED(WSTRB); int_database_in_d1 <= UNSIGNED(WDATA); -- matched_out int_matched_out_address0 <= SHIFT_RIGHT(UNSIGNED(matched_out_address0), 2)(6 downto 0); int_matched_out_ce0 <= matched_out_ce0; int_matched_out_we0 <= matched_out_we0; int_matched_out_be0 <= SHIFT_LEFT(TO_UNSIGNED(1, 4), TO_INTEGER(UNSIGNED(matched_out_address0(1 downto 0)))); int_matched_out_d0 <= UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)); int_matched_out_address1 <= raddr(8 downto 2) when ar_hs = '1' else waddr(8 downto 2); int_matched_out_ce1 <= '1' when ar_hs = '1' or (int_matched_out_write = '1' and WVALID = '1') else '0'; int_matched_out_we1 <= '1' when int_matched_out_write = '1' and WVALID = '1' else '0'; int_matched_out_be1 <= UNSIGNED(WSTRB); int_matched_out_d1 <= UNSIGNED(WDATA); process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_contact_in_read <= '0'; elsif (ACLK_EN = '1') then if (ar_hs = '1' and raddr >= ADDR_CONTACT_IN_BASE and raddr <= ADDR_CONTACT_IN_HIGH) then int_contact_in_read <= '1'; else int_contact_in_read <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_contact_in_write <= '0'; elsif (ACLK_EN = '1') then if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_CONTACT_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_CONTACT_IN_HIGH) then int_contact_in_write <= '1'; elsif (WVALID = '1') then int_contact_in_write <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (contact_in_ce0 = '1') then int_contact_in_shift <= UNSIGNED(contact_in_address0(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_database_in_read <= '0'; elsif (ACLK_EN = '1') then if (ar_hs = '1' and raddr >= ADDR_DATABASE_IN_BASE and raddr <= ADDR_DATABASE_IN_HIGH) then int_database_in_read <= '1'; else int_database_in_read <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_database_in_write <= '0'; elsif (ACLK_EN = '1') then if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_DATABASE_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_DATABASE_IN_HIGH) then int_database_in_write <= '1'; elsif (WVALID = '1') then int_database_in_write <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (database_in_ce0 = '1') then int_database_in_shift <= UNSIGNED(database_in_address0(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_matched_out_read <= '0'; elsif (ACLK_EN = '1') then if (ar_hs = '1' and raddr >= ADDR_MATCHED_OUT_BASE and raddr <= ADDR_MATCHED_OUT_HIGH) then int_matched_out_read <= '1'; else int_matched_out_read <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_matched_out_write <= '0'; elsif (ACLK_EN = '1') then if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_MATCHED_OUT_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_MATCHED_OUT_HIGH) then int_matched_out_write <= '1'; elsif (WVALID = '1') then int_matched_out_write <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (matched_out_ce0 = '1') then int_matched_out_shift <= UNSIGNED(matched_out_address0(1 downto 0)); end if; end if; end if; end process; end architecture behave; library IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all; entity contact_discovery_AXILiteS_s_axi_ram is generic ( BYTES : INTEGER :=4; DEPTH : INTEGER :=256; AWIDTH : INTEGER :=8); port ( clk0 : in STD_LOGIC; address0: in UNSIGNED(AWIDTH-1 downto 0); ce0 : in STD_LOGIC; we0 : in STD_LOGIC; be0 : in UNSIGNED(BYTES-1 downto 0); d0 : in UNSIGNED(BYTES*8-1 downto 0); q0 : out UNSIGNED(BYTES*8-1 downto 0); clk1 : in STD_LOGIC; address1: in UNSIGNED(AWIDTH-1 downto 0); ce1 : in STD_LOGIC; we1 : in STD_LOGIC; be1 : in UNSIGNED(BYTES-1 downto 0); d1 : in UNSIGNED(BYTES*8-1 downto 0); q1 : out UNSIGNED(BYTES*8-1 downto 0)); end entity contact_discovery_AXILiteS_s_axi_ram; architecture behave of contact_discovery_AXILiteS_s_axi_ram is signal address0_tmp : UNSIGNED(AWIDTH-1 downto 0); signal address1_tmp : UNSIGNED(AWIDTH-1 downto 0); type RAM_T is array (0 to DEPTH - 1) of UNSIGNED(BYTES*8 - 1 downto 0); shared variable mem : RAM_T := (others => (others => '0')); begin process (address0) begin address0_tmp <= address0; --synthesis translate_off if (address0 > DEPTH-1) then address0_tmp <= (others => '0'); else address0_tmp <= address0; end if; --synthesis translate_on end process; process (address1) begin address1_tmp <= address1; --synthesis translate_off if (address1 > DEPTH-1) then address1_tmp <= (others => '0'); else address1_tmp <= address1; end if; --synthesis translate_on end process; --read port 0 process (clk0) begin if (clk0'event and clk0 = '1') then if (ce0 = '1') then q0 <= mem(to_integer(address0_tmp)); end if; end if; end process; --read port 1 process (clk1) begin if (clk1'event and clk1 = '1') then if (ce1 = '1') then q1 <= mem(to_integer(address1_tmp)); end if; end if; end process; gen_write : for i in 0 to BYTES - 1 generate begin --write port 0 process (clk0) begin if (clk0'event and clk0 = '1') then if (ce0 = '1' and we0 = '1' and be0(i) = '1') then mem(to_integer(address0_tmp))(8*i+7 downto 8*i) := d0(8*i+7 downto 8*i); end if; end if; end process; --write port 1 process (clk1) begin if (clk1'event and clk1 = '1') then if (ce1 = '1' and we1 = '1' and be1(i) = '1') then mem(to_integer(address1_tmp))(8*i+7 downto 8*i) := d1(8*i+7 downto 8*i); end if; end if; end process; end generate; end architecture behave;
gpl-3.0
mcoughli/root_of_trust
operational_os/hls/contact_discovery_axi_experimental/solution1/impl/vhdl/match_db_contact.vhd
3
247575
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity match_db_contact is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; ap_ce : IN STD_LOGIC; db_item_V : IN STD_LOGIC_VECTOR (511 downto 0); contacts_V_address0 : OUT STD_LOGIC_VECTOR (6 downto 0); contacts_V_ce0 : OUT STD_LOGIC; contacts_V_q0 : IN STD_LOGIC_VECTOR (511 downto 0); contacts_V_address1 : OUT STD_LOGIC_VECTOR (6 downto 0); contacts_V_ce1 : OUT STD_LOGIC; contacts_V_q1 : IN STD_LOGIC_VECTOR (511 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of match_db_contact is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001"; constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010"; constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100"; constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000"; constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000"; constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000"; constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000"; constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000"; constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000"; constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000"; constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000"; constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000"; constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000"; constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000"; constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000"; constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000"; constant ap_ST_fsm_pp0_stage16 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000"; constant ap_ST_fsm_pp0_stage17 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000"; constant ap_ST_fsm_pp0_stage18 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000"; constant ap_ST_fsm_pp0_stage19 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000"; constant ap_ST_fsm_pp0_stage20 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000"; constant ap_ST_fsm_pp0_stage21 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000"; constant ap_ST_fsm_pp0_stage22 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000"; constant ap_ST_fsm_pp0_stage23 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000"; constant ap_ST_fsm_pp0_stage24 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000"; constant ap_ST_fsm_pp0_stage25 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000"; constant ap_ST_fsm_pp0_stage26 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000"; constant ap_ST_fsm_pp0_stage27 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000"; constant ap_ST_fsm_pp0_stage28 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000"; constant ap_ST_fsm_pp0_stage29 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000"; constant ap_ST_fsm_pp0_stage30 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage31 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage32 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage33 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage34 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage35 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage36 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage37 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage38 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage39 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage40 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage41 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage42 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage43 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage44 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage45 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage46 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage47 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage48 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage49 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage50 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage51 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage52 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage53 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage54 : STD_LOGIC_VECTOR (63 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage55 : STD_LOGIC_VECTOR (63 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage56 : STD_LOGIC_VECTOR (63 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage57 : STD_LOGIC_VECTOR (63 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage58 : STD_LOGIC_VECTOR (63 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage59 : STD_LOGIC_VECTOR (63 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage60 : STD_LOGIC_VECTOR (63 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage61 : STD_LOGIC_VECTOR (63 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage62 : STD_LOGIC_VECTOR (63 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage63 : STD_LOGIC_VECTOR (63 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000"; constant ap_const_boolean_1 : BOOLEAN := true; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_boolean_0 : BOOLEAN := false; constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001"; constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010"; constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011"; constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100"; constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101"; constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110"; constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111"; constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000"; constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001"; constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010"; constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011"; constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100"; constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101"; constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110"; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000"; constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001"; constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010"; constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011"; constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100"; constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101"; constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110"; constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111"; constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000"; constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001"; constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010"; constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011"; constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100"; constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101"; constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110"; constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111"; constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000"; constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001"; constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010"; constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011"; constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100"; constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101"; constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110"; constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111"; constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000"; constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001"; constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010"; constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011"; constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100"; constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101"; constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110"; constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000"; constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001"; constant ap_const_lv7_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010"; constant ap_const_lv7_3 : STD_LOGIC_VECTOR (6 downto 0) := "0000011"; constant ap_const_lv7_4 : STD_LOGIC_VECTOR (6 downto 0) := "0000100"; constant ap_const_lv7_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101"; constant ap_const_lv7_6 : STD_LOGIC_VECTOR (6 downto 0) := "0000110"; constant ap_const_lv7_7 : STD_LOGIC_VECTOR (6 downto 0) := "0000111"; constant ap_const_lv7_8 : STD_LOGIC_VECTOR (6 downto 0) := "0001000"; constant ap_const_lv7_9 : STD_LOGIC_VECTOR (6 downto 0) := "0001001"; constant ap_const_lv7_A : STD_LOGIC_VECTOR (6 downto 0) := "0001010"; constant ap_const_lv7_B : STD_LOGIC_VECTOR (6 downto 0) := "0001011"; constant ap_const_lv7_C : STD_LOGIC_VECTOR (6 downto 0) := "0001100"; constant ap_const_lv7_D : STD_LOGIC_VECTOR (6 downto 0) := "0001101"; constant ap_const_lv7_E : STD_LOGIC_VECTOR (6 downto 0) := "0001110"; constant ap_const_lv7_F : STD_LOGIC_VECTOR (6 downto 0) := "0001111"; constant ap_const_lv7_10 : STD_LOGIC_VECTOR (6 downto 0) := "0010000"; constant ap_const_lv7_11 : STD_LOGIC_VECTOR (6 downto 0) := "0010001"; constant ap_const_lv7_12 : STD_LOGIC_VECTOR (6 downto 0) := "0010010"; constant ap_const_lv7_13 : STD_LOGIC_VECTOR (6 downto 0) := "0010011"; constant ap_const_lv7_14 : STD_LOGIC_VECTOR (6 downto 0) := "0010100"; constant ap_const_lv7_15 : STD_LOGIC_VECTOR (6 downto 0) := "0010101"; constant ap_const_lv7_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010110"; constant ap_const_lv7_17 : STD_LOGIC_VECTOR (6 downto 0) := "0010111"; constant ap_const_lv7_18 : STD_LOGIC_VECTOR (6 downto 0) := "0011000"; constant ap_const_lv7_19 : STD_LOGIC_VECTOR (6 downto 0) := "0011001"; constant ap_const_lv7_1A : STD_LOGIC_VECTOR (6 downto 0) := "0011010"; constant ap_const_lv7_1B : STD_LOGIC_VECTOR (6 downto 0) := "0011011"; constant ap_const_lv7_1C : STD_LOGIC_VECTOR (6 downto 0) := "0011100"; constant ap_const_lv7_1D : STD_LOGIC_VECTOR (6 downto 0) := "0011101"; constant ap_const_lv7_1E : STD_LOGIC_VECTOR (6 downto 0) := "0011110"; constant ap_const_lv7_1F : STD_LOGIC_VECTOR (6 downto 0) := "0011111"; constant ap_const_lv7_20 : STD_LOGIC_VECTOR (6 downto 0) := "0100000"; constant ap_const_lv7_21 : STD_LOGIC_VECTOR (6 downto 0) := "0100001"; constant ap_const_lv7_22 : STD_LOGIC_VECTOR (6 downto 0) := "0100010"; constant ap_const_lv7_23 : STD_LOGIC_VECTOR (6 downto 0) := "0100011"; constant ap_const_lv7_24 : STD_LOGIC_VECTOR (6 downto 0) := "0100100"; constant ap_const_lv7_25 : STD_LOGIC_VECTOR (6 downto 0) := "0100101"; constant ap_const_lv7_26 : STD_LOGIC_VECTOR (6 downto 0) := "0100110"; constant ap_const_lv7_27 : STD_LOGIC_VECTOR (6 downto 0) := "0100111"; constant ap_const_lv7_28 : STD_LOGIC_VECTOR (6 downto 0) := "0101000"; constant ap_const_lv7_29 : STD_LOGIC_VECTOR (6 downto 0) := "0101001"; constant ap_const_lv7_2A : STD_LOGIC_VECTOR (6 downto 0) := "0101010"; constant ap_const_lv7_2B : STD_LOGIC_VECTOR (6 downto 0) := "0101011"; constant ap_const_lv7_2C : STD_LOGIC_VECTOR (6 downto 0) := "0101100"; constant ap_const_lv7_2D : STD_LOGIC_VECTOR (6 downto 0) := "0101101"; constant ap_const_lv7_2E : STD_LOGIC_VECTOR (6 downto 0) := "0101110"; constant ap_const_lv7_2F : STD_LOGIC_VECTOR (6 downto 0) := "0101111"; constant ap_const_lv7_30 : STD_LOGIC_VECTOR (6 downto 0) := "0110000"; constant ap_const_lv7_31 : STD_LOGIC_VECTOR (6 downto 0) := "0110001"; constant ap_const_lv7_32 : STD_LOGIC_VECTOR (6 downto 0) := "0110010"; constant ap_const_lv7_33 : STD_LOGIC_VECTOR (6 downto 0) := "0110011"; constant ap_const_lv7_34 : STD_LOGIC_VECTOR (6 downto 0) := "0110100"; constant ap_const_lv7_35 : STD_LOGIC_VECTOR (6 downto 0) := "0110101"; constant ap_const_lv7_36 : STD_LOGIC_VECTOR (6 downto 0) := "0110110"; constant ap_const_lv7_37 : STD_LOGIC_VECTOR (6 downto 0) := "0110111"; constant ap_const_lv7_38 : STD_LOGIC_VECTOR (6 downto 0) := "0111000"; constant ap_const_lv7_39 : STD_LOGIC_VECTOR (6 downto 0) := "0111001"; constant ap_const_lv7_3A : STD_LOGIC_VECTOR (6 downto 0) := "0111010"; constant ap_const_lv7_3B : STD_LOGIC_VECTOR (6 downto 0) := "0111011"; constant ap_const_lv7_3C : STD_LOGIC_VECTOR (6 downto 0) := "0111100"; constant ap_const_lv7_3D : STD_LOGIC_VECTOR (6 downto 0) := "0111101"; constant ap_const_lv7_3E : STD_LOGIC_VECTOR (6 downto 0) := "0111110"; constant ap_const_lv7_3F : STD_LOGIC_VECTOR (6 downto 0) := "0111111"; constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000"; constant ap_const_lv7_41 : STD_LOGIC_VECTOR (6 downto 0) := "1000001"; constant ap_const_lv7_42 : STD_LOGIC_VECTOR (6 downto 0) := "1000010"; constant ap_const_lv7_43 : STD_LOGIC_VECTOR (6 downto 0) := "1000011"; constant ap_const_lv7_44 : STD_LOGIC_VECTOR (6 downto 0) := "1000100"; constant ap_const_lv7_45 : STD_LOGIC_VECTOR (6 downto 0) := "1000101"; constant ap_const_lv7_46 : STD_LOGIC_VECTOR (6 downto 0) := "1000110"; constant ap_const_lv7_47 : STD_LOGIC_VECTOR (6 downto 0) := "1000111"; constant ap_const_lv7_48 : STD_LOGIC_VECTOR (6 downto 0) := "1001000"; constant ap_const_lv7_49 : STD_LOGIC_VECTOR (6 downto 0) := "1001001"; constant ap_const_lv7_4A : STD_LOGIC_VECTOR (6 downto 0) := "1001010"; constant ap_const_lv7_4B : STD_LOGIC_VECTOR (6 downto 0) := "1001011"; constant ap_const_lv7_4C : STD_LOGIC_VECTOR (6 downto 0) := "1001100"; constant ap_const_lv7_4D : STD_LOGIC_VECTOR (6 downto 0) := "1001101"; constant ap_const_lv7_4E : STD_LOGIC_VECTOR (6 downto 0) := "1001110"; constant ap_const_lv7_4F : STD_LOGIC_VECTOR (6 downto 0) := "1001111"; constant ap_const_lv7_50 : STD_LOGIC_VECTOR (6 downto 0) := "1010000"; constant ap_const_lv7_51 : STD_LOGIC_VECTOR (6 downto 0) := "1010001"; constant ap_const_lv7_52 : STD_LOGIC_VECTOR (6 downto 0) := "1010010"; constant ap_const_lv7_53 : STD_LOGIC_VECTOR (6 downto 0) := "1010011"; constant ap_const_lv7_54 : STD_LOGIC_VECTOR (6 downto 0) := "1010100"; constant ap_const_lv7_55 : STD_LOGIC_VECTOR (6 downto 0) := "1010101"; constant ap_const_lv7_56 : STD_LOGIC_VECTOR (6 downto 0) := "1010110"; constant ap_const_lv7_57 : STD_LOGIC_VECTOR (6 downto 0) := "1010111"; constant ap_const_lv7_58 : STD_LOGIC_VECTOR (6 downto 0) := "1011000"; constant ap_const_lv7_59 : STD_LOGIC_VECTOR (6 downto 0) := "1011001"; constant ap_const_lv7_5A : STD_LOGIC_VECTOR (6 downto 0) := "1011010"; constant ap_const_lv7_5B : STD_LOGIC_VECTOR (6 downto 0) := "1011011"; constant ap_const_lv7_5C : STD_LOGIC_VECTOR (6 downto 0) := "1011100"; constant ap_const_lv7_5D : STD_LOGIC_VECTOR (6 downto 0) := "1011101"; constant ap_const_lv7_5E : STD_LOGIC_VECTOR (6 downto 0) := "1011110"; constant ap_const_lv7_5F : STD_LOGIC_VECTOR (6 downto 0) := "1011111"; constant ap_const_lv7_60 : STD_LOGIC_VECTOR (6 downto 0) := "1100000"; constant ap_const_lv7_61 : STD_LOGIC_VECTOR (6 downto 0) := "1100001"; constant ap_const_lv7_62 : STD_LOGIC_VECTOR (6 downto 0) := "1100010"; constant ap_const_lv7_63 : STD_LOGIC_VECTOR (6 downto 0) := "1100011"; constant ap_const_lv7_64 : STD_LOGIC_VECTOR (6 downto 0) := "1100100"; constant ap_const_lv7_65 : STD_LOGIC_VECTOR (6 downto 0) := "1100101"; constant ap_const_lv7_66 : STD_LOGIC_VECTOR (6 downto 0) := "1100110"; constant ap_const_lv7_67 : STD_LOGIC_VECTOR (6 downto 0) := "1100111"; constant ap_const_lv7_68 : STD_LOGIC_VECTOR (6 downto 0) := "1101000"; constant ap_const_lv7_69 : STD_LOGIC_VECTOR (6 downto 0) := "1101001"; constant ap_const_lv7_6A : STD_LOGIC_VECTOR (6 downto 0) := "1101010"; constant ap_const_lv7_6B : STD_LOGIC_VECTOR (6 downto 0) := "1101011"; constant ap_const_lv7_6C : STD_LOGIC_VECTOR (6 downto 0) := "1101100"; constant ap_const_lv7_6D : STD_LOGIC_VECTOR (6 downto 0) := "1101101"; constant ap_const_lv7_6E : STD_LOGIC_VECTOR (6 downto 0) := "1101110"; constant ap_const_lv7_6F : STD_LOGIC_VECTOR (6 downto 0) := "1101111"; constant ap_const_lv7_70 : STD_LOGIC_VECTOR (6 downto 0) := "1110000"; constant ap_const_lv7_71 : STD_LOGIC_VECTOR (6 downto 0) := "1110001"; constant ap_const_lv7_72 : STD_LOGIC_VECTOR (6 downto 0) := "1110010"; constant ap_const_lv7_73 : STD_LOGIC_VECTOR (6 downto 0) := "1110011"; constant ap_const_lv7_74 : STD_LOGIC_VECTOR (6 downto 0) := "1110100"; constant ap_const_lv7_75 : STD_LOGIC_VECTOR (6 downto 0) := "1110101"; constant ap_const_lv7_76 : STD_LOGIC_VECTOR (6 downto 0) := "1110110"; constant ap_const_lv7_77 : STD_LOGIC_VECTOR (6 downto 0) := "1110111"; constant ap_const_lv7_78 : STD_LOGIC_VECTOR (6 downto 0) := "1111000"; constant ap_const_lv7_79 : STD_LOGIC_VECTOR (6 downto 0) := "1111001"; constant ap_const_lv7_7A : STD_LOGIC_VECTOR (6 downto 0) := "1111010"; constant ap_const_lv7_7B : STD_LOGIC_VECTOR (6 downto 0) := "1111011"; constant ap_const_lv7_7C : STD_LOGIC_VECTOR (6 downto 0) := "1111100"; constant ap_const_lv7_7D : STD_LOGIC_VECTOR (6 downto 0) := "1111101"; constant ap_const_lv7_7E : STD_LOGIC_VECTOR (6 downto 0) := "1111110"; constant ap_const_lv7_7F : STD_LOGIC_VECTOR (6 downto 0) := "1111111"; signal ap_CS_fsm : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_pp0_stage0 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none"; signal ap_enable_reg_pp0_iter0 : STD_LOGIC; signal ap_block_pp0_stage0_flag00000000 : BOOLEAN; signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0'; signal ap_idle_pp0 : STD_LOGIC; signal ap_CS_fsm_pp0_stage63 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage63 : signal is "none"; signal ap_block_state64_pp0_stage63_iter0 : BOOLEAN; signal ap_block_pp0_stage63_flag00011001 : BOOLEAN; signal db_item_V_read_reg_1082 : STD_LOGIC_VECTOR (511 downto 0); signal ap_CS_fsm_pp0_stage1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none"; signal ap_block_state2_pp0_stage1_iter0 : BOOLEAN; signal ap_block_pp0_stage1_flag00011001 : BOOLEAN; signal grp_fu_403_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_1_reg_1088 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_1_1_reg_1093 : STD_LOGIC_VECTOR (0 downto 0); signal tmp4_fu_425_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp4_reg_1098 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none"; signal ap_block_state3_pp0_stage2_iter0 : BOOLEAN; signal ap_block_pp0_stage2_flag00011001 : BOOLEAN; signal tmp_1_4_reg_1103 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage3 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none"; signal ap_block_state4_pp0_stage3_iter0 : BOOLEAN; signal ap_block_pp0_stage3_flag00011001 : BOOLEAN; signal tmp_1_5_reg_1108 : STD_LOGIC_VECTOR (0 downto 0); signal tmp3_fu_447_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp3_reg_1113 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage4 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none"; signal ap_block_state5_pp0_stage4_iter0 : BOOLEAN; signal ap_block_pp0_stage4_flag00011001 : BOOLEAN; signal tmp_1_8_reg_1118 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage5 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none"; signal ap_block_state6_pp0_stage5_iter0 : BOOLEAN; signal ap_block_pp0_stage5_flag00011001 : BOOLEAN; signal tmp_1_9_reg_1123 : STD_LOGIC_VECTOR (0 downto 0); signal tmp11_fu_462_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp11_reg_1128 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage6 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none"; signal ap_block_state7_pp0_stage6_iter0 : BOOLEAN; signal ap_block_pp0_stage6_flag00011001 : BOOLEAN; signal tmp_1_11_reg_1133 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage7 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none"; signal ap_block_state8_pp0_stage7_iter0 : BOOLEAN; signal ap_block_pp0_stage7_flag00011001 : BOOLEAN; signal tmp_1_12_reg_1138 : STD_LOGIC_VECTOR (0 downto 0); signal tmp2_fu_489_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp2_reg_1143 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage8 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none"; signal ap_block_state9_pp0_stage8_iter0 : BOOLEAN; signal ap_block_pp0_stage8_flag00011001 : BOOLEAN; signal tmp_1_15_reg_1148 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage9 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none"; signal ap_block_state10_pp0_stage9_iter0 : BOOLEAN; signal ap_block_pp0_stage9_flag00011001 : BOOLEAN; signal tmp_1_16_reg_1153 : STD_LOGIC_VECTOR (0 downto 0); signal tmp19_fu_504_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp19_reg_1158 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage10 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none"; signal ap_block_state11_pp0_stage10_iter0 : BOOLEAN; signal ap_block_pp0_stage10_flag00011001 : BOOLEAN; signal tmp_1_19_reg_1163 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage11 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none"; signal ap_block_state12_pp0_stage11_iter0 : BOOLEAN; signal ap_block_pp0_stage11_flag00011001 : BOOLEAN; signal tmp_1_20_reg_1168 : STD_LOGIC_VECTOR (0 downto 0); signal tmp18_fu_526_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp18_reg_1173 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage12 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none"; signal ap_block_state13_pp0_stage12_iter0 : BOOLEAN; signal ap_block_pp0_stage12_flag00011001 : BOOLEAN; signal tmp_1_23_reg_1178 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage13 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none"; signal ap_block_state14_pp0_stage13_iter0 : BOOLEAN; signal ap_block_pp0_stage13_flag00011001 : BOOLEAN; signal tmp_1_24_reg_1183 : STD_LOGIC_VECTOR (0 downto 0); signal tmp26_fu_541_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp26_reg_1188 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage14 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none"; signal ap_block_state15_pp0_stage14_iter0 : BOOLEAN; signal ap_block_pp0_stage14_flag00011001 : BOOLEAN; signal tmp_1_27_reg_1193 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage15 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none"; signal ap_block_state16_pp0_stage15_iter0 : BOOLEAN; signal ap_block_pp0_stage15_flag00011001 : BOOLEAN; signal tmp_1_28_reg_1198 : STD_LOGIC_VECTOR (0 downto 0); signal tmp17_fu_568_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp17_reg_1203 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage16 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage16 : signal is "none"; signal ap_block_state17_pp0_stage16_iter0 : BOOLEAN; signal ap_block_pp0_stage16_flag00011001 : BOOLEAN; signal tmp_1_31_reg_1208 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage17 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage17 : signal is "none"; signal ap_block_state18_pp0_stage17_iter0 : BOOLEAN; signal ap_block_pp0_stage17_flag00011001 : BOOLEAN; signal tmp_1_32_reg_1213 : STD_LOGIC_VECTOR (0 downto 0); signal tmp35_fu_583_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp35_reg_1218 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage18 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage18 : signal is "none"; signal ap_block_state19_pp0_stage18_iter0 : BOOLEAN; signal ap_block_pp0_stage18_flag00011001 : BOOLEAN; signal tmp_1_35_reg_1223 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage19 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage19 : signal is "none"; signal ap_block_state20_pp0_stage19_iter0 : BOOLEAN; signal ap_block_pp0_stage19_flag00011001 : BOOLEAN; signal tmp_1_36_reg_1228 : STD_LOGIC_VECTOR (0 downto 0); signal tmp34_fu_605_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp34_reg_1233 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage20 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage20 : signal is "none"; signal ap_block_state21_pp0_stage20_iter0 : BOOLEAN; signal ap_block_pp0_stage20_flag00011001 : BOOLEAN; signal tmp_1_39_reg_1238 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage21 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage21 : signal is "none"; signal ap_block_state22_pp0_stage21_iter0 : BOOLEAN; signal ap_block_pp0_stage21_flag00011001 : BOOLEAN; signal tmp_1_40_reg_1243 : STD_LOGIC_VECTOR (0 downto 0); signal tmp42_fu_620_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp42_reg_1248 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage22 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage22 : signal is "none"; signal ap_block_state23_pp0_stage22_iter0 : BOOLEAN; signal ap_block_pp0_stage22_flag00011001 : BOOLEAN; signal tmp_1_43_reg_1253 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage23 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage23 : signal is "none"; signal ap_block_state24_pp0_stage23_iter0 : BOOLEAN; signal ap_block_pp0_stage23_flag00011001 : BOOLEAN; signal tmp_1_44_reg_1258 : STD_LOGIC_VECTOR (0 downto 0); signal tmp33_fu_647_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp33_reg_1263 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage24 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage24 : signal is "none"; signal ap_block_state25_pp0_stage24_iter0 : BOOLEAN; signal ap_block_pp0_stage24_flag00011001 : BOOLEAN; signal tmp_1_47_reg_1268 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage25 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage25 : signal is "none"; signal ap_block_state26_pp0_stage25_iter0 : BOOLEAN; signal ap_block_pp0_stage25_flag00011001 : BOOLEAN; signal tmp_1_48_reg_1273 : STD_LOGIC_VECTOR (0 downto 0); signal tmp50_fu_662_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp50_reg_1278 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage26 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage26 : signal is "none"; signal ap_block_state27_pp0_stage26_iter0 : BOOLEAN; signal ap_block_pp0_stage26_flag00011001 : BOOLEAN; signal tmp_1_51_reg_1283 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage27 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage27 : signal is "none"; signal ap_block_state28_pp0_stage27_iter0 : BOOLEAN; signal ap_block_pp0_stage27_flag00011001 : BOOLEAN; signal tmp_1_52_reg_1288 : STD_LOGIC_VECTOR (0 downto 0); signal tmp49_fu_684_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp49_reg_1293 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage28 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage28 : signal is "none"; signal ap_block_state29_pp0_stage28_iter0 : BOOLEAN; signal ap_block_pp0_stage28_flag00011001 : BOOLEAN; signal tmp_1_55_reg_1298 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage29 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage29 : signal is "none"; signal ap_block_state30_pp0_stage29_iter0 : BOOLEAN; signal ap_block_pp0_stage29_flag00011001 : BOOLEAN; signal tmp_1_56_reg_1303 : STD_LOGIC_VECTOR (0 downto 0); signal tmp57_fu_699_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp57_reg_1308 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage30 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage30 : signal is "none"; signal ap_block_state31_pp0_stage30_iter0 : BOOLEAN; signal ap_block_pp0_stage30_flag00011001 : BOOLEAN; signal tmp_1_59_reg_1313 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage31 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage31 : signal is "none"; signal ap_block_state32_pp0_stage31_iter0 : BOOLEAN; signal ap_block_pp0_stage31_flag00011001 : BOOLEAN; signal tmp_1_60_reg_1318 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_fu_740_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_reg_1323 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage32 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage32 : signal is "none"; signal ap_block_state33_pp0_stage32_iter0 : BOOLEAN; signal ap_block_pp0_stage32_flag00011001 : BOOLEAN; signal tmp_1_63_reg_1328 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage33 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage33 : signal is "none"; signal ap_block_state34_pp0_stage33_iter0 : BOOLEAN; signal ap_block_pp0_stage33_flag00011001 : BOOLEAN; signal tmp_1_64_reg_1333 : STD_LOGIC_VECTOR (0 downto 0); signal tmp67_fu_756_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp67_reg_1338 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage34 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage34 : signal is "none"; signal ap_block_state35_pp0_stage34_iter0 : BOOLEAN; signal ap_block_pp0_stage34_flag00011001 : BOOLEAN; signal tmp_1_67_reg_1343 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage35 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage35 : signal is "none"; signal ap_block_state36_pp0_stage35_iter0 : BOOLEAN; signal ap_block_pp0_stage35_flag00011001 : BOOLEAN; signal tmp_1_68_reg_1348 : STD_LOGIC_VECTOR (0 downto 0); signal tmp66_fu_778_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp66_reg_1353 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage36 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage36 : signal is "none"; signal ap_block_state37_pp0_stage36_iter0 : BOOLEAN; signal ap_block_pp0_stage36_flag00011001 : BOOLEAN; signal tmp_1_71_reg_1358 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage37 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage37 : signal is "none"; signal ap_block_state38_pp0_stage37_iter0 : BOOLEAN; signal ap_block_pp0_stage37_flag00011001 : BOOLEAN; signal tmp_1_72_reg_1363 : STD_LOGIC_VECTOR (0 downto 0); signal tmp74_fu_793_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp74_reg_1368 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage38 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage38 : signal is "none"; signal ap_block_state39_pp0_stage38_iter0 : BOOLEAN; signal ap_block_pp0_stage38_flag00011001 : BOOLEAN; signal tmp_1_75_reg_1373 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage39 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage39 : signal is "none"; signal ap_block_state40_pp0_stage39_iter0 : BOOLEAN; signal ap_block_pp0_stage39_flag00011001 : BOOLEAN; signal tmp_1_76_reg_1378 : STD_LOGIC_VECTOR (0 downto 0); signal tmp65_fu_820_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp65_reg_1383 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage40 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage40 : signal is "none"; signal ap_block_state41_pp0_stage40_iter0 : BOOLEAN; signal ap_block_pp0_stage40_flag00011001 : BOOLEAN; signal tmp_1_79_reg_1388 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage41 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage41 : signal is "none"; signal ap_block_state42_pp0_stage41_iter0 : BOOLEAN; signal ap_block_pp0_stage41_flag00011001 : BOOLEAN; signal tmp_1_80_reg_1393 : STD_LOGIC_VECTOR (0 downto 0); signal tmp82_fu_835_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp82_reg_1398 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage42 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage42 : signal is "none"; signal ap_block_state43_pp0_stage42_iter0 : BOOLEAN; signal ap_block_pp0_stage42_flag00011001 : BOOLEAN; signal tmp_1_83_reg_1403 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage43 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage43 : signal is "none"; signal ap_block_state44_pp0_stage43_iter0 : BOOLEAN; signal ap_block_pp0_stage43_flag00011001 : BOOLEAN; signal tmp_1_84_reg_1408 : STD_LOGIC_VECTOR (0 downto 0); signal tmp81_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp81_reg_1413 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage44 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage44 : signal is "none"; signal ap_block_state45_pp0_stage44_iter0 : BOOLEAN; signal ap_block_pp0_stage44_flag00011001 : BOOLEAN; signal tmp_1_87_reg_1418 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage45 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage45 : signal is "none"; signal ap_block_state46_pp0_stage45_iter0 : BOOLEAN; signal ap_block_pp0_stage45_flag00011001 : BOOLEAN; signal tmp_1_88_reg_1423 : STD_LOGIC_VECTOR (0 downto 0); signal tmp89_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp89_reg_1428 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage46 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage46 : signal is "none"; signal ap_block_state47_pp0_stage46_iter0 : BOOLEAN; signal ap_block_pp0_stage46_flag00011001 : BOOLEAN; signal tmp_1_91_reg_1433 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage47 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage47 : signal is "none"; signal ap_block_state48_pp0_stage47_iter0 : BOOLEAN; signal ap_block_pp0_stage47_flag00011001 : BOOLEAN; signal tmp_1_92_reg_1438 : STD_LOGIC_VECTOR (0 downto 0); signal tmp80_fu_899_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp80_reg_1443 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage48 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage48 : signal is "none"; signal ap_block_state49_pp0_stage48_iter0 : BOOLEAN; signal ap_block_pp0_stage48_flag00011001 : BOOLEAN; signal tmp_1_95_reg_1448 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage49 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage49 : signal is "none"; signal ap_block_state50_pp0_stage49_iter0 : BOOLEAN; signal ap_block_pp0_stage49_flag00011001 : BOOLEAN; signal tmp_1_96_reg_1453 : STD_LOGIC_VECTOR (0 downto 0); signal tmp98_fu_914_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp98_reg_1458 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage50 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage50 : signal is "none"; signal ap_block_state51_pp0_stage50_iter0 : BOOLEAN; signal ap_block_pp0_stage50_flag00011001 : BOOLEAN; signal tmp_1_99_reg_1463 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage51 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage51 : signal is "none"; signal ap_block_state52_pp0_stage51_iter0 : BOOLEAN; signal ap_block_pp0_stage51_flag00011001 : BOOLEAN; signal tmp_1_100_reg_1468 : STD_LOGIC_VECTOR (0 downto 0); signal tmp97_fu_936_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp97_reg_1473 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage52 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage52 : signal is "none"; signal ap_block_state53_pp0_stage52_iter0 : BOOLEAN; signal ap_block_pp0_stage52_flag00011001 : BOOLEAN; signal tmp_1_103_reg_1478 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage53 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage53 : signal is "none"; signal ap_block_state54_pp0_stage53_iter0 : BOOLEAN; signal ap_block_pp0_stage53_flag00011001 : BOOLEAN; signal tmp_1_104_reg_1483 : STD_LOGIC_VECTOR (0 downto 0); signal tmp105_fu_951_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp105_reg_1488 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage54 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage54 : signal is "none"; signal ap_block_state55_pp0_stage54_iter0 : BOOLEAN; signal ap_block_pp0_stage54_flag00011001 : BOOLEAN; signal tmp_1_107_reg_1493 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage55 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage55 : signal is "none"; signal ap_block_state56_pp0_stage55_iter0 : BOOLEAN; signal ap_block_pp0_stage55_flag00011001 : BOOLEAN; signal tmp_1_108_reg_1498 : STD_LOGIC_VECTOR (0 downto 0); signal tmp96_fu_978_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp96_reg_1503 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage56 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage56 : signal is "none"; signal ap_block_state57_pp0_stage56_iter0 : BOOLEAN; signal ap_block_pp0_stage56_flag00011001 : BOOLEAN; signal tmp_1_111_reg_1508 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage57 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage57 : signal is "none"; signal ap_block_state58_pp0_stage57_iter0 : BOOLEAN; signal ap_block_pp0_stage57_flag00011001 : BOOLEAN; signal tmp_1_112_reg_1513 : STD_LOGIC_VECTOR (0 downto 0); signal tmp113_fu_993_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp113_reg_1518 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage58 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage58 : signal is "none"; signal ap_block_state59_pp0_stage58_iter0 : BOOLEAN; signal ap_block_pp0_stage58_flag00011001 : BOOLEAN; signal tmp_1_115_reg_1523 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage59 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage59 : signal is "none"; signal ap_block_state60_pp0_stage59_iter0 : BOOLEAN; signal ap_block_pp0_stage59_flag00011001 : BOOLEAN; signal tmp_1_116_reg_1528 : STD_LOGIC_VECTOR (0 downto 0); signal tmp112_fu_1015_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp112_reg_1533 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage60 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage60 : signal is "none"; signal ap_block_state61_pp0_stage60_iter0 : BOOLEAN; signal ap_block_pp0_stage60_flag00011001 : BOOLEAN; signal tmp_1_119_reg_1538 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage61 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage61 : signal is "none"; signal ap_block_state62_pp0_stage61_iter0 : BOOLEAN; signal ap_block_pp0_stage61_flag00011001 : BOOLEAN; signal tmp_1_120_reg_1543 : STD_LOGIC_VECTOR (0 downto 0); signal tmp120_fu_1030_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp120_reg_1548 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage62 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage62 : signal is "none"; signal ap_block_state63_pp0_stage62_iter0 : BOOLEAN; signal ap_block_pp0_stage62_flag00011001 : BOOLEAN; signal tmp_1_123_reg_1553 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_1_124_reg_1558 : STD_LOGIC_VECTOR (0 downto 0); signal ap_enable_reg_pp0_iter0_reg : STD_LOGIC := '0'; signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN; signal ap_block_state65_pp0_stage0_iter1 : BOOLEAN; signal ap_block_pp0_stage0_flag00011011 : BOOLEAN; signal ap_block_pp0_stage63_flag00011011 : BOOLEAN; signal ap_port_reg_db_item_V : STD_LOGIC_VECTOR (511 downto 0); signal ap_block_pp0_stage0_flag00011001 : BOOLEAN; signal ap_block_pp0_stage1_flag00000000 : BOOLEAN; signal ap_block_pp0_stage2_flag00000000 : BOOLEAN; signal ap_block_pp0_stage3_flag00000000 : BOOLEAN; signal ap_block_pp0_stage4_flag00000000 : BOOLEAN; signal ap_block_pp0_stage5_flag00000000 : BOOLEAN; signal ap_block_pp0_stage6_flag00000000 : BOOLEAN; signal ap_block_pp0_stage7_flag00000000 : BOOLEAN; signal ap_block_pp0_stage8_flag00000000 : BOOLEAN; signal ap_block_pp0_stage9_flag00000000 : BOOLEAN; signal ap_block_pp0_stage10_flag00000000 : BOOLEAN; signal ap_block_pp0_stage11_flag00000000 : BOOLEAN; signal ap_block_pp0_stage12_flag00000000 : BOOLEAN; signal ap_block_pp0_stage13_flag00000000 : BOOLEAN; signal ap_block_pp0_stage14_flag00000000 : BOOLEAN; signal ap_block_pp0_stage15_flag00000000 : BOOLEAN; signal ap_block_pp0_stage16_flag00000000 : BOOLEAN; signal ap_block_pp0_stage17_flag00000000 : BOOLEAN; signal ap_block_pp0_stage18_flag00000000 : BOOLEAN; signal ap_block_pp0_stage19_flag00000000 : BOOLEAN; signal ap_block_pp0_stage20_flag00000000 : BOOLEAN; signal ap_block_pp0_stage21_flag00000000 : BOOLEAN; signal ap_block_pp0_stage22_flag00000000 : BOOLEAN; signal ap_block_pp0_stage23_flag00000000 : BOOLEAN; signal ap_block_pp0_stage24_flag00000000 : BOOLEAN; signal ap_block_pp0_stage25_flag00000000 : BOOLEAN; signal ap_block_pp0_stage26_flag00000000 : BOOLEAN; signal ap_block_pp0_stage27_flag00000000 : BOOLEAN; signal ap_block_pp0_stage28_flag00000000 : BOOLEAN; signal ap_block_pp0_stage29_flag00000000 : BOOLEAN; signal ap_block_pp0_stage30_flag00000000 : BOOLEAN; signal ap_block_pp0_stage31_flag00000000 : BOOLEAN; signal ap_block_pp0_stage32_flag00000000 : BOOLEAN; signal ap_block_pp0_stage33_flag00000000 : BOOLEAN; signal ap_block_pp0_stage34_flag00000000 : BOOLEAN; signal ap_block_pp0_stage35_flag00000000 : BOOLEAN; signal ap_block_pp0_stage36_flag00000000 : BOOLEAN; signal ap_block_pp0_stage37_flag00000000 : BOOLEAN; signal ap_block_pp0_stage38_flag00000000 : BOOLEAN; signal ap_block_pp0_stage39_flag00000000 : BOOLEAN; signal ap_block_pp0_stage40_flag00000000 : BOOLEAN; signal ap_block_pp0_stage41_flag00000000 : BOOLEAN; signal ap_block_pp0_stage42_flag00000000 : BOOLEAN; signal ap_block_pp0_stage43_flag00000000 : BOOLEAN; signal ap_block_pp0_stage44_flag00000000 : BOOLEAN; signal ap_block_pp0_stage45_flag00000000 : BOOLEAN; signal ap_block_pp0_stage46_flag00000000 : BOOLEAN; signal ap_block_pp0_stage47_flag00000000 : BOOLEAN; signal ap_block_pp0_stage48_flag00000000 : BOOLEAN; signal ap_block_pp0_stage49_flag00000000 : BOOLEAN; signal ap_block_pp0_stage50_flag00000000 : BOOLEAN; signal ap_block_pp0_stage51_flag00000000 : BOOLEAN; signal ap_block_pp0_stage52_flag00000000 : BOOLEAN; signal ap_block_pp0_stage53_flag00000000 : BOOLEAN; signal ap_block_pp0_stage54_flag00000000 : BOOLEAN; signal ap_block_pp0_stage55_flag00000000 : BOOLEAN; signal ap_block_pp0_stage56_flag00000000 : BOOLEAN; signal ap_block_pp0_stage57_flag00000000 : BOOLEAN; signal ap_block_pp0_stage58_flag00000000 : BOOLEAN; signal ap_block_pp0_stage59_flag00000000 : BOOLEAN; signal ap_block_pp0_stage60_flag00000000 : BOOLEAN; signal ap_block_pp0_stage61_flag00000000 : BOOLEAN; signal ap_block_pp0_stage62_flag00000000 : BOOLEAN; signal ap_block_pp0_stage63_flag00000000 : BOOLEAN; signal grp_fu_403_p1 : STD_LOGIC_VECTOR (511 downto 0); signal grp_fu_409_p1 : STD_LOGIC_VECTOR (511 downto 0); signal tmp6_fu_419_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp5_fu_415_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp9_fu_435_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp8_fu_431_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp7_fu_441_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp13_fu_456_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp12_fu_452_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp16_fu_472_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp15_fu_468_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp14_fu_478_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp10_fu_484_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp21_fu_498_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp20_fu_494_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp24_fu_514_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp23_fu_510_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp22_fu_520_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp28_fu_535_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp27_fu_531_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp31_fu_551_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp30_fu_547_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp29_fu_557_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp25_fu_563_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp37_fu_577_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp36_fu_573_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp40_fu_593_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp39_fu_589_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp38_fu_599_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp44_fu_614_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp43_fu_610_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp47_fu_630_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp46_fu_626_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp45_fu_636_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp41_fu_642_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp52_fu_656_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp51_fu_652_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp55_fu_672_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp54_fu_668_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp53_fu_678_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp59_fu_693_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp58_fu_689_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp62_fu_713_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp61_fu_709_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp60_fu_719_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp56_fu_725_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp48_fu_730_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp32_fu_735_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp1_fu_705_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp69_fu_750_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp68_fu_746_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp72_fu_766_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp71_fu_762_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp70_fu_772_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp76_fu_787_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp75_fu_783_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp79_fu_803_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp78_fu_799_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp77_fu_809_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp73_fu_815_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp84_fu_829_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp83_fu_825_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp87_fu_845_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp86_fu_841_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp85_fu_851_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp91_fu_866_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp90_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp94_fu_882_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp93_fu_878_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp92_fu_888_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp88_fu_894_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp100_fu_908_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp99_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp103_fu_924_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp102_fu_920_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp101_fu_930_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp107_fu_945_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp106_fu_941_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp110_fu_961_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp109_fu_957_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp108_fu_967_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp104_fu_973_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp115_fu_987_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp114_fu_983_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp118_fu_1003_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp117_fu_999_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp116_fu_1009_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp122_fu_1024_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp121_fu_1020_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp125_fu_1044_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp124_fu_1040_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp123_fu_1050_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp119_fu_1056_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp111_fu_1061_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp95_fu_1066_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp64_fu_1036_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp63_fu_1071_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (63 downto 0); signal ap_idle_pp0_0to0 : STD_LOGIC; signal ap_reset_idle_pp0 : STD_LOGIC; signal ap_idle_pp0_1to1 : STD_LOGIC; signal ap_block_pp0_stage1_flag00011011 : BOOLEAN; signal ap_block_pp0_stage2_flag00011011 : BOOLEAN; signal ap_block_pp0_stage3_flag00011011 : BOOLEAN; signal ap_block_pp0_stage4_flag00011011 : BOOLEAN; signal ap_block_pp0_stage5_flag00011011 : BOOLEAN; signal ap_block_pp0_stage6_flag00011011 : BOOLEAN; signal ap_block_pp0_stage7_flag00011011 : BOOLEAN; signal ap_block_pp0_stage8_flag00011011 : BOOLEAN; signal ap_block_pp0_stage9_flag00011011 : BOOLEAN; signal ap_block_pp0_stage10_flag00011011 : BOOLEAN; signal ap_block_pp0_stage11_flag00011011 : BOOLEAN; signal ap_block_pp0_stage12_flag00011011 : BOOLEAN; signal ap_block_pp0_stage13_flag00011011 : BOOLEAN; signal ap_block_pp0_stage14_flag00011011 : BOOLEAN; signal ap_block_pp0_stage15_flag00011011 : BOOLEAN; signal ap_block_pp0_stage16_flag00011011 : BOOLEAN; signal ap_block_pp0_stage17_flag00011011 : BOOLEAN; signal ap_block_pp0_stage18_flag00011011 : BOOLEAN; signal ap_block_pp0_stage19_flag00011011 : BOOLEAN; signal ap_block_pp0_stage20_flag00011011 : BOOLEAN; signal ap_block_pp0_stage21_flag00011011 : BOOLEAN; signal ap_block_pp0_stage22_flag00011011 : BOOLEAN; signal ap_block_pp0_stage23_flag00011011 : BOOLEAN; signal ap_block_pp0_stage24_flag00011011 : BOOLEAN; signal ap_block_pp0_stage25_flag00011011 : BOOLEAN; signal ap_block_pp0_stage26_flag00011011 : BOOLEAN; signal ap_block_pp0_stage27_flag00011011 : BOOLEAN; signal ap_block_pp0_stage28_flag00011011 : BOOLEAN; signal ap_block_pp0_stage29_flag00011011 : BOOLEAN; signal ap_block_pp0_stage30_flag00011011 : BOOLEAN; signal ap_block_pp0_stage31_flag00011011 : BOOLEAN; signal ap_block_pp0_stage32_flag00011011 : BOOLEAN; signal ap_block_pp0_stage33_flag00011011 : BOOLEAN; signal ap_block_pp0_stage34_flag00011011 : BOOLEAN; signal ap_block_pp0_stage35_flag00011011 : BOOLEAN; signal ap_block_pp0_stage36_flag00011011 : BOOLEAN; signal ap_block_pp0_stage37_flag00011011 : BOOLEAN; signal ap_block_pp0_stage38_flag00011011 : BOOLEAN; signal ap_block_pp0_stage39_flag00011011 : BOOLEAN; signal ap_block_pp0_stage40_flag00011011 : BOOLEAN; signal ap_block_pp0_stage41_flag00011011 : BOOLEAN; signal ap_block_pp0_stage42_flag00011011 : BOOLEAN; signal ap_block_pp0_stage43_flag00011011 : BOOLEAN; signal ap_block_pp0_stage44_flag00011011 : BOOLEAN; signal ap_block_pp0_stage45_flag00011011 : BOOLEAN; signal ap_block_pp0_stage46_flag00011011 : BOOLEAN; signal ap_block_pp0_stage47_flag00011011 : BOOLEAN; signal ap_block_pp0_stage48_flag00011011 : BOOLEAN; signal ap_block_pp0_stage49_flag00011011 : BOOLEAN; signal ap_block_pp0_stage50_flag00011011 : BOOLEAN; signal ap_block_pp0_stage51_flag00011011 : BOOLEAN; signal ap_block_pp0_stage52_flag00011011 : BOOLEAN; signal ap_block_pp0_stage53_flag00011011 : BOOLEAN; signal ap_block_pp0_stage54_flag00011011 : BOOLEAN; signal ap_block_pp0_stage55_flag00011011 : BOOLEAN; signal ap_block_pp0_stage56_flag00011011 : BOOLEAN; signal ap_block_pp0_stage57_flag00011011 : BOOLEAN; signal ap_block_pp0_stage58_flag00011011 : BOOLEAN; signal ap_block_pp0_stage59_flag00011011 : BOOLEAN; signal ap_block_pp0_stage60_flag00011011 : BOOLEAN; signal ap_block_pp0_stage61_flag00011011 : BOOLEAN; signal ap_block_pp0_stage62_flag00011011 : BOOLEAN; signal ap_enable_pp0 : STD_LOGIC; begin ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_fsm_pp0_stage0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; ap_enable_reg_pp0_iter0_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_enable_reg_pp0_iter0_reg <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then ap_enable_reg_pp0_iter0_reg <= ap_start; end if; end if; end if; end process; ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0))) then ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; end if; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then ap_port_reg_db_item_V <= db_item_V; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then db_item_V_read_reg_1082 <= ap_port_reg_db_item_V; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0))) then tmp105_reg_1488 <= tmp105_fu_951_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0))) then tmp112_reg_1533 <= tmp112_fu_1015_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0))) then tmp113_reg_1518 <= tmp113_fu_993_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then tmp11_reg_1128 <= tmp11_fu_462_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0))) then tmp120_reg_1548 <= tmp120_fu_1030_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0))) then tmp17_reg_1203 <= tmp17_fu_568_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then tmp18_reg_1173 <= tmp18_fu_526_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then tmp19_reg_1158 <= tmp19_fu_504_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0))) then tmp26_reg_1188 <= tmp26_fu_541_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then tmp2_reg_1143 <= tmp2_fu_489_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0))) then tmp33_reg_1263 <= tmp33_fu_647_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0))) then tmp34_reg_1233 <= tmp34_fu_605_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0))) then tmp35_reg_1218 <= tmp35_fu_583_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then tmp3_reg_1113 <= tmp3_fu_447_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0))) then tmp42_reg_1248 <= tmp42_fu_620_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0))) then tmp49_reg_1293 <= tmp49_fu_684_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then tmp4_reg_1098 <= tmp4_fu_425_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0))) then tmp50_reg_1278 <= tmp50_fu_662_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0))) then tmp57_reg_1308 <= tmp57_fu_699_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0))) then tmp65_reg_1383 <= tmp65_fu_820_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0))) then tmp66_reg_1353 <= tmp66_fu_778_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0))) then tmp67_reg_1338 <= tmp67_fu_756_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0))) then tmp74_reg_1368 <= tmp74_fu_793_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0))) then tmp80_reg_1443 <= tmp80_fu_899_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0))) then tmp81_reg_1413 <= tmp81_fu_857_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0))) then tmp82_reg_1398 <= tmp82_fu_835_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0))) then tmp89_reg_1428 <= tmp89_fu_872_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0))) then tmp96_reg_1503 <= tmp96_fu_978_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0))) then tmp97_reg_1473 <= tmp97_fu_936_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0))) then tmp98_reg_1458 <= tmp98_fu_914_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0))) then tmp_1_100_reg_1468 <= grp_fu_409_p2; tmp_1_99_reg_1463 <= grp_fu_403_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0))) then tmp_1_103_reg_1478 <= grp_fu_403_p2; tmp_1_104_reg_1483 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0))) then tmp_1_107_reg_1493 <= grp_fu_403_p2; tmp_1_108_reg_1498 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0))) then tmp_1_111_reg_1508 <= grp_fu_403_p2; tmp_1_112_reg_1513 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0))) then tmp_1_115_reg_1523 <= grp_fu_403_p2; tmp_1_116_reg_1528 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0))) then tmp_1_119_reg_1538 <= grp_fu_403_p2; tmp_1_120_reg_1543 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then tmp_1_11_reg_1133 <= grp_fu_403_p2; tmp_1_12_reg_1138 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then tmp_1_123_reg_1553 <= grp_fu_403_p2; tmp_1_124_reg_1558 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then tmp_1_15_reg_1148 <= grp_fu_403_p2; tmp_1_16_reg_1153 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then tmp_1_19_reg_1163 <= grp_fu_403_p2; tmp_1_20_reg_1168 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then tmp_1_1_reg_1093 <= grp_fu_409_p2; tmp_1_reg_1088 <= grp_fu_403_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then tmp_1_23_reg_1178 <= grp_fu_403_p2; tmp_1_24_reg_1183 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then tmp_1_27_reg_1193 <= grp_fu_403_p2; tmp_1_28_reg_1198 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0))) then tmp_1_31_reg_1208 <= grp_fu_403_p2; tmp_1_32_reg_1213 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0))) then tmp_1_35_reg_1223 <= grp_fu_403_p2; tmp_1_36_reg_1228 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0))) then tmp_1_39_reg_1238 <= grp_fu_403_p2; tmp_1_40_reg_1243 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0))) then tmp_1_43_reg_1253 <= grp_fu_403_p2; tmp_1_44_reg_1258 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0))) then tmp_1_47_reg_1268 <= grp_fu_403_p2; tmp_1_48_reg_1273 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then tmp_1_4_reg_1103 <= grp_fu_403_p2; tmp_1_5_reg_1108 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0))) then tmp_1_51_reg_1283 <= grp_fu_403_p2; tmp_1_52_reg_1288 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0))) then tmp_1_55_reg_1298 <= grp_fu_403_p2; tmp_1_56_reg_1303 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0))) then tmp_1_59_reg_1313 <= grp_fu_403_p2; tmp_1_60_reg_1318 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0))) then tmp_1_63_reg_1328 <= grp_fu_403_p2; tmp_1_64_reg_1333 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0))) then tmp_1_67_reg_1343 <= grp_fu_403_p2; tmp_1_68_reg_1348 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0))) then tmp_1_71_reg_1358 <= grp_fu_403_p2; tmp_1_72_reg_1363 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0))) then tmp_1_75_reg_1373 <= grp_fu_403_p2; tmp_1_76_reg_1378 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0))) then tmp_1_79_reg_1388 <= grp_fu_403_p2; tmp_1_80_reg_1393 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0))) then tmp_1_83_reg_1403 <= grp_fu_403_p2; tmp_1_84_reg_1408 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0))) then tmp_1_87_reg_1418 <= grp_fu_403_p2; tmp_1_88_reg_1423 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then tmp_1_8_reg_1118 <= grp_fu_403_p2; tmp_1_9_reg_1123 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0))) then tmp_1_91_reg_1433 <= grp_fu_403_p2; tmp_1_92_reg_1438 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0))) then tmp_1_95_reg_1448 <= grp_fu_403_p2; tmp_1_96_reg_1453 <= grp_fu_409_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0))) then tmp_reg_1323 <= tmp_fu_740_p2; end if; end if; end process; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage63_flag00011011, ap_reset_idle_pp0, ap_idle_pp0_1to1, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage13_flag00011011, ap_block_pp0_stage14_flag00011011, ap_block_pp0_stage15_flag00011011, ap_block_pp0_stage16_flag00011011, ap_block_pp0_stage17_flag00011011, ap_block_pp0_stage18_flag00011011, ap_block_pp0_stage19_flag00011011, ap_block_pp0_stage20_flag00011011, ap_block_pp0_stage21_flag00011011, ap_block_pp0_stage22_flag00011011, ap_block_pp0_stage23_flag00011011, ap_block_pp0_stage24_flag00011011, ap_block_pp0_stage25_flag00011011, ap_block_pp0_stage26_flag00011011, ap_block_pp0_stage27_flag00011011, ap_block_pp0_stage28_flag00011011, ap_block_pp0_stage29_flag00011011, ap_block_pp0_stage30_flag00011011, ap_block_pp0_stage31_flag00011011, ap_block_pp0_stage32_flag00011011, ap_block_pp0_stage33_flag00011011, ap_block_pp0_stage34_flag00011011, ap_block_pp0_stage35_flag00011011, ap_block_pp0_stage36_flag00011011, ap_block_pp0_stage37_flag00011011, ap_block_pp0_stage38_flag00011011, ap_block_pp0_stage39_flag00011011, ap_block_pp0_stage40_flag00011011, ap_block_pp0_stage41_flag00011011, ap_block_pp0_stage42_flag00011011, ap_block_pp0_stage43_flag00011011, ap_block_pp0_stage44_flag00011011, ap_block_pp0_stage45_flag00011011, ap_block_pp0_stage46_flag00011011, ap_block_pp0_stage47_flag00011011, ap_block_pp0_stage48_flag00011011, ap_block_pp0_stage49_flag00011011, ap_block_pp0_stage50_flag00011011, ap_block_pp0_stage51_flag00011011, ap_block_pp0_stage52_flag00011011, ap_block_pp0_stage53_flag00011011, ap_block_pp0_stage54_flag00011011, ap_block_pp0_stage55_flag00011011, ap_block_pp0_stage56_flag00011011, ap_block_pp0_stage57_flag00011011, ap_block_pp0_stage58_flag00011011, ap_block_pp0_stage59_flag00011011, ap_block_pp0_stage60_flag00011011, ap_block_pp0_stage61_flag00011011, ap_block_pp0_stage62_flag00011011) begin case ap_CS_fsm is when ap_ST_fsm_pp0_stage0 => if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_reset_idle_pp0 = ap_const_logic_0) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_1to1))))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage1; elsif (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_reset_idle_pp0))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; else ap_NS_fsm <= ap_ST_fsm_pp0_stage0; end if; when ap_ST_fsm_pp0_stage1 => if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage2; else ap_NS_fsm <= ap_ST_fsm_pp0_stage1; end if; when ap_ST_fsm_pp0_stage2 => if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage3; else ap_NS_fsm <= ap_ST_fsm_pp0_stage2; end if; when ap_ST_fsm_pp0_stage3 => if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage4; else ap_NS_fsm <= ap_ST_fsm_pp0_stage3; end if; when ap_ST_fsm_pp0_stage4 => if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage5; else ap_NS_fsm <= ap_ST_fsm_pp0_stage4; end if; when ap_ST_fsm_pp0_stage5 => if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage6; else ap_NS_fsm <= ap_ST_fsm_pp0_stage5; end if; when ap_ST_fsm_pp0_stage6 => if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage7; else ap_NS_fsm <= ap_ST_fsm_pp0_stage6; end if; when ap_ST_fsm_pp0_stage7 => if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage8; else ap_NS_fsm <= ap_ST_fsm_pp0_stage7; end if; when ap_ST_fsm_pp0_stage8 => if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage9; else ap_NS_fsm <= ap_ST_fsm_pp0_stage8; end if; when ap_ST_fsm_pp0_stage9 => if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage10; else ap_NS_fsm <= ap_ST_fsm_pp0_stage9; end if; when ap_ST_fsm_pp0_stage10 => if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage11; else ap_NS_fsm <= ap_ST_fsm_pp0_stage10; end if; when ap_ST_fsm_pp0_stage11 => if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage12; else ap_NS_fsm <= ap_ST_fsm_pp0_stage11; end if; when ap_ST_fsm_pp0_stage12 => if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage13; else ap_NS_fsm <= ap_ST_fsm_pp0_stage12; end if; when ap_ST_fsm_pp0_stage13 => if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage14; else ap_NS_fsm <= ap_ST_fsm_pp0_stage13; end if; when ap_ST_fsm_pp0_stage14 => if ((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage15; else ap_NS_fsm <= ap_ST_fsm_pp0_stage14; end if; when ap_ST_fsm_pp0_stage15 => if ((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage16; else ap_NS_fsm <= ap_ST_fsm_pp0_stage15; end if; when ap_ST_fsm_pp0_stage16 => if ((ap_block_pp0_stage16_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage17; else ap_NS_fsm <= ap_ST_fsm_pp0_stage16; end if; when ap_ST_fsm_pp0_stage17 => if ((ap_block_pp0_stage17_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage18; else ap_NS_fsm <= ap_ST_fsm_pp0_stage17; end if; when ap_ST_fsm_pp0_stage18 => if ((ap_block_pp0_stage18_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage19; else ap_NS_fsm <= ap_ST_fsm_pp0_stage18; end if; when ap_ST_fsm_pp0_stage19 => if ((ap_block_pp0_stage19_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage20; else ap_NS_fsm <= ap_ST_fsm_pp0_stage19; end if; when ap_ST_fsm_pp0_stage20 => if ((ap_block_pp0_stage20_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage21; else ap_NS_fsm <= ap_ST_fsm_pp0_stage20; end if; when ap_ST_fsm_pp0_stage21 => if ((ap_block_pp0_stage21_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage22; else ap_NS_fsm <= ap_ST_fsm_pp0_stage21; end if; when ap_ST_fsm_pp0_stage22 => if ((ap_block_pp0_stage22_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage23; else ap_NS_fsm <= ap_ST_fsm_pp0_stage22; end if; when ap_ST_fsm_pp0_stage23 => if ((ap_block_pp0_stage23_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage24; else ap_NS_fsm <= ap_ST_fsm_pp0_stage23; end if; when ap_ST_fsm_pp0_stage24 => if ((ap_block_pp0_stage24_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage25; else ap_NS_fsm <= ap_ST_fsm_pp0_stage24; end if; when ap_ST_fsm_pp0_stage25 => if ((ap_block_pp0_stage25_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage26; else ap_NS_fsm <= ap_ST_fsm_pp0_stage25; end if; when ap_ST_fsm_pp0_stage26 => if ((ap_block_pp0_stage26_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage27; else ap_NS_fsm <= ap_ST_fsm_pp0_stage26; end if; when ap_ST_fsm_pp0_stage27 => if ((ap_block_pp0_stage27_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage28; else ap_NS_fsm <= ap_ST_fsm_pp0_stage27; end if; when ap_ST_fsm_pp0_stage28 => if ((ap_block_pp0_stage28_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage29; else ap_NS_fsm <= ap_ST_fsm_pp0_stage28; end if; when ap_ST_fsm_pp0_stage29 => if ((ap_block_pp0_stage29_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage30; else ap_NS_fsm <= ap_ST_fsm_pp0_stage29; end if; when ap_ST_fsm_pp0_stage30 => if ((ap_block_pp0_stage30_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage31; else ap_NS_fsm <= ap_ST_fsm_pp0_stage30; end if; when ap_ST_fsm_pp0_stage31 => if ((ap_block_pp0_stage31_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage32; else ap_NS_fsm <= ap_ST_fsm_pp0_stage31; end if; when ap_ST_fsm_pp0_stage32 => if ((ap_block_pp0_stage32_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage33; else ap_NS_fsm <= ap_ST_fsm_pp0_stage32; end if; when ap_ST_fsm_pp0_stage33 => if ((ap_block_pp0_stage33_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage34; else ap_NS_fsm <= ap_ST_fsm_pp0_stage33; end if; when ap_ST_fsm_pp0_stage34 => if ((ap_block_pp0_stage34_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage35; else ap_NS_fsm <= ap_ST_fsm_pp0_stage34; end if; when ap_ST_fsm_pp0_stage35 => if ((ap_block_pp0_stage35_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage36; else ap_NS_fsm <= ap_ST_fsm_pp0_stage35; end if; when ap_ST_fsm_pp0_stage36 => if ((ap_block_pp0_stage36_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage37; else ap_NS_fsm <= ap_ST_fsm_pp0_stage36; end if; when ap_ST_fsm_pp0_stage37 => if ((ap_block_pp0_stage37_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage38; else ap_NS_fsm <= ap_ST_fsm_pp0_stage37; end if; when ap_ST_fsm_pp0_stage38 => if ((ap_block_pp0_stage38_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage39; else ap_NS_fsm <= ap_ST_fsm_pp0_stage38; end if; when ap_ST_fsm_pp0_stage39 => if ((ap_block_pp0_stage39_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage40; else ap_NS_fsm <= ap_ST_fsm_pp0_stage39; end if; when ap_ST_fsm_pp0_stage40 => if ((ap_block_pp0_stage40_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage41; else ap_NS_fsm <= ap_ST_fsm_pp0_stage40; end if; when ap_ST_fsm_pp0_stage41 => if ((ap_block_pp0_stage41_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage42; else ap_NS_fsm <= ap_ST_fsm_pp0_stage41; end if; when ap_ST_fsm_pp0_stage42 => if ((ap_block_pp0_stage42_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage43; else ap_NS_fsm <= ap_ST_fsm_pp0_stage42; end if; when ap_ST_fsm_pp0_stage43 => if ((ap_block_pp0_stage43_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage44; else ap_NS_fsm <= ap_ST_fsm_pp0_stage43; end if; when ap_ST_fsm_pp0_stage44 => if ((ap_block_pp0_stage44_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage45; else ap_NS_fsm <= ap_ST_fsm_pp0_stage44; end if; when ap_ST_fsm_pp0_stage45 => if ((ap_block_pp0_stage45_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage46; else ap_NS_fsm <= ap_ST_fsm_pp0_stage45; end if; when ap_ST_fsm_pp0_stage46 => if ((ap_block_pp0_stage46_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage47; else ap_NS_fsm <= ap_ST_fsm_pp0_stage46; end if; when ap_ST_fsm_pp0_stage47 => if ((ap_block_pp0_stage47_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage48; else ap_NS_fsm <= ap_ST_fsm_pp0_stage47; end if; when ap_ST_fsm_pp0_stage48 => if ((ap_block_pp0_stage48_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage49; else ap_NS_fsm <= ap_ST_fsm_pp0_stage48; end if; when ap_ST_fsm_pp0_stage49 => if ((ap_block_pp0_stage49_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage50; else ap_NS_fsm <= ap_ST_fsm_pp0_stage49; end if; when ap_ST_fsm_pp0_stage50 => if ((ap_block_pp0_stage50_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage51; else ap_NS_fsm <= ap_ST_fsm_pp0_stage50; end if; when ap_ST_fsm_pp0_stage51 => if ((ap_block_pp0_stage51_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage52; else ap_NS_fsm <= ap_ST_fsm_pp0_stage51; end if; when ap_ST_fsm_pp0_stage52 => if ((ap_block_pp0_stage52_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage53; else ap_NS_fsm <= ap_ST_fsm_pp0_stage52; end if; when ap_ST_fsm_pp0_stage53 => if ((ap_block_pp0_stage53_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage54; else ap_NS_fsm <= ap_ST_fsm_pp0_stage53; end if; when ap_ST_fsm_pp0_stage54 => if ((ap_block_pp0_stage54_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage55; else ap_NS_fsm <= ap_ST_fsm_pp0_stage54; end if; when ap_ST_fsm_pp0_stage55 => if ((ap_block_pp0_stage55_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage56; else ap_NS_fsm <= ap_ST_fsm_pp0_stage55; end if; when ap_ST_fsm_pp0_stage56 => if ((ap_block_pp0_stage56_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage57; else ap_NS_fsm <= ap_ST_fsm_pp0_stage56; end if; when ap_ST_fsm_pp0_stage57 => if ((ap_block_pp0_stage57_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage58; else ap_NS_fsm <= ap_ST_fsm_pp0_stage57; end if; when ap_ST_fsm_pp0_stage58 => if ((ap_block_pp0_stage58_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage59; else ap_NS_fsm <= ap_ST_fsm_pp0_stage58; end if; when ap_ST_fsm_pp0_stage59 => if ((ap_block_pp0_stage59_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage60; else ap_NS_fsm <= ap_ST_fsm_pp0_stage59; end if; when ap_ST_fsm_pp0_stage60 => if ((ap_block_pp0_stage60_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage61; else ap_NS_fsm <= ap_ST_fsm_pp0_stage60; end if; when ap_ST_fsm_pp0_stage61 => if ((ap_block_pp0_stage61_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage62; else ap_NS_fsm <= ap_ST_fsm_pp0_stage61; end if; when ap_ST_fsm_pp0_stage62 => if ((ap_block_pp0_stage62_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage63; else ap_NS_fsm <= ap_ST_fsm_pp0_stage62; end if; when ap_ST_fsm_pp0_stage63 => if ((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; else ap_NS_fsm <= ap_ST_fsm_pp0_stage63; end if; when others => ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end case; end process; ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0); ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(1); ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(10); ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(11); ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(12); ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(13); ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(14); ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(15); ap_CS_fsm_pp0_stage16 <= ap_CS_fsm(16); ap_CS_fsm_pp0_stage17 <= ap_CS_fsm(17); ap_CS_fsm_pp0_stage18 <= ap_CS_fsm(18); ap_CS_fsm_pp0_stage19 <= ap_CS_fsm(19); ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(2); ap_CS_fsm_pp0_stage20 <= ap_CS_fsm(20); ap_CS_fsm_pp0_stage21 <= ap_CS_fsm(21); ap_CS_fsm_pp0_stage22 <= ap_CS_fsm(22); ap_CS_fsm_pp0_stage23 <= ap_CS_fsm(23); ap_CS_fsm_pp0_stage24 <= ap_CS_fsm(24); ap_CS_fsm_pp0_stage25 <= ap_CS_fsm(25); ap_CS_fsm_pp0_stage26 <= ap_CS_fsm(26); ap_CS_fsm_pp0_stage27 <= ap_CS_fsm(27); ap_CS_fsm_pp0_stage28 <= ap_CS_fsm(28); ap_CS_fsm_pp0_stage29 <= ap_CS_fsm(29); ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(3); ap_CS_fsm_pp0_stage30 <= ap_CS_fsm(30); ap_CS_fsm_pp0_stage31 <= ap_CS_fsm(31); ap_CS_fsm_pp0_stage32 <= ap_CS_fsm(32); ap_CS_fsm_pp0_stage33 <= ap_CS_fsm(33); ap_CS_fsm_pp0_stage34 <= ap_CS_fsm(34); ap_CS_fsm_pp0_stage35 <= ap_CS_fsm(35); ap_CS_fsm_pp0_stage36 <= ap_CS_fsm(36); ap_CS_fsm_pp0_stage37 <= ap_CS_fsm(37); ap_CS_fsm_pp0_stage38 <= ap_CS_fsm(38); ap_CS_fsm_pp0_stage39 <= ap_CS_fsm(39); ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(4); ap_CS_fsm_pp0_stage40 <= ap_CS_fsm(40); ap_CS_fsm_pp0_stage41 <= ap_CS_fsm(41); ap_CS_fsm_pp0_stage42 <= ap_CS_fsm(42); ap_CS_fsm_pp0_stage43 <= ap_CS_fsm(43); ap_CS_fsm_pp0_stage44 <= ap_CS_fsm(44); ap_CS_fsm_pp0_stage45 <= ap_CS_fsm(45); ap_CS_fsm_pp0_stage46 <= ap_CS_fsm(46); ap_CS_fsm_pp0_stage47 <= ap_CS_fsm(47); ap_CS_fsm_pp0_stage48 <= ap_CS_fsm(48); ap_CS_fsm_pp0_stage49 <= ap_CS_fsm(49); ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(5); ap_CS_fsm_pp0_stage50 <= ap_CS_fsm(50); ap_CS_fsm_pp0_stage51 <= ap_CS_fsm(51); ap_CS_fsm_pp0_stage52 <= ap_CS_fsm(52); ap_CS_fsm_pp0_stage53 <= ap_CS_fsm(53); ap_CS_fsm_pp0_stage54 <= ap_CS_fsm(54); ap_CS_fsm_pp0_stage55 <= ap_CS_fsm(55); ap_CS_fsm_pp0_stage56 <= ap_CS_fsm(56); ap_CS_fsm_pp0_stage57 <= ap_CS_fsm(57); ap_CS_fsm_pp0_stage58 <= ap_CS_fsm(58); ap_CS_fsm_pp0_stage59 <= ap_CS_fsm(59); ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(6); ap_CS_fsm_pp0_stage60 <= ap_CS_fsm(60); ap_CS_fsm_pp0_stage61 <= ap_CS_fsm(61); ap_CS_fsm_pp0_stage62 <= ap_CS_fsm(62); ap_CS_fsm_pp0_stage63 <= ap_CS_fsm(63); ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(7); ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(8); ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(9); ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0) begin ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)); end process; ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0, ap_ce) begin ap_block_pp0_stage0_flag00011011 <= ((ap_ce = ap_const_logic_0) or ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))); end process; ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage10_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage10_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage10_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage11_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage11_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage12_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage12_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage13_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage13_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage13_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage14_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage14_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage14_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage15_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage15_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage15_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage15_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage16_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage16_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage16_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage16_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage17_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage17_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage17_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage17_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage18_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage18_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage18_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage18_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage19_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage19_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage19_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage19_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage1_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage1_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage20_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage20_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage20_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage20_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage21_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage21_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage21_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage21_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage22_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage22_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage22_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage22_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage23_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage23_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage23_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage23_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage24_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage24_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage24_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage24_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage25_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage25_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage25_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage25_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage26_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage26_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage26_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage26_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage27_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage27_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage27_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage27_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage28_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage28_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage28_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage28_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage29_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage29_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage29_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage29_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage2_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage2_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage30_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage30_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage30_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage30_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage31_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage31_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage31_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage31_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage32_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage32_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage32_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage32_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage33_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage33_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage33_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage33_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage34_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage34_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage34_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage34_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage35_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage35_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage35_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage35_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage36_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage36_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage36_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage36_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage37_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage37_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage37_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage37_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage38_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage38_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage38_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage38_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage39_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage39_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage39_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage39_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage3_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage3_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage40_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage40_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage40_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage40_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage41_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage41_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage41_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage41_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage42_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage42_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage42_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage42_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage43_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage43_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage43_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage43_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage44_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage44_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage44_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage44_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage45_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage45_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage45_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage45_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage46_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage46_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage46_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage46_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage47_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage47_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage47_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage47_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage48_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage48_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage48_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage48_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage49_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage49_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage49_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage49_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage4_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage4_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage50_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage50_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage50_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage50_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage51_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage51_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage51_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage51_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage52_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage52_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage52_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage52_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage53_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage53_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage53_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage53_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage54_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage54_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage54_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage54_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage55_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage55_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage55_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage55_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage56_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage56_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage56_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage56_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage57_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage57_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage57_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage57_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage58_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage58_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage58_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage58_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage59_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage59_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage59_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage59_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage5_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage5_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage60_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage60_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage60_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage60_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage61_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage61_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage61_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage61_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage62_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage62_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage62_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage62_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage63_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage63_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage63_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage63_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage6_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage6_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage7_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage7_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage8_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage8_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage8_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage9_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage9_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage9_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_state10_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state11_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state12_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state13_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state14_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state15_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state16_pp0_stage15_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state17_pp0_stage16_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state18_pp0_stage17_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state19_pp0_stage18_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start) begin ap_block_state1_pp0_stage0_iter0 <= (ap_const_logic_0 = ap_start); end process; ap_block_state20_pp0_stage19_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state21_pp0_stage20_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state22_pp0_stage21_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state23_pp0_stage22_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state24_pp0_stage23_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state25_pp0_stage24_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state26_pp0_stage25_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state27_pp0_stage26_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state28_pp0_stage27_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state29_pp0_stage28_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state2_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state30_pp0_stage29_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state31_pp0_stage30_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state32_pp0_stage31_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state33_pp0_stage32_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state34_pp0_stage33_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state35_pp0_stage34_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state36_pp0_stage35_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state37_pp0_stage36_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state38_pp0_stage37_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state39_pp0_stage38_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state3_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state40_pp0_stage39_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state41_pp0_stage40_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state42_pp0_stage41_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state43_pp0_stage42_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state44_pp0_stage43_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state45_pp0_stage44_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state46_pp0_stage45_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state47_pp0_stage46_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state48_pp0_stage47_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state49_pp0_stage48_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state4_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state50_pp0_stage49_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state51_pp0_stage50_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state52_pp0_stage51_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state53_pp0_stage52_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state54_pp0_stage53_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state55_pp0_stage54_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state56_pp0_stage55_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state57_pp0_stage56_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state58_pp0_stage57_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state59_pp0_stage58_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state5_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state60_pp0_stage59_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state61_pp0_stage60_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state62_pp0_stage61_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state63_pp0_stage62_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state64_pp0_stage63_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state65_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state6_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state7_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state8_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state9_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_done_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_ce, ap_block_pp0_stage0_flag00011001) begin if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1); ap_enable_reg_pp0_iter0_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0_reg) begin if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then ap_enable_reg_pp0_iter0 <= ap_start; else ap_enable_reg_pp0_iter0 <= ap_enable_reg_pp0_iter0_reg; end if; end process; ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_idle_pp0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1) begin if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then ap_idle_pp0 <= ap_const_logic_1; else ap_idle_pp0 <= ap_const_logic_0; end if; end process; ap_idle_pp0_0to0_assign_proc : process(ap_enable_reg_pp0_iter0) begin if ((ap_const_logic_0 = ap_enable_reg_pp0_iter0)) then ap_idle_pp0_0to0 <= ap_const_logic_1; else ap_idle_pp0_0to0 <= ap_const_logic_0; end if; end process; ap_idle_pp0_1to1_assign_proc : process(ap_enable_reg_pp0_iter1) begin if ((ap_const_logic_0 = ap_enable_reg_pp0_iter1)) then ap_idle_pp0_1to1 <= ap_const_logic_1; else ap_idle_pp0_1to1 <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to0) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to0))) then ap_reset_idle_pp0 <= ap_const_logic_1; else ap_reset_idle_pp0 <= ap_const_logic_0; end if; end process; ap_return <= (tmp63_fu_1071_p2 or tmp_reg_1323); contacts_V_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage63, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000) begin if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_7E; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_7C; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_7A; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_78; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_76; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_74; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_72; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_70; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_6E; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_6C; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_6A; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_68; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_66; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_64; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_62; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_60; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_5E; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_5C; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_5A; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_58; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_56; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_54; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_52; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_50; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_4E; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_4C; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_4A; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_48; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_46; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_44; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_42; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_40; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_3E; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_3C; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_3A; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_38; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_36; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_34; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_32; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_30; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_2E; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_2C; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_2A; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_28; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_26; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_24; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_22; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_20; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_1E; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_1C; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_1A; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_18; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_16; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_14; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_12; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_10; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_E; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_C; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_A; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_8; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_6; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_4; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_2; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then contacts_V_address0 <= ap_const_lv7_0; else contacts_V_address0 <= "XXXXXXX"; end if; else contacts_V_address0 <= "XXXXXXX"; end if; end process; contacts_V_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage63, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000) begin if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_7F; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_7D; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_7B; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_79; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_77; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_75; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_73; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_71; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_6F; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_6D; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_6B; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_69; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_67; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_65; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_63; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_61; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_5F; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_5D; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_5B; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_59; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_57; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_55; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_53; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_51; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_4F; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_4D; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_4B; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_49; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_47; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_45; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_43; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_41; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_3F; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_3D; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_3B; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_39; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_37; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_35; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_33; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_31; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_2F; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_2D; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_2B; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_29; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_27; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_25; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_23; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_21; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_1F; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_1D; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_1B; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_19; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_17; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_15; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_13; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_11; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_F; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_D; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_B; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_9; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_7; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_5; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_3; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then contacts_V_address1 <= ap_const_lv7_1; else contacts_V_address1 <= "XXXXXXX"; end if; else contacts_V_address1 <= "XXXXXXX"; end if; end process; contacts_V_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage62_flag00011001, ap_block_pp0_stage0_flag00011001) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)))) then contacts_V_ce0 <= ap_const_logic_1; else contacts_V_ce0 <= ap_const_logic_0; end if; end process; contacts_V_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage62_flag00011001, ap_block_pp0_stage0_flag00011001) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)))) then contacts_V_ce1 <= ap_const_logic_1; else contacts_V_ce1 <= ap_const_logic_0; end if; end process; grp_fu_403_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage63, db_item_V_read_reg_1082, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_port_reg_db_item_V, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then grp_fu_403_p1 <= db_item_V_read_reg_1082; elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then grp_fu_403_p1 <= ap_port_reg_db_item_V; else grp_fu_403_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; grp_fu_403_p2 <= "1" when (contacts_V_q0 = grp_fu_403_p1) else "0"; grp_fu_409_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage63, db_item_V_read_reg_1082, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_port_reg_db_item_V, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then grp_fu_409_p1 <= db_item_V_read_reg_1082; elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then grp_fu_409_p1 <= ap_port_reg_db_item_V; else grp_fu_409_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; grp_fu_409_p2 <= "1" when (contacts_V_q1 = grp_fu_409_p1) else "0"; tmp100_fu_908_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp101_fu_930_p2 <= (tmp103_fu_924_p2 or tmp102_fu_920_p2); tmp102_fu_920_p2 <= (tmp_1_99_reg_1463 or tmp_1_100_reg_1468); tmp103_fu_924_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp104_fu_973_p2 <= (tmp108_fu_967_p2 or tmp105_reg_1488); tmp105_fu_951_p2 <= (tmp107_fu_945_p2 or tmp106_fu_941_p2); tmp106_fu_941_p2 <= (tmp_1_103_reg_1478 or tmp_1_104_reg_1483); tmp107_fu_945_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp108_fu_967_p2 <= (tmp110_fu_961_p2 or tmp109_fu_957_p2); tmp109_fu_957_p2 <= (tmp_1_107_reg_1493 or tmp_1_108_reg_1498); tmp10_fu_484_p2 <= (tmp14_fu_478_p2 or tmp11_reg_1128); tmp110_fu_961_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp111_fu_1061_p2 <= (tmp119_fu_1056_p2 or tmp112_reg_1533); tmp112_fu_1015_p2 <= (tmp116_fu_1009_p2 or tmp113_reg_1518); tmp113_fu_993_p2 <= (tmp115_fu_987_p2 or tmp114_fu_983_p2); tmp114_fu_983_p2 <= (tmp_1_111_reg_1508 or tmp_1_112_reg_1513); tmp115_fu_987_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp116_fu_1009_p2 <= (tmp118_fu_1003_p2 or tmp117_fu_999_p2); tmp117_fu_999_p2 <= (tmp_1_115_reg_1523 or tmp_1_116_reg_1528); tmp118_fu_1003_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp119_fu_1056_p2 <= (tmp123_fu_1050_p2 or tmp120_reg_1548); tmp11_fu_462_p2 <= (tmp13_fu_456_p2 or tmp12_fu_452_p2); tmp120_fu_1030_p2 <= (tmp122_fu_1024_p2 or tmp121_fu_1020_p2); tmp121_fu_1020_p2 <= (tmp_1_119_reg_1538 or tmp_1_120_reg_1543); tmp122_fu_1024_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp123_fu_1050_p2 <= (tmp125_fu_1044_p2 or tmp124_fu_1040_p2); tmp124_fu_1040_p2 <= (tmp_1_123_reg_1553 or tmp_1_124_reg_1558); tmp125_fu_1044_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp12_fu_452_p2 <= (tmp_1_8_reg_1118 or tmp_1_9_reg_1123); tmp13_fu_456_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp14_fu_478_p2 <= (tmp16_fu_472_p2 or tmp15_fu_468_p2); tmp15_fu_468_p2 <= (tmp_1_11_reg_1133 or tmp_1_12_reg_1138); tmp16_fu_472_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp17_fu_568_p2 <= (tmp25_fu_563_p2 or tmp18_reg_1173); tmp18_fu_526_p2 <= (tmp22_fu_520_p2 or tmp19_reg_1158); tmp19_fu_504_p2 <= (tmp21_fu_498_p2 or tmp20_fu_494_p2); tmp1_fu_705_p2 <= (tmp17_reg_1203 or tmp2_reg_1143); tmp20_fu_494_p2 <= (tmp_1_15_reg_1148 or tmp_1_16_reg_1153); tmp21_fu_498_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp22_fu_520_p2 <= (tmp24_fu_514_p2 or tmp23_fu_510_p2); tmp23_fu_510_p2 <= (tmp_1_19_reg_1163 or tmp_1_20_reg_1168); tmp24_fu_514_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp25_fu_563_p2 <= (tmp29_fu_557_p2 or tmp26_reg_1188); tmp26_fu_541_p2 <= (tmp28_fu_535_p2 or tmp27_fu_531_p2); tmp27_fu_531_p2 <= (tmp_1_23_reg_1178 or tmp_1_24_reg_1183); tmp28_fu_535_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp29_fu_557_p2 <= (tmp31_fu_551_p2 or tmp30_fu_547_p2); tmp2_fu_489_p2 <= (tmp10_fu_484_p2 or tmp3_reg_1113); tmp30_fu_547_p2 <= (tmp_1_27_reg_1193 or tmp_1_28_reg_1198); tmp31_fu_551_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp32_fu_735_p2 <= (tmp48_fu_730_p2 or tmp33_reg_1263); tmp33_fu_647_p2 <= (tmp41_fu_642_p2 or tmp34_reg_1233); tmp34_fu_605_p2 <= (tmp38_fu_599_p2 or tmp35_reg_1218); tmp35_fu_583_p2 <= (tmp37_fu_577_p2 or tmp36_fu_573_p2); tmp36_fu_573_p2 <= (tmp_1_31_reg_1208 or tmp_1_32_reg_1213); tmp37_fu_577_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp38_fu_599_p2 <= (tmp40_fu_593_p2 or tmp39_fu_589_p2); tmp39_fu_589_p2 <= (tmp_1_35_reg_1223 or tmp_1_36_reg_1228); tmp3_fu_447_p2 <= (tmp7_fu_441_p2 or tmp4_reg_1098); tmp40_fu_593_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp41_fu_642_p2 <= (tmp45_fu_636_p2 or tmp42_reg_1248); tmp42_fu_620_p2 <= (tmp44_fu_614_p2 or tmp43_fu_610_p2); tmp43_fu_610_p2 <= (tmp_1_39_reg_1238 or tmp_1_40_reg_1243); tmp44_fu_614_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp45_fu_636_p2 <= (tmp47_fu_630_p2 or tmp46_fu_626_p2); tmp46_fu_626_p2 <= (tmp_1_43_reg_1253 or tmp_1_44_reg_1258); tmp47_fu_630_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp48_fu_730_p2 <= (tmp56_fu_725_p2 or tmp49_reg_1293); tmp49_fu_684_p2 <= (tmp53_fu_678_p2 or tmp50_reg_1278); tmp4_fu_425_p2 <= (tmp6_fu_419_p2 or tmp5_fu_415_p2); tmp50_fu_662_p2 <= (tmp52_fu_656_p2 or tmp51_fu_652_p2); tmp51_fu_652_p2 <= (tmp_1_47_reg_1268 or tmp_1_48_reg_1273); tmp52_fu_656_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp53_fu_678_p2 <= (tmp55_fu_672_p2 or tmp54_fu_668_p2); tmp54_fu_668_p2 <= (tmp_1_51_reg_1283 or tmp_1_52_reg_1288); tmp55_fu_672_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp56_fu_725_p2 <= (tmp60_fu_719_p2 or tmp57_reg_1308); tmp57_fu_699_p2 <= (tmp59_fu_693_p2 or tmp58_fu_689_p2); tmp58_fu_689_p2 <= (tmp_1_55_reg_1298 or tmp_1_56_reg_1303); tmp59_fu_693_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp5_fu_415_p2 <= (tmp_1_reg_1088 or tmp_1_1_reg_1093); tmp60_fu_719_p2 <= (tmp62_fu_713_p2 or tmp61_fu_709_p2); tmp61_fu_709_p2 <= (tmp_1_59_reg_1313 or tmp_1_60_reg_1318); tmp62_fu_713_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp63_fu_1071_p2 <= (tmp95_fu_1066_p2 or tmp64_fu_1036_p2); tmp64_fu_1036_p2 <= (tmp80_reg_1443 or tmp65_reg_1383); tmp65_fu_820_p2 <= (tmp73_fu_815_p2 or tmp66_reg_1353); tmp66_fu_778_p2 <= (tmp70_fu_772_p2 or tmp67_reg_1338); tmp67_fu_756_p2 <= (tmp69_fu_750_p2 or tmp68_fu_746_p2); tmp68_fu_746_p2 <= (tmp_1_63_reg_1328 or tmp_1_64_reg_1333); tmp69_fu_750_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp6_fu_419_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp70_fu_772_p2 <= (tmp72_fu_766_p2 or tmp71_fu_762_p2); tmp71_fu_762_p2 <= (tmp_1_67_reg_1343 or tmp_1_68_reg_1348); tmp72_fu_766_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp73_fu_815_p2 <= (tmp77_fu_809_p2 or tmp74_reg_1368); tmp74_fu_793_p2 <= (tmp76_fu_787_p2 or tmp75_fu_783_p2); tmp75_fu_783_p2 <= (tmp_1_71_reg_1358 or tmp_1_72_reg_1363); tmp76_fu_787_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp77_fu_809_p2 <= (tmp79_fu_803_p2 or tmp78_fu_799_p2); tmp78_fu_799_p2 <= (tmp_1_75_reg_1373 or tmp_1_76_reg_1378); tmp79_fu_803_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp7_fu_441_p2 <= (tmp9_fu_435_p2 or tmp8_fu_431_p2); tmp80_fu_899_p2 <= (tmp88_fu_894_p2 or tmp81_reg_1413); tmp81_fu_857_p2 <= (tmp85_fu_851_p2 or tmp82_reg_1398); tmp82_fu_835_p2 <= (tmp84_fu_829_p2 or tmp83_fu_825_p2); tmp83_fu_825_p2 <= (tmp_1_79_reg_1388 or tmp_1_80_reg_1393); tmp84_fu_829_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp85_fu_851_p2 <= (tmp87_fu_845_p2 or tmp86_fu_841_p2); tmp86_fu_841_p2 <= (tmp_1_83_reg_1403 or tmp_1_84_reg_1408); tmp87_fu_845_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp88_fu_894_p2 <= (tmp92_fu_888_p2 or tmp89_reg_1428); tmp89_fu_872_p2 <= (tmp91_fu_866_p2 or tmp90_fu_862_p2); tmp8_fu_431_p2 <= (tmp_1_4_reg_1103 or tmp_1_5_reg_1108); tmp90_fu_862_p2 <= (tmp_1_87_reg_1418 or tmp_1_88_reg_1423); tmp91_fu_866_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp92_fu_888_p2 <= (tmp94_fu_882_p2 or tmp93_fu_878_p2); tmp93_fu_878_p2 <= (tmp_1_91_reg_1433 or tmp_1_92_reg_1438); tmp94_fu_882_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp95_fu_1066_p2 <= (tmp111_fu_1061_p2 or tmp96_reg_1503); tmp96_fu_978_p2 <= (tmp104_fu_973_p2 or tmp97_reg_1473); tmp97_fu_936_p2 <= (tmp101_fu_930_p2 or tmp98_reg_1458); tmp98_fu_914_p2 <= (tmp100_fu_908_p2 or tmp99_fu_904_p2); tmp99_fu_904_p2 <= (tmp_1_95_reg_1448 or tmp_1_96_reg_1453); tmp9_fu_435_p2 <= (grp_fu_403_p2 or grp_fu_409_p2); tmp_fu_740_p2 <= (tmp32_fu_735_p2 or tmp1_fu_705_p2); end behav;
gpl-3.0
mcoughli/root_of_trust
operational_os/hls/contact_discovery_axi/solution1/syn/vhdl/contact_discoverycud.vhd
3
4162
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity contact_discoverycud_ram is generic( mem_type : string := "block"; dwidth : integer := 8; awidth : integer := 15; mem_size : integer := 19200 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; d0 : in std_logic_vector(dwidth-1 downto 0); we0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); addr1 : in std_logic_vector(awidth-1 downto 0); ce1 : in std_logic; q1 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of contact_discoverycud_ram is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); signal addr1_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); shared variable ram : mem_array := (others=>(others=>'0')); attribute syn_ramstyle : string; attribute syn_ramstyle of ram : variable is "block_ram"; attribute ram_style : string; attribute ram_style of ram : variable is mem_type; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; p_memory_access_0: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then if (we0 = '1') then ram(CONV_INTEGER(addr0_tmp)) := d0; end if; q0 <= ram(CONV_INTEGER(addr0_tmp)); end if; end if; end process; memory_access_guard_1: process (addr1) begin addr1_tmp <= addr1; --synthesis translate_off if (CONV_INTEGER(addr1) > mem_size-1) then addr1_tmp <= (others => '0'); else addr1_tmp <= addr1; end if; --synthesis translate_on end process; p_memory_access_1: process (clk) begin if (clk'event and clk = '1') then if (ce1 = '1') then q1 <= ram(CONV_INTEGER(addr1_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity contact_discoverycud is generic ( DataWidth : INTEGER := 8; AddressRange : INTEGER := 19200; AddressWidth : INTEGER := 15); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of contact_discoverycud is component contact_discoverycud_ram is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR; we0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR; addr1 : IN STD_LOGIC_VECTOR; ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR); end component; begin contact_discoverycud_ram_U : component contact_discoverycud_ram port map ( clk => clk, addr0 => address0, ce0 => ce0, d0 => d0, we0 => we0, q0 => q0, addr1 => address1, ce1 => ce1, q1 => q1); end architecture;
gpl-3.0
mcoughli/root_of_trust
operational_os/hls/contact_discovery_axi_experimental/solution1/impl/ip/hdl/vhdl/contact_discovery.vhd
3
282362
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity contact_discovery is generic ( C_M_AXI_DB_MEM_V_ADDR_WIDTH : INTEGER := 64; C_M_AXI_DB_MEM_V_ID_WIDTH : INTEGER := 1; C_M_AXI_DB_MEM_V_AWUSER_WIDTH : INTEGER := 1; C_M_AXI_DB_MEM_V_DATA_WIDTH : INTEGER := 512; C_M_AXI_DB_MEM_V_WUSER_WIDTH : INTEGER := 1; C_M_AXI_DB_MEM_V_ARUSER_WIDTH : INTEGER := 1; C_M_AXI_DB_MEM_V_RUSER_WIDTH : INTEGER := 1; C_M_AXI_DB_MEM_V_BUSER_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_ADDR_WIDTH : INTEGER := 64; C_M_AXI_RESULTS_OUT_ID_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_AWUSER_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_DATA_WIDTH : INTEGER := 32; C_M_AXI_RESULTS_OUT_WUSER_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_ARUSER_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_RUSER_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_BUSER_WIDTH : INTEGER := 1; C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 7; C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32; C_M_AXI_RESULTS_OUT_TARGET_ADDR : INTEGER := 0; C_M_AXI_DB_MEM_V_USER_VALUE : INTEGER := 0; C_M_AXI_RESULTS_OUT_PROT_VALUE : INTEGER := 0; C_M_AXI_DB_MEM_V_TARGET_ADDR : INTEGER := 0; C_M_AXI_DB_MEM_V_PROT_VALUE : INTEGER := 0; C_M_AXI_DB_MEM_V_CACHE_VALUE : INTEGER := 3; C_M_AXI_RESULTS_OUT_CACHE_VALUE : INTEGER := 3; C_M_AXI_RESULTS_OUT_USER_VALUE : INTEGER := 0 ); port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; m_axi_db_mem_V_AWVALID : OUT STD_LOGIC; m_axi_db_mem_V_AWREADY : IN STD_LOGIC; m_axi_db_mem_V_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ADDR_WIDTH-1 downto 0); m_axi_db_mem_V_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ID_WIDTH-1 downto 0); m_axi_db_mem_V_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0); m_axi_db_mem_V_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_db_mem_V_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_db_mem_V_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_AWUSER_WIDTH-1 downto 0); m_axi_db_mem_V_WVALID : OUT STD_LOGIC; m_axi_db_mem_V_WREADY : IN STD_LOGIC; m_axi_db_mem_V_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_DATA_WIDTH-1 downto 0); m_axi_db_mem_V_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_DATA_WIDTH/8-1 downto 0); m_axi_db_mem_V_WLAST : OUT STD_LOGIC; m_axi_db_mem_V_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ID_WIDTH-1 downto 0); m_axi_db_mem_V_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_WUSER_WIDTH-1 downto 0); m_axi_db_mem_V_ARVALID : OUT STD_LOGIC; m_axi_db_mem_V_ARREADY : IN STD_LOGIC; m_axi_db_mem_V_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ADDR_WIDTH-1 downto 0); m_axi_db_mem_V_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ID_WIDTH-1 downto 0); m_axi_db_mem_V_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0); m_axi_db_mem_V_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_db_mem_V_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_db_mem_V_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ARUSER_WIDTH-1 downto 0); m_axi_db_mem_V_RVALID : IN STD_LOGIC; m_axi_db_mem_V_RREADY : OUT STD_LOGIC; m_axi_db_mem_V_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_DATA_WIDTH-1 downto 0); m_axi_db_mem_V_RLAST : IN STD_LOGIC; m_axi_db_mem_V_RID : IN STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ID_WIDTH-1 downto 0); m_axi_db_mem_V_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_RUSER_WIDTH-1 downto 0); m_axi_db_mem_V_RRESP : IN STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_BVALID : IN STD_LOGIC; m_axi_db_mem_V_BREADY : OUT STD_LOGIC; m_axi_db_mem_V_BRESP : IN STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_BID : IN STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ID_WIDTH-1 downto 0); m_axi_db_mem_V_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_BUSER_WIDTH-1 downto 0); m_axi_results_out_AWVALID : OUT STD_LOGIC; m_axi_results_out_AWREADY : IN STD_LOGIC; m_axi_results_out_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ADDR_WIDTH-1 downto 0); m_axi_results_out_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ID_WIDTH-1 downto 0); m_axi_results_out_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0); m_axi_results_out_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_results_out_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_results_out_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_AWUSER_WIDTH-1 downto 0); m_axi_results_out_WVALID : OUT STD_LOGIC; m_axi_results_out_WREADY : IN STD_LOGIC; m_axi_results_out_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_DATA_WIDTH-1 downto 0); m_axi_results_out_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_DATA_WIDTH/8-1 downto 0); m_axi_results_out_WLAST : OUT STD_LOGIC; m_axi_results_out_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ID_WIDTH-1 downto 0); m_axi_results_out_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_WUSER_WIDTH-1 downto 0); m_axi_results_out_ARVALID : OUT STD_LOGIC; m_axi_results_out_ARREADY : IN STD_LOGIC; m_axi_results_out_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ADDR_WIDTH-1 downto 0); m_axi_results_out_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ID_WIDTH-1 downto 0); m_axi_results_out_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0); m_axi_results_out_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_results_out_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_results_out_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ARUSER_WIDTH-1 downto 0); m_axi_results_out_RVALID : IN STD_LOGIC; m_axi_results_out_RREADY : OUT STD_LOGIC; m_axi_results_out_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_DATA_WIDTH-1 downto 0); m_axi_results_out_RLAST : IN STD_LOGIC; m_axi_results_out_RID : IN STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ID_WIDTH-1 downto 0); m_axi_results_out_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_RUSER_WIDTH-1 downto 0); m_axi_results_out_RRESP : IN STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_BVALID : IN STD_LOGIC; m_axi_results_out_BREADY : OUT STD_LOGIC; m_axi_results_out_BRESP : IN STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_BID : IN STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ID_WIDTH-1 downto 0); m_axi_results_out_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_BUSER_WIDTH-1 downto 0); s_axi_AXILiteS_AWVALID : IN STD_LOGIC; s_axi_AXILiteS_AWREADY : OUT STD_LOGIC; s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0); s_axi_AXILiteS_WVALID : IN STD_LOGIC; s_axi_AXILiteS_WREADY : OUT STD_LOGIC; s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0); s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0); s_axi_AXILiteS_ARVALID : IN STD_LOGIC; s_axi_AXILiteS_ARREADY : OUT STD_LOGIC; s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0); s_axi_AXILiteS_RVALID : OUT STD_LOGIC; s_axi_AXILiteS_RREADY : IN STD_LOGIC; s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0); s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_AXILiteS_BVALID : OUT STD_LOGIC; s_axi_AXILiteS_BREADY : IN STD_LOGIC; s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); interrupt : OUT STD_LOGIC ); end; architecture behav of contact_discovery is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "contact_discovery,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xczu9eg-ffvb1156-1-i,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=67108871,HLS_SYN_TPT=none,HLS_SYN_MEM=33,HLS_SYN_DSP=0,HLS_SYN_FF=4501,HLS_SYN_LUT=5277}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001"; constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010"; constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100"; constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000"; constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000"; constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000"; constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000"; constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000"; constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000"; constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000"; constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000"; constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000"; constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000"; constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000"; constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000"; constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000"; constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000"; constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000"; constant ap_ST_fsm_pp0_stage16 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000"; constant ap_ST_fsm_pp0_stage17 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000"; constant ap_ST_fsm_pp0_stage18 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000"; constant ap_ST_fsm_pp0_stage19 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000"; constant ap_ST_fsm_pp0_stage20 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000"; constant ap_ST_fsm_pp0_stage21 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000"; constant ap_ST_fsm_pp0_stage22 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000"; constant ap_ST_fsm_pp0_stage23 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000"; constant ap_ST_fsm_pp0_stage24 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000"; constant ap_ST_fsm_pp0_stage25 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000"; constant ap_ST_fsm_pp0_stage26 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000"; constant ap_ST_fsm_pp0_stage27 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000"; constant ap_ST_fsm_pp0_stage28 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage29 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage30 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage31 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage32 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage33 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage34 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage35 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage36 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage37 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage38 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage39 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage40 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage41 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage42 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage43 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage44 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage45 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage46 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage47 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage48 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage49 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage50 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage51 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage52 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage53 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage54 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage55 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage56 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage57 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage58 : STD_LOGIC_VECTOR (69 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage59 : STD_LOGIC_VECTOR (69 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage60 : STD_LOGIC_VECTOR (69 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage61 : STD_LOGIC_VECTOR (69 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage62 : STD_LOGIC_VECTOR (69 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage63 : STD_LOGIC_VECTOR (69 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_state83 : STD_LOGIC_VECTOR (69 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_state84 : STD_LOGIC_VECTOR (69 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_state85 : STD_LOGIC_VECTOR (69 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_state86 : STD_LOGIC_VECTOR (69 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_boolean_1 : BOOLEAN := true; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_boolean_0 : BOOLEAN := false; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_41 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000001"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010"; constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011"; constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100"; constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101"; constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110"; constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111"; constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000"; constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001"; constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010"; constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011"; constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100"; constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101"; constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110"; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000"; constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001"; constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010"; constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011"; constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100"; constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101"; constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110"; constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111"; constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000"; constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001"; constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010"; constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011"; constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100"; constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101"; constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110"; constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111"; constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000"; constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001"; constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010"; constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011"; constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100"; constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101"; constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110"; constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111"; constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000"; constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001"; constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010"; constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011"; constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100"; constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101"; constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110"; constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111"; constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv24_0 : STD_LOGIC_VECTOR (23 downto 0) := "000000000000000000000000"; constant ap_const_lv32_43 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000011"; constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv32_44 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000100"; constant ap_const_lv25_0 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000000"; constant ap_const_lv24_1 : STD_LOGIC_VECTOR (23 downto 0) := "000000000000000000000001"; constant ap_const_lv32_45 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000101"; constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; constant ap_const_lv512_lc_1 : STD_LOGIC_VECTOR (511 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; signal ap_rst_n_inv : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_state1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none"; signal ap_ready : STD_LOGIC; signal operation : STD_LOGIC_VECTOR (31 downto 0); signal operation_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal operation_ap_vld : STD_LOGIC; signal operation_in_sig : STD_LOGIC_VECTOR (31 downto 0); signal operation_ap_vld_preg : STD_LOGIC := '0'; signal operation_ap_vld_in_sig : STD_LOGIC; signal contact_in_V : STD_LOGIC_VECTOR (511 downto 0); signal offset : STD_LOGIC_VECTOR (63 downto 0); signal db_size_in : STD_LOGIC_VECTOR (31 downto 0); signal error_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal error_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0); signal error_out_1_vld_reg : STD_LOGIC := '0'; signal error_out_1_vld_in : STD_LOGIC; signal error_out_1_ack_in : STD_LOGIC; signal contacts_size_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal contacts_size_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0); signal contacts_size_out_1_vld_reg : STD_LOGIC := '0'; signal contacts_size_out_1_vld_in : STD_LOGIC; signal contacts_size_out_1_ack_in : STD_LOGIC; signal contacts_size : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal contacts_V_address0 : STD_LOGIC_VECTOR (6 downto 0); signal contacts_V_ce0 : STD_LOGIC; signal contacts_V_we0 : STD_LOGIC; signal contacts_V_q0 : STD_LOGIC_VECTOR (511 downto 0); signal contacts_V_ce1 : STD_LOGIC; signal contacts_V_q1 : STD_LOGIC_VECTOR (511 downto 0); signal operation_blk_n : STD_LOGIC; signal db_mem_V_blk_n_AR : STD_LOGIC; signal ap_CS_fsm_pp0_stage1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none"; signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0'; signal ap_block_pp0_stage1_flag00000000 : BOOLEAN; signal tmp_127_reg_356 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_8_reg_365 : STD_LOGIC_VECTOR (0 downto 0); signal db_mem_V_blk_n_R : STD_LOGIC; signal ap_CS_fsm_pp0_stage8 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none"; signal ap_block_pp0_stage8_flag00000000 : BOOLEAN; signal results_out_blk_n_AW : STD_LOGIC; signal ap_CS_fsm_pp0_stage9 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none"; signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0'; signal ap_block_pp0_stage9_flag00000000 : BOOLEAN; signal ap_reg_pp0_iter1_tmp_127_reg_356 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_pp0_iter1_tmp_8_reg_365 : STD_LOGIC_VECTOR (0 downto 0); signal results_out_blk_n_W : STD_LOGIC; signal ap_CS_fsm_pp0_stage10 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none"; signal ap_block_pp0_stage10_flag00000000 : BOOLEAN; signal results_out_blk_n_B : STD_LOGIC; signal ap_CS_fsm_pp0_stage15 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none"; signal ap_block_pp0_stage15_flag00000000 : BOOLEAN; signal db_mem_V_AWREADY : STD_LOGIC; signal db_mem_V_WREADY : STD_LOGIC; signal db_mem_V_ARVALID : STD_LOGIC; signal db_mem_V_ARREADY : STD_LOGIC; signal db_mem_V_RVALID : STD_LOGIC; signal db_mem_V_RREADY : STD_LOGIC; signal db_mem_V_RDATA : STD_LOGIC_VECTOR (511 downto 0); signal db_mem_V_RLAST : STD_LOGIC; signal db_mem_V_RID : STD_LOGIC_VECTOR (0 downto 0); signal db_mem_V_RUSER : STD_LOGIC_VECTOR (0 downto 0); signal db_mem_V_RRESP : STD_LOGIC_VECTOR (1 downto 0); signal db_mem_V_BVALID : STD_LOGIC; signal db_mem_V_BRESP : STD_LOGIC_VECTOR (1 downto 0); signal db_mem_V_BID : STD_LOGIC_VECTOR (0 downto 0); signal db_mem_V_BUSER : STD_LOGIC_VECTOR (0 downto 0); signal results_out_AWVALID : STD_LOGIC; signal results_out_AWREADY : STD_LOGIC; signal results_out_WVALID : STD_LOGIC; signal results_out_WREADY : STD_LOGIC; signal results_out_WDATA : STD_LOGIC_VECTOR (7 downto 0); signal results_out_ARREADY : STD_LOGIC; signal results_out_RVALID : STD_LOGIC; signal results_out_RDATA : STD_LOGIC_VECTOR (7 downto 0); signal results_out_RLAST : STD_LOGIC; signal results_out_RID : STD_LOGIC_VECTOR (0 downto 0); signal results_out_RUSER : STD_LOGIC_VECTOR (0 downto 0); signal results_out_RRESP : STD_LOGIC_VECTOR (1 downto 0); signal results_out_BVALID : STD_LOGIC; signal results_out_BREADY : STD_LOGIC; signal results_out_BRESP : STD_LOGIC_VECTOR (1 downto 0); signal results_out_BID : STD_LOGIC_VECTOR (0 downto 0); signal results_out_BUSER : STD_LOGIC_VECTOR (0 downto 0); signal database_index_reg_189 : STD_LOGIC_VECTOR (23 downto 0); signal ap_block_state1 : BOOLEAN; signal contact_in_V_read_reg_325 : STD_LOGIC_VECTOR (511 downto 0); signal operation_read_read_fu_130_p2 : STD_LOGIC_VECTOR (31 downto 0); signal contacts_size_load_reg_334 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_126_fu_230_p1 : STD_LOGIC_VECTOR (24 downto 0); signal tmp_126_reg_343 : STD_LOGIC_VECTOR (24 downto 0); signal tmp_5_fu_253_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none"; signal icmp_fu_243_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_127_fu_264_p3 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage0 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none"; signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN; signal ap_block_state67_pp0_stage0_iter1 : BOOLEAN; signal ap_block_pp0_stage0_flag00011001 : BOOLEAN; signal database_index_1_fu_272_p2 : STD_LOGIC_VECTOR (23 downto 0); signal database_index_1_reg_360 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_8_fu_290_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sum_fu_295_p2 : STD_LOGIC_VECTOR (24 downto 0); signal sum_reg_369 : STD_LOGIC_VECTOR (24 downto 0); signal results_out_addr_reg_374 : STD_LOGIC_VECTOR (63 downto 0); signal ap_reg_pp0_iter1_results_out_addr_reg_374 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_state4_pp0_stage1_iter0 : BOOLEAN; signal ap_sig_ioackin_db_mem_V_ARREADY : STD_LOGIC; signal ap_predicate_op161_readreq_state4 : BOOLEAN; signal ap_block_state4_io : BOOLEAN; signal ap_block_state68_pp0_stage1_iter1 : BOOLEAN; signal ap_block_pp0_stage1_flag00011001 : BOOLEAN; signal db_mem_V_addr_read_reg_385 : STD_LOGIC_VECTOR (511 downto 0); signal ap_predicate_op168_read_state11 : BOOLEAN; signal ap_block_state11_pp0_stage8_iter0 : BOOLEAN; signal ap_block_state75_pp0_stage8_iter1 : BOOLEAN; signal ap_block_pp0_stage8_flag00011001 : BOOLEAN; signal grp_match_db_contact_fu_212_ap_return : STD_LOGIC_VECTOR (0 downto 0); signal tmp_s_reg_390 : STD_LOGIC_VECTOR (0 downto 0); signal ap_block_state12_pp0_stage9_iter0 : BOOLEAN; signal ap_block_state76_pp0_stage9_iter1 : BOOLEAN; signal ap_sig_ioackin_results_out_AWREADY : STD_LOGIC; signal ap_predicate_op234_writereq_state76 : BOOLEAN; signal ap_block_state76_io : BOOLEAN; signal ap_block_pp0_stage9_flag00011001 : BOOLEAN; signal ap_block_pp0_stage0_flag00011011 : BOOLEAN; signal ap_predicate_tran3to83_state3 : BOOLEAN; signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC; signal ap_block_state66_pp0_stage63_iter0 : BOOLEAN; signal ap_block_pp0_stage63_flag00011011 : BOOLEAN; signal ap_CS_fsm_pp0_stage63 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage63 : signal is "none"; signal ap_block_state18_pp0_stage15_iter0 : BOOLEAN; signal ap_predicate_op241_writeresp_state82 : BOOLEAN; signal ap_block_state82_pp0_stage15_iter1 : BOOLEAN; signal ap_block_pp0_stage15_flag00011011 : BOOLEAN; signal grp_match_db_contact_fu_212_ap_start : STD_LOGIC; signal grp_match_db_contact_fu_212_ap_done : STD_LOGIC; signal grp_match_db_contact_fu_212_ap_idle : STD_LOGIC; signal grp_match_db_contact_fu_212_ap_ready : STD_LOGIC; signal grp_match_db_contact_fu_212_ap_ce : STD_LOGIC; signal grp_match_db_contact_fu_212_contacts_V_address0 : STD_LOGIC_VECTOR (6 downto 0); signal grp_match_db_contact_fu_212_contacts_V_ce0 : STD_LOGIC; signal grp_match_db_contact_fu_212_contacts_V_address1 : STD_LOGIC_VECTOR (6 downto 0); signal grp_match_db_contact_fu_212_contacts_V_ce1 : STD_LOGIC; signal ap_predicate_op169_call_state12 : BOOLEAN; signal ap_predicate_op170_call_state13 : BOOLEAN; signal ap_predicate_op171_call_state14 : BOOLEAN; signal ap_predicate_op172_call_state15 : BOOLEAN; signal ap_predicate_op173_call_state16 : BOOLEAN; signal ap_predicate_op174_call_state17 : BOOLEAN; signal ap_predicate_op175_call_state18 : BOOLEAN; signal ap_predicate_op176_call_state19 : BOOLEAN; signal ap_predicate_op177_call_state20 : BOOLEAN; signal ap_predicate_op178_call_state21 : BOOLEAN; signal ap_predicate_op179_call_state22 : BOOLEAN; signal ap_predicate_op180_call_state23 : BOOLEAN; signal ap_predicate_op181_call_state24 : BOOLEAN; signal ap_predicate_op182_call_state25 : BOOLEAN; signal ap_predicate_op183_call_state26 : BOOLEAN; signal ap_predicate_op184_call_state27 : BOOLEAN; signal ap_predicate_op185_call_state28 : BOOLEAN; signal ap_predicate_op186_call_state29 : BOOLEAN; signal ap_predicate_op187_call_state30 : BOOLEAN; signal ap_predicate_op188_call_state31 : BOOLEAN; signal ap_predicate_op189_call_state32 : BOOLEAN; signal ap_predicate_op190_call_state33 : BOOLEAN; signal ap_predicate_op191_call_state34 : BOOLEAN; signal ap_predicate_op192_call_state35 : BOOLEAN; signal ap_predicate_op193_call_state36 : BOOLEAN; signal ap_predicate_op194_call_state37 : BOOLEAN; signal ap_predicate_op195_call_state38 : BOOLEAN; signal ap_predicate_op196_call_state39 : BOOLEAN; signal ap_predicate_op197_call_state40 : BOOLEAN; signal ap_predicate_op198_call_state41 : BOOLEAN; signal ap_predicate_op199_call_state42 : BOOLEAN; signal ap_predicate_op200_call_state43 : BOOLEAN; signal ap_predicate_op201_call_state44 : BOOLEAN; signal ap_predicate_op202_call_state45 : BOOLEAN; signal ap_predicate_op203_call_state46 : BOOLEAN; signal ap_predicate_op204_call_state47 : BOOLEAN; signal ap_predicate_op205_call_state48 : BOOLEAN; signal ap_predicate_op206_call_state49 : BOOLEAN; signal ap_predicate_op207_call_state50 : BOOLEAN; signal ap_predicate_op208_call_state51 : BOOLEAN; signal ap_predicate_op209_call_state52 : BOOLEAN; signal ap_predicate_op210_call_state53 : BOOLEAN; signal ap_predicate_op211_call_state54 : BOOLEAN; signal ap_predicate_op212_call_state55 : BOOLEAN; signal ap_predicate_op213_call_state56 : BOOLEAN; signal ap_predicate_op214_call_state57 : BOOLEAN; signal ap_predicate_op215_call_state58 : BOOLEAN; signal ap_predicate_op216_call_state59 : BOOLEAN; signal ap_predicate_op217_call_state60 : BOOLEAN; signal ap_predicate_op218_call_state61 : BOOLEAN; signal ap_predicate_op219_call_state62 : BOOLEAN; signal ap_predicate_op220_call_state63 : BOOLEAN; signal ap_predicate_op221_call_state64 : BOOLEAN; signal ap_predicate_op222_call_state65 : BOOLEAN; signal ap_predicate_op223_call_state66 : BOOLEAN; signal ap_predicate_op224_call_state67 : BOOLEAN; signal ap_predicate_op225_call_state68 : BOOLEAN; signal ap_predicate_op226_call_state69 : BOOLEAN; signal ap_predicate_op227_call_state70 : BOOLEAN; signal ap_predicate_op228_call_state71 : BOOLEAN; signal ap_predicate_op229_call_state72 : BOOLEAN; signal ap_predicate_op230_call_state73 : BOOLEAN; signal ap_predicate_op231_call_state74 : BOOLEAN; signal ap_predicate_op232_call_state75 : BOOLEAN; signal ap_block_state13_pp0_stage10_iter0_ignore_call5 : BOOLEAN; signal ap_block_state77_pp0_stage10_iter1_ignore_call5 : BOOLEAN; signal ap_sig_ioackin_results_out_WREADY : STD_LOGIC; signal ap_predicate_op236_write_state77 : BOOLEAN; signal ap_block_state77_io : BOOLEAN; signal ap_block_pp0_stage10_flag00011001 : BOOLEAN; signal ap_block_state14_pp0_stage11_iter0_ignore_call5 : BOOLEAN; signal ap_block_state78_pp0_stage11_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage11_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage11 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none"; signal ap_block_state15_pp0_stage12_iter0_ignore_call5 : BOOLEAN; signal ap_block_state79_pp0_stage12_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage12_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage12 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none"; signal ap_block_state16_pp0_stage13_iter0_ignore_call5 : BOOLEAN; signal ap_block_state80_pp0_stage13_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage13_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage13 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none"; signal ap_block_state17_pp0_stage14_iter0_ignore_call5 : BOOLEAN; signal ap_block_state81_pp0_stage14_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage14_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage14 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none"; signal ap_block_state18_pp0_stage15_iter0_ignore_call5 : BOOLEAN; signal ap_block_state82_pp0_stage15_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage15_flag00011001 : BOOLEAN; signal ap_block_state19_pp0_stage16_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage16_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage16 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage16 : signal is "none"; signal ap_block_state20_pp0_stage17_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage17_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage17 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage17 : signal is "none"; signal ap_block_state21_pp0_stage18_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage18_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage18 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage18 : signal is "none"; signal ap_block_state22_pp0_stage19_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage19_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage19 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage19 : signal is "none"; signal ap_block_state23_pp0_stage20_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage20_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage20 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage20 : signal is "none"; signal ap_block_state24_pp0_stage21_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage21_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage21 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage21 : signal is "none"; signal ap_block_state25_pp0_stage22_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage22_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage22 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage22 : signal is "none"; signal ap_block_state26_pp0_stage23_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage23_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage23 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage23 : signal is "none"; signal ap_block_state27_pp0_stage24_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage24_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage24 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage24 : signal is "none"; signal ap_block_state28_pp0_stage25_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage25_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage25 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage25 : signal is "none"; signal ap_block_state29_pp0_stage26_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage26_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage26 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage26 : signal is "none"; signal ap_block_state30_pp0_stage27_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage27_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage27 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage27 : signal is "none"; signal ap_block_state31_pp0_stage28_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage28_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage28 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage28 : signal is "none"; signal ap_block_state32_pp0_stage29_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage29_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage29 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage29 : signal is "none"; signal ap_block_state33_pp0_stage30_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage30_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage30 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage30 : signal is "none"; signal ap_block_state34_pp0_stage31_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage31_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage31 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage31 : signal is "none"; signal ap_block_state35_pp0_stage32_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage32_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage32 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage32 : signal is "none"; signal ap_block_state36_pp0_stage33_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage33_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage33 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage33 : signal is "none"; signal ap_block_state37_pp0_stage34_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage34_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage34 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage34 : signal is "none"; signal ap_block_state38_pp0_stage35_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage35_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage35 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage35 : signal is "none"; signal ap_block_state39_pp0_stage36_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage36_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage36 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage36 : signal is "none"; signal ap_block_state40_pp0_stage37_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage37_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage37 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage37 : signal is "none"; signal ap_block_state41_pp0_stage38_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage38_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage38 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage38 : signal is "none"; signal ap_block_state42_pp0_stage39_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage39_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage39 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage39 : signal is "none"; signal ap_block_state43_pp0_stage40_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage40_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage40 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage40 : signal is "none"; signal ap_block_state44_pp0_stage41_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage41_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage41 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage41 : signal is "none"; signal ap_block_state45_pp0_stage42_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage42_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage42 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage42 : signal is "none"; signal ap_block_state46_pp0_stage43_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage43_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage43 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage43 : signal is "none"; signal ap_block_state47_pp0_stage44_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage44_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage44 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage44 : signal is "none"; signal ap_block_state48_pp0_stage45_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage45_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage45 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage45 : signal is "none"; signal ap_block_state49_pp0_stage46_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage46_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage46 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage46 : signal is "none"; signal ap_block_state50_pp0_stage47_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage47_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage47 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage47 : signal is "none"; signal ap_block_state51_pp0_stage48_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage48_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage48 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage48 : signal is "none"; signal ap_block_state52_pp0_stage49_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage49_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage49 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage49 : signal is "none"; signal ap_block_state53_pp0_stage50_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage50_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage50 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage50 : signal is "none"; signal ap_block_state54_pp0_stage51_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage51_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage51 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage51 : signal is "none"; signal ap_block_state55_pp0_stage52_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage52_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage52 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage52 : signal is "none"; signal ap_block_state56_pp0_stage53_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage53_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage53 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage53 : signal is "none"; signal ap_block_state57_pp0_stage54_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage54_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage54 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage54 : signal is "none"; signal ap_block_state58_pp0_stage55_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage55_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage55 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage55 : signal is "none"; signal ap_block_state59_pp0_stage56_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage56_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage56 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage56 : signal is "none"; signal ap_block_state60_pp0_stage57_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage57_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage57 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage57 : signal is "none"; signal ap_block_state61_pp0_stage58_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage58_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage58 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage58 : signal is "none"; signal ap_block_state62_pp0_stage59_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage59_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage59 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage59 : signal is "none"; signal ap_block_state63_pp0_stage60_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage60_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage60 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage60 : signal is "none"; signal ap_block_state64_pp0_stage61_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage61_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage61 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage61 : signal is "none"; signal ap_block_state65_pp0_stage62_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage62_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage62 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage62 : signal is "none"; signal ap_block_state66_pp0_stage63_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage63_flag00011001 : BOOLEAN; signal ap_block_state5_pp0_stage2_iter0_ignore_call5 : BOOLEAN; signal ap_block_state69_pp0_stage2_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage2_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none"; signal ap_block_state6_pp0_stage3_iter0_ignore_call5 : BOOLEAN; signal ap_block_state70_pp0_stage3_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage3_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage3 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none"; signal ap_block_state7_pp0_stage4_iter0_ignore_call5 : BOOLEAN; signal ap_block_state71_pp0_stage4_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage4_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage4 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none"; signal ap_block_state8_pp0_stage5_iter0_ignore_call5 : BOOLEAN; signal ap_block_state72_pp0_stage5_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage5_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage5 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none"; signal ap_block_state9_pp0_stage6_iter0_ignore_call5 : BOOLEAN; signal ap_block_state73_pp0_stage6_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage6_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage6 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none"; signal ap_block_state10_pp0_stage7_iter0_ignore_call5 : BOOLEAN; signal ap_block_state74_pp0_stage7_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage7_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage7 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none"; signal database_index_phi_fu_193_p4 : STD_LOGIC_VECTOR (23 downto 0); signal ap_block_pp0_stage0_flag00000000 : BOOLEAN; signal storemerge_reg_200 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state84 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state84 : signal is "none"; signal ap_reg_grp_match_db_contact_fu_212_ap_start : STD_LOGIC := '0'; signal ap_predicate_op169_call_state12_state11 : BOOLEAN; signal ap_block_pp0_stage11_flag00000000 : BOOLEAN; signal ap_block_pp0_stage12_flag00000000 : BOOLEAN; signal ap_block_pp0_stage13_flag00000000 : BOOLEAN; signal ap_block_pp0_stage14_flag00000000 : BOOLEAN; signal ap_block_pp0_stage16_flag00000000 : BOOLEAN; signal ap_block_pp0_stage17_flag00000000 : BOOLEAN; signal ap_block_pp0_stage18_flag00000000 : BOOLEAN; signal ap_block_pp0_stage19_flag00000000 : BOOLEAN; signal ap_block_pp0_stage20_flag00000000 : BOOLEAN; signal ap_block_pp0_stage21_flag00000000 : BOOLEAN; signal ap_block_pp0_stage22_flag00000000 : BOOLEAN; signal ap_block_pp0_stage23_flag00000000 : BOOLEAN; signal ap_block_pp0_stage24_flag00000000 : BOOLEAN; signal ap_block_pp0_stage25_flag00000000 : BOOLEAN; signal ap_block_pp0_stage26_flag00000000 : BOOLEAN; signal ap_block_pp0_stage27_flag00000000 : BOOLEAN; signal ap_block_pp0_stage28_flag00000000 : BOOLEAN; signal ap_block_pp0_stage29_flag00000000 : BOOLEAN; signal ap_block_pp0_stage30_flag00000000 : BOOLEAN; signal ap_block_pp0_stage31_flag00000000 : BOOLEAN; signal ap_block_pp0_stage32_flag00000000 : BOOLEAN; signal ap_block_pp0_stage33_flag00000000 : BOOLEAN; signal ap_block_pp0_stage34_flag00000000 : BOOLEAN; signal ap_block_pp0_stage35_flag00000000 : BOOLEAN; signal ap_block_pp0_stage36_flag00000000 : BOOLEAN; signal ap_block_pp0_stage37_flag00000000 : BOOLEAN; signal ap_block_pp0_stage38_flag00000000 : BOOLEAN; signal ap_block_pp0_stage39_flag00000000 : BOOLEAN; signal ap_block_pp0_stage40_flag00000000 : BOOLEAN; signal ap_block_pp0_stage41_flag00000000 : BOOLEAN; signal ap_block_pp0_stage42_flag00000000 : BOOLEAN; signal ap_block_pp0_stage43_flag00000000 : BOOLEAN; signal ap_block_pp0_stage44_flag00000000 : BOOLEAN; signal ap_block_pp0_stage45_flag00000000 : BOOLEAN; signal ap_block_pp0_stage46_flag00000000 : BOOLEAN; signal ap_block_pp0_stage47_flag00000000 : BOOLEAN; signal ap_block_pp0_stage48_flag00000000 : BOOLEAN; signal ap_block_pp0_stage49_flag00000000 : BOOLEAN; signal ap_block_pp0_stage50_flag00000000 : BOOLEAN; signal ap_block_pp0_stage51_flag00000000 : BOOLEAN; signal ap_block_pp0_stage52_flag00000000 : BOOLEAN; signal ap_block_pp0_stage53_flag00000000 : BOOLEAN; signal ap_block_pp0_stage54_flag00000000 : BOOLEAN; signal ap_block_pp0_stage55_flag00000000 : BOOLEAN; signal ap_block_pp0_stage56_flag00000000 : BOOLEAN; signal ap_block_pp0_stage57_flag00000000 : BOOLEAN; signal ap_block_pp0_stage58_flag00000000 : BOOLEAN; signal ap_block_pp0_stage59_flag00000000 : BOOLEAN; signal ap_block_pp0_stage60_flag00000000 : BOOLEAN; signal ap_block_pp0_stage61_flag00000000 : BOOLEAN; signal ap_block_pp0_stage62_flag00000000 : BOOLEAN; signal ap_block_pp0_stage63_flag00000000 : BOOLEAN; signal ap_block_pp0_stage2_flag00000000 : BOOLEAN; signal ap_block_pp0_stage3_flag00000000 : BOOLEAN; signal ap_block_pp0_stage4_flag00000000 : BOOLEAN; signal ap_block_pp0_stage5_flag00000000 : BOOLEAN; signal ap_block_pp0_stage6_flag00000000 : BOOLEAN; signal ap_block_pp0_stage7_flag00000000 : BOOLEAN; signal tmp_4_fu_249_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_7_fu_282_p1 : STD_LOGIC_VECTOR (63 downto 0); signal sum_cast_fu_306_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_reg_ioackin_db_mem_V_ARREADY : STD_LOGIC := '0'; signal ap_block_pp0_stage1_flag00001001 : BOOLEAN; signal ap_reg_ioackin_results_out_AWREADY : STD_LOGIC := '0'; signal ap_block_pp0_stage9_flag00001001 : BOOLEAN; signal ap_reg_ioackin_results_out_WREADY : STD_LOGIC := '0'; signal ap_block_state13_pp0_stage10_iter0 : BOOLEAN; signal ap_block_state77_pp0_stage10_iter1 : BOOLEAN; signal ap_block_pp0_stage10_flag00001001 : BOOLEAN; signal ap_CS_fsm_state85 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state85 : signal is "none"; signal tmp_fu_234_p4 : STD_LOGIC_VECTOR (24 downto 0); signal database_index_cast1_fu_278_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_7_cast_fu_286_p1 : STD_LOGIC_VECTOR (24 downto 0); signal ap_CS_fsm_state86 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state86 : signal is "none"; signal ap_block_state86 : BOOLEAN; signal ap_NS_fsm : STD_LOGIC_VECTOR (69 downto 0); signal ap_block_pp0_stage1_flag00011011 : BOOLEAN; signal ap_block_state5_pp0_stage2_iter0 : BOOLEAN; signal ap_block_state69_pp0_stage2_iter1 : BOOLEAN; signal ap_block_pp0_stage2_flag00011011 : BOOLEAN; signal ap_block_state6_pp0_stage3_iter0 : BOOLEAN; signal ap_block_state70_pp0_stage3_iter1 : BOOLEAN; signal ap_block_pp0_stage3_flag00011011 : BOOLEAN; signal ap_block_state7_pp0_stage4_iter0 : BOOLEAN; signal ap_block_state71_pp0_stage4_iter1 : BOOLEAN; signal ap_block_pp0_stage4_flag00011011 : BOOLEAN; signal ap_block_state8_pp0_stage5_iter0 : BOOLEAN; signal ap_block_state72_pp0_stage5_iter1 : BOOLEAN; signal ap_block_pp0_stage5_flag00011011 : BOOLEAN; signal ap_block_state9_pp0_stage6_iter0 : BOOLEAN; signal ap_block_state73_pp0_stage6_iter1 : BOOLEAN; signal ap_block_pp0_stage6_flag00011011 : BOOLEAN; signal ap_block_state10_pp0_stage7_iter0 : BOOLEAN; signal ap_block_state74_pp0_stage7_iter1 : BOOLEAN; signal ap_block_pp0_stage7_flag00011011 : BOOLEAN; signal ap_block_pp0_stage8_flag00011011 : BOOLEAN; signal ap_block_pp0_stage9_flag00011011 : BOOLEAN; signal ap_block_pp0_stage10_flag00011011 : BOOLEAN; signal ap_block_state14_pp0_stage11_iter0 : BOOLEAN; signal ap_block_state78_pp0_stage11_iter1 : BOOLEAN; signal ap_block_pp0_stage11_flag00011011 : BOOLEAN; signal ap_block_state15_pp0_stage12_iter0 : BOOLEAN; signal ap_block_state79_pp0_stage12_iter1 : BOOLEAN; signal ap_block_pp0_stage12_flag00011011 : BOOLEAN; signal ap_block_state16_pp0_stage13_iter0 : BOOLEAN; signal ap_block_state80_pp0_stage13_iter1 : BOOLEAN; signal ap_block_pp0_stage13_flag00011011 : BOOLEAN; signal ap_block_state17_pp0_stage14_iter0 : BOOLEAN; signal ap_block_state81_pp0_stage14_iter1 : BOOLEAN; signal ap_block_pp0_stage14_flag00011011 : BOOLEAN; signal ap_block_state19_pp0_stage16_iter0 : BOOLEAN; signal ap_block_pp0_stage16_flag00011011 : BOOLEAN; signal ap_block_state20_pp0_stage17_iter0 : BOOLEAN; signal ap_block_pp0_stage17_flag00011011 : BOOLEAN; signal ap_block_state21_pp0_stage18_iter0 : BOOLEAN; signal ap_block_pp0_stage18_flag00011011 : BOOLEAN; signal ap_block_state22_pp0_stage19_iter0 : BOOLEAN; signal ap_block_pp0_stage19_flag00011011 : BOOLEAN; signal ap_block_state23_pp0_stage20_iter0 : BOOLEAN; signal ap_block_pp0_stage20_flag00011011 : BOOLEAN; signal ap_block_state24_pp0_stage21_iter0 : BOOLEAN; signal ap_block_pp0_stage21_flag00011011 : BOOLEAN; signal ap_block_state25_pp0_stage22_iter0 : BOOLEAN; signal ap_block_pp0_stage22_flag00011011 : BOOLEAN; signal ap_block_state26_pp0_stage23_iter0 : BOOLEAN; signal ap_block_pp0_stage23_flag00011011 : BOOLEAN; signal ap_block_state27_pp0_stage24_iter0 : BOOLEAN; signal ap_block_pp0_stage24_flag00011011 : BOOLEAN; signal ap_block_state28_pp0_stage25_iter0 : BOOLEAN; signal ap_block_pp0_stage25_flag00011011 : BOOLEAN; signal ap_block_state29_pp0_stage26_iter0 : BOOLEAN; signal ap_block_pp0_stage26_flag00011011 : BOOLEAN; signal ap_block_state30_pp0_stage27_iter0 : BOOLEAN; signal ap_block_pp0_stage27_flag00011011 : BOOLEAN; signal ap_block_state31_pp0_stage28_iter0 : BOOLEAN; signal ap_block_pp0_stage28_flag00011011 : BOOLEAN; signal ap_block_state32_pp0_stage29_iter0 : BOOLEAN; signal ap_block_pp0_stage29_flag00011011 : BOOLEAN; signal ap_block_state33_pp0_stage30_iter0 : BOOLEAN; signal ap_block_pp0_stage30_flag00011011 : BOOLEAN; signal ap_block_state34_pp0_stage31_iter0 : BOOLEAN; signal ap_block_pp0_stage31_flag00011011 : BOOLEAN; signal ap_block_state35_pp0_stage32_iter0 : BOOLEAN; signal ap_block_pp0_stage32_flag00011011 : BOOLEAN; signal ap_block_state36_pp0_stage33_iter0 : BOOLEAN; signal ap_block_pp0_stage33_flag00011011 : BOOLEAN; signal ap_block_state37_pp0_stage34_iter0 : BOOLEAN; signal ap_block_pp0_stage34_flag00011011 : BOOLEAN; signal ap_block_state38_pp0_stage35_iter0 : BOOLEAN; signal ap_block_pp0_stage35_flag00011011 : BOOLEAN; signal ap_block_state39_pp0_stage36_iter0 : BOOLEAN; signal ap_block_pp0_stage36_flag00011011 : BOOLEAN; signal ap_block_state40_pp0_stage37_iter0 : BOOLEAN; signal ap_block_pp0_stage37_flag00011011 : BOOLEAN; signal ap_block_state41_pp0_stage38_iter0 : BOOLEAN; signal ap_block_pp0_stage38_flag00011011 : BOOLEAN; signal ap_block_state42_pp0_stage39_iter0 : BOOLEAN; signal ap_block_pp0_stage39_flag00011011 : BOOLEAN; signal ap_block_state43_pp0_stage40_iter0 : BOOLEAN; signal ap_block_pp0_stage40_flag00011011 : BOOLEAN; signal ap_block_state44_pp0_stage41_iter0 : BOOLEAN; signal ap_block_pp0_stage41_flag00011011 : BOOLEAN; signal ap_block_state45_pp0_stage42_iter0 : BOOLEAN; signal ap_block_pp0_stage42_flag00011011 : BOOLEAN; signal ap_block_state46_pp0_stage43_iter0 : BOOLEAN; signal ap_block_pp0_stage43_flag00011011 : BOOLEAN; signal ap_block_state47_pp0_stage44_iter0 : BOOLEAN; signal ap_block_pp0_stage44_flag00011011 : BOOLEAN; signal ap_block_state48_pp0_stage45_iter0 : BOOLEAN; signal ap_block_pp0_stage45_flag00011011 : BOOLEAN; signal ap_block_state49_pp0_stage46_iter0 : BOOLEAN; signal ap_block_pp0_stage46_flag00011011 : BOOLEAN; signal ap_block_state50_pp0_stage47_iter0 : BOOLEAN; signal ap_block_pp0_stage47_flag00011011 : BOOLEAN; signal ap_block_state51_pp0_stage48_iter0 : BOOLEAN; signal ap_block_pp0_stage48_flag00011011 : BOOLEAN; signal ap_block_state52_pp0_stage49_iter0 : BOOLEAN; signal ap_block_pp0_stage49_flag00011011 : BOOLEAN; signal ap_block_state53_pp0_stage50_iter0 : BOOLEAN; signal ap_block_pp0_stage50_flag00011011 : BOOLEAN; signal ap_block_state54_pp0_stage51_iter0 : BOOLEAN; signal ap_block_pp0_stage51_flag00011011 : BOOLEAN; signal ap_block_state55_pp0_stage52_iter0 : BOOLEAN; signal ap_block_pp0_stage52_flag00011011 : BOOLEAN; signal ap_block_state56_pp0_stage53_iter0 : BOOLEAN; signal ap_block_pp0_stage53_flag00011011 : BOOLEAN; signal ap_block_state57_pp0_stage54_iter0 : BOOLEAN; signal ap_block_pp0_stage54_flag00011011 : BOOLEAN; signal ap_block_state58_pp0_stage55_iter0 : BOOLEAN; signal ap_block_pp0_stage55_flag00011011 : BOOLEAN; signal ap_block_state59_pp0_stage56_iter0 : BOOLEAN; signal ap_block_pp0_stage56_flag00011011 : BOOLEAN; signal ap_block_state60_pp0_stage57_iter0 : BOOLEAN; signal ap_block_pp0_stage57_flag00011011 : BOOLEAN; signal ap_block_state61_pp0_stage58_iter0 : BOOLEAN; signal ap_block_pp0_stage58_flag00011011 : BOOLEAN; signal ap_block_state62_pp0_stage59_iter0 : BOOLEAN; signal ap_block_pp0_stage59_flag00011011 : BOOLEAN; signal ap_block_state63_pp0_stage60_iter0 : BOOLEAN; signal ap_block_pp0_stage60_flag00011011 : BOOLEAN; signal ap_block_state64_pp0_stage61_iter0 : BOOLEAN; signal ap_block_pp0_stage61_flag00011011 : BOOLEAN; signal ap_block_state65_pp0_stage62_iter0 : BOOLEAN; signal ap_block_pp0_stage62_flag00011011 : BOOLEAN; signal ap_idle_pp0 : STD_LOGIC; signal ap_enable_pp0 : STD_LOGIC; signal ap_condition_2628 : BOOLEAN; signal ap_condition_2632 : BOOLEAN; signal ap_condition_2636 : BOOLEAN; component match_db_contact IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; ap_ce : IN STD_LOGIC; db_item_V : IN STD_LOGIC_VECTOR (511 downto 0); contacts_V_address0 : OUT STD_LOGIC_VECTOR (6 downto 0); contacts_V_ce0 : OUT STD_LOGIC; contacts_V_q0 : IN STD_LOGIC_VECTOR (511 downto 0); contacts_V_address1 : OUT STD_LOGIC_VECTOR (6 downto 0); contacts_V_ce1 : OUT STD_LOGIC; contacts_V_q1 : IN STD_LOGIC_VECTOR (511 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component contact_discoverybkb IS generic ( DataWidth : INTEGER; AddressRange : INTEGER; AddressWidth : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR (6 downto 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR (511 downto 0); q0 : OUT STD_LOGIC_VECTOR (511 downto 0); address1 : IN STD_LOGIC_VECTOR (6 downto 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR (511 downto 0) ); end component; component contact_discovery_AXILiteS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; ap_start : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; ap_ready : IN STD_LOGIC; ap_done : IN STD_LOGIC; ap_idle : IN STD_LOGIC; operation : OUT STD_LOGIC_VECTOR (31 downto 0); operation_ap_vld : OUT STD_LOGIC; contact_in_V : OUT STD_LOGIC_VECTOR (511 downto 0); offset : OUT STD_LOGIC_VECTOR (63 downto 0); db_size_in : OUT STD_LOGIC_VECTOR (31 downto 0); error_out : IN STD_LOGIC_VECTOR (31 downto 0); contacts_size_out : IN STD_LOGIC_VECTOR (31 downto 0) ); end component; component contact_discovery_db_mem_V_m_axi IS generic ( USER_DW : INTEGER; USER_AW : INTEGER; USER_MAXREQS : INTEGER; NUM_READ_OUTSTANDING : INTEGER; NUM_WRITE_OUTSTANDING : INTEGER; MAX_READ_BURST_LENGTH : INTEGER; MAX_WRITE_BURST_LENGTH : INTEGER; C_M_AXI_ID_WIDTH : INTEGER; C_M_AXI_ADDR_WIDTH : INTEGER; C_M_AXI_DATA_WIDTH : INTEGER; C_M_AXI_AWUSER_WIDTH : INTEGER; C_M_AXI_ARUSER_WIDTH : INTEGER; C_M_AXI_WUSER_WIDTH : INTEGER; C_M_AXI_RUSER_WIDTH : INTEGER; C_M_AXI_BUSER_WIDTH : INTEGER; C_TARGET_ADDR : INTEGER; C_USER_VALUE : INTEGER; C_PROT_VALUE : INTEGER; C_CACHE_VALUE : INTEGER ); port ( AWVALID : OUT STD_LOGIC; AWREADY : IN STD_LOGIC; AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0); AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0); AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0); AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0); AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0); AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0); AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0); WVALID : OUT STD_LOGIC; WREADY : IN STD_LOGIC; WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0); WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0); WLAST : OUT STD_LOGIC; WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0); ARVALID : OUT STD_LOGIC; ARREADY : IN STD_LOGIC; ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0); ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0); ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0); ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0); ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0); ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0); ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0); RVALID : IN STD_LOGIC; RREADY : OUT STD_LOGIC; RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0); RLAST : IN STD_LOGIC; RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0); RRESP : IN STD_LOGIC_VECTOR (1 downto 0); BVALID : IN STD_LOGIC; BREADY : OUT STD_LOGIC; BRESP : IN STD_LOGIC_VECTOR (1 downto 0); BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; I_ARVALID : IN STD_LOGIC; I_ARREADY : OUT STD_LOGIC; I_ARADDR : IN STD_LOGIC_VECTOR (63 downto 0); I_ARID : IN STD_LOGIC_VECTOR (0 downto 0); I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0); I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0); I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0); I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0); I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0); I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0); I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0); I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0); I_RVALID : OUT STD_LOGIC; I_RREADY : IN STD_LOGIC; I_RDATA : OUT STD_LOGIC_VECTOR (511 downto 0); I_RID : OUT STD_LOGIC_VECTOR (0 downto 0); I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0); I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); I_RLAST : OUT STD_LOGIC; I_AWVALID : IN STD_LOGIC; I_AWREADY : OUT STD_LOGIC; I_AWADDR : IN STD_LOGIC_VECTOR (63 downto 0); I_AWID : IN STD_LOGIC_VECTOR (0 downto 0); I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0); I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0); I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0); I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0); I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0); I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0); I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0); I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0); I_WVALID : IN STD_LOGIC; I_WREADY : OUT STD_LOGIC; I_WDATA : IN STD_LOGIC_VECTOR (511 downto 0); I_WID : IN STD_LOGIC_VECTOR (0 downto 0); I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_WLAST : IN STD_LOGIC; I_WSTRB : IN STD_LOGIC_VECTOR (63 downto 0); I_BVALID : OUT STD_LOGIC; I_BREADY : IN STD_LOGIC; I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); I_BID : OUT STD_LOGIC_VECTOR (0 downto 0); I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component contact_discovery_results_out_m_axi IS generic ( USER_DW : INTEGER; USER_AW : INTEGER; USER_MAXREQS : INTEGER; NUM_READ_OUTSTANDING : INTEGER; NUM_WRITE_OUTSTANDING : INTEGER; MAX_READ_BURST_LENGTH : INTEGER; MAX_WRITE_BURST_LENGTH : INTEGER; C_M_AXI_ID_WIDTH : INTEGER; C_M_AXI_ADDR_WIDTH : INTEGER; C_M_AXI_DATA_WIDTH : INTEGER; C_M_AXI_AWUSER_WIDTH : INTEGER; C_M_AXI_ARUSER_WIDTH : INTEGER; C_M_AXI_WUSER_WIDTH : INTEGER; C_M_AXI_RUSER_WIDTH : INTEGER; C_M_AXI_BUSER_WIDTH : INTEGER; C_TARGET_ADDR : INTEGER; C_USER_VALUE : INTEGER; C_PROT_VALUE : INTEGER; C_CACHE_VALUE : INTEGER ); port ( AWVALID : OUT STD_LOGIC; AWREADY : IN STD_LOGIC; AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0); AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0); AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0); AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0); AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0); AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0); AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0); WVALID : OUT STD_LOGIC; WREADY : IN STD_LOGIC; WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0); WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0); WLAST : OUT STD_LOGIC; WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0); ARVALID : OUT STD_LOGIC; ARREADY : IN STD_LOGIC; ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0); ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0); ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0); ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0); ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0); ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0); ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0); RVALID : IN STD_LOGIC; RREADY : OUT STD_LOGIC; RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0); RLAST : IN STD_LOGIC; RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0); RRESP : IN STD_LOGIC_VECTOR (1 downto 0); BVALID : IN STD_LOGIC; BREADY : OUT STD_LOGIC; BRESP : IN STD_LOGIC_VECTOR (1 downto 0); BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; I_ARVALID : IN STD_LOGIC; I_ARREADY : OUT STD_LOGIC; I_ARADDR : IN STD_LOGIC_VECTOR (63 downto 0); I_ARID : IN STD_LOGIC_VECTOR (0 downto 0); I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0); I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0); I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0); I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0); I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0); I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0); I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0); I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0); I_RVALID : OUT STD_LOGIC; I_RREADY : IN STD_LOGIC; I_RDATA : OUT STD_LOGIC_VECTOR (7 downto 0); I_RID : OUT STD_LOGIC_VECTOR (0 downto 0); I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0); I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); I_RLAST : OUT STD_LOGIC; I_AWVALID : IN STD_LOGIC; I_AWREADY : OUT STD_LOGIC; I_AWADDR : IN STD_LOGIC_VECTOR (63 downto 0); I_AWID : IN STD_LOGIC_VECTOR (0 downto 0); I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0); I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0); I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0); I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0); I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0); I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0); I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0); I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0); I_WVALID : IN STD_LOGIC; I_WREADY : OUT STD_LOGIC; I_WDATA : IN STD_LOGIC_VECTOR (7 downto 0); I_WID : IN STD_LOGIC_VECTOR (0 downto 0); I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_WLAST : IN STD_LOGIC; I_WSTRB : IN STD_LOGIC_VECTOR (0 downto 0); I_BVALID : OUT STD_LOGIC; I_BREADY : IN STD_LOGIC; I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); I_BID : OUT STD_LOGIC_VECTOR (0 downto 0); I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; begin contacts_V_U : component contact_discoverybkb generic map ( DataWidth => 512, AddressRange => 128, AddressWidth => 7) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => contacts_V_address0, ce0 => contacts_V_ce0, we0 => contacts_V_we0, d0 => contact_in_V_read_reg_325, q0 => contacts_V_q0, address1 => grp_match_db_contact_fu_212_contacts_V_address1, ce1 => contacts_V_ce1, q1 => contacts_V_q1); contact_discovery_AXILiteS_s_axi_U : component contact_discovery_AXILiteS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH) port map ( AWVALID => s_axi_AXILiteS_AWVALID, AWREADY => s_axi_AXILiteS_AWREADY, AWADDR => s_axi_AXILiteS_AWADDR, WVALID => s_axi_AXILiteS_WVALID, WREADY => s_axi_AXILiteS_WREADY, WDATA => s_axi_AXILiteS_WDATA, WSTRB => s_axi_AXILiteS_WSTRB, ARVALID => s_axi_AXILiteS_ARVALID, ARREADY => s_axi_AXILiteS_ARREADY, ARADDR => s_axi_AXILiteS_ARADDR, RVALID => s_axi_AXILiteS_RVALID, RREADY => s_axi_AXILiteS_RREADY, RDATA => s_axi_AXILiteS_RDATA, RRESP => s_axi_AXILiteS_RRESP, BVALID => s_axi_AXILiteS_BVALID, BREADY => s_axi_AXILiteS_BREADY, BRESP => s_axi_AXILiteS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, ap_start => ap_start, interrupt => interrupt, ap_ready => ap_ready, ap_done => ap_done, ap_idle => ap_idle, operation => operation, operation_ap_vld => operation_ap_vld, contact_in_V => contact_in_V, offset => offset, db_size_in => db_size_in, error_out => error_out_1_data_reg, contacts_size_out => contacts_size_out_1_data_reg); contact_discovery_db_mem_V_m_axi_U : component contact_discovery_db_mem_V_m_axi generic map ( USER_DW => 512, USER_AW => 64, USER_MAXREQS => 5, NUM_READ_OUTSTANDING => 16, NUM_WRITE_OUTSTANDING => 16, MAX_READ_BURST_LENGTH => 16, MAX_WRITE_BURST_LENGTH => 16, C_M_AXI_ID_WIDTH => C_M_AXI_DB_MEM_V_ID_WIDTH, C_M_AXI_ADDR_WIDTH => C_M_AXI_DB_MEM_V_ADDR_WIDTH, C_M_AXI_DATA_WIDTH => C_M_AXI_DB_MEM_V_DATA_WIDTH, C_M_AXI_AWUSER_WIDTH => C_M_AXI_DB_MEM_V_AWUSER_WIDTH, C_M_AXI_ARUSER_WIDTH => C_M_AXI_DB_MEM_V_ARUSER_WIDTH, C_M_AXI_WUSER_WIDTH => C_M_AXI_DB_MEM_V_WUSER_WIDTH, C_M_AXI_RUSER_WIDTH => C_M_AXI_DB_MEM_V_RUSER_WIDTH, C_M_AXI_BUSER_WIDTH => C_M_AXI_DB_MEM_V_BUSER_WIDTH, C_TARGET_ADDR => C_M_AXI_DB_MEM_V_TARGET_ADDR, C_USER_VALUE => C_M_AXI_DB_MEM_V_USER_VALUE, C_PROT_VALUE => C_M_AXI_DB_MEM_V_PROT_VALUE, C_CACHE_VALUE => C_M_AXI_DB_MEM_V_CACHE_VALUE) port map ( AWVALID => m_axi_db_mem_V_AWVALID, AWREADY => m_axi_db_mem_V_AWREADY, AWADDR => m_axi_db_mem_V_AWADDR, AWID => m_axi_db_mem_V_AWID, AWLEN => m_axi_db_mem_V_AWLEN, AWSIZE => m_axi_db_mem_V_AWSIZE, AWBURST => m_axi_db_mem_V_AWBURST, AWLOCK => m_axi_db_mem_V_AWLOCK, AWCACHE => m_axi_db_mem_V_AWCACHE, AWPROT => m_axi_db_mem_V_AWPROT, AWQOS => m_axi_db_mem_V_AWQOS, AWREGION => m_axi_db_mem_V_AWREGION, AWUSER => m_axi_db_mem_V_AWUSER, WVALID => m_axi_db_mem_V_WVALID, WREADY => m_axi_db_mem_V_WREADY, WDATA => m_axi_db_mem_V_WDATA, WSTRB => m_axi_db_mem_V_WSTRB, WLAST => m_axi_db_mem_V_WLAST, WID => m_axi_db_mem_V_WID, WUSER => m_axi_db_mem_V_WUSER, ARVALID => m_axi_db_mem_V_ARVALID, ARREADY => m_axi_db_mem_V_ARREADY, ARADDR => m_axi_db_mem_V_ARADDR, ARID => m_axi_db_mem_V_ARID, ARLEN => m_axi_db_mem_V_ARLEN, ARSIZE => m_axi_db_mem_V_ARSIZE, ARBURST => m_axi_db_mem_V_ARBURST, ARLOCK => m_axi_db_mem_V_ARLOCK, ARCACHE => m_axi_db_mem_V_ARCACHE, ARPROT => m_axi_db_mem_V_ARPROT, ARQOS => m_axi_db_mem_V_ARQOS, ARREGION => m_axi_db_mem_V_ARREGION, ARUSER => m_axi_db_mem_V_ARUSER, RVALID => m_axi_db_mem_V_RVALID, RREADY => m_axi_db_mem_V_RREADY, RDATA => m_axi_db_mem_V_RDATA, RLAST => m_axi_db_mem_V_RLAST, RID => m_axi_db_mem_V_RID, RUSER => m_axi_db_mem_V_RUSER, RRESP => m_axi_db_mem_V_RRESP, BVALID => m_axi_db_mem_V_BVALID, BREADY => m_axi_db_mem_V_BREADY, BRESP => m_axi_db_mem_V_BRESP, BID => m_axi_db_mem_V_BID, BUSER => m_axi_db_mem_V_BUSER, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, I_ARVALID => db_mem_V_ARVALID, I_ARREADY => db_mem_V_ARREADY, I_ARADDR => sum_cast_fu_306_p1, I_ARID => ap_const_lv1_0, I_ARLEN => ap_const_lv32_1, I_ARSIZE => ap_const_lv3_0, I_ARLOCK => ap_const_lv2_0, I_ARCACHE => ap_const_lv4_0, I_ARQOS => ap_const_lv4_0, I_ARPROT => ap_const_lv3_0, I_ARUSER => ap_const_lv1_0, I_ARBURST => ap_const_lv2_0, I_ARREGION => ap_const_lv4_0, I_RVALID => db_mem_V_RVALID, I_RREADY => db_mem_V_RREADY, I_RDATA => db_mem_V_RDATA, I_RID => db_mem_V_RID, I_RUSER => db_mem_V_RUSER, I_RRESP => db_mem_V_RRESP, I_RLAST => db_mem_V_RLAST, I_AWVALID => ap_const_logic_0, I_AWREADY => db_mem_V_AWREADY, I_AWADDR => ap_const_lv64_0, I_AWID => ap_const_lv1_0, I_AWLEN => ap_const_lv32_0, I_AWSIZE => ap_const_lv3_0, I_AWLOCK => ap_const_lv2_0, I_AWCACHE => ap_const_lv4_0, I_AWQOS => ap_const_lv4_0, I_AWPROT => ap_const_lv3_0, I_AWUSER => ap_const_lv1_0, I_AWBURST => ap_const_lv2_0, I_AWREGION => ap_const_lv4_0, I_WVALID => ap_const_logic_0, I_WREADY => db_mem_V_WREADY, I_WDATA => ap_const_lv512_lc_1, I_WID => ap_const_lv1_0, I_WUSER => ap_const_lv1_0, I_WLAST => ap_const_logic_0, I_WSTRB => ap_const_lv64_0, I_BVALID => db_mem_V_BVALID, I_BREADY => ap_const_logic_0, I_BRESP => db_mem_V_BRESP, I_BID => db_mem_V_BID, I_BUSER => db_mem_V_BUSER); contact_discovery_results_out_m_axi_U : component contact_discovery_results_out_m_axi generic map ( USER_DW => 8, USER_AW => 64, USER_MAXREQS => 5, NUM_READ_OUTSTANDING => 16, NUM_WRITE_OUTSTANDING => 16, MAX_READ_BURST_LENGTH => 16, MAX_WRITE_BURST_LENGTH => 16, C_M_AXI_ID_WIDTH => C_M_AXI_RESULTS_OUT_ID_WIDTH, C_M_AXI_ADDR_WIDTH => C_M_AXI_RESULTS_OUT_ADDR_WIDTH, C_M_AXI_DATA_WIDTH => C_M_AXI_RESULTS_OUT_DATA_WIDTH, C_M_AXI_AWUSER_WIDTH => C_M_AXI_RESULTS_OUT_AWUSER_WIDTH, C_M_AXI_ARUSER_WIDTH => C_M_AXI_RESULTS_OUT_ARUSER_WIDTH, C_M_AXI_WUSER_WIDTH => C_M_AXI_RESULTS_OUT_WUSER_WIDTH, C_M_AXI_RUSER_WIDTH => C_M_AXI_RESULTS_OUT_RUSER_WIDTH, C_M_AXI_BUSER_WIDTH => C_M_AXI_RESULTS_OUT_BUSER_WIDTH, C_TARGET_ADDR => C_M_AXI_RESULTS_OUT_TARGET_ADDR, C_USER_VALUE => C_M_AXI_RESULTS_OUT_USER_VALUE, C_PROT_VALUE => C_M_AXI_RESULTS_OUT_PROT_VALUE, C_CACHE_VALUE => C_M_AXI_RESULTS_OUT_CACHE_VALUE) port map ( AWVALID => m_axi_results_out_AWVALID, AWREADY => m_axi_results_out_AWREADY, AWADDR => m_axi_results_out_AWADDR, AWID => m_axi_results_out_AWID, AWLEN => m_axi_results_out_AWLEN, AWSIZE => m_axi_results_out_AWSIZE, AWBURST => m_axi_results_out_AWBURST, AWLOCK => m_axi_results_out_AWLOCK, AWCACHE => m_axi_results_out_AWCACHE, AWPROT => m_axi_results_out_AWPROT, AWQOS => m_axi_results_out_AWQOS, AWREGION => m_axi_results_out_AWREGION, AWUSER => m_axi_results_out_AWUSER, WVALID => m_axi_results_out_WVALID, WREADY => m_axi_results_out_WREADY, WDATA => m_axi_results_out_WDATA, WSTRB => m_axi_results_out_WSTRB, WLAST => m_axi_results_out_WLAST, WID => m_axi_results_out_WID, WUSER => m_axi_results_out_WUSER, ARVALID => m_axi_results_out_ARVALID, ARREADY => m_axi_results_out_ARREADY, ARADDR => m_axi_results_out_ARADDR, ARID => m_axi_results_out_ARID, ARLEN => m_axi_results_out_ARLEN, ARSIZE => m_axi_results_out_ARSIZE, ARBURST => m_axi_results_out_ARBURST, ARLOCK => m_axi_results_out_ARLOCK, ARCACHE => m_axi_results_out_ARCACHE, ARPROT => m_axi_results_out_ARPROT, ARQOS => m_axi_results_out_ARQOS, ARREGION => m_axi_results_out_ARREGION, ARUSER => m_axi_results_out_ARUSER, RVALID => m_axi_results_out_RVALID, RREADY => m_axi_results_out_RREADY, RDATA => m_axi_results_out_RDATA, RLAST => m_axi_results_out_RLAST, RID => m_axi_results_out_RID, RUSER => m_axi_results_out_RUSER, RRESP => m_axi_results_out_RRESP, BVALID => m_axi_results_out_BVALID, BREADY => m_axi_results_out_BREADY, BRESP => m_axi_results_out_BRESP, BID => m_axi_results_out_BID, BUSER => m_axi_results_out_BUSER, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, I_ARVALID => ap_const_logic_0, I_ARREADY => results_out_ARREADY, I_ARADDR => ap_const_lv64_0, I_ARID => ap_const_lv1_0, I_ARLEN => ap_const_lv32_0, I_ARSIZE => ap_const_lv3_0, I_ARLOCK => ap_const_lv2_0, I_ARCACHE => ap_const_lv4_0, I_ARQOS => ap_const_lv4_0, I_ARPROT => ap_const_lv3_0, I_ARUSER => ap_const_lv1_0, I_ARBURST => ap_const_lv2_0, I_ARREGION => ap_const_lv4_0, I_RVALID => results_out_RVALID, I_RREADY => ap_const_logic_0, I_RDATA => results_out_RDATA, I_RID => results_out_RID, I_RUSER => results_out_RUSER, I_RRESP => results_out_RRESP, I_RLAST => results_out_RLAST, I_AWVALID => results_out_AWVALID, I_AWREADY => results_out_AWREADY, I_AWADDR => ap_reg_pp0_iter1_results_out_addr_reg_374, I_AWID => ap_const_lv1_0, I_AWLEN => ap_const_lv32_1, I_AWSIZE => ap_const_lv3_0, I_AWLOCK => ap_const_lv2_0, I_AWCACHE => ap_const_lv4_0, I_AWQOS => ap_const_lv4_0, I_AWPROT => ap_const_lv3_0, I_AWUSER => ap_const_lv1_0, I_AWBURST => ap_const_lv2_0, I_AWREGION => ap_const_lv4_0, I_WVALID => results_out_WVALID, I_WREADY => results_out_WREADY, I_WDATA => results_out_WDATA, I_WID => ap_const_lv1_0, I_WUSER => ap_const_lv1_0, I_WLAST => ap_const_logic_0, I_WSTRB => ap_const_lv1_1, I_BVALID => results_out_BVALID, I_BREADY => results_out_BREADY, I_BRESP => results_out_BRESP, I_BID => results_out_BID, I_BUSER => results_out_BUSER); grp_match_db_contact_fu_212 : component match_db_contact port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => grp_match_db_contact_fu_212_ap_start, ap_done => grp_match_db_contact_fu_212_ap_done, ap_idle => grp_match_db_contact_fu_212_ap_idle, ap_ready => grp_match_db_contact_fu_212_ap_ready, ap_ce => grp_match_db_contact_fu_212_ap_ce, db_item_V => db_mem_V_addr_read_reg_385, contacts_V_address0 => grp_match_db_contact_fu_212_contacts_V_address0, contacts_V_ce0 => grp_match_db_contact_fu_212_contacts_V_ce0, contacts_V_q0 => contacts_V_q0, contacts_V_address1 => grp_match_db_contact_fu_212_contacts_V_address1, contacts_V_ce1 => grp_match_db_contact_fu_212_contacts_V_ce1, contacts_V_q1 => contacts_V_q1, ap_return => grp_match_db_contact_fu_212_ap_return); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_fsm_state1; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_enable_reg_pp0_iter0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then ap_enable_reg_pp0_iter0 <= ap_const_logic_0; elsif (((operation_read_read_fu_130_p2 = ap_const_lv32_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then ap_enable_reg_pp0_iter0 <= ap_const_logic_1; end if; end if; end if; end process; ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))))) then ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state3 xor ap_const_logic_1); elsif ((((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)))) then ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; elsif (((operation_read_read_fu_130_p2 = ap_const_lv32_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; end if; end if; end if; end process; ap_reg_grp_match_db_contact_fu_212_ap_start_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_grp_match_db_contact_fu_212_ap_start <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op169_call_state12_state11))) then ap_reg_grp_match_db_contact_fu_212_ap_start <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_match_db_contact_fu_212_ap_ready)) then ap_reg_grp_match_db_contact_fu_212_ap_start <= ap_const_logic_0; end if; end if; end if; end process; ap_reg_ioackin_db_mem_V_ARREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_db_mem_V_ARREADY <= ap_const_logic_0; else if ((ap_condition_2628 = ap_const_boolean_1)) then if ((ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) then ap_reg_ioackin_db_mem_V_ARREADY <= ap_const_logic_0; elsif (((ap_const_logic_1 = db_mem_V_ARREADY) and (ap_block_pp0_stage1_flag00001001 = ap_const_boolean_0))) then ap_reg_ioackin_db_mem_V_ARREADY <= ap_const_logic_1; end if; end if; end if; end if; end process; ap_reg_ioackin_results_out_AWREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_results_out_AWREADY <= ap_const_logic_0; else if ((ap_condition_2632 = ap_const_boolean_1)) then if ((ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) then ap_reg_ioackin_results_out_AWREADY <= ap_const_logic_0; elsif (((ap_const_logic_1 = results_out_AWREADY) and (ap_block_pp0_stage9_flag00001001 = ap_const_boolean_0))) then ap_reg_ioackin_results_out_AWREADY <= ap_const_logic_1; end if; end if; end if; end if; end process; ap_reg_ioackin_results_out_WREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_results_out_WREADY <= ap_const_logic_0; else if ((ap_condition_2636 = ap_const_boolean_1)) then if ((ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) then ap_reg_ioackin_results_out_WREADY <= ap_const_logic_0; elsif (((ap_const_logic_1 = results_out_WREADY) and (ap_block_pp0_stage10_flag00001001 = ap_const_boolean_0))) then ap_reg_ioackin_results_out_WREADY <= ap_const_logic_1; end if; end if; end if; end if; end process; operation_ap_vld_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then operation_ap_vld_preg <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_CS_fsm_state86) and not(((ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then operation_ap_vld_preg <= ap_const_logic_0; elsif (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then operation_ap_vld_preg <= operation_ap_vld; end if; end if; end if; end process; operation_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then operation_preg <= ap_const_lv32_0; else if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then operation_preg <= operation; end if; end if; end if; end process; contacts_size_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_0 = icmp_fu_243_p2))) then contacts_size <= tmp_5_fu_253_p2; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_2))) then contacts_size <= ap_const_lv32_0; end if; end if; end process; contacts_size_out_1_vld_reg_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; database_index_reg_189_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then database_index_reg_189 <= database_index_1_reg_360; elsif (((operation_read_read_fu_130_p2 = ap_const_lv32_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then database_index_reg_189 <= ap_const_lv24_0; end if; end if; end process; error_out_1_vld_reg_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; storemerge_reg_200_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state84)) then storemerge_reg_200 <= contacts_size_load_reg_334; elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_0 = icmp_fu_243_p2))) then storemerge_reg_200 <= tmp_5_fu_253_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then ap_reg_pp0_iter1_results_out_addr_reg_374(23 downto 0) <= results_out_addr_reg_374(23 downto 0); ap_reg_pp0_iter1_tmp_127_reg_356 <= tmp_127_reg_356; ap_reg_pp0_iter1_tmp_8_reg_365 <= tmp_8_reg_365; tmp_127_reg_356 <= database_index_phi_fu_193_p4(23 downto 23); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))))) then contact_in_V_read_reg_325 <= contact_in_V; contacts_size_load_reg_334 <= contacts_size; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_0 = contacts_size_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then contacts_size_out_1_data_reg <= contacts_size_out_1_data_in; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then database_index_1_reg_360 <= database_index_1_fu_272_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_boolean_1 = ap_predicate_op168_read_state11) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then db_mem_V_addr_read_reg_385 <= db_mem_V_RDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_0 = error_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then error_out_1_data_reg <= error_out_1_data_in; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_127_fu_264_p3) and (ap_const_lv1_1 = tmp_8_fu_290_p2))) then results_out_addr_reg_374(23 downto 0) <= tmp_7_fu_282_p1(23 downto 0); sum_reg_369 <= sum_fu_295_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_1))) then tmp_126_reg_343 <= tmp_126_fu_230_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_127_fu_264_p3))) then tmp_8_reg_365 <= tmp_8_fu_290_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then tmp_s_reg_390 <= grp_match_db_contact_fu_212_ap_return; end if; end if; end process; results_out_addr_reg_374(63 downto 24) <= "0000000000000000000000000000000000000000"; ap_reg_pp0_iter1_results_out_addr_reg_374(63 downto 24) <= "0000000000000000000000000000000000000000"; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, operation_ap_vld_in_sig, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage15, operation_read_read_fu_130_p2, ap_CS_fsm_state2, icmp_fu_243_p2, ap_block_pp0_stage0_flag00011011, ap_predicate_tran3to83_state3, ap_block_pp0_stage63_flag00011011, ap_block_pp0_stage15_flag00011011, ap_CS_fsm_state86, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage13_flag00011011, ap_block_pp0_stage14_flag00011011, ap_block_pp0_stage16_flag00011011, ap_block_pp0_stage17_flag00011011, ap_block_pp0_stage18_flag00011011, ap_block_pp0_stage19_flag00011011, ap_block_pp0_stage20_flag00011011, ap_block_pp0_stage21_flag00011011, ap_block_pp0_stage22_flag00011011, ap_block_pp0_stage23_flag00011011, ap_block_pp0_stage24_flag00011011, ap_block_pp0_stage25_flag00011011, ap_block_pp0_stage26_flag00011011, ap_block_pp0_stage27_flag00011011, ap_block_pp0_stage28_flag00011011, ap_block_pp0_stage29_flag00011011, ap_block_pp0_stage30_flag00011011, ap_block_pp0_stage31_flag00011011, ap_block_pp0_stage32_flag00011011, ap_block_pp0_stage33_flag00011011, ap_block_pp0_stage34_flag00011011, ap_block_pp0_stage35_flag00011011, ap_block_pp0_stage36_flag00011011, ap_block_pp0_stage37_flag00011011, ap_block_pp0_stage38_flag00011011, ap_block_pp0_stage39_flag00011011, ap_block_pp0_stage40_flag00011011, ap_block_pp0_stage41_flag00011011, ap_block_pp0_stage42_flag00011011, ap_block_pp0_stage43_flag00011011, ap_block_pp0_stage44_flag00011011, ap_block_pp0_stage45_flag00011011, ap_block_pp0_stage46_flag00011011, ap_block_pp0_stage47_flag00011011, ap_block_pp0_stage48_flag00011011, ap_block_pp0_stage49_flag00011011, ap_block_pp0_stage50_flag00011011, ap_block_pp0_stage51_flag00011011, ap_block_pp0_stage52_flag00011011, ap_block_pp0_stage53_flag00011011, ap_block_pp0_stage54_flag00011011, ap_block_pp0_stage55_flag00011011, ap_block_pp0_stage56_flag00011011, ap_block_pp0_stage57_flag00011011, ap_block_pp0_stage58_flag00011011, ap_block_pp0_stage59_flag00011011, ap_block_pp0_stage60_flag00011011, ap_block_pp0_stage61_flag00011011, ap_block_pp0_stage62_flag00011011) begin case ap_CS_fsm is when ap_ST_fsm_state1 => if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state1; end if; when ap_ST_fsm_state2 => if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_0 = icmp_fu_243_p2))) then ap_NS_fsm <= ap_ST_fsm_state85; elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_1 = icmp_fu_243_p2))) then ap_NS_fsm <= ap_ST_fsm_state84; elsif (((operation_read_read_fu_130_p2 = ap_const_lv32_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; else ap_NS_fsm <= ap_ST_fsm_state86; end if; when ap_ST_fsm_pp0_stage0 => if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_tran3to83_state3) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage1; elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_tran3to83_state3) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_fsm_state83; else ap_NS_fsm <= ap_ST_fsm_pp0_stage0; end if; when ap_ST_fsm_pp0_stage1 => if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage2; else ap_NS_fsm <= ap_ST_fsm_pp0_stage1; end if; when ap_ST_fsm_pp0_stage2 => if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage3; else ap_NS_fsm <= ap_ST_fsm_pp0_stage2; end if; when ap_ST_fsm_pp0_stage3 => if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage4; else ap_NS_fsm <= ap_ST_fsm_pp0_stage3; end if; when ap_ST_fsm_pp0_stage4 => if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage5; else ap_NS_fsm <= ap_ST_fsm_pp0_stage4; end if; when ap_ST_fsm_pp0_stage5 => if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage6; else ap_NS_fsm <= ap_ST_fsm_pp0_stage5; end if; when ap_ST_fsm_pp0_stage6 => if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage7; else ap_NS_fsm <= ap_ST_fsm_pp0_stage6; end if; when ap_ST_fsm_pp0_stage7 => if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage8; else ap_NS_fsm <= ap_ST_fsm_pp0_stage7; end if; when ap_ST_fsm_pp0_stage8 => if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage9; else ap_NS_fsm <= ap_ST_fsm_pp0_stage8; end if; when ap_ST_fsm_pp0_stage9 => if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage10; else ap_NS_fsm <= ap_ST_fsm_pp0_stage9; end if; when ap_ST_fsm_pp0_stage10 => if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage11; else ap_NS_fsm <= ap_ST_fsm_pp0_stage10; end if; when ap_ST_fsm_pp0_stage11 => if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage12; else ap_NS_fsm <= ap_ST_fsm_pp0_stage11; end if; when ap_ST_fsm_pp0_stage12 => if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage13; else ap_NS_fsm <= ap_ST_fsm_pp0_stage12; end if; when ap_ST_fsm_pp0_stage13 => if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage14; else ap_NS_fsm <= ap_ST_fsm_pp0_stage13; end if; when ap_ST_fsm_pp0_stage14 => if ((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage15; else ap_NS_fsm <= ap_ST_fsm_pp0_stage14; end if; when ap_ST_fsm_pp0_stage15 => if (((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage16; elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_fsm_state83; else ap_NS_fsm <= ap_ST_fsm_pp0_stage15; end if; when ap_ST_fsm_pp0_stage16 => if ((ap_block_pp0_stage16_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage17; else ap_NS_fsm <= ap_ST_fsm_pp0_stage16; end if; when ap_ST_fsm_pp0_stage17 => if ((ap_block_pp0_stage17_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage18; else ap_NS_fsm <= ap_ST_fsm_pp0_stage17; end if; when ap_ST_fsm_pp0_stage18 => if ((ap_block_pp0_stage18_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage19; else ap_NS_fsm <= ap_ST_fsm_pp0_stage18; end if; when ap_ST_fsm_pp0_stage19 => if ((ap_block_pp0_stage19_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage20; else ap_NS_fsm <= ap_ST_fsm_pp0_stage19; end if; when ap_ST_fsm_pp0_stage20 => if ((ap_block_pp0_stage20_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage21; else ap_NS_fsm <= ap_ST_fsm_pp0_stage20; end if; when ap_ST_fsm_pp0_stage21 => if ((ap_block_pp0_stage21_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage22; else ap_NS_fsm <= ap_ST_fsm_pp0_stage21; end if; when ap_ST_fsm_pp0_stage22 => if ((ap_block_pp0_stage22_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage23; else ap_NS_fsm <= ap_ST_fsm_pp0_stage22; end if; when ap_ST_fsm_pp0_stage23 => if ((ap_block_pp0_stage23_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage24; else ap_NS_fsm <= ap_ST_fsm_pp0_stage23; end if; when ap_ST_fsm_pp0_stage24 => if ((ap_block_pp0_stage24_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage25; else ap_NS_fsm <= ap_ST_fsm_pp0_stage24; end if; when ap_ST_fsm_pp0_stage25 => if ((ap_block_pp0_stage25_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage26; else ap_NS_fsm <= ap_ST_fsm_pp0_stage25; end if; when ap_ST_fsm_pp0_stage26 => if ((ap_block_pp0_stage26_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage27; else ap_NS_fsm <= ap_ST_fsm_pp0_stage26; end if; when ap_ST_fsm_pp0_stage27 => if ((ap_block_pp0_stage27_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage28; else ap_NS_fsm <= ap_ST_fsm_pp0_stage27; end if; when ap_ST_fsm_pp0_stage28 => if ((ap_block_pp0_stage28_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage29; else ap_NS_fsm <= ap_ST_fsm_pp0_stage28; end if; when ap_ST_fsm_pp0_stage29 => if ((ap_block_pp0_stage29_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage30; else ap_NS_fsm <= ap_ST_fsm_pp0_stage29; end if; when ap_ST_fsm_pp0_stage30 => if ((ap_block_pp0_stage30_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage31; else ap_NS_fsm <= ap_ST_fsm_pp0_stage30; end if; when ap_ST_fsm_pp0_stage31 => if ((ap_block_pp0_stage31_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage32; else ap_NS_fsm <= ap_ST_fsm_pp0_stage31; end if; when ap_ST_fsm_pp0_stage32 => if ((ap_block_pp0_stage32_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage33; else ap_NS_fsm <= ap_ST_fsm_pp0_stage32; end if; when ap_ST_fsm_pp0_stage33 => if ((ap_block_pp0_stage33_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage34; else ap_NS_fsm <= ap_ST_fsm_pp0_stage33; end if; when ap_ST_fsm_pp0_stage34 => if ((ap_block_pp0_stage34_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage35; else ap_NS_fsm <= ap_ST_fsm_pp0_stage34; end if; when ap_ST_fsm_pp0_stage35 => if ((ap_block_pp0_stage35_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage36; else ap_NS_fsm <= ap_ST_fsm_pp0_stage35; end if; when ap_ST_fsm_pp0_stage36 => if ((ap_block_pp0_stage36_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage37; else ap_NS_fsm <= ap_ST_fsm_pp0_stage36; end if; when ap_ST_fsm_pp0_stage37 => if ((ap_block_pp0_stage37_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage38; else ap_NS_fsm <= ap_ST_fsm_pp0_stage37; end if; when ap_ST_fsm_pp0_stage38 => if ((ap_block_pp0_stage38_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage39; else ap_NS_fsm <= ap_ST_fsm_pp0_stage38; end if; when ap_ST_fsm_pp0_stage39 => if ((ap_block_pp0_stage39_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage40; else ap_NS_fsm <= ap_ST_fsm_pp0_stage39; end if; when ap_ST_fsm_pp0_stage40 => if ((ap_block_pp0_stage40_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage41; else ap_NS_fsm <= ap_ST_fsm_pp0_stage40; end if; when ap_ST_fsm_pp0_stage41 => if ((ap_block_pp0_stage41_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage42; else ap_NS_fsm <= ap_ST_fsm_pp0_stage41; end if; when ap_ST_fsm_pp0_stage42 => if ((ap_block_pp0_stage42_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage43; else ap_NS_fsm <= ap_ST_fsm_pp0_stage42; end if; when ap_ST_fsm_pp0_stage43 => if ((ap_block_pp0_stage43_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage44; else ap_NS_fsm <= ap_ST_fsm_pp0_stage43; end if; when ap_ST_fsm_pp0_stage44 => if ((ap_block_pp0_stage44_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage45; else ap_NS_fsm <= ap_ST_fsm_pp0_stage44; end if; when ap_ST_fsm_pp0_stage45 => if ((ap_block_pp0_stage45_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage46; else ap_NS_fsm <= ap_ST_fsm_pp0_stage45; end if; when ap_ST_fsm_pp0_stage46 => if ((ap_block_pp0_stage46_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage47; else ap_NS_fsm <= ap_ST_fsm_pp0_stage46; end if; when ap_ST_fsm_pp0_stage47 => if ((ap_block_pp0_stage47_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage48; else ap_NS_fsm <= ap_ST_fsm_pp0_stage47; end if; when ap_ST_fsm_pp0_stage48 => if ((ap_block_pp0_stage48_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage49; else ap_NS_fsm <= ap_ST_fsm_pp0_stage48; end if; when ap_ST_fsm_pp0_stage49 => if ((ap_block_pp0_stage49_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage50; else ap_NS_fsm <= ap_ST_fsm_pp0_stage49; end if; when ap_ST_fsm_pp0_stage50 => if ((ap_block_pp0_stage50_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage51; else ap_NS_fsm <= ap_ST_fsm_pp0_stage50; end if; when ap_ST_fsm_pp0_stage51 => if ((ap_block_pp0_stage51_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage52; else ap_NS_fsm <= ap_ST_fsm_pp0_stage51; end if; when ap_ST_fsm_pp0_stage52 => if ((ap_block_pp0_stage52_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage53; else ap_NS_fsm <= ap_ST_fsm_pp0_stage52; end if; when ap_ST_fsm_pp0_stage53 => if ((ap_block_pp0_stage53_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage54; else ap_NS_fsm <= ap_ST_fsm_pp0_stage53; end if; when ap_ST_fsm_pp0_stage54 => if ((ap_block_pp0_stage54_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage55; else ap_NS_fsm <= ap_ST_fsm_pp0_stage54; end if; when ap_ST_fsm_pp0_stage55 => if ((ap_block_pp0_stage55_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage56; else ap_NS_fsm <= ap_ST_fsm_pp0_stage55; end if; when ap_ST_fsm_pp0_stage56 => if ((ap_block_pp0_stage56_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage57; else ap_NS_fsm <= ap_ST_fsm_pp0_stage56; end if; when ap_ST_fsm_pp0_stage57 => if ((ap_block_pp0_stage57_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage58; else ap_NS_fsm <= ap_ST_fsm_pp0_stage57; end if; when ap_ST_fsm_pp0_stage58 => if ((ap_block_pp0_stage58_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage59; else ap_NS_fsm <= ap_ST_fsm_pp0_stage58; end if; when ap_ST_fsm_pp0_stage59 => if ((ap_block_pp0_stage59_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage60; else ap_NS_fsm <= ap_ST_fsm_pp0_stage59; end if; when ap_ST_fsm_pp0_stage60 => if ((ap_block_pp0_stage60_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage61; else ap_NS_fsm <= ap_ST_fsm_pp0_stage60; end if; when ap_ST_fsm_pp0_stage61 => if ((ap_block_pp0_stage61_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage62; else ap_NS_fsm <= ap_ST_fsm_pp0_stage61; end if; when ap_ST_fsm_pp0_stage62 => if ((ap_block_pp0_stage62_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage63; else ap_NS_fsm <= ap_ST_fsm_pp0_stage62; end if; when ap_ST_fsm_pp0_stage63 => if ((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; else ap_NS_fsm <= ap_ST_fsm_pp0_stage63; end if; when ap_ST_fsm_state83 => ap_NS_fsm <= ap_ST_fsm_state86; when ap_ST_fsm_state84 => ap_NS_fsm <= ap_ST_fsm_state85; when ap_ST_fsm_state85 => ap_NS_fsm <= ap_ST_fsm_state86; when ap_ST_fsm_state86 => if (((ap_const_logic_1 = ap_CS_fsm_state86) and not(((ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then ap_NS_fsm <= ap_ST_fsm_state1; else ap_NS_fsm <= ap_ST_fsm_state86; end if; when others => ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end case; end process; ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2); ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(3); ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(12); ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(13); ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(14); ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(15); ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(16); ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(17); ap_CS_fsm_pp0_stage16 <= ap_CS_fsm(18); ap_CS_fsm_pp0_stage17 <= ap_CS_fsm(19); ap_CS_fsm_pp0_stage18 <= ap_CS_fsm(20); ap_CS_fsm_pp0_stage19 <= ap_CS_fsm(21); ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(4); ap_CS_fsm_pp0_stage20 <= ap_CS_fsm(22); ap_CS_fsm_pp0_stage21 <= ap_CS_fsm(23); ap_CS_fsm_pp0_stage22 <= ap_CS_fsm(24); ap_CS_fsm_pp0_stage23 <= ap_CS_fsm(25); ap_CS_fsm_pp0_stage24 <= ap_CS_fsm(26); ap_CS_fsm_pp0_stage25 <= ap_CS_fsm(27); ap_CS_fsm_pp0_stage26 <= ap_CS_fsm(28); ap_CS_fsm_pp0_stage27 <= ap_CS_fsm(29); ap_CS_fsm_pp0_stage28 <= ap_CS_fsm(30); ap_CS_fsm_pp0_stage29 <= ap_CS_fsm(31); ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(5); ap_CS_fsm_pp0_stage30 <= ap_CS_fsm(32); ap_CS_fsm_pp0_stage31 <= ap_CS_fsm(33); ap_CS_fsm_pp0_stage32 <= ap_CS_fsm(34); ap_CS_fsm_pp0_stage33 <= ap_CS_fsm(35); ap_CS_fsm_pp0_stage34 <= ap_CS_fsm(36); ap_CS_fsm_pp0_stage35 <= ap_CS_fsm(37); ap_CS_fsm_pp0_stage36 <= ap_CS_fsm(38); ap_CS_fsm_pp0_stage37 <= ap_CS_fsm(39); ap_CS_fsm_pp0_stage38 <= ap_CS_fsm(40); ap_CS_fsm_pp0_stage39 <= ap_CS_fsm(41); ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(6); ap_CS_fsm_pp0_stage40 <= ap_CS_fsm(42); ap_CS_fsm_pp0_stage41 <= ap_CS_fsm(43); ap_CS_fsm_pp0_stage42 <= ap_CS_fsm(44); ap_CS_fsm_pp0_stage43 <= ap_CS_fsm(45); ap_CS_fsm_pp0_stage44 <= ap_CS_fsm(46); ap_CS_fsm_pp0_stage45 <= ap_CS_fsm(47); ap_CS_fsm_pp0_stage46 <= ap_CS_fsm(48); ap_CS_fsm_pp0_stage47 <= ap_CS_fsm(49); ap_CS_fsm_pp0_stage48 <= ap_CS_fsm(50); ap_CS_fsm_pp0_stage49 <= ap_CS_fsm(51); ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(7); ap_CS_fsm_pp0_stage50 <= ap_CS_fsm(52); ap_CS_fsm_pp0_stage51 <= ap_CS_fsm(53); ap_CS_fsm_pp0_stage52 <= ap_CS_fsm(54); ap_CS_fsm_pp0_stage53 <= ap_CS_fsm(55); ap_CS_fsm_pp0_stage54 <= ap_CS_fsm(56); ap_CS_fsm_pp0_stage55 <= ap_CS_fsm(57); ap_CS_fsm_pp0_stage56 <= ap_CS_fsm(58); ap_CS_fsm_pp0_stage57 <= ap_CS_fsm(59); ap_CS_fsm_pp0_stage58 <= ap_CS_fsm(60); ap_CS_fsm_pp0_stage59 <= ap_CS_fsm(61); ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(8); ap_CS_fsm_pp0_stage60 <= ap_CS_fsm(62); ap_CS_fsm_pp0_stage61 <= ap_CS_fsm(63); ap_CS_fsm_pp0_stage62 <= ap_CS_fsm(64); ap_CS_fsm_pp0_stage63 <= ap_CS_fsm(65); ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(9); ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(10); ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(11); ap_CS_fsm_state1 <= ap_CS_fsm(0); ap_CS_fsm_state2 <= ap_CS_fsm(1); ap_CS_fsm_state84 <= ap_CS_fsm(67); ap_CS_fsm_state85 <= ap_CS_fsm(68); ap_CS_fsm_state86 <= ap_CS_fsm(69); ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage10_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage10_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter1, ap_block_state77_io) begin ap_block_pp0_stage10_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_block_state77_io)); end process; ap_block_pp0_stage10_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter1, ap_block_state77_io) begin ap_block_pp0_stage10_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_block_state77_io)); end process; ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage11_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage12_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage13_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage13_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage14_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage14_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage15_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage15_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter1, results_out_BVALID, ap_predicate_op241_writeresp_state82) begin ap_block_pp0_stage15_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = results_out_BVALID) and (ap_const_boolean_1 = ap_predicate_op241_writeresp_state82)); end process; ap_block_pp0_stage15_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter1, results_out_BVALID, ap_predicate_op241_writeresp_state82) begin ap_block_pp0_stage15_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = results_out_BVALID) and (ap_const_boolean_1 = ap_predicate_op241_writeresp_state82)); end process; ap_block_pp0_stage16_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage16_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage16_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage17_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage17_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage17_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage18_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage18_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage18_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage19_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage19_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage19_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage1_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage1_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state4_io) begin ap_block_pp0_stage1_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state4_io)); end process; ap_block_pp0_stage1_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state4_io) begin ap_block_pp0_stage1_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state4_io)); end process; ap_block_pp0_stage20_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage20_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage20_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage21_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage21_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage21_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage22_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage22_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage22_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage23_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage23_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage23_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage24_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage24_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage24_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage25_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage25_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage25_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage26_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage26_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage26_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage27_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage27_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage27_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage28_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage28_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage28_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage29_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage29_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage29_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage30_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage30_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage30_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage31_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage31_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage31_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage32_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage32_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage32_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage33_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage33_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage33_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage34_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage34_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage34_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage35_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage35_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage35_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage36_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage36_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage36_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage37_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage37_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage37_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage38_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage38_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage38_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage39_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage39_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage39_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage40_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage40_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage40_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage41_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage41_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage41_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage42_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage42_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage42_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage43_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage43_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage43_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage44_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage44_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage44_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage45_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage45_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage45_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage46_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage46_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage46_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage47_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage47_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage47_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage48_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage48_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage48_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage49_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage49_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage49_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage50_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage50_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage50_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage51_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage51_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage51_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage52_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage52_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage52_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage53_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage53_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage53_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage54_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage54_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage54_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage55_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage55_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage55_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage56_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage56_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage56_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage57_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage57_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage57_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage58_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage58_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage58_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage59_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage59_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage59_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage60_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage60_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage60_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage61_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage61_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage61_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage62_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage62_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage62_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage63_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage63_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage63_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage6_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage7_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage8_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, db_mem_V_RVALID, ap_predicate_op168_read_state11) begin ap_block_pp0_stage8_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = db_mem_V_RVALID) and (ap_const_boolean_1 = ap_predicate_op168_read_state11)); end process; ap_block_pp0_stage8_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, db_mem_V_RVALID, ap_predicate_op168_read_state11) begin ap_block_pp0_stage8_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = db_mem_V_RVALID) and (ap_const_boolean_1 = ap_predicate_op168_read_state11)); end process; ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage9_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage9_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter1, ap_block_state76_io) begin ap_block_pp0_stage9_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_block_state76_io)); end process; ap_block_pp0_stage9_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter1, ap_block_state76_io) begin ap_block_pp0_stage9_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_block_state76_io)); end process; ap_block_state1_assign_proc : process(ap_start, operation_ap_vld_in_sig) begin ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig)); end process; ap_block_state10_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state10_pp0_stage7_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state11_pp0_stage8_iter0_assign_proc : process(db_mem_V_RVALID, ap_predicate_op168_read_state11) begin ap_block_state11_pp0_stage8_iter0 <= ((ap_const_logic_0 = db_mem_V_RVALID) and (ap_const_boolean_1 = ap_predicate_op168_read_state11)); end process; ap_block_state12_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state13_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state13_pp0_stage10_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state14_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state14_pp0_stage11_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state15_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state15_pp0_stage12_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state16_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state16_pp0_stage13_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state17_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state17_pp0_stage14_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state18_pp0_stage15_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state18_pp0_stage15_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state19_pp0_stage16_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state19_pp0_stage16_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state20_pp0_stage17_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state20_pp0_stage17_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state21_pp0_stage18_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state21_pp0_stage18_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state22_pp0_stage19_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state22_pp0_stage19_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state23_pp0_stage20_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state23_pp0_stage20_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state24_pp0_stage21_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state24_pp0_stage21_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state25_pp0_stage22_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state25_pp0_stage22_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state26_pp0_stage23_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state26_pp0_stage23_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state27_pp0_stage24_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state27_pp0_stage24_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state28_pp0_stage25_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state28_pp0_stage25_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state29_pp0_stage26_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state29_pp0_stage26_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state30_pp0_stage27_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state30_pp0_stage27_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state31_pp0_stage28_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state31_pp0_stage28_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state32_pp0_stage29_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state32_pp0_stage29_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state33_pp0_stage30_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state33_pp0_stage30_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state34_pp0_stage31_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state34_pp0_stage31_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state35_pp0_stage32_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state35_pp0_stage32_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state36_pp0_stage33_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state36_pp0_stage33_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state37_pp0_stage34_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state37_pp0_stage34_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state38_pp0_stage35_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state38_pp0_stage35_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state39_pp0_stage36_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state39_pp0_stage36_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state40_pp0_stage37_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state40_pp0_stage37_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state41_pp0_stage38_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state41_pp0_stage38_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state42_pp0_stage39_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state42_pp0_stage39_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state43_pp0_stage40_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state43_pp0_stage40_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state44_pp0_stage41_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state44_pp0_stage41_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state45_pp0_stage42_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state45_pp0_stage42_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state46_pp0_stage43_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state46_pp0_stage43_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state47_pp0_stage44_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state47_pp0_stage44_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state48_pp0_stage45_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state48_pp0_stage45_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state49_pp0_stage46_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state49_pp0_stage46_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state4_io_assign_proc : process(ap_sig_ioackin_db_mem_V_ARREADY, ap_predicate_op161_readreq_state4) begin ap_block_state4_io <= ((ap_const_logic_0 = ap_sig_ioackin_db_mem_V_ARREADY) and (ap_const_boolean_1 = ap_predicate_op161_readreq_state4)); end process; ap_block_state4_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state50_pp0_stage47_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state50_pp0_stage47_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state51_pp0_stage48_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state51_pp0_stage48_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state52_pp0_stage49_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state52_pp0_stage49_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state53_pp0_stage50_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state53_pp0_stage50_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state54_pp0_stage51_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state54_pp0_stage51_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state55_pp0_stage52_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state55_pp0_stage52_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state56_pp0_stage53_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state56_pp0_stage53_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state57_pp0_stage54_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state57_pp0_stage54_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state58_pp0_stage55_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state58_pp0_stage55_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state59_pp0_stage56_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state59_pp0_stage56_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state5_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state5_pp0_stage2_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state60_pp0_stage57_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state60_pp0_stage57_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state61_pp0_stage58_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state61_pp0_stage58_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state62_pp0_stage59_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state62_pp0_stage59_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state63_pp0_stage60_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state63_pp0_stage60_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state64_pp0_stage61_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state64_pp0_stage61_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state65_pp0_stage62_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state65_pp0_stage62_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state66_pp0_stage63_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state66_pp0_stage63_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state67_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state68_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state69_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state69_pp0_stage2_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state6_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state6_pp0_stage3_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state70_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state70_pp0_stage3_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state71_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state71_pp0_stage4_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state72_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state72_pp0_stage5_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state73_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state73_pp0_stage6_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state74_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state74_pp0_stage7_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state75_pp0_stage8_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state76_io_assign_proc : process(ap_sig_ioackin_results_out_AWREADY, ap_predicate_op234_writereq_state76) begin ap_block_state76_io <= ((ap_const_logic_0 = ap_sig_ioackin_results_out_AWREADY) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76)); end process; ap_block_state76_pp0_stage9_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state77_io_assign_proc : process(ap_sig_ioackin_results_out_WREADY, ap_predicate_op236_write_state77) begin ap_block_state77_io <= ((ap_const_logic_0 = ap_sig_ioackin_results_out_WREADY) and (ap_const_boolean_1 = ap_predicate_op236_write_state77)); end process; ap_block_state77_pp0_stage10_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state77_pp0_stage10_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state78_pp0_stage11_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state78_pp0_stage11_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state79_pp0_stage12_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state79_pp0_stage12_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state7_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state7_pp0_stage4_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state80_pp0_stage13_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state80_pp0_stage13_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state81_pp0_stage14_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state81_pp0_stage14_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state82_pp0_stage15_iter1_assign_proc : process(results_out_BVALID, ap_predicate_op241_writeresp_state82) begin ap_block_state82_pp0_stage15_iter1 <= ((ap_const_logic_0 = results_out_BVALID) and (ap_const_boolean_1 = ap_predicate_op241_writeresp_state82)); end process; ap_block_state82_pp0_stage15_iter1_ignore_call5_assign_proc : process(results_out_BVALID, ap_predicate_op241_writeresp_state82) begin ap_block_state82_pp0_stage15_iter1_ignore_call5 <= ((ap_const_logic_0 = results_out_BVALID) and (ap_const_boolean_1 = ap_predicate_op241_writeresp_state82)); end process; ap_block_state86_assign_proc : process(error_out_1_ack_in, contacts_size_out_1_ack_in) begin ap_block_state86 <= ((ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in)); end process; ap_block_state8_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state8_pp0_stage5_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state9_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state9_pp0_stage6_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_condition_2628_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_predicate_op161_readreq_state4) begin ap_condition_2628 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op161_readreq_state4)); end process; ap_condition_2632_assign_proc : process(ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_predicate_op234_writereq_state76) begin ap_condition_2632 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76)); end process; ap_condition_2636_assign_proc : process(ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage10, ap_predicate_op236_write_state77) begin ap_condition_2636 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_boolean_1 = ap_predicate_op236_write_state77)); end process; ap_condition_pp0_exit_iter0_state3_assign_proc : process(ap_predicate_tran3to83_state3) begin if ((ap_const_boolean_1 = ap_predicate_tran3to83_state3)) then ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1; else ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0; end if; end process; ap_done_assign_proc : process(error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state86) begin if (((ap_const_logic_1 = ap_CS_fsm_state86) and not(((ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1); ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1) begin if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then ap_idle_pp0 <= ap_const_logic_1; else ap_idle_pp0 <= ap_const_logic_0; end if; end process; ap_predicate_op161_readreq_state4_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op161_readreq_state4 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op168_read_state11_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op168_read_state11 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op169_call_state12_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op169_call_state12 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op169_call_state12_state11_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op169_call_state12_state11 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op170_call_state13_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op170_call_state13 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op171_call_state14_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op171_call_state14 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op172_call_state15_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op172_call_state15 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op173_call_state16_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op173_call_state16 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op174_call_state17_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op174_call_state17 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op175_call_state18_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op175_call_state18 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op176_call_state19_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op176_call_state19 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op177_call_state20_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op177_call_state20 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op178_call_state21_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op178_call_state21 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op179_call_state22_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op179_call_state22 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op180_call_state23_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op180_call_state23 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op181_call_state24_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op181_call_state24 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op182_call_state25_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op182_call_state25 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op183_call_state26_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op183_call_state26 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op184_call_state27_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op184_call_state27 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op185_call_state28_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op185_call_state28 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op186_call_state29_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op186_call_state29 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op187_call_state30_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op187_call_state30 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op188_call_state31_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op188_call_state31 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op189_call_state32_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op189_call_state32 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op190_call_state33_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op190_call_state33 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op191_call_state34_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op191_call_state34 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op192_call_state35_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op192_call_state35 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op193_call_state36_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op193_call_state36 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op194_call_state37_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op194_call_state37 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op195_call_state38_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op195_call_state38 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op196_call_state39_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op196_call_state39 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op197_call_state40_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op197_call_state40 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op198_call_state41_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op198_call_state41 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op199_call_state42_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op199_call_state42 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op200_call_state43_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op200_call_state43 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op201_call_state44_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op201_call_state44 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op202_call_state45_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op202_call_state45 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op203_call_state46_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op203_call_state46 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op204_call_state47_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op204_call_state47 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op205_call_state48_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op205_call_state48 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op206_call_state49_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op206_call_state49 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op207_call_state50_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op207_call_state50 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op208_call_state51_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op208_call_state51 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op209_call_state52_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op209_call_state52 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op210_call_state53_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op210_call_state53 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op211_call_state54_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op211_call_state54 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op212_call_state55_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op212_call_state55 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op213_call_state56_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op213_call_state56 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op214_call_state57_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op214_call_state57 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op215_call_state58_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op215_call_state58 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op216_call_state59_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op216_call_state59 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op217_call_state60_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op217_call_state60 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op218_call_state61_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op218_call_state61 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op219_call_state62_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op219_call_state62 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op220_call_state63_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op220_call_state63 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op221_call_state64_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op221_call_state64 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op222_call_state65_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op222_call_state65 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op223_call_state66_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op223_call_state66 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op224_call_state67_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op224_call_state67 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op225_call_state68_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op225_call_state68 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op226_call_state69_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op226_call_state69 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op227_call_state70_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op227_call_state70 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op228_call_state71_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op228_call_state71 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op229_call_state72_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op229_call_state72 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op230_call_state73_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op230_call_state73 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op231_call_state74_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op231_call_state74 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op232_call_state75_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op232_call_state75 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op234_writereq_state76_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op234_writereq_state76 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op236_write_state77_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op236_write_state77 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op241_writeresp_state82_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op241_writeresp_state82 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_tran3to83_state3_assign_proc : process(tmp_127_fu_264_p3, tmp_8_fu_290_p2) begin ap_predicate_tran3to83_state3 <= ((ap_const_lv1_1 = tmp_127_fu_264_p3) or ((ap_const_lv1_0 = tmp_127_fu_264_p3) and (ap_const_lv1_0 = tmp_8_fu_290_p2))); end process; ap_ready_assign_proc : process(error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state86) begin if (((ap_const_logic_1 = ap_CS_fsm_state86) and not(((ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; ap_sig_ioackin_db_mem_V_ARREADY_assign_proc : process(db_mem_V_ARREADY, ap_reg_ioackin_db_mem_V_ARREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_db_mem_V_ARREADY)) then ap_sig_ioackin_db_mem_V_ARREADY <= db_mem_V_ARREADY; else ap_sig_ioackin_db_mem_V_ARREADY <= ap_const_logic_1; end if; end process; ap_sig_ioackin_results_out_AWREADY_assign_proc : process(results_out_AWREADY, ap_reg_ioackin_results_out_AWREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_results_out_AWREADY)) then ap_sig_ioackin_results_out_AWREADY <= results_out_AWREADY; else ap_sig_ioackin_results_out_AWREADY <= ap_const_logic_1; end if; end process; ap_sig_ioackin_results_out_WREADY_assign_proc : process(results_out_WREADY, ap_reg_ioackin_results_out_WREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_results_out_WREADY)) then ap_sig_ioackin_results_out_WREADY <= results_out_WREADY; else ap_sig_ioackin_results_out_WREADY <= ap_const_logic_1; end if; end process; contacts_V_address0_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_block_pp0_stage1_flag00000000, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00000000, ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_block_pp0_stage9_flag00000000, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00000000, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00000000, ap_CS_fsm_state2, ap_CS_fsm_pp0_stage0, ap_predicate_op234_writereq_state76, ap_CS_fsm_pp0_stage63, grp_match_db_contact_fu_212_contacts_V_address0, ap_predicate_op169_call_state12, ap_predicate_op170_call_state13, ap_predicate_op171_call_state14, ap_predicate_op172_call_state15, ap_predicate_op173_call_state16, ap_predicate_op174_call_state17, ap_predicate_op175_call_state18, ap_predicate_op176_call_state19, ap_predicate_op177_call_state20, ap_predicate_op178_call_state21, ap_predicate_op179_call_state22, ap_predicate_op180_call_state23, ap_predicate_op181_call_state24, ap_predicate_op182_call_state25, ap_predicate_op183_call_state26, ap_predicate_op184_call_state27, ap_predicate_op185_call_state28, ap_predicate_op186_call_state29, ap_predicate_op187_call_state30, ap_predicate_op188_call_state31, ap_predicate_op189_call_state32, ap_predicate_op190_call_state33, ap_predicate_op191_call_state34, ap_predicate_op192_call_state35, ap_predicate_op193_call_state36, ap_predicate_op194_call_state37, ap_predicate_op195_call_state38, ap_predicate_op196_call_state39, ap_predicate_op197_call_state40, ap_predicate_op198_call_state41, ap_predicate_op199_call_state42, ap_predicate_op200_call_state43, ap_predicate_op201_call_state44, ap_predicate_op202_call_state45, ap_predicate_op203_call_state46, ap_predicate_op204_call_state47, ap_predicate_op205_call_state48, ap_predicate_op206_call_state49, ap_predicate_op207_call_state50, ap_predicate_op208_call_state51, ap_predicate_op209_call_state52, ap_predicate_op210_call_state53, ap_predicate_op211_call_state54, ap_predicate_op212_call_state55, ap_predicate_op213_call_state56, ap_predicate_op214_call_state57, ap_predicate_op215_call_state58, ap_predicate_op216_call_state59, ap_predicate_op217_call_state60, ap_predicate_op218_call_state61, ap_predicate_op219_call_state62, ap_predicate_op220_call_state63, ap_predicate_op221_call_state64, ap_predicate_op222_call_state65, ap_predicate_op223_call_state66, ap_predicate_op224_call_state67, ap_predicate_op225_call_state68, ap_predicate_op226_call_state69, ap_predicate_op227_call_state70, ap_predicate_op228_call_state71, ap_predicate_op229_call_state72, ap_predicate_op230_call_state73, ap_predicate_op231_call_state74, ap_predicate_op232_call_state75, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, tmp_4_fu_249_p1) begin if ((ap_const_logic_1 = ap_CS_fsm_state2)) then contacts_V_address0 <= tmp_4_fu_249_p1(7 - 1 downto 0); elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op169_call_state12)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op170_call_state13)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op171_call_state14) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op172_call_state15) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op173_call_state16) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op174_call_state17) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op175_call_state18)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op176_call_state19) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op177_call_state20) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op178_call_state21) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op179_call_state22) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op180_call_state23) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op181_call_state24) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op182_call_state25) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op183_call_state26) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op184_call_state27) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op185_call_state28) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op186_call_state29) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op187_call_state30) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op188_call_state31) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op189_call_state32) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op190_call_state33) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op191_call_state34) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op192_call_state35) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op193_call_state36) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op194_call_state37) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op195_call_state38) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op196_call_state39) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op197_call_state40) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op198_call_state41) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op199_call_state42) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op200_call_state43) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op201_call_state44) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op202_call_state45) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op203_call_state46) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op204_call_state47) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op205_call_state48) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op206_call_state49) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op207_call_state50) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op208_call_state51) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op209_call_state52) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op210_call_state53) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op211_call_state54) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op212_call_state55) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op213_call_state56) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op214_call_state57) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op215_call_state58) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op216_call_state59) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op217_call_state60) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op218_call_state61) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op219_call_state62) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op220_call_state63) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op221_call_state64) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op222_call_state65) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_const_boolean_1 = ap_predicate_op223_call_state66) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_1 = ap_predicate_op224_call_state67) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op225_call_state68)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op226_call_state69) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op227_call_state70) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op228_call_state71) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op229_call_state72) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op230_call_state73) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op231_call_state74) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op232_call_state75)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76)))) then contacts_V_address0 <= grp_match_db_contact_fu_212_contacts_V_address0; else contacts_V_address0 <= "XXXXXXX"; end if; end process; contacts_V_ce0_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage15, ap_CS_fsm_state2, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_block_pp0_stage1_flag00011001, ap_block_pp0_stage8_flag00011001, ap_predicate_op234_writereq_state76, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage63, grp_match_db_contact_fu_212_contacts_V_ce0, ap_predicate_op169_call_state12, ap_predicate_op170_call_state13, ap_predicate_op171_call_state14, ap_predicate_op172_call_state15, ap_predicate_op173_call_state16, ap_predicate_op174_call_state17, ap_predicate_op175_call_state18, ap_predicate_op176_call_state19, ap_predicate_op177_call_state20, ap_predicate_op178_call_state21, ap_predicate_op179_call_state22, ap_predicate_op180_call_state23, ap_predicate_op181_call_state24, ap_predicate_op182_call_state25, ap_predicate_op183_call_state26, ap_predicate_op184_call_state27, ap_predicate_op185_call_state28, ap_predicate_op186_call_state29, ap_predicate_op187_call_state30, ap_predicate_op188_call_state31, ap_predicate_op189_call_state32, ap_predicate_op190_call_state33, ap_predicate_op191_call_state34, ap_predicate_op192_call_state35, ap_predicate_op193_call_state36, ap_predicate_op194_call_state37, ap_predicate_op195_call_state38, ap_predicate_op196_call_state39, ap_predicate_op197_call_state40, ap_predicate_op198_call_state41, ap_predicate_op199_call_state42, ap_predicate_op200_call_state43, ap_predicate_op201_call_state44, ap_predicate_op202_call_state45, ap_predicate_op203_call_state46, ap_predicate_op204_call_state47, ap_predicate_op205_call_state48, ap_predicate_op206_call_state49, ap_predicate_op207_call_state50, ap_predicate_op208_call_state51, ap_predicate_op209_call_state52, ap_predicate_op210_call_state53, ap_predicate_op211_call_state54, ap_predicate_op212_call_state55, ap_predicate_op213_call_state56, ap_predicate_op214_call_state57, ap_predicate_op215_call_state58, ap_predicate_op216_call_state59, ap_predicate_op217_call_state60, ap_predicate_op218_call_state61, ap_predicate_op219_call_state62, ap_predicate_op220_call_state63, ap_predicate_op221_call_state64, ap_predicate_op222_call_state65, ap_predicate_op223_call_state66, ap_predicate_op224_call_state67, ap_predicate_op225_call_state68, ap_predicate_op226_call_state69, ap_predicate_op227_call_state70, ap_predicate_op228_call_state71, ap_predicate_op229_call_state72, ap_predicate_op230_call_state73, ap_predicate_op231_call_state74, ap_predicate_op232_call_state75, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage62_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage63_flag00011001, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage7) begin if ((ap_const_logic_1 = ap_CS_fsm_state2)) then contacts_V_ce0 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op169_call_state12)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_boolean_1 = ap_predicate_op170_call_state13) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op171_call_state14) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op172_call_state15) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op173_call_state16) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op174_call_state17) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_boolean_1 = ap_predicate_op175_call_state18) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op176_call_state19) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op177_call_state20) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op178_call_state21) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op179_call_state22) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op180_call_state23) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op181_call_state24) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op182_call_state25) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op183_call_state26) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op184_call_state27) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op185_call_state28) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op186_call_state29) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op187_call_state30) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op188_call_state31) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op189_call_state32) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op190_call_state33) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op191_call_state34) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op192_call_state35) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op193_call_state36) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op194_call_state37) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op195_call_state38) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op196_call_state39) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op197_call_state40) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op198_call_state41) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op199_call_state42) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op200_call_state43) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op201_call_state44) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op202_call_state45) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op203_call_state46) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op204_call_state47) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op205_call_state48) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op206_call_state49) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op207_call_state50) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op208_call_state51) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op209_call_state52) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op210_call_state53) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op211_call_state54) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op212_call_state55) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op213_call_state56) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op214_call_state57) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op215_call_state58) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op216_call_state59) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op217_call_state60) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op218_call_state61) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op219_call_state62) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op220_call_state63) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op221_call_state64) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op222_call_state65) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_const_boolean_1 = ap_predicate_op223_call_state66) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op224_call_state67)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op225_call_state68)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op226_call_state69) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op227_call_state70) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op228_call_state71) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op229_call_state72) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op230_call_state73) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op231_call_state74) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op232_call_state75)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)))) then contacts_V_ce0 <= grp_match_db_contact_fu_212_contacts_V_ce0; else contacts_V_ce0 <= ap_const_logic_0; end if; end process; contacts_V_ce1_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_block_pp0_stage1_flag00011001, ap_block_pp0_stage8_flag00011001, ap_predicate_op234_writereq_state76, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage63, grp_match_db_contact_fu_212_contacts_V_ce1, ap_predicate_op169_call_state12, ap_predicate_op170_call_state13, ap_predicate_op171_call_state14, ap_predicate_op172_call_state15, ap_predicate_op173_call_state16, ap_predicate_op174_call_state17, ap_predicate_op175_call_state18, ap_predicate_op176_call_state19, ap_predicate_op177_call_state20, ap_predicate_op178_call_state21, ap_predicate_op179_call_state22, ap_predicate_op180_call_state23, ap_predicate_op181_call_state24, ap_predicate_op182_call_state25, ap_predicate_op183_call_state26, ap_predicate_op184_call_state27, ap_predicate_op185_call_state28, ap_predicate_op186_call_state29, ap_predicate_op187_call_state30, ap_predicate_op188_call_state31, ap_predicate_op189_call_state32, ap_predicate_op190_call_state33, ap_predicate_op191_call_state34, ap_predicate_op192_call_state35, ap_predicate_op193_call_state36, ap_predicate_op194_call_state37, ap_predicate_op195_call_state38, ap_predicate_op196_call_state39, ap_predicate_op197_call_state40, ap_predicate_op198_call_state41, ap_predicate_op199_call_state42, ap_predicate_op200_call_state43, ap_predicate_op201_call_state44, ap_predicate_op202_call_state45, ap_predicate_op203_call_state46, ap_predicate_op204_call_state47, ap_predicate_op205_call_state48, ap_predicate_op206_call_state49, ap_predicate_op207_call_state50, ap_predicate_op208_call_state51, ap_predicate_op209_call_state52, ap_predicate_op210_call_state53, ap_predicate_op211_call_state54, ap_predicate_op212_call_state55, ap_predicate_op213_call_state56, ap_predicate_op214_call_state57, ap_predicate_op215_call_state58, ap_predicate_op216_call_state59, ap_predicate_op217_call_state60, ap_predicate_op218_call_state61, ap_predicate_op219_call_state62, ap_predicate_op220_call_state63, ap_predicate_op221_call_state64, ap_predicate_op222_call_state65, ap_predicate_op223_call_state66, ap_predicate_op224_call_state67, ap_predicate_op225_call_state68, ap_predicate_op226_call_state69, ap_predicate_op227_call_state70, ap_predicate_op228_call_state71, ap_predicate_op229_call_state72, ap_predicate_op230_call_state73, ap_predicate_op231_call_state74, ap_predicate_op232_call_state75, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage62_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage63_flag00011001, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage7) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op169_call_state12)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_boolean_1 = ap_predicate_op170_call_state13) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op171_call_state14) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op172_call_state15) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op173_call_state16) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op174_call_state17) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_boolean_1 = ap_predicate_op175_call_state18) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op176_call_state19) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op177_call_state20) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op178_call_state21) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op179_call_state22) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op180_call_state23) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op181_call_state24) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op182_call_state25) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op183_call_state26) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op184_call_state27) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op185_call_state28) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op186_call_state29) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op187_call_state30) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op188_call_state31) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op189_call_state32) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op190_call_state33) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op191_call_state34) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op192_call_state35) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op193_call_state36) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op194_call_state37) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op195_call_state38) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op196_call_state39) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op197_call_state40) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op198_call_state41) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op199_call_state42) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op200_call_state43) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op201_call_state44) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op202_call_state45) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op203_call_state46) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op204_call_state47) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op205_call_state48) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op206_call_state49) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op207_call_state50) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op208_call_state51) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op209_call_state52) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op210_call_state53) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op211_call_state54) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op212_call_state55) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op213_call_state56) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op214_call_state57) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op215_call_state58) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op216_call_state59) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op217_call_state60) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op218_call_state61) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op219_call_state62) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op220_call_state63) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op221_call_state64) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op222_call_state65) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_const_boolean_1 = ap_predicate_op223_call_state66) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op224_call_state67)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op225_call_state68)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op226_call_state69) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op227_call_state70) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op228_call_state71) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op229_call_state72) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op230_call_state73) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op231_call_state74) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op232_call_state75)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)))) then contacts_V_ce1 <= grp_match_db_contact_fu_212_contacts_V_ce1; else contacts_V_ce1 <= ap_const_logic_0; end if; end process; contacts_V_we0_assign_proc : process(operation_read_read_fu_130_p2, ap_CS_fsm_state2, icmp_fu_243_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_0 = icmp_fu_243_p2))) then contacts_V_we0 <= ap_const_logic_1; else contacts_V_we0 <= ap_const_logic_0; end if; end process; contacts_size_out_1_ack_in_assign_proc : process(contacts_size_out_1_vld_reg) begin if (((ap_const_logic_0 = contacts_size_out_1_vld_reg) or ((ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then contacts_size_out_1_ack_in <= ap_const_logic_1; else contacts_size_out_1_ack_in <= ap_const_logic_0; end if; end process; contacts_size_out_1_data_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, contacts_size, operation_read_read_fu_130_p2, storemerge_reg_200, ap_CS_fsm_state85) begin if ((ap_const_logic_1 = ap_CS_fsm_state85)) then contacts_size_out_1_data_in <= storemerge_reg_200; elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_130_p2)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_2))))) then contacts_size_out_1_data_in <= contacts_size; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_2))) then contacts_size_out_1_data_in <= ap_const_lv32_0; else contacts_size_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; contacts_size_out_1_vld_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_130_p2, ap_CS_fsm_state85) begin if ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_130_p2)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_2))) or (ap_const_logic_1 = ap_CS_fsm_state85))) then contacts_size_out_1_vld_in <= ap_const_logic_1; else contacts_size_out_1_vld_in <= ap_const_logic_0; end if; end process; database_index_1_fu_272_p2 <= std_logic_vector(unsigned(database_index_phi_fu_193_p4) + unsigned(ap_const_lv24_1)); database_index_cast1_fu_278_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(database_index_phi_fu_193_p4),32)); database_index_phi_fu_193_p4_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365, ap_enable_reg_pp0_iter1, database_index_reg_189, ap_CS_fsm_pp0_stage0, database_index_1_reg_360, ap_block_pp0_stage0_flag00000000) begin if (((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then database_index_phi_fu_193_p4 <= database_index_1_reg_360; else database_index_phi_fu_193_p4 <= database_index_reg_189; end if; end process; db_mem_V_ARVALID_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_predicate_op161_readreq_state4, ap_reg_ioackin_db_mem_V_ARREADY, ap_block_pp0_stage1_flag00001001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op161_readreq_state4) and (ap_block_pp0_stage1_flag00001001 = ap_const_boolean_0) and (ap_const_logic_0 = ap_reg_ioackin_db_mem_V_ARREADY))) then db_mem_V_ARVALID <= ap_const_logic_1; else db_mem_V_ARVALID <= ap_const_logic_0; end if; end process; db_mem_V_RREADY_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage8, ap_predicate_op168_read_state11, ap_block_pp0_stage8_flag00011001) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_boolean_1 = ap_predicate_op168_read_state11) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then db_mem_V_RREADY <= ap_const_logic_1; else db_mem_V_RREADY <= ap_const_logic_0; end if; end process; db_mem_V_blk_n_AR_assign_proc : process(m_axi_db_mem_V_ARREADY, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_block_pp0_stage1_flag00000000, tmp_127_reg_356, tmp_8_reg_365) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1))) then db_mem_V_blk_n_AR <= m_axi_db_mem_V_ARREADY; else db_mem_V_blk_n_AR <= ap_const_logic_1; end if; end process; db_mem_V_blk_n_R_assign_proc : process(m_axi_db_mem_V_RVALID, ap_enable_reg_pp0_iter0, tmp_127_reg_356, tmp_8_reg_365, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00000000) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then db_mem_V_blk_n_R <= m_axi_db_mem_V_RVALID; else db_mem_V_blk_n_R <= ap_const_logic_1; end if; end process; error_out_1_ack_in_assign_proc : process(error_out_1_vld_reg) begin if (((ap_const_logic_0 = error_out_1_vld_reg) or ((ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then error_out_1_ack_in <= ap_const_logic_1; else error_out_1_ack_in <= ap_const_logic_0; end if; end process; error_out_1_data_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_130_p2, ap_CS_fsm_state2, icmp_fu_243_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_1 = icmp_fu_243_p2))) then error_out_1_data_in <= ap_const_lv32_1; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_130_p2)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_2)))) then error_out_1_data_in <= ap_const_lv32_3; elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (ap_const_lv32_0 = operation_read_read_fu_130_p2)))) then error_out_1_data_in <= ap_const_lv32_0; else error_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; error_out_1_vld_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_130_p2, ap_CS_fsm_state2, icmp_fu_243_p2) begin if ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (ap_const_lv32_0 = operation_read_read_fu_130_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_130_p2)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_1 = icmp_fu_243_p2)))) then error_out_1_vld_in <= ap_const_logic_1; else error_out_1_vld_in <= ap_const_logic_0; end if; end process; grp_match_db_contact_fu_212_ap_ce_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_block_pp0_stage1_flag00011001, ap_block_pp0_stage8_flag00011001, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage62_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage63_flag00011001, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage7) begin if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)))) then grp_match_db_contact_fu_212_ap_ce <= ap_const_logic_1; else grp_match_db_contact_fu_212_ap_ce <= ap_const_logic_0; end if; end process; grp_match_db_contact_fu_212_ap_start <= ap_reg_grp_match_db_contact_fu_212_ap_start; icmp_fu_243_p2 <= "1" when (signed(tmp_fu_234_p4) > signed(ap_const_lv25_0)) else "0"; operation_ap_vld_in_sig_assign_proc : process(operation_ap_vld, operation_ap_vld_preg) begin if ((ap_const_logic_1 = operation_ap_vld)) then operation_ap_vld_in_sig <= operation_ap_vld; else operation_ap_vld_in_sig <= operation_ap_vld_preg; end if; end process; operation_blk_n_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld) begin if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then operation_blk_n <= operation_ap_vld; else operation_blk_n <= ap_const_logic_1; end if; end process; operation_in_sig_assign_proc : process(operation, operation_preg, operation_ap_vld) begin if ((ap_const_logic_1 = operation_ap_vld)) then operation_in_sig <= operation; else operation_in_sig <= operation_preg; end if; end process; operation_read_read_fu_130_p2 <= operation_in_sig; results_out_AWVALID_assign_proc : process(ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_predicate_op234_writereq_state76, ap_reg_ioackin_results_out_AWREADY, ap_block_pp0_stage9_flag00001001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76) and (ap_block_pp0_stage9_flag00001001 = ap_const_boolean_0) and (ap_const_logic_0 = ap_reg_ioackin_results_out_AWREADY))) then results_out_AWVALID <= ap_const_logic_1; else results_out_AWVALID <= ap_const_logic_0; end if; end process; results_out_BREADY_assign_proc : process(ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage15, ap_predicate_op241_writeresp_state82, ap_block_pp0_stage15_flag00011001) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_boolean_1 = ap_predicate_op241_writeresp_state82) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then results_out_BREADY <= ap_const_logic_1; else results_out_BREADY <= ap_const_logic_0; end if; end process; results_out_WDATA <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_reg_390),8)); results_out_WVALID_assign_proc : process(ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage10, ap_predicate_op236_write_state77, ap_reg_ioackin_results_out_WREADY, ap_block_pp0_stage10_flag00001001) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_boolean_1 = ap_predicate_op236_write_state77) and (ap_block_pp0_stage10_flag00001001 = ap_const_boolean_0) and (ap_const_logic_0 = ap_reg_ioackin_results_out_WREADY))) then results_out_WVALID <= ap_const_logic_1; else results_out_WVALID <= ap_const_logic_0; end if; end process; results_out_blk_n_AW_assign_proc : process(m_axi_results_out_AWREADY, ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_block_pp0_stage9_flag00000000, ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365))) then results_out_blk_n_AW <= m_axi_results_out_AWREADY; else results_out_blk_n_AW <= ap_const_logic_1; end if; end process; results_out_blk_n_B_assign_proc : process(m_axi_results_out_BVALID, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00000000) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then results_out_blk_n_B <= m_axi_results_out_BVALID; else results_out_blk_n_B <= ap_const_logic_1; end if; end process; results_out_blk_n_W_assign_proc : process(m_axi_results_out_WREADY, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00000000) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then results_out_blk_n_W <= m_axi_results_out_WREADY; else results_out_blk_n_W <= ap_const_logic_1; end if; end process; sum_cast_fu_306_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(sum_reg_369),64)); sum_fu_295_p2 <= std_logic_vector(unsigned(tmp_7_cast_fu_286_p1) + unsigned(tmp_126_reg_343)); tmp_126_fu_230_p1 <= offset(25 - 1 downto 0); tmp_127_fu_264_p3 <= database_index_phi_fu_193_p4(23 downto 23); tmp_4_fu_249_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(contacts_size_load_reg_334),64)); tmp_5_fu_253_p2 <= std_logic_vector(unsigned(contacts_size_load_reg_334) + unsigned(ap_const_lv32_1)); tmp_7_cast_fu_286_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(database_index_phi_fu_193_p4),25)); tmp_7_fu_282_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(database_index_phi_fu_193_p4),64)); tmp_8_fu_290_p2 <= "1" when (unsigned(database_index_cast1_fu_278_p1) < unsigned(db_size_in)) else "0"; tmp_fu_234_p4 <= contacts_size_load_reg_334(31 downto 7); end behav;
gpl-3.0