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tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2173.vhd | 4 | 1706 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2173.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02173ent IS
END c07s02b05x00p01n01i02173ent;
ARCHITECTURE c07s02b05x00p01n01i02173arch OF c07s02b05x00p01n01i02173ent IS
BEGIN
TESTING: PROCESS
constant x1: integer := - 10;
BEGIN
assert NOT(x1=-10)
report "***PASSED TEST: c07s02b05x00p01n01i02173"
severity NOTE;
assert (x1=-10)
report "***FAILED TEST: c07s02b05x00p01n01i02173 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02173arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1237/mwe.vhdl | 1 | 456 | library ieee;
use ieee.std_logic_1164.all;
entity MWE is
end MWE;
architecture test of MWE is
constant P : integer := 1;
signal my_sig : std_logic_vector(P downto 0);
begin
block2: if P = 2 generate
my_sig(2) <= '1';
end generate;
block1: if P = 1 generate
my_sig(1) <= '1';
end generate;
-- even this block alone breaks during analysis
blockf: if false generate
my_sig(2) <= '1';
end generate;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2584.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2584.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02584ent IS
END c13s03b01x00p02n01i02584ent;
ARCHITECTURE c13s03b01x00p02n01i02584arch OF c13s03b01x00p02n01i02584ent IS
BEGIN
TESTING: PROCESS
variable k^ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02584 - Identifier can not end with '^'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02584arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue317/PoC/src/sort/sortnet/sortnet_BitonicSort.vhdl | 2 | 7916 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: Sorting network: bitonic sort
--
-- Description:
-- -------------------------------------
-- This sorting network uses the *bitonic sort* algorithm.
--
-- .. image:: /_static/sort/sortnet/sortnet_BitonicSort.*
-- :target: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.math.all;
use PoC.vectors.all;
use PoC.components.all;
entity sortnet_BitonicSort is
generic (
INPUTS : positive := 32; -- input count
KEY_BITS : positive := 32; -- the first KEY_BITS of In_Data are used as a sorting critera (key)
DATA_BITS : positive := 64; -- inclusive KEY_BITS
META_BITS : natural := 2; -- additional bits, not sorted but delayed as long as In_Data
PIPELINE_STAGE_AFTER : natural := 2; -- add a pipline stage after n sorting stages
ADD_INPUT_REGISTERS : boolean := FALSE; --
ADD_OUTPUT_REGISTERS : boolean := TRUE --
);
port (
Clock : in std_logic;
Reset : in std_logic;
Inverse : in std_logic := '0';
In_Valid : in std_logic;
In_IsKey : in std_logic;
In_Data : in T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
In_Meta : in std_logic_vector(META_BITS - 1 downto 0);
Out_Valid : out std_logic;
Out_IsKey : out std_logic;
Out_Data : out T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
Out_Meta : out std_logic_vector(META_BITS - 1 downto 0)
);
end entity;
architecture rtl of sortnet_BitonicSort is
constant C_VERBOSE : boolean := POC_VERBOSE;
constant BLOCKS : positive := log2ceil(INPUTS);
constant STAGES : positive := triangularNumber(BLOCKS);
constant COMPARATORS : positive := STAGES * (INPUTS / 2);
constant META_VALID_BIT : natural := 0;
constant META_ISKEY_BIT : natural := 1;
constant META_VECTOR_BITS : positive := META_BITS + 2;
subtype T_META is std_logic_vector(META_VECTOR_BITS - 1 downto 0);
type T_META_VECTOR is array(natural range <>) of T_META;
subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
type T_DATA_MATRIX is array(natural range <>) of T_DATA_VECTOR(INPUTS - 1 downto 0);
function to_dv(slm : T_SLM) return T_DATA_VECTOR is
variable Result : T_DATA_VECTOR(slm'range(1));
begin
for i in slm'range(1) loop
for j in slm'high(2) downto slm'low(2) loop
Result(i)(j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_slm(dv : T_DATA_VECTOR) return T_SLM is
variable Result : T_SLM(dv'range, T_DATA'range);
begin
for i in dv'range loop
for j in T_DATA'range loop
Result(i, j) := dv(i)(j);
end loop;
end loop;
return Result;
end function;
signal In_Valid_d : std_logic := '0';
signal In_IsKey_d : std_logic := '0';
signal In_Data_d : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => '0'));
signal In_Meta_d : std_logic_vector(META_BITS - 1 downto 0) := (others => '0');
signal MetaVector : T_META_VECTOR(STAGES downto 0) := (others => (others => '0'));
signal DataMatrix : T_DATA_MATRIX(STAGES downto 0) := (others => (others => (others => '0')));
signal MetaOutputs_d : T_META := (others => '0');
signal DataOutputs_d : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => '0'));
begin
assert (not C_VERBOSE)
report "sortnet_BitonicSort:" & LF &
" DATA_BITS=" & integer'image(DATA_BITS) &
" KEY_BITS=" & integer'image(KEY_BITS) &
" META_BITS=" & integer'image(META_BITS)
severity NOTE;
In_Valid_d <= In_Valid when registered(Clock, ADD_INPUT_REGISTERS);
In_IsKey_d <= In_IsKey when registered(Clock, ADD_INPUT_REGISTERS);
In_Data_d <= In_Data when registered(Clock, ADD_INPUT_REGISTERS);
In_Meta_d <= In_Meta when registered(Clock, ADD_INPUT_REGISTERS);
DataMatrix(0) <= to_dv(In_Data_d);
MetaVector(0)(META_VALID_BIT) <= In_Valid_d;
MetaVector(0)(META_ISKEY_BIT) <= In_IsKey_d;
MetaVector(0)(META_VECTOR_BITS - 1 downto META_VECTOR_BITS - META_BITS) <= In_Meta_d;
genBlocks : for b in 0 to BLOCKS - 1 generate
constant START_DISTANCE : positive := 2**b;
begin
genStage : for s in 0 to b generate
constant STAGE_INDEX : natural := triangularNumber(b) + s;
constant DISTANCE : positive := 2**(b - s);
constant GROUPS : positive := INPUTS / (DISTANCE * 2);
constant INSERT_PIPELINE_REGISTER : boolean := (PIPELINE_STAGE_AFTER /= 0) and (STAGE_INDEX mod PIPELINE_STAGE_AFTER = 0);
begin
MetaVector(STAGE_INDEX + 1) <= MetaVector(STAGE_INDEX) when registered(Clock, INSERT_PIPELINE_REGISTER);
genGroups : for g in 0 to GROUPS - 1 generate
constant INV : std_logic := to_sl((g / (2 ** s) mod 2 = 1));
begin
genLoop : for l in 0 to DISTANCE - 1 generate
constant SRC0 : natural := g * (DISTANCE * 2) + l;
constant SRC1 : natural := SRC0 + DISTANCE;
signal Greater : std_logic;
signal Switch_d : std_logic;
signal Switch_en : std_logic;
signal Switch_r : std_logic := '0';
signal Switch : std_logic;
signal NewData0 : T_DATA;
signal NewData1 : T_DATA;
begin
Greater <= to_sl(unsigned(DataMatrix(STAGE_INDEX)(SRC0)(KEY_BITS - 1 downto 0)) > unsigned(DataMatrix(STAGE_INDEX)(SRC1)(KEY_BITS - 1 downto 0)));
Switch_d <= Greater xor Inverse xor INV;
Switch_en <= MetaVector(STAGE_INDEX)(META_ISKEY_BIT) and MetaVector(STAGE_INDEX)(META_VALID_BIT);
Switch_r <= ffdre(q => Switch_r, d => Switch_d, en => Switch_en) when rising_edge(Clock);
Switch <= mux(Switch_en, Switch_r, Switch_d);
NewData0 <= mux(Switch, DataMatrix(STAGE_INDEX)(SRC0), DataMatrix(STAGE_INDEX)(SRC1));
NewData1 <= mux(Switch, DataMatrix(STAGE_INDEX)(SRC1), DataMatrix(STAGE_INDEX)(SRC0));
DataMatrix(STAGE_INDEX + 1)(SRC0) <= NewData0 when registered(Clock, INSERT_PIPELINE_REGISTER);
DataMatrix(STAGE_INDEX + 1)(SRC1) <= NewData1 when registered(Clock, INSERT_PIPELINE_REGISTER);
end generate;
end generate;
end generate;
end generate;
MetaOutputs_d <= MetaVector(STAGES) when registered(Clock, ADD_OUTPUT_REGISTERS);
DataOutputs_d <= to_slm(DataMatrix(STAGES)) when registered(Clock, ADD_OUTPUT_REGISTERS);
Out_Valid <= MetaOutputs_d(META_VALID_BIT);
Out_IsKey <= MetaOutputs_d(META_ISKEY_BIT);
Out_Data <= DataOutputs_d;
Out_Meta <= MetaOutputs_d(META_VECTOR_BITS - 1 downto META_VECTOR_BITS - META_BITS);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket89/repro2.vhdl | 3 | 354 | entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (10 ns);
end process;
process
begin
s <= 3;
wait for 0 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1049.vhd | 4 | 1839 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1049.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01049ent IS
END c06s04b00x00p03n01i01049ent;
ARCHITECTURE c06s04b00x00p03n01i01049arch OF c06s04b00x00p03n01i01049ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type ONE is range 1 to 1;
type A2 is array (ONE) of BOOLEAN;
variable V1: BOOLEAN;
BEGIN
V1 := A2'(others=>TRUE)(1);
-- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01049 - Prefix of an indexed name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01049arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc791.vhd | 4 | 2065 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc791.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b02x00p03n01i00791ent_1 IS
END ;
-- legal. with entity_simple_name
ENTITY c01s01b02x00p03n01i00791ent_2 IS
END c01s01b02x00p03n01i00791ent_2 ;
-- legal. begin with no statements following
ENTITY c01s01b02x00p03n01i00791ent_3 IS
begin
END c01s01b02x00p03n01i00791ent_3;
-- legal. no space before semicolon
ENTITY c01s01b02x00p03n01i00791ent_4 IS
END c01s01b02x00p03n01i00791ent_4;
-- legal. NEW line before semicolon
ENTITY c01s01b02x00p03n01i00791ent_5 IS
END c01s01b02x00p03n01i00791ent_5
;
--------------------------------
ENTITY c01s01b02x00p03n01i00791ent IS
END c01s01b02x00p03n01i00791ent;
ARCHITECTURE c01s01b02x00p03n01i00791arch OF c01s01b02x00p03n01i00791ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b02x00p03n01i00791"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00791arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/dispout01/tb_rec10.vhdl | 1 | 461 | entity tb_rec10 is
end tb_rec10;
library ieee;
use ieee.std_logic_1164.all;
use work.rec10_pkg.all;
architecture behav of tb_rec10 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec10
port map (inp => inp, o => r);
process
begin
inp <= '1';
wait for 1 ns;
assert r.b (1) = '0' severity failure;
inp <= '0';
wait for 1 ns;
assert r.b (1) = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2662.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2662.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02662ent IS
END c13s03b01x00p02n01i02662ent;
ARCHITECTURE c13s03b01x00p02n01i02662arch OF c13s03b01x00p02n01i02662ent IS
BEGIN
TESTING: PROCESS
variable !k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02662 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02662arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2280.vhd | 4 | 2390 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2280.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02280ent IS
END c07s02b06x00p14n01i02280ent;
ARCHITECTURE c07s02b06x00p14n01i02280arch OF c07s02b06x00p14n01i02280ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable REALV : REAL;
variable DISTV : DISTANCE;
BEGIN
REALV := REALV / DISTV; -- ERROR:
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02280 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02280arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1242/issue.vhdl | 1 | 497 | library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (bar : in std_logic_vector (3 downto 0);
foobar : out std_logic);
end issue;
architecture beh of issue is
function foo (bar: std_logic_vector) return std_logic is
variable i : integer range 0 to 2 := 0;
begin
loop
exit when bar (i) = '0';
i := i + 1;
end loop;
return bar (i);
end function foo;
begin
foobar <= foo (bar);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue140/repro.vhdl | 2 | 155 | entity tb is
end tb;
architecture behav of tb is
begin
p : process
variable v : natural;
begin
v := 5;
v: null;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2587.vhd | 4 | 1687 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2587.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02587ent IS
END c13s03b01x00p02n01i02587ent;
ARCHITECTURE c13s03b01x00p02n01i02587arch OF c13s03b01x00p02n01i02587ent IS
BEGIN
TESTING: PROCESS
variable k( : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02587 - Identifier can not end with '('."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02587arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1372.vhd | 4 | 6488 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1372.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01372ent IS
END c08s05b00x00p03n01i01372ent;
ARCHITECTURE c08s05b00x00p03n01i01372arch OF c08s05b00x00p03n01i01372ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01372"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST:c08s05b00x00p03n01i01372 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01372arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_07.vhd | 4 | 1385 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity SR_flipflop is
port ( S, R : in bit; Q : out bit );
end entity SR_flipflop;
architecture checking of SR_flipflop is
begin
set_reset : process (S, R) is
begin
assert S = '1' nand R = '1';
if S = '1' then
Q <= '1';
end if;
if R = '1' then
Q <= '0';
end if;
end process set_reset;
end architecture checking;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket14/reprook.vhdl | 3 | 564 | entity reprook is
generic (
BUS_WIDTH : integer := 8;
ARRAY_WIDTH : integer := 2);
end entity reprook;
architecture behavioural of reprook is
type test_array_btype is array (integer range <>) of
bit_vector (BUS_WIDTH-1 downto 0);
subtype test_array_type is test_array_btype (ARRAY_WIDTH-1 downto 0);
signal s : test_array_type := (others => (others => '0'));
begin
failing_process : process
begin
assert s'left = 1;
assert s'right = 0;
wait;
end process failing_process;
end architecture behavioural;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug042/centerconfig.vhdl | 2 | 1880 | library ieee;
use ieee.std_logic_1164.all;
entity CenterConfig is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
center_height: out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
center_width: out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0)
);
end entity CenterConfig;
architecture foo of centerconfig is
begin
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity instance is
generic (
CENTERHEIGHT: integer := 16;
CENTERWIDTH: integer := 16
);
end entity;
architecture fum of instance is
constant C_S_AXI_DATA_WIDTH: integer := 32;
constant C_S_AXI_ADDR_WIDTH: integer := 4;
component centerconfig is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
center_height:
out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
center_width:
out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0)
);
end component;
signal std_center_height: std_logic_vector (CENTERHEIGHT - 1 downto 0);
signal std_center_width: std_logic_vector (CENTERWIDTH - 1 downto 0);
begin
Config:
CenterConfig
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
center_height(std_center_height'range) => std_center_height,
-- center_height(C_S_AXI_DATA_WIDTH-1 downto std_center_height'length) => open,
-- not working, not elegant
center_width(std_center_width'range) => std_center_width
);
end architecture; | gpl-2.0 |
tgingold/ghdl | testsuite/synth/asgn01/tb_asgn05.vhdl | 1 | 524 | entity tb_asgn05 is
end tb_asgn05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn05 is
signal s0 : std_logic;
signal s1 : std_logic;
signal r : std_logic_vector (5 downto 0);
begin
dut: entity work.asgn05
port map (s0 => s0, s1 => s1, r => r);
process
begin
s0 <= '0';
s1 <= '0';
wait for 1 ns;
assert r = "000000" severity failure;
s0 <= '1';
s1 <= '0';
wait for 1 ns;
assert r = "010110" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/arr01/tb_arr07.vhdl | 1 | 1012 | entity tb_arr07 is
end tb_arr07;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_arr07 is
signal clk : std_logic;
signal val : std_logic_vector(7 downto 0);
signal res : std_logic_vector(7 downto 0);
signal par : std_logic;
begin
dut: entity work.arr07
port map (clk => clk, val => val, res => res, par => par);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
for i in 0 to 15 loop
val <= std_logic_vector (to_unsigned(i, 4) & to_unsigned (15 - i, 4));
pulse;
end loop;
assert res = x"0f" severity failure;
val <= x"e4";
pulse;
assert res = x"1e" severity failure;
val <= x"c5";
pulse;
assert res = x"2d" severity failure;
val <= x"f6";
pulse;
assert res = x"3c" severity failure;
val <= x"57";
pulse;
assert res = x"4b" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd | 4 | 1457 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity and2 is
port ( a, b : in std_ulogic; y : out std_ulogic );
end entity and2;
--------------------------------------------------
architecture detailed_delay of and2 is
signal result : std_ulogic;
begin
gate : process (a, b) is
begin
result <= a and b;
end process gate;
delay : process (result) is
begin
if result = '1' then
y <= reject 400 ps inertial '1' after 1.5 ns;
elsif result = '0' then
y <= reject 300 ps inertial '0' after 1.2 ns;
else
y <= reject 300 ps inertial 'X' after 500 ps;
end if;
end process delay;
end architecture detailed_delay;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc57.vhd | 4 | 1788 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc57.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p05n02i00057ent IS
END c04s03b01x01p05n02i00057ent;
ARCHITECTURE c04s03b01x01p05n02i00057arch OF c04s03b01x01p05n02i00057ent IS
BEGIN
TESTING: PROCESS
variable i : integer; -- loop index
variable x : integer;
BEGIN
i := 10;
for i in 1 to 5 loop
x := X + 1;
i := 5; -- Failure_here - the loop index is being modified.
end loop;
assert FALSE
report "***FAILED TEST:c04s03b01x01p05n02i00057 - A loop index may not be altered within the loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p05n02i00057arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/conv01/conv01.vhdl | 1 | 211 | library ieee;
use ieee.std_logic_1164.all;
entity conv01 is
port (a, b : in std_logic;
z : out std_logic);
end conv01;
architecture behav of conv01 is
begin
z <= not a and std_logic(b);
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug18280/alias_bug.vhd | 3 | 981 | --
-- <alias_bug.vhd>
--
-- Illustrates GHDL 0.29.1 WinXP problem with attributes and aliases
--
-- Problem:
-- A signal attribute, placed after an alias on the signal, causes errors like this:
--
-- .\alias_bug.vhd:35:13: alias "address_ms" does not denote the entire object
--
--
-- Workaround: move the attribute before the alias
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_bug is
end alias_bug;
architecture test of alias_bug is
signal processor_address : std_logic_vector(15 downto 0);
--
-- if alias is _NOT_ declared, error goes away
--
alias address_ms : std_logic_vector(3 downto 0) is processor_address(15 downto 12);
--
-- if the keep attribute is placed _BEFORE_ the alias, no error occurs
--
attribute keep : boolean;
attribute keep of processor_address: signal is TRUE;
begin
processor_address <= X"1234";
end test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/add_202.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_202 is
port (
output : out std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end add_202;
architecture augh of add_202 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
output <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue9/repro.vhdl | 2 | 172 | entity tmp is end entity;
architecture arch of tmp is
signal b : bit;
begin
with true select b <=
'0' when false | true,
'1' when true;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue663/repro.vhdl | 1 | 829 | library ieee;
use ieee.std_logic_1164.all;
entity repro is
end entity repro;
architecture a of repro is
signal clk : std_logic := '0';
signal check_stable_in_1 : std_logic_vector(1 to 5) := "00000";
alias check_stable_expr_1 : std_logic_vector(2 downto 0) is check_stable_in_1(3 to 5);
procedure check_stable(
signal clock : in std_logic;
signal expr : in std_logic_vector) is
begin
wait until rising_edge(clock);
end;
begin
clock : process is
begin
clk <= '1', '0' after 5 ns;
wait;
end process clock;
-- process
-- begin
-- check_stable(clk, check_stable_expr_1);
-- wait on clk, check_stable_expr_1;
-- assert check_stable_expr_1 = "000";
-- end process;
check_stable_1 : check_stable(clk, check_stable_expr_1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1357.vhd | 4 | 1670 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1357.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01357ent IS
END c08s05b00x00p03n01i01357ent;
ARCHITECTURE c08s05b00x00p03n01i01357arch OF c08s05b00x00p03n01i01357ent IS
BEGIN
TESTING: PROCESS
variable i : integer := 12;
variable r : boolean;
BEGIN
r := i;
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01357 - Target and the expression on the right-hand side should have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01357arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1211.vhd | 4 | 2059 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1211.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p25n01i01211ent IS
END c08s01b00x00p25n01i01211ent;
ARCHITECTURE c08s01b00x00p25n01i01211arch OF c08s01b00x00p25n01i01211ent IS
-- Local signals.
signal A : BIT;
BEGIN
TESTING: PROCESS
-- Local variables.
variable ShouldBeTime : TIME;
BEGIN
-- Check a condition clause that is NEVER true.
-- Should suspend until the timeout_clause is reached.
A <= '1' after 1 ns;
ShouldBeTime := NOW + 20 ns;
wait on A until (FALSE) for 20 ns;
assert NOT(ShouldBeTime = NOW)
report "***PASSED TEST: c08s01b00x00p25n01i01211"
severity NOTE;
assert (ShouldBeTime = NOW)
report "***FAILED TEST: c08s01b00x00p25n01i01211 - If the condition specified by the condition clause is FALSE, the wait statement will suspend itself again."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p25n01i01211arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/mul_376.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_376 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_376;
architecture augh of mul_376 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue530/repro2.vhdl | 1 | 1083 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity submodule is
port (
clk : in std_logic;
arg : in std_logic_vector(15 downto 0);
res : out std_logic_vector(15 downto 0)
);
end submodule;
architecture behav of submodule is
begin
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sliced_ex is
port (
clk : in std_logic;
arg_a : in signed(7 downto 0);
arg_b : in signed(7 downto 0);
res_a : out signed(7 downto 0);
res_b : out signed(7 downto 0)
);
end sliced_ex;
architecture rtl of sliced_ex is
signal tmp : signed(15 downto 0);
begin
SUB_MODULE : entity work.submodule
port map (
clk => clk,
arg( 7 downto 0) => std_logic_vector(arg_a),
arg(15 downto 8) => std_logic_vector(arg_b),
-- The casting of a sliced output causes an exception.
-- Casting of the entire output bus does work
-- signed(res) => tmp -- (this would work)
signed(res( 7 downto 0)) => res_a,
signed(res(15 downto 8)) => res_b
);
end rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1000.vhd | 4 | 1825 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1000.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01000pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01000pkg;
use work.c06s03b00x00p09n01i01000pkg.all;
ENTITY c06s03b00x00p09n01i01000ent IS
END c06s03b00x00p09n01i01000ent;
ARCHITECTURE c06s03b00x00p09n01i01000arch OF c06s03b00x00p09n01i01000ent IS
BEGIN
TESTING: PROCESS
subtype ST4 is c06s03b00x00p09n01i01000ent.c06s03b00x00p09n01i01000pkg.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01000 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01000arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/sub_596.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_596 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_596;
architecture augh of sub_596 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1375.vhd | 4 | 3691 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1375.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s05b00x00p03n01i01375pkg is
-- Type declarations.
subtype BV2 is BIT_VECTOR( 0 to 1 );
subtype CH2 is STRING( 1 to 2 );
-- Constant declarations.
constant BVC : BV2 := B"00";
constant CHC : CH2 := "bb";
-- Function returns BV2.
function returnBV2 return BV2;
-- Function returns CH2.
function returnCH2 return CH2;
end c08s05b00x00p03n01i01375pkg;
package body c08s05b00x00p03n01i01375pkg is
-- Function returns BV2.
function returnBV2 return BV2 is
begin
return ( BVC );
end returnBV2;
-- Function returns CH2.
function returnCH2 return CH2 is
begin
return( CHC );
end returnCH2;
end c08s05b00x00p03n01i01375pkg;
use work.c08s05b00x00p03n01i01375pkg.all;
ENTITY c08s05b00x00p03n01i01375ent IS
END c08s05b00x00p03n01i01375ent;
ARCHITECTURE c08s05b00x00p03n01i01375arch OF c08s05b00x00p03n01i01375ent IS
BEGIN
TESTING: PROCESS
-- local variables
variable BITV : BV2 := B"11";
variable STRV : CH2 := "ab";
variable S, T : BIT;
variable S1, T1 : BIT;
variable S11, T11 : BIT;
variable C1, C2 : CHARACTER;
variable C11, C22 : CHARACTER;
variable C111, C222 : CHARACTER;
BEGIN
-- Assign with a variable as the expression.
( S, T ) := BITV;
( C1,C2 ) := STRV;
-- Assign with a function return value.
( S1, T1 ) := returnBV2;
( C11,C22 ) := returnCH2;
-- Assign with a qualified expression.
( S11, T11 ) := BV2'( '0', '1' );
( C111,C222 ) := CH2'( 'c', 'c' );
assert NOT(((S = BITV( 0 )) and (T = BITV( 1 )))
and ((C1 = STRV( 1 )) and (C2 = STRV( 2 )))
and ((S1 = BVC( 0 )) and (T1 = BVC( 1 )))
and ((C11 = CHC( 1 )) and (C22 = CHC( 2 )))
and ((S11 = '0') and (T11 = '1'))
and ((C111 = 'c') and (C222 = 'c')))
report "***PASSED TEST: c08s05b00x00p03n01i01375"
severity NOTE;
assert (((S = BITV( 0 )) and (T = BITV( 1 )))
and ((C1 = STRV( 1 )) and (C2 = STRV( 2 )))
and ((S1 = BVC( 0 )) and (T1 = BVC( 1 )))
and ((C11 = CHC( 1 )) and (C22 = CHC( 2 )))
and ((S11 = '0') and (T11 = '1'))
and ((C111 = 'c') and (C222 = 'c')))
report "***FAILED TEST: c08s05b00x00p03n01i01375 - Legal aggregate variable assignment fail."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01375arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1528.vhd | 4 | 1606 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1528.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p08n01i01528ent IS
END c08s09b00x00p08n01i01528ent;
ARCHITECTURE c08s09b00x00p08n01i01528arch OF c08s09b00x00p08n01i01528ent IS
BEGIN
TESTING: PROCESS
BEGIN
while '1' and '0' loop
end loop;
assert FALSE
report "***FAILED TEST: c08s09b00x00p08n01i01528 - while condition is not boolean expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p08n01i01528arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_25.vhd | 4 | 2096 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity nand3 is
generic ( Tpd : delay_length );
port ( a, b, c : in bit; y : out bit );
end entity nand3;
architecture basic of nand3 is
begin
y <= not (a and b and c) after Tpd;
end architecture basic;
library project_lib;
library stimulus;
use stimulus.stimulus_generators.all;
entity misc_logic is
end entity misc_logic;
-- code from book
architecture gate_level of misc_logic is
component nand3 is
generic ( Tpd : delay_length );
port ( a, b, c : in bit; y : out bit );
end component nand3;
for all : nand3
use entity project_lib.nand3(basic);
-- . . .
-- not in book
signal sig1, sig2, sig3, out_sig : bit;
signal test_vector : bit_vector(1 to 3);
-- end not in book
begin
gate1 : component nand3
generic map ( Tpd => 2 ns )
port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
-- . . .
-- not in book
all_possible_values(test_vector, 10 ns);
(sig1, sig2, sig3) <= test_vector;
-- end not in book
end architecture gate_level;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1137/testbench.vhdl | 1 | 2064 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity testbench is
end entity;
architecture simu of testbench is
-- Dummy control
signal clk : std_logic := '0';
signal simu_clock_enable : std_logic := '1';
-- Dummy source signal
signal data_src : std_logic_vector(1 downto 0) := "00";
-- Three destination signals
signal data_dst1 : std_logic_vector(1 downto 0) := "11";
signal data_dst2 : std_logic_vector(1 downto 0) := "11";
signal data_dst3 : std_logic_vector(1 downto 0) := "11";
signal data_dst4 : std_logic_vector(1 downto 0) := "11";
begin
-- Solution 1
-- THIS WORKS
process(all)
variable idx : integer;
begin
for c in 0 to 1 loop
idx := c;
data_dst1(idx) <= data_src(idx);
end loop;
end process;
-- Solution 2
-- FIXME THIS DOES NOT WORK, CREATES XXX
gen2 : for c in 0 to 1 generate
process(all)
variable idx : integer;
begin
idx := c;
data_dst2(idx) <= data_src(idx);
end process;
end generate;
-- Solution 4
-- THIS WORKS
gen4 : for c in 0 to 1 generate
process(all)
constant idx : integer := c;
begin
data_dst4(idx) <= data_src(idx);
end process;
end generate;
-- Solution 3
-- THIS WORKS
gen3 : for c in 0 to 1 generate
constant idx : integer := c;
begin
data_dst3(idx) <= data_src(idx);
end generate;
-- Dummy clock generation
clk <= (not clk) and simu_clock_enable after 5 ns;
-- Main testbench process
process
-- To print simulation messages
variable l : line;
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
write(l, string'("Result 1 : "));
write(l, to_string(data_dst1));
writeline(output, l);
write(l, string'("Result 2 : "));
write(l, to_string(data_dst2));
writeline(output, l);
write(l, string'("Result 3 : "));
write(l, to_string(data_dst3));
writeline(output, l);
write(l, string'("Result 4 : "));
write(l, to_string(data_dst4));
writeline(output, l);
simu_clock_enable <= '0';
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1219.vhd | 4 | 1799 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1219.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p26n03i01219ent IS
END c08s01b00x00p26n03i01219ent;
ARCHITECTURE c08s01b00x00p26n03i01219arch OF c08s01b00x00p26n03i01219ent IS
BEGIN
TESTING: PROCESS
BEGIN
--
-- The following wait statement is illegal; time
-- expressions may not be negative. This test is
-- based on 32 bit time values.
--
wait for x"FFFFFFFE"; -- illegal time expression (-1 ?)
assert FALSE
report "***FAILED TEST: c08s01b00x00p26n03i01219 - Negative time expression accepted in a wait statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p26n03i01219arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2438.vhd | 4 | 2371 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2438.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n02i02438ent IS
END c07s03b02x02p01n02i02438ent;
ARCHITECTURE c07s03b02x02p01n02i02438arch OF c07s03b02x02p01n02i02438ent IS
BEGIN
TESTING: PROCESS
type ENUM is ( ONE, TWO, THREE, FOUR, FIVE );
type A_ARRAY is array ( boolean range <>,integer range <>) of integer;
type B_ARRAY is array ( ENUM range <>, ENUM range <> ) of real;
subtype A_CON is A_ARRAY (FALSE to TRUE, 1 to 2);
function F return A_CON is
begin
return ( FALSE =>
( 1 =>
B_ARRAY'( ONE =>
( FIVE => 2.0),
TWO =>
(FIVE => 3.0)
),
2 =>
B_ARRAY'( ONE =>
( FIVE => 2.0),
TWO =>
(FIVE => 3.0)
)
)
);
end;
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n02i02438 - Each element association must be a n-1 dimensional array aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n02i02438arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc210.vhd | 4 | 1645 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc210.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p09n01i00210ent IS
END c03s01b00x00p09n01i00210ent;
ARCHITECTURE c03s01b00x00p09n01i00210arch OF c03s01b00x00p09n01i00210ent IS
type hex is range 0 to 15;
subtype byte is hex range 0.0 to 7;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b00x00p09n01i00210 - The type of expression is not the same as the base type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p09n01i00210arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc244.vhd | 4 | 1746 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc244.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00244ent IS
END c03s01b02x00p04n01i00244ent;
ARCHITECTURE c03s01b02x00p04n01i00244arch OF c03s01b02x00p04n01i00244ent IS
type CLSI is (Jasmine, Jim, Milan, Paul, Saurin);
constant x: CLSI := Jim;
constant y: CLSI := Paul;
type People is range CLSI'(Milan) to CLSI'(Saurin);
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00244 - Type mis-match in integer range constraint for type 'People'."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00244_arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug19195/pkg.vhd | 3 | 258 | library IEEE;
use IEEE.std_logic_1164.all;
package test_pkg is
type a is record
b : std_logic_vector(3 downto 0);
end record a;
type b is record
a1 : a;
end record b;
signal c : b;
alias c0 : a is c.a1;
end package test_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2801.vhd | 4 | 1822 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2801.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity GENERATE is
end GENERATE;
ENTITY c13s09b00x00p99n01i02801ent IS
END c13s09b00x00p99n01i02801ent;
ARCHITECTURE c13s09b00x00p99n01i02801arch OF c13s09b00x00p99n01i02801ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02801 - Reserved word GENERATE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02801arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/cmp_979.vhd | 2 | 383 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_979 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_979;
architecture augh of cmp_979 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket65/bug1.vhdl | 3 | 476 | entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Error
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue301/packages/pkg_types.vhd | 7 | 1331 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Global types for the Viterbi decoder
--! @author Markus Fehrenz
--! @date 2011/07/04
--!
--! @details Most types are shared and used in different context.
--! Changing single types should be done with adding an additional type.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
package pkg_types is
-- Parity structure: p1_bit, p2_bit, ..., pN_bit
type t_input_block is array (NUMBER_PARITY_BITS - 1 downto 0) of signed(BW_LLR_INPUT - 1 downto 0);
-- Types are used for bulk information to ACS and branch unit.
type t_node_s is array (NUMBER_TRELLIS_STATES - 1 downto 0) of signed(BW_MAX_PROBABILITY - 1 downto 0);
type t_node is array (NUMBER_TRELLIS_STATES - 1 downto 0) of std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
type t_branch is array (NUMBER_BRANCH_UNITS - 1 downto 0) of std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
-- RAM Data
type t_ram_rd_data is array (1 downto 0) of std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
end package pkg_types;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1385.vhd | 4 | 1735 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1385.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01385ent IS
END c08s05b00x00p03n01i01385ent;
ARCHITECTURE c08s05b00x00p03n01i01385arch OF c08s05b00x00p03n01i01385ent IS
BEGIN
TESTING: PROCESS
subtype small_int is range 0 to 7;
variable v1 : small_int := 0;
BEGIN
small_int := v1; -- illegal type name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01385 - Target of a variable assignment can not be the name of a subtype name."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01385arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1121.vhd | 4 | 2201 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1121.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n02i01121ent IS
END c06s05b00x00p03n02i01121ent;
ARCHITECTURE c06s05b00x00p03n02i01121arch OF c06s05b00x00p03n02i01121ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5, M6);
type A1 is array (ENUM1 range <>) of BOOLEAN;
subtype A11 is A1 (M1 to M3);
subtype A12 is A1 (M4 to M6);
variable V1 : A1 (M1 to M6) ;
variable V11 : A11;
variable V12 : A12;
variable k : integer;
BEGIN
if (
(V11 = V12)
and (V11(M2 to M3) = V12(M4 to M5))
and (V1 (M1 to M3) = V11(M1 to M3))
and (V1 (M2 to M3) = V12(M4 to M5))
) then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s05b00x00p03n02i01121"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s05b00x00p03n02i01121 - The type of the slice is the same as the base type of the one-dimensional array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n02i01121arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue473/repro2.vhdl | 1 | 429 | entity repro is
end entity repro;
architecture TB of repro is
begin
DM: process
type t_ram is array(natural range <>) of bit_vector;
type p_ram is access t_ram;
variable myram : p_ram;
begin
myram := new t_ram(0 to 31)(15 downto 0);
for i in myram'range loop
myram(i) := (others => '0');
end loop;
wait;
end process DM;
end architecture TB;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket32/simulation.vhdl | 3 | 3437 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
package simulation is
--+ Test Bench Status Management ++++++++++++++++++++++++++++++++++++++++++
--* The testbench is marked as failed. If a message is provided, it is
--* reported as an error.
procedure tbFail(msg : in string := "");
--* If the passed condition has evaluated false, the testbench is marked
--* as failed. In this case, the optional message will be reported as an
--* an error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
--* Prints out the overall testbench result as defined by the automated
--* testbench process. Unless tbFail() or tbAssert() with a false condition
--* have been called before, a successful completion will be reported, a
--* failure otherwise.
procedure tbPrintResult;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end;
use std.TextIO.all;
package body simulation is
--+ Test Bench Status Management ++++++++++++++++++++++++++++++++++++++++++
--* Internal state variable to log a failure condition for final reporting.
--* Once de-asserted, this variable will never return to a value of true.
shared variable pass : boolean := true;
procedure tbFail(msg : in string := "") is
begin
if msg'length > 0 then
report msg severity error;
end if;
pass := false;
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
tbFail(msg);
end if;
end;
procedure tbPrintResult is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end procedure;
-- checksum functions
-- ===========================================================================
end package body;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc27.vhd | 4 | 2391 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc27.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p10n04i00027ent IS
END c04s02b00x00p10n04i00027ent;
ARCHITECTURE c04s02b00x00p10n04i00027arch OF c04s02b00x00p10n04i00027ent IS
subtype s1 is integer range 1 to 10; -- No_failure_here
subtype s2 is integer range 10 downto 1; -- No_failure_here
-- the following are null ranges
subtype s3 is integer range 1 downto 10; -- No_failure_here
subtype s4 is integer range 10 to 1; -- No_failure_here
BEGIN
TESTING: PROCESS
variable k1 : s1 := 1;
variable k2 : s2 := 10;
variable k : integer := 0;
BEGIN
for i in s1 loop
if (i /= k1) then
k := 1;
end if;
if (k1 < 10) then
k1 := k1 + 1;
end if;
end loop;
for i in s2 loop
if (i /= k2) then
k := 1;
end if;
if (k2 > 1) then
k2 := k2 - 1;
end if;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c04s02b00x00p10n04i00027"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c04s02b00x00p10n04i00027 - The direction of a discrete subtype is the same as the direction of its subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p10n04i00027arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd | 4 | 1437 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.resolve.all;
-- code from book (in text)
entity tri_state_reg is
port ( d : in resolved_byte;
q : out resolved_byte bus;
clock, out_enable : in bit );
end entity tri_state_reg;
-- end code from book
-- code from book
architecture behavioral of tri_state_reg is
begin
reg_behavior : process (d, clock, out_enable) is
variable stored_byte : byte;
begin
if clock'event and clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
end process reg_behavior;
end architecture behavioral;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3015.vhd | 4 | 1663 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3015.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c11s02b00x00p05n02i03015ent IS
library work; -- ERROR:
-- failure_here.
END c11s02b00x00p05n02i03015ent;
ARCHITECTURE c11s02b00x00p05n02i03015arch OF c11s02b00x00p05n02i03015ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c11s02b00x00p05n02i03015 - Library clause should appear as part of a context clause at the beginning of a design unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s02b00x00p05n02i03015arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc731.vhd | 4 | 1575 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc731.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p04n01i00731ent IS
-- A basic entity with a port
port ( signal s : bit);
END c01s01b01x00p04n01i00731ent;
ARCHITECTURE c01s01b01x00p04n01i00731arch OF c01s01b01x00p04n01i00731ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x00p04n01i00731"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x00p04n01i00731arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/synth60/leds.vhdl | 1 | 196 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity leds is
port (clk : in std_logic;
led1, led2, led3, led4, led5, led6, led7, led8 : out std_logic);
end leds;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1730.vhd | 4 | 1741 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1730.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s03b00x00p02n01i01730ent IS
port (signal AA,BB: in bit);
END c09s03b00x00p02n01i01730ent;
ARCHITECTURE c09s03b00x00p02n01i01730arch OF c09s03b00x00p02n01i01730ent IS
procedure P1 (signal A,B: in bit; signal C: out bit) is
begin
C <= A and B;
end;
signal CC : bit;
BEGIN
PROC P1 (AA,BB,CC); -- Failure_here
-- Colon is misssing
assert FALSE
report "***FAILED TEST: c09s03b00x00p02n01i01730 - Colon between the label and a procedure call statement is missing."
severity ERROR;
END c09s03b00x00p02n01i01730arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1901.vhd | 4 | 3494 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1901.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01901pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01901pkg;
use work.c07s01b00x00p08n01i01901pkg.all;
ENTITY c07s01b00x00p08n01i01901ent_a IS
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
END c07s01b00x00p08n01i01901ent_a;
ARCHITECTURE c07s01b00x00p08n01i01901arch_a OF c07s01b00x00p08n01i01901ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01901arch_a;
use work.c07s01b00x00p08n01i01901pkg.all;
ENTITY c07s01b00x00p08n01i01901ent IS
END c07s01b00x00p08n01i01901ent;
ARCHITECTURE c07s01b00x00p08n01i01901arch OF c07s01b00x00p08n01i01901ent IS
constant bus_width : natural := 7;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width));
signal out_bus : out cmd_bus (0 to small_int(bus_width)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01901ent_a(c07s01b00x00p08n01i01901arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
c : test port map ( ibus, c07s01b00x00p08n01i01901arch ); -- body name illegal here
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "body name accepted as primary in a component instantiation port map expression."
severity note ;
exit l;
end loop l;
end process p;
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01901 - Architecture body name are not permitted as primaries in a component instantiation port map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01901arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1064/test.vhdl | 1 | 420 | library ieee;
use ieee.std_logic_1164.all;
entity test is
port (i : std_ulogic;
o : out std_ulogic);
end entity test;
architecture behaviour of test is
procedure zot(e: inout std_ulogic) is
begin
e := '0';
end;
begin
execute1_1: process(all)
variable blah: std_ulogic;
begin
blah := i;
zot(blah);
o <= blah;
end process;
end architecture behaviour;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1573.vhd | 4 | 1820 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1573.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p04n01i01573ent IS
END c08s10b00x00p04n01i01573ent;
ARCHITECTURE c08s10b00x00p04n01i01573arch OF c08s10b00x00p04n01i01573ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for i in 1 to 10 loop
next when i > 5;
k := k + 1;
end loop;
assert NOT( k=5 )
report "***PASSED TEST: c08s10b00x00p04n01i01573"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s10b00x00p04n01i01573 - The current iteration of the loop is terminated if the value of the condition is TRUE"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p04n01i01573arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/lit01/tb_aggr02.vhdl | 1 | 519 | entity tb_aggr02 is
end tb_aggr02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_aggr02 is
signal i0 : natural range 0 to 5;
signal o : std_logic_vector(7 downto 0);
begin
dut: entity work.aggr02
port map (i0, o);
process
begin
i0 <= 0;
wait for 1 ns;
assert o = x"00" severity failure;
i0 <= 1;
wait for 1 ns;
assert o = x"81" severity failure;
i0 <= 2;
wait for 1 ns;
assert o = x"02" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1157.vhd | 4 | 1927 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1157.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p02n01i01157ent IS
END c06s06b00x00p02n01i01157ent;
ARCHITECTURE c06s06b00x00p02n01i01157arch OF c06s06b00x00p02n01i01157ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 5) of BOOLEAN;
type R1 is record
RE1: REAL;
RE2: A1;
end record;
variable V: R1;
variable k : integer := 0;
BEGIN
if V.RE2'LOW = 1 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01157"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01157 - The prefix of an attribute name may be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01157arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/switch_dig_2in.vhd | 4 | 2582 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity switch_dig_2in is
port ( sw_state : in std_ulogic; -- Digital control input
terminal p_in1, p_in2, p_out : electrical ); -- Analog output
end entity switch_dig_2in;
----------------------------------------------------------------
architecture ideal of switch_dig_2in is
constant r_open : resistance := 1.0e6; -- Open switch resistance
constant r_closed : resistance := 0.001; -- Closed switch resistance
constant trans_time : real := 0.00001; -- Transition time to each position
signal r_sig1 : resistance := r_closed; -- Closed switch resistance variable
signal r_sig2 : resistance := r_open; -- Open switch resistance variable
quantity v1 across i1 through p_in1 to p_out; -- V & I for in1 to out
quantity v2 across i2 through p_in2 to p_out; -- V & I for in2 to out
quantity r1 : resistance; -- Time-varying resistance for in1 to out
quantity r2 : resistance; -- Time-varying resistance for in2 to out
begin
process (sw_state) is -- Sensitivity to digital control input
begin
if sw_state = '0' or sw_state = 'L' then -- Close sig1, open sig2
r_sig1 <= r_closed;
r_sig2 <= r_open;
elsif sw_state = '1' or sw_state = 'H' then -- Open sig1, close sig2
r_sig1 <= r_open;
r_sig2 <= r_closed;
end if;
end process;
r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
v1 == r1 * i1; -- Apply Ohm's law to in1
v2 == r2 * i2; -- Apply Ohm's law to in2
end architecture ideal;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug086/sig.vhdl | 1 | 431 | entity sig is
end;
architecture behav of sig is
signal s : natural;
signal last : time;
begin
s <= 1 after 20 ns;
b: block
port (q : boolean);
port map (q => s'quiet(10 ns));
begin
process (q)
begin
report "q is " & boolean'image (q);
last <= now;
end process;
end block;
process
begin
wait for 100 ns;
assert last = 30 ns severity failure;
wait;
end process;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue254/repro1.vhdl | 2 | 391 | entity repro1 is
end entity;
architecture a of repro1 is
begin
process
type LongInteger is range -2**47 to 2**47-1;
variable v : LongInteger;
variable s : string (1 to 4);
begin
v := 12345678901;
report "v = " & LongInteger'image(v) severity note;
s := "1245";
assert LongInteger'Value (s) = 1245 severity failure;
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd | 4 | 1267 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity edge_triggered_Dff is
port ( D : in bit; clk : in bit; clr : in bit;
Q : out bit );
end entity edge_triggered_Dff;
--------------------------------------------------
architecture behavioral of edge_triggered_Dff is
begin
state_change : process (clk, clr) is
begin
if clr = '1' then
Q <= '0' after 2 ns;
elsif clk'event and clk = '1' then
Q <= D after 2 ns;
end if;
end process state_change;
end architecture behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1003.vhd | 4 | 1771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1003.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01003pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01003pkg;
use work.c06s03b00x00p09n01i01003pkg.all;
ENTITY c06s03b00x00p09n01i01003ent IS
END c06s03b00x00p09n01i01003ent;
ARCHITECTURE c06s03b00x00p09n01i01003arch OF c06s03b00x00p09n01i01003ent IS
BEGIN
TESTING: PROCESS
subtype ST8 is E.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01003 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01003arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2589.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2589.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02589ent IS
END c13s03b01x00p02n01i02589ent;
ARCHITECTURE c13s03b01x00p02n01i02589arch OF c13s03b01x00p02n01i02589ent IS
BEGIN
TESTING: PROCESS
variable k+ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02589 - Identifier can not end with '+'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02589arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue864/mwe2.vhdl | 1 | 607 | library ieee;
use ieee.std_logic_1164.all;
entity a is
port (
a_in : IN std_logic;
a_out : OUT std_logic
);
end entity a;
library ieee;
use ieee.std_logic_1164.all;
entity b is
port (
b_in : IN std_logic;
b_out : OUT std_logic
);
end entity b;
architecture rtl of a is
begin
process (a_in)
begin
a_out <= a_in;
end process;
end architecture rtl;
architecture rtl of b is
component a
port (
a_in : IN std_logic;
a_out : OUT std_logic
);
end component;
for a0 : a;
begin
a0: a port map (a_in => b_in, a_out => b_out);
end architecture rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc193.vhd | 4 | 1721 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc193.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s05b00x00p02n01i00193ent IS
END c04s05b00x00p02n01i00193ent;
ARCHITECTURE c04s05b00x00p02n01i00193arch OF c04s05b00x00p02n01i00193ent IS
component C1
generic (T1 : TIME; T2 : Integer) ;
port (P1 : in BIT;
P2 : out BIT ;
P3 : linkage BIT) ;
end component -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s05b00x00p02n01i00193 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s05b00x00p02n01i00193arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_170.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_170 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_170;
architecture augh of add_170 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2987.vhd | 4 | 1964 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2987.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p06n01i02987pkg is
constant wtime: time := 5 ns;
end c02s05b00x00p06n01i02987pkg;
ENTITY c02s05b00x00p06n01i02987ent IS
END c02s05b00x00p06n01i02987ent;
ARCHITECTURE c02s05b00x00p06n01i02987arch OF c02s05b00x00p06n01i02987ent IS
use work.c02s05b00x00p06n01i02987pkg.wtime;
BEGIN
TESTING: PROCESS
variable TimeCount : time := 0 ns;
BEGIN
TimeCount := NOW;
wait for wtime;
TimeCount := NOW - TimeCount;
assert NOT( TimeCount = 5 ns )
report "***PASSED TEST: c02s05b00x00p06n01i02987"
severity NOTE;
assert ( TimeCount = 5 ns )
report "***FAILED TEST: c02s05b00x00p06n01i02987 - Package declaration visibility test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p06n01i02987arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/dff01/dff04.vhdl | 1 | 448 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dff04 is
port (r : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic);
end dff04;
architecture behav of dff04 is
signal q : std_logic_vector(7 downto 0);
begin
process (clk, q) is
begin
if rising_edge (clk) then
q <= d;
end if;
r <= std_logic_vector(unsigned(q) + 1);
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1386.vhd | 4 | 2758 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1386.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n02i01386ent IS
END c08s05b00x00p03n02i01386ent;
ARCHITECTURE c08s05b00x00p03n02i01386arch OF c08s05b00x00p03n02i01386ent IS
BEGIN
TESTING : PROCESS
variable radix : natural := 10;
variable v1 : natural;
type r_array_index_type is range 1 to 3;
type r_array_type is array (r_array_index_type) of natural;
variable r_array : r_array_type;
procedure set_radix ( constant radix : natural
) is
begin
TESTING.radix := radix; -- test selected name as target
end set_radix;
BEGIN
v1 := 8; --test simple name as target
assert v1 = 8
report "Simple name as target failed."
severity note ;
set_radix (v1);
assert radix = v1
report "Selected name as target failed."
severity note ;
r_array ( 3 to 3 ) := (3 => 10); -- test slice name as target
assert r_array ( 3 ) = 10
report "Slice name as target failed."
severity note ;
r_array ( 2 ) := 8; -- test indexed name as target
assert r_array ( 2 ) = 8
report "Indexed name as target failed."
severity note ;
assert NOT(v1=8 and r_array(3)=10 and r_array(2)=8)
report "***PASSED TEST: c08s05b00x00p03n02i01386"
severity NOTE;
assert (v1=8 and r_array(3)=10 and r_array(2)=8)
report "***FAILED TEST: c08s05b00x00p03n02i01386 - The name of thetarget of the variable assignment statement must denote a variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n02i01386arch;
| gpl-2.0 |
tgingold/ghdl | libraries/ieee2008/math_real.vhdl | 3 | 21134 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_REAL package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common REAL
-- : constants and common REAL elementary mathematical
-- : functions.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice : STRING
:= "Copyright IEEE P1076 WG. Licensed Apache 2.0";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E : REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2 : REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2 : REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI : REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD : REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG : REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X : in REAL) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X : in REAL; BASE : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS (X : in REAL) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end package MATH_REAL;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue381/test.vhdl | 1 | 306 | library ieee;
use ieee.std_logic_1164.all;
entity can_rx is
port (
demo : in std_logic;
status : out std_logic_vector (31 downto 0)
);
end can_rx;
architecture rtl of can_rx is
begin
status(0) <= (0=>'0', others => '0') when demo = '1' else (0=>'1', others => '0');
end rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue238/proc1.vhdl | 2 | 423 | entity proc1 is
end;
use work.pkg.all;
architecture behav of proc1 is
procedure proc (v : inout rec) is
begin
v.a := 5;
assert v.a = 5 severity failure;
v.s := "Good";
assert v.a = 5 severity failure;
assert v.s = "Good" severity failure;
assert false report "ok" severity note;
end proc;
begin
process
variable v : rec_4;
begin
proc (v);
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/sub_159.vhd | 2 | 1740 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_159 is
port (
gt : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end sub_159;
architecture augh of sub_159 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
gt <= not(tmp_le);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc215.vhd | 4 | 1613 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc215.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p03n01i00215ent IS
END c03s01b01x00p03n01i00215ent;
ARCHITECTURE c03s01b01x00p03n01i00215arch OF c03s01b01x00p03n01i00215ent IS
type ENUM3 is (TUV, "XYZ");
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b01x00p03n01i00215 - Enumeration literal cannot be a string or integer lliteral."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p03n01i00215arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc331.vhd | 4 | 1764 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc331.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p05n01i00331ent IS
END c03s02b01x00p05n01i00331ent;
ARCHITECTURE c03s02b01x00p05n01i00331arch OF c03s02b01x00p05n01i00331ent IS
type bit_vctor is array (natural range <>) of bit;
type str_vctor is array (natural range <>) of character;
type matrix is array (integer range ) of real; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p05n01i00331 - The box (<>) in the unconstrained array definition is missing."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p05n01i00331arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2637.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2637.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02637ent IS
END c13s03b01x00p02n01i02637ent;
ARCHITECTURE c13s03b01x00p02n01i02637arch OF c13s03b01x00p02n01i02637ent IS
BEGIN
TESTING: PROCESS
variable k?k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02637 - Identifier can not contain '?'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02637arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue333/time_test.vhdl | 1 | 1136 | entity Time_test is
end Time_test;
architecture Behavioral of Time_test is
constant c_CLOCK_FREQUENCY : natural := 32000000;
constant c_SWITCH_ON_TIME_ms : time := 200 ms;
constant c_SWITCH_COUNT_CYCLES : integer := integer(real(c_CLOCK_FREQUENCY *
(c_SWITCH_ON_TIME_ms / 1 ms)) / 1000.0);
begin
process is
begin
report " Switch ON time " & time'image(c_SWITCH_ON_TIME_ms) severity NOTE;
report " Switch count " & natural'image(c_SWITCH_COUNT_CYCLES) severity NOTE;
-- sanity checks on time constraints
report "Clock frequency = " & natural'image(c_CLOCK_FREQUENCY) & " Hz" severity NOTE;
report "Clock period = " & time'image( 1 sec / c_CLOCK_FREQUENCY) severity NOTE;
report "Switch period = " & time'image ( 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES) severity NOTE;
Assert c_SWITCH_ON_TIME_ms = 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES
report "Wrong Switch ON time = " & time'image ( 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES) severity ERROR;
wait;
end process;
end Behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1227.vhd | 4 | 2516 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1227.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p29n01i01227ent IS
END c08s01b00x00p29n01i01227ent;
ARCHITECTURE c08s01b00x00p29n01i01227arch OF c08s01b00x00p29n01i01227ent IS
procedure call_wait (constant dly : in time) is
--
-- This procedure simply waits for the time
-- specified in its argument.
--
begin
wait for dly;
end call_wait;
procedure indirect_wait (constant dly : in time) is
--
-- This procedure calls a procedure to wait for the
-- time specified in its argument.
--
begin
call_wait (dly);
end indirect_wait;
function call_waiter (constant dly : in time) return time is
--
-- This function indirectly calls a procedure to wait
-- for the time specified in its argument, then
-- returns an incremented delay.
--
-- This is an illegal operation for a function and
-- will probably be caught at runtime.
--
begin
indirect_wait(dly);
return dly * 2;
end call_waiter;
BEGIN
TESTING: PROCESS
variable delay : time := 2 ns;
BEGIN
delay := call_waiter(delay); -- use wait indirectly
assert FALSE
report "***FAILED TEST: c08s01b00x00p29n01i01227 - Wait statement appears in a procedure that has a parent that is a function subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p29n01i01227arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc537.vhd | 4 | 1935 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc537.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p05n02i00537ent IS
END c03s03b00x00p05n02i00537ent;
ARCHITECTURE c03s03b00x00p05n02i00537arch OF c03s03b00x00p05n02i00537ent IS
type ARR is access BIT_VECTOR ;
BEGIN
TESTING: PROCESS
variable V1 : ARR := null ;
variable V2 : ARR(0 to 3) := new BIT_VECTOR'("1111") ; -- no_failure_here
BEGIN
V1 := V2;
assert NOT(V1(0 to 3)="1111")
report "***PASSED TEST: c03s03b00x00p05n02i00537"
severity NOTE;
assert (V1(0 to 3)="1111")
report "***FAILED TEST: c03s03b00x00p05n02i00537 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p05n02i00537arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc419.vhd | 4 | 3125 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc419.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00419ent IS
END c03s02b01x01p19n01i00419ent;
ARCHITECTURE c03s02b01x01p19n01i00419arch OF c03s02b01x01p19n01i00419ent IS
type time_cons_vector is array (15 downto 0) of time;
constant C1 : time_cons_vector := (others => 3 ns);
function complex_scalar(s : time_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return time_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : time_cons_vector;
signal S2 : time_cons_vector;
signal S3 : time_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00419"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00419 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00419arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1790.vhd | 4 | 1792 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1790.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s07b00x00p02n01i01790ent IS
END c09s07b00x00p02n01i01790ent;
ARCHITECTURE c09s07b00x00p02n01i01790arch OF c09s07b00x00p02n01i01790ent IS
signal TS,SS: bit_vector(1 to 3);
BEGIN
GEN: for I in 1 to 3 generate
TS(I) <= SS(I);
end generate
-- Failure_here
-- Semicolon missing before 'end'
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s07b00x00p02n01i01790 - In the generate statement, the reserved word end generate must be followed by a semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s07b00x00p02n01i01790arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/cmp_400.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_400 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_400;
architecture augh of cmp_400 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug08/paren9.vhdl | 3 | 260 | entity paren9 is
end paren9;
architecture behav of paren9
is
begin
process
function a return string is
begin
return "hello";
end a;
subtype b is natural range 1 to 2;
begin
assert a(b) = "he";
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1002/test.vhdl | 1 | 290 | library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity test is
generic (
BITS : positive := 2
);
end entity test;
architecture rtl of test is
constant count : positive := 2 ** BITS - 1;
subtype node_t is integer range 0 to count;
begin
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1242.vhd | 4 | 1672 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1242.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n01i01242ent IS
END c08s02b00x00p04n01i01242ent;
ARCHITECTURE c08s02b00x00p04n01i01242arch OF c08s02b00x00p04n01i01242ent IS
BEGIN
TESTING: PROCESS
constant N2 : Character := 'R';
BEGIN
assert FALSE
report N2
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n01i01242 - Expression type used in a report clause should be STRING"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n01i01242arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3140.vhd | 4 | 2315 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3140.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p10n01i03140ent_a IS
generic ( g1 : real := 22.0 );
END c05s02b02x00p10n01i03140ent_a;
ARCHITECTURE c05s02b02x00p10n01i03140arch_a OF c05s02b02x00p10n01i03140ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( g1 = 22.0 )
report "***PASSED TEST: c05s02b02x00p10n01i03140"
severity NOTE;
assert ( g1 = 22.0 )
report "***FAILED TEST: c05s02b02x00p10n01i03140 - The formal generics take on implicit OPENs."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p10n01i03140arch_a;
--
ENTITY c05s02b02x00p10n01i03140ent IS
END c05s02b02x00p10n01i03140ent;
ARCHITECTURE c05s02b02x00p10n01i03140arch OF c05s02b02x00p10n01i03140ent IS
component c05s02b02x00p10n01i03140ent_a
end component;
BEGIN
comp1 : c05s02b02x00p10n01i03140ent_a;
END c05s02b02x00p10n01i03140arch;
configuration c05s02b02x00p10n01i03140cfg of c05s02b02x00p10n01i03140ent is
for c05s02b02x00p10n01i03140arch
for comp1 : c05s02b02x00p10n01i03140ent_a use entity work.c05s02b02x00p10n01i03140ent_a(c05s02b02x00p10n01i03140arch_a);
end for;
end for;
end c05s02b02x00p10n01i03140cfg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1183.vhd | 4 | 1681 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1183.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p02n01i01183ent IS
END c08s01b00x00p02n01i01183ent;
ARCHITECTURE c08s01b00x00p02n01i01183arch OF c08s01b00x00p02n01i01183ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
assert FALSE
report "***PASSED TEST: c08s01b00x00p02n01i01183"
severity NOTE;
wait;
assert FALSE
report "***FAILED TEST: c08s01b00x00p02n01i01183 - A wait statement with no argument"
severity ERROR;
END PROCESS TESTING;
END c08s01b00x00p02n01i01183arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc737.vhd | 4 | 3447 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc737.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x01p04n01i00737ent_a is
generic (
constant gc1 : in integer;
constant gc2 : in real;
constant gc3 : in boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00737ent_a;
architecture c01s01b01x01p04n01i00737arch_a of c01s01b01x01p04n01i00737ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1 = 5) AND (gc2 = 0.1234) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00737"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00737 - Simple generic association in component instantiation (type conversion done on actual in generic map failed)."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00737arch_a;
ENTITY c01s01b01x01p04n01i00737ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00737ent;
ARCHITECTURE c01s01b01x01p04n01i00737arch OF c01s01b01x01p04n01i00737ent IS
constant c1 : integer := 33;
constant c2 : real := 1.23557;
constant c3 : boolean := FALSE;
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : real;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00737ent_a(c01s01b01x01p04n01i00737_arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
function BoolToInt(bin : boolean) return integer is
begin
if bin then
return 5;
else
return 99;
end if;
end;
function IntegerToReal(iin : integer) return real is
begin
return 0.1234;
end;
function BitToBool(bin : bit) return boolean is
begin
if (bin = '1') then
return TRUE;
else
return FALSE;
end if;
end;
BEGIN
u1 : comp1
generic map (BoolToInt(TRUE), IntegerToReal(1234), BitToBool('1'))
port map (ee1,ee2);
END c01s01b01x01p04n01i00737arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2646.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2646.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02646ent IS
END c13s03b01x00p02n01i02646ent;
ARCHITECTURE c13s03b01x00p02n01i02646arch OF c13s03b01x00p02n01i02646ent IS
BEGIN
TESTING: PROCESS
variable &k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02646 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02646arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/cmp_974.vhd | 2 | 383 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_974 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_974;
architecture augh of cmp_974 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2649.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2649.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02649ent IS
END c13s03b01x00p02n01i02649ent;
ARCHITECTURE c13s03b01x00p02n01i02649arch OF c13s03b01x00p02n01i02649ent IS
BEGIN
TESTING: PROCESS
variable )k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02649 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02649arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2596.vhd | 4 | 1687 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2596.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02596ent IS
END c13s03b01x00p02n01i02596ent;
ARCHITECTURE c13s03b01x00p02n01i02596arch OF c13s03b01x00p02n01i02596ent IS
BEGIN
TESTING: PROCESS
variable k[ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02596 - Identifier can not end with '['."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02596arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2111.vhd | 4 | 2140 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2111.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02111ent IS
END c07s02b04x00p20n01i02111ent;
ARCHITECTURE c07s02b04x00p20n01i02111arch OF c07s02b04x00p20n01i02111ent IS
TYPE time_v is array (integer range <>) of time;
SUBTYPE time_null is time_v (1 to 0);
SUBTYPE time_4 is time_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : time_4;
variable l_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
variable r_operand : time_null;
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
report "***PASSED TEST: c07s02b04x00p20n01i02111"
severity NOTE;
assert ((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
report "***FAILED TEST: c07s02b04x00p20n01i02111 - Concatenation of null and TIME array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02111arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2964.vhd | 4 | 5109 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2964.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b00x00p03n01i02964ent IS
END c02s03b00x00p03n01i02964ent;
ARCHITECTURE c02s03b00x00p03n01i02964arch OF c02s03b00x00p03n01i02964ent IS
function f1a(constant c1 : in integer) return integer is
begin
return 12;
end;
function f1a(constant c1,c2 : in integer) return integer is
begin
return 25;
end;
function f2b(constant c1 : in integer) return integer is
begin
return 22;
end;
function f2b(constant c1 : in real) return integer is
begin
return 28;
end;
function f3c(constant c0:integer; constant c1:real) return integer is
begin
return 32;
end;
function f3c(constant c1:real; constant c0:integer) return integer is
begin
return 38;
end;
function f4d(constant c1 : in integer) return integer is
begin
return 42;
end;
function f4d(constant c1 : in integer) return real is
begin
return 48.0;
end;
function f5e(constant c1 : in integer) return integer is
begin
return 52;
end;
procedure f5e(constant c1 : in integer) is
begin
return;
end;
function f6f(constant c0 : in real;constant c1 : in integer) return integer is
begin
return 62;
end;
function f6f(constant c2 : in integer;constant c3 : in real) return integer is
begin
return 68;
end;
BEGIN
TESTING: PROCESS
variable i1 : integer;
variable r1 : real;
variable k : integer := 0;
BEGIN
i1 := 8;
if (i1 /= 8) then
k := 1;
end if;
assert (i1=8)
report "Error in initial conditions detected"
severity failure;
i1:= f1a(4);
if (i1 /= 12) then
k := 1;
end if;
assert (i1=12)
report "Error differentiating overloaded subprog by number of formals"
severity failure;
i1:=f1a(16,23);
if (i1 /= 25) then
k := 1;
end if;
assert (i1=25)
report "Error differentiating overloaded subprog by number of formals"
severity failure;
i1:= f2b(4);
if (i1 /= 22) then
k := 1;
end if;
assert (i1=22)
report "Error differentiating overloaded subprog by type of formals"
severity failure;
i1:=f2b(4.0);
if (i1 /= 28) then
k := 1;
end if;
assert (i1=28)
report "Error differentiating overloaded subprog by type of formals"
severity failure;
i1:= f3c(4,4.0);
if (i1 /= 32) then
k := 1;
end if;
assert (i1=32)
report "Error differentiating overloaded subprog by order of formals"
severity failure;
i1:= f3c(4.0,4);
if (i1 /= 38) then
k := 1;
end if;
assert (i1=38)
report "Error differentiating overloaded subprog by order of formals"
severity failure;
i1:= f4d(4);
if (i1 /= 42) then
k := 1;
end if;
assert (i1=42)
report "Error differentiating overloaded subprog by return type"
severity failure;
r1:= f4d(4);
if (r1 /= 48.0) then
k := 1;
end if;
assert (r1=48.0)
report "Error differentiating overloaded subprog by return type"
severity failure;
i1:= f5e(4);
if (i1 /= 52) then
k := 1;
end if;
assert (i1=52)
report "Error differentiating overloaded subprog by having a return"
severity failure;
i1:= f6f(c1 => 4, c0 => 4.4);
if (i1 /= 62) then
k := 1;
end if;
assert (i1=62)
report "Error differentiating overloaded subprog by name of formals"
severity failure;
i1:= f6f(c3 => 4.4, c2 => 4);
if (i1 /= 68) then
k := 1;
end if;
assert (i1=68)
report "Error differentiating overloaded subprog by name of formals"
severity failure;
wait for 5 ns;
assert NOT( k=0 )
report "***PASSED TEST: c02s03b00x00p03n01i02964"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c02s03b00x00p03n01i02964 - Overload subprogram call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p03n01i02964arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue132/repro.vhdl | 2 | 121 | package pkg is
constant a : integer := 5; -- Strange but valid character: é
-- Invalid ascii character
end pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc353.vhd | 4 | 1664 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc353.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00353ent IS
END c03s02b01x01p02n01i00353ent;
ARCHITECTURE c03s02b01x01p02n01i00353arch OF c03s02b01x01p02n01i00353ent IS
type bit_vctor is array (0.0 to 7) of real; --Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00353 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00353arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd | 4 | 1769 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity battery is
port ( terminal plus, minus : electrical );
end entity battery;
architecture wrong of battery is
constant v_nominal : real := 9.0;
quantity v across plus to minus;
begin
v == v_nominal;
end architecture wrong;
--
architecture correct of battery is
constant v_nominal : real := 9.0;
quantity v across i through plus to minus;
begin
v == v_nominal;
end architecture correct;
-- end code from book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
signal clamp : bit;
quantity v1, v2 : real;
begin
-- code from book
if clamp = '1' use
v1 == 5.0;
v2 == 0.0;
else
v1 == v2;
end use;
-- end code from book
end architecture test;
| gpl-2.0 |
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