repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect-b.vhd
|
4
|
1850
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tovect-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of to_vector_test is
signal vec : std_ulogic_vector(15 downto 0);
signal r : real := 0.0;
begin
dut : entity work.to_vector(behavioral)
port map (r, vec);
stimulus : process is
begin
r <= 0.0; wait for 10 ns;
r <= -1.0; wait for 10 ns;
r <= -2.0; wait for 10 ns;
r <= +0.9999; wait for 10 ns;
r <= +2.0; wait for 10 ns;
r <= -0.5; wait for 10 ns;
r <= +0.5; wait for 10 ns;
wait;
end process stimulus;
end architecture bench;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1903.vhd
|
4
|
3476
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1903.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01903pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01903pkg;
use work.c07s01b00x00p08n01i01903pkg.all;
ENTITY c07s01b00x00p08n01i01903ent_a IS
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
END c07s01b00x00p08n01i01903ent_a;
ARCHITECTURE c07s01b00x00p08n01i01903arch_a OF c07s01b00x00p08n01i01903ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01903arch_a;
use work.c07s01b00x00p08n01i01903pkg.all;
ENTITY c07s01b00x00p08n01i01903ent IS
END c07s01b00x00p08n01i01903ent;
ARCHITECTURE c07s01b00x00p08n01i01903arch OF c07s01b00x00p08n01i01903ent IS
constant bus_width : natural := 7;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width));
signal out_bus : out cmd_bus (0 to small_int(bus_width)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01903ent_a(c07s01b00x00p08n01i01903arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "process label accepted as primary in a component instantiation port map expression."
severity note ;
exit l;
end loop l;
end process p;
c : test port map ( ibus, p ); -- process label illegal here
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01903 - Process labels are not permitted as primaries in a component instantiation port map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01903arch;
|
gpl-2.0
|
swinman/exuberant-ctags
|
Test/test.vhd
|
91
|
192381
|
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
|
gpl-2.0
|
tgingold/ghdl
|
libraries/openieee/v87/numeric_std-body.vhdl
|
1
|
80784
|
-- This -*- vhdl -*- file was generated from numeric_std-body.proto
-- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.3 compliant numeric std package body.
-- The implementation is based only on the specifications.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
package body NUMERIC_STD is
constant NO_WARNING : Boolean := False;
constant null_unsigned : unsigned (0 downto 1) := (others => '0');
constant null_signed : signed (0 downto 1) := (others => '0');
subtype nat1 is natural range 0 to 1;
type nat1_to_sl_type is array (nat1) of std_ulogic;
constant nat1_to_01 : nat1_to_sl_type := (0 => '0', 1 => '1');
subtype sl_01 is std_ulogic range '0' to '1';
subtype sl_x01 is std_ulogic range 'X' to '1';
type carry_array is array (sl_01, sl_01, sl_01) of sl_01;
constant compute_carry : carry_array :=
('0' => ('0' => ('0' => '0', '1' => '0'),
'1' => ('0' => '0', '1' => '1')),
'1' => ('0' => ('0' => '0', '1' => '1'),
'1' => ('0' => '1', '1' => '1')));
constant compute_sum : carry_array :=
('0' => ('0' => ('0' => '0', '1' => '1'),
'1' => ('0' => '1', '1' => '0')),
'1' => ('0' => ('0' => '1', '1' => '0'),
'1' => ('0' => '0', '1' => '1')));
type sl_to_x01_array is array (std_ulogic) of sl_x01;
constant sl_to_x01 : sl_to_x01_array :=
('0' | 'L' => '0', '1' | 'H' => '1', others => 'X');
type compare_type is (compare_unknown,
compare_lt,
compare_eq,
compare_gt);
-- Match.
-- '-' matches with everything.
-- '0'/'L' matches, '1'/'H' matches.
type match_table_type is array (std_ulogic, std_ulogic) of boolean;
constant match_table: match_table_type :=
('0' | 'L' => ('0' | 'L' | '-' => true, others => false),
'1' | 'H' => ('1' | 'H' | '-' => true, others => false),
'-' => (others => true),
others => ('-' => true, others => false));
function MAX (L, R : natural) return natural is
begin
if L > R then
return L;
else
return R;
end if;
end MAX;
function TO_INTEGER (ARG : UNSIGNED) return NATURAL
is
variable argn : UNSIGNED (ARG'Length -1 downto 0);
variable res : natural := 0;
begin
if argn'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null array detected, returning 0"
severity warning;
return 0;
end if;
argn := TO_01 (ARG, 'X');
if argn (0) = 'X' then
assert NO_WARNING
report
"NUMERIC_STD.TO_INTEGER: non logical value detected, returning 0"
severity warning;
return 0;
end if;
for i in argn'range loop
res := res + res;
if argn (i) = '1' then
res := res + 1;
end if;
end loop;
return res;
end TO_INTEGER;
function TO_INTEGER (ARG : SIGNED) return INTEGER
is
variable argn : SIGNED (ARG'Length -1 downto 0);
variable res : integer := 0;
variable b : STD_ULOGIC;
begin
if argn'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null array detected, returning 0"
severity warning;
return 0;
end if;
argn := TO_01 (ARG, 'X');
if argn (0) = 'X' then
assert NO_WARNING
report
"NUMERIC_STD.TO_INTEGER: non logical value detected, returning 0"
severity warning;
return 0;
end if;
if argn (argn'left) = '1' then
-- Negative value
b := '0';
else
b := '1';
end if;
for i in argn'range loop
res := res + res;
if argn (i) = b then
res := res + 1;
end if;
end loop;
if b = '0' then
-- Avoid overflow.
res := -res - 1;
end if;
return res;
end TO_INTEGER;
function TO_01 (S : SIGNED; XMAP : STD_LOGIC := '0') return SIGNED
is
subtype res_type is SIGNED (S'Length - 1 downto 0);
variable res : res_type;
alias snorm: res_type is S;
begin
if S'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null array detected"
severity warning;
return null_signed;
else
for i in res_type'range loop
case snorm (i) is
when '0' | 'L' => res (i) := '0';
when '1' | 'H' => res (i) := '1';
when others =>
assert NO_WARNING
report "NUMERIC_STD.TO_01: non logical value detected"
severity warning;
res := (others => XMAP);
exit;
end case;
end loop;
end if;
return res;
end TO_01;
function TO_01 (S : UNSIGNED; XMAP : STD_LOGIC := '0') return UNSIGNED
is
subtype res_type is UNSIGNED (S'Length - 1 downto 0);
variable res : res_type;
alias snorm: res_type is S;
begin
if S'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null array detected"
severity warning;
return null_unsigned;
else
for i in res_type'range loop
case snorm (i) is
when '0' | 'L' => res (i) := '0';
when '1' | 'H' => res (i) := '1';
when others =>
assert NO_WARNING
report "NUMERIC_STD.TO_01: non logical value detected"
severity warning;
res := (others => XMAP);
exit;
end case;
end loop;
end if;
return res;
end TO_01;
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED
is
variable res : UNSIGNED (SIZE - 1 downto 0);
variable a : natural := arg;
variable d : nat1;
begin
if size = 0 then
return null_unsigned;
end if;
for i in res'reverse_range loop
d := a rem 2;
res (i) := nat1_to_01 (d);
a := a / 2;
end loop;
if a /= 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector is truncated"
severity warning;
end if;
return res;
end TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED
is
variable res : SIGNED (SIZE - 1 downto 0);
variable v : integer := arg;
variable b0, b1 : std_ulogic;
variable d : nat1;
begin
if size = 0 then
return null_signed;
end if;
if arg < 0 then
-- Use one complement to avoid overflow:
-- -v = (not v) + 1
-- not v = -v - 1
-- not v = -(v + 1)
v := -(arg + 1);
b0 := '1';
b1 := '0';
else
v := arg;
b0 := '0';
b1 := '1';
end if;
for i in res'reverse_range loop
d := v rem 2;
v := v / 2;
if d = 0 then
res (i) := b0;
else
res (i) := b1;
end if;
end loop;
if v /= 0 or res (res'left) /= b0 then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector is truncated"
severity warning;
end if;
return res;
end TO_SIGNED;
function std_match (l, r : std_ulogic) return boolean is
begin
return match_table (l, r);
end std_match;
function std_match (l, r : std_ulogic_vector) return boolean
is
alias la : std_ulogic_vector (l'length downto 1) is l;
alias ra : std_ulogic_vector (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function std_match (l, r : std_logic_vector) return boolean
is
alias la : std_logic_vector (l'length downto 1) is l;
alias ra : std_logic_vector (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function std_match (l, r : UNSIGNED) return boolean
is
alias la : UNSIGNED (l'length downto 1) is l;
alias ra : UNSIGNED (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function std_match (l, r : SIGNED) return boolean
is
alias la : SIGNED (l'length downto 1) is l;
alias ra : SIGNED (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function "+" (l, r : UNSIGNED) return UNSIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is UNSIGNED (lft downto 0);
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_UNSIGNED;
end if;
carry := '0';
for i in 0 to lft loop
if i > la'left then
lb := '0';
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := '0';
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "+";
function "+" (l, r : SIGNED) return SIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is SIGNED (lft downto 0);
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_SIGNED;
end if;
carry := '0';
for i in 0 to lft loop
if i > la'left then
lb := l (l'left);
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := r (r'left);
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "+";
function "+" (l : UNSIGNED; r : NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '0';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : NATURAL; r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '0';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
ld := l1 - 2 * l2;
l1 := l2;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : SIGNED; r : INTEGER) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '0';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= -rmsb then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : INTEGER; r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '0';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
if l1 < 0 then
ld := 2 * l2 - l1;
l1 := l2 - ld;
else
ld := l1 - 2 * l2;
l1 := l2;
end if;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= -lmsb then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "-" (l, r : UNSIGNED) return UNSIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is UNSIGNED (lft downto 0);
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_UNSIGNED;
end if;
carry := '1';
for i in 0 to lft loop
if i > la'left then
lb := '0';
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := '0';
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "-";
function "-" (l, r : SIGNED) return SIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is SIGNED (lft downto 0);
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_SIGNED;
end if;
carry := '1';
for i in 0 to lft loop
if i > la'left then
lb := l (l'left);
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := r (r'left);
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "-";
function "-" (l : UNSIGNED; r : NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '1';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : NATURAL; r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '1';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
ld := l1 - 2 * l2;
l1 := l2;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : SIGNED; r : INTEGER) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '1';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= -rmsb then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : INTEGER; r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '1';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
if l1 < 0 then
ld := 2 * l2 - l1;
l1 := l2 - ld;
else
ld := l1 - 2 * l2;
l1 := l2;
end if;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= -lmsb then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "*" (L, R : UNSIGNED) return UNSIGNED
is
alias la : UNSIGNED (L'Length - 1 downto 0) is l;
alias ra : UNSIGNED (R'Length - 1 downto 0) is r;
variable res : UNSIGNED (L'length + R'Length -1 downto 0) := (others => '0');
variable rb, lb, vb, carry : sl_x01;
begin
if la'length = 0 or ra'length = 0 then
return null_UNSIGNED;
end if;
-- Shift and add L.
for i in natural range 0 to ra'left loop
rb := sl_to_x01 (ra (i));
if rb = '1' then
-- Compute res := res + shift_left (l, i).
carry := '0';
for j in la'reverse_range loop
lb := la (j);
vb := res (i + j);
res (i + j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
-- Propagate carry.
for j in i + la'length to res'left loop
exit when carry = '0';
vb := res (j);
res (j) := carry xor vb;
carry := carry and vb;
end loop;
elsif rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""*"": non logical value detected"
severity warning;
end if;
end loop;
return res;
end "*";
function "*" (L, R : SIGNED) return SIGNED
is
alias la : SIGNED (L'Length - 1 downto 0) is l;
alias ra : SIGNED (R'Length - 1 downto 0) is r;
variable res : SIGNED (L'length + R'Length -1 downto 0) := (others => '0');
variable rb, lb, vb, carry : sl_x01;
begin
if la'length = 0 or ra'length = 0 then
return null_SIGNED;
end if;
-- Shift and add L.
for i in natural range 0 to ra'left - 1 loop
rb := sl_to_x01 (ra (i));
if rb = '1' then
-- Compute res := res + shift_left (l, i).
carry := '0';
for j in la'reverse_range loop
lb := la (j);
vb := res (i + j);
res (i + j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
-- Sign extend and propagate carry.
lb := la (la'left);
for j in i + l'length to res'left loop
vb := res (j);
res (j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
elsif rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""*"": non logical value detected"
severity warning;
end if;
end loop;
if ra (ra'left) = '1' then
-- R is a negative number. It is considered as:
-- -2**n + (Rn-1 Rn-2 ... R0).
-- Compute res := res - 2**n * l.
carry := '1';
for i in la'reverse_range loop
vb := res (ra'length - 1 + i);
lb := not la (i);
res (ra'length - 1+ i) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
vb := res (res'left);
lb := not la (la'left);
res (res'left) := compute_sum (carry, vb, lb);
end if;
return res;
end "*";
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant size : natural := l'length;
begin
if size = 0 then
return null_UNSIGNED;
end if;
return l * to_UNSIGNED (r, size);
end "*";
function "*" (L : SIGNED; R : INTEGER) return SIGNED
is
constant size : natural := l'length;
begin
if size = 0 then
return null_SIGNED;
end if;
return l * to_SIGNED (r, size);
end "*";
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant size : natural := r'length;
begin
if size = 0 then
return null_UNSIGNED;
end if;
return r * to_UNSIGNED (l, size);
end "*";
function "*" (L : INTEGER; R : SIGNED) return SIGNED
is
constant size : natural := r'length;
begin
if size = 0 then
return null_SIGNED;
end if;
return r * to_SIGNED (l, size);
end "*";
function has_0x (a : UNSIGNED) return sl_x01
is
variable res : sl_x01 := '0';
begin
for i in a'range loop
if a (i) = 'X' then
return 'X';
end if;
res := res or a (i);
end loop;
return res;
end has_0x;
-- All index range are normalized (N downto 0).
-- NUM and QUOT have the same range.
-- DEM and REMAIN have the same range.
-- No 'X'.
procedure divmod (num, dem : UNSIGNED; quot, remain : out UNSIGNED)
is
variable reg : unsigned (dem'left + 1 downto 0) := (others => '0');
variable sub : unsigned (dem'range) := (others => '0');
variable carry, d : sl_x01;
begin
for i in num'range loop
-- Shift
reg (reg'left downto 1) := reg (reg'left - 1 downto 0);
reg (0) := num (i);
-- Substract
carry := '1';
for j in dem'reverse_range loop
d := not dem (j);
sub (j) := compute_sum (carry, reg (j), d);
carry := compute_carry (carry, reg (j), d);
end loop;
carry := compute_carry (carry, reg (reg'left), '1');
-- Test
if carry = '0' then
-- Greater than
quot (i) := '0';
else
quot (i) := '1';
reg (reg'left) := '0';
reg (sub'range) := sub;
end if;
end loop;
remain := reg (dem'range);
end divmod;
function size_unsigned (n : natural) return natural
is
-- At least one bit (even for 0).
variable res : natural := 1;
variable n1 : natural := n;
begin
while n1 > 1 loop
res := res + 1;
n1 := n1 / 2;
end loop;
return res;
end size_unsigned;
function size_signed (n : integer) return natural
is
variable res : natural := 1;
variable n1 : natural;
begin
if n >= 0 then
n1 := n;
else
-- Use /N = -X -1 = -(X + 1) (No overflow).
n1 := -(n + 1);
end if;
while n1 /= 0 loop
res := res + 1;
n1 := n1 / 2;
end loop;
return res;
end size_signed;
function "/" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""/"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return quot;
end "/";
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return l / to_unsigned (r, r_size);
end "/";
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return resize (to_unsigned (l, l_size) / r, r'length);
end "/";
function "rem" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""rem"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return rema;
end "rem";
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return resize (l rem to_unsigned (r, r_size), l'length);
end "rem";
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return to_unsigned (l, l_size) rem r;
end "rem";
function "mod" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""mod"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return rema;
end "mod";
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return resize (l mod to_unsigned (r, r_size), l'length);
end "mod";
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return to_unsigned (l, l_size) mod r;
end "mod";
function has_0x (a : SIGNED) return sl_x01
is
variable res : sl_x01 := '0';
begin
for i in a'range loop
if a (i) = 'X' then
return 'X';
end if;
res := res or a (i);
end loop;
return res;
end has_0x;
function "-" (ARG : SIGNED) return SIGNED
is
subtype arg_type is SIGNED (ARG'length - 1 downto 0);
alias arga : arg_type is arg;
variable res : arg_type;
variable carry, a : sl_x01;
begin
if arga'length = 0 then
return null_signed;
end if;
if has_0x (arga) = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
return arg_type'(others => 'X');
end if;
carry := '1';
for i in arga'reverse_range loop
a := not arga (i);
res (i) := carry xor a;
carry := carry and a;
end loop;
return res;
end "-";
function "abs" (ARG : SIGNED) return SIGNED
is
subtype arg_type is SIGNED (ARG'length - 1 downto 0);
alias arga : arg_type is arg;
variable res : arg_type;
variable carry, a : sl_x01;
begin
if arga'length = 0 then
return null_signed;
end if;
if has_0x (arga) = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
return arg_type'(others => 'X');
end if;
if arga (arga'left) = '0' then
return arga;
end if;
carry := '1';
for i in arga'reverse_range loop
a := not arga (i);
res (i) := carry xor a;
carry := carry and a;
end loop;
return res;
end "abs";
function "/" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""/"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
if (ra (ra'left) xor la (la'left)) = '1' then
return -signed (quot);
else
return signed (quot);
end if;
end "/";
function "/" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return l / to_signed (r, r_size);
end "/";
function "/" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return resize (to_signed (l, max (l_size, r'length)) / r, r'length);
end "/";
function "rem" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""rem"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""rem"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
-- Result of rem has the sign of the dividend.
if la (la'left) = '1' then
return -signed (rema);
else
return signed (rema);
end if;
end "rem";
function "rem" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return resize (l rem to_signed (r, r_size), l'length);
end "rem";
function "rem" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return to_signed (l, l_size) rem r;
end "rem";
function "mod" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""mod"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""mod"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
-- Result of mod has the sign of the divisor.
if rema = r_utype'(others => '0') then
-- If the remainder is 0, then the modulus is 0.
return signed (rema);
else
if ra (ra'left) = '1' then
if la (la'left) = '1' then
return -signed (rema);
else
return ra + signed (rema);
end if;
else
if la (la'left) = '1' then
return ra - signed (rema);
else
return signed (rema);
end if;
end if;
end if;
end "mod";
function "mod" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return resize (l mod to_signed (r, r_size), l'length);
end "mod";
function "mod" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return to_signed (l, l_size) mod r;
end "mod";
function resize (ARG : UNSIGNED; NEW_SIZE: natural) return UNSIGNED
is
alias arg1 : UNSIGNED (ARG'length - 1 downto 0) is arg;
variable res : UNSIGNED (new_size - 1 downto 0) := (others => '0');
begin
if new_size = 0 then
return null_UNSIGNED;
end if;
if arg1'length = 0 then
return res;
end if;
if arg1'length > new_size then
-- Reduction.
res := arg1 (res'range);
else
-- Expansion
res (arg1'range) := arg1;
end if;
return res;
end resize;
function resize (ARG : SIGNED; NEW_SIZE: natural) return SIGNED
is
alias arg1 : SIGNED (ARG'length - 1 downto 0) is arg;
variable res : SIGNED (new_size - 1 downto 0) := (others => '0');
begin
if new_size = 0 then
return null_SIGNED;
end if;
if arg1'length = 0 then
return res;
end if;
if arg1'length > new_size then
-- Reduction.
res (res'left) := arg1 (arg1'left);
res (res'left - 1 downto 0) := arg1 (res'left - 1 downto 0);
else
-- Expansion
res (arg1'range) := arg1;
res (res'left downto arg1'length) := (others => arg1 (arg1'left));
end if;
return res;
end resize;
function "not" (l : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not la (I);
end loop;
return res;
end "not";
function "not" (l : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not la (I);
end loop;
return res;
end "not";
function "and" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""and"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) and ra (I);
end loop;
end if;
return res;
end "and";
function "and" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""and"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) and ra (I);
end loop;
end if;
return res;
end "and";
function "nand" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nand"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nand ra (I);
end loop;
end if;
return res;
end "nand";
function "nand" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nand"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nand ra (I);
end loop;
end if;
return res;
end "nand";
function "or" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""or"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) or ra (I);
end loop;
end if;
return res;
end "or";
function "or" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""or"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) or ra (I);
end loop;
end if;
return res;
end "or";
function "nor" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nor ra (I);
end loop;
end if;
return res;
end "nor";
function "nor" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nor ra (I);
end loop;
end if;
return res;
end "nor";
function "xor" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) xor ra (I);
end loop;
end if;
return res;
end "xor";
function "xor" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) xor ra (I);
end loop;
end if;
return res;
end "xor";
function ucompare (l, r : UNSIGNED) return compare_type
is
constant sz : integer := MAX (l'length, r'length) - 1;
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable lb, rb : sl_x01;
variable res : compare_type;
begin
res := compare_eq;
for i in 0 to sz loop
if i > la'left then
lb := '0';
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := '0';
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
return res;
end ucompare;
function scompare (l, r : SIGNED) return compare_type
is
constant sz : integer := MAX (l'length, r'length) - 1;
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable lb, rb : sl_x01;
variable res : compare_type;
begin
-- Consider sign bit as S * -(2**N).
lb := sl_to_x01 (la (la'left));
rb := sl_to_x01 (ra (ra'left));
if lb = '1' and rb = '0' then
return compare_lt;
elsif lb = '0' and rb = '1' then
return compare_gt;
else
res := compare_eq;
end if;
for i in 0 to sz - 1 loop
if i > la'left then
lb := l (l'left);
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := r (r'left);
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
return res;
end scompare;
function ucompare (l : UNSIGNED; r : NATURAL) return compare_type
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable lb, rb : sl_x01;
variable res : compare_type;
begin
res := compare_eq;
r1 := r;
for i in la'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
if lb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
if r1 /= 0 then
res := compare_lt;
end if;
return res;
end ucompare;
function scompare (l : SIGNED; r : INTEGER) return compare_type
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable lb, rb : sl_x01;
variable res : compare_type;
begin
res := compare_eq;
r1 := r;
for i in la'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
if lb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
if sl_to_x01 (l (l'left)) = '1' then
if r >= 0 then
res := compare_lt;
end if;
else
if r < 0 then
res := compare_gt;
end if;
end if;
return res;
end scompare;
function "=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq = res;
end "=";
function "=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq = res;
end "=";
function "/=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq /= res;
end "/=";
function "/=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq /= res;
end "/=";
function ">" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq > res;
end ">";
function ">" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq > res;
end ">";
function ">=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq >= res;
end ">=";
function ">=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq >= res;
end ">=";
function "<" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq < res;
end "<";
function "<" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq < res;
end "<";
function "<=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq <= res;
end "<=";
function "<=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq <= res;
end "<=";
function shift_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
end if;
return res;
end shift_left;
function shift_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
end if;
return res;
end shift_right;
function rotate_left (ARG : UNSIGNED; COUNT: natural) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count rem res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end rotate_left;
function rotate_right (ARG : UNSIGNED; COUNT: natural) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count rem res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end rotate_right;
function shift_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
end if;
return res;
end shift_left;
function shift_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => arg1 (arg1'left));
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
end if;
return res;
end shift_right;
function rotate_left (ARG : SIGNED; COUNT: natural) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count rem res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end rotate_left;
function rotate_right (ARG : SIGNED; COUNT: natural) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count rem res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end rotate_right;
end NUMERIC_STD;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_3.vhdl
|
4
|
2020
|
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity fopen_test_3 is
end fopen_test_3;
architecture test0 of fopen_test_3 is
constant StringLength: integer := 16;
constant NumOfStrings: integer := 5;
subtype str16 is string (1 to StringLength);
type string_table is array (1 to NumOfStrings) of str16;
constant string_array: string_table :=
( "This is string 1"
,"__Hello World__"
,"This is string " & "3"
,"_Bird is a word_"
,"_Goodbye (ciao)_"
);
type ft is file of string;
begin
doit: process
file file_desc : ft;
begin
file_open(file_desc, "fopen_test_3.out", write_mode);
for i in NumOfStrings downto 1 loop
write(file_desc, string_array(i));
end loop;
file_close(file_desc);
file_open(file_desc, "fopen_test_3.out", write_mode);
for i in 1 to NumOfStrings loop
write(file_desc, string_array(i));
end loop;
file_close(file_desc);
wait;
end process;
end test0;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1011.vhd
|
4
|
2100
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1011.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01011ent IS
END c06s03b00x00p10n01i01011ent;
ARCHITECTURE c06s03b00x00p10n01i01011arch OF c06s03b00x00p10n01i01011ent IS
procedure check (x: in integer; y: in boolean; signal z :out integer) is
begin
z <= 5;
end;
signal p: integer ;
signal q: boolean ;
signal k: integer ;
BEGIN
TESTING: PROCESS
BEGIN
check(c06s03b00x00p10n01i01011arch.p, c06s03b00x00p10n01i01011arch.q, k);
wait for 10 ns;
assert NOT(k=5)
report "***PASSED TEST: c06s03b00x00p10n01i01011"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s03b00x00p10n01i01011 - An expanded name with the prefix of an architecture name and the suffix of signal names declared in the architecture can be used in a statement (in this test, procedure call statement) within the architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n01i01011arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2974.vhd
|
4
|
2035
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2974.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p03n01i02974ent IS
END c02s03b01x00p03n01i02974ent;
ARCHITECTURE c02s03b01x00p03n01i02974arch OF c02s03b01x00p03n01i02974ent IS
type newt is (one,two,three,four);
function "-" (constant c1 : in integer) return newt is
begin
assert (c1=70)
report "Error in association of unary - operator"
severity failure;
assert NOT( c1=70 )
report "***PASSED TEST: c02s03b01x00p03n01i02974"
severity NOTE;
assert ( c1=70 )
report "***FAILED TEST: c02s03b01x00p03n01i02974 - Error in - overloading as unary operator."
severity ERROR;
return four;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
n1:= -70;
assert (n1=four)
report "Error in call to overloaded unary - operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p03n01i02974arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random.vhd
|
4
|
2379
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_random.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package random is
type distribution_type is (fixed, uniform, exponential);
subtype probability is real range 0.0 to 1.0;
type probability_vector is array (positive range <>) of probability;
type seed_type is record
seed1, seed2 : positive;
end record seed_type;
type seed_array is array ( natural range <> ) of seed_type;
constant sample_seeds : seed_array(0 to 50);
type random_info_record is record
seed : seed_type;
distribution : distribution_type;
mean : real;
lower_bound, upper_bound : real;
end record random_info_record;
procedure init_fixed ( random_info : out random_info_record;
mean : in real );
procedure init_uniform ( random_info : out random_info_record;
lower_bound, upper_bound : in real;
seed : in seed_type );
procedure init_exponential ( random_info : out random_info_record;
mean : in real;
seed : in seed_type );
procedure generate_random ( random_info : inout random_info_record;
random_number : out real );
end package random;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc393.vhd
|
4
|
1876
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc393.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p06n01i00393ent IS
END c03s02b01x01p06n01i00393ent;
ARCHITECTURE c03s02b01x01p06n01i00393arch OF c03s02b01x01p06n01i00393ent IS
type M1 is array (positive range <>) of integer;
BEGIN
TESTING: PROCESS
variable V1 : M1(4 to 10) ; -- No_failure_here
BEGIN
V1(4) := 4;
V1(10) := 10;
assert NOT(V1(4)=4 and V1(10)=10)
report "***PASSED TEST: c03s02b01x01p06n01i00393"
severity NOTE;
assert (V1(4)=4 and V1(10)=10)
report "***FAILED TEST: c03s02b01x01p06n01i00393 - Subtype indication of array object declaration must denote a constrained array."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p06n01i00393arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2450.vhd
|
4
|
2588
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2450.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02450ent IS
END c07s03b02x02p03n02i02450ent;
ARCHITECTURE c07s03b02x02p03n02i02450arch OF c07s03b02x02p03n02i02450ent IS
BEGIN
TESTING: PROCESS
type ENUM is ( ONE );
type A_ARRAY is array ( integer range <> ) of integer;
type B_ARRAY is array ( boolean range <> ) of real;
type C_ARRAY is array ( ENUM range <>, ENUM range <>) of bit;
subtype A_CON is A_ARRAY ( 1 to 4 );
subtype B_CON is B_ARRAY ( FALSE to TRUE );
subtype C_CON is C_ARRAY ( ONE to ONE, ONE to ONE );
function F_A ( PAR : A_ARRAY ) return A_CON is
begin return (1,2,3,4);
end F_A;
function F_B ( PAR : B_ARRAY ) return B_CON is
begin return (1.0, 2.0);
end F_B;
function F_C ( PAR : C_ARRAY ) return C_CON is
begin return (ONE=>(ONE=>'0'));
end F_C;
variable V_A : A_CON ;
variable V_B : B_CON ;
variable V_C : C_CON ;
BEGIN
V_A := F_A( F_A( (1,2,others=>3) ) ); -- Failure_here
-- SEMANTIC ERROR: "others" used in aggregate which corresponds to
-- an unconstrained formal parameter
assert FALSE
report "***FAILED TEST: c07s03b02x02p03n02i02450 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02450arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue1152/ent.vhdl
|
1
|
499
|
entity ent is
end;
architecture arch of ent is
type range_t is array (integer range <>) of bit;
function get_range (constant code : string) return range_t is
constant ret_val : range_t(1 to 10) := (others => '0');
begin
return ret_val;
end function get_range;
signal ret_val : boolean_vector(get_range("HELLO")'range) := (others => false);
--constant ret_range : range_t := get_range("HELLO");
--signal ret_val : boolean_vector(ret_range) := (others => false);
begin
end;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue818/tc7.vhdl
|
1
|
269
|
entity tc7 is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tc7 is
signal clk : std_logic;
signal tg : std_logic;
begin
process (clk) is
begin
if ?? falling_edge(clk) and (tg) then
null;
end if;
end process;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1805.vhd
|
4
|
1683
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1805.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p07n01i01805ent IS
END c07s01b00x00p07n01i01805ent;
ARCHITECTURE c07s01b00x00p07n01i01805arch OF c07s01b00x00p07n01i01805ent IS
signal POS : Boolean;
signal P1 : Boolean := False;
signal P2 : Boolean := True;
BEGIN
TESTING: PROCESS
BEGIN
POS <= P1 and (not ) after 20 ns; -- Failure_here
assert FALSE
report "***FAILED TEST: c07s01b00x00p07n01i01805 - Missing Primary."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p07n01i01805arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc658.vhd
|
4
|
2319
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc658.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:55 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00658ent IS
END c03s04b01x00p01n01i00658ent;
ARCHITECTURE c03s04b01x00p01n01i00658arch OF c03s04b01x00p01n01i00658ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type time_vector is array (natural range <>) of time;
subtype time_vector_range is time_vector(hi_to_low_range);
constant C1 : time_vector_range := (others => 3 ns);
type time_vector_range_file is file of time_vector_range;
BEGIN
TESTING: PROCESS
file filein : time_vector_range_file open write_mode is "iofile.07";
BEGIN
for i in 1 to 100 loop
write(filein,C1);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00658 - The output file will be verified by test s010108.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00658arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/sr2940/Prim.vhd
|
3
|
2219
|
-- Types and functions for Haskell Primitives
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package \Prim\ is
subtype \Int#\ is signed(31 downto 0);
subtype \GHC.Types.Int\ is signed(31 downto 0);
subtype \GHC.Types.Bool\ is std_logic;
-- Primitive arithmetic operations
function \GHC.Prim.==#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\;
function \GHC.Prim.<#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\;
function \GHC.Prim.-#\ ( a, b : \Int#\ ) return \Int#\;
-- Data Constructor predicates: each takes a object and returns
-- a boolean (i.e., tested with VHDL's if) that indicates whether the
-- object was constructed with the given constructor
function \is_GHC.Types.False\ (a : \GHC.Types.Bool\) return boolean;
function \is_GHC.Types.True\ (a : \GHC.Types.Bool\) return boolean;
function \is_GHC.Types.I#\ (a : \GHC.Types.Int\) return boolean;
-- Data "deconstructor" procedures: split apart an algebraic data type
-- into fields
procedure \expand_GHC.Types.I#\ ( input : in \GHC.Types.Int\;
field1 : out \Int#\);
end \Prim\;
package body \Prim\ is
function \GHC.Prim.==#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\ is
begin
if a = b then
return '1';
else
return '0';
end if;
end \GHC.Prim.==#\;
function \GHC.Prim.<#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\ is
begin
if a < b then
return '1';
else
return '0';
end if;
end \GHC.Prim.<#\;
function \GHC.Prim.-#\ ( a, b : \Int#\ ) return \Int#\ is
begin
return a - b;
end \GHC.Prim.-#\;
function \is_GHC.Types.False\ (a : \GHC.Types.Bool\) return boolean is
begin
return a = '0';
end \is_GHC.Types.False\;
function \is_GHC.Types.True\ (a : \GHC.Types.Bool\) return boolean is
begin
return a = '1';
end \is_GHC.Types.True\;
function \is_GHC.Types.I#\ (a : \GHC.Types.Int\) return boolean is
begin
return true; -- Trivial: there's only one constructor
end \is_GHC.Types.I#\;
procedure \expand_GHC.Types.I#\ (
input : in \GHC.Types.Int\;
field1 : out \Int#\) is
begin
field1 := input;
end \expand_GHC.Types.I#\;
end \Prim\;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc333.vhd
|
4
|
1810
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc333.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00333ent IS
END c03s02b01x00p06n01i00333ent;
ARCHITECTURE c03s02b01x00p06n01i00333arch OF c03s02b01x00p06n01i00333ent IS
type bit_vctor is array (1 to 8, 1 to 8) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1,8) := 56;
assert NOT(k(1,8)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00333"
severity NOTE;
assert (k(1,8)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00333 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00333arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_12.vhd
|
4
|
2544
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package fg_11_12 is
procedure init_synchronize ( signal synch : out std_logic );
procedure begin_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs );
procedure end_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs );
end package fg_11_12;
package body fg_11_12 is
-- code from book
procedure init_synchronize ( signal synch : out std_logic ) is
begin
synch <= '0';
end procedure init_synchronize;
procedure begin_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs ) is
begin
synch <= 'Z' after Tdelay;
wait until synch = 'H';
end procedure begin_synchronize;
procedure end_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs ) is
begin
synch <= '0' after Tdelay;
wait until synch = '0';
end procedure end_synchronize;
-- end code from book
end package body fg_11_12;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/comp01/and6comp.vhdl
|
1
|
418
|
library ieee;
use ieee.std_logic_1164.all;
entity and6 is
port (i0, i1, i2, i3, i4, i5 : std_logic;
o : out std_logic);
end and6;
architecture behav of and6 is
component and3 is
port (a, b, c : std_logic;
o : out std_logic);
end component;
signal t1, t2 : std_logic;
begin
a1: and3
port map (i0, i1, i2, t1);
a2: and3
port map (i3, i4, i5, t2);
o <= t1 and t2;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/dispout01/pkg_rec03.vhdl
|
2
|
190
|
library ieee;
use ieee.std_logic_1164.all;
package rec03_pkg is
type myenum is (s0, s1, s2, s3);
type myrec is record
a : myenum;
b : std_logic;
end record;
end rec03_pkg;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/exit01/tb_exit01.vhdl
|
1
|
806
|
entity tb_exit01 is
end tb_exit01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_exit01 is
signal v : std_logic_vector(3 downto 0);
signal r : integer;
begin
dut: entity work.exit01
port map (val => v, res => r);
process
begin
v <= "0001";
wait for 1 ns;
assert r = 0 severity failure;
v <= "0010";
wait for 1 ns;
assert r = 1 severity failure;
v <= "0100";
wait for 1 ns;
assert r = 2 severity failure;
v <= "1000";
wait for 1 ns;
assert r = 3 severity failure;
v <= "0000";
wait for 1 ns;
assert r = 4 severity failure;
v <= "0110";
wait for 1 ns;
assert r = 1 severity failure;
v <= "1001";
wait for 1 ns;
assert r = 0 severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue50/idct.d/sub_562.vhd
|
2
|
800
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_562 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_562;
architecture augh of sub_562 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc637.vhd
|
4
|
2028
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc637.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:50 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00637ent IS
END c03s04b01x00p01n01i00637ent;
ARCHITECTURE c03s04b01x00p01n01i00637arch OF c03s04b01x00p01n01i00637ent IS
subtype word is bit_vector(0 to 15);
type word_file is file of word;
constant C38 : word := (others => '1');
BEGIN
TESTING: PROCESS
file filein : word_file open write_mode is "iofile.41";
BEGIN
for i in 1 to 100 loop
write(filein, C38);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00637 - The output file will be verified by test s010284.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00637arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1041.vhd
|
4
|
1656
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1041.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01041ent IS
END c06s04b00x00p03n01i01041ent;
ARCHITECTURE c06s04b00x00p03n01i01041arch OF c06s04b00x00p03n01i01041ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if k(1) = 1 then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01041 - Prefix of an indexed name can only denote an array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01041arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue50/vector.d/prog.vhd
|
2
|
2944
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity prog is
port(
clock : in std_logic;
reset : in std_logic;
step : in std_logic;
instr_next : out instruction
);
end prog;
architecture rtl of prog is
signal instr_n : instruction := instr_rst;
--Table describing fsm behavior
constant fsm_behavior : table_behavior := (
--##PROGRAM_GOES_DOWN_HERE##--
0 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
1 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
2 => (state => Sig_start, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
3 => (state => Ack_data, context_uut => "01", arg => to_unsigned(2,ARG_WIDTH)),
4 => (state => Running, context_uut => "01", arg => to_unsigned(5,ARG_WIDTH)),
5 => (state => Cp_search, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
6 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
7 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
8 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
9 => (state => Sig_start, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
10 => (state => Ack_data, context_uut => "10", arg => to_unsigned(2,ARG_WIDTH)),
11 => (state => Running, context_uut => "10", arg => to_unsigned(6,ARG_WIDTH)),
12 => (state => Cp_search, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
13 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
14 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
15 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
16 => (state => Rest_ini0, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
17 => (state => Waitfor, context_uut => "01", arg => to_unsigned(1,ARG_WIDTH)),
18 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
19 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
20 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
21 => (state => Rest_ini0, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
22 => (state => Waitfor, context_uut => "10", arg => to_unsigned(1,ARG_WIDTH)),
23 => (state => Stop, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
--##PROGRAM_GOES_OVER_HERE##--
others => instr_rst);
signal pc : unsigned(PC_SIZE - 1 downto 0) := (others => '0');
begin
drive_state : process (reset,clock) is
begin
if reset = '1' then
instr_n <= instr_rst;
pc <= (others => '0');
elsif rising_edge(clock) then
if (step = '1') then
pc <= pc + 1;
end if;
instr_n <= fsm_behavior(to_integer(pc));
end if;
end process drive_state;
--instr_next <= instr_n;
instr_next <= fsm_behavior(to_integer(pc));
end rtl;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc795.vhd
|
4
|
1623
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc795.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00795ent IS
begin
generic ( constant const : boolean );
END c01s01b03x00p03n01i00795ent;
ARCHITECTURE c01s01b03x00p03n01i00795arch OF c01s01b03x00p03n01i00795ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00795 - Generic clause is not permitted as an entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00795arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc724.vhd
|
4
|
1684
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc724.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p03n01i00724ent IS
generic (( constant i : integer -- extra parenthesis
)); -- extra parenthesis
END c01s01b01x00p03n01i00724ent;
ARCHITECTURE c01s01b01x00p03n01i00724arch OF c01s01b01x00p03n01i00724ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p03n01i00724 - Extra parenthesis in generic clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p03n01i00724arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc479.vhd
|
4
|
3296
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc479.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00479ent IS
END c03s02b01x01p19n01i00479ent;
ARCHITECTURE c03s02b01x01p19n01i00479arch OF c03s02b01x01p19n01i00479ent IS
type integer_vector is array (natural range <>) of integer;
function resolution5(i:in integer_vector) return integer is
variable temp : integer := 3;
begin
return temp;
end resolution5;
subtype integer_state is resolution5 integer;
constant C66 : integer_state := 3;
function complex_scalar(s : integer_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_state;
signal S2 : integer_state;
signal S3 : integer_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00479"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00479 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00479arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2796.vhd
|
4
|
1608
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2796.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ENTITY is
end ENTITY;
ENTITY c13s09b00x00p99n01i02796ent IS
END c13s09b00x00p99n01i02796ent;
ARCHITECTURE c13s09b00x00p99n01i02796arch OF c13s09b00x00p99n01i02796ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02796 - Reserved word ENTITY can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02796arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1339.vhd
|
4
|
1775
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1339.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01339ent IS
END c08s04b01x00p04n01i01339ent;
ARCHITECTURE c08s04b01x00p04n01i01339arch OF c08s04b01x00p04n01i01339ent IS
signal X : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
X <= 15 after 10 us;
wait for 10 us;
assert NOT( X=15 )
report "***PASSED TEST: c08s04b01x00p04n01i01339"
severity NOTE;
assert ( X=15 )
report "***FAILED TEST: c08s04b01x00p04n01i01339 - Predefined TIME unit us as the base type of the time expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01339arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue418/tc749-3.vhdl
|
1
|
2667
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc749.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY tc749 IS
generic(
zero : integer := 0;
seven: integer := 7;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1
);
END tc749;
ARCHITECTURE arch OF tc749 IS
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
end record;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C51 : record_cons_array := (C19,C20,C21);
constant C86: array_rec_cons (0 to 7) :=(others => C51);
signal V49 : array_rec_cons(zero to seven) ;
BEGIN
V49 <= C86;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert V49= C86 report " error in initializing S49" severity error;
wait;
END PROCESS TESTING;
END arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd
|
4
|
3450
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity phase_locked_clock_gen is
port ( ref_clock : in std_ulogic;
phi1, phi2 : out std_ulogic );
end entity phase_locked_clock_gen;
architecture std_cell of phase_locked_clock_gen is
use work.clock_power_pkg.Tpw;
begin
phi1_gen : phi1 <= '1', '0' after Tpw when rising_edge(ref_clock);
phi2_gen : phi2 <= '1', '0' after Tpw when falling_edge(ref_clock);
end architecture std_cell;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity regulator is
port ( terminal plus_in, minus_in, plus_out, minus_out : electrical );
end entity regulator;
architecture device_level of regulator is
begin
end architecture device_level;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
entity io_controller is
port ( signal ref_clock : in std_ulogic;
terminal ext_supply, ext_ground : electrical; -- . . . );
-- not in book
other_port : in std_ulogic );
-- end not in book
end entity io_controller;
--------------------------------------------------
architecture top_level of io_controller is
-- . . .
-- not in book
signal rd, wr, sel, width, burst : std_ulogic;
signal addr : std_ulogic_vector(3 downto 0);
signal ready : std_ulogic;
signal control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
other_signal : std_ulogic;
signal analog_out_wr_0 : std_ulogic;
signal internal_data : std_ulogic_vector(7 downto 0);
terminal analog_out_0 : electrical;
-- end not in book
begin
internal_clock_gen : entity work.phase_locked_clock_gen(std_cell)
port map ( ref_clock => ref_clock,
phi1 => work.clock_power_pkg.clock_phase1,
phi2 => work.clock_power_pkg.clock_phase2 );
internal_analog_regulator : entity work.regulator(device_level)
port map ( plus_in => ext_supply, minus_in => ext_ground,
plus_out => work.clock_power_pkg.analog_plus_supply,
minus_out => work.clock_power_pkg.analog_ground );
the_bus_sequencer : entity work.bus_sequencer(fsm)
port map ( rd, wr, sel, width, burst, addr(3 downto 0), ready,
control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
analog_out_wr_0, -- . . . );
-- not in book
other_signal );
-- not in book
analog_output_interface_0 : entity work.analog_output_interface(structural)
port map ( analog_out_wr_0, internal_data(7 downto 0), analog_out_0 );
-- . . .
end architecture top_level;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2357.vhd
|
4
|
1734
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2357.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02357ent IS
END c07s02b07x00p02n02i02357ent;
ARCHITECTURE c07s02b07x00p02n02i02357arch OF c07s02b07x00p02n02i02357ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
type WORDPTR is access WORD;
variable WORDPTRV : WORDPTR;
variable INTV : INTEGER;
BEGIN
INTV := 2 ** WORDPTRV ;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02357 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02357arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue50/idct.d/add_172.vhd
|
2
|
800
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_172 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_172;
architecture augh of add_172 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc175.vhd
|
4
|
1751
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc175.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00175ent IS
END c04s03b03x01p03n02i00175ent;
ARCHITECTURE c04s03b03x01p03n02i00175arch OF c04s03b03x01p03n02i00175ent IS
signal Addr : bit;
alias SIGN1 : integer is Addr; -- Failure_here
-- error as Addr is of type bit
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c04s03b03x01p03n02i00175 - Alias base type does not match subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00175arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/sanity/002hello2008/err93.vhdl
|
1
|
167
|
entity err93 is
end err93;
architecture behav of err93 is
begin
process (all) is
begin
report "not valid in vhdl-93" severity note;
end process;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2736.vhd
|
4
|
2150
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2736.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p01n01i02736ent IS
END c13s06b00x00p01n01i02736ent;
ARCHITECTURE c13s06b00x00p01n01i02736arch OF c13s06b00x00p01n01i02736ent IS
BEGIN
TESTING: PROCESS
variable S45 : STRING (1 to 44);
variable S50 : STRING (1 to 50);
BEGIN
S45 := "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,";
S50 := "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~";
wait for 5 ns;
assert NOT( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***PASSED TEST: c13s06b00x00p01n01i02736"
severity NOTE;
assert ( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***FAILED TEST: c13s06b00x00p01n01i02736 - String literal lexical test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p01n01i02736arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/bug027/repro.vhdl
|
2
|
158
|
use work.pkg.all;
use work.all;
entity repro is
end repro;
architecture behav of repro is
component comp is
end component;
begin
c : comp;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/bug055/gen1-body.vhdl
|
2
|
97
|
package body gen1 is
function get return natural is
begin
return v;
end get;
end gen1;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_07.vhd
|
4
|
1701
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_07 is
end entity inline_07;
----------------------------------------------------------------
architecture test of inline_07 is
component multiplier is
end component multiplier;
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
type orientation_type is (up, down, left, right);
attribute cell_allocation : string;
attribute cell_position : coordinate;
attribute cell_orientation : orientation_type;
-- code from book:
attribute cell_allocation of mult : label is "wallace_tree_multiplier";
attribute cell_position of mult : label is ( 1200 um, 4500 um );
attribute cell_orientation of mult : label is down;
-- end of code from book
begin
mult : component multiplier;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc979.vhd
|
4
|
1927
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc979.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00979ent IS
END c06s03b00x00p05n01i00979ent;
ARCHITECTURE c06s03b00x00p05n01i00979arch OF c06s03b00x00p05n01i00979ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
type R2 is record
RE2: BOOLEAN;
end record;
function F1 return R1 is
begin
return (RE1=>TRUE);
end F1;
variable V1: R1 ;
variable V2: R2 ;
variable V10: BOOLEAN;
BEGIN
V10 := F1.RE2;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00979 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00979arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd
|
4
|
1571
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity negate is
end entity negate;
architecture test of negate is
subtype word32 is bit_vector(31 downto 0);
-- code in book
procedure negate ( a : inout word32 ) is
variable carry_in : bit := '1';
variable carry_out : bit;
begin
a := not a;
for index in a'reverse_range loop
carry_out := a(index) and carry_in;
a(index) := a(index) xor carry_in;
carry_in := carry_out;
end loop;
end procedure negate;
-- end code in book
begin
stimulus : process is
-- code in book (in text)
variable op1 : word32;
-- . . .
-- end code in book
begin
op1 := X"0000_0002";
-- code in book (in text)
negate ( op1 );
-- end code in book
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_04.vhd
|
4
|
2297
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_04 is
end entity fg_07_04;
architecture test of fg_07_04 is
signal phase1, phase2, reg_file_write_en,
A_reg_out_en, B_reg_out_en, C_reg_load_en : bit := '0';
begin
-- code from book
control_sequencer : process is
procedure control_write_back is
begin
wait until phase1 = '1';
reg_file_write_en <= '1';
wait until phase2 = '0';
reg_file_write_en <= '0';
end procedure control_write_back;
procedure control_arith_op is
begin
wait until phase1 = '1';
A_reg_out_en <= '1';
B_reg_out_en <= '1';
wait until phase1 = '0';
A_reg_out_en <= '0';
B_reg_out_en <= '0';
wait until phase2 = '1';
C_reg_load_en <= '1';
wait until phase2 = '0';
C_reg_load_en <= '0';
control_write_back; -- call procedure
end procedure control_arith_op;
-- . . .
begin
-- . . .
control_arith_op; -- call procedure
-- . . .
-- not in book
wait;
-- end not in book
end process control_sequencer;
-- end code from book
clock_gen : process is
begin
phase1 <= '1' after 10 ns, '0' after 20 ns;
phase2 <= '1' after 30 ns, '0' after 40 ns;
wait for 40 ns;
end process clock_gen;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc338.vhd
|
4
|
1672
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc338.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p07n01i00338ent IS
END c03s02b01x00p07n01i00338ent;
ARCHITECTURE c03s02b01x00p07n01i00338arch OF c03s02b01x00p07n01i00338ent IS
type bit_vctor is array (1 to 8, positive range <>) of integer;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p07n01i00338 - The discrete range is neither a valid discrete subtype indication nor a valid range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p07n01i00338arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc881.vhd
|
4
|
3150
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc881.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s01b00x00p06n01i00881PKG is
-- VAL1 is here a constant
constant VAL1 : INTEGER := 65;
type DBLINTREC is
record
-- VAL1 is here a record element
VAL1 : INTEGER;
VAL2 : INTEGER;
end record;
end c10s01b00x00p06n01i00881PKG;
use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC;
entity c10s01b00x00p06n01i00881ent_a is
port (
PS1: in DBLINTREC;
PS2: out DBLINTREC
);
end c10s01b00x00p06n01i00881ent_a;
architecture c10s01b00x00p06n01i00881arch_a of c10s01b00x00p06n01i00881ent_a is
begin
process
begin
PS2.VAL1 <= PS1.VAL1 + 1;
PS2.VAL2 <= PS1.VAL2 + 2;
wait;
end process;
end c10s01b00x00p06n01i00881arch_a;
use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC;
use WORK.c10s01b00x00p06n01i00881ent_a;
ENTITY c10s01b00x00p06n01i00881ent IS
END c10s01b00x00p06n01i00881ent;
ARCHITECTURE c10s01b00x00p06n01i00881arch OF c10s01b00x00p06n01i00881ent IS
component c10s01b00x00p06n01i00881ent_a
port ( PS1: in DBLINTREC; PS2: out DBLINTREC );
end component;
for A1: c10s01b00x00p06n01i00881ent_a
use entity work.c10s01b00x00p06n01i00881ent_a ( c10s01b00x00p06n01i00881arch_a );
signal S1: DBLINTREC := (3, 9);
signal S2: DBLINTREC := (0, 0);
BEGIN
A1: c10s01b00x00p06n01i00881ent_a port map ( S1, S2 );
TESTING: PROCESS
BEGIN
wait for 1 ns; -- let a time increment go by so init done
assert ( S2.VAL1 = 4 )
report "didn't add to record element S2.VAL1 correctly"
severity FAILURE;
assert ( S2.VAL2 = 11 )
report "didn't add to record element S2.VAL2 correctly"
severity FAILURE;
assert NOT( S2.VAL1 = 4 and S2.VAL2 =11 )
report "***PASSED TEST: c10s01b00x00p06n01i00881"
severity NOTE;
assert ( S2.VAL1 = 4 and S2.VAL2 =11 )
report "***FAILED TEST: c10s01b00x00p06n01i00881 - A declaratione region is formed by a record type declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p06n01i00881arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2697.vhd
|
4
|
1813
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2697.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p05n01i02697ent IS
END c13s04b01x00p05n01i02697ent;
ARCHITECTURE c13s04b01x00p05n01i02697arch OF c13s04b01x00p05n01i02697ent IS
constant a : real := 2.34;
constant b : real := 2.3_4;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a=b )
report "***PASSED TEST: c13s04b01x00p05n01i02697"
severity NOTE;
assert ( a=b )
report "***FAILED TEST: c13s04b01x00p05n01i02697 - The underline character inserted between adjacent digits of a real literal should not affect the value of this abstract literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p05n01i02697arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc476.vhd
|
4
|
3394
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc476.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00476ent IS
END c03s02b01x01p19n01i00476ent;
ARCHITECTURE c03s02b01x01p19n01i00476arch OF c03s02b01x01p19n01i00476ent IS
type severity_level_vector is array (natural range <>) of severity_level;
function resolution2(i:in severity_level_vector) return severity_level is
variable temp : severity_level := note;
begin
return temp;
end resolution2;
subtype severity_level_state is resolution2 severity_level;
constant C66 : severity_level_state := note;
function complex_scalar(s : severity_level_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return severity_level_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : severity_level_state;
signal S2 : severity_level_state;
signal S3 : severity_level_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00476"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00476 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00476arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc316.vhd
|
4
|
1725
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc316.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b00x00p03n02i00316ent IS
END c03s02b00x00p03n02i00316ent;
ARCHITECTURE c03s02b00x00p03n02i00316arch OF c03s02b00x00p03n02i00316ent IS
type FT is file of integer;
type rec_type is
record
x : bit;
y : integer;
z : FT; -- Failure_here
end record;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b00x00p03n02i00316 - Elements of file types are not allowed in a composite type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b00x00p03n02i00316arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/func02/tb_func01.vhdl
|
1
|
494
|
entity tb_func01 is
end tb_func01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func01 is
signal a, b : std_logic_vector(7 downto 0);
begin
dut: entity work.func01
port map (a, b);
process
begin
a <= x"5d";
wait for 1 ns;
assert b = x"1d" severity failure;
a <= x"ff";
wait for 1 ns;
assert b = x"3f" severity failure;
a <= x"c0";
wait for 1 ns;
assert b = x"00" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc248.vhd
|
4
|
1704
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc248.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00248ent IS
END c03s01b02x00p04n01i00248ent;
ARCHITECTURE c03s01b02x00p04n01i00248arch OF c03s01b02x00p04n01i00248ent IS
type I4 is range "000" to "999"; -- Failure_here
-- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
-- MUST BE OF INTEGER TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00248 - Range constraint must be an integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00248arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd
|
4
|
1318
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee_proposed.mechanical_systems.all;
entity inline_24a is
end entity inline_24a;
architecture test of inline_24a is
-- code from book
terminal plus, minus : electrical;
quantity v across i through plus to minus;
terminal shaft : rotational_v;
quantity applied_torque through shaft;
-- end code from book
begin
-- code from book
applied_torque == v * i;
-- end code from book
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/bug042/centerconfig_works.vhdl
|
2
|
2253
|
library ieee;
use ieee.std_logic_1164.all;
entity CenterConfig is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
center_height: out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
center_width: out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0)
);
end entity CenterConfig;
architecture foo of centerconfig is
begin
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity instance is
-- generic (
-- CENTERHEIGHT: integer := 16;
-- CENTERWIDTH: integer := 16
-- );
end entity;
architecture fum of instance is
constant CENTERHEIGHT: integer := 32; -- 16;
constant CENTERWIDTH: integer := 32; -- 16;
constant C_S_AXI_DATA_WIDTH: integer := 32;
constant C_S_AXI_ADDR_WIDTH: integer := 4;
component centerconfig is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
center_height:
out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
center_width:
out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0)
);
end component;
signal std_center_height: std_logic_vector (CENTERHEIGHT - 1 downto 0);
signal std_center_width: std_logic_vector (CENTERWIDTH - 1 downto 0);
begin
Config:
CenterConfig
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
--center_height(std_center_height'range) => std_center_height,
center_height(std_center_height'LEFT downto
std_center_height'RIGHT) => std_center_height,
-- center_height(C_S_AXI_DATA_WIDTH-1 downto std_center_height'length) => open,
-- not working, not elegant
-- center_width(std_center_width'range) => std_center_width
center_width(std_center_width'LEFT downto
std_center_width'RIGHT) => std_center_width
);
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue1246/pkg_a.vhdl
|
1
|
469
|
package pkg_A is
--------------------------------------
generic (
A: integer := 1
);
--------------------------------------
-- constant A: integer := 1;
--------------------------------------
package pkgB is new work.pkg_B
generic map(
B => A+1
);
procedure showA;
end pkg_A;
package body pkg_A is
procedure showA is
use pkgB.showB;
begin
report "A:" & integer'image(A);
showB;
end procedure showA;
end package body pkg_A;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2490.vhd
|
4
|
1980
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2490.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n01i02490ent IS
END c07s03b03x00p04n01i02490ent;
ARCHITECTURE c07s03b03x00p04n01i02490arch OF c07s03b03x00p04n01i02490ent IS
BEGIN
TESTING: PROCESS
function check (x:integer; y:boolean; z:real) return boolean is
begin
if y then
return true;
end if;
return false;
end;
variable p : integer := 3;
variable q : boolean := true;
variable s : boolean;
variable r : real;
variable r1: real;
BEGIN
s := check (p, q, r, r1); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s03b03x00p04n01i02490 - Each formal parameter of a function should have exactly one actual parameter associated with it in a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n01i02490arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1398.vhd
|
4
|
1689
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1398.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY ch0805_p00601_04_03_ent IS
END ch0805_p00601_04_03_ent;
ARCHITECTURE ch0805_p00601_04_03_arch OF ch0805_p00601_04_03_ent IS
BEGIN
TESTING: PROCESS
subtype a is integer range 1 to 10;
variable k : integer := 5;
BEGIN
a := k;
assert FALSE
report "***FAILED TEST: c08s05b00x00p06n01i01398 - If the target of a variable assignment statement is a name, then the name must denote a variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p06n01i01398arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue50/vector.d/cmp_191.vhd
|
2
|
376
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_191 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_191;
architecture augh of cmp_191 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1963.vhd
|
4
|
1773
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1963.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01963ent IS
END c07s02b01x00p02n02i01963ent;
ARCHITECTURE c07s02b01x00p02n02i01963arch OF c07s02b01x00p02n02i01963ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := FALSE;
variable b : boolean := FALSE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=FALSE)
report "***PASSED TEST: c07s02b01x00p02n02i01963"
severity NOTE;
assert ( c=FALSE )
report "***FAILED TEST: c07s02b01x00p02n02i01963 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01963arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd
|
4
|
1305
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
----------------------------------------------------------------
architecture test_behavior of tb_counter is
signal clk : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, count => count );
stimulus : process is
begin
for cycle_count in 1 to 100 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_behavior;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/issue1330/test3.vhdl
|
1
|
477
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test3 is
port(
clk : in std_logic;
write_data : in std_ulogic;
arst : std_ulogic
);
end;
architecture rtl of test3 is
begin
test_1: process(clk, arst)
begin
if arst = '1' then
null;
elsif rising_edge(clk) then
assert write_data = '0' report "bad" severity failure;
end if;
end process test_1;
end architecture rtl;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/simple-write.vhdl
|
3
|
1548
|
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity simple_write is
end simple_write;
use std.textio.all;
architecture only of simple_write is
type integer_file is file of integer;
begin -- only
doit: process
file infile : integer_file open write_mode is "simple.file";
variable v : integer;
begin -- process
write( infile, 1 );
write( infile, 2 );
write( infile, 3 );
write( infile, 4 );
report "PASSED"
severity NOTE;
wait;
end process;
end only;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-integer-initialize.vhdl
|
8
|
301
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
assert x = 0 report "TEST FAILED - x does not equal 1" severity failure;
report "TEST PASSED" severity note;
wait;
end process;
end only;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2305.vhd
|
4
|
1981
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2305.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p37n01i02305ent IS
END c07s02b06x00p37n01i02305ent;
ARCHITECTURE c07s02b06x00p37n01i02305arch OF c07s02b06x00p37n01i02305ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test dividing the predefined type TIME.
assert ((1 hr / 1 min) = 60);
assert ((1 min / 1 sec) = 60);
wait for 5 sec;
assert NOT( ((1 hr / 1 min) = 60) and
((1 min / 1 sec) = 60) )
report "***PASSED TEST: c07s02b06x00p37n01i02305"
severity NOTE;
assert ( ((1 hr / 1 min) = 60) and
((1 min / 1 sec) = 60) )
report "***FAILED TEST: c07s02b06x00p37n01i02305 - Division of a physical type by another physical type (predefined TIME) test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p37n01i02305arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2953.vhd
|
4
|
1735
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2953.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p24n01i02953ent IS
END c02s02b00x00p24n01i02953ent;
ARCHITECTURE c02s02b00x00p24n01i02953arch OF c02s02b00x00p24n01i02953ent IS
BEGIN
TESTING: PROCESS
variable a1 : integer := func1 (1); --Failure_here
function func1 (x: in integer) return integer is
begin
return 12;
end;
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p24n01i02953 - Subprogram declaration should appear before call of subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p24n01i02953arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3165.vhd
|
4
|
2123
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3165.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p12n01i03165ent IS
END c14s01b00x00p12n01i03165ent;
ARCHITECTURE c14s01b00x00p12n01i03165arch OF c14s01b00x00p12n01i03165ent IS
subtype abc is real range 0.0 to 20.0;
subtype cba is real range 20.0 downto 0.0;
subtype xyz is real range 20.0 to 0.0;
subtype zyx is real range 0.0 downto 20.0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***PASSED TEST: c14s01b00x00p12n01i03165"
severity NOTE;
assert ( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***FAILED TEST: c14s01b00x00p12n01i03165 - Predefined attribute LEFT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p12n01i03165arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/synth109/ram2.vhdl
|
1
|
1465
|
library ieee;
use ieee.std_logic_1164.all;
entity ram2 is
generic (
WIDTH : integer := 32;
SIZE : integer := 64;
ADDRWIDTH : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end ram2;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
architecture behavioral of ram2 is
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
doA <= ram(conv_integer(addrA));
end if;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
doB <= ram(conv_integer(addrB));
end if;
end if;
end process;
end behavioral;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2150.vhd
|
4
|
2222
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2150.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02150ent IS
END c07s02b04x00p21n01i02150ent;
ARCHITECTURE c07s02b04x00p21n01i02150arch OF c07s02b04x00p21n01i02150ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_5 is real_v (1 to 5);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : real_5;
variable l_operand : real_4 := ( 12.34, 56.78, 12.34, 56.78 );
variable r_operand : real := 12.34;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (12.34, 56.78, 12.34, 56.78, 12.34)) and (result(1) = 12.34))
report "***PASSED TEST: c07s02b04x00p21n01i02150"
severity NOTE;
assert ((result = (12.34, 56.78, 12.34, 56.78, 12.34)) and (result(1) = 12.34))
report "***FAILED TEST: c07s02b04x00p21n01i02150 - Concatenation of element and REAL array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02150arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc470.vhd
|
4
|
3399
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc470.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00470ent IS
END c03s02b01x01p19n01i00470ent;
ARCHITECTURE c03s02b01x01p19n01i00470arch OF c03s02b01x01p19n01i00470ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type positive_vector is array (natural range <>) of positive;
subtype positive_vector_range is positive_vector(hi_to_low_range);
constant C66: positive_vector_range := (others => 1);
function complex_scalar(s : positive_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return positive_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : positive_vector_range;
signal S2 : positive_vector_range;
signal S3 : positive_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00470"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00470 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00470arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_17.vhd
|
4
|
1215
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_17 is
end entity inline_17;
----------------------------------------------------------------
architecture test of inline_17 is
begin
process_4_f : process is
begin
-- code from book:
for i in 10 to 1 loop
-- . . .
end loop;
for i in 10 downto 1 loop
-- . . .
end loop;
-- end of code from book
wait;
end process process_4_f;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1032.vhd
|
4
|
2198
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1032.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01032ent IS
END c06s04b00x00p02n01i01032ent;
ARCHITECTURE c06s04b00x00p02n01i01032arch OF c06s04b00x00p02n01i01032ent IS
BEGIN
TESTING: PROCESS
type TWO is range 1 to 2;
type A0 is array (TWO) of BOOLEAN;
type A1 is array (TWO) of A0;
type A2 is array (TWO) of A1;
type A3 is array (TWO) of A2;
type A4 is array (TWO) of A3;
type A5 is array (TWO) of A4;
type A6 is array (TWO) of A5;
type A7 is array (TWO) of A6;
type A8 is array (TWO) of A7;
type A9 is array (TWO) of A8;
variable V1: A9;
BEGIN
V1(1)(2)(1)(2)(1)(2)(1)(2)(1)(2) := TRUE;
assert NOT(V1(1)(2)(1)(2)(1)(2)(1)(2)(1)(2) = TRUE)
report "***PASSED TEST: c06s04b00x00p02n01i01032"
severity NOTE;
assert (V1(1)(2)(1)(2)(1)(2)(1)(2)(1)(2) = TRUE)
report "***FAILED TEST: c06s04b00x00p02n01i01032 - The prefix of an indexed name can be a indexed name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01032arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue301/src/axi4s_buffer.vhd
|
7
|
3625
|
--!
--! Copyright (C) 2012 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief AXI4-Stream buffer that allows to buffer the accept-signal.
--! @author Matthias Alles
--! @date 2012/04/18
--!
--! @details
--! One problem when concatenating multiple AXI4-Stream builind blocks is that
--! the accept signal has to pass from the very last component to the input
--! of the very first component. Only then it is possible to have an interruption
--! free data processing within the whole chain. The drawback of this approach is
--! that the accept signal has a long path and high fanouts.
--! This entity allows to use registers on the accept signals by introducing buffers
--! for storing the input values. It should improve timing of bigger building blocks.
--!
library ieee;
use ieee.std_logic_1164.all;
entity axi4s_buffer is
generic (
DATA_WIDTH : natural := 1
);
port (
clk : in std_logic;
rst : in std_logic;
-- Input data handling
----------------------
input : in std_logic_vector(DATA_WIDTH - 1 downto 0);
input_valid : in std_logic;
input_last : in std_logic;
input_accept : out std_logic;
-- Output data handling
-----------------------
output : out std_logic_vector(DATA_WIDTH - 1 downto 0);
output_valid : out std_logic;
output_last : out std_logic;
output_accept : in std_logic
);
end entity axi4s_buffer;
architecture rtl of axi4s_buffer is
signal input_accept_int : std_logic;
signal output_reg : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal output_last_reg : std_logic;
signal output_valid_reg : std_logic;
signal buffer_full : std_logic;
signal buffer_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal buffer_last : std_logic;
begin
input_accept <= input_accept_int;
output <= output_reg;
output_last <= output_last_reg;
output_valid <= output_valid_reg;
--
-- This process registers all signals.
-- No combinatorial logic is bypassed from input to output and vice versa.
--
pr_reg: process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
output_reg <= (others => '0');
output_last_reg <= '0';
output_valid_reg <= '0';
input_accept_int <= '1';
buffer_full <= '0';
buffer_data <= (others => '0');
buffer_last <= '0';
else
--
-- Data is coming, buf output data can't be sent => Store input data in buffer
-- and remove input_accept signal!
--
if input_valid = '1' and input_accept_int = '1' and output_valid_reg = '1' and output_accept = '0' then
buffer_data <= input;
buffer_last <= input_last;
buffer_full <= '1';
input_accept_int <= '0';
end if;
--
-- Output data is being read but there is data in the buffer waiting for being sent
-- => Use the buffer data!
--
if output_accept = '1' and output_valid_reg = '1' and buffer_full = '1' then
output_reg <= buffer_data;
output_last_reg <= buffer_last;
output_valid_reg <= '1';
buffer_full <= '0';
input_accept_int <= '1';
--
-- Data is being read and buffer is empty => Use input data directly!
-- Output register is empty => Use input data directly!
--
elsif (output_accept = '1' and output_valid_reg = '1') or output_valid_reg = '0' then
output_reg <= input;
output_last_reg <= input_last;
output_valid_reg <= input_valid;
end if;
end if;
end if;
end process pr_reg;
end architecture rtl;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_11.vhd
|
4
|
1800
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_11.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_05_11 is
end entity ch_05_11;
----------------------------------------------------------------
architecture test of ch_05_11 is
signal line_in, line_out : bit := '0';
begin
-- code from book:
transmission_line : process (line_in) is
begin
line_out <= transport line_in after 500 ps;
end process transmission_line;
-- end of code from book
----------------
stimulus : process is
begin
line_in <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps,
'1' after 8000 ps,
'0' after 8200 ps,
'1' after 8300 ps,
'0' after 8400 ps;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1014.vhd
|
4
|
1769
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1014.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01014ent IS
END c06s03b00x00p10n01i01014ent;
ARCHITECTURE c06s03b00x00p10n01i01014arch OF c06s03b00x00p10n01i01014ent IS
signal p : bit := '0';
signal q : bit := '1';
BEGIN
TESTING: PROCESS(c06s03b00x00p10n01i01014arch.p,c06s03b00x00p10n01i01014ent.q)
BEGIN
c06s03b00x00p10n01i01014ent.q <= c06s03b00x00p10n01i01014arch.p;
assert FALSE
report "***FAILED TEST: c06s03b00x00p10n01i01014 - Declaration of suffix must occur within the construct denoted by the prefix."
severity ERROR;
END PROCESS TESTING;
END c06s03b00x00p10n01i01014arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2678.vhd
|
4
|
1788
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2678.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p05n02i02678ent IS
END c13s03b01x00p05n02i02678ent;
ARCHITECTURE c13s03b01x00p05n02i02678arch OF c13s03b01x00p05n02i02678ent IS
constant UPPER_CASE : integer := 27;
-- ERROR: double declaration due to case insensitivity;
signal upper_case:integer; -- failure_here.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p05n02i02678 - Identifiers differing only in the use of corresponding upper and lower case letters are considered as the same."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p05n02i02678arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/bug057/tb.vhdl
|
2
|
293
|
package pkg1 is
generic (c : natural);
generic map (c => 5);
function f return natural;
end pkg1;
package body pkg1 is
function f return natural is
begin
return c;
end f;
end pkg1;
entity tb is
end tb;
architecture behav of tb is
begin
assert work.pkg1.f = 5;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_limit_checker.vhd
|
4
|
1564
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
use work.project_util.all;
entity tb_limit_checker is
end entity tb_limit_checker;
architecture test of tb_limit_checker is
signal input : word;
signal out_of_bounds : std_logic;
begin
dut : entity work.limit_checker(behavioral)
port map ( input => input,
lower_bound => X"FFFFFFF0", upper_bound => X"00000010",
out_of_bounds => out_of_bounds );
stimulus : input <= X"00000000",
X"00000008" after 10 ns,
X"00000010" after 20 ns,
X"00000018" after 30 ns,
X"FFFFFFF8" after 40 ns,
X"FFFFFFF0" after 50 ns,
X"FFFFFF00" after 60 ns;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_01.vhd
|
4
|
5648
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity D_flipflop is
port ( clk : in std_logic; d : in std_logic;
q : out std_logic );
end entity D_flipflop;
architecture synthesized of D_flipflop is
begin
q <= d when not clk'stable and (To_X01(clk) = '1') and
(To_X01(clk'last_value) = '0');
end architecture synthesized;
library ieee; use ieee.std_logic_1164.all;
entity tristate_buffer is
port ( a : in std_logic;
en : in std_logic;
y : out std_logic );
end entity tristate_buffer;
architecture synthesized of tristate_buffer is
begin
y <= 'X' when is_X(en) else
a when To_X01(en) = '1' else
'Z';
end architecture synthesized;
-- code from book (in Figure 14-1)
library ieee; use ieee.std_logic_1164.all;
entity register_tristate is
generic ( width : positive );
port ( clock : in std_logic;
out_enable : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity register_tristate;
--------------------------------------------------
architecture cell_level of register_tristate is
component D_flipflop is
port ( clk : in std_logic; d : in std_logic;
q : out std_logic );
end component D_flipflop;
component tristate_buffer is
port ( a : in std_logic;
en : in std_logic;
y : out std_logic );
end component tristate_buffer;
begin
cell_array : for bit_index in 0 to width - 1 generate
signal data_unbuffered : std_logic;
begin
cell_storage : component D_flipflop
port map ( clk => clock, d => data_in(bit_index),
q => data_unbuffered );
cell_buffer : component tristate_buffer
port map ( a => data_unbuffered, en => out_enable,
y => data_out(bit_index) );
end generate cell_array;
end architecture cell_level;
-- end code from book (in Figure 14-1)
-- code from book (in Figure 14-11)
library cell_lib;
configuration identical_cells of register_tristate is
for cell_level
for cell_array
for cell_storage : D_flipflop
use entity cell_lib.D_flipflop(synthesized);
end for;
for cell_buffer : tristate_buffer
use entity cell_lib.tristate_buffer(synthesized);
end for;
end for;
end for;
end configuration identical_cells;
-- code from book (in Figure 14-11)
library ieee; use ieee.std_logic_1164.all;
entity fg_14_01 is
end entity fg_14_01;
architecture test of fg_14_01 is
signal clk, en : std_logic;
signal d_in, d_out : std_logic_vector(0 to 3);
begin
dut : configuration work.identical_cells
generic map ( width => d_in'length )
port map ( clock => clk, out_enable => en,
data_in => d_in, data_out => d_out );
stimulus : process is
begin
wait for 10 ns;
d_in <= "0000"; en <= '0'; clk <= '0'; wait for 10 ns;
clk <= '1', '0' after 5 ns; wait for 10 ns;
en <= '1', '0' after 5 ns; wait for 10 ns;
d_in <= "0101"; wait for 10 ns;
clk <= '1', '0' after 5 ns; wait for 10 ns;
en <= 'H', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
-- end not in book
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_11.vhd
|
4
|
1495
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_11.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_11 is
end entity ch_03_11;
architecture test of ch_03_11 is
signal sensitivity_list : bit := '0';
begin
-- code from book:
-- make "sensitivity_list" roman italic
control_section : process ( sensitivity_list ) is
begin
null;
end process control_section;
-- end of code from book
stimulus : process is
begin
sensitivity_list <= '1' after 10 ns, '0' after 20 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2606.vhd
|
4
|
1587
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2606.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02606ent IS
END c13s03b01x00p02n01i02606ent;
ARCHITECTURE c13s03b01x00p02n01i02606arch OF c13s03b01x00p02n01i02606ent IS
BEGIN
TESTING: PROCESS
variable k> : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02606 - Identifier can not end with '>'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02606arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3144.vhd
|
4
|
2318
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3144.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p10n01i03144ent_a IS
generic ( g1 : real := 22.0 );
END c05s02b02x00p10n01i03144ent_a;
ARCHITECTURE c05s02b02x00p10n01i03144arch_a OF c05s02b02x00p10n01i03144ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( g1 = 22.0 )
report "***PASSED TEST: c05s02b02x00p10n01i03144"
severity NOTE;
assert ( g1 = 22.0 )
report "***FAILED TEST: c05s02b02x00p10n01i03144 - The formal generics take on implicit OPENs."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p10n01i03144arch_a;
--
ENTITY c05s02b02x00p10n01i03144ent IS
END c05s02b02x00p10n01i03144ent;
ARCHITECTURE c05s02b02x00p10n01i03144arch OF c05s02b02x00p10n01i03144ent IS
component c05s02b02x00p10n01i03144ent_a
end component;
for comp1 : c05s02b02x00p10n01i03144ent_a use entity work.c05s02b02x00p10n01i03144ent_a(c05s02b02x00p10n01i03144arch_a)
generic map(OPEN);
BEGIN
comp1 : c05s02b02x00p10n01i03144ent_a;
END c05s02b02x00p10n01i03144arch;
configuration c05s02b02x00p10n01i03144cfg of c05s02b02x00p10n01i03144ent is
for c05s02b02x00p10n01i03144arch
end for;
end c05s02b02x00p10n01i03144cfg;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1490.vhd
|
4
|
1754
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1490.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p05n01i01490ent IS
END c08s08b00x00p05n01i01490ent;
ARCHITECTURE c08s08b00x00p05n01i01490arch OF c08s08b00x00p05n01i01490ent IS
BEGIN
TESTING: PROCESS
type x is (Jan,Feb,Mar,Apr);
variable y:x;
BEGIN
case y is
when Jan => NULL;
when Feb => NULL;
when Mar => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p05n01i01490 - the choice OTHERS must be present when all alternatives are not covered "
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p05n01i01490arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue560/reproducer.vhdl
|
1
|
1191
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reproducer_pkg is
-- Functions
function MIN(LEFT, RIGHT: unsigned) return unsigned;
function MIN(LEFT, RIGHT: integer) return integer;
end reproducer_pkg;
package body reproducer_pkg is
function MIN(LEFT, RIGHT: unsigned) return unsigned is
begin
if LEFT < RIGHT then
return LEFT;
else
return RIGHT;
end if;
end;
function MIN(LEFT, RIGHT: integer) return integer is
begin
if LEFT < RIGHT then
return LEFT;
else
return RIGHT;
end if;
end;
end reproducer_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reproducer_pkg.all;
entity reproducer is
port(
inputA : in unsigned(7 downto 0);
inputB : in unsigned(7 downto 0);
inputC : in integer;
inputD : in integer;
OutputA : out unsigned(7 downto 0);
OutputB : out integer
);
end reproducer;
architecture rtl of reproducer is
begin
OutputA <= min(inputA, inputB);
OutputB <= min(inputC, inputD);
end rtl;
|
gpl-2.0
|
tgingold/ghdl
|
libraries/ieee2008/fixed_pkg.vhdl
|
2
|
2249
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
--
-- Title : Fixed-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
);
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/dff01/tb_dff05.vhdl
|
1
|
1076
|
entity tb_dff05 is
end tb_dff05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff05 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
signal en : std_logic;
begin
dut: entity work.dff05
port map (
q => dout,
d => din,
clk => clk,
rst => rst,
en => en);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
en <= '1';
wait for 1 ns;
assert dout = x"00" severity failure;
rst <= '0';
din <= x"7e";
pulse;
assert dout = x"7e" severity failure;
din <= x"38";
en <= '0';
pulse;
assert dout = x"7e" severity failure;
en <= '1';
pulse;
assert dout = x"38" severity failure;
din <= x"27";
pulse;
assert dout = x"27" severity failure;
rst <= '1';
wait for 1 ns;
assert dout = x"00" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3112.vhd
|
4
|
2525
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3112.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b00x00p06n01i03112ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b00x00p06n01i03112ent_a;
ARCHITECTURE c05s02b00x00p06n01i03112arch_a OF c05s02b00x00p06n01i03112ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b00x00p06n01i03112arch_a;
ENTITY c05s02b00x00p06n01i03112ent IS
END c05s02b00x00p06n01i03112ent;
ARCHITECTURE c05s02b00x00p06n01i03112arch OF c05s02b00x00p06n01i03112ent IS
signal s1 : Bit := '0';
signal s2 : Bit := '1';
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
BEGIN
u1 : virtual generic map ( true ) port map (s1, s2);
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert NOT( s2 = s1 )
report "***PASSED TEST: c05s02b00x00p06n01i03112"
severity NOTE;
assert ( s2 = s1 )
report "***FAILED TEST: c05s02b00x00p06n01i03112 - Component instance configuration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b00x00p06n01i03112arch;
configuration c05s02b00x00p06n01i03112cfg of c05s02b00x00p06n01i03112ent is
for c05s02b00x00p06n01i03112arch
for u1 : virtual use entity work.c05s02b00x00p06n01i03112ent_a (c05s02b00x00p06n01i03112arch_a);
end for;
end for;
end c05s02b00x00p06n01i03112cfg;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/issue1074/blinky.vhdl
|
1
|
822
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity blinky is
port (
clk : in std_logic;
led : out std_logic
);
end blinky;
architecture rtl of blinky is
constant max_count : natural := 48000000;
signal rst : std_logic;
begin
rst <= '0';
-- 0 to max_count counter
counter : process(clk, Rst)
variable count : natural range 0 to max_count;
begin
if rising_edge(clk) then
if count < max_count/2 then
count := count + 1;
led <= '1';
elsif count < max_count then
led <= '0';
count := count + 1;
else
led <= '1';
count := 0;
end if;
elsif rst = '1' then
count := 0;
led <= '1';
end if;
end process counter;
end rtl;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/bug04/test.vhdl
|
3
|
1424
|
library ieee;
use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.is_x;
package std_logic_warning is
function EQ_BUT_NOT_META(l, r : std_logic) return boolean;
end package;
package body std_logic_warning is
use ieee.std_logic_1164."=";
function EQ_BUT_NOT_META(l, r : std_logic) return boolean is
begin
if is_x(l) or is_x(r) then
report "std_logic_warning.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return l = r; -- std_logic_1164."="(l, r);
end function;
end package body;
library ieee;
use ieee.std_logic_1164.std_ulogic;
use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.all;
use work.std_logic_warning.all;
entity warning_test is
end entity;
architecture foo of warning_test is
signal a: std_logic;
signal b: std_logic;
begin
UNLABELLED:
process
begin
wait for 1 ns;
a <= 'X';
wait for 1 ns;
b <= '1';
wait for 1 ns;
a <= '0';
wait for 1 ns;
b <= '0';
wait;
end process;
MONITOR:
process (a,b)
begin
assert EQ_BUT_NOT_META(a,b) = TRUE
report "a = b " & "( " & std_logic'image(a)
& "=" & std_logic'image(b) & " )"
severity NOTE;
end process;
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue441/e.vhdl
|
1
|
222
|
entity e is end entity;
architecture a of e is
component c is
generic(constant k :natural := 0);
port (signal s :bit_vector(k to k));
end component;
begin
inst: c port map(s(k) => '0');
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd
|
4
|
2107
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_06a is
end entity inline_06a;
architecture test of inline_06a is
-- code from book
terminal a_bus : electrical_vector(1 to 8);
terminal b_bus : electrical_vector(8 downto 1);
--
quantity a_to_b_drops across a_to_b_currents through a_bus to b_bus;
--
nature electrical_bus is
record
strobe: electrical;
databus : electrical_vector(0 to 7);
end record;
terminal t1, t2 : electrical_bus;
--
quantity bus_voltages across t1 to t2;
--
terminal p1, p2 : electrical_vector(0 to 3);
quantity v across i through p1 to p2;
-- end code from book
begin
block_1 : block is
terminal anode, cathode : electrical;
-- code from book
quantity battery_voltage tolerance "battery_tolerance" across
battery_current tolerance "battery_tolerance" through anode to cathode;
-- end code from book
begin
end block block_1;
block_2 : block is
terminal anode, cathode : electrical;
-- code from book
quantity battery_volts := 5.0 across
battery_amps := 0.0 through
anode to cathode;
-- end code from book
begin
end block block_2;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_12.vhd
|
4
|
2726
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
begin
process_4_a : process is
constant condition, condition_1,
condition_2, condition_3 : boolean := true;
variable index : integer;
begin
-- code from book: syntax check only
-- change "condition" to roman italic
-- not in book:
loop
-- end not in book
if condition then
exit;
end if;
-- not in book:
end loop;
-- end not in book
--
-- change "condition" to roman italic
loop
-- . . .
exit when condition;
-- . . .
end loop;
-- . . . -- control transferred to here
-- when condition becomes true within the loop
--
loop_name : loop
-- . . .
exit loop_name;
-- . . .
end loop loop_name ;
--
-- change conditions to roman italic with hyphens
outer : loop
-- . . .
inner : loop
-- . . .
exit outer when condition_1; -- exit 1
-- . . .
exit when condition_2; -- exit 2
-- . . .
end loop inner;
-- . . . -- target A
exit outer when condition_3; -- exit 3
-- . . .
end loop outer;
-- . . . -- target B
--
-- "statement..." in roman italic with hyphens
loop
-- statement_1;
next when condition;
-- statement_2;
end loop;
--
-- "statement..." in roman italic with hyphens
loop
-- statement_1;
if not condition then
-- statement_2;
end if;
end loop;
--
while index > 0 loop
-- . . . -- statement A: do something with index
end loop;
-- . . . -- statement B
-- end of code from book
wait;
end process process_4_a;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd
|
4
|
1609
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library project_lib;
library util; use util.stimulus_generators.all;
entity misc_logic is
end entity misc_logic;
-- code from book
architecture gate_level of misc_logic is
component nand3 is
generic ( Tpd : delay_length );
port ( a, b, c : in bit; y : out bit );
end component nand3;
for all : nand3
use entity project_lib.nand3(basic);
-- . . .
-- not in book
signal sig1, sig2, sig3, out_sig : bit;
signal test_vector : bit_vector(1 to 3);
-- end not in book
begin
gate1 : component nand3
generic map ( Tpd => 2 ns )
port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
-- . . .
-- not in book
all_possible_values(test_vector, 10 ns);
(sig1, sig2, sig3) <= test_vector;
-- end not in book
end architecture gate_level;
-- end code from book
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_25.vhd
|
4
|
1549
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_25.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity reg4 is
port ( clk, clr, d0, d1, d2, d3 : in bit;
q0, q1, q2, q3 : out bit );
end entity reg4;
architecture struct of reg4 is
begin
bit0 : entity work.edge_triggered_Dff(behavioral)
port map (d0, clk, clr, q0);
bit1 : entity work.edge_triggered_Dff(behavioral)
port map (d1, clk, clr, q1);
bit2 : entity work.edge_triggered_Dff(behavioral)
port map (d2, clk, clr, q2);
bit3 : entity work.edge_triggered_Dff(behavioral)
port map (d3, clk, clr, q3);
end architecture struct;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1132.vhd
|
4
|
2117
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1132.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01132ent IS
END c06s05b00x00p04n01i01132ent;
ARCHITECTURE c06s05b00x00p04n01i01132arch OF c06s05b00x00p04n01i01132ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5);
type ENUM2 is (N1, N2, N3, N4, N5);
type FIVE1 is range 1 to 5;
type FIVE2 is range 1 to 5;
type A1B is array (ENUM1 range <>) of BOOLEAN;
subtype A1 is A1B(ENUM1);
type A2B is array (ENUM2 range <>) of A1;
subtype A2 is A2B(ENUM2);
variable V1: A1 ;
variable V2: A2 ;
constant FIVE2_2: FIVE2 := 2;
constant FIVE2_4: FIVE2 := 4;
BEGIN
V2(N3)(M2 to M4) := V2(N3)(N1 to N2);
-- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01132 - Discrete range incompatible with index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01132arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3203.vhd
|
4
|
2916
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3203.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.textio.all;
ENTITY c14s03b00x00p56n01i03203ent IS
END c14s03b00x00p56n01i03203ent;
ARCHITECTURE c14s03b00x00p56n01i03203arch OF c14s03b00x00p56n01i03203ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.61";
variable L : LINE;
variable BV : Bit_Vector(1 to 60);
BEGIN
-- Write an arbitrary line...
L := new STRING'("hello world");
WRITELINE(F, L);
-- Write a blank line...
WRITELINE(F, L);
-- Write some BITs...
for i in 1 to 10 loop
WRITE(L, Bit'('0'), RIGHT, i);
WRITE(L, String'("**"), RIGHT, 12-i);
WRITE(L, Bit'('1'), LEFT, i);
WRITE(L, String'("**"), LEFT, 0);
WRITELINE(F, L);
end loop;
WRITELINE(F, L);
-- Write some Bit vectors...
for i in BV'Range loop
BV(i) := Bit'Val(Boolean'Pos(BV'Right mod i = 0));
end loop;
for i in 15 downto 1 loop
WRITE(L, BV((15-i)*2+1 to 30), RIGHT, 30);
WRITE(L, String'("**"), RIGHT, 3);
WRITE(L, BV(1 to 2*i), LEFT, 30);
WRITELINE(F, L);
end loop;
WRITELINE(F, L);
-- Write some BOOLEANs...
for i in 10 downto 1 loop
WRITE(L, Boolean'(FALSE), RIGHT, i);
WRITE(L, String'("**"), RIGHT, 12-i);
WRITE(L, Boolean'(TRUE), RIGHT, 11-i);
WRITELINE(F, L);
end loop;
WRITELINE(F, L);
wait for 10 ns;
assert FALSE
report "***PASSED TEST: c14s03b00x00p56n01i03203 - This test file will output an TEXT file with predefined data type BIT, BITVECOTR, BOOLEAN and STRING, and next test file will be used to verify the correctness of the this writing test."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p56n01i03203arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2484.vhd
|
4
|
3529
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2484.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p01n02i02484ent IS
END c07s03b03x00p01n02i02484ent;
ARCHITECTURE c07s03b03x00p01n02i02484arch OF c07s03b03x00p01n02i02484ent IS
signal t1, t2, t3, t4 : INTEGER := -1;
BEGIN
TESTING: PROCESS
constant ref : INTEGER := 123;
function FuncN1 return INTEGER is
function FuncN2 return INTEGER is
function FuncN3 return INTEGER is
function FuncN4 return INTEGER is
function FuncN5 return INTEGER is
function FuncN6 return INTEGER is
function FuncN7 return INTEGER is
function FuncN8 return INTEGER is
function FuncN9 return INTEGER is
function FuncN10 return INTEGER is
function FuncN11 return INTEGER is
begin
return ref;
end FuncN11;
begin
return FuncN11;
end FuncN10;
begin
return FuncN10;
end FuncN9;
begin
return FuncN9;
end FuncN8;
begin
return FuncN8;
end FuncN7;
begin
return FuncN7;
end FuncN6;
begin
return FuncN6;
end FuncN5;
begin
return FuncN5;
end FuncN4;
begin
return FuncN4;
end FuncN3;
begin
return FuncN3;
end FuncN2;
begin
return FuncN2;
end FuncN1;
function Func1 return INTEGER is
begin
return 1;
end Func1;
function Func2(selector : BOOLEAN) return INTEGER is
begin
if selector then
return 11;
else
return 13;
end if;
end Func2;
BEGIN
t1 <= func1;
t2 <= func2(TRUE);
t3 <= func2(FALSE);
t4 <= funcN1;
wait for 5 ns;
assert NOT( t1=1 and t2=11 and t3=13 and t4=123 )
report "***PASSED TEST: c07s03b03x00p01n02i02484"
severity NOTE;
assert ( t1=1 and t2=11 and t3=13 and t4=123 )
report "***FAILED TEST: c07s03b03x00p01n02i02484 - Function call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p01n02i02484arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue317/PoC/src/sim/sim_protected.v08.vhdl
|
2
|
18629
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- -------------------------------------
-- .. TODO:: No documentation available.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.sim_types.all;
package sim_protected is
-- Simulation Task and Status Management
-- ===========================================================================
type T_SIM_STATUS is protected
-- Initializer and Finalizer
procedure initialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high);
procedure finalize;
-- Assertions
procedure fail(Message : string := "");
procedure assertion(Condition : boolean; Message : string := "");
procedure writeMessage(Message : string);
procedure writeReport;
-- Process Management
impure function registerProcess(Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID;
impure function registerProcess(TestID : T_SIM_TEST_ID; Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID;
procedure deactivateProcess(procID : T_SIM_PROCESS_ID; SkipLowPriority : boolean := FALSE);
procedure stopAllProcesses;
procedure stopProcesses(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID);
-- Test Management
procedure createDefaultTest;
impure function createTest(Name : string) return T_SIM_TEST_ID;
procedure activateDefaultTest;
procedure finalizeTest;
procedure finalizeTest(TestID : T_SIM_TEST_ID);
-- Run Management
procedure stopAllClocks;
procedure stopClocks(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID);
impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean;
impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean;
impure function isAllFinalized return boolean;
end protected;
end package;
package body sim_protected is
-- Simulation process and Status Management
-- ===========================================================================
type T_SIM_STATUS_STATE is record
IsInitialized : boolean;
IsFinalized : boolean;
end record;
type T_SIM_STATUS is protected body
-- status
variable State : T_SIM_STATUS_STATE := (FALSE, FALSE);
variable Max_AssertFailures : natural := natural'high;
variable Max_SimulationRuntime : time := time'high;
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
variable Passed : boolean := TRUE;
variable AssertCount : natural := 0;
variable FailedAssertCount : natural := 0;
-- Clock Management
variable MainProcessEnables : T_SIM_BOOLVEC(T_SIM_TEST_ID) := (others => TRUE);
variable MainClockEnables : T_SIM_BOOLVEC(T_SIM_TEST_ID) := (others => TRUE);
-- Process Management
variable ProcessCount : natural := 0;
variable ActiveProcessCount : natural := 0;
variable Processes : T_SIM_PROCESS_VECTOR(T_SIM_PROCESS_ID);
-- Test Management
variable TestCount : natural := 0;
variable ActiveTestCount : natural := 0;
variable Tests : T_SIM_TEST_VECTOR(T_SIM_TEST_ID);
-- Initializer
procedure init is
begin
if (State.IsInitialized = FALSE) then
if C_SIM_VERBOSE then report "init:" severity NOTE; end if;
State.IsInitialized := TRUE;
createDefaultTest;
end if;
end procedure;
procedure initialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is
begin
if C_SIM_VERBOSE then report "initialize:" severity NOTE; end if;
init;
Max_AssertFailures := MaxAssertFailures;
Max_SimulationRuntime := MaxSimulationRuntime;
end procedure;
procedure finalize is
begin
if (State.IsFinalized = FALSE) then
if C_SIM_VERBOSE then report "finalize: " severity NOTE; end if;
State.IsFinalized := TRUE;
for i in C_SIM_DEFAULT_TEST_ID to TestCount - 1 loop
finalizeTest(i);
end loop;
writeReport;
end if;
end procedure;
procedure writeReport_Header is
variable LineBuffer : LINE;
begin
write(LineBuffer, ( string'("========================================")));
write(LineBuffer, (LF & string'("POC TESTBENCH REPORT")));
write(LineBuffer, (LF & string'("========================================")));
writeline(output, LineBuffer);
end procedure;
procedure writeReport_TestReport(Prefix : string := "") is
variable LineBuffer : LINE;
begin
if (Tests(C_SIM_DEFAULT_TEST_ID).Status /= SIM_TEST_STATUS_CREATED) then
write(LineBuffer, Prefix & "Tests " & integer'image(TestCount + 1));
write(LineBuffer, LF & Prefix & " " & str_ralign("-1", log10ceilnz(TestCount + 1) + 1) & ": " & C_SIM_DEFAULT_TEST_NAME);
else
write(LineBuffer, Prefix & "Tests " & integer'image(TestCount));
end if;
for i in 0 to TestCount - 1 loop
write(LineBuffer, LF & Prefix & " " & str_ralign(integer'image(i), log10ceilnz(TestCount)) & ": " & str_trim(Tests(i).Name));
end loop;
writeline(output, LineBuffer);
end procedure;
procedure writeReport_AssertReport(Prefix : string := "") is
variable LineBuffer : LINE;
begin
write(LineBuffer, Prefix & "Assertions " & integer'image(AssertCount));
write(LineBuffer, LF & Prefix & " failed " & integer'image(FailedAssertCount) & ite((FailedAssertCount >= Max_AssertFailures), " Too many failed asserts!", ""));
writeline(output, LineBuffer);
end procedure;
procedure writeReport_ProcessReport(Prefix : string := "") is
variable LineBuffer : LINE;
begin
write(LineBuffer, Prefix & "Processes " & integer'image(ProcessCount));
write(LineBuffer, LF & Prefix & " active " & integer'image(ActiveProcessCount));
-- report killed processes
for i in 0 to ProcessCount - 1 loop
if ((Processes(i).Status = SIM_PROCESS_STATUS_ACTIVE) and (Processes(i).IsLowPriority = FALSE)) then
write(LineBuffer, LF & Prefix & " " & str_ralign(integer'image(i), log10ceilnz(ProcessCount)) & ": " & str_trim(Processes(i).Name));
end if;
end loop;
writeline(output, LineBuffer);
end procedure;
procedure writeReport_RuntimeReport(Prefix : string := "") is
variable LineBuffer : LINE;
begin
write(LineBuffer, Prefix & "Runtime " & to_string(now, 1));
writeline(output, LineBuffer);
end procedure;
procedure writeReport_SimulationResult is
variable LineBuffer : LINE;
begin
write(LineBuffer, ( string'("========================================")));
if not Passed then write(LineBuffer, (LF & string'("SIMULATION RESULT = FAILED")));
elsif AssertCount = 0 then write(LineBuffer, (LF & string'("SIMULATION RESULT = NO ASSERTS")));
elsif Passed then write(LineBuffer, (LF & string'("SIMULATION RESULT = PASSED")));
end if;
write(LineBuffer, (LF & string'("========================================")));
writeline(output, LineBuffer);
end procedure;
procedure writeReport is
variable LineBuffer : LINE;
begin
writeReport_Header;
writeReport_TestReport("");
write(LineBuffer, LF & "Overall");
writeline(output, LineBuffer);
writeReport_AssertReport(" ");
writeReport_ProcessReport(" ");
writeReport_RuntimeReport(" ");
writeReport_SimulationResult;
end procedure;
procedure assertion(condition : boolean; Message : string := "") is
begin
AssertCount := AssertCount + 1;
if not condition then
fail(Message);
FailedAssertCount := FailedAssertCount + 1;
if (FailedAssertCount >= Max_AssertFailures) then
stopAllProcesses;
end if;
end if;
end procedure;
procedure fail(Message : string := "") is
begin
if (Message'length > 0) then
report Message severity ERROR;
end if;
Passed := FALSE;
end procedure;
procedure writeMessage(Message : string) is
variable LineBuffer : LINE;
begin
write(LineBuffer, Message);
writeline(output, LineBuffer);
end procedure;
procedure createDefaultTest is
variable Test : T_SIM_TEST;
begin
if (State.IsInitialized = FALSE) then
init;
end if;
if C_SIM_VERBOSE then report "createDefaultTest(" & C_SIM_DEFAULT_TEST_NAME & "):" severity NOTE; end if;
Test.ID := C_SIM_DEFAULT_TEST_ID;
Test.Name := resize(C_SIM_DEFAULT_TEST_NAME, T_SIM_TEST_NAME'length);
Test.Status := SIM_TEST_STATUS_CREATED;
Test.ProcessIDs := (others => 0);
Test.ProcessCount := 0;
Test.ActiveProcessCount := 0;
-- add to the internal structure
Tests(Test.ID) := Test;
end procedure;
impure function createTest(Name : string) return T_SIM_TEST_ID is
variable Test : T_SIM_TEST;
begin
if (State.IsInitialized = FALSE) then
init;
end if;
if C_SIM_VERBOSE then report "createTest(" & Name & "): => " & T_SIM_TEST_ID'image(TestCount) severity NOTE; end if;
Test.ID := TestCount;
Test.Name := resize(Name, T_SIM_TEST_NAME'length);
Test.Status := SIM_TEST_STATUS_ACTIVE;
Test.ProcessIDs := (others => 0);
Test.ProcessCount := 0;
Test.ActiveProcessCount := 0;
-- add to the internal structure
Tests(Test.ID) := Test;
TestCount := TestCount + 1;
ActiveTestCount := ActiveTestCount + 1;
-- return TestID for finalizeTest
return Test.ID;
end function;
procedure activateDefaultTest is
begin
if (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_CREATED) then
Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ACTIVE;
ActiveTestCount := ActiveTestCount + 1;
end if;
end procedure;
procedure finalizeTest is
begin
finalizeTest(C_SIM_DEFAULT_TEST_ID);
end procedure;
procedure finalizeTest(TestID : T_SIM_TEST_ID) is
begin
if (TestID >= TestCount) then
report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE;
return;
end if;
if TestID = C_SIM_DEFAULT_TEST_ID then
if (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_CREATED) then
if C_SIM_VERBOSE then report "finalizeTest(" & integer'image(C_SIM_DEFAULT_TEST_ID) & "): inactive" severity NOTE; end if;
Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ENDED;
stopProcesses(C_SIM_DEFAULT_TEST_ID);
return;
elsif (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_ACTIVE) then
if ActiveTestCount > 1 then
for ProcIdx in 0 to Tests(C_SIM_DEFAULT_TEST_ID).ProcessCount - 1 loop
deactivateProcess(Tests(C_SIM_DEFAULT_TEST_ID).ProcessIDs(ProcIdx), TRUE);
end loop;
Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ZOMBI;
return;
else
if C_SIM_VERBOSE then report "finalizeTest(" & integer'image(C_SIM_DEFAULT_TEST_ID) & "): active" severity NOTE; end if;
Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ENDED;
ActiveTestCount := ActiveTestCount - 1;
stopProcesses(C_SIM_DEFAULT_TEST_ID);
end if;
end if;
elsif (Tests(TestID).Status /= SIM_TEST_STATUS_ENDED) then
if C_SIM_VERBOSE then report "finalizeTest(TestID=" & T_SIM_TEST_ID'image(TestID) & "): " severity NOTE; end if;
Tests(TestID).Status := SIM_TEST_STATUS_ENDED;
ActiveTestCount := ActiveTestCount - 1;
if (Tests(TestID).ActiveProcessCount > 0) then
fail("Test " & integer'image(TestID) & " '" & str_trim(Tests(TestID).Name) & "' has still active process while finalizing:");
for ProcIdx in 0 to Tests(TestID).ProcessCount - 1 loop
if (Processes(Tests(TestID).ProcessIDs(ProcIdx)).Status = SIM_PROCESS_STATUS_ACTIVE) then
report " " & Processes(Tests(TestID).ProcessIDs(ProcIdx)).Name severity WARNING;
end if;
end loop;
end if;
stopProcesses(TestID);
end if;
if ActiveTestCount = 0 then
finalize;
elsif ActiveTestCount = 1 then
if (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_ACTIVE) then
finalizeTest(C_SIM_DEFAULT_TEST_ID);
elsif (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_ZOMBI) then
stopProcesses(C_SIM_DEFAULT_TEST_ID);
else
return;
end if;
finalize;
end if;
end procedure;
impure function registerProcess(Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is
begin
return registerProcess(C_SIM_DEFAULT_TEST_ID, Name, IsLowPriority);
end function;
impure function registerProcess(TestID : T_SIM_TEST_ID; Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is
variable Proc : T_SIM_PROCESS;
variable TestProcID : T_SIM_TEST_ID;
begin
if (State.IsInitialized = FALSE) then
init;
end if;
if TestID = C_SIM_DEFAULT_TEST_ID then
activateDefaultTest;
end if;
if (TestID >= TestCount) then
report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE;
return T_SIM_PROCESS_ID'high;
end if;
if C_SIM_VERBOSE then report "registerProcess(TestID=" & T_SIM_TEST_ID'image(TestID) & ", " & Name & "): => " & T_SIM_PROCESS_ID'image(ProcessCount) severity NOTE; end if;
Proc.ID := ProcessCount;
Proc.TestID := TestID;
Proc.Name := resize(Name, T_SIM_PROCESS_NAME'length);
Proc.Status := SIM_PROCESS_STATUS_ACTIVE;
Proc.IsLowPriority := IsLowPriority;
-- add process to list
Processes(Proc.ID) := Proc;
ProcessCount := ProcessCount + 1;
ActiveProcessCount := inc_if(not IsLowPriority, ActiveProcessCount);
-- add process to test
TestProcID := Tests(TestID).ProcessCount;
Tests(TestID).ProcessIDs(TestProcID) := Proc.ID;
Tests(TestID).ProcessCount := TestProcID + 1;
Tests(TestID).ActiveProcessCount := inc_if(not IsLowPriority, Tests(TestID).ActiveProcessCount);
-- return the process ID
return Proc.ID;
end function;
procedure deactivateProcess(ProcID : T_SIM_PROCESS_ID; SkipLowPriority : boolean := FALSE) is
variable TestID : T_SIM_TEST_ID;
begin
if (ProcID >= ProcessCount) then
report "ProcID (" & T_SIM_PROCESS_ID'image(ProcID) & ") is unknown." severity FAILURE;
return;
elsif (Processes(ProcID).IsLowPriority and SkipLowPriority) then
return;
end if;
TestID := Processes(ProcID).TestID;
-- deactivate process
if (Processes(ProcID).Status = SIM_PROCESS_STATUS_ACTIVE) then
if C_SIM_VERBOSE then report "deactivateProcess(ProcID=" & T_SIM_PROCESS_ID'image(ProcID) & "): TestID=" & T_SIM_TEST_ID'image(TestID) & " Name=" & str_trim(Processes(ProcID).Name) severity NOTE; end if;
Processes(ProcID).Status := SIM_PROCESS_STATUS_ENDED;
ActiveProcessCount := dec_if(not Processes(ProcID).IsLowPriority, ActiveProcessCount);
Tests(TestID).ActiveProcessCount := dec_if(not Processes(ProcID).IsLowPriority, Tests(TestID).ActiveProcessCount);
if (Tests(TestID).ActiveProcessCount = 0) then
finalizeTest(TestID);
end if;
end if;
end procedure;
procedure stopAllProcesses is
begin
if C_SIM_VERBOSE then report "stopAllProcesses:" severity NOTE; end if;
for i in C_SIM_DEFAULT_TEST_ID to TestCount - 1 loop
stopProcesses(i);
end loop;
end procedure;
procedure stopProcesses(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) is
begin
if (TestID >= TestCount) then
report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE;
return;
end if;
if C_SIM_VERBOSE then report "stopProcesses(TestID=" & T_SIM_TEST_ID'image(TestID) & "): Name=" & str_trim(Tests(TestID).Name) severity NOTE; end if;
MainProcessEnables(TestID) := FALSE;
stopClocks(TestID);
end procedure;
procedure stopAllClocks is
begin
if C_SIM_VERBOSE then report "stopAllClocks:" severity NOTE; end if;
for i in C_SIM_DEFAULT_TEST_ID to TestCount - 1 loop
stopClocks(i);
end loop;
end procedure;
procedure stopClocks(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) is
begin
if (TestID >= TestCount) then
report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE;
return;
end if;
if C_SIM_VERBOSE then report "stopClocks(TestID=" & T_SIM_TEST_ID'image(TestID) & "): Name=" & str_trim(Tests(TestID).Name) severity NOTE; end if;
MainClockEnables(TestID) := FALSE;
end procedure;
impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is
begin
return not MainClockEnables(TestID);
end function;
impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is
begin
return (Tests(TestID).Status = SIM_TEST_STATUS_ENDED);
end function;
impure function isAllFinalized return boolean is
begin
if (State.IsFinalized = TRUE) then
if ActiveTestCount = 0 then
return TRUE;
end if;
report "isAllFinalized: " severity ERROR;
return FALSE;
else
return FALSE;
end if;
end function;
end protected body;
end package body;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd
|
4
|
1934
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity circuit is
generic ( inpad_delay, outpad_delay : delay_length );
port ( in1, in2, in3 : in bit; out1, out2 : out bit );
end entity circuit;
--------------------------------------------------
architecture with_pad_delays of circuit is
component subcircuit is
port ( a, b : in bit; y1, y2 : out bit );
end component subcircuit;
signal delayed_in1, delayed_in2, delayed_in3 : bit;
signal undelayed_out1, undelayed_out2 : bit;
begin
input_delays : block is
begin
delayed_in1 <= in1 after inpad_delay;
delayed_in2 <= in2 after inpad_delay;
delayed_in3 <= in3 after inpad_delay;
end block input_delays;
functionality : block is
signal intermediate : bit;
begin
cell1 : component subcircuit
port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate );
cell2 : component subcircuit
port map ( intermediate, delayed_in3, undelayed_out2, open );
end block functionality;
output_delays : block is
begin
out1 <= undelayed_out1 after outpad_delay;
out2 <= undelayed_out2 after outpad_delay;
end block output_delays;
end architecture with_pad_delays;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/bug090/hang7.vhdl
|
1
|
1300
|
library ieee;
use ieee.s_1164.all;
entity dff is
generic (len : natural := 8);
port (clk : in std_logic;
t_n : in std_logic;
d : c_vector (len - 1 downto 0);
q : out stdector (len - 1 downto 0));
end dff;
architecture behav of dff is
begin
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else
q <= d;
end if;
end if;
end process p;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : s;
signal rst_n : std_logic;
signal din, dout, dout2 : std_loor (7 downto 0);
component dff is
generic (len : natural := 8);
port (clk : in std_logic;
st_n : in std_logic;
d : std_logic_vector (len - 1 downto 0);
q : out std_logic_vector (len - 1 downto 0));
end component;
begin
mydff : entity work.dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout);
dff2 : dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout2);
rst_n <= '0' after 0 ns, '1' after 4 ns;
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1case
end process;
chkr: process (clk)
begin
if!rst_n = '0' then
null;
elsif rising_edge (av;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue645/foo.vhdl
|
1
|
714
|
library ieee;
use ieee.std_logic_1164.all;
package types is
type t is array (natural range <>) of std_logic_vector;
-- Warning : only compiles with --std=08
end package;
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity foo is
generic (n: natural; p: natural);
port (clk: in std_logic;
din: in std_logic_vector(p-1 downto 0);
dout: out t);
end entity;
architecture rtl of foo is
signal REG: t(0 to n-1)(p-1 downto 0); -- !!! CRASH HERE
begin
process (clk)
begin
if clk'event and clk='1' then
for i in 1 to n-1 loop
reg(i) <= reg(i-1);
end loop;
reg(0) <= din;
end if;
end process;
dout <= reg;
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc142.vhd
|
4
|
2142
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc142.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p10n01i00142ent IS
PORT ( SIGNAL a : IN bit;
SIGNAL b : IN integer;
SIGNAL c : IN boolean;
SIGNAL d : IN time;
SIGNAL e : IN real;
SIGNAL oint : INOUT integer);
END c04s03b02x02p10n01i00142ent;
ARCHITECTURE c04s03b02x02p10n01i00142arch OF c04s03b02x02p10n01i00142ent IS
function funct1( fpar1:bit :='1';
fpar2:integer :=455;
fpar3:boolean :=true;
fpar4:time :=55.77 ns;
fpar5:real :=34.558) return integer is
begin
return 1;
end funct1;
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
oint <= funct1(fpar3=>c,fpar2=>b,fpar1=>a,d,e);
assert FALSE
report "***FAILED TEST: c04s03b02x02p10n01i00142 - Positional association can not follow named association."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p10n01i00142arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1867.vhd
|
4
|
1992
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1867.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01867ent IS
END c07s01b00x00p08n01i01867ent;
ARCHITECTURE c07s01b00x00p08n01i01867arch OF c07s01b00x00p08n01i01867ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal s_int : small_int;
signal bool : boolean;
BEGIN
with c07s01b00x00p08n01i01867arch select --body name illegal here
obus <= (0 => 1, others => 0) after 5 ns when true;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01867 - Architecture body names are not permitted as primaries in a selected signal expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01867arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1054.vhd
|
4
|
1881
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1054.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01054ent IS
END c06s04b00x00p03n02i01054ent;
ARCHITECTURE c06s04b00x00p03n02i01054arch OF c06s04b00x00p03n02i01054ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (EN1, EN2, EN3);
type A12 is array (ENUM1) of BOOLEAN;
variable V1: BOOLEAN;
variable V12: A12 ;
BEGIN
V1 := V12(EN3, EN2); -- ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01054 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01054arch;
|
gpl-2.0
|
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