repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/stratixii/simprims/stratixii_components.vhd | 2 | 49003 | -- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixii_atom_pack.all;
package STRATIXII_COMPONENTS is
--
-- STRATIXII_LCELL_FF
--
component stratixii_lcell_ff
generic (
x_on_violation : string := "on";
lpm_type : string := "stratixii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end component;
--
-- STRATIXII_LCELL_COMB
--
component stratixii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "stratixii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
end component;
--
-- STRATIXII_IO
--
component stratixii_io
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "stratixii_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
end component;
--
-- STRATIXII_CLKCTRL
--
component stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
--
-- STRATIXII_MAC_MULT
--
component stratixii_mac_mult
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
dynamic_mode : string := "no";
lpm_type : string := "stratixii_mac_mult"
);
port
(
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode : IN std_logic := '0';
zeroacc : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1'
);
end component;
--
-- STRATIXII_MAC_OUT
--
component stratixii_mac_out
generic
(
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "stratixii_mac_out"
);
port
(
dataa : in std_logic_vector (dataa_width - 1 downto 0) := (others => '1');
datab : in std_logic_vector (datab_width - 1 downto 0) := (others => '1');
datac : in std_logic_vector (datac_width - 1 downto 0) := (others => '1');
datad : in std_logic_vector (datad_width - 1 downto 0) := (others => '1');
zeroacc : in std_logic := '0';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
round0 : in std_logic := '0';
round1 : in std_logic := '0';
saturate : in std_logic := '0';
multabsaturate : in std_logic := '0';
multcdsaturate : in std_logic := '0';
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector (3 downto 0) := "0000";
aclr : in std_logic_vector (3 downto 0) := "0000";
ena : in std_logic_vector (3 downto 0) := "1111";
mode0 : in std_logic := '0';
mode1 : in std_logic := '0';
zeroacc1 : in std_logic := '0';
saturate1 : in std_logic := '0';
dataout : out std_logic_vector (dataout_width -1 downto 0);
accoverflow : out std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1'
);
end component;
--
-- STRATIXII_PLL
--
COMPONENT stratixii_pll
GENERIC (operation_mode : string := "normal";
pll_type : string := "auto";
compensate_clock : string := "clk0";
feedback_source : string := "e0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0 %";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USE PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_c : integer := 16;
loop_filter_r : string := "1.0" ;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
scan_chain_mif_file : string := "";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (inclk : IN std_logic_vector(1 downto 0);
fbin : IN std_logic := '0';
ena : IN std_logic := '1';
clkswitch : IN std_logic := '0';
areset : IN std_logic := '0';
pfdena : IN std_logic := '1';
scanread : IN std_logic := '0';
scanwrite : IN std_logic := '0';
scandata : IN std_logic := '0';
scanclk : IN std_logic := '0';
testin : IN std_logic_vector(3 downto 0) := "0000";
clk : OUT std_logic_vector(5 downto 0);
clkbad : OUT std_logic_vector(1 downto 0);
activeclock : OUT std_logic;
locked : OUT std_logic;
clkloss : OUT std_logic;
scandataout : OUT std_logic;
scandone : OUT std_logic;
testupout : OUT std_logic;
testdownout : OUT std_logic;
-- lvds specific ports
enable0 : OUT std_logic;
enable1 : OUT std_logic;
sclkout : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--
-- STRATIXII_LVDS_TRANSMITTER
--
COMPONENT stratixii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : String := "stratixii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- STRATIXII_LVDS_RECEIVER
--
COMPONENT stratixii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "stratixii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- STRATIXII_DLL_COMPONENT
--
COMPONENT stratixii_dll
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "stratixii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '0';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
--
-- STRATIXII_RUBLOCK
--
--
component stratixii_rublock
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
end component;
--
-- STRATIXII_TERMINATION_COMPONENT
--
COMPONENT stratixii_termination
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "stratixii_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END COMPONENT;
--
-- STRATIXII_ROUTING_WIRE
--
component stratixii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
end component;
--
-- STRATIXII_JTAG
--
component stratixii_jtag
generic (
lpm_type : string := "stratixii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end component;
--
--
-- STRATIXII_CRCBLOCK
--
--
component stratixii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end component;
--
-- STRATIXII_ASMIBLOCK
--
component stratixii_asmiblock
generic (
lpm_type : string := "stratixii_asmiblock"
);
port (
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic
);
end component;
--
-- stratixii_ram_block
--
component stratixii_ram_block
generic
(
operation_mode : string := "single_port";
mixed_port_feed_through_mode : string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name : string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout : string := "none";
data_interleave_width_in_bits : integer := 1;
data_interleave_offset_in_bits : integer := 1;
port_a_logical_ram_depth : integer := 0;
port_a_logical_ram_width : integer := 0;
port_a_data_in_clear : string := "none";
port_a_address_clear : string := "none";
port_a_write_enable_clear : string := "none";
port_a_data_out_clock : string := "none";
port_a_data_out_clear : string := "none";
port_a_first_address : integer := 0;
port_a_last_address : integer := 0;
port_a_first_bit_number : integer := 0;
port_a_data_width : integer := 1;
port_a_byte_enable_clear : string := "none";
port_a_data_in_clock : string := "clock0";
port_a_address_clock : string := "clock0";
port_a_write_enable_clock : string := "clock0";
port_a_byte_enable_clock : string := "clock0";
port_b_logical_ram_depth : integer := 0;
port_b_logical_ram_width : integer := 0;
port_b_data_in_clock : string := "clock1";
port_b_data_in_clear : string := "none";
port_b_address_clock : string := "clock1";
port_b_address_clear : string := "none";
port_b_read_enable_write_enable_clock : string := "clock1";
port_b_read_enable_write_enable_clear : string := "none";
port_b_data_out_clock : string := "none";
port_b_data_out_clear : string := "none";
port_b_first_address : integer := 0;
port_b_last_address : integer := 0;
port_b_first_bit_number : integer := 0;
port_b_data_width : integer := 1;
port_b_byte_enable_clear : string := "none";
port_b_byte_enable_clock : string := "clock1";
port_a_address_width : integer := 1;
port_b_address_width : integer := 1;
port_a_byte_enable_mask_width : integer := 1;
port_b_byte_enable_mask_width : integer := 1;
power_up_uninitialized : string := "false";
port_a_byte_size : integer := 0;
port_a_disable_ce_on_input_registers : string := "off";
port_a_disable_ce_on_output_registers : string := "off";
port_b_byte_size : integer := 0;
port_b_disable_ce_on_input_registers : string := "off";
port_b_disable_ce_on_output_registers : string := "off";
lpm_type : string := "stratixii_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
port
(
portawe : in std_logic := '0';
portabyteenamasks : in std_logic_vector (port_a_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbbyteenamasks : in std_logic_vector (port_b_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbrewe : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
portadatain : in std_logic_vector (port_a_data_width - 1 DOWNTO 0) := (others => '0');
portbdatain : in std_logic_vector (port_b_data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : in std_logic_vector (port_a_address_width - 1 DOWNTO 0) := (others => '0');
portbaddr : in std_logic_vector (port_b_address_width - 1 DOWNTO 0) := (others => '0');
portaaddrstall : in std_logic := '0';
portbaddrstall : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
portadataout : out std_logic_vector (port_a_data_width - 1 DOWNTO 0);
portbdataout : out std_logic_vector (port_b_data_width - 1 DOWNTO 0)
);
end component;
end stratixii_components;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/grdware/mul_dware.vhd | 1 | 4078 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: misc
-- File: mul_dware.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Dware multipliers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end;
architecture rtl of mul_dw is
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
signal gnd : std_ulogic;
begin
gnd <= '0';
np : if num_stages = 1 generate
u0 : DW02_mult
generic map ( a_width => a_width, b_width => b_width)
port map (a => a, b => b, TC => sign, product => product);
end generate;
pipe : if num_stages > 1 generate
u0 : DW_mult_pipe
generic map ( a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode, rst_mode => 0)
port map (a => a, b => b, TC => sign, clk => clk, product => product,
rst_n => gnd, en => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
-- u0 : DW02_mult_2_stage
-- generic map ( A_width => A'length, B_width => B'length )
-- port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
u0 : DW_mult_pipe
generic map ( a_width => 61, b_width => 61,
num_stages => 2, stall_mode => 0, rst_mode => 0)
port map (a => a, b => b, TC => gnd, clk => clk, product => pin,
rst_n => gnd, en => gnd);
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/unisim/spictrl_unisim.vhd | 3 | 6932 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2011, Aeroflex Gaisler AB - all rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library synplify;
entity spictrl_unisim is
generic (
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end spictrl_unisim;
architecture rtl of spictrl_unisim is
-- Combination 0, 32 slave selects
component spictrl_unisim_comb0
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector(31 downto 0));
end component;
-- Combination 1, 32 disabled slave selects
component spictrl_unisim_comb1
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector(31 downto 0));
end component;
begin
slvselact : if slvselen /= 0 generate
spic0 : spictrl_unisim_comb0
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi_psel,
apbi_penable => apbi_penable,
apbi_paddr => apbi_paddr,
apbi_pwrite => apbi_pwrite,
apbi_pwdata => apbi_pwdata,
apbi_testen => apbi_testen,
apbi_testrst => apbi_testrst,
apbi_scanen => apbi_scanen,
apbi_testoen => apbi_testoen,
apbo_prdata => apbo_prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii_miso,
spii_mosi => spii_mosi,
spii_sck => spii_sck,
spii_spisel => spii_spisel,
spii_astart => spii_astart,
spii_cstart => spii_cstart,
spio_miso => spio_miso,
spio_misooen => spio_misooen,
spio_mosi => spio_mosi,
spio_mosioen => spio_mosioen,
spio_sck => spio_sck,
spio_sckoen => spio_sckoen,
spio_enable => spio_enable,
spio_astart => spio_astart,
spio_aready => spio_aready,
slvsel => slvsel);
end generate;
noslvsel : if slvselen = 0 generate
spic0 : spictrl_unisim_comb1
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi_psel,
apbi_penable => apbi_penable,
apbi_paddr => apbi_paddr,
apbi_pwrite => apbi_pwrite,
apbi_pwdata => apbi_pwdata,
apbi_testen => apbi_testen,
apbi_testrst => apbi_testrst,
apbi_scanen => apbi_scanen,
apbi_testoen => apbi_testoen,
apbo_prdata => apbo_prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii_miso,
spii_mosi => spii_mosi,
spii_sck => spii_sck,
spii_spisel => spii_spisel,
spii_astart => spii_astart,
spii_cstart => spii_cstart,
spio_miso => spio_miso,
spio_misooen => spio_misooen,
spio_mosi => spio_mosi,
spio_mosioen => spio_mosioen,
spio_sck => spio_sck,
spio_sckoen => spio_sckoen,
spio_enable => spio_enable,
spio_astart => spio_astart,
spio_aready => spio_aready,
slvsel => slvsel);
end generate;
end rtl;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/can/can.vhd | 1 | 6902 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: can
-- File: can.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: CAN component declartions
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package can is
component can_mod
generic (memtech : integer := DEFMEMTECH; syncrst : integer := 0;
ft : integer := 0);
port (
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic;
testen : in std_logic);
end component;
component can_oc
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
ft : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic;
can_txo : out std_logic
);
end component;
component can_mc
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 2 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
end component;
component can_rd
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end component;
component canmux
port(
sel : in std_logic;
canrx : out std_logic;
cantx : in std_logic;
canrxv : in std_logic_vector(0 to 1);
cantxv : out std_logic_vector(0 to 1)
);
end component;
-----------------------------------------------------------------------------
-- interface type declarations for can controller
-----------------------------------------------------------------------------
type can_in_type is record
rx: std_logic_vector(1 downto 0); -- receive lines
end record;
type can_out_type is record
tx: std_logic_vector(1 downto 0); -- transmit lines
en: std_logic_vector(1 downto 0); -- transmit enables
end record;
-----------------------------------------------------------------------------
-- component declaration for grcan controller
-----------------------------------------------------------------------------
component grcan is
generic (
hindex: integer := 0;
pindex: integer := 0;
paddr: integer := 0;
pmask: integer := 16#ffc#;
pirq: integer := 1; -- index of first irq
singleirq: integer := 0; -- single irq output
txchannels: integer range 1 to 1 := 1; -- 1 to 1 channels
rxchannels: integer range 1 to 1 := 1; -- 1 to 1 channels
ptrwidth: integer range 16 to 16 := 16);-- 16 to 64k messages
-- 2k to 8M bits
port (
rstn: in std_ulogic;
clk: in std_ulogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
cani: in can_in_type;
cano: out can_out_type);
end component;
-----------------------------------------------------------------------------
-- component declaration for grhcan controller
-----------------------------------------------------------------------------
component grhcan is
generic (
hindex: integer := 0;
pindex: integer := 0;
paddr: integer := 0;
pmask: integer := 16#ffc#;
pirq: integer := 1; -- index of first irq
txchannels: integer range 1 to 1 := 1; -- 1 to 16 channels
rxchannels: integer range 1 to 1 := 1; -- 1 to 16 channels
ptrwidth: integer range 16 to 16 := 16; -- 16 to 64k messages
-- 2k to 8 m bits
singleirq: Integer := 0; -- single irq output
version: Integer := 0); -- 0=516, 1=524
port (
rstn: in std_ulogic;
clk: in std_ulogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
cani: in can_in_type;
cano: out can_out_type);
end component;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml50x/svga2ch7301c.vhd | 3 | 10192 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/modgen/leaves.vhd | 6 | 682913 | -----------------------------------------------------------------------------
-- File: leaves.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package blocks is
component FLIPFLOP
port (
DIN, CLK: in std_logic;
DOUT: out std_logic
);
end component;
component DBLCADDER_32_32
port(OPA: in std_logic_vector(0 to 31);
OPB: in std_logic_vector(0 to 31);
CIN: in std_logic;
PHI: in std_logic;
SUM: out std_logic_vector(0 to 31);
COUT: out std_logic);
end component;
component FULL_ADDER
port
(
DATA_A, DATA_B, DATA_C: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
component HALF_ADDER
port
(
DATA_A, DATA_B: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
component R_GATE
port
(
INA, INB, INC: in std_logic;
PPBIT: out std_logic
);
end component;
component DECODER
port
(
INA, INB, INC: in std_logic;
TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end component;
component PP_LOW
port
(
ONEPOS, ONENEG, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_MIDDLE
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB, INC, IND: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_HIGH
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component BLOCK0
port
(
A,B,PHI: in std_logic;
POUT,GOUT: out std_logic
);
end component;
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK2
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component PRESTAGE_32
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 31);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component XXOR1
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end component;
component XXOR2
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end component;
component DBLCTREE_32
port
(
PIN:in std_logic_vector(0 to 31);
GIN:in std_logic_vector(0 to 32);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 32);
POUT:out std_logic_vector(0 to 0)
);
end component;
component XORSTAGE_32
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
PBIT: in std_logic;
PHI: in std_logic;
CARRY: in std_logic_vector(0 to 32);
SUM: out std_logic_vector(0 to 31);
COUT: out std_logic
);
end component;
component DBLC_0_32
port
(
PIN: in std_logic_vector(0 to 31);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 30);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_1_32
port
(
PIN: in std_logic_vector(0 to 30);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 28);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_2_32
port
(
PIN: in std_logic_vector(0 to 28);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 24);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_3_32
port
(
PIN: in std_logic_vector(0 to 24);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 16);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_4_32
port
(
PIN: in std_logic_vector(0 to 16);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component PRESTAGE_64
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 63);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLCTREE_64
port
(
PIN:in std_logic_vector(0 to 63);
GIN:in std_logic_vector(0 to 64);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 64);
POUT:out std_logic_vector(0 to 0)
);
end component;
component XORSTAGE_64
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
PBIT: in std_logic;
PHI: in std_logic;
CARRY: in std_logic_vector(0 to 64);
SUM: out std_logic_vector(0 to 63);
COUT: out std_logic
);
end component;
component DBLC_0_64
port
(
PIN: in std_logic_vector(0 to 63);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 62);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_1_64
port
(
PIN: in std_logic_vector(0 to 62);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 60);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_2_64
port
(
PIN: in std_logic_vector(0 to 60);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 56);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_3_64
port
(
PIN: in std_logic_vector(0 to 56);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 48);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_4_64
port
(
PIN: in std_logic_vector(0 to 48);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 32);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_5_64
port
(
PIN: in std_logic_vector(0 to 32);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_0_128
port
(
PIN: in std_logic_vector(0 to 127);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 126);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_1_128
port
(
PIN: in std_logic_vector(0 to 126);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 124);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_2_128
port
(
PIN: in std_logic_vector(0 to 124);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 120);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_3_128
port
(
PIN: in std_logic_vector(0 to 120);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 112);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_4_128
port
(
PIN: in std_logic_vector(0 to 112);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 96);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_5_128
port
(
PIN: in std_logic_vector(0 to 96);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 64);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_6_128
port
(
PIN: in std_logic_vector(0 to 64);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component PRESTAGE_128
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 127);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLCTREE_128
port
(
PIN:in std_logic_vector(0 to 127);
GIN:in std_logic_vector(0 to 128);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 128);
POUT:out std_logic_vector(0 to 0)
);
end component;
component XORSTAGE_128
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
PBIT: in std_logic;
PHI: in std_logic;
CARRY: in std_logic_vector(0 to 128);
SUM: out std_logic_vector(0 to 127);
COUT: out std_logic
);
end component;
component BOOTHCODER_18_18
port
(
OPA: in std_logic_vector(0 to 17);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 188)
);
end component;
component WALLACE_18_18
port
(
SUMMAND: in std_logic_vector(0 to 188);
CARRY: out std_logic_vector(0 to 33);
SUM: out std_logic_vector(0 to 34)
);
end component;
component DBLCADDER_64_64
port
(
OPA:in std_logic_vector(0 to 63);
OPB:in std_logic_vector(0 to 63);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 63);
COUT:out std_logic
);
end component;
component BOOTHCODER_34_10
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 9);
SUMMAND: out std_logic_vector(0 to 184)
);
end component;
component WALLACE_34_10
port
(
SUMMAND: in std_logic_vector(0 to 184);
CARRY: out std_logic_vector(0 to 41);
SUM: out std_logic_vector(0 to 42)
);
end component;
component BOOTHCODER_34_18
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 332)
);
end component;
component WALLACE_34_18
port
(
SUMMAND: in std_logic_vector(0 to 332);
CARRY: out std_logic_vector(0 to 49);
SUM: out std_logic_vector(0 to 50)
);
end component;
component BOOTHCODER_34_34
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 33);
SUMMAND: out std_logic_vector(0 to 628)
);
end component;
component WALLACE_34_34
port
(
SUMMAND: in std_logic_vector(0 to 628);
CARRY: out std_logic_vector(0 to 65);
SUM: out std_logic_vector(0 to 66)
);
end component;
component DBLCADDER_128_128
port
(
OPA:in std_logic_vector(0 to 127);
OPB:in std_logic_vector(0 to 127);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 127);
COUT:out std_logic
);
end component;
component MULTIPLIER_18_18
generic (mulpipe : integer := 0);
port(MULTIPLICAND: in std_logic_vector(0 to 17);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_ulogic;
holdn: in std_ulogic;
RESULT: out std_logic_vector(0 to 63));
end component;
component MULTIPLIER_34_10
port(MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 9);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63));
end component;
component MULTIPLIER_34_18
port(MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63));
end component;
component MULTIPLIER_34_34
generic (mulpipe : integer := 0);
port(MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 33);
PHI: in std_logic;
holdn: in std_ulogic;
RESULT: out std_logic_vector(0 to 127));
end component;
end;
------------------------------------------------------------
-- START: Entities used within the Modified Booth Recoding
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity FLIPFLOP is
port
(
DIN: in std_logic;
CLK: in std_logic;
DOUT: out std_logic
);
end FLIPFLOP;
architecture FLIPFLOP of FLIPFLOP is
begin
process(CLK)
begin
if(CLK='1')and(CLK'event)then
DOUT <= DIN;
end if;
end process;
end FLIPFLOP;
library ieee;
use ieee.std_logic_1164.all;
entity PP_LOW is
port
(
ONEPOS, ONENEG, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end PP_LOW;
architecture PP_LOW of PP_LOW is
begin
PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG;
end PP_LOW;
library ieee;
use ieee.std_logic_1164.all;
entity PP_MIDDLE is
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB, INC, IND: in std_logic;
PPBIT: out std_logic
);
end PP_MIDDLE;
architecture PP_MIDDLE of PP_MIDDLE is
begin
PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG)));
end PP_MIDDLE;
library ieee;
use ieee.std_logic_1164.all;
entity PP_HIGH is
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end PP_HIGH;
architecture PP_HIGH of PP_HIGH is
begin
PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG));
end PP_HIGH;
library ieee;
use ieee.std_logic_1164.all;
entity R_GATE is
port
(
INA, INB, INC: in std_logic;
PPBIT: out std_logic
);
end R_GATE;
architecture R_GATE of R_GATE is
begin
PPBIT <= (not(INA and INB)) and INC;
end R_GATE;
library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
port
(
INA, INB, INC: in std_logic;
TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end DECODER;
architecture DECODER of DECODER is
begin
TWOPOS <= not(not(INA and INB and (not INC)));
TWONEG <= not(not((not INA) and (not INB) and INC));
ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA);
ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA));
end DECODER;
library ieee;
use ieee.std_logic_1164.all;
entity FULL_ADDER is
port
(
DATA_A, DATA_B, DATA_C: in std_logic;
SAVE, CARRY: out std_logic
);
end FULL_ADDER;
architecture FULL_ADDER of FULL_ADDER is
signal TMP: std_logic;
begin
TMP <= DATA_A xor DATA_B;
SAVE <= TMP xor DATA_C;
CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B)));
end FULL_ADDER;
library ieee;
use ieee.std_logic_1164.all;
entity HALF_ADDER is
port
(
DATA_A, DATA_B: in std_logic;
SAVE, CARRY: out std_logic
);
end HALF_ADDER;
architecture HALF_ADDER of HALF_ADDER is
begin
SAVE <= DATA_A xor DATA_B;
CARRY <= DATA_A and DATA_B;
end HALF_ADDER;
library ieee;
use ieee.std_logic_1164.all;
entity INVBLOCK is
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end INVBLOCK;
architecture INVBLOCK_regular of INVBLOCK is
begin
GOUT <= not GIN;
end INVBLOCK_regular;
library ieee;
use ieee.std_logic_1164.all;
entity XXOR1 is
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end XXOR1;
architecture XXOR_regular of XXOR1 is
begin
SUM <= (not (A xor B)) xor GIN;
end XXOR_regular;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK0 is
port
(
A,B,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end BLOCK0;
architecture BLOCK0_regular of BLOCK0 is
begin
POUT <= not(A or B);
GOUT <= not(A and B);
end BLOCK0_regular;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK1 is
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end BLOCK1;
architecture BLOCK1_regular of BLOCK1 is
begin
POUT <= not(PIN1 or PIN2);
GOUT <= not(GIN2 and (PIN2 or GIN1));
end BLOCK1_regular;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK2 is
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end BLOCK2;
architecture BLOCK2_regular of BLOCK2 is
begin
POUT <= not(PIN1 and PIN2);
GOUT <= not(GIN2 or (PIN2 and GIN1));
end BLOCK2_regular;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK1A is
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end BLOCK1A;
architecture BLOCK1A_regular of BLOCK1A is
begin
GOUT <= not(GIN2 and (PIN2 or GIN1));
end BLOCK1A_regular;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK2A is
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end BLOCK2A;
architecture BLOCK2A_regular of BLOCK2A is
begin
GOUT <= not(GIN2 or (PIN2 and GIN1));
end BLOCK2A_regular;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity PRESTAGE_64 is
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 63);
GOUT: out std_logic_vector(0 to 64)
);
end PRESTAGE_64;
architecture PRESTAGE of PRESTAGE_64 is
begin -- PRESTAGE
U1:for I in 0 to 63 generate
U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: Level 0
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_0_64 is
port
(
PIN: in std_logic_vector(0 to 63);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 62);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_0_64;
architecture DBLC_0 of DBLC_0_64 is
begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 64 generate
U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;
-- The DBLC-tree: Level 1
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_1_64 is
port
(
PIN: in std_logic_vector(0 to 62);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 60);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_1_64;
architecture DBLC_1 of DBLC_1_64 is
begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 64 generate
U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;
-- The DBLC-tree: Level 2
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_2_64 is
port
(
PIN: in std_logic_vector(0 to 60);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 56);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_2_64;
architecture DBLC_2 of DBLC_2_64 is
begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 64 generate
U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;
-- The DBLC-tree: Level 3
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_3_64 is
port
(
PIN: in std_logic_vector(0 to 56);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 48);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_3_64;
architecture DBLC_3 of DBLC_3_64 is
begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 64 generate
U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;
-- The DBLC-tree: Level 4
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_4_64 is
port
(
PIN: in std_logic_vector(0 to 48);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 32);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_4_64;
architecture DBLC_4 of DBLC_4_64 is
begin -- Architecture DBLC_4
U1: for I in 0 to 15 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 16 to 31 generate
U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 64 generate
U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;
-- The DBLC-tree: Level 5
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_5_64 is
port
(
PIN: in std_logic_vector(0 to 32);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_5_64;
architecture DBLC_5 of DBLC_5_64 is
begin -- Architecture DBLC_5
U1: for I in 0 to 31 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 32 to 63 generate
U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 64 to 64 generate
U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I));
end generate U3;
end DBLC_5;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity XORSTAGE_64 is
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
PBIT, PHI: in std_logic;
CARRY: in std_logic_vector(0 to 64);
SUM: out std_logic_vector(0 to 63);
COUT: out std_logic
);
end XORSTAGE_64;
architecture XORSTAGE of XORSTAGE_64 is
begin -- XORSTAGE
U2:for I in 0 to 63 generate
U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U1: BLOCK1A port map(PBIT,CARRY(0),CARRY(64),PHI,COUT);
end XORSTAGE;
-- The DBLC-tree: All levels encapsulated
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCTREE_64 is
port
(
PIN:in std_logic_vector(0 to 63);
GIN:in std_logic_vector(0 to 64);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 64);
POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_64;
architecture DBLCTREE of DBLCTREE_64 is
signal INTPROP_0: std_logic_vector(0 to 62);
signal INTGEN_0: std_logic_vector(0 to 64);
signal INTPROP_1: std_logic_vector(0 to 60);
signal INTGEN_1: std_logic_vector(0 to 64);
signal INTPROP_2: std_logic_vector(0 to 56);
signal INTGEN_2: std_logic_vector(0 to 64);
signal INTPROP_3: std_logic_vector(0 to 48);
signal INTGEN_3: std_logic_vector(0 to 64);
signal INTPROP_4: std_logic_vector(0 to 32);
signal INTGEN_4: std_logic_vector(0 to 64);
begin -- Architecture DBLCTREE
U_0: DBLC_0_64 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_64 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_64 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_64 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_64 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4);
U_5: DBLC_5_64 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCADDER_64_64 is
port
(
OPA:in std_logic_vector(0 to 63);
OPB:in std_logic_vector(0 to 63);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 63);
COUT:out std_logic
);
end DBLCADDER_64_64;
architecture DBLCADDER of DBLCADDER_64_64 is
signal INTPROP: std_logic_vector(0 to 63);
signal INTGEN: std_logic_vector(0 to 64);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 64);
begin -- Architecture DBLCADDER
U1: PRESTAGE_64 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_64 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_64 port map(OPA(0 to 63),OPB(0 to 63),PBIT(0),PHI,CARRY(0 to 64),SUM,COUT);
end DBLCADDER;
------------------------------------------------------------
-- END: Architectures used with the DBLC adder
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity XXOR2 is
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end XXOR2;
architecture XXOR_true of XXOR2 is
begin
SUM <= (A xor B) xor GIN;
end XXOR_true;
--
-- Modgen adder created Fri Aug 16 14:47:23 2002
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_0_32 is
port
(
PIN: in std_logic_vector(0 to 31);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 30);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_0_32;
architecture DBLC_0 of DBLC_0_32 is
begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 32 generate
U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;
-- The DBLC-tree: Level 1
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_1_32 is
port
(
PIN: in std_logic_vector(0 to 30);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 28);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_1_32;
architecture DBLC_1 of DBLC_1_32 is
begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 32 generate
U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;
-- The DBLC-tree: Level 2
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_2_32 is
port
(
PIN: in std_logic_vector(0 to 28);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 24);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_2_32;
architecture DBLC_2 of DBLC_2_32 is
begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 32 generate
U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;
-- The DBLC-tree: Level 3
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_3_32 is
port
(
PIN: in std_logic_vector(0 to 24);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 16);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_3_32;
architecture DBLC_3 of DBLC_3_32 is
begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 32 generate
U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;
-- The DBLC-tree: Level 4
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_4_32 is
port
(
PIN: in std_logic_vector(0 to 16);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_4_32;
architecture DBLC_4 of DBLC_4_32 is
begin -- Architecture DBLC_4
GOUT(0 to 15) <= GIN(0 to 15);
U2: for I in 16 to 31 generate
U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 32 generate
U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity XORSTAGE_32 is
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
PBIT, PHI: in std_logic;
CARRY: in std_logic_vector(0 to 32);
SUM: out std_logic_vector(0 to 31);
COUT: out std_logic
);
end XORSTAGE_32;
architecture XORSTAGE of XORSTAGE_32 is
begin -- XORSTAGE
U2:for I in 0 to 15 generate
U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U3:for I in 16 to 31 generate
U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U3;
U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(32),PHI,COUT);
end XORSTAGE;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity PRESTAGE_32 is
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 31);
GOUT: out std_logic_vector(0 to 32)
);
end PRESTAGE_32;
architecture PRESTAGE of PRESTAGE_32 is
begin -- PRESTAGE
U1:for I in 0 to 31 generate
U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: All levels encapsulated
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCTREE_32 is
port
(
PIN:in std_logic_vector(0 to 31);
GIN:in std_logic_vector(0 to 32);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 32);
POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_32;
architecture DBLCTREE of DBLCTREE_32 is
signal INTPROP_0: std_logic_vector(0 to 30);
signal INTGEN_0: std_logic_vector(0 to 32);
signal INTPROP_1: std_logic_vector(0 to 28);
signal INTGEN_1: std_logic_vector(0 to 32);
signal INTPROP_2: std_logic_vector(0 to 24);
signal INTGEN_2: std_logic_vector(0 to 32);
signal INTPROP_3: std_logic_vector(0 to 16);
signal INTGEN_3: std_logic_vector(0 to 32);
begin -- Architecture DBLCTREE
U_0: DBLC_0_32 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_32 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_32 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_32 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_32 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCADDER_32_32 is
port
(
OPA:in std_logic_vector(0 to 31);
OPB:in std_logic_vector(0 to 31);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 31);
COUT:out std_logic
);
end DBLCADDER_32_32;
architecture DBLCADDER of DBLCADDER_32_32 is
signal INTPROP: std_logic_vector(0 to 31);
signal INTGEN: std_logic_vector(0 to 32);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 32);
begin -- Architecture DBLCADDER
U1: PRESTAGE_32 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_32 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_32 port map(OPA(0 to 31),OPB(0 to 31),PBIT(0),PHI,CARRY(0 to 32),SUM,COUT);
end DBLCADDER;
------------------------------------------------------------
-- END: Architectures used with the DBLC adder
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity PRESTAGE_128 is
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 127);
GOUT: out std_logic_vector(0 to 128)
);
end PRESTAGE_128;
architecture PRESTAGE of PRESTAGE_128 is
begin -- PRESTAGE
U1:for I in 0 to 127 generate
U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: Level 0
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_0_128 is
port
(
PIN: in std_logic_vector(0 to 127);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 126);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_0_128;
architecture DBLC_0 of DBLC_0_128 is
begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 128 generate
U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;
-- The DBLC-tree: Level 1
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_1_128 is
port
(
PIN: in std_logic_vector(0 to 126);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 124);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_1_128;
architecture DBLC_1 of DBLC_1_128 is
begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 128 generate
U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;
-- The DBLC-tree: Level 2
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_2_128 is
port
(
PIN: in std_logic_vector(0 to 124);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 120);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_2_128;
architecture DBLC_2 of DBLC_2_128 is
begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 128 generate
U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;
-- The DBLC-tree: Level 3
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_3_128 is
port
(
PIN: in std_logic_vector(0 to 120);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 112);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_3_128;
architecture DBLC_3 of DBLC_3_128 is
begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 128 generate
U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;
-- The DBLC-tree: Level 4
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_4_128 is
port
(
PIN: in std_logic_vector(0 to 112);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 96);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_4_128;
architecture DBLC_4 of DBLC_4_128 is
begin -- Architecture DBLC_4
U1: for I in 0 to 15 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 16 to 31 generate
U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 128 generate
U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;
-- The DBLC-tree: Level 5
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_5_128 is
port
(
PIN: in std_logic_vector(0 to 96);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 64);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_5_128;
architecture DBLC_5 of DBLC_5_128 is
begin -- Architecture DBLC_5
U1: for I in 0 to 31 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 32 to 63 generate
U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 64 to 128 generate
U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I));
end generate U3;
end DBLC_5;
-- The DBLC-tree: Level 6
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_6_128 is
port
(
PIN: in std_logic_vector(0 to 64);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_6_128;
architecture DBLC_6 of DBLC_6_128 is
begin -- Architecture DBLC_6
GOUT(0 to 63) <= GIN(0 to 63);
U2: for I in 64 to 127 generate
U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 128 to 128 generate
U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I));
end generate U3;
end DBLC_6;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity XORSTAGE_128 is
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
PBIT, PHI: in std_logic;
CARRY: in std_logic_vector(0 to 128);
SUM: out std_logic_vector(0 to 127);
COUT: out std_logic
);
end XORSTAGE_128;
architecture XORSTAGE of XORSTAGE_128 is
begin -- XORSTAGE
U2:for I in 0 to 63 generate
U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U3:for I in 64 to 127 generate
U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U3;
U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT);
end XORSTAGE;
-- The DBLC-tree: All levels encapsulated
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCTREE_128 is
port
(
PIN:in std_logic_vector(0 to 127);
GIN:in std_logic_vector(0 to 128);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 128);
POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_128;
architecture DBLCTREE of DBLCTREE_128 is
signal INTPROP_0: std_logic_vector(0 to 126);
signal INTGEN_0: std_logic_vector(0 to 128);
signal INTPROP_1: std_logic_vector(0 to 124);
signal INTGEN_1: std_logic_vector(0 to 128);
signal INTPROP_2: std_logic_vector(0 to 120);
signal INTGEN_2: std_logic_vector(0 to 128);
signal INTPROP_3: std_logic_vector(0 to 112);
signal INTGEN_3: std_logic_vector(0 to 128);
signal INTPROP_4: std_logic_vector(0 to 96);
signal INTGEN_4: std_logic_vector(0 to 128);
signal INTPROP_5: std_logic_vector(0 to 64);
signal INTGEN_5: std_logic_vector(0 to 128);
begin -- Architecture DBLCTREE
U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4);
U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5);
U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCADDER_128_128 is
port
(
OPA:in std_logic_vector(0 to 127);
OPB:in std_logic_vector(0 to 127);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 127);
COUT:out std_logic
);
end DBLCADDER_128_128;
architecture DBLCADDER of DBLCADDER_128_128 is
signal INTPROP: std_logic_vector(0 to 127);
signal INTGEN: std_logic_vector(0 to 128);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 128);
begin -- Architecture DBLCADDER
U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT);
end DBLCADDER;
--
-- Modified Booth algorithm architecture
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity BOOTHCODER_18_18 is
port
(
OPA: in std_logic_vector(0 to 17);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 188)
);
end BOOTHCODER_18_18;
------------------------------------------------------------
-- END: Entities used within the Modified Booth Recoding
------------------------------------------------------------
architecture BOOTHCODER of BOOTHCODER_18_18 is
-- Components used in the architecture
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 17);
signal INT_MULTIPLIER: std_logic_vector(0 to 35);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(42)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(48)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(56)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(63)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(72)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(99)
);
SUMMAND(100) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(43)
);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(49)
);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(57)
);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(64)
);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(73)
);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(101)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(109)
);
SUMMAND(110) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(118)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(44)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(50)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(58)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(65)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(74)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(102)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(111)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(119)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(126)
);
SUMMAND(127) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(134)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(45)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(51)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(59)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(66)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(75)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(103)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(112)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(120)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(128)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(135)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(141)
);
SUMMAND(142) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(148)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(46)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(52)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(60)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(67)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(76)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(104)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(113)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(121)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(129)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(136)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(143)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(149)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(154)
);
SUMMAND(155) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(160)
);
-- Begin partial product 5
-- Begin decoder block 6
DEC_5:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23)
);
-- End decoder block 6
-- Begin partial product 6
PPL_5:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(40)
);
RGATE_5:R_GATE
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
PPBIT => SUMMAND(41)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(47)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(53)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(61)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(68)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(77)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(85)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(95)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(105)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(114)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(122)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(130)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(137)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(144)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(150)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(156)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(161)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(165)
);
SUMMAND(166) <= LOGIC_ONE;
PPH_5:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(170)
);
-- Begin partial product 6
-- Begin decoder block 7
DEC_6:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27)
);
-- End decoder block 7
-- Begin partial product 7
PPL_6:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(54)
);
RGATE_6:R_GATE
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
PPBIT => SUMMAND(55)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(62)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(69)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(78)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(86)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(96)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(106)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(115)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(123)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(131)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(138)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(145)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(151)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(157)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(162)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(167)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(171)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(174)
);
SUMMAND(175) <= LOGIC_ONE;
PPH_6:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(178)
);
-- Begin partial product 7
-- Begin decoder block 8
DEC_7:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31)
);
-- End decoder block 8
-- Begin partial product 8
PPL_7:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(70)
);
RGATE_7:R_GATE
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
PPBIT => SUMMAND(71)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(79)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(87)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(97)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(107)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(116)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(124)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(132)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(139)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(146)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(152)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(158)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(163)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(168)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(172)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(176)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(179)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(181)
);
SUMMAND(182) <= LOGIC_ONE;
PPH_7:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(184)
);
-- Begin partial product 8
-- Begin decoder block 9
DEC_8:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35)
);
-- End decoder block 9
-- Begin partial product 9
PPL_8:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(88)
);
RGATE_8:R_GATE
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
PPBIT => SUMMAND(89)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(98)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(108)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(117)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(125)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(133)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(140)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(147)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(153)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(159)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(164)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(169)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(173)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(177)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(180)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(183)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(185)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(186)
);
SUMMAND(187) <= LOGIC_ONE;
PPH_8:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(188)
);
-- Begin partial product 9
end BOOTHCODER;
------------------------------------------------------------
-- END: Architectures used with the Modified Booth recoding
------------------------------------------------------------
--
-- Wallace tree architecture
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity WALLACE_18_18 is
port
(
SUMMAND: in std_logic_vector(0 to 188);
CARRY: out std_logic_vector(0 to 33);
SUM: out std_logic_vector(0 to 34)
);
end WALLACE_18_18;
------------------------------------------------------------
-- END: Entities within the Wallace-tree
------------------------------------------------------------
architecture WALLACE of WALLACE_18_18 is
-- Components used in the netlist
-- Signals used inside the wallace trees
signal INT_CARRY: std_logic_vector(0 to 114);
signal INT_SUM: std_logic_vector(0 to 158);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End FA stage
---- Begin NO stage
INT_SUM(18) <= SUMMAND(41); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18),
SAVE => INT_SUM(19), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End HA stage
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End FA stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(23), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin NO stage
INT_SUM(24) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End FA stage
---- Begin NO stage
INT_SUM(26) <= INT_CARRY(15); -- At Level 3
---- End NO stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(25), DATA_B => INT_SUM(26),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End HA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50),
SAVE => INT_SUM(27), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin NO stage
INT_SUM(29) <= SUMMAND(54); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(30) <= SUMMAND(55); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29),
SAVE => INT_SUM(31), CARRY => INT_CARRY(22)
);
---- End FA stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17),
SAVE => INT_SUM(32), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(33), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End HA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58),
SAVE => INT_SUM(34), CARRY => INT_CARRY(25)
);
---- End FA stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61),
SAVE => INT_SUM(35), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(36) <= SUMMAND(62); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36),
SAVE => INT_SUM(37), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21),
SAVE => INT_SUM(38), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22),
SAVE => INT_SUM(39), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(40) <= INT_CARRY(23); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65),
SAVE => INT_SUM(41), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68),
SAVE => INT_SUM(42), CARRY => INT_CARRY(31)
);
---- End FA stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71),
SAVE => INT_SUM(43), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(28); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End HA stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50),
SAVE => INT_SUM(51), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32),
SAVE => INT_SUM(52), CARRY => INT_CARRY(40)
);
---- End FA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(53), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(54) <= INT_CARRY(34); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(55), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85),
SAVE => INT_SUM(56), CARRY => INT_CARRY(43)
);
---- End FA stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88),
SAVE => INT_SUM(57), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(58) <= SUMMAND(89); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57),
SAVE => INT_SUM(59), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37),
SAVE => INT_SUM(60), CARRY => INT_CARRY(46)
);
---- End FA stage
---- Begin NO stage
INT_SUM(61) <= INT_CARRY(38); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40),
SAVE => INT_SUM(63), CARRY => INT_CARRY(48)
);
---- End HA stage
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(64), CARRY => INT_CARRY(49)
);
---- End FA stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95),
SAVE => INT_SUM(65), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98),
SAVE => INT_SUM(66), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66),
SAVE => INT_SUM(67), CARRY => INT_CARRY(52)
);
---- End FA stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44),
SAVE => INT_SUM(68), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(69), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin NO stage
INT_SUM(70) <= INT_CARRY(46); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47),
SAVE => INT_SUM(71), CARRY => INT_CARRY(55)
);
---- End FA stage
---- Begin NO stage
INT_SUM(72) <= INT_CARRY(48); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(71), DATA_B => INT_SUM(72),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End HA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101),
SAVE => INT_SUM(73), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104),
SAVE => INT_SUM(74), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(75), CARRY => INT_CARRY(58)
);
---- End FA stage
---- Begin NO stage
INT_SUM(76) <= SUMMAND(108); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75),
SAVE => INT_SUM(77), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_CARRY(49), DATA_C => INT_CARRY(50),
SAVE => INT_SUM(78), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin NO stage
INT_SUM(79) <= INT_CARRY(51); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(77), DATA_B => INT_SUM(78), DATA_C => INT_SUM(79),
SAVE => INT_SUM(80), CARRY => INT_CARRY(61)
);
---- End FA stage
---- Begin NO stage
INT_SUM(81) <= INT_CARRY(52); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(82) <= INT_CARRY(53); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_SUM(82),
SAVE => INT_SUM(83), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin NO stage
INT_SUM(84) <= INT_CARRY(54); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(83), DATA_B => INT_SUM(84), DATA_C => INT_CARRY(55),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End FA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(109), DATA_B => SUMMAND(110), DATA_C => SUMMAND(111),
SAVE => INT_SUM(85), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(112), DATA_B => SUMMAND(113), DATA_C => SUMMAND(114),
SAVE => INT_SUM(86), CARRY => INT_CARRY(64)
);
---- End FA stage
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117),
SAVE => INT_SUM(87), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58),
SAVE => INT_SUM(88), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87),
SAVE => INT_SUM(89), CARRY => INT_CARRY(67)
);
---- End FA stage
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_CARRY(59), DATA_C => INT_CARRY(60),
SAVE => INT_SUM(90), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_CARRY(61),
SAVE => INT_SUM(91), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(91), DATA_B => INT_CARRY(62),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End HA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), DATA_C => SUMMAND(120),
SAVE => INT_SUM(92), CARRY => INT_CARRY(70)
);
---- End FA stage
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(121), DATA_B => SUMMAND(122), DATA_C => SUMMAND(123),
SAVE => INT_SUM(93), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin NO stage
INT_SUM(94) <= SUMMAND(124); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(95) <= SUMMAND(125); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_SUM(94),
SAVE => INT_SUM(96), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin NO stage
INT_SUM(97) <= INT_SUM(95); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(63),
SAVE => INT_SUM(98), CARRY => INT_CARRY(73)
);
---- End FA stage
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(64), DATA_B => INT_CARRY(65), DATA_C => INT_CARRY(66),
SAVE => INT_SUM(99), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(67),
SAVE => INT_SUM(100), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin NO stage
INT_SUM(101) <= INT_CARRY(68); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(69),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End FA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128),
SAVE => INT_SUM(102), CARRY => INT_CARRY(76)
);
---- End FA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131),
SAVE => INT_SUM(103), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => INT_CARRY(70),
SAVE => INT_SUM(104), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin NO stage
INT_SUM(105) <= INT_CARRY(71); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_SUM(104),
SAVE => INT_SUM(106), CARRY => INT_CARRY(79)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(105), DATA_B => INT_CARRY(72),
SAVE => INT_SUM(107), CARRY => INT_CARRY(80)
);
---- End HA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(73),
SAVE => INT_SUM(108), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin NO stage
INT_SUM(109) <= INT_CARRY(74); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(75),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End FA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(134), DATA_B => SUMMAND(135), DATA_C => SUMMAND(136),
SAVE => INT_SUM(110), CARRY => INT_CARRY(82)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(137), DATA_B => SUMMAND(138), DATA_C => SUMMAND(139),
SAVE => INT_SUM(111), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin NO stage
INT_SUM(112) <= SUMMAND(140); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_SUM(112),
SAVE => INT_SUM(113), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), DATA_C => INT_CARRY(78),
SAVE => INT_SUM(114), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_CARRY(79),
SAVE => INT_SUM(115), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin NO stage
INT_SUM(116) <= INT_CARRY(80); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(81),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End FA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143),
SAVE => INT_SUM(117), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146),
SAVE => INT_SUM(118), CARRY => INT_CARRY(88)
);
---- End FA stage
---- Begin NO stage
INT_SUM(119) <= SUMMAND(147); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_SUM(119),
SAVE => INT_SUM(120), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83),
SAVE => INT_SUM(121), CARRY => INT_CARRY(90)
);
---- End HA stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(84),
SAVE => INT_SUM(122), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin NO stage
INT_SUM(123) <= INT_CARRY(85); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(86),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End FA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), DATA_C => SUMMAND(150),
SAVE => INT_SUM(124), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(151), DATA_B => SUMMAND(152), DATA_C => SUMMAND(153),
SAVE => INT_SUM(125), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(126), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin NO stage
INT_SUM(127) <= INT_CARRY(88); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(89),
SAVE => INT_SUM(128), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin NO stage
INT_SUM(129) <= INT_CARRY(90); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(91),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End FA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_101:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(154), DATA_B => SUMMAND(155), DATA_C => SUMMAND(156),
SAVE => INT_SUM(130), CARRY => INT_CARRY(96)
);
---- End FA stage
---- Begin FA stage
FA_102:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(157), DATA_B => SUMMAND(158), DATA_C => SUMMAND(159),
SAVE => INT_SUM(131), CARRY => INT_CARRY(97)
);
---- End FA stage
---- Begin FA stage
FA_103:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), DATA_C => INT_CARRY(92),
SAVE => INT_SUM(132), CARRY => INT_CARRY(98)
);
---- End FA stage
---- Begin NO stage
INT_SUM(133) <= INT_CARRY(93); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_104:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(94),
SAVE => INT_SUM(134), CARRY => INT_CARRY(99)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(134), DATA_B => INT_CARRY(95),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End HA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_105:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(160), DATA_B => SUMMAND(161), DATA_C => SUMMAND(162),
SAVE => INT_SUM(135), CARRY => INT_CARRY(100)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(163), DATA_B => SUMMAND(164),
SAVE => INT_SUM(136), CARRY => INT_CARRY(101)
);
---- End HA stage
---- Begin FA stage
FA_106:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_CARRY(96),
SAVE => INT_SUM(137), CARRY => INT_CARRY(102)
);
---- End FA stage
---- Begin NO stage
INT_SUM(138) <= INT_CARRY(97); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_107:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_CARRY(98),
SAVE => INT_SUM(139), CARRY => INT_CARRY(103)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(139), DATA_B => INT_CARRY(99),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End HA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_108:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167),
SAVE => INT_SUM(140), CARRY => INT_CARRY(104)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(168), DATA_B => SUMMAND(169),
SAVE => INT_SUM(141), CARRY => INT_CARRY(105)
);
---- End HA stage
---- Begin FA stage
FA_109:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(100),
SAVE => INT_SUM(142), CARRY => INT_CARRY(106)
);
---- End FA stage
---- Begin NO stage
INT_SUM(143) <= INT_CARRY(101); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_110:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(102),
SAVE => INT_SUM(144), CARRY => INT_CARRY(107)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(144), DATA_B => INT_CARRY(103),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End HA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_111:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172),
SAVE => INT_SUM(145), CARRY => INT_CARRY(108)
);
---- End FA stage
---- Begin FA stage
FA_112:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(173), DATA_B => INT_CARRY(104), DATA_C => INT_CARRY(105),
SAVE => INT_SUM(146), CARRY => INT_CARRY(109)
);
---- End FA stage
---- Begin FA stage
FA_113:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(106),
SAVE => INT_SUM(147), CARRY => INT_CARRY(110)
);
---- End FA stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(147), DATA_B => INT_CARRY(107),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End HA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_114:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(148), CARRY => INT_CARRY(111)
);
---- End FA stage
---- Begin NO stage
INT_SUM(149) <= SUMMAND(177); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_115:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(108),
SAVE => INT_SUM(150), CARRY => INT_CARRY(112)
);
---- End FA stage
---- Begin NO stage
INT_SUM(151) <= INT_CARRY(109); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_116:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(110),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End FA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_117:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(178), DATA_B => SUMMAND(179), DATA_C => SUMMAND(180),
SAVE => INT_SUM(152), CARRY => INT_CARRY(113)
);
---- End FA stage
---- Begin NO stage
INT_SUM(153) <= INT_SUM(152); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(154) <= INT_CARRY(111); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_118:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_CARRY(112),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End FA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_119:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(181), DATA_B => SUMMAND(182), DATA_C => SUMMAND(183),
SAVE => INT_SUM(155), CARRY => INT_CARRY(114)
);
---- End FA stage
---- Begin NO stage
INT_SUM(156) <= INT_CARRY(113); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(155), DATA_B => INT_SUM(156),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End HA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin NO stage
INT_SUM(157) <= SUMMAND(184); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(158) <= SUMMAND(185); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_120:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(114),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End FA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 5
port map
(
DATA_A => SUMMAND(186), DATA_B => SUMMAND(187),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End HA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin NO stage
SUM(34) <= SUMMAND(188); -- At Level 5
---- End NO stage
-- End WT-branch 35
end WALLACE;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MULTIPLIER_18_18 is
generic (mulpipe : integer := 0);
port
(
MULTIPLICAND: in std_logic_vector(0 to 17);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_ulogic;
holdn: in std_ulogic;
RESULT: out std_logic_vector(0 to 63)
);
end MULTIPLIER_18_18;
architecture MULTIPLIER of MULTIPLIER_18_18 is
signal PPBIT:std_logic_vector(0 to 188);
signal INT_CARRY: std_logic_vector(0 to 64);
signal INT_CARRYR: std_logic_vector(0 to 64);
signal INT_SUM: std_logic_vector(0 to 63);
signal INT_SUMR: std_logic_vector(0 to 63);
signal LOGIC_ZERO: std_logic;
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_18_18
port map
(
OPA(0 to 17) => MULTIPLICAND(0 to 17),
OPB(0 to 17) => MULTIPLIER(0 to 17),
SUMMAND(0 to 188) => PPBIT(0 to 188)
);
W:WALLACE_18_18
port map
(
SUMMAND(0 to 188) => PPBIT(0 to 188),
CARRY(0 to 33) => INT_CARRY(1 to 34),
SUM(0 to 34) => INT_SUM(0 to 34)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(35) <= LOGIC_ZERO;
INT_CARRY(36) <= LOGIC_ZERO;
INT_CARRY(37) <= LOGIC_ZERO;
INT_CARRY(38) <= LOGIC_ZERO;
INT_CARRY(39) <= LOGIC_ZERO;
INT_CARRY(40) <= LOGIC_ZERO;
INT_CARRY(41) <= LOGIC_ZERO;
INT_CARRY(42) <= LOGIC_ZERO;
INT_CARRY(43) <= LOGIC_ZERO;
INT_CARRY(44) <= LOGIC_ZERO;
INT_CARRY(45) <= LOGIC_ZERO;
INT_CARRY(46) <= LOGIC_ZERO;
INT_CARRY(47) <= LOGIC_ZERO;
INT_CARRY(48) <= LOGIC_ZERO;
INT_CARRY(49) <= LOGIC_ZERO;
INT_CARRY(50) <= LOGIC_ZERO;
INT_CARRY(51) <= LOGIC_ZERO;
INT_CARRY(52) <= LOGIC_ZERO;
INT_CARRY(53) <= LOGIC_ZERO;
INT_CARRY(54) <= LOGIC_ZERO;
INT_CARRY(55) <= LOGIC_ZERO;
INT_CARRY(56) <= LOGIC_ZERO;
INT_CARRY(57) <= LOGIC_ZERO;
INT_CARRY(58) <= LOGIC_ZERO;
INT_CARRY(59) <= LOGIC_ZERO;
INT_CARRY(60) <= LOGIC_ZERO;
INT_CARRY(61) <= LOGIC_ZERO;
INT_CARRY(62) <= LOGIC_ZERO;
INT_CARRY(63) <= LOGIC_ZERO;
INT_SUM(35) <= LOGIC_ZERO;
INT_SUM(36) <= LOGIC_ZERO;
INT_SUM(37) <= LOGIC_ZERO;
INT_SUM(38) <= LOGIC_ZERO;
INT_SUM(39) <= LOGIC_ZERO;
INT_SUM(40) <= LOGIC_ZERO;
INT_SUM(41) <= LOGIC_ZERO;
INT_SUM(42) <= LOGIC_ZERO;
INT_SUM(43) <= LOGIC_ZERO;
INT_SUM(44) <= LOGIC_ZERO;
INT_SUM(45) <= LOGIC_ZERO;
INT_SUM(46) <= LOGIC_ZERO;
INT_SUM(47) <= LOGIC_ZERO;
INT_SUM(48) <= LOGIC_ZERO;
INT_SUM(49) <= LOGIC_ZERO;
INT_SUM(50) <= LOGIC_ZERO;
INT_SUM(51) <= LOGIC_ZERO;
INT_SUM(52) <= LOGIC_ZERO;
INT_SUM(53) <= LOGIC_ZERO;
INT_SUM(54) <= LOGIC_ZERO;
INT_SUM(55) <= LOGIC_ZERO;
INT_SUM(56) <= LOGIC_ZERO;
INT_SUM(57) <= LOGIC_ZERO;
INT_SUM(58) <= LOGIC_ZERO;
INT_SUM(59) <= LOGIC_ZERO;
INT_SUM(60) <= LOGIC_ZERO;
INT_SUM(61) <= LOGIC_ZERO;
INT_SUM(62) <= LOGIC_ZERO;
INT_SUM(63) <= LOGIC_ZERO;
INT_SUMR(35 to 63) <= INT_SUM(35 to 63);
INT_CARRYR(35 to 63) <= INT_CARRY(35 to 63);
INT_CARRYR(0) <= INT_CARRY(0);
reg : if MULPIPE /= 0 generate
process (PHI) begin
if rising_edge(PHI ) then
if (holdn = '1') then
INT_SUMR(0 to 34) <= INT_SUM(0 to 34);
INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34);
end if;
end if;
end process;
end generate;
noreg : if MULPIPE = 0 generate
INT_SUMR(0 to 34) <= INT_SUM(0 to 34);
INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34);
end generate;
D:DBLCADDER_64_64
port map
(
OPA(0 to 63) => INT_SUMR(0 to 63),
OPB(0 to 63) => INT_CARRYR(0 to 63),
CIN => LOGIC_ZERO,
PHI => PHI ,
SUM(0 to 63) => RESULT(0 to 63)
);
end MULTIPLIER;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity BOOTHCODER_34_10 is
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 9);
SUMMAND: out std_logic_vector(0 to 184)
);
end BOOTHCODER_34_10;
architecture BOOTHCODER of BOOTHCODER_34_10 is
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 33);
signal INT_MULTIPLIER: std_logic_vector(0 to 19);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(40)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(45)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(50)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(55)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(60)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(65)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(70)
);
INV_MULTIPLICAND(18) <= NOT OPA(18);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(75)
);
INV_MULTIPLICAND(19) <= NOT OPA(19);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(20) <= NOT OPA(20);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(85)
);
INV_MULTIPLICAND(21) <= NOT OPA(21);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
INV_MULTIPLICAND(22) <= NOT OPA(22);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(95)
);
INV_MULTIPLICAND(23) <= NOT OPA(23);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(100)
);
INV_MULTIPLICAND(24) <= NOT OPA(24);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(105)
);
INV_MULTIPLICAND(25) <= NOT OPA(25);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(110)
);
INV_MULTIPLICAND(26) <= NOT OPA(26);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(115)
);
INV_MULTIPLICAND(27) <= NOT OPA(27);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(120)
);
INV_MULTIPLICAND(28) <= NOT OPA(28);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(125)
);
INV_MULTIPLICAND(29) <= NOT OPA(29);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(130)
);
INV_MULTIPLICAND(30) <= NOT OPA(30);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(135)
);
INV_MULTIPLICAND(31) <= NOT OPA(31);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(140)
);
INV_MULTIPLICAND(32) <= NOT OPA(32);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(145)
);
INV_MULTIPLICAND(33) <= NOT OPA(33);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(150)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(155)
);
SUMMAND(156) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(41)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(46)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(51)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(56)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(61)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(66)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(71)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(76)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(86)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(96)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(101)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(106)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(111)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(116)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(121)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(126)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(131)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(136)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(141)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(146)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(151)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(157)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(161)
);
SUMMAND(162) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(166)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(42)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(47)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(52)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(57)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(62)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(67)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(72)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(77)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(87)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(97)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(102)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(107)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(112)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(117)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(122)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(127)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(132)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(137)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(142)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(147)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(152)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(158)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(163)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(167)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(170)
);
SUMMAND(171) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(174)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(43)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(48)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(53)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(58)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(63)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(68)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(73)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(78)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(88)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(98)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(103)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(108)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(113)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(118)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(123)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(128)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(133)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(138)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(143)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(148)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(153)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(159)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(164)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(168)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(172)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(175)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(177)
);
SUMMAND(178) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(180)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(44)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(49)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(54)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(59)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(64)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(69)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(74)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(79)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(89)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(99)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(104)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(109)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(114)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(119)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(124)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(129)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(134)
);
PPM_153:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(139)
);
PPM_154:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(144)
);
PPM_155:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(149)
);
PPM_156:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(154)
);
PPM_157:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(160)
);
PPM_158:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(165)
);
PPM_159:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(169)
);
PPM_160:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(173)
);
PPM_161:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(176)
);
PPM_162:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(179)
);
PPM_163:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(181)
);
PPM_164:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(182)
);
SUMMAND(183) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(184)
);
-- Begin partial product 5
end BOOTHCODER;
------------------------------------------------------------
-- END: Architectures used with the Modified Booth recoding
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the Wallace-tree
------------------------------------------------------------
--
-- Wallace tree architecture
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity WALLACE_34_10 is
port
(
SUMMAND: in std_logic_vector(0 to 184);
CARRY: out std_logic_vector(0 to 41);
SUM: out std_logic_vector(0 to 42)
);
end WALLACE_34_10;
architecture WALLACE of WALLACE_34_10 is
signal INT_CARRY: std_logic_vector(0 to 95);
signal INT_SUM: std_logic_vector(0 to 133);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End HA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_CARRY(9),
SAVE => INT_SUM(18), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin NO stage
INT_SUM(19) <= INT_CARRY(10); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(18), DATA_B => INT_SUM(19), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(40), DATA_B => SUMMAND(41), DATA_C => SUMMAND(42),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End FA stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(43), DATA_B => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End HA stage
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(20), DATA_B => INT_SUM(21), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin NO stage
INT_SUM(23) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(22), DATA_B => INT_SUM(23), DATA_C => INT_CARRY(14),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End FA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(24), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End HA stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(24), DATA_B => INT_SUM(25), DATA_C => INT_CARRY(15),
SAVE => INT_SUM(26), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin NO stage
INT_SUM(27) <= INT_CARRY(16); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(26), DATA_B => INT_SUM(27), DATA_C => INT_CARRY(17),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End FA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(50), DATA_B => SUMMAND(51), DATA_C => SUMMAND(52),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(53), DATA_B => SUMMAND(54),
SAVE => INT_SUM(29), CARRY => INT_CARRY(22)
);
---- End HA stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(28), DATA_B => INT_SUM(29), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(30), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin NO stage
INT_SUM(31) <= INT_CARRY(19); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_SUM(31), DATA_C => INT_CARRY(20),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(55), DATA_B => SUMMAND(56), DATA_C => SUMMAND(57),
SAVE => INT_SUM(32), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(58), DATA_B => SUMMAND(59),
SAVE => INT_SUM(33), CARRY => INT_CARRY(25)
);
---- End HA stage
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(32), DATA_B => INT_SUM(33), DATA_C => INT_CARRY(21),
SAVE => INT_SUM(34), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(35) <= INT_CARRY(22); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_CARRY(23),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(60), DATA_B => SUMMAND(61), DATA_C => SUMMAND(62),
SAVE => INT_SUM(36), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64),
SAVE => INT_SUM(37), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(36), DATA_B => INT_SUM(37), DATA_C => INT_CARRY(24),
SAVE => INT_SUM(38), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(39) <= INT_CARRY(25); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(38), DATA_B => INT_SUM(39), DATA_C => INT_CARRY(26),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(65), DATA_B => SUMMAND(66), DATA_C => SUMMAND(67),
SAVE => INT_SUM(40), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(68), DATA_B => SUMMAND(69),
SAVE => INT_SUM(41), CARRY => INT_CARRY(31)
);
---- End HA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(40), DATA_B => INT_SUM(41), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(42), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin NO stage
INT_SUM(43) <= INT_CARRY(28); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(42), DATA_B => INT_SUM(43), DATA_C => INT_CARRY(29),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(70), DATA_B => SUMMAND(71), DATA_C => SUMMAND(72),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(73), DATA_B => SUMMAND(74),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(30),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(31); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(32),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End FA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End HA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End FA stage
---- Begin NO stage
INT_SUM(51) <= INT_CARRY(34); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(50), DATA_B => INT_SUM(51), DATA_C => INT_CARRY(35),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End FA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(52), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84),
SAVE => INT_SUM(53), CARRY => INT_CARRY(40)
);
---- End HA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(52), DATA_B => INT_SUM(53), DATA_C => INT_CARRY(36),
SAVE => INT_SUM(54), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(55) <= INT_CARRY(37); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(54), DATA_B => INT_SUM(55), DATA_C => INT_CARRY(38),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End FA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(85), DATA_B => SUMMAND(86), DATA_C => SUMMAND(87),
SAVE => INT_SUM(56), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(88), DATA_B => SUMMAND(89),
SAVE => INT_SUM(57), CARRY => INT_CARRY(43)
);
---- End HA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(56), DATA_B => INT_SUM(57), DATA_C => INT_CARRY(39),
SAVE => INT_SUM(58), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(59) <= INT_CARRY(40); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_SUM(59), DATA_C => INT_CARRY(41),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End FA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(60), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94),
SAVE => INT_SUM(61), CARRY => INT_CARRY(46)
);
---- End HA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(60), DATA_B => INT_SUM(61), DATA_C => INT_CARRY(42),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin NO stage
INT_SUM(63) <= INT_CARRY(43); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(44),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End FA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(95), DATA_B => SUMMAND(96), DATA_C => SUMMAND(97),
SAVE => INT_SUM(64), CARRY => INT_CARRY(48)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(98), DATA_B => SUMMAND(99),
SAVE => INT_SUM(65), CARRY => INT_CARRY(49)
);
---- End HA stage
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(66), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin NO stage
INT_SUM(67) <= INT_CARRY(46); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(66), DATA_B => INT_SUM(67), DATA_C => INT_CARRY(47),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End FA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(100), DATA_B => SUMMAND(101), DATA_C => SUMMAND(102),
SAVE => INT_SUM(68), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(103), DATA_B => SUMMAND(104),
SAVE => INT_SUM(69), CARRY => INT_CARRY(52)
);
---- End HA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(68), DATA_B => INT_SUM(69), DATA_C => INT_CARRY(48),
SAVE => INT_SUM(70), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin NO stage
INT_SUM(71) <= INT_CARRY(49); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(70), DATA_B => INT_SUM(71), DATA_C => INT_CARRY(50),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End FA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(72), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(108), DATA_B => SUMMAND(109),
SAVE => INT_SUM(73), CARRY => INT_CARRY(55)
);
---- End HA stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(72), DATA_B => INT_SUM(73), DATA_C => INT_CARRY(51),
SAVE => INT_SUM(74), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin NO stage
INT_SUM(75) <= INT_CARRY(52); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(74), DATA_B => INT_SUM(75), DATA_C => INT_CARRY(53),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End FA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112),
SAVE => INT_SUM(76), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(113), DATA_B => SUMMAND(114),
SAVE => INT_SUM(77), CARRY => INT_CARRY(58)
);
---- End HA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(54),
SAVE => INT_SUM(78), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin NO stage
INT_SUM(79) <= INT_CARRY(55); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(56),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End FA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117),
SAVE => INT_SUM(80), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(118), DATA_B => SUMMAND(119),
SAVE => INT_SUM(81), CARRY => INT_CARRY(61)
);
---- End HA stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_CARRY(57),
SAVE => INT_SUM(82), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin NO stage
INT_SUM(83) <= INT_CARRY(58); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(59),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End FA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122),
SAVE => INT_SUM(84), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(123), DATA_B => SUMMAND(124),
SAVE => INT_SUM(85), CARRY => INT_CARRY(64)
);
---- End HA stage
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(60),
SAVE => INT_SUM(86), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin NO stage
INT_SUM(87) <= INT_CARRY(61); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(62),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End FA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(125), DATA_B => SUMMAND(126), DATA_C => SUMMAND(127),
SAVE => INT_SUM(88), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(128), DATA_B => SUMMAND(129),
SAVE => INT_SUM(89), CARRY => INT_CARRY(67)
);
---- End HA stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_SUM(89), DATA_C => INT_CARRY(63),
SAVE => INT_SUM(90), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin NO stage
INT_SUM(91) <= INT_CARRY(64); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(90), DATA_B => INT_SUM(91), DATA_C => INT_CARRY(65),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End FA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(130), DATA_B => SUMMAND(131), DATA_C => SUMMAND(132),
SAVE => INT_SUM(92), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_27:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(133), DATA_B => SUMMAND(134),
SAVE => INT_SUM(93), CARRY => INT_CARRY(70)
);
---- End HA stage
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66),
SAVE => INT_SUM(94), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin NO stage
INT_SUM(95) <= INT_CARRY(67); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End FA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137),
SAVE => INT_SUM(96), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin HA stage
HA_28:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(138), DATA_B => SUMMAND(139),
SAVE => INT_SUM(97), CARRY => INT_CARRY(73)
);
---- End HA stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(69),
SAVE => INT_SUM(98), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin NO stage
INT_SUM(99) <= INT_CARRY(70); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(71),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End FA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(140), DATA_B => SUMMAND(141), DATA_C => SUMMAND(142),
SAVE => INT_SUM(100), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin HA stage
HA_29:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(143), DATA_B => SUMMAND(144),
SAVE => INT_SUM(101), CARRY => INT_CARRY(76)
);
---- End HA stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(72),
SAVE => INT_SUM(102), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin NO stage
INT_SUM(103) <= INT_CARRY(73); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(74),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End FA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(145), DATA_B => SUMMAND(146), DATA_C => SUMMAND(147),
SAVE => INT_SUM(104), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin HA stage
HA_30:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(148), DATA_B => SUMMAND(149),
SAVE => INT_SUM(105), CARRY => INT_CARRY(79)
);
---- End HA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(104), DATA_B => INT_SUM(105), DATA_C => INT_CARRY(75),
SAVE => INT_SUM(106), CARRY => INT_CARRY(80)
);
---- End FA stage
---- Begin NO stage
INT_SUM(107) <= INT_CARRY(76); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(77),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End FA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152),
SAVE => INT_SUM(108), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin HA stage
HA_31:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(153), DATA_B => SUMMAND(154),
SAVE => INT_SUM(109), CARRY => INT_CARRY(82)
);
---- End HA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(78),
SAVE => INT_SUM(110), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin NO stage
INT_SUM(111) <= INT_CARRY(79); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(80),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End FA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(155), DATA_B => SUMMAND(156), DATA_C => SUMMAND(157),
SAVE => INT_SUM(112), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(158), DATA_B => SUMMAND(159), DATA_C => SUMMAND(160),
SAVE => INT_SUM(113), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_CARRY(81),
SAVE => INT_SUM(114), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin NO stage
INT_SUM(115) <= INT_CARRY(82); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(114), DATA_B => INT_SUM(115), DATA_C => INT_CARRY(83),
SAVE => SUM(34), CARRY => CARRY(34)
);
---- End FA stage
-- End WT-branch 35
-- Begin WT-branch 36
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(161), DATA_B => SUMMAND(162), DATA_C => SUMMAND(163),
SAVE => INT_SUM(116), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin HA stage
HA_32:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(164), DATA_B => SUMMAND(165),
SAVE => INT_SUM(117), CARRY => INT_CARRY(88)
);
---- End HA stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(84),
SAVE => INT_SUM(118), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin NO stage
INT_SUM(119) <= INT_CARRY(85); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(86),
SAVE => SUM(35), CARRY => CARRY(35)
);
---- End FA stage
-- End WT-branch 36
-- Begin WT-branch 37
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(166), DATA_B => SUMMAND(167), DATA_C => SUMMAND(168),
SAVE => INT_SUM(120), CARRY => INT_CARRY(90)
);
---- End FA stage
---- Begin NO stage
INT_SUM(121) <= SUMMAND(169); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(122), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin NO stage
INT_SUM(123) <= INT_CARRY(88); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(89),
SAVE => SUM(36), CARRY => CARRY(36)
);
---- End FA stage
-- End WT-branch 37
-- Begin WT-branch 38
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172),
SAVE => INT_SUM(124), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin NO stage
INT_SUM(125) <= SUMMAND(173); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(90),
SAVE => INT_SUM(126), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin HA stage
HA_33:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(126), DATA_B => INT_CARRY(91),
SAVE => SUM(37), CARRY => CARRY(37)
);
---- End HA stage
-- End WT-branch 38
-- Begin WT-branch 39
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(127), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin NO stage
INT_SUM(128) <= INT_SUM(127); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(129) <= INT_CARRY(92); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(93),
SAVE => SUM(38), CARRY => CARRY(38)
);
---- End FA stage
-- End WT-branch 39
-- Begin WT-branch 40
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179),
SAVE => INT_SUM(130), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin NO stage
INT_SUM(131) <= INT_CARRY(94); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_34:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(130), DATA_B => INT_SUM(131),
SAVE => SUM(39), CARRY => CARRY(39)
);
---- End HA stage
-- End WT-branch 40
-- Begin WT-branch 41
---- Begin NO stage
INT_SUM(132) <= SUMMAND(180); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(133) <= SUMMAND(181); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(95),
SAVE => SUM(40), CARRY => CARRY(40)
);
---- End FA stage
-- End WT-branch 41
-- Begin WT-branch 42
---- Begin HA stage
HA_35:HALF_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(182), DATA_B => SUMMAND(183),
SAVE => SUM(41), CARRY => CARRY(41)
);
---- End HA stage
-- End WT-branch 42
-- Begin WT-branch 43
---- Begin NO stage
SUM(42) <= SUMMAND(184); -- At Level 3
---- End NO stage
-- End WT-branch 43
end WALLACE;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MULTIPLIER_34_10 is
port
(
MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 9);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63)
);
end MULTIPLIER_34_10;
------------------------------------------------------------
-- End: Multiplier Entitiy
architecture MULTIPLIER of MULTIPLIER_34_10 is
signal PPBIT:std_logic_vector(0 to 184);
signal INT_CARRY: std_logic_vector(0 to 64);
signal INT_SUM: std_logic_vector(0 to 63);
signal LOGIC_ZERO: std_logic;
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_34_10
port map
(
OPA(0 to 33) => MULTIPLICAND(0 to 33),
OPB(0 to 9) => MULTIPLIER(0 to 9),
SUMMAND(0 to 184) => PPBIT(0 to 184)
);
W:WALLACE_34_10
port map
(
SUMMAND(0 to 184) => PPBIT(0 to 184),
CARRY(0 to 41) => INT_CARRY(1 to 42),
SUM(0 to 42) => INT_SUM(0 to 42)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(43) <= LOGIC_ZERO;
INT_CARRY(44) <= LOGIC_ZERO;
INT_CARRY(45) <= LOGIC_ZERO;
INT_CARRY(46) <= LOGIC_ZERO;
INT_CARRY(47) <= LOGIC_ZERO;
INT_CARRY(48) <= LOGIC_ZERO;
INT_CARRY(49) <= LOGIC_ZERO;
INT_CARRY(50) <= LOGIC_ZERO;
INT_CARRY(51) <= LOGIC_ZERO;
INT_CARRY(52) <= LOGIC_ZERO;
INT_CARRY(53) <= LOGIC_ZERO;
INT_CARRY(54) <= LOGIC_ZERO;
INT_CARRY(55) <= LOGIC_ZERO;
INT_CARRY(56) <= LOGIC_ZERO;
INT_CARRY(57) <= LOGIC_ZERO;
INT_CARRY(58) <= LOGIC_ZERO;
INT_CARRY(59) <= LOGIC_ZERO;
INT_CARRY(60) <= LOGIC_ZERO;
INT_CARRY(61) <= LOGIC_ZERO;
INT_CARRY(62) <= LOGIC_ZERO;
INT_CARRY(63) <= LOGIC_ZERO;
INT_SUM(43) <= LOGIC_ZERO;
INT_SUM(44) <= LOGIC_ZERO;
INT_SUM(45) <= LOGIC_ZERO;
INT_SUM(46) <= LOGIC_ZERO;
INT_SUM(47) <= LOGIC_ZERO;
INT_SUM(48) <= LOGIC_ZERO;
INT_SUM(49) <= LOGIC_ZERO;
INT_SUM(50) <= LOGIC_ZERO;
INT_SUM(51) <= LOGIC_ZERO;
INT_SUM(52) <= LOGIC_ZERO;
INT_SUM(53) <= LOGIC_ZERO;
INT_SUM(54) <= LOGIC_ZERO;
INT_SUM(55) <= LOGIC_ZERO;
INT_SUM(56) <= LOGIC_ZERO;
INT_SUM(57) <= LOGIC_ZERO;
INT_SUM(58) <= LOGIC_ZERO;
INT_SUM(59) <= LOGIC_ZERO;
INT_SUM(60) <= LOGIC_ZERO;
INT_SUM(61) <= LOGIC_ZERO;
INT_SUM(62) <= LOGIC_ZERO;
INT_SUM(63) <= LOGIC_ZERO;
D:DBLCADDER_64_64
port map
(
OPA(0 to 63) => INT_SUM(0 to 63),
OPB(0 to 63) => INT_CARRY(0 to 63),
CIN => LOGIC_ZERO,
PHI => PHI,
SUM(0 to 63) => RESULT(0 to 63)
);
end MULTIPLIER;
------------------------------------------------------------
-- END: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MUL_33_9 is
port(X: in std_logic_vector(32 downto 0);
Y: in std_logic_vector(8 downto 0);
P: out std_logic_vector(41 downto 0));
end MUL_33_9;
library ieee;
use ieee.std_logic_1164.all;
architecture A of MUL_33_9 is
signal A: std_logic_vector(0 to 33);
signal B: std_logic_vector(0 to 9);
signal Q: std_logic_vector(0 to 63);
signal CLK: std_logic;
begin
U1: MULTIPLIER_34_10 port map(A,B,CLK,Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(17);
A(18) <= X(18);
A(19) <= X(19);
A(20) <= X(20);
A(21) <= X(21);
A(22) <= X(22);
A(23) <= X(23);
A(24) <= X(24);
A(25) <= X(25);
A(26) <= X(26);
A(27) <= X(27);
A(28) <= X(28);
A(29) <= X(29);
A(30) <= X(30);
A(31) <= X(31);
A(32) <= X(32);
A(33) <= X(32);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(8);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
P(34) <= Q(34);
P(35) <= Q(35);
P(36) <= Q(36);
P(37) <= Q(37);
P(38) <= Q(38);
P(39) <= Q(39);
P(40) <= Q(40);
P(41) <= Q(41);
end A;
------------------------------------------------------------
-- START: Entities within the Wallace-tree
------------------------------------------------------------
--
-- Modified Booth algorithm architecture
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity BOOTHCODER_34_18 is
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 332)
);
end BOOTHCODER_34_18;
architecture BOOTHCODER of BOOTHCODER_34_18 is
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 33);
signal INT_MULTIPLIER: std_logic_vector(0 to 35);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(42)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(48)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(56)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(63)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(72)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
INV_MULTIPLICAND(18) <= NOT OPA(18);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(99)
);
INV_MULTIPLICAND(19) <= NOT OPA(19);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(108)
);
INV_MULTIPLICAND(20) <= NOT OPA(20);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(117)
);
INV_MULTIPLICAND(21) <= NOT OPA(21);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(126)
);
INV_MULTIPLICAND(22) <= NOT OPA(22);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(135)
);
INV_MULTIPLICAND(23) <= NOT OPA(23);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(144)
);
INV_MULTIPLICAND(24) <= NOT OPA(24);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(153)
);
INV_MULTIPLICAND(25) <= NOT OPA(25);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(162)
);
INV_MULTIPLICAND(26) <= NOT OPA(26);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(171)
);
INV_MULTIPLICAND(27) <= NOT OPA(27);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(180)
);
INV_MULTIPLICAND(28) <= NOT OPA(28);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(189)
);
INV_MULTIPLICAND(29) <= NOT OPA(29);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(198)
);
INV_MULTIPLICAND(30) <= NOT OPA(30);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(207)
);
INV_MULTIPLICAND(31) <= NOT OPA(31);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(216)
);
INV_MULTIPLICAND(32) <= NOT OPA(32);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(225)
);
INV_MULTIPLICAND(33) <= NOT OPA(33);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(234)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(243)
);
SUMMAND(244) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(43)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(49)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(57)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(64)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(73)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(100)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(109)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(118)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(127)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(136)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(145)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(154)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(163)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(172)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(181)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(190)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(199)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(208)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(217)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(226)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(235)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(245)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(253)
);
SUMMAND(254) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(262)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(44)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(50)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(58)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(65)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(74)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(101)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(110)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(119)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(128)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(137)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(146)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(155)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(164)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(173)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(182)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(191)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(200)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(209)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(218)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(227)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(236)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(246)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(255)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(263)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(270)
);
SUMMAND(271) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(278)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(45)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(51)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(59)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(66)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(75)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(102)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(111)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(120)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(129)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(138)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(147)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(156)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(165)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(174)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(183)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(192)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(201)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(210)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(219)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(228)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(237)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(247)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(256)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(264)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(272)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(279)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(285)
);
SUMMAND(286) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(292)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(46)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(52)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(60)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(67)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(76)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(103)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(112)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(121)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(130)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(139)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(148)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(157)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(166)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(175)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(184)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(193)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(202)
);
PPM_153:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(211)
);
PPM_154:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(220)
);
PPM_155:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(229)
);
PPM_156:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(238)
);
PPM_157:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(248)
);
PPM_158:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(257)
);
PPM_159:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(265)
);
PPM_160:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(273)
);
PPM_161:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(280)
);
PPM_162:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(287)
);
PPM_163:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(293)
);
PPM_164:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(298)
);
SUMMAND(299) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(304)
);
-- Begin partial product 5
-- Begin decoder block 6
DEC_5:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23)
);
-- End decoder block 6
-- Begin partial product 6
PPL_5:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(40)
);
RGATE_5:R_GATE
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
PPBIT => SUMMAND(41)
);
PPM_165:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(47)
);
PPM_166:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(53)
);
PPM_167:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(61)
);
PPM_168:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(68)
);
PPM_169:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(77)
);
PPM_170:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(85)
);
PPM_171:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(95)
);
PPM_172:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(104)
);
PPM_173:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(113)
);
PPM_174:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(122)
);
PPM_175:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(131)
);
PPM_176:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(140)
);
PPM_177:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(149)
);
PPM_178:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(158)
);
PPM_179:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(167)
);
PPM_180:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(176)
);
PPM_181:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(185)
);
PPM_182:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(194)
);
PPM_183:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(203)
);
PPM_184:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(212)
);
PPM_185:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(221)
);
PPM_186:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(230)
);
PPM_187:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(239)
);
PPM_188:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(249)
);
PPM_189:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(258)
);
PPM_190:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(266)
);
PPM_191:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(274)
);
PPM_192:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(281)
);
PPM_193:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(288)
);
PPM_194:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(294)
);
PPM_195:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(300)
);
PPM_196:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(305)
);
PPM_197:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(309)
);
SUMMAND(310) <= LOGIC_ONE;
PPH_5:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(314)
);
-- Begin partial product 6
-- Begin decoder block 7
DEC_6:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27)
);
-- End decoder block 7
-- Begin partial product 7
PPL_6:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(54)
);
RGATE_6:R_GATE
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
PPBIT => SUMMAND(55)
);
PPM_198:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(62)
);
PPM_199:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(69)
);
PPM_200:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(78)
);
PPM_201:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(86)
);
PPM_202:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(96)
);
PPM_203:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(105)
);
PPM_204:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(114)
);
PPM_205:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(123)
);
PPM_206:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(132)
);
PPM_207:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(141)
);
PPM_208:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(150)
);
PPM_209:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(159)
);
PPM_210:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(168)
);
PPM_211:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(177)
);
PPM_212:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(186)
);
PPM_213:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(195)
);
PPM_214:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(204)
);
PPM_215:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(213)
);
PPM_216:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(222)
);
PPM_217:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(231)
);
PPM_218:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(240)
);
PPM_219:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(250)
);
PPM_220:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(259)
);
PPM_221:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(267)
);
PPM_222:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(275)
);
PPM_223:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(282)
);
PPM_224:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(289)
);
PPM_225:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(295)
);
PPM_226:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(301)
);
PPM_227:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(306)
);
PPM_228:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(311)
);
PPM_229:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(315)
);
PPM_230:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(318)
);
SUMMAND(319) <= LOGIC_ONE;
PPH_6:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(322)
);
-- Begin partial product 7
-- Begin decoder block 8
DEC_7:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31)
);
-- End decoder block 8
-- Begin partial product 8
PPL_7:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(70)
);
RGATE_7:R_GATE
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
PPBIT => SUMMAND(71)
);
PPM_231:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(79)
);
PPM_232:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(87)
);
PPM_233:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(97)
);
PPM_234:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(106)
);
PPM_235:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(115)
);
PPM_236:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(124)
);
PPM_237:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(133)
);
PPM_238:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(142)
);
PPM_239:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(151)
);
PPM_240:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(160)
);
PPM_241:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(169)
);
PPM_242:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(178)
);
PPM_243:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(187)
);
PPM_244:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(196)
);
PPM_245:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(205)
);
PPM_246:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(214)
);
PPM_247:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(223)
);
PPM_248:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(232)
);
PPM_249:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(241)
);
PPM_250:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(251)
);
PPM_251:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(260)
);
PPM_252:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(268)
);
PPM_253:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(276)
);
PPM_254:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(283)
);
PPM_255:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(290)
);
PPM_256:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(296)
);
PPM_257:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(302)
);
PPM_258:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(307)
);
PPM_259:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(312)
);
PPM_260:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(316)
);
PPM_261:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(320)
);
PPM_262:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(323)
);
PPM_263:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(325)
);
SUMMAND(326) <= LOGIC_ONE;
PPH_7:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(328)
);
-- Begin partial product 8
-- Begin decoder block 9
DEC_8:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35)
);
-- End decoder block 9
-- Begin partial product 9
PPL_8:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(88)
);
RGATE_8:R_GATE
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
PPBIT => SUMMAND(89)
);
PPM_264:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(98)
);
PPM_265:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(107)
);
PPM_266:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(116)
);
PPM_267:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(125)
);
PPM_268:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(134)
);
PPM_269:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(143)
);
PPM_270:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(152)
);
PPM_271:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(161)
);
PPM_272:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(170)
);
PPM_273:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(179)
);
PPM_274:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(188)
);
PPM_275:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(197)
);
PPM_276:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(206)
);
PPM_277:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(215)
);
PPM_278:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(224)
);
PPM_279:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(233)
);
PPM_280:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(242)
);
PPM_281:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(252)
);
PPM_282:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(261)
);
PPM_283:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(269)
);
PPM_284:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(277)
);
PPM_285:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(284)
);
PPM_286:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(291)
);
PPM_287:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(297)
);
PPM_288:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(303)
);
PPM_289:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(308)
);
PPM_290:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(313)
);
PPM_291:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(317)
);
PPM_292:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(321)
);
PPM_293:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(324)
);
PPM_294:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(327)
);
PPM_295:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(329)
);
PPM_296:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(330)
);
SUMMAND(331) <= LOGIC_ONE;
PPH_8:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(332)
);
-- Begin partial product 9
end BOOTHCODER;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity WALLACE_34_18 is
port
(
SUMMAND: in std_logic_vector(0 to 332);
CARRY: out std_logic_vector(0 to 49);
SUM: out std_logic_vector(0 to 50)
);
end WALLACE_34_18;
architecture WALLACE of WALLACE_34_18 is
-- Signals used inside the wallace trees
signal INT_CARRY: std_logic_vector(0 to 226);
signal INT_SUM: std_logic_vector(0 to 286);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End FA stage
---- Begin NO stage
INT_SUM(18) <= SUMMAND(41); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18),
SAVE => INT_SUM(19), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End HA stage
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End FA stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(23), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin NO stage
INT_SUM(24) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End FA stage
---- Begin NO stage
INT_SUM(26) <= INT_CARRY(15); -- At Level 3
---- End NO stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(25), DATA_B => INT_SUM(26),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End HA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50),
SAVE => INT_SUM(27), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin NO stage
INT_SUM(29) <= SUMMAND(54); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(30) <= SUMMAND(55); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29),
SAVE => INT_SUM(31), CARRY => INT_CARRY(22)
);
---- End FA stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17),
SAVE => INT_SUM(32), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(33), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End HA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58),
SAVE => INT_SUM(34), CARRY => INT_CARRY(25)
);
---- End FA stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61),
SAVE => INT_SUM(35), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(36) <= SUMMAND(62); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36),
SAVE => INT_SUM(37), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21),
SAVE => INT_SUM(38), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22),
SAVE => INT_SUM(39), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(40) <= INT_CARRY(23); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65),
SAVE => INT_SUM(41), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68),
SAVE => INT_SUM(42), CARRY => INT_CARRY(31)
);
---- End FA stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71),
SAVE => INT_SUM(43), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(28); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End HA stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50),
SAVE => INT_SUM(51), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32),
SAVE => INT_SUM(52), CARRY => INT_CARRY(40)
);
---- End FA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(53), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(54) <= INT_CARRY(34); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(55), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85),
SAVE => INT_SUM(56), CARRY => INT_CARRY(43)
);
---- End FA stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88),
SAVE => INT_SUM(57), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(58) <= SUMMAND(89); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57),
SAVE => INT_SUM(59), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37),
SAVE => INT_SUM(60), CARRY => INT_CARRY(46)
);
---- End FA stage
---- Begin NO stage
INT_SUM(61) <= INT_CARRY(38); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40),
SAVE => INT_SUM(63), CARRY => INT_CARRY(48)
);
---- End HA stage
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(64), CARRY => INT_CARRY(49)
);
---- End FA stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95),
SAVE => INT_SUM(65), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98),
SAVE => INT_SUM(66), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66),
SAVE => INT_SUM(67), CARRY => INT_CARRY(52)
);
---- End FA stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44),
SAVE => INT_SUM(68), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(69), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin NO stage
INT_SUM(70) <= INT_CARRY(46); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47),
SAVE => INT_SUM(71), CARRY => INT_CARRY(55)
);
---- End FA stage
---- Begin NO stage
INT_SUM(72) <= INT_CARRY(48); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(71), DATA_B => INT_SUM(72),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End HA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101),
SAVE => INT_SUM(73), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104),
SAVE => INT_SUM(74), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(75), CARRY => INT_CARRY(58)
);
---- End FA stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75),
SAVE => INT_SUM(76), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(49), DATA_B => INT_CARRY(50), DATA_C => INT_CARRY(51),
SAVE => INT_SUM(77), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(52),
SAVE => INT_SUM(78), CARRY => INT_CARRY(61)
);
---- End FA stage
---- Begin NO stage
INT_SUM(79) <= INT_CARRY(53); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(54),
SAVE => INT_SUM(80), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(80), DATA_B => INT_CARRY(55),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End HA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), DATA_C => SUMMAND(110),
SAVE => INT_SUM(81), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(111), DATA_B => SUMMAND(112), DATA_C => SUMMAND(113),
SAVE => INT_SUM(82), CARRY => INT_CARRY(64)
);
---- End FA stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(114), DATA_B => SUMMAND(115), DATA_C => SUMMAND(116),
SAVE => INT_SUM(83), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(81), DATA_B => INT_SUM(82), DATA_C => INT_SUM(83),
SAVE => INT_SUM(84), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58),
SAVE => INT_SUM(85), CARRY => INT_CARRY(67)
);
---- End FA stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(59),
SAVE => INT_SUM(86), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin NO stage
INT_SUM(87) <= INT_CARRY(60); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(61),
SAVE => INT_SUM(88), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_CARRY(62),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End HA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(117), DATA_B => SUMMAND(118), DATA_C => SUMMAND(119),
SAVE => INT_SUM(89), CARRY => INT_CARRY(70)
);
---- End FA stage
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122),
SAVE => INT_SUM(90), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125),
SAVE => INT_SUM(91), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91),
SAVE => INT_SUM(92), CARRY => INT_CARRY(73)
);
---- End FA stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(63), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65),
SAVE => INT_SUM(93), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66),
SAVE => INT_SUM(94), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin NO stage
INT_SUM(95) <= INT_CARRY(67); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68),
SAVE => INT_SUM(96), CARRY => INT_CARRY(76)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_CARRY(69),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End HA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128),
SAVE => INT_SUM(97), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131),
SAVE => INT_SUM(98), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134),
SAVE => INT_SUM(99), CARRY => INT_CARRY(79)
);
---- End FA stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(97), DATA_B => INT_SUM(98), DATA_C => INT_SUM(99),
SAVE => INT_SUM(100), CARRY => INT_CARRY(80)
);
---- End FA stage
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(70), DATA_B => INT_CARRY(71), DATA_C => INT_CARRY(72),
SAVE => INT_SUM(101), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(73),
SAVE => INT_SUM(102), CARRY => INT_CARRY(82)
);
---- End FA stage
---- Begin NO stage
INT_SUM(103) <= INT_CARRY(74); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(75),
SAVE => INT_SUM(104), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(104), DATA_B => INT_CARRY(76),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End HA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137),
SAVE => INT_SUM(105), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140),
SAVE => INT_SUM(106), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143),
SAVE => INT_SUM(107), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_SUM(107),
SAVE => INT_SUM(108), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(77), DATA_B => INT_CARRY(78), DATA_C => INT_CARRY(79),
SAVE => INT_SUM(109), CARRY => INT_CARRY(88)
);
---- End FA stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(80),
SAVE => INT_SUM(110), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin NO stage
INT_SUM(111) <= INT_CARRY(81); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(82),
SAVE => INT_SUM(112), CARRY => INT_CARRY(90)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(112), DATA_B => INT_CARRY(83),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End HA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146),
SAVE => INT_SUM(113), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(147), DATA_B => SUMMAND(148), DATA_C => SUMMAND(149),
SAVE => INT_SUM(114), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152),
SAVE => INT_SUM(115), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_SUM(115),
SAVE => INT_SUM(116), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86),
SAVE => INT_SUM(117), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(118), CARRY => INT_CARRY(96)
);
---- End FA stage
---- Begin NO stage
INT_SUM(119) <= INT_CARRY(88); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(89),
SAVE => INT_SUM(120), CARRY => INT_CARRY(97)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(120), DATA_B => INT_CARRY(90),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End HA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), DATA_C => SUMMAND(155),
SAVE => INT_SUM(121), CARRY => INT_CARRY(98)
);
---- End FA stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158),
SAVE => INT_SUM(122), CARRY => INT_CARRY(99)
);
---- End FA stage
---- Begin FA stage
FA_101:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161),
SAVE => INT_SUM(123), CARRY => INT_CARRY(100)
);
---- End FA stage
---- Begin FA stage
FA_102:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(121), DATA_B => INT_SUM(122), DATA_C => INT_SUM(123),
SAVE => INT_SUM(124), CARRY => INT_CARRY(101)
);
---- End FA stage
---- Begin FA stage
FA_103:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(91), DATA_B => INT_CARRY(92), DATA_C => INT_CARRY(93),
SAVE => INT_SUM(125), CARRY => INT_CARRY(102)
);
---- End FA stage
---- Begin FA stage
FA_104:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(94),
SAVE => INT_SUM(126), CARRY => INT_CARRY(103)
);
---- End FA stage
---- Begin NO stage
INT_SUM(127) <= INT_CARRY(95); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_105:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(96),
SAVE => INT_SUM(128), CARRY => INT_CARRY(104)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(128), DATA_B => INT_CARRY(97),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End HA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_106:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164),
SAVE => INT_SUM(129), CARRY => INT_CARRY(105)
);
---- End FA stage
---- Begin FA stage
FA_107:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167),
SAVE => INT_SUM(130), CARRY => INT_CARRY(106)
);
---- End FA stage
---- Begin FA stage
FA_108:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170),
SAVE => INT_SUM(131), CARRY => INT_CARRY(107)
);
---- End FA stage
---- Begin FA stage
FA_109:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_SUM(131),
SAVE => INT_SUM(132), CARRY => INT_CARRY(108)
);
---- End FA stage
---- Begin FA stage
FA_110:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(98), DATA_B => INT_CARRY(99), DATA_C => INT_CARRY(100),
SAVE => INT_SUM(133), CARRY => INT_CARRY(109)
);
---- End FA stage
---- Begin FA stage
FA_111:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(101),
SAVE => INT_SUM(134), CARRY => INT_CARRY(110)
);
---- End FA stage
---- Begin NO stage
INT_SUM(135) <= INT_CARRY(102); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_112:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(134), DATA_B => INT_SUM(135), DATA_C => INT_CARRY(103),
SAVE => INT_SUM(136), CARRY => INT_CARRY(111)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(136), DATA_B => INT_CARRY(104),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End HA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_113:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173),
SAVE => INT_SUM(137), CARRY => INT_CARRY(112)
);
---- End FA stage
---- Begin FA stage
FA_114:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(138), CARRY => INT_CARRY(113)
);
---- End FA stage
---- Begin FA stage
FA_115:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179),
SAVE => INT_SUM(139), CARRY => INT_CARRY(114)
);
---- End FA stage
---- Begin FA stage
FA_116:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_SUM(139),
SAVE => INT_SUM(140), CARRY => INT_CARRY(115)
);
---- End FA stage
---- Begin FA stage
FA_117:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(105), DATA_B => INT_CARRY(106), DATA_C => INT_CARRY(107),
SAVE => INT_SUM(141), CARRY => INT_CARRY(116)
);
---- End FA stage
---- Begin FA stage
FA_118:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(108),
SAVE => INT_SUM(142), CARRY => INT_CARRY(117)
);
---- End FA stage
---- Begin NO stage
INT_SUM(143) <= INT_CARRY(109); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_119:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(110),
SAVE => INT_SUM(144), CARRY => INT_CARRY(118)
);
---- End FA stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(144), DATA_B => INT_CARRY(111),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End HA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_120:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), DATA_C => SUMMAND(182),
SAVE => INT_SUM(145), CARRY => INT_CARRY(119)
);
---- End FA stage
---- Begin FA stage
FA_121:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(183), DATA_B => SUMMAND(184), DATA_C => SUMMAND(185),
SAVE => INT_SUM(146), CARRY => INT_CARRY(120)
);
---- End FA stage
---- Begin FA stage
FA_122:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), DATA_C => SUMMAND(188),
SAVE => INT_SUM(147), CARRY => INT_CARRY(121)
);
---- End FA stage
---- Begin FA stage
FA_123:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_SUM(147),
SAVE => INT_SUM(148), CARRY => INT_CARRY(122)
);
---- End FA stage
---- Begin FA stage
FA_124:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(112), DATA_B => INT_CARRY(113), DATA_C => INT_CARRY(114),
SAVE => INT_SUM(149), CARRY => INT_CARRY(123)
);
---- End FA stage
---- Begin FA stage
FA_125:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(115),
SAVE => INT_SUM(150), CARRY => INT_CARRY(124)
);
---- End FA stage
---- Begin NO stage
INT_SUM(151) <= INT_CARRY(116); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_126:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(117),
SAVE => INT_SUM(152), CARRY => INT_CARRY(125)
);
---- End FA stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(152), DATA_B => INT_CARRY(118),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End HA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_127:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(189), DATA_B => SUMMAND(190), DATA_C => SUMMAND(191),
SAVE => INT_SUM(153), CARRY => INT_CARRY(126)
);
---- End FA stage
---- Begin FA stage
FA_128:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(192), DATA_B => SUMMAND(193), DATA_C => SUMMAND(194),
SAVE => INT_SUM(154), CARRY => INT_CARRY(127)
);
---- End FA stage
---- Begin FA stage
FA_129:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197),
SAVE => INT_SUM(155), CARRY => INT_CARRY(128)
);
---- End FA stage
---- Begin FA stage
FA_130:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_SUM(155),
SAVE => INT_SUM(156), CARRY => INT_CARRY(129)
);
---- End FA stage
---- Begin FA stage
FA_131:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(119), DATA_B => INT_CARRY(120), DATA_C => INT_CARRY(121),
SAVE => INT_SUM(157), CARRY => INT_CARRY(130)
);
---- End FA stage
---- Begin FA stage
FA_132:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(156), DATA_B => INT_SUM(157), DATA_C => INT_CARRY(122),
SAVE => INT_SUM(158), CARRY => INT_CARRY(131)
);
---- End FA stage
---- Begin NO stage
INT_SUM(159) <= INT_CARRY(123); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_133:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(158), DATA_B => INT_SUM(159), DATA_C => INT_CARRY(124),
SAVE => INT_SUM(160), CARRY => INT_CARRY(132)
);
---- End FA stage
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(160), DATA_B => INT_CARRY(125),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End HA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_134:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200),
SAVE => INT_SUM(161), CARRY => INT_CARRY(133)
);
---- End FA stage
---- Begin FA stage
FA_135:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203),
SAVE => INT_SUM(162), CARRY => INT_CARRY(134)
);
---- End FA stage
---- Begin FA stage
FA_136:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206),
SAVE => INT_SUM(163), CARRY => INT_CARRY(135)
);
---- End FA stage
---- Begin FA stage
FA_137:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(161), DATA_B => INT_SUM(162), DATA_C => INT_SUM(163),
SAVE => INT_SUM(164), CARRY => INT_CARRY(136)
);
---- End FA stage
---- Begin FA stage
FA_138:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(126), DATA_B => INT_CARRY(127), DATA_C => INT_CARRY(128),
SAVE => INT_SUM(165), CARRY => INT_CARRY(137)
);
---- End FA stage
---- Begin FA stage
FA_139:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(164), DATA_B => INT_SUM(165), DATA_C => INT_CARRY(129),
SAVE => INT_SUM(166), CARRY => INT_CARRY(138)
);
---- End FA stage
---- Begin NO stage
INT_SUM(167) <= INT_CARRY(130); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_140:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(131),
SAVE => INT_SUM(168), CARRY => INT_CARRY(139)
);
---- End FA stage
---- Begin HA stage
HA_27:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(168), DATA_B => INT_CARRY(132),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End HA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_141:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209),
SAVE => INT_SUM(169), CARRY => INT_CARRY(140)
);
---- End FA stage
---- Begin FA stage
FA_142:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212),
SAVE => INT_SUM(170), CARRY => INT_CARRY(141)
);
---- End FA stage
---- Begin FA stage
FA_143:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215),
SAVE => INT_SUM(171), CARRY => INT_CARRY(142)
);
---- End FA stage
---- Begin FA stage
FA_144:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(169), DATA_B => INT_SUM(170), DATA_C => INT_SUM(171),
SAVE => INT_SUM(172), CARRY => INT_CARRY(143)
);
---- End FA stage
---- Begin FA stage
FA_145:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135),
SAVE => INT_SUM(173), CARRY => INT_CARRY(144)
);
---- End FA stage
---- Begin FA stage
FA_146:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(172), DATA_B => INT_SUM(173), DATA_C => INT_CARRY(136),
SAVE => INT_SUM(174), CARRY => INT_CARRY(145)
);
---- End FA stage
---- Begin NO stage
INT_SUM(175) <= INT_CARRY(137); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_147:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(174), DATA_B => INT_SUM(175), DATA_C => INT_CARRY(138),
SAVE => INT_SUM(176), CARRY => INT_CARRY(146)
);
---- End FA stage
---- Begin HA stage
HA_28:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(176), DATA_B => INT_CARRY(139),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End HA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_148:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218),
SAVE => INT_SUM(177), CARRY => INT_CARRY(147)
);
---- End FA stage
---- Begin FA stage
FA_149:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221),
SAVE => INT_SUM(178), CARRY => INT_CARRY(148)
);
---- End FA stage
---- Begin FA stage
FA_150:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), DATA_C => SUMMAND(224),
SAVE => INT_SUM(179), CARRY => INT_CARRY(149)
);
---- End FA stage
---- Begin FA stage
FA_151:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(177), DATA_B => INT_SUM(178), DATA_C => INT_SUM(179),
SAVE => INT_SUM(180), CARRY => INT_CARRY(150)
);
---- End FA stage
---- Begin FA stage
FA_152:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(140), DATA_B => INT_CARRY(141), DATA_C => INT_CARRY(142),
SAVE => INT_SUM(181), CARRY => INT_CARRY(151)
);
---- End FA stage
---- Begin FA stage
FA_153:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), DATA_C => INT_CARRY(143),
SAVE => INT_SUM(182), CARRY => INT_CARRY(152)
);
---- End FA stage
---- Begin NO stage
INT_SUM(183) <= INT_CARRY(144); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_154:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_CARRY(145),
SAVE => INT_SUM(184), CARRY => INT_CARRY(153)
);
---- End FA stage
---- Begin HA stage
HA_29:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(184), DATA_B => INT_CARRY(146),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End HA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin FA stage
FA_155:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(225), DATA_B => SUMMAND(226), DATA_C => SUMMAND(227),
SAVE => INT_SUM(185), CARRY => INT_CARRY(154)
);
---- End FA stage
---- Begin FA stage
FA_156:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(228), DATA_B => SUMMAND(229), DATA_C => SUMMAND(230),
SAVE => INT_SUM(186), CARRY => INT_CARRY(155)
);
---- End FA stage
---- Begin FA stage
FA_157:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(231), DATA_B => SUMMAND(232), DATA_C => SUMMAND(233),
SAVE => INT_SUM(187), CARRY => INT_CARRY(156)
);
---- End FA stage
---- Begin FA stage
FA_158:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_SUM(187),
SAVE => INT_SUM(188), CARRY => INT_CARRY(157)
);
---- End FA stage
---- Begin FA stage
FA_159:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(147), DATA_B => INT_CARRY(148), DATA_C => INT_CARRY(149),
SAVE => INT_SUM(189), CARRY => INT_CARRY(158)
);
---- End FA stage
---- Begin FA stage
FA_160:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(188), DATA_B => INT_SUM(189), DATA_C => INT_CARRY(150),
SAVE => INT_SUM(190), CARRY => INT_CARRY(159)
);
---- End FA stage
---- Begin NO stage
INT_SUM(191) <= INT_CARRY(151); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_161:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(190), DATA_B => INT_SUM(191), DATA_C => INT_CARRY(152),
SAVE => INT_SUM(192), CARRY => INT_CARRY(160)
);
---- End FA stage
---- Begin HA stage
HA_30:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(192), DATA_B => INT_CARRY(153),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End HA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin FA stage
FA_162:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(234), DATA_B => SUMMAND(235), DATA_C => SUMMAND(236),
SAVE => INT_SUM(193), CARRY => INT_CARRY(161)
);
---- End FA stage
---- Begin FA stage
FA_163:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(237), DATA_B => SUMMAND(238), DATA_C => SUMMAND(239),
SAVE => INT_SUM(194), CARRY => INT_CARRY(162)
);
---- End FA stage
---- Begin FA stage
FA_164:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242),
SAVE => INT_SUM(195), CARRY => INT_CARRY(163)
);
---- End FA stage
---- Begin FA stage
FA_165:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(193), DATA_B => INT_SUM(194), DATA_C => INT_SUM(195),
SAVE => INT_SUM(196), CARRY => INT_CARRY(164)
);
---- End FA stage
---- Begin FA stage
FA_166:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(154), DATA_B => INT_CARRY(155), DATA_C => INT_CARRY(156),
SAVE => INT_SUM(197), CARRY => INT_CARRY(165)
);
---- End FA stage
---- Begin FA stage
FA_167:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(196), DATA_B => INT_SUM(197), DATA_C => INT_CARRY(157),
SAVE => INT_SUM(198), CARRY => INT_CARRY(166)
);
---- End FA stage
---- Begin NO stage
INT_SUM(199) <= INT_CARRY(158); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_168:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(198), DATA_B => INT_SUM(199), DATA_C => INT_CARRY(159),
SAVE => INT_SUM(200), CARRY => INT_CARRY(167)
);
---- End FA stage
---- Begin HA stage
HA_31:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(200), DATA_B => INT_CARRY(160),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End HA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin FA stage
FA_169:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245),
SAVE => INT_SUM(201), CARRY => INT_CARRY(168)
);
---- End FA stage
---- Begin FA stage
FA_170:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248),
SAVE => INT_SUM(202), CARRY => INT_CARRY(169)
);
---- End FA stage
---- Begin FA stage
FA_171:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251),
SAVE => INT_SUM(203), CARRY => INT_CARRY(170)
);
---- End FA stage
---- Begin NO stage
INT_SUM(204) <= SUMMAND(252); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_172:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(201), DATA_B => INT_SUM(202), DATA_C => INT_SUM(203),
SAVE => INT_SUM(205), CARRY => INT_CARRY(171)
);
---- End FA stage
---- Begin FA stage
FA_173:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(204), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162),
SAVE => INT_SUM(206), CARRY => INT_CARRY(172)
);
---- End FA stage
---- Begin NO stage
INT_SUM(207) <= INT_CARRY(163); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_174:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207),
SAVE => INT_SUM(208), CARRY => INT_CARRY(173)
);
---- End FA stage
---- Begin NO stage
INT_SUM(209) <= INT_CARRY(164); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(210) <= INT_CARRY(165); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_175:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_SUM(210),
SAVE => INT_SUM(211), CARRY => INT_CARRY(174)
);
---- End FA stage
---- Begin NO stage
INT_SUM(212) <= INT_CARRY(166); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_176:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(211), DATA_B => INT_SUM(212), DATA_C => INT_CARRY(167),
SAVE => SUM(34), CARRY => CARRY(34)
);
---- End FA stage
-- End WT-branch 35
-- Begin WT-branch 36
---- Begin FA stage
FA_177:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(253), DATA_B => SUMMAND(254), DATA_C => SUMMAND(255),
SAVE => INT_SUM(213), CARRY => INT_CARRY(175)
);
---- End FA stage
---- Begin FA stage
FA_178:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(256), DATA_B => SUMMAND(257), DATA_C => SUMMAND(258),
SAVE => INT_SUM(214), CARRY => INT_CARRY(176)
);
---- End FA stage
---- Begin FA stage
FA_179:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(259), DATA_B => SUMMAND(260), DATA_C => SUMMAND(261),
SAVE => INT_SUM(215), CARRY => INT_CARRY(177)
);
---- End FA stage
---- Begin FA stage
FA_180:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(168), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170),
SAVE => INT_SUM(216), CARRY => INT_CARRY(178)
);
---- End FA stage
---- Begin FA stage
FA_181:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(213), DATA_B => INT_SUM(214), DATA_C => INT_SUM(215),
SAVE => INT_SUM(217), CARRY => INT_CARRY(179)
);
---- End FA stage
---- Begin FA stage
FA_182:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(216), DATA_B => INT_CARRY(171), DATA_C => INT_CARRY(172),
SAVE => INT_SUM(218), CARRY => INT_CARRY(180)
);
---- End FA stage
---- Begin FA stage
FA_183:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_CARRY(173),
SAVE => INT_SUM(219), CARRY => INT_CARRY(181)
);
---- End FA stage
---- Begin HA stage
HA_32:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(219), DATA_B => INT_CARRY(174),
SAVE => SUM(35), CARRY => CARRY(35)
);
---- End HA stage
-- End WT-branch 36
-- Begin WT-branch 37
---- Begin FA stage
FA_184:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(262), DATA_B => SUMMAND(263), DATA_C => SUMMAND(264),
SAVE => INT_SUM(220), CARRY => INT_CARRY(182)
);
---- End FA stage
---- Begin FA stage
FA_185:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(265), DATA_B => SUMMAND(266), DATA_C => SUMMAND(267),
SAVE => INT_SUM(221), CARRY => INT_CARRY(183)
);
---- End FA stage
---- Begin NO stage
INT_SUM(222) <= SUMMAND(268); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(223) <= SUMMAND(269); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_186:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_SUM(222),
SAVE => INT_SUM(224), CARRY => INT_CARRY(184)
);
---- End FA stage
---- Begin NO stage
INT_SUM(225) <= INT_SUM(223); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_187:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(224), DATA_B => INT_SUM(225), DATA_C => INT_CARRY(175),
SAVE => INT_SUM(226), CARRY => INT_CARRY(185)
);
---- End FA stage
---- Begin FA stage
FA_188:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(176), DATA_B => INT_CARRY(177), DATA_C => INT_CARRY(178),
SAVE => INT_SUM(227), CARRY => INT_CARRY(186)
);
---- End FA stage
---- Begin FA stage
FA_189:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_CARRY(179),
SAVE => INT_SUM(228), CARRY => INT_CARRY(187)
);
---- End FA stage
---- Begin NO stage
INT_SUM(229) <= INT_CARRY(180); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_190:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(228), DATA_B => INT_SUM(229), DATA_C => INT_CARRY(181),
SAVE => SUM(36), CARRY => CARRY(36)
);
---- End FA stage
-- End WT-branch 37
-- Begin WT-branch 38
---- Begin FA stage
FA_191:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(270), DATA_B => SUMMAND(271), DATA_C => SUMMAND(272),
SAVE => INT_SUM(230), CARRY => INT_CARRY(188)
);
---- End FA stage
---- Begin FA stage
FA_192:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(273), DATA_B => SUMMAND(274), DATA_C => SUMMAND(275),
SAVE => INT_SUM(231), CARRY => INT_CARRY(189)
);
---- End FA stage
---- Begin FA stage
FA_193:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(276), DATA_B => SUMMAND(277), DATA_C => INT_CARRY(182),
SAVE => INT_SUM(232), CARRY => INT_CARRY(190)
);
---- End FA stage
---- Begin NO stage
INT_SUM(233) <= INT_CARRY(183); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_194:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(230), DATA_B => INT_SUM(231), DATA_C => INT_SUM(232),
SAVE => INT_SUM(234), CARRY => INT_CARRY(191)
);
---- End FA stage
---- Begin HA stage
HA_33:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(233), DATA_B => INT_CARRY(184),
SAVE => INT_SUM(235), CARRY => INT_CARRY(192)
);
---- End HA stage
---- Begin FA stage
FA_195:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(234), DATA_B => INT_SUM(235), DATA_C => INT_CARRY(185),
SAVE => INT_SUM(236), CARRY => INT_CARRY(193)
);
---- End FA stage
---- Begin NO stage
INT_SUM(237) <= INT_CARRY(186); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_196:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_CARRY(187),
SAVE => SUM(37), CARRY => CARRY(37)
);
---- End FA stage
-- End WT-branch 38
-- Begin WT-branch 39
---- Begin FA stage
FA_197:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280),
SAVE => INT_SUM(238), CARRY => INT_CARRY(194)
);
---- End FA stage
---- Begin FA stage
FA_198:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283),
SAVE => INT_SUM(239), CARRY => INT_CARRY(195)
);
---- End FA stage
---- Begin NO stage
INT_SUM(240) <= SUMMAND(284); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_199:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(238), DATA_B => INT_SUM(239), DATA_C => INT_SUM(240),
SAVE => INT_SUM(241), CARRY => INT_CARRY(196)
);
---- End FA stage
---- Begin FA stage
FA_200:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190),
SAVE => INT_SUM(242), CARRY => INT_CARRY(197)
);
---- End FA stage
---- Begin FA stage
FA_201:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(241), DATA_B => INT_SUM(242), DATA_C => INT_CARRY(191),
SAVE => INT_SUM(243), CARRY => INT_CARRY(198)
);
---- End FA stage
---- Begin NO stage
INT_SUM(244) <= INT_CARRY(192); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_202:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(243), DATA_B => INT_SUM(244), DATA_C => INT_CARRY(193),
SAVE => SUM(38), CARRY => CARRY(38)
);
---- End FA stage
-- End WT-branch 39
-- Begin WT-branch 40
---- Begin FA stage
FA_203:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(285), DATA_B => SUMMAND(286), DATA_C => SUMMAND(287),
SAVE => INT_SUM(245), CARRY => INT_CARRY(199)
);
---- End FA stage
---- Begin FA stage
FA_204:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290),
SAVE => INT_SUM(246), CARRY => INT_CARRY(200)
);
---- End FA stage
---- Begin NO stage
INT_SUM(247) <= SUMMAND(291); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_205:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(245), DATA_B => INT_SUM(246), DATA_C => INT_SUM(247),
SAVE => INT_SUM(248), CARRY => INT_CARRY(201)
);
---- End FA stage
---- Begin HA stage
HA_34:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(194), DATA_B => INT_CARRY(195),
SAVE => INT_SUM(249), CARRY => INT_CARRY(202)
);
---- End HA stage
---- Begin FA stage
FA_206:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(248), DATA_B => INT_SUM(249), DATA_C => INT_CARRY(196),
SAVE => INT_SUM(250), CARRY => INT_CARRY(203)
);
---- End FA stage
---- Begin NO stage
INT_SUM(251) <= INT_CARRY(197); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_207:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(250), DATA_B => INT_SUM(251), DATA_C => INT_CARRY(198),
SAVE => SUM(39), CARRY => CARRY(39)
);
---- End FA stage
-- End WT-branch 40
-- Begin WT-branch 41
---- Begin FA stage
FA_208:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(292), DATA_B => SUMMAND(293), DATA_C => SUMMAND(294),
SAVE => INT_SUM(252), CARRY => INT_CARRY(204)
);
---- End FA stage
---- Begin FA stage
FA_209:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(295), DATA_B => SUMMAND(296), DATA_C => SUMMAND(297),
SAVE => INT_SUM(253), CARRY => INT_CARRY(205)
);
---- End FA stage
---- Begin FA stage
FA_210:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(252), DATA_B => INT_SUM(253), DATA_C => INT_CARRY(199),
SAVE => INT_SUM(254), CARRY => INT_CARRY(206)
);
---- End FA stage
---- Begin NO stage
INT_SUM(255) <= INT_CARRY(200); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_211:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_CARRY(201),
SAVE => INT_SUM(256), CARRY => INT_CARRY(207)
);
---- End FA stage
---- Begin NO stage
INT_SUM(257) <= INT_CARRY(202); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_212:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(256), DATA_B => INT_SUM(257), DATA_C => INT_CARRY(203),
SAVE => SUM(40), CARRY => CARRY(40)
);
---- End FA stage
-- End WT-branch 41
-- Begin WT-branch 42
---- Begin FA stage
FA_213:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(298), DATA_B => SUMMAND(299), DATA_C => SUMMAND(300),
SAVE => INT_SUM(258), CARRY => INT_CARRY(208)
);
---- End FA stage
---- Begin FA stage
FA_214:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(301), DATA_B => SUMMAND(302), DATA_C => SUMMAND(303),
SAVE => INT_SUM(259), CARRY => INT_CARRY(209)
);
---- End FA stage
---- Begin FA stage
FA_215:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(258), DATA_B => INT_SUM(259), DATA_C => INT_CARRY(204),
SAVE => INT_SUM(260), CARRY => INT_CARRY(210)
);
---- End FA stage
---- Begin NO stage
INT_SUM(261) <= INT_CARRY(205); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_216:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(206),
SAVE => INT_SUM(262), CARRY => INT_CARRY(211)
);
---- End FA stage
---- Begin HA stage
HA_35:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(262), DATA_B => INT_CARRY(207),
SAVE => SUM(41), CARRY => CARRY(41)
);
---- End HA stage
-- End WT-branch 42
-- Begin WT-branch 43
---- Begin FA stage
FA_217:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(304), DATA_B => SUMMAND(305), DATA_C => SUMMAND(306),
SAVE => INT_SUM(263), CARRY => INT_CARRY(212)
);
---- End FA stage
---- Begin HA stage
HA_36:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(307), DATA_B => SUMMAND(308),
SAVE => INT_SUM(264), CARRY => INT_CARRY(213)
);
---- End HA stage
---- Begin FA stage
FA_218:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(263), DATA_B => INT_SUM(264), DATA_C => INT_CARRY(208),
SAVE => INT_SUM(265), CARRY => INT_CARRY(214)
);
---- End FA stage
---- Begin NO stage
INT_SUM(266) <= INT_CARRY(209); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_219:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(210),
SAVE => INT_SUM(267), CARRY => INT_CARRY(215)
);
---- End FA stage
---- Begin HA stage
HA_37:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(267), DATA_B => INT_CARRY(211),
SAVE => SUM(42), CARRY => CARRY(42)
);
---- End HA stage
-- End WT-branch 43
-- Begin WT-branch 44
---- Begin FA stage
FA_220:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311),
SAVE => INT_SUM(268), CARRY => INT_CARRY(216)
);
---- End FA stage
---- Begin HA stage
HA_38:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(312), DATA_B => SUMMAND(313),
SAVE => INT_SUM(269), CARRY => INT_CARRY(217)
);
---- End HA stage
---- Begin FA stage
FA_221:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(268), DATA_B => INT_SUM(269), DATA_C => INT_CARRY(212),
SAVE => INT_SUM(270), CARRY => INT_CARRY(218)
);
---- End FA stage
---- Begin NO stage
INT_SUM(271) <= INT_CARRY(213); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_222:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(270), DATA_B => INT_SUM(271), DATA_C => INT_CARRY(214),
SAVE => INT_SUM(272), CARRY => INT_CARRY(219)
);
---- End FA stage
---- Begin HA stage
HA_39:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(272), DATA_B => INT_CARRY(215),
SAVE => SUM(43), CARRY => CARRY(43)
);
---- End HA stage
-- End WT-branch 44
-- Begin WT-branch 45
---- Begin FA stage
FA_223:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(314), DATA_B => SUMMAND(315), DATA_C => SUMMAND(316),
SAVE => INT_SUM(273), CARRY => INT_CARRY(220)
);
---- End FA stage
---- Begin FA stage
FA_224:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(317), DATA_B => INT_CARRY(216), DATA_C => INT_CARRY(217),
SAVE => INT_SUM(274), CARRY => INT_CARRY(221)
);
---- End FA stage
---- Begin FA stage
FA_225:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(273), DATA_B => INT_SUM(274), DATA_C => INT_CARRY(218),
SAVE => INT_SUM(275), CARRY => INT_CARRY(222)
);
---- End FA stage
---- Begin HA stage
HA_40:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(275), DATA_B => INT_CARRY(219),
SAVE => SUM(44), CARRY => CARRY(44)
);
---- End HA stage
-- End WT-branch 45
-- Begin WT-branch 46
---- Begin FA stage
FA_226:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320),
SAVE => INT_SUM(276), CARRY => INT_CARRY(223)
);
---- End FA stage
---- Begin NO stage
INT_SUM(277) <= SUMMAND(321); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_227:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(276), DATA_B => INT_SUM(277), DATA_C => INT_CARRY(220),
SAVE => INT_SUM(278), CARRY => INT_CARRY(224)
);
---- End FA stage
---- Begin NO stage
INT_SUM(279) <= INT_CARRY(221); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_228:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(278), DATA_B => INT_SUM(279), DATA_C => INT_CARRY(222),
SAVE => SUM(45), CARRY => CARRY(45)
);
---- End FA stage
-- End WT-branch 46
-- Begin WT-branch 47
---- Begin FA stage
FA_229:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(322), DATA_B => SUMMAND(323), DATA_C => SUMMAND(324),
SAVE => INT_SUM(280), CARRY => INT_CARRY(225)
);
---- End FA stage
---- Begin NO stage
INT_SUM(281) <= INT_SUM(280); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(282) <= INT_CARRY(223); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_230:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(281), DATA_B => INT_SUM(282), DATA_C => INT_CARRY(224),
SAVE => SUM(46), CARRY => CARRY(46)
);
---- End FA stage
-- End WT-branch 47
-- Begin WT-branch 48
---- Begin FA stage
FA_231:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(325), DATA_B => SUMMAND(326), DATA_C => SUMMAND(327),
SAVE => INT_SUM(283), CARRY => INT_CARRY(226)
);
---- End FA stage
---- Begin NO stage
INT_SUM(284) <= INT_CARRY(225); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_41:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(283), DATA_B => INT_SUM(284),
SAVE => SUM(47), CARRY => CARRY(47)
);
---- End HA stage
-- End WT-branch 48
-- Begin WT-branch 49
---- Begin NO stage
INT_SUM(285) <= SUMMAND(328); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(286) <= SUMMAND(329); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_232:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(285), DATA_B => INT_SUM(286), DATA_C => INT_CARRY(226),
SAVE => SUM(48), CARRY => CARRY(48)
);
---- End FA stage
-- End WT-branch 49
-- Begin WT-branch 50
---- Begin HA stage
HA_42:HALF_ADDER -- At Level 5
port map
(
DATA_A => SUMMAND(330), DATA_B => SUMMAND(331),
SAVE => SUM(49), CARRY => CARRY(49)
);
---- End HA stage
-- End WT-branch 50
-- Begin WT-branch 51
---- Begin NO stage
SUM(50) <= SUMMAND(332); -- At Level 5
---- End NO stage
-- End WT-branch 51
end WALLACE;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MULTIPLIER_34_18 is
port
(
MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63)
);
end MULTIPLIER_34_18;
------------------------------------------------------------
-- End: Multiplier Entitiy
architecture MULTIPLIER of MULTIPLIER_34_18 is
signal PPBIT:std_logic_vector(0 to 332);
signal INT_CARRY: std_logic_vector(0 to 64);
signal INT_SUM: std_logic_vector(0 to 63);
signal LOGIC_ZERO: std_logic;
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_34_18
port map
(
OPA(0 to 33) => MULTIPLICAND(0 to 33),
OPB(0 to 17) => MULTIPLIER(0 to 17),
SUMMAND(0 to 332) => PPBIT(0 to 332)
);
W:WALLACE_34_18
port map
(
SUMMAND(0 to 332) => PPBIT(0 to 332),
CARRY(0 to 49) => INT_CARRY(1 to 50),
SUM(0 to 50) => INT_SUM(0 to 50)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(51) <= LOGIC_ZERO;
INT_CARRY(52) <= LOGIC_ZERO;
INT_CARRY(53) <= LOGIC_ZERO;
INT_CARRY(54) <= LOGIC_ZERO;
INT_CARRY(55) <= LOGIC_ZERO;
INT_CARRY(56) <= LOGIC_ZERO;
INT_CARRY(57) <= LOGIC_ZERO;
INT_CARRY(58) <= LOGIC_ZERO;
INT_CARRY(59) <= LOGIC_ZERO;
INT_CARRY(60) <= LOGIC_ZERO;
INT_CARRY(61) <= LOGIC_ZERO;
INT_CARRY(62) <= LOGIC_ZERO;
INT_CARRY(63) <= LOGIC_ZERO;
INT_SUM(51) <= LOGIC_ZERO;
INT_SUM(52) <= LOGIC_ZERO;
INT_SUM(53) <= LOGIC_ZERO;
INT_SUM(54) <= LOGIC_ZERO;
INT_SUM(55) <= LOGIC_ZERO;
INT_SUM(56) <= LOGIC_ZERO;
INT_SUM(57) <= LOGIC_ZERO;
INT_SUM(58) <= LOGIC_ZERO;
INT_SUM(59) <= LOGIC_ZERO;
INT_SUM(60) <= LOGIC_ZERO;
INT_SUM(61) <= LOGIC_ZERO;
INT_SUM(62) <= LOGIC_ZERO;
INT_SUM(63) <= LOGIC_ZERO;
D:DBLCADDER_64_64
port map
(
OPA(0 to 63) => INT_SUM(0 to 63),
OPB(0 to 63) => INT_CARRY(0 to 63),
CIN => LOGIC_ZERO,
PHI => PHI,
SUM(0 to 63) => RESULT(0 to 63)
);
end MULTIPLIER;
------------------------------------------------------------
-- END: Architectures used with the multiplier
------------------------------------------------------------
--
-- Modgen multiplier created Fri Aug 16 16:29:15 2002
--
------------------------------------------------------------
-- START: Multiplier Entitiy
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- START: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MUL_33_17 is
port(X: in std_logic_vector(32 downto 0);
Y: in std_logic_vector(16 downto 0);
P: out std_logic_vector(49 downto 0));
end MUL_33_17;
library ieee;
use ieee.std_logic_1164.all;
architecture A of MUL_33_17 is
signal A: std_logic_vector(0 to 33);
signal B: std_logic_vector(0 to 17);
signal Q: std_logic_vector(0 to 63);
signal CLK: std_logic;
begin
U1: MULTIPLIER_34_18 port map(A,B,CLK,Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(17);
A(18) <= X(18);
A(19) <= X(19);
A(20) <= X(20);
A(21) <= X(21);
A(22) <= X(22);
A(23) <= X(23);
A(24) <= X(24);
A(25) <= X(25);
A(26) <= X(26);
A(27) <= X(27);
A(28) <= X(28);
A(29) <= X(29);
A(30) <= X(30);
A(31) <= X(31);
A(32) <= X(32);
A(33) <= X(32);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(9);
B(10) <= Y(10);
B(11) <= Y(11);
B(12) <= Y(12);
B(13) <= Y(13);
B(14) <= Y(14);
B(15) <= Y(15);
B(16) <= Y(16);
B(17) <= Y(16);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
P(34) <= Q(34);
P(35) <= Q(35);
P(36) <= Q(36);
P(37) <= Q(37);
P(38) <= Q(38);
P(39) <= Q(39);
P(40) <= Q(40);
P(41) <= Q(41);
P(42) <= Q(42);
P(43) <= Q(43);
P(44) <= Q(44);
P(45) <= Q(45);
P(46) <= Q(46);
P(47) <= Q(47);
P(48) <= Q(48);
P(49) <= Q(49);
end A;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity BOOTHCODER_34_34 is
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 33);
SUMMAND: out std_logic_vector(0 to 628)
);
end BOOTHCODER_34_34;
architecture BOOTHCODER of BOOTHCODER_34_34 is
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 33);
signal INT_MULTIPLIER: std_logic_vector(0 to 67);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(42)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(48)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(56)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(63)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(72)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
INV_MULTIPLICAND(18) <= NOT OPA(18);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(99)
);
INV_MULTIPLICAND(19) <= NOT OPA(19);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(110)
);
INV_MULTIPLICAND(20) <= NOT OPA(20);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(120)
);
INV_MULTIPLICAND(21) <= NOT OPA(21);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(132)
);
INV_MULTIPLICAND(22) <= NOT OPA(22);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(143)
);
INV_MULTIPLICAND(23) <= NOT OPA(23);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(156)
);
INV_MULTIPLICAND(24) <= NOT OPA(24);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(168)
);
INV_MULTIPLICAND(25) <= NOT OPA(25);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(182)
);
INV_MULTIPLICAND(26) <= NOT OPA(26);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(195)
);
INV_MULTIPLICAND(27) <= NOT OPA(27);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(210)
);
INV_MULTIPLICAND(28) <= NOT OPA(28);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(224)
);
INV_MULTIPLICAND(29) <= NOT OPA(29);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(240)
);
INV_MULTIPLICAND(30) <= NOT OPA(30);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(255)
);
INV_MULTIPLICAND(31) <= NOT OPA(31);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(272)
);
INV_MULTIPLICAND(32) <= NOT OPA(32);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(288)
);
INV_MULTIPLICAND(33) <= NOT OPA(33);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(306)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(323)
);
SUMMAND(324) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(43)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(49)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(57)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(64)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(73)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(100)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(111)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(121)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(133)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(144)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(157)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(169)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(183)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(196)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(211)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(225)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(241)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(256)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(273)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(289)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(307)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(325)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(341)
);
SUMMAND(342) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(358)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(44)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(50)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(58)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(65)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(74)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(101)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(112)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(122)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(134)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(145)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(158)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(170)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(184)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(197)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(212)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(226)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(242)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(257)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(274)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(290)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(308)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(326)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(343)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(359)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(374)
);
SUMMAND(375) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(390)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(45)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(51)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(59)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(66)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(75)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(102)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(113)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(123)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(135)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(146)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(159)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(171)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(185)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(198)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(213)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(227)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(243)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(258)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(275)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(291)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(309)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(327)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(344)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(360)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(376)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(391)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(405)
);
SUMMAND(406) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(420)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(46)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(52)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(60)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(67)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(76)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(103)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(114)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(124)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(136)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(147)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(160)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(172)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(186)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(199)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(214)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(228)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(244)
);
PPM_153:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(259)
);
PPM_154:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(276)
);
PPM_155:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(292)
);
PPM_156:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(310)
);
PPM_157:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(328)
);
PPM_158:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(345)
);
PPM_159:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(361)
);
PPM_160:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(377)
);
PPM_161:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(392)
);
PPM_162:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(407)
);
PPM_163:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(421)
);
PPM_164:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(434)
);
SUMMAND(435) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(448)
);
-- Begin partial product 5
-- Begin decoder block 6
DEC_5:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23)
);
-- End decoder block 6
-- Begin partial product 6
PPL_5:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(40)
);
RGATE_5:R_GATE
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
PPBIT => SUMMAND(41)
);
PPM_165:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(47)
);
PPM_166:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(53)
);
PPM_167:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(61)
);
PPM_168:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(68)
);
PPM_169:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(77)
);
PPM_170:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(85)
);
PPM_171:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(95)
);
PPM_172:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(104)
);
PPM_173:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(115)
);
PPM_174:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(125)
);
PPM_175:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(137)
);
PPM_176:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(148)
);
PPM_177:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(161)
);
PPM_178:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(173)
);
PPM_179:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(187)
);
PPM_180:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(200)
);
PPM_181:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(215)
);
PPM_182:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(229)
);
PPM_183:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(245)
);
PPM_184:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(260)
);
PPM_185:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(277)
);
PPM_186:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(293)
);
PPM_187:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(311)
);
PPM_188:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(329)
);
PPM_189:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(346)
);
PPM_190:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(362)
);
PPM_191:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(378)
);
PPM_192:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(393)
);
PPM_193:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(408)
);
PPM_194:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(422)
);
PPM_195:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(436)
);
PPM_196:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(449)
);
PPM_197:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(461)
);
SUMMAND(462) <= LOGIC_ONE;
PPH_5:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(474)
);
-- Begin partial product 6
-- Begin decoder block 7
DEC_6:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27)
);
-- End decoder block 7
-- Begin partial product 7
PPL_6:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(54)
);
RGATE_6:R_GATE
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
PPBIT => SUMMAND(55)
);
PPM_198:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(62)
);
PPM_199:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(69)
);
PPM_200:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(78)
);
PPM_201:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(86)
);
PPM_202:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(96)
);
PPM_203:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(105)
);
PPM_204:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(116)
);
PPM_205:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(126)
);
PPM_206:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(138)
);
PPM_207:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(149)
);
PPM_208:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(162)
);
PPM_209:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(174)
);
PPM_210:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(188)
);
PPM_211:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(201)
);
PPM_212:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(216)
);
PPM_213:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(230)
);
PPM_214:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(246)
);
PPM_215:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(261)
);
PPM_216:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(278)
);
PPM_217:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(294)
);
PPM_218:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(312)
);
PPM_219:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(330)
);
PPM_220:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(347)
);
PPM_221:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(363)
);
PPM_222:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(379)
);
PPM_223:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(394)
);
PPM_224:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(409)
);
PPM_225:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(423)
);
PPM_226:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(437)
);
PPM_227:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(450)
);
PPM_228:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(463)
);
PPM_229:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(475)
);
PPM_230:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(486)
);
SUMMAND(487) <= LOGIC_ONE;
PPH_6:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(498)
);
-- Begin partial product 7
-- Begin decoder block 8
DEC_7:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31)
);
-- End decoder block 8
-- Begin partial product 8
PPL_7:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(70)
);
RGATE_7:R_GATE
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
PPBIT => SUMMAND(71)
);
PPM_231:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(79)
);
PPM_232:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(87)
);
PPM_233:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(97)
);
PPM_234:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(106)
);
PPM_235:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(117)
);
PPM_236:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(127)
);
PPM_237:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(139)
);
PPM_238:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(150)
);
PPM_239:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(163)
);
PPM_240:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(175)
);
PPM_241:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(189)
);
PPM_242:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(202)
);
PPM_243:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(217)
);
PPM_244:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(231)
);
PPM_245:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(247)
);
PPM_246:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(262)
);
PPM_247:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(279)
);
PPM_248:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(295)
);
PPM_249:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(313)
);
PPM_250:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(331)
);
PPM_251:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(348)
);
PPM_252:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(364)
);
PPM_253:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(380)
);
PPM_254:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(395)
);
PPM_255:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(410)
);
PPM_256:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(424)
);
PPM_257:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(438)
);
PPM_258:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(451)
);
PPM_259:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(464)
);
PPM_260:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(476)
);
PPM_261:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(488)
);
PPM_262:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(499)
);
PPM_263:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(509)
);
SUMMAND(510) <= LOGIC_ONE;
PPH_7:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(520)
);
-- Begin partial product 8
-- Begin decoder block 9
DEC_8:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35)
);
-- End decoder block 9
-- Begin partial product 9
PPL_8:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(88)
);
RGATE_8:R_GATE
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
PPBIT => SUMMAND(89)
);
PPM_264:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(98)
);
PPM_265:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(107)
);
PPM_266:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(118)
);
PPM_267:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(128)
);
PPM_268:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(140)
);
PPM_269:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(151)
);
PPM_270:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(164)
);
PPM_271:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(176)
);
PPM_272:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(190)
);
PPM_273:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(203)
);
PPM_274:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(218)
);
PPM_275:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(232)
);
PPM_276:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(248)
);
PPM_277:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(263)
);
PPM_278:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(280)
);
PPM_279:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(296)
);
PPM_280:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(314)
);
PPM_281:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(332)
);
PPM_282:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(349)
);
PPM_283:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(365)
);
PPM_284:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(381)
);
PPM_285:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(396)
);
PPM_286:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(411)
);
PPM_287:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(425)
);
PPM_288:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(439)
);
PPM_289:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(452)
);
PPM_290:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(465)
);
PPM_291:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(477)
);
PPM_292:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(489)
);
PPM_293:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(500)
);
PPM_294:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(511)
);
PPM_295:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(521)
);
PPM_296:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(530)
);
SUMMAND(531) <= LOGIC_ONE;
PPH_8:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(540)
);
-- Begin partial product 9
-- Begin decoder block 10
DEC_9:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(17),INB => OPB(18),INC => OPB(19),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39)
);
-- End decoder block 10
-- Begin partial product 10
PPL_9:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(108)
);
RGATE_9:R_GATE
port map
(
INA => OPB(17),INB => OPB(18),INC => OPB(19),
PPBIT => SUMMAND(109)
);
PPM_297:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(119)
);
PPM_298:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(129)
);
PPM_299:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(141)
);
PPM_300:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(152)
);
PPM_301:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(165)
);
PPM_302:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(177)
);
PPM_303:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(191)
);
PPM_304:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(204)
);
PPM_305:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(219)
);
PPM_306:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(233)
);
PPM_307:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(249)
);
PPM_308:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(264)
);
PPM_309:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(281)
);
PPM_310:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(297)
);
PPM_311:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(315)
);
PPM_312:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(333)
);
PPM_313:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(350)
);
PPM_314:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(366)
);
PPM_315:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(382)
);
PPM_316:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(397)
);
PPM_317:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(412)
);
PPM_318:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(426)
);
PPM_319:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(440)
);
PPM_320:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(453)
);
PPM_321:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(466)
);
PPM_322:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(478)
);
PPM_323:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(490)
);
PPM_324:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(501)
);
PPM_325:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(512)
);
PPM_326:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(522)
);
PPM_327:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(532)
);
PPM_328:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(541)
);
PPM_329:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(549)
);
SUMMAND(550) <= LOGIC_ONE;
PPH_9:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(558)
);
-- Begin partial product 10
-- Begin decoder block 11
DEC_10:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(19),INB => OPB(20),INC => OPB(21),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43)
);
-- End decoder block 11
-- Begin partial product 11
PPL_10:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(130)
);
RGATE_10:R_GATE
port map
(
INA => OPB(19),INB => OPB(20),INC => OPB(21),
PPBIT => SUMMAND(131)
);
PPM_330:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(142)
);
PPM_331:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(153)
);
PPM_332:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(166)
);
PPM_333:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(178)
);
PPM_334:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(192)
);
PPM_335:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(205)
);
PPM_336:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(220)
);
PPM_337:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(234)
);
PPM_338:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(250)
);
PPM_339:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(265)
);
PPM_340:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(282)
);
PPM_341:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(298)
);
PPM_342:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(316)
);
PPM_343:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(334)
);
PPM_344:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(351)
);
PPM_345:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(367)
);
PPM_346:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(383)
);
PPM_347:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(398)
);
PPM_348:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(413)
);
PPM_349:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(427)
);
PPM_350:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(441)
);
PPM_351:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(454)
);
PPM_352:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(467)
);
PPM_353:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(479)
);
PPM_354:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(491)
);
PPM_355:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(502)
);
PPM_356:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(513)
);
PPM_357:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(523)
);
PPM_358:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(533)
);
PPM_359:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(542)
);
PPM_360:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(551)
);
PPM_361:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(559)
);
PPM_362:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(566)
);
SUMMAND(567) <= LOGIC_ONE;
PPH_10:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(574)
);
-- Begin partial product 11
-- Begin decoder block 12
DEC_11:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(21),INB => OPB(22),INC => OPB(23),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47)
);
-- End decoder block 12
-- Begin partial product 12
PPL_11:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(154)
);
RGATE_11:R_GATE
port map
(
INA => OPB(21),INB => OPB(22),INC => OPB(23),
PPBIT => SUMMAND(155)
);
PPM_363:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(167)
);
PPM_364:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(179)
);
PPM_365:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(193)
);
PPM_366:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(206)
);
PPM_367:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(221)
);
PPM_368:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(235)
);
PPM_369:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(251)
);
PPM_370:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(266)
);
PPM_371:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(283)
);
PPM_372:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(299)
);
PPM_373:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(317)
);
PPM_374:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(335)
);
PPM_375:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(352)
);
PPM_376:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(368)
);
PPM_377:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(384)
);
PPM_378:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(399)
);
PPM_379:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(414)
);
PPM_380:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(428)
);
PPM_381:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(442)
);
PPM_382:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(455)
);
PPM_383:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(468)
);
PPM_384:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(480)
);
PPM_385:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(492)
);
PPM_386:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(503)
);
PPM_387:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(514)
);
PPM_388:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(524)
);
PPM_389:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(534)
);
PPM_390:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(543)
);
PPM_391:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(552)
);
PPM_392:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(560)
);
PPM_393:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(568)
);
PPM_394:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(575)
);
PPM_395:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(581)
);
SUMMAND(582) <= LOGIC_ONE;
PPH_11:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(588)
);
-- Begin partial product 12
-- Begin decoder block 13
DEC_12:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(23),INB => OPB(24),INC => OPB(25),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51)
);
-- End decoder block 13
-- Begin partial product 13
PPL_12:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(180)
);
RGATE_12:R_GATE
port map
(
INA => OPB(23),INB => OPB(24),INC => OPB(25),
PPBIT => SUMMAND(181)
);
PPM_396:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(194)
);
PPM_397:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(207)
);
PPM_398:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(222)
);
PPM_399:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(236)
);
PPM_400:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(252)
);
PPM_401:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(267)
);
PPM_402:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(284)
);
PPM_403:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(300)
);
PPM_404:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(318)
);
PPM_405:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(336)
);
PPM_406:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(353)
);
PPM_407:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(369)
);
PPM_408:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(385)
);
PPM_409:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(400)
);
PPM_410:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(415)
);
PPM_411:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(429)
);
PPM_412:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(443)
);
PPM_413:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(456)
);
PPM_414:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(469)
);
PPM_415:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(481)
);
PPM_416:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(493)
);
PPM_417:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(504)
);
PPM_418:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(515)
);
PPM_419:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(525)
);
PPM_420:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(535)
);
PPM_421:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(544)
);
PPM_422:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(553)
);
PPM_423:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(561)
);
PPM_424:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(569)
);
PPM_425:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(576)
);
PPM_426:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(583)
);
PPM_427:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(589)
);
PPM_428:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(594)
);
SUMMAND(595) <= LOGIC_ONE;
PPH_12:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(600)
);
-- Begin partial product 13
-- Begin decoder block 14
DEC_13:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(25),INB => OPB(26),INC => OPB(27),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55)
);
-- End decoder block 14
-- Begin partial product 14
PPL_13:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(208)
);
RGATE_13:R_GATE
port map
(
INA => OPB(25),INB => OPB(26),INC => OPB(27),
PPBIT => SUMMAND(209)
);
PPM_429:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(223)
);
PPM_430:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(237)
);
PPM_431:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(253)
);
PPM_432:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(268)
);
PPM_433:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(285)
);
PPM_434:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(301)
);
PPM_435:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(319)
);
PPM_436:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(337)
);
PPM_437:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(354)
);
PPM_438:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(370)
);
PPM_439:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(386)
);
PPM_440:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(401)
);
PPM_441:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(416)
);
PPM_442:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(430)
);
PPM_443:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(444)
);
PPM_444:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(457)
);
PPM_445:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(470)
);
PPM_446:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(482)
);
PPM_447:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(494)
);
PPM_448:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(505)
);
PPM_449:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(516)
);
PPM_450:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(526)
);
PPM_451:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(536)
);
PPM_452:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(545)
);
PPM_453:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(554)
);
PPM_454:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(562)
);
PPM_455:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(570)
);
PPM_456:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(577)
);
PPM_457:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(584)
);
PPM_458:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(590)
);
PPM_459:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(596)
);
PPM_460:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(601)
);
PPM_461:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(605)
);
SUMMAND(606) <= LOGIC_ONE;
PPH_13:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(610)
);
-- Begin partial product 14
-- Begin decoder block 15
DEC_14:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(27),INB => OPB(28),INC => OPB(29),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59)
);
-- End decoder block 15
-- Begin partial product 15
PPL_14:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(238)
);
RGATE_14:R_GATE
port map
(
INA => OPB(27),INB => OPB(28),INC => OPB(29),
PPBIT => SUMMAND(239)
);
PPM_462:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(254)
);
PPM_463:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(269)
);
PPM_464:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(286)
);
PPM_465:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(302)
);
PPM_466:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(320)
);
PPM_467:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(338)
);
PPM_468:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(355)
);
PPM_469:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(371)
);
PPM_470:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(387)
);
PPM_471:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(402)
);
PPM_472:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(417)
);
PPM_473:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(431)
);
PPM_474:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(445)
);
PPM_475:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(458)
);
PPM_476:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(471)
);
PPM_477:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(483)
);
PPM_478:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(495)
);
PPM_479:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(506)
);
PPM_480:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(517)
);
PPM_481:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(527)
);
PPM_482:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(537)
);
PPM_483:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(546)
);
PPM_484:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(555)
);
PPM_485:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(563)
);
PPM_486:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(571)
);
PPM_487:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(578)
);
PPM_488:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(585)
);
PPM_489:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(591)
);
PPM_490:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(597)
);
PPM_491:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(602)
);
PPM_492:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(607)
);
PPM_493:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(611)
);
PPM_494:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(614)
);
SUMMAND(615) <= LOGIC_ONE;
PPH_14:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(618)
);
-- Begin partial product 15
-- Begin decoder block 16
DEC_15:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(29),INB => OPB(30),INC => OPB(31),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63)
);
-- End decoder block 16
-- Begin partial product 16
PPL_15:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(270)
);
RGATE_15:R_GATE
port map
(
INA => OPB(29),INB => OPB(30),INC => OPB(31),
PPBIT => SUMMAND(271)
);
PPM_495:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(287)
);
PPM_496:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(303)
);
PPM_497:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(321)
);
PPM_498:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(339)
);
PPM_499:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(356)
);
PPM_500:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(372)
);
PPM_501:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(388)
);
PPM_502:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(403)
);
PPM_503:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(418)
);
PPM_504:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(432)
);
PPM_505:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(446)
);
PPM_506:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(459)
);
PPM_507:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(472)
);
PPM_508:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(484)
);
PPM_509:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(496)
);
PPM_510:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(507)
);
PPM_511:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(518)
);
PPM_512:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(528)
);
PPM_513:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(538)
);
PPM_514:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(547)
);
PPM_515:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(556)
);
PPM_516:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(564)
);
PPM_517:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(572)
);
PPM_518:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(579)
);
PPM_519:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(586)
);
PPM_520:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(592)
);
PPM_521:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(598)
);
PPM_522:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(603)
);
PPM_523:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(608)
);
PPM_524:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(612)
);
PPM_525:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(616)
);
PPM_526:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(619)
);
PPM_527:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(621)
);
SUMMAND(622) <= LOGIC_ONE;
PPH_15:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(624)
);
-- Begin partial product 16
-- Begin decoder block 17
DEC_16:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(31),INB => OPB(32),INC => OPB(33),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67)
);
-- End decoder block 17
-- Begin partial product 17
PPL_16:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(304)
);
RGATE_16:R_GATE
port map
(
INA => OPB(31),INB => OPB(32),INC => OPB(33),
PPBIT => SUMMAND(305)
);
PPM_528:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(322)
);
PPM_529:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(340)
);
PPM_530:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(357)
);
PPM_531:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(373)
);
PPM_532:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(389)
);
PPM_533:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(404)
);
PPM_534:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(419)
);
PPM_535:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(433)
);
PPM_536:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(447)
);
PPM_537:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(460)
);
PPM_538:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(473)
);
PPM_539:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(485)
);
PPM_540:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(497)
);
PPM_541:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(508)
);
PPM_542:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(519)
);
PPM_543:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(529)
);
PPM_544:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(539)
);
PPM_545:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(548)
);
PPM_546:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(557)
);
PPM_547:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(565)
);
PPM_548:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(573)
);
PPM_549:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(580)
);
PPM_550:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(587)
);
PPM_551:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(593)
);
PPM_552:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(599)
);
PPM_553:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(604)
);
PPM_554:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(609)
);
PPM_555:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(613)
);
PPM_556:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(617)
);
PPM_557:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(620)
);
PPM_558:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(623)
);
PPM_559:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(625)
);
PPM_560:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(626)
);
SUMMAND(627) <= LOGIC_ONE;
PPH_16:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(628)
);
-- Begin partial product 17
end BOOTHCODER;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity WALLACE_34_34 is
port
(
SUMMAND: in std_logic_vector(0 to 628);
CARRY: out std_logic_vector(0 to 65);
SUM: out std_logic_vector(0 to 66)
);
end WALLACE_34_34;
architecture WALLACE of WALLACE_34_34 is
-- Signals used inside the wallace trees
signal INT_CARRY: std_logic_vector(0 to 486);
signal INT_SUM: std_logic_vector(0 to 620);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End FA stage
---- Begin NO stage
INT_SUM(18) <= SUMMAND(41); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18),
SAVE => INT_SUM(19), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End HA stage
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End FA stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(23), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin NO stage
INT_SUM(24) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End FA stage
---- Begin NO stage
INT_SUM(26) <= INT_CARRY(15); -- At Level 3
---- End NO stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(25), DATA_B => INT_SUM(26),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End HA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50),
SAVE => INT_SUM(27), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin NO stage
INT_SUM(29) <= SUMMAND(54); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(30) <= SUMMAND(55); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29),
SAVE => INT_SUM(31), CARRY => INT_CARRY(22)
);
---- End FA stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17),
SAVE => INT_SUM(32), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(33), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End HA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58),
SAVE => INT_SUM(34), CARRY => INT_CARRY(25)
);
---- End FA stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61),
SAVE => INT_SUM(35), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(36) <= SUMMAND(62); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36),
SAVE => INT_SUM(37), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21),
SAVE => INT_SUM(38), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22),
SAVE => INT_SUM(39), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(40) <= INT_CARRY(23); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65),
SAVE => INT_SUM(41), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68),
SAVE => INT_SUM(42), CARRY => INT_CARRY(31)
);
---- End FA stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71),
SAVE => INT_SUM(43), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(28); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End HA stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50),
SAVE => INT_SUM(51), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32),
SAVE => INT_SUM(52), CARRY => INT_CARRY(40)
);
---- End FA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(53), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(54) <= INT_CARRY(34); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(55), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85),
SAVE => INT_SUM(56), CARRY => INT_CARRY(43)
);
---- End FA stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88),
SAVE => INT_SUM(57), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(58) <= SUMMAND(89); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57),
SAVE => INT_SUM(59), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37),
SAVE => INT_SUM(60), CARRY => INT_CARRY(46)
);
---- End FA stage
---- Begin NO stage
INT_SUM(61) <= INT_CARRY(38); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40),
SAVE => INT_SUM(63), CARRY => INT_CARRY(48)
);
---- End HA stage
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(64), CARRY => INT_CARRY(49)
);
---- End FA stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95),
SAVE => INT_SUM(65), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98),
SAVE => INT_SUM(66), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66),
SAVE => INT_SUM(67), CARRY => INT_CARRY(52)
);
---- End FA stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44),
SAVE => INT_SUM(68), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(69), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin NO stage
INT_SUM(70) <= INT_CARRY(46); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47),
SAVE => INT_SUM(71), CARRY => INT_CARRY(55)
);
---- End FA stage
---- Begin NO stage
INT_SUM(72) <= INT_CARRY(48); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(71), DATA_B => INT_SUM(72),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End HA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101),
SAVE => INT_SUM(73), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104),
SAVE => INT_SUM(74), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(75), CARRY => INT_CARRY(58)
);
---- End FA stage
---- Begin NO stage
INT_SUM(76) <= SUMMAND(108); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(77) <= SUMMAND(109); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75),
SAVE => INT_SUM(78), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(49),
SAVE => INT_SUM(79), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin NO stage
INT_SUM(80) <= INT_CARRY(50); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(81) <= INT_CARRY(51); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_SUM(80),
SAVE => INT_SUM(82), CARRY => INT_CARRY(61)
);
---- End FA stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(81), DATA_B => INT_CARRY(52), DATA_C => INT_CARRY(53),
SAVE => INT_SUM(83), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(54),
SAVE => INT_SUM(84), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(84), DATA_B => INT_CARRY(55),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End HA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112),
SAVE => INT_SUM(85), CARRY => INT_CARRY(64)
);
---- End FA stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), DATA_C => SUMMAND(115),
SAVE => INT_SUM(86), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(116), DATA_B => SUMMAND(117), DATA_C => SUMMAND(118),
SAVE => INT_SUM(87), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin NO stage
INT_SUM(88) <= SUMMAND(119); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87),
SAVE => INT_SUM(89), CARRY => INT_CARRY(67)
);
---- End FA stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_CARRY(56), DATA_C => INT_CARRY(57),
SAVE => INT_SUM(90), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin NO stage
INT_SUM(91) <= INT_CARRY(58); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91),
SAVE => INT_SUM(92), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(59), DATA_B => INT_CARRY(60),
SAVE => INT_SUM(93), CARRY => INT_CARRY(70)
);
---- End HA stage
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(61),
SAVE => INT_SUM(94), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin NO stage
INT_SUM(95) <= INT_CARRY(62); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(63),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End FA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122),
SAVE => INT_SUM(96), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125),
SAVE => INT_SUM(97), CARRY => INT_CARRY(73)
);
---- End FA stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128),
SAVE => INT_SUM(98), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131),
SAVE => INT_SUM(99), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_SUM(98),
SAVE => INT_SUM(100), CARRY => INT_CARRY(76)
);
---- End FA stage
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(99), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65),
SAVE => INT_SUM(101), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin NO stage
INT_SUM(102) <= INT_CARRY(66); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_SUM(102),
SAVE => INT_SUM(103), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(67), DATA_B => INT_CARRY(68),
SAVE => INT_SUM(104), CARRY => INT_CARRY(79)
);
---- End HA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(103), DATA_B => INT_SUM(104), DATA_C => INT_CARRY(69),
SAVE => INT_SUM(105), CARRY => INT_CARRY(80)
);
---- End FA stage
---- Begin NO stage
INT_SUM(106) <= INT_CARRY(70); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_CARRY(71),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End FA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134),
SAVE => INT_SUM(107), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137),
SAVE => INT_SUM(108), CARRY => INT_CARRY(82)
);
---- End FA stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140),
SAVE => INT_SUM(109), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin NO stage
INT_SUM(110) <= SUMMAND(141); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(111) <= SUMMAND(142); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(107), DATA_B => INT_SUM(108), DATA_C => INT_SUM(109),
SAVE => INT_SUM(112), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(72),
SAVE => INT_SUM(113), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(73), DATA_B => INT_CARRY(74), DATA_C => INT_CARRY(75),
SAVE => INT_SUM(114), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_SUM(114),
SAVE => INT_SUM(115), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77),
SAVE => INT_SUM(116), CARRY => INT_CARRY(88)
);
---- End HA stage
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(78),
SAVE => INT_SUM(117), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin NO stage
INT_SUM(118) <= INT_CARRY(79); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_CARRY(80),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End FA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), DATA_C => SUMMAND(145),
SAVE => INT_SUM(119), CARRY => INT_CARRY(90)
);
---- End FA stage
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(146), DATA_B => SUMMAND(147), DATA_C => SUMMAND(148),
SAVE => INT_SUM(120), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(149), DATA_B => SUMMAND(150), DATA_C => SUMMAND(151),
SAVE => INT_SUM(121), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(152), DATA_B => SUMMAND(153), DATA_C => SUMMAND(154),
SAVE => INT_SUM(122), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin NO stage
INT_SUM(123) <= SUMMAND(155); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(119), DATA_B => INT_SUM(120), DATA_C => INT_SUM(121),
SAVE => INT_SUM(124), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(81),
SAVE => INT_SUM(125), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83),
SAVE => INT_SUM(126), CARRY => INT_CARRY(96)
);
---- End HA stage
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_SUM(126),
SAVE => INT_SUM(127), CARRY => INT_CARRY(97)
);
---- End FA stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86),
SAVE => INT_SUM(128), CARRY => INT_CARRY(98)
);
---- End FA stage
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(127), DATA_B => INT_SUM(128), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(129), CARRY => INT_CARRY(99)
);
---- End FA stage
---- Begin NO stage
INT_SUM(130) <= INT_CARRY(88); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_CARRY(89),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End FA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_101:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158),
SAVE => INT_SUM(131), CARRY => INT_CARRY(100)
);
---- End FA stage
---- Begin FA stage
FA_102:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161),
SAVE => INT_SUM(132), CARRY => INT_CARRY(101)
);
---- End FA stage
---- Begin FA stage
FA_103:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164),
SAVE => INT_SUM(133), CARRY => INT_CARRY(102)
);
---- End FA stage
---- Begin FA stage
FA_104:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167),
SAVE => INT_SUM(134), CARRY => INT_CARRY(103)
);
---- End FA stage
---- Begin FA stage
FA_105:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(131), DATA_B => INT_SUM(132), DATA_C => INT_SUM(133),
SAVE => INT_SUM(135), CARRY => INT_CARRY(104)
);
---- End FA stage
---- Begin FA stage
FA_106:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(134), DATA_B => INT_CARRY(90), DATA_C => INT_CARRY(91),
SAVE => INT_SUM(136), CARRY => INT_CARRY(105)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(92), DATA_B => INT_CARRY(93),
SAVE => INT_SUM(137), CARRY => INT_CARRY(106)
);
---- End HA stage
---- Begin FA stage
FA_107:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_SUM(137),
SAVE => INT_SUM(138), CARRY => INT_CARRY(107)
);
---- End FA stage
---- Begin FA stage
FA_108:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(94), DATA_B => INT_CARRY(95), DATA_C => INT_CARRY(96),
SAVE => INT_SUM(139), CARRY => INT_CARRY(108)
);
---- End FA stage
---- Begin FA stage
FA_109:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(138), DATA_B => INT_SUM(139), DATA_C => INT_CARRY(97),
SAVE => INT_SUM(140), CARRY => INT_CARRY(109)
);
---- End FA stage
---- Begin NO stage
INT_SUM(141) <= INT_CARRY(98); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_110:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(99),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End FA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_111:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170),
SAVE => INT_SUM(142), CARRY => INT_CARRY(110)
);
---- End FA stage
---- Begin FA stage
FA_112:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173),
SAVE => INT_SUM(143), CARRY => INT_CARRY(111)
);
---- End FA stage
---- Begin FA stage
FA_113:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(144), CARRY => INT_CARRY(112)
);
---- End FA stage
---- Begin FA stage
FA_114:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179),
SAVE => INT_SUM(145), CARRY => INT_CARRY(113)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(180), DATA_B => SUMMAND(181),
SAVE => INT_SUM(146), CARRY => INT_CARRY(114)
);
---- End HA stage
---- Begin FA stage
FA_115:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_SUM(144),
SAVE => INT_SUM(147), CARRY => INT_CARRY(115)
);
---- End FA stage
---- Begin FA stage
FA_116:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(100),
SAVE => INT_SUM(148), CARRY => INT_CARRY(116)
);
---- End FA stage
---- Begin FA stage
FA_117:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(101), DATA_B => INT_CARRY(102), DATA_C => INT_CARRY(103),
SAVE => INT_SUM(149), CARRY => INT_CARRY(117)
);
---- End FA stage
---- Begin FA stage
FA_118:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(147), DATA_B => INT_SUM(148), DATA_C => INT_SUM(149),
SAVE => INT_SUM(150), CARRY => INT_CARRY(118)
);
---- End FA stage
---- Begin FA stage
FA_119:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(104), DATA_B => INT_CARRY(105), DATA_C => INT_CARRY(106),
SAVE => INT_SUM(151), CARRY => INT_CARRY(119)
);
---- End FA stage
---- Begin FA stage
FA_120:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(107),
SAVE => INT_SUM(152), CARRY => INT_CARRY(120)
);
---- End FA stage
---- Begin NO stage
INT_SUM(153) <= INT_CARRY(108); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_121:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(152), DATA_B => INT_SUM(153), DATA_C => INT_CARRY(109),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End FA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_122:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), DATA_C => SUMMAND(184),
SAVE => INT_SUM(154), CARRY => INT_CARRY(121)
);
---- End FA stage
---- Begin FA stage
FA_123:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(185), DATA_B => SUMMAND(186), DATA_C => SUMMAND(187),
SAVE => INT_SUM(155), CARRY => INT_CARRY(122)
);
---- End FA stage
---- Begin FA stage
FA_124:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(188), DATA_B => SUMMAND(189), DATA_C => SUMMAND(190),
SAVE => INT_SUM(156), CARRY => INT_CARRY(123)
);
---- End FA stage
---- Begin FA stage
FA_125:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(191), DATA_B => SUMMAND(192), DATA_C => SUMMAND(193),
SAVE => INT_SUM(157), CARRY => INT_CARRY(124)
);
---- End FA stage
---- Begin NO stage
INT_SUM(158) <= SUMMAND(194); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_126:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(154), DATA_B => INT_SUM(155), DATA_C => INT_SUM(156),
SAVE => INT_SUM(159), CARRY => INT_CARRY(125)
);
---- End FA stage
---- Begin FA stage
FA_127:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(110),
SAVE => INT_SUM(160), CARRY => INT_CARRY(126)
);
---- End FA stage
---- Begin FA stage
FA_128:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(111), DATA_B => INT_CARRY(112), DATA_C => INT_CARRY(113),
SAVE => INT_SUM(161), CARRY => INT_CARRY(127)
);
---- End FA stage
---- Begin NO stage
INT_SUM(162) <= INT_CARRY(114); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_129:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(159), DATA_B => INT_SUM(160), DATA_C => INT_SUM(161),
SAVE => INT_SUM(163), CARRY => INT_CARRY(128)
);
---- End FA stage
---- Begin FA stage
FA_130:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(162), DATA_B => INT_CARRY(115), DATA_C => INT_CARRY(116),
SAVE => INT_SUM(164), CARRY => INT_CARRY(129)
);
---- End FA stage
---- Begin NO stage
INT_SUM(165) <= INT_CARRY(117); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_131:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(163), DATA_B => INT_SUM(164), DATA_C => INT_SUM(165),
SAVE => INT_SUM(166), CARRY => INT_CARRY(130)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(118), DATA_B => INT_CARRY(119),
SAVE => INT_SUM(167), CARRY => INT_CARRY(131)
);
---- End HA stage
---- Begin FA stage
FA_132:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(120),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End FA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_133:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197),
SAVE => INT_SUM(168), CARRY => INT_CARRY(132)
);
---- End FA stage
---- Begin FA stage
FA_134:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200),
SAVE => INT_SUM(169), CARRY => INT_CARRY(133)
);
---- End FA stage
---- Begin FA stage
FA_135:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203),
SAVE => INT_SUM(170), CARRY => INT_CARRY(134)
);
---- End FA stage
---- Begin FA stage
FA_136:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206),
SAVE => INT_SUM(171), CARRY => INT_CARRY(135)
);
---- End FA stage
---- Begin FA stage
FA_137:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209),
SAVE => INT_SUM(172), CARRY => INT_CARRY(136)
);
---- End FA stage
---- Begin FA stage
FA_138:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(168), DATA_B => INT_SUM(169), DATA_C => INT_SUM(170),
SAVE => INT_SUM(173), CARRY => INT_CARRY(137)
);
---- End FA stage
---- Begin FA stage
FA_139:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(171), DATA_B => INT_SUM(172), DATA_C => INT_CARRY(121),
SAVE => INT_SUM(174), CARRY => INT_CARRY(138)
);
---- End FA stage
---- Begin FA stage
FA_140:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(122), DATA_B => INT_CARRY(123), DATA_C => INT_CARRY(124),
SAVE => INT_SUM(175), CARRY => INT_CARRY(139)
);
---- End FA stage
---- Begin FA stage
FA_141:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(173), DATA_B => INT_SUM(174), DATA_C => INT_SUM(175),
SAVE => INT_SUM(176), CARRY => INT_CARRY(140)
);
---- End FA stage
---- Begin FA stage
FA_142:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(125), DATA_B => INT_CARRY(126), DATA_C => INT_CARRY(127),
SAVE => INT_SUM(177), CARRY => INT_CARRY(141)
);
---- End FA stage
---- Begin FA stage
FA_143:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(176), DATA_B => INT_SUM(177), DATA_C => INT_CARRY(128),
SAVE => INT_SUM(178), CARRY => INT_CARRY(142)
);
---- End FA stage
---- Begin NO stage
INT_SUM(179) <= INT_CARRY(129); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_144:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(178), DATA_B => INT_SUM(179), DATA_C => INT_CARRY(130),
SAVE => INT_SUM(180), CARRY => INT_CARRY(143)
);
---- End FA stage
---- Begin NO stage
INT_SUM(181) <= INT_CARRY(131); -- At Level 5
---- End NO stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(180), DATA_B => INT_SUM(181),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End HA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_145:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212),
SAVE => INT_SUM(182), CARRY => INT_CARRY(144)
);
---- End FA stage
---- Begin FA stage
FA_146:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215),
SAVE => INT_SUM(183), CARRY => INT_CARRY(145)
);
---- End FA stage
---- Begin FA stage
FA_147:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218),
SAVE => INT_SUM(184), CARRY => INT_CARRY(146)
);
---- End FA stage
---- Begin FA stage
FA_148:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221),
SAVE => INT_SUM(185), CARRY => INT_CARRY(147)
);
---- End FA stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(222), DATA_B => SUMMAND(223),
SAVE => INT_SUM(186), CARRY => INT_CARRY(148)
);
---- End HA stage
---- Begin FA stage
FA_149:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_SUM(184),
SAVE => INT_SUM(187), CARRY => INT_CARRY(149)
);
---- End FA stage
---- Begin FA stage
FA_150:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_CARRY(132),
SAVE => INT_SUM(188), CARRY => INT_CARRY(150)
);
---- End FA stage
---- Begin FA stage
FA_151:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135),
SAVE => INT_SUM(189), CARRY => INT_CARRY(151)
);
---- End FA stage
---- Begin NO stage
INT_SUM(190) <= INT_CARRY(136); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_152:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(187), DATA_B => INT_SUM(188), DATA_C => INT_SUM(189),
SAVE => INT_SUM(191), CARRY => INT_CARRY(152)
);
---- End FA stage
---- Begin FA stage
FA_153:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(190), DATA_B => INT_CARRY(137), DATA_C => INT_CARRY(138),
SAVE => INT_SUM(192), CARRY => INT_CARRY(153)
);
---- End FA stage
---- Begin NO stage
INT_SUM(193) <= INT_CARRY(139); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_154:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(191), DATA_B => INT_SUM(192), DATA_C => INT_SUM(193),
SAVE => INT_SUM(194), CARRY => INT_CARRY(154)
);
---- End FA stage
---- Begin NO stage
INT_SUM(195) <= INT_CARRY(140); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(196) <= INT_CARRY(141); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_155:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(194), DATA_B => INT_SUM(195), DATA_C => INT_SUM(196),
SAVE => INT_SUM(197), CARRY => INT_CARRY(155)
);
---- End FA stage
---- Begin NO stage
INT_SUM(198) <= INT_CARRY(142); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_156:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(197), DATA_B => INT_SUM(198), DATA_C => INT_CARRY(143),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End FA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_157:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(224), DATA_B => SUMMAND(225), DATA_C => SUMMAND(226),
SAVE => INT_SUM(199), CARRY => INT_CARRY(156)
);
---- End FA stage
---- Begin FA stage
FA_158:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(227), DATA_B => SUMMAND(228), DATA_C => SUMMAND(229),
SAVE => INT_SUM(200), CARRY => INT_CARRY(157)
);
---- End FA stage
---- Begin FA stage
FA_159:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(230), DATA_B => SUMMAND(231), DATA_C => SUMMAND(232),
SAVE => INT_SUM(201), CARRY => INT_CARRY(158)
);
---- End FA stage
---- Begin FA stage
FA_160:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(233), DATA_B => SUMMAND(234), DATA_C => SUMMAND(235),
SAVE => INT_SUM(202), CARRY => INT_CARRY(159)
);
---- End FA stage
---- Begin FA stage
FA_161:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(236), DATA_B => SUMMAND(237), DATA_C => SUMMAND(238),
SAVE => INT_SUM(203), CARRY => INT_CARRY(160)
);
---- End FA stage
---- Begin NO stage
INT_SUM(204) <= SUMMAND(239); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_162:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(199), DATA_B => INT_SUM(200), DATA_C => INT_SUM(201),
SAVE => INT_SUM(205), CARRY => INT_CARRY(161)
);
---- End FA stage
---- Begin FA stage
FA_163:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(202), DATA_B => INT_SUM(203), DATA_C => INT_SUM(204),
SAVE => INT_SUM(206), CARRY => INT_CARRY(162)
);
---- End FA stage
---- Begin FA stage
FA_164:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(144), DATA_B => INT_CARRY(145), DATA_C => INT_CARRY(146),
SAVE => INT_SUM(207), CARRY => INT_CARRY(163)
);
---- End FA stage
---- Begin NO stage
INT_SUM(208) <= INT_CARRY(147); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(209) <= INT_CARRY(148); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_165:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207),
SAVE => INT_SUM(210), CARRY => INT_CARRY(164)
);
---- End FA stage
---- Begin FA stage
FA_166:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_CARRY(149),
SAVE => INT_SUM(211), CARRY => INT_CARRY(165)
);
---- End FA stage
---- Begin NO stage
INT_SUM(212) <= INT_CARRY(150); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(213) <= INT_CARRY(151); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_167:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(210), DATA_B => INT_SUM(211), DATA_C => INT_SUM(212),
SAVE => INT_SUM(214), CARRY => INT_CARRY(166)
);
---- End FA stage
---- Begin FA stage
FA_168:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(213), DATA_B => INT_CARRY(152), DATA_C => INT_CARRY(153),
SAVE => INT_SUM(215), CARRY => INT_CARRY(167)
);
---- End FA stage
---- Begin FA stage
FA_169:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(214), DATA_B => INT_SUM(215), DATA_C => INT_CARRY(154),
SAVE => INT_SUM(216), CARRY => INT_CARRY(168)
);
---- End FA stage
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(216), DATA_B => INT_CARRY(155),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End HA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_170:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242),
SAVE => INT_SUM(217), CARRY => INT_CARRY(169)
);
---- End FA stage
---- Begin FA stage
FA_171:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245),
SAVE => INT_SUM(218), CARRY => INT_CARRY(170)
);
---- End FA stage
---- Begin FA stage
FA_172:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248),
SAVE => INT_SUM(219), CARRY => INT_CARRY(171)
);
---- End FA stage
---- Begin FA stage
FA_173:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251),
SAVE => INT_SUM(220), CARRY => INT_CARRY(172)
);
---- End FA stage
---- Begin FA stage
FA_174:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(252), DATA_B => SUMMAND(253), DATA_C => SUMMAND(254),
SAVE => INT_SUM(221), CARRY => INT_CARRY(173)
);
---- End FA stage
---- Begin FA stage
FA_175:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_SUM(219),
SAVE => INT_SUM(222), CARRY => INT_CARRY(174)
);
---- End FA stage
---- Begin FA stage
FA_176:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_CARRY(156),
SAVE => INT_SUM(223), CARRY => INT_CARRY(175)
);
---- End FA stage
---- Begin FA stage
FA_177:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(157), DATA_B => INT_CARRY(158), DATA_C => INT_CARRY(159),
SAVE => INT_SUM(224), CARRY => INT_CARRY(176)
);
---- End FA stage
---- Begin NO stage
INT_SUM(225) <= INT_CARRY(160); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_178:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(222), DATA_B => INT_SUM(223), DATA_C => INT_SUM(224),
SAVE => INT_SUM(226), CARRY => INT_CARRY(177)
);
---- End FA stage
---- Begin FA stage
FA_179:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(225), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162),
SAVE => INT_SUM(227), CARRY => INT_CARRY(178)
);
---- End FA stage
---- Begin NO stage
INT_SUM(228) <= INT_CARRY(163); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_180:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_SUM(228),
SAVE => INT_SUM(229), CARRY => INT_CARRY(179)
);
---- End FA stage
---- Begin HA stage
HA_27:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(164), DATA_B => INT_CARRY(165),
SAVE => INT_SUM(230), CARRY => INT_CARRY(180)
);
---- End HA stage
---- Begin FA stage
FA_181:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(229), DATA_B => INT_SUM(230), DATA_C => INT_CARRY(166),
SAVE => INT_SUM(231), CARRY => INT_CARRY(181)
);
---- End FA stage
---- Begin NO stage
INT_SUM(232) <= INT_CARRY(167); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_182:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(231), DATA_B => INT_SUM(232), DATA_C => INT_CARRY(168),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End FA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_183:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(255), DATA_B => SUMMAND(256), DATA_C => SUMMAND(257),
SAVE => INT_SUM(233), CARRY => INT_CARRY(182)
);
---- End FA stage
---- Begin FA stage
FA_184:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(258), DATA_B => SUMMAND(259), DATA_C => SUMMAND(260),
SAVE => INT_SUM(234), CARRY => INT_CARRY(183)
);
---- End FA stage
---- Begin FA stage
FA_185:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(261), DATA_B => SUMMAND(262), DATA_C => SUMMAND(263),
SAVE => INT_SUM(235), CARRY => INT_CARRY(184)
);
---- End FA stage
---- Begin FA stage
FA_186:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(264), DATA_B => SUMMAND(265), DATA_C => SUMMAND(266),
SAVE => INT_SUM(236), CARRY => INT_CARRY(185)
);
---- End FA stage
---- Begin FA stage
FA_187:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(267), DATA_B => SUMMAND(268), DATA_C => SUMMAND(269),
SAVE => INT_SUM(237), CARRY => INT_CARRY(186)
);
---- End FA stage
---- Begin NO stage
INT_SUM(238) <= SUMMAND(270); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(239) <= SUMMAND(271); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_188:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(233), DATA_B => INT_SUM(234), DATA_C => INT_SUM(235),
SAVE => INT_SUM(240), CARRY => INT_CARRY(187)
);
---- End FA stage
---- Begin FA stage
FA_189:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_SUM(238),
SAVE => INT_SUM(241), CARRY => INT_CARRY(188)
);
---- End FA stage
---- Begin FA stage
FA_190:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(239), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170),
SAVE => INT_SUM(242), CARRY => INT_CARRY(189)
);
---- End FA stage
---- Begin FA stage
FA_191:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(171), DATA_B => INT_CARRY(172), DATA_C => INT_CARRY(173),
SAVE => INT_SUM(243), CARRY => INT_CARRY(190)
);
---- End FA stage
---- Begin FA stage
FA_192:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(240), DATA_B => INT_SUM(241), DATA_C => INT_SUM(242),
SAVE => INT_SUM(244), CARRY => INT_CARRY(191)
);
---- End FA stage
---- Begin FA stage
FA_193:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(243), DATA_B => INT_CARRY(174), DATA_C => INT_CARRY(175),
SAVE => INT_SUM(245), CARRY => INT_CARRY(192)
);
---- End FA stage
---- Begin NO stage
INT_SUM(246) <= INT_CARRY(176); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_194:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(244), DATA_B => INT_SUM(245), DATA_C => INT_SUM(246),
SAVE => INT_SUM(247), CARRY => INT_CARRY(193)
);
---- End FA stage
---- Begin HA stage
HA_28:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(177), DATA_B => INT_CARRY(178),
SAVE => INT_SUM(248), CARRY => INT_CARRY(194)
);
---- End HA stage
---- Begin FA stage
FA_195:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(247), DATA_B => INT_SUM(248), DATA_C => INT_CARRY(179),
SAVE => INT_SUM(249), CARRY => INT_CARRY(195)
);
---- End FA stage
---- Begin NO stage
INT_SUM(250) <= INT_CARRY(180); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_196:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(249), DATA_B => INT_SUM(250), DATA_C => INT_CARRY(181),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End FA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_197:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(272), DATA_B => SUMMAND(273), DATA_C => SUMMAND(274),
SAVE => INT_SUM(251), CARRY => INT_CARRY(196)
);
---- End FA stage
---- Begin FA stage
FA_198:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(275), DATA_B => SUMMAND(276), DATA_C => SUMMAND(277),
SAVE => INT_SUM(252), CARRY => INT_CARRY(197)
);
---- End FA stage
---- Begin FA stage
FA_199:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280),
SAVE => INT_SUM(253), CARRY => INT_CARRY(198)
);
---- End FA stage
---- Begin FA stage
FA_200:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283),
SAVE => INT_SUM(254), CARRY => INT_CARRY(199)
);
---- End FA stage
---- Begin FA stage
FA_201:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(284), DATA_B => SUMMAND(285), DATA_C => SUMMAND(286),
SAVE => INT_SUM(255), CARRY => INT_CARRY(200)
);
---- End FA stage
---- Begin NO stage
INT_SUM(256) <= SUMMAND(287); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_202:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(251), DATA_B => INT_SUM(252), DATA_C => INT_SUM(253),
SAVE => INT_SUM(257), CARRY => INT_CARRY(201)
);
---- End FA stage
---- Begin FA stage
FA_203:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_SUM(256),
SAVE => INT_SUM(258), CARRY => INT_CARRY(202)
);
---- End FA stage
---- Begin FA stage
FA_204:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(182), DATA_B => INT_CARRY(183), DATA_C => INT_CARRY(184),
SAVE => INT_SUM(259), CARRY => INT_CARRY(203)
);
---- End FA stage
---- Begin NO stage
INT_SUM(260) <= INT_CARRY(185); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(261) <= INT_CARRY(186); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_205:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(257), DATA_B => INT_SUM(258), DATA_C => INT_SUM(259),
SAVE => INT_SUM(262), CARRY => INT_CARRY(204)
);
---- End FA stage
---- Begin FA stage
FA_206:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(187),
SAVE => INT_SUM(263), CARRY => INT_CARRY(205)
);
---- End FA stage
---- Begin FA stage
FA_207:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190),
SAVE => INT_SUM(264), CARRY => INT_CARRY(206)
);
---- End FA stage
---- Begin FA stage
FA_208:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(262), DATA_B => INT_SUM(263), DATA_C => INT_SUM(264),
SAVE => INT_SUM(265), CARRY => INT_CARRY(207)
);
---- End FA stage
---- Begin HA stage
HA_29:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(191), DATA_B => INT_CARRY(192),
SAVE => INT_SUM(266), CARRY => INT_CARRY(208)
);
---- End HA stage
---- Begin FA stage
FA_209:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(193),
SAVE => INT_SUM(267), CARRY => INT_CARRY(209)
);
---- End FA stage
---- Begin NO stage
INT_SUM(268) <= INT_CARRY(194); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_210:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(267), DATA_B => INT_SUM(268), DATA_C => INT_CARRY(195),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End FA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin FA stage
FA_211:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290),
SAVE => INT_SUM(269), CARRY => INT_CARRY(210)
);
---- End FA stage
---- Begin FA stage
FA_212:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(291), DATA_B => SUMMAND(292), DATA_C => SUMMAND(293),
SAVE => INT_SUM(270), CARRY => INT_CARRY(211)
);
---- End FA stage
---- Begin FA stage
FA_213:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(294), DATA_B => SUMMAND(295), DATA_C => SUMMAND(296),
SAVE => INT_SUM(271), CARRY => INT_CARRY(212)
);
---- End FA stage
---- Begin FA stage
FA_214:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(297), DATA_B => SUMMAND(298), DATA_C => SUMMAND(299),
SAVE => INT_SUM(272), CARRY => INT_CARRY(213)
);
---- End FA stage
---- Begin FA stage
FA_215:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(300), DATA_B => SUMMAND(301), DATA_C => SUMMAND(302),
SAVE => INT_SUM(273), CARRY => INT_CARRY(214)
);
---- End FA stage
---- Begin FA stage
FA_216:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(303), DATA_B => SUMMAND(304), DATA_C => SUMMAND(305),
SAVE => INT_SUM(274), CARRY => INT_CARRY(215)
);
---- End FA stage
---- Begin FA stage
FA_217:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(269), DATA_B => INT_SUM(270), DATA_C => INT_SUM(271),
SAVE => INT_SUM(275), CARRY => INT_CARRY(216)
);
---- End FA stage
---- Begin FA stage
FA_218:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(272), DATA_B => INT_SUM(273), DATA_C => INT_SUM(274),
SAVE => INT_SUM(276), CARRY => INT_CARRY(217)
);
---- End FA stage
---- Begin FA stage
FA_219:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(196), DATA_B => INT_CARRY(197), DATA_C => INT_CARRY(198),
SAVE => INT_SUM(277), CARRY => INT_CARRY(218)
);
---- End FA stage
---- Begin HA stage
HA_30:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(199), DATA_B => INT_CARRY(200),
SAVE => INT_SUM(278), CARRY => INT_CARRY(219)
);
---- End HA stage
---- Begin FA stage
FA_220:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(275), DATA_B => INT_SUM(276), DATA_C => INT_SUM(277),
SAVE => INT_SUM(279), CARRY => INT_CARRY(220)
);
---- End FA stage
---- Begin FA stage
FA_221:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(278), DATA_B => INT_CARRY(201), DATA_C => INT_CARRY(202),
SAVE => INT_SUM(280), CARRY => INT_CARRY(221)
);
---- End FA stage
---- Begin NO stage
INT_SUM(281) <= INT_CARRY(203); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_222:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(279), DATA_B => INT_SUM(280), DATA_C => INT_SUM(281),
SAVE => INT_SUM(282), CARRY => INT_CARRY(222)
);
---- End FA stage
---- Begin FA stage
FA_223:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(204), DATA_B => INT_CARRY(205), DATA_C => INT_CARRY(206),
SAVE => INT_SUM(283), CARRY => INT_CARRY(223)
);
---- End FA stage
---- Begin FA stage
FA_224:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(282), DATA_B => INT_SUM(283), DATA_C => INT_CARRY(207),
SAVE => INT_SUM(284), CARRY => INT_CARRY(224)
);
---- End FA stage
---- Begin NO stage
INT_SUM(285) <= INT_CARRY(208); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_225:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(284), DATA_B => INT_SUM(285), DATA_C => INT_CARRY(209),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End FA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin FA stage
FA_226:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(306), DATA_B => SUMMAND(307), DATA_C => SUMMAND(308),
SAVE => INT_SUM(286), CARRY => INT_CARRY(225)
);
---- End FA stage
---- Begin FA stage
FA_227:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311),
SAVE => INT_SUM(287), CARRY => INT_CARRY(226)
);
---- End FA stage
---- Begin FA stage
FA_228:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), DATA_C => SUMMAND(314),
SAVE => INT_SUM(288), CARRY => INT_CARRY(227)
);
---- End FA stage
---- Begin FA stage
FA_229:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(315), DATA_B => SUMMAND(316), DATA_C => SUMMAND(317),
SAVE => INT_SUM(289), CARRY => INT_CARRY(228)
);
---- End FA stage
---- Begin FA stage
FA_230:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320),
SAVE => INT_SUM(290), CARRY => INT_CARRY(229)
);
---- End FA stage
---- Begin NO stage
INT_SUM(291) <= SUMMAND(321); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(292) <= SUMMAND(322); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_231:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(286), DATA_B => INT_SUM(287), DATA_C => INT_SUM(288),
SAVE => INT_SUM(293), CARRY => INT_CARRY(230)
);
---- End FA stage
---- Begin FA stage
FA_232:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(289), DATA_B => INT_SUM(290), DATA_C => INT_SUM(291),
SAVE => INT_SUM(294), CARRY => INT_CARRY(231)
);
---- End FA stage
---- Begin FA stage
FA_233:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(292), DATA_B => INT_CARRY(210), DATA_C => INT_CARRY(211),
SAVE => INT_SUM(295), CARRY => INT_CARRY(232)
);
---- End FA stage
---- Begin FA stage
FA_234:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(212), DATA_B => INT_CARRY(213), DATA_C => INT_CARRY(214),
SAVE => INT_SUM(296), CARRY => INT_CARRY(233)
);
---- End FA stage
---- Begin NO stage
INT_SUM(297) <= INT_CARRY(215); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_235:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(293), DATA_B => INT_SUM(294), DATA_C => INT_SUM(295),
SAVE => INT_SUM(298), CARRY => INT_CARRY(234)
);
---- End FA stage
---- Begin FA stage
FA_236:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(296), DATA_B => INT_SUM(297), DATA_C => INT_CARRY(216),
SAVE => INT_SUM(299), CARRY => INT_CARRY(235)
);
---- End FA stage
---- Begin FA stage
FA_237:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(217), DATA_B => INT_CARRY(218), DATA_C => INT_CARRY(219),
SAVE => INT_SUM(300), CARRY => INT_CARRY(236)
);
---- End FA stage
---- Begin FA stage
FA_238:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(298), DATA_B => INT_SUM(299), DATA_C => INT_SUM(300),
SAVE => INT_SUM(301), CARRY => INT_CARRY(237)
);
---- End FA stage
---- Begin HA stage
HA_31:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(220), DATA_B => INT_CARRY(221),
SAVE => INT_SUM(302), CARRY => INT_CARRY(238)
);
---- End HA stage
---- Begin FA stage
FA_239:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(301), DATA_B => INT_SUM(302), DATA_C => INT_CARRY(222),
SAVE => INT_SUM(303), CARRY => INT_CARRY(239)
);
---- End FA stage
---- Begin NO stage
INT_SUM(304) <= INT_CARRY(223); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_240:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(303), DATA_B => INT_SUM(304), DATA_C => INT_CARRY(224),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End FA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin FA stage
FA_241:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(323), DATA_B => SUMMAND(324), DATA_C => SUMMAND(325),
SAVE => INT_SUM(305), CARRY => INT_CARRY(240)
);
---- End FA stage
---- Begin FA stage
FA_242:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(326), DATA_B => SUMMAND(327), DATA_C => SUMMAND(328),
SAVE => INT_SUM(306), CARRY => INT_CARRY(241)
);
---- End FA stage
---- Begin FA stage
FA_243:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(329), DATA_B => SUMMAND(330), DATA_C => SUMMAND(331),
SAVE => INT_SUM(307), CARRY => INT_CARRY(242)
);
---- End FA stage
---- Begin FA stage
FA_244:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(332), DATA_B => SUMMAND(333), DATA_C => SUMMAND(334),
SAVE => INT_SUM(308), CARRY => INT_CARRY(243)
);
---- End FA stage
---- Begin FA stage
FA_245:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(335), DATA_B => SUMMAND(336), DATA_C => SUMMAND(337),
SAVE => INT_SUM(309), CARRY => INT_CARRY(244)
);
---- End FA stage
---- Begin FA stage
FA_246:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(338), DATA_B => SUMMAND(339), DATA_C => SUMMAND(340),
SAVE => INT_SUM(310), CARRY => INT_CARRY(245)
);
---- End FA stage
---- Begin FA stage
FA_247:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(305), DATA_B => INT_SUM(306), DATA_C => INT_SUM(307),
SAVE => INT_SUM(311), CARRY => INT_CARRY(246)
);
---- End FA stage
---- Begin FA stage
FA_248:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(308), DATA_B => INT_SUM(309), DATA_C => INT_SUM(310),
SAVE => INT_SUM(312), CARRY => INT_CARRY(247)
);
---- End FA stage
---- Begin FA stage
FA_249:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(225), DATA_B => INT_CARRY(226), DATA_C => INT_CARRY(227),
SAVE => INT_SUM(313), CARRY => INT_CARRY(248)
);
---- End FA stage
---- Begin NO stage
INT_SUM(314) <= INT_CARRY(228); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(315) <= INT_CARRY(229); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_250:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(311), DATA_B => INT_SUM(312), DATA_C => INT_SUM(313),
SAVE => INT_SUM(316), CARRY => INT_CARRY(249)
);
---- End FA stage
---- Begin FA stage
FA_251:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(314), DATA_B => INT_SUM(315), DATA_C => INT_CARRY(230),
SAVE => INT_SUM(317), CARRY => INT_CARRY(250)
);
---- End FA stage
---- Begin FA stage
FA_252:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(231), DATA_B => INT_CARRY(232), DATA_C => INT_CARRY(233),
SAVE => INT_SUM(318), CARRY => INT_CARRY(251)
);
---- End FA stage
---- Begin FA stage
FA_253:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(316), DATA_B => INT_SUM(317), DATA_C => INT_SUM(318),
SAVE => INT_SUM(319), CARRY => INT_CARRY(252)
);
---- End FA stage
---- Begin FA stage
FA_254:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(234), DATA_B => INT_CARRY(235), DATA_C => INT_CARRY(236),
SAVE => INT_SUM(320), CARRY => INT_CARRY(253)
);
---- End FA stage
---- Begin FA stage
FA_255:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(319), DATA_B => INT_SUM(320), DATA_C => INT_CARRY(237),
SAVE => INT_SUM(321), CARRY => INT_CARRY(254)
);
---- End FA stage
---- Begin NO stage
INT_SUM(322) <= INT_CARRY(238); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_256:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(321), DATA_B => INT_SUM(322), DATA_C => INT_CARRY(239),
SAVE => SUM(34), CARRY => CARRY(34)
);
---- End FA stage
-- End WT-branch 35
-- Begin WT-branch 36
---- Begin FA stage
FA_257:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(341), DATA_B => SUMMAND(342), DATA_C => SUMMAND(343),
SAVE => INT_SUM(323), CARRY => INT_CARRY(255)
);
---- End FA stage
---- Begin FA stage
FA_258:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(344), DATA_B => SUMMAND(345), DATA_C => SUMMAND(346),
SAVE => INT_SUM(324), CARRY => INT_CARRY(256)
);
---- End FA stage
---- Begin FA stage
FA_259:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(347), DATA_B => SUMMAND(348), DATA_C => SUMMAND(349),
SAVE => INT_SUM(325), CARRY => INT_CARRY(257)
);
---- End FA stage
---- Begin FA stage
FA_260:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(350), DATA_B => SUMMAND(351), DATA_C => SUMMAND(352),
SAVE => INT_SUM(326), CARRY => INT_CARRY(258)
);
---- End FA stage
---- Begin FA stage
FA_261:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(353), DATA_B => SUMMAND(354), DATA_C => SUMMAND(355),
SAVE => INT_SUM(327), CARRY => INT_CARRY(259)
);
---- End FA stage
---- Begin HA stage
HA_32:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(356), DATA_B => SUMMAND(357),
SAVE => INT_SUM(328), CARRY => INT_CARRY(260)
);
---- End HA stage
---- Begin FA stage
FA_262:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(323), DATA_B => INT_SUM(324), DATA_C => INT_SUM(325),
SAVE => INT_SUM(329), CARRY => INT_CARRY(261)
);
---- End FA stage
---- Begin FA stage
FA_263:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(326), DATA_B => INT_SUM(327), DATA_C => INT_SUM(328),
SAVE => INT_SUM(330), CARRY => INT_CARRY(262)
);
---- End FA stage
---- Begin FA stage
FA_264:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(240), DATA_B => INT_CARRY(241), DATA_C => INT_CARRY(242),
SAVE => INT_SUM(331), CARRY => INT_CARRY(263)
);
---- End FA stage
---- Begin FA stage
FA_265:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(243), DATA_B => INT_CARRY(244), DATA_C => INT_CARRY(245),
SAVE => INT_SUM(332), CARRY => INT_CARRY(264)
);
---- End FA stage
---- Begin FA stage
FA_266:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(329), DATA_B => INT_SUM(330), DATA_C => INT_SUM(331),
SAVE => INT_SUM(333), CARRY => INT_CARRY(265)
);
---- End FA stage
---- Begin FA stage
FA_267:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(332), DATA_B => INT_CARRY(246), DATA_C => INT_CARRY(247),
SAVE => INT_SUM(334), CARRY => INT_CARRY(266)
);
---- End FA stage
---- Begin NO stage
INT_SUM(335) <= INT_CARRY(248); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_268:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(333), DATA_B => INT_SUM(334), DATA_C => INT_SUM(335),
SAVE => INT_SUM(336), CARRY => INT_CARRY(267)
);
---- End FA stage
---- Begin FA stage
FA_269:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(249), DATA_B => INT_CARRY(250), DATA_C => INT_CARRY(251),
SAVE => INT_SUM(337), CARRY => INT_CARRY(268)
);
---- End FA stage
---- Begin FA stage
FA_270:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(336), DATA_B => INT_SUM(337), DATA_C => INT_CARRY(252),
SAVE => INT_SUM(338), CARRY => INT_CARRY(269)
);
---- End FA stage
---- Begin NO stage
INT_SUM(339) <= INT_CARRY(253); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_271:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(338), DATA_B => INT_SUM(339), DATA_C => INT_CARRY(254),
SAVE => SUM(35), CARRY => CARRY(35)
);
---- End FA stage
-- End WT-branch 36
-- Begin WT-branch 37
---- Begin FA stage
FA_272:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(358), DATA_B => SUMMAND(359), DATA_C => SUMMAND(360),
SAVE => INT_SUM(340), CARRY => INT_CARRY(270)
);
---- End FA stage
---- Begin FA stage
FA_273:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(361), DATA_B => SUMMAND(362), DATA_C => SUMMAND(363),
SAVE => INT_SUM(341), CARRY => INT_CARRY(271)
);
---- End FA stage
---- Begin FA stage
FA_274:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(364), DATA_B => SUMMAND(365), DATA_C => SUMMAND(366),
SAVE => INT_SUM(342), CARRY => INT_CARRY(272)
);
---- End FA stage
---- Begin FA stage
FA_275:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(367), DATA_B => SUMMAND(368), DATA_C => SUMMAND(369),
SAVE => INT_SUM(343), CARRY => INT_CARRY(273)
);
---- End FA stage
---- Begin FA stage
FA_276:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(370), DATA_B => SUMMAND(371), DATA_C => SUMMAND(372),
SAVE => INT_SUM(344), CARRY => INT_CARRY(274)
);
---- End FA stage
---- Begin NO stage
INT_SUM(345) <= SUMMAND(373); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_277:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(340), DATA_B => INT_SUM(341), DATA_C => INT_SUM(342),
SAVE => INT_SUM(346), CARRY => INT_CARRY(275)
);
---- End FA stage
---- Begin FA stage
FA_278:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(343), DATA_B => INT_SUM(344), DATA_C => INT_SUM(345),
SAVE => INT_SUM(347), CARRY => INT_CARRY(276)
);
---- End FA stage
---- Begin FA stage
FA_279:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(255), DATA_B => INT_CARRY(256), DATA_C => INT_CARRY(257),
SAVE => INT_SUM(348), CARRY => INT_CARRY(277)
);
---- End FA stage
---- Begin FA stage
FA_280:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(258), DATA_B => INT_CARRY(259), DATA_C => INT_CARRY(260),
SAVE => INT_SUM(349), CARRY => INT_CARRY(278)
);
---- End FA stage
---- Begin FA stage
FA_281:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(346), DATA_B => INT_SUM(347), DATA_C => INT_SUM(348),
SAVE => INT_SUM(350), CARRY => INT_CARRY(279)
);
---- End FA stage
---- Begin FA stage
FA_282:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(349), DATA_B => INT_CARRY(261), DATA_C => INT_CARRY(262),
SAVE => INT_SUM(351), CARRY => INT_CARRY(280)
);
---- End FA stage
---- Begin NO stage
INT_SUM(352) <= INT_CARRY(263); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(353) <= INT_CARRY(264); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_283:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(350), DATA_B => INT_SUM(351), DATA_C => INT_SUM(352),
SAVE => INT_SUM(354), CARRY => INT_CARRY(281)
);
---- End FA stage
---- Begin FA stage
FA_284:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(353), DATA_B => INT_CARRY(265), DATA_C => INT_CARRY(266),
SAVE => INT_SUM(355), CARRY => INT_CARRY(282)
);
---- End FA stage
---- Begin FA stage
FA_285:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(354), DATA_B => INT_SUM(355), DATA_C => INT_CARRY(267),
SAVE => INT_SUM(356), CARRY => INT_CARRY(283)
);
---- End FA stage
---- Begin NO stage
INT_SUM(357) <= INT_CARRY(268); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_286:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(356), DATA_B => INT_SUM(357), DATA_C => INT_CARRY(269),
SAVE => SUM(36), CARRY => CARRY(36)
);
---- End FA stage
-- End WT-branch 37
-- Begin WT-branch 38
---- Begin FA stage
FA_287:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(374), DATA_B => SUMMAND(375), DATA_C => SUMMAND(376),
SAVE => INT_SUM(358), CARRY => INT_CARRY(284)
);
---- End FA stage
---- Begin FA stage
FA_288:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(377), DATA_B => SUMMAND(378), DATA_C => SUMMAND(379),
SAVE => INT_SUM(359), CARRY => INT_CARRY(285)
);
---- End FA stage
---- Begin FA stage
FA_289:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(380), DATA_B => SUMMAND(381), DATA_C => SUMMAND(382),
SAVE => INT_SUM(360), CARRY => INT_CARRY(286)
);
---- End FA stage
---- Begin FA stage
FA_290:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(383), DATA_B => SUMMAND(384), DATA_C => SUMMAND(385),
SAVE => INT_SUM(361), CARRY => INT_CARRY(287)
);
---- End FA stage
---- Begin FA stage
FA_291:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(386), DATA_B => SUMMAND(387), DATA_C => SUMMAND(388),
SAVE => INT_SUM(362), CARRY => INT_CARRY(288)
);
---- End FA stage
---- Begin NO stage
INT_SUM(363) <= SUMMAND(389); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_292:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(358), DATA_B => INT_SUM(359), DATA_C => INT_SUM(360),
SAVE => INT_SUM(364), CARRY => INT_CARRY(289)
);
---- End FA stage
---- Begin FA stage
FA_293:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(361), DATA_B => INT_SUM(362), DATA_C => INT_SUM(363),
SAVE => INT_SUM(365), CARRY => INT_CARRY(290)
);
---- End FA stage
---- Begin FA stage
FA_294:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(270), DATA_B => INT_CARRY(271), DATA_C => INT_CARRY(272),
SAVE => INT_SUM(366), CARRY => INT_CARRY(291)
);
---- End FA stage
---- Begin NO stage
INT_SUM(367) <= INT_CARRY(273); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(368) <= INT_CARRY(274); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_295:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(364), DATA_B => INT_SUM(365), DATA_C => INT_SUM(366),
SAVE => INT_SUM(369), CARRY => INT_CARRY(292)
);
---- End FA stage
---- Begin FA stage
FA_296:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(367), DATA_B => INT_SUM(368), DATA_C => INT_CARRY(275),
SAVE => INT_SUM(370), CARRY => INT_CARRY(293)
);
---- End FA stage
---- Begin FA stage
FA_297:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(276), DATA_B => INT_CARRY(277), DATA_C => INT_CARRY(278),
SAVE => INT_SUM(371), CARRY => INT_CARRY(294)
);
---- End FA stage
---- Begin FA stage
FA_298:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(369), DATA_B => INT_SUM(370), DATA_C => INT_SUM(371),
SAVE => INT_SUM(372), CARRY => INT_CARRY(295)
);
---- End FA stage
---- Begin HA stage
HA_33:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(279), DATA_B => INT_CARRY(280),
SAVE => INT_SUM(373), CARRY => INT_CARRY(296)
);
---- End HA stage
---- Begin FA stage
FA_299:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(372), DATA_B => INT_SUM(373), DATA_C => INT_CARRY(281),
SAVE => INT_SUM(374), CARRY => INT_CARRY(297)
);
---- End FA stage
---- Begin NO stage
INT_SUM(375) <= INT_CARRY(282); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_300:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(374), DATA_B => INT_SUM(375), DATA_C => INT_CARRY(283),
SAVE => SUM(37), CARRY => CARRY(37)
);
---- End FA stage
-- End WT-branch 38
-- Begin WT-branch 39
---- Begin FA stage
FA_301:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(390), DATA_B => SUMMAND(391), DATA_C => SUMMAND(392),
SAVE => INT_SUM(376), CARRY => INT_CARRY(298)
);
---- End FA stage
---- Begin FA stage
FA_302:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(393), DATA_B => SUMMAND(394), DATA_C => SUMMAND(395),
SAVE => INT_SUM(377), CARRY => INT_CARRY(299)
);
---- End FA stage
---- Begin FA stage
FA_303:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(396), DATA_B => SUMMAND(397), DATA_C => SUMMAND(398),
SAVE => INT_SUM(378), CARRY => INT_CARRY(300)
);
---- End FA stage
---- Begin FA stage
FA_304:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(399), DATA_B => SUMMAND(400), DATA_C => SUMMAND(401),
SAVE => INT_SUM(379), CARRY => INT_CARRY(301)
);
---- End FA stage
---- Begin FA stage
FA_305:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(402), DATA_B => SUMMAND(403), DATA_C => SUMMAND(404),
SAVE => INT_SUM(380), CARRY => INT_CARRY(302)
);
---- End FA stage
---- Begin FA stage
FA_306:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(376), DATA_B => INT_SUM(377), DATA_C => INT_SUM(378),
SAVE => INT_SUM(381), CARRY => INT_CARRY(303)
);
---- End FA stage
---- Begin FA stage
FA_307:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(379), DATA_B => INT_SUM(380), DATA_C => INT_CARRY(284),
SAVE => INT_SUM(382), CARRY => INT_CARRY(304)
);
---- End FA stage
---- Begin FA stage
FA_308:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(285), DATA_B => INT_CARRY(286), DATA_C => INT_CARRY(287),
SAVE => INT_SUM(383), CARRY => INT_CARRY(305)
);
---- End FA stage
---- Begin NO stage
INT_SUM(384) <= INT_CARRY(288); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_309:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(381), DATA_B => INT_SUM(382), DATA_C => INT_SUM(383),
SAVE => INT_SUM(385), CARRY => INT_CARRY(306)
);
---- End FA stage
---- Begin FA stage
FA_310:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(384), DATA_B => INT_CARRY(289), DATA_C => INT_CARRY(290),
SAVE => INT_SUM(386), CARRY => INT_CARRY(307)
);
---- End FA stage
---- Begin NO stage
INT_SUM(387) <= INT_CARRY(291); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_311:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(385), DATA_B => INT_SUM(386), DATA_C => INT_SUM(387),
SAVE => INT_SUM(388), CARRY => INT_CARRY(308)
);
---- End FA stage
---- Begin FA stage
FA_312:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(292), DATA_B => INT_CARRY(293), DATA_C => INT_CARRY(294),
SAVE => INT_SUM(389), CARRY => INT_CARRY(309)
);
---- End FA stage
---- Begin FA stage
FA_313:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(388), DATA_B => INT_SUM(389), DATA_C => INT_CARRY(295),
SAVE => INT_SUM(390), CARRY => INT_CARRY(310)
);
---- End FA stage
---- Begin NO stage
INT_SUM(391) <= INT_CARRY(296); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_314:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(390), DATA_B => INT_SUM(391), DATA_C => INT_CARRY(297),
SAVE => SUM(38), CARRY => CARRY(38)
);
---- End FA stage
-- End WT-branch 39
-- Begin WT-branch 40
---- Begin FA stage
FA_315:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(405), DATA_B => SUMMAND(406), DATA_C => SUMMAND(407),
SAVE => INT_SUM(392), CARRY => INT_CARRY(311)
);
---- End FA stage
---- Begin FA stage
FA_316:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(408), DATA_B => SUMMAND(409), DATA_C => SUMMAND(410),
SAVE => INT_SUM(393), CARRY => INT_CARRY(312)
);
---- End FA stage
---- Begin FA stage
FA_317:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(411), DATA_B => SUMMAND(412), DATA_C => SUMMAND(413),
SAVE => INT_SUM(394), CARRY => INT_CARRY(313)
);
---- End FA stage
---- Begin FA stage
FA_318:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(414), DATA_B => SUMMAND(415), DATA_C => SUMMAND(416),
SAVE => INT_SUM(395), CARRY => INT_CARRY(314)
);
---- End FA stage
---- Begin FA stage
FA_319:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(417), DATA_B => SUMMAND(418), DATA_C => SUMMAND(419),
SAVE => INT_SUM(396), CARRY => INT_CARRY(315)
);
---- End FA stage
---- Begin FA stage
FA_320:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(392), DATA_B => INT_SUM(393), DATA_C => INT_SUM(394),
SAVE => INT_SUM(397), CARRY => INT_CARRY(316)
);
---- End FA stage
---- Begin FA stage
FA_321:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(395), DATA_B => INT_SUM(396), DATA_C => INT_CARRY(298),
SAVE => INT_SUM(398), CARRY => INT_CARRY(317)
);
---- End FA stage
---- Begin FA stage
FA_322:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(299), DATA_B => INT_CARRY(300), DATA_C => INT_CARRY(301),
SAVE => INT_SUM(399), CARRY => INT_CARRY(318)
);
---- End FA stage
---- Begin NO stage
INT_SUM(400) <= INT_CARRY(302); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_323:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(397), DATA_B => INT_SUM(398), DATA_C => INT_SUM(399),
SAVE => INT_SUM(401), CARRY => INT_CARRY(319)
);
---- End FA stage
---- Begin FA stage
FA_324:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(400), DATA_B => INT_CARRY(303), DATA_C => INT_CARRY(304),
SAVE => INT_SUM(402), CARRY => INT_CARRY(320)
);
---- End FA stage
---- Begin NO stage
INT_SUM(403) <= INT_CARRY(305); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_325:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(401), DATA_B => INT_SUM(402), DATA_C => INT_SUM(403),
SAVE => INT_SUM(404), CARRY => INT_CARRY(321)
);
---- End FA stage
---- Begin HA stage
HA_34:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(306), DATA_B => INT_CARRY(307),
SAVE => INT_SUM(405), CARRY => INT_CARRY(322)
);
---- End HA stage
---- Begin FA stage
FA_326:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(404), DATA_B => INT_SUM(405), DATA_C => INT_CARRY(308),
SAVE => INT_SUM(406), CARRY => INT_CARRY(323)
);
---- End FA stage
---- Begin NO stage
INT_SUM(407) <= INT_CARRY(309); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_327:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(406), DATA_B => INT_SUM(407), DATA_C => INT_CARRY(310),
SAVE => SUM(39), CARRY => CARRY(39)
);
---- End FA stage
-- End WT-branch 40
-- Begin WT-branch 41
---- Begin FA stage
FA_328:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(420), DATA_B => SUMMAND(421), DATA_C => SUMMAND(422),
SAVE => INT_SUM(408), CARRY => INT_CARRY(324)
);
---- End FA stage
---- Begin FA stage
FA_329:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(423), DATA_B => SUMMAND(424), DATA_C => SUMMAND(425),
SAVE => INT_SUM(409), CARRY => INT_CARRY(325)
);
---- End FA stage
---- Begin FA stage
FA_330:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(426), DATA_B => SUMMAND(427), DATA_C => SUMMAND(428),
SAVE => INT_SUM(410), CARRY => INT_CARRY(326)
);
---- End FA stage
---- Begin FA stage
FA_331:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(429), DATA_B => SUMMAND(430), DATA_C => SUMMAND(431),
SAVE => INT_SUM(411), CARRY => INT_CARRY(327)
);
---- End FA stage
---- Begin HA stage
HA_35:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(432), DATA_B => SUMMAND(433),
SAVE => INT_SUM(412), CARRY => INT_CARRY(328)
);
---- End HA stage
---- Begin FA stage
FA_332:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(408), DATA_B => INT_SUM(409), DATA_C => INT_SUM(410),
SAVE => INT_SUM(413), CARRY => INT_CARRY(329)
);
---- End FA stage
---- Begin FA stage
FA_333:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(411), DATA_B => INT_SUM(412), DATA_C => INT_CARRY(311),
SAVE => INT_SUM(414), CARRY => INT_CARRY(330)
);
---- End FA stage
---- Begin FA stage
FA_334:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(312), DATA_B => INT_CARRY(313), DATA_C => INT_CARRY(314),
SAVE => INT_SUM(415), CARRY => INT_CARRY(331)
);
---- End FA stage
---- Begin NO stage
INT_SUM(416) <= INT_CARRY(315); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_335:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(413), DATA_B => INT_SUM(414), DATA_C => INT_SUM(415),
SAVE => INT_SUM(417), CARRY => INT_CARRY(332)
);
---- End FA stage
---- Begin FA stage
FA_336:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(416), DATA_B => INT_CARRY(316), DATA_C => INT_CARRY(317),
SAVE => INT_SUM(418), CARRY => INT_CARRY(333)
);
---- End FA stage
---- Begin NO stage
INT_SUM(419) <= INT_CARRY(318); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_337:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(417), DATA_B => INT_SUM(418), DATA_C => INT_SUM(419),
SAVE => INT_SUM(420), CARRY => INT_CARRY(334)
);
---- End FA stage
---- Begin HA stage
HA_36:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(319), DATA_B => INT_CARRY(320),
SAVE => INT_SUM(421), CARRY => INT_CARRY(335)
);
---- End HA stage
---- Begin FA stage
FA_338:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(420), DATA_B => INT_SUM(421), DATA_C => INT_CARRY(321),
SAVE => INT_SUM(422), CARRY => INT_CARRY(336)
);
---- End FA stage
---- Begin NO stage
INT_SUM(423) <= INT_CARRY(322); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_339:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(422), DATA_B => INT_SUM(423), DATA_C => INT_CARRY(323),
SAVE => SUM(40), CARRY => CARRY(40)
);
---- End FA stage
-- End WT-branch 41
-- Begin WT-branch 42
---- Begin FA stage
FA_340:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(434), DATA_B => SUMMAND(435), DATA_C => SUMMAND(436),
SAVE => INT_SUM(424), CARRY => INT_CARRY(337)
);
---- End FA stage
---- Begin FA stage
FA_341:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(437), DATA_B => SUMMAND(438), DATA_C => SUMMAND(439),
SAVE => INT_SUM(425), CARRY => INT_CARRY(338)
);
---- End FA stage
---- Begin FA stage
FA_342:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(440), DATA_B => SUMMAND(441), DATA_C => SUMMAND(442),
SAVE => INT_SUM(426), CARRY => INT_CARRY(339)
);
---- End FA stage
---- Begin FA stage
FA_343:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(443), DATA_B => SUMMAND(444), DATA_C => SUMMAND(445),
SAVE => INT_SUM(427), CARRY => INT_CARRY(340)
);
---- End FA stage
---- Begin HA stage
HA_37:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(446), DATA_B => SUMMAND(447),
SAVE => INT_SUM(428), CARRY => INT_CARRY(341)
);
---- End HA stage
---- Begin FA stage
FA_344:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(424), DATA_B => INT_SUM(425), DATA_C => INT_SUM(426),
SAVE => INT_SUM(429), CARRY => INT_CARRY(342)
);
---- End FA stage
---- Begin FA stage
FA_345:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(427), DATA_B => INT_SUM(428), DATA_C => INT_CARRY(324),
SAVE => INT_SUM(430), CARRY => INT_CARRY(343)
);
---- End FA stage
---- Begin FA stage
FA_346:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(325), DATA_B => INT_CARRY(326), DATA_C => INT_CARRY(327),
SAVE => INT_SUM(431), CARRY => INT_CARRY(344)
);
---- End FA stage
---- Begin NO stage
INT_SUM(432) <= INT_CARRY(328); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_347:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(429), DATA_B => INT_SUM(430), DATA_C => INT_SUM(431),
SAVE => INT_SUM(433), CARRY => INT_CARRY(345)
);
---- End FA stage
---- Begin FA stage
FA_348:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(432), DATA_B => INT_CARRY(329), DATA_C => INT_CARRY(330),
SAVE => INT_SUM(434), CARRY => INT_CARRY(346)
);
---- End FA stage
---- Begin NO stage
INT_SUM(435) <= INT_CARRY(331); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_349:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(433), DATA_B => INT_SUM(434), DATA_C => INT_SUM(435),
SAVE => INT_SUM(436), CARRY => INT_CARRY(347)
);
---- End FA stage
---- Begin HA stage
HA_38:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(332), DATA_B => INT_CARRY(333),
SAVE => INT_SUM(437), CARRY => INT_CARRY(348)
);
---- End HA stage
---- Begin FA stage
FA_350:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(436), DATA_B => INT_SUM(437), DATA_C => INT_CARRY(334),
SAVE => INT_SUM(438), CARRY => INT_CARRY(349)
);
---- End FA stage
---- Begin NO stage
INT_SUM(439) <= INT_CARRY(335); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_351:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(438), DATA_B => INT_SUM(439), DATA_C => INT_CARRY(336),
SAVE => SUM(41), CARRY => CARRY(41)
);
---- End FA stage
-- End WT-branch 42
-- Begin WT-branch 43
---- Begin FA stage
FA_352:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(448), DATA_B => SUMMAND(449), DATA_C => SUMMAND(450),
SAVE => INT_SUM(440), CARRY => INT_CARRY(350)
);
---- End FA stage
---- Begin FA stage
FA_353:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(451), DATA_B => SUMMAND(452), DATA_C => SUMMAND(453),
SAVE => INT_SUM(441), CARRY => INT_CARRY(351)
);
---- End FA stage
---- Begin FA stage
FA_354:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(454), DATA_B => SUMMAND(455), DATA_C => SUMMAND(456),
SAVE => INT_SUM(442), CARRY => INT_CARRY(352)
);
---- End FA stage
---- Begin FA stage
FA_355:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(457), DATA_B => SUMMAND(458), DATA_C => SUMMAND(459),
SAVE => INT_SUM(443), CARRY => INT_CARRY(353)
);
---- End FA stage
---- Begin NO stage
INT_SUM(444) <= SUMMAND(460); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_356:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(440), DATA_B => INT_SUM(441), DATA_C => INT_SUM(442),
SAVE => INT_SUM(445), CARRY => INT_CARRY(354)
);
---- End FA stage
---- Begin FA stage
FA_357:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(443), DATA_B => INT_SUM(444), DATA_C => INT_CARRY(337),
SAVE => INT_SUM(446), CARRY => INT_CARRY(355)
);
---- End FA stage
---- Begin FA stage
FA_358:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(338), DATA_B => INT_CARRY(339), DATA_C => INT_CARRY(340),
SAVE => INT_SUM(447), CARRY => INT_CARRY(356)
);
---- End FA stage
---- Begin NO stage
INT_SUM(448) <= INT_CARRY(341); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_359:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(445), DATA_B => INT_SUM(446), DATA_C => INT_SUM(447),
SAVE => INT_SUM(449), CARRY => INT_CARRY(357)
);
---- End FA stage
---- Begin FA stage
FA_360:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(448), DATA_B => INT_CARRY(342), DATA_C => INT_CARRY(343),
SAVE => INT_SUM(450), CARRY => INT_CARRY(358)
);
---- End FA stage
---- Begin NO stage
INT_SUM(451) <= INT_CARRY(344); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_361:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(449), DATA_B => INT_SUM(450), DATA_C => INT_SUM(451),
SAVE => INT_SUM(452), CARRY => INT_CARRY(359)
);
---- End FA stage
---- Begin HA stage
HA_39:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(345), DATA_B => INT_CARRY(346),
SAVE => INT_SUM(453), CARRY => INT_CARRY(360)
);
---- End HA stage
---- Begin FA stage
FA_362:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(452), DATA_B => INT_SUM(453), DATA_C => INT_CARRY(347),
SAVE => INT_SUM(454), CARRY => INT_CARRY(361)
);
---- End FA stage
---- Begin NO stage
INT_SUM(455) <= INT_CARRY(348); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_363:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(454), DATA_B => INT_SUM(455), DATA_C => INT_CARRY(349),
SAVE => SUM(42), CARRY => CARRY(42)
);
---- End FA stage
-- End WT-branch 43
-- Begin WT-branch 44
---- Begin FA stage
FA_364:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(461), DATA_B => SUMMAND(462), DATA_C => SUMMAND(463),
SAVE => INT_SUM(456), CARRY => INT_CARRY(362)
);
---- End FA stage
---- Begin FA stage
FA_365:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(464), DATA_B => SUMMAND(465), DATA_C => SUMMAND(466),
SAVE => INT_SUM(457), CARRY => INT_CARRY(363)
);
---- End FA stage
---- Begin FA stage
FA_366:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(467), DATA_B => SUMMAND(468), DATA_C => SUMMAND(469),
SAVE => INT_SUM(458), CARRY => INT_CARRY(364)
);
---- End FA stage
---- Begin FA stage
FA_367:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(470), DATA_B => SUMMAND(471), DATA_C => SUMMAND(472),
SAVE => INT_SUM(459), CARRY => INT_CARRY(365)
);
---- End FA stage
---- Begin FA stage
FA_368:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(473), DATA_B => INT_CARRY(350), DATA_C => INT_CARRY(351),
SAVE => INT_SUM(460), CARRY => INT_CARRY(366)
);
---- End FA stage
---- Begin NO stage
INT_SUM(461) <= INT_CARRY(352); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(462) <= INT_CARRY(353); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_369:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(456), DATA_B => INT_SUM(457), DATA_C => INT_SUM(458),
SAVE => INT_SUM(463), CARRY => INT_CARRY(367)
);
---- End FA stage
---- Begin FA stage
FA_370:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(459), DATA_B => INT_SUM(460), DATA_C => INT_SUM(461),
SAVE => INT_SUM(464), CARRY => INT_CARRY(368)
);
---- End FA stage
---- Begin FA stage
FA_371:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(462), DATA_B => INT_CARRY(354), DATA_C => INT_CARRY(355),
SAVE => INT_SUM(465), CARRY => INT_CARRY(369)
);
---- End FA stage
---- Begin NO stage
INT_SUM(466) <= INT_CARRY(356); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_372:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(463), DATA_B => INT_SUM(464), DATA_C => INT_SUM(465),
SAVE => INT_SUM(467), CARRY => INT_CARRY(370)
);
---- End FA stage
---- Begin FA stage
FA_373:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(466), DATA_B => INT_CARRY(357), DATA_C => INT_CARRY(358),
SAVE => INT_SUM(468), CARRY => INT_CARRY(371)
);
---- End FA stage
---- Begin FA stage
FA_374:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(467), DATA_B => INT_SUM(468), DATA_C => INT_CARRY(359),
SAVE => INT_SUM(469), CARRY => INT_CARRY(372)
);
---- End FA stage
---- Begin NO stage
INT_SUM(470) <= INT_CARRY(360); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_375:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(469), DATA_B => INT_SUM(470), DATA_C => INT_CARRY(361),
SAVE => SUM(43), CARRY => CARRY(43)
);
---- End FA stage
-- End WT-branch 44
-- Begin WT-branch 45
---- Begin FA stage
FA_376:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(474), DATA_B => SUMMAND(475), DATA_C => SUMMAND(476),
SAVE => INT_SUM(471), CARRY => INT_CARRY(373)
);
---- End FA stage
---- Begin FA stage
FA_377:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(477), DATA_B => SUMMAND(478), DATA_C => SUMMAND(479),
SAVE => INT_SUM(472), CARRY => INT_CARRY(374)
);
---- End FA stage
---- Begin FA stage
FA_378:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(480), DATA_B => SUMMAND(481), DATA_C => SUMMAND(482),
SAVE => INT_SUM(473), CARRY => INT_CARRY(375)
);
---- End FA stage
---- Begin FA stage
FA_379:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(483), DATA_B => SUMMAND(484), DATA_C => SUMMAND(485),
SAVE => INT_SUM(474), CARRY => INT_CARRY(376)
);
---- End FA stage
---- Begin FA stage
FA_380:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(471), DATA_B => INT_SUM(472), DATA_C => INT_SUM(473),
SAVE => INT_SUM(475), CARRY => INT_CARRY(377)
);
---- End FA stage
---- Begin FA stage
FA_381:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(474), DATA_B => INT_CARRY(362), DATA_C => INT_CARRY(363),
SAVE => INT_SUM(476), CARRY => INT_CARRY(378)
);
---- End FA stage
---- Begin FA stage
FA_382:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(364), DATA_B => INT_CARRY(365), DATA_C => INT_CARRY(366),
SAVE => INT_SUM(477), CARRY => INT_CARRY(379)
);
---- End FA stage
---- Begin FA stage
FA_383:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(475), DATA_B => INT_SUM(476), DATA_C => INT_SUM(477),
SAVE => INT_SUM(478), CARRY => INT_CARRY(380)
);
---- End FA stage
---- Begin FA stage
FA_384:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(367), DATA_B => INT_CARRY(368), DATA_C => INT_CARRY(369),
SAVE => INT_SUM(479), CARRY => INT_CARRY(381)
);
---- End FA stage
---- Begin FA stage
FA_385:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(478), DATA_B => INT_SUM(479), DATA_C => INT_CARRY(370),
SAVE => INT_SUM(480), CARRY => INT_CARRY(382)
);
---- End FA stage
---- Begin NO stage
INT_SUM(481) <= INT_CARRY(371); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_386:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(480), DATA_B => INT_SUM(481), DATA_C => INT_CARRY(372),
SAVE => SUM(44), CARRY => CARRY(44)
);
---- End FA stage
-- End WT-branch 45
-- Begin WT-branch 46
---- Begin FA stage
FA_387:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(486), DATA_B => SUMMAND(487), DATA_C => SUMMAND(488),
SAVE => INT_SUM(482), CARRY => INT_CARRY(383)
);
---- End FA stage
---- Begin FA stage
FA_388:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(489), DATA_B => SUMMAND(490), DATA_C => SUMMAND(491),
SAVE => INT_SUM(483), CARRY => INT_CARRY(384)
);
---- End FA stage
---- Begin FA stage
FA_389:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(492), DATA_B => SUMMAND(493), DATA_C => SUMMAND(494),
SAVE => INT_SUM(484), CARRY => INT_CARRY(385)
);
---- End FA stage
---- Begin FA stage
FA_390:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(495), DATA_B => SUMMAND(496), DATA_C => SUMMAND(497),
SAVE => INT_SUM(485), CARRY => INT_CARRY(386)
);
---- End FA stage
---- Begin FA stage
FA_391:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(482), DATA_B => INT_SUM(483), DATA_C => INT_SUM(484),
SAVE => INT_SUM(486), CARRY => INT_CARRY(387)
);
---- End FA stage
---- Begin FA stage
FA_392:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(485), DATA_B => INT_CARRY(373), DATA_C => INT_CARRY(374),
SAVE => INT_SUM(487), CARRY => INT_CARRY(388)
);
---- End FA stage
---- Begin HA stage
HA_40:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(375), DATA_B => INT_CARRY(376),
SAVE => INT_SUM(488), CARRY => INT_CARRY(389)
);
---- End HA stage
---- Begin FA stage
FA_393:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(486), DATA_B => INT_SUM(487), DATA_C => INT_SUM(488),
SAVE => INT_SUM(489), CARRY => INT_CARRY(390)
);
---- End FA stage
---- Begin FA stage
FA_394:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(377), DATA_B => INT_CARRY(378), DATA_C => INT_CARRY(379),
SAVE => INT_SUM(490), CARRY => INT_CARRY(391)
);
---- End FA stage
---- Begin FA stage
FA_395:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(489), DATA_B => INT_SUM(490), DATA_C => INT_CARRY(380),
SAVE => INT_SUM(491), CARRY => INT_CARRY(392)
);
---- End FA stage
---- Begin NO stage
INT_SUM(492) <= INT_CARRY(381); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_396:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(491), DATA_B => INT_SUM(492), DATA_C => INT_CARRY(382),
SAVE => SUM(45), CARRY => CARRY(45)
);
---- End FA stage
-- End WT-branch 46
-- Begin WT-branch 47
---- Begin FA stage
FA_397:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(498), DATA_B => SUMMAND(499), DATA_C => SUMMAND(500),
SAVE => INT_SUM(493), CARRY => INT_CARRY(393)
);
---- End FA stage
---- Begin FA stage
FA_398:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(501), DATA_B => SUMMAND(502), DATA_C => SUMMAND(503),
SAVE => INT_SUM(494), CARRY => INT_CARRY(394)
);
---- End FA stage
---- Begin FA stage
FA_399:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(504), DATA_B => SUMMAND(505), DATA_C => SUMMAND(506),
SAVE => INT_SUM(495), CARRY => INT_CARRY(395)
);
---- End FA stage
---- Begin NO stage
INT_SUM(496) <= SUMMAND(507); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(497) <= SUMMAND(508); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_400:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(493), DATA_B => INT_SUM(494), DATA_C => INT_SUM(495),
SAVE => INT_SUM(498), CARRY => INT_CARRY(396)
);
---- End FA stage
---- Begin FA stage
FA_401:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(496), DATA_B => INT_SUM(497), DATA_C => INT_CARRY(383),
SAVE => INT_SUM(499), CARRY => INT_CARRY(397)
);
---- End FA stage
---- Begin FA stage
FA_402:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(384), DATA_B => INT_CARRY(385), DATA_C => INT_CARRY(386),
SAVE => INT_SUM(500), CARRY => INT_CARRY(398)
);
---- End FA stage
---- Begin FA stage
FA_403:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(498), DATA_B => INT_SUM(499), DATA_C => INT_SUM(500),
SAVE => INT_SUM(501), CARRY => INT_CARRY(399)
);
---- End FA stage
---- Begin FA stage
FA_404:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(387), DATA_B => INT_CARRY(388), DATA_C => INT_CARRY(389),
SAVE => INT_SUM(502), CARRY => INT_CARRY(400)
);
---- End FA stage
---- Begin FA stage
FA_405:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(501), DATA_B => INT_SUM(502), DATA_C => INT_CARRY(390),
SAVE => INT_SUM(503), CARRY => INT_CARRY(401)
);
---- End FA stage
---- Begin NO stage
INT_SUM(504) <= INT_CARRY(391); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_406:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(503), DATA_B => INT_SUM(504), DATA_C => INT_CARRY(392),
SAVE => SUM(46), CARRY => CARRY(46)
);
---- End FA stage
-- End WT-branch 47
-- Begin WT-branch 48
---- Begin FA stage
FA_407:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(509), DATA_B => SUMMAND(510), DATA_C => SUMMAND(511),
SAVE => INT_SUM(505), CARRY => INT_CARRY(402)
);
---- End FA stage
---- Begin FA stage
FA_408:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(512), DATA_B => SUMMAND(513), DATA_C => SUMMAND(514),
SAVE => INT_SUM(506), CARRY => INT_CARRY(403)
);
---- End FA stage
---- Begin FA stage
FA_409:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(515), DATA_B => SUMMAND(516), DATA_C => SUMMAND(517),
SAVE => INT_SUM(507), CARRY => INT_CARRY(404)
);
---- End FA stage
---- Begin HA stage
HA_41:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(518), DATA_B => SUMMAND(519),
SAVE => INT_SUM(508), CARRY => INT_CARRY(405)
);
---- End HA stage
---- Begin FA stage
FA_410:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(505), DATA_B => INT_SUM(506), DATA_C => INT_SUM(507),
SAVE => INT_SUM(509), CARRY => INT_CARRY(406)
);
---- End FA stage
---- Begin FA stage
FA_411:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(508), DATA_B => INT_CARRY(393), DATA_C => INT_CARRY(394),
SAVE => INT_SUM(510), CARRY => INT_CARRY(407)
);
---- End FA stage
---- Begin NO stage
INT_SUM(511) <= INT_CARRY(395); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_412:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(509), DATA_B => INT_SUM(510), DATA_C => INT_SUM(511),
SAVE => INT_SUM(512), CARRY => INT_CARRY(408)
);
---- End FA stage
---- Begin FA stage
FA_413:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(396), DATA_B => INT_CARRY(397), DATA_C => INT_CARRY(398),
SAVE => INT_SUM(513), CARRY => INT_CARRY(409)
);
---- End FA stage
---- Begin FA stage
FA_414:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(512), DATA_B => INT_SUM(513), DATA_C => INT_CARRY(399),
SAVE => INT_SUM(514), CARRY => INT_CARRY(410)
);
---- End FA stage
---- Begin NO stage
INT_SUM(515) <= INT_CARRY(400); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_415:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(514), DATA_B => INT_SUM(515), DATA_C => INT_CARRY(401),
SAVE => SUM(47), CARRY => CARRY(47)
);
---- End FA stage
-- End WT-branch 48
-- Begin WT-branch 49
---- Begin FA stage
FA_416:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(520), DATA_B => SUMMAND(521), DATA_C => SUMMAND(522),
SAVE => INT_SUM(516), CARRY => INT_CARRY(411)
);
---- End FA stage
---- Begin FA stage
FA_417:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(523), DATA_B => SUMMAND(524), DATA_C => SUMMAND(525),
SAVE => INT_SUM(517), CARRY => INT_CARRY(412)
);
---- End FA stage
---- Begin FA stage
FA_418:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(526), DATA_B => SUMMAND(527), DATA_C => SUMMAND(528),
SAVE => INT_SUM(518), CARRY => INT_CARRY(413)
);
---- End FA stage
---- Begin NO stage
INT_SUM(519) <= SUMMAND(529); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_419:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(516), DATA_B => INT_SUM(517), DATA_C => INT_SUM(518),
SAVE => INT_SUM(520), CARRY => INT_CARRY(414)
);
---- End FA stage
---- Begin FA stage
FA_420:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(519), DATA_B => INT_CARRY(402), DATA_C => INT_CARRY(403),
SAVE => INT_SUM(521), CARRY => INT_CARRY(415)
);
---- End FA stage
---- Begin NO stage
INT_SUM(522) <= INT_CARRY(404); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(523) <= INT_CARRY(405); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_421:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(520), DATA_B => INT_SUM(521), DATA_C => INT_SUM(522),
SAVE => INT_SUM(524), CARRY => INT_CARRY(416)
);
---- End FA stage
---- Begin FA stage
FA_422:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(523), DATA_B => INT_CARRY(406), DATA_C => INT_CARRY(407),
SAVE => INT_SUM(525), CARRY => INT_CARRY(417)
);
---- End FA stage
---- Begin FA stage
FA_423:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(524), DATA_B => INT_SUM(525), DATA_C => INT_CARRY(408),
SAVE => INT_SUM(526), CARRY => INT_CARRY(418)
);
---- End FA stage
---- Begin NO stage
INT_SUM(527) <= INT_CARRY(409); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_424:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(526), DATA_B => INT_SUM(527), DATA_C => INT_CARRY(410),
SAVE => SUM(48), CARRY => CARRY(48)
);
---- End FA stage
-- End WT-branch 49
-- Begin WT-branch 50
---- Begin FA stage
FA_425:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(530), DATA_B => SUMMAND(531), DATA_C => SUMMAND(532),
SAVE => INT_SUM(528), CARRY => INT_CARRY(419)
);
---- End FA stage
---- Begin FA stage
FA_426:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(533), DATA_B => SUMMAND(534), DATA_C => SUMMAND(535),
SAVE => INT_SUM(529), CARRY => INT_CARRY(420)
);
---- End FA stage
---- Begin FA stage
FA_427:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(536), DATA_B => SUMMAND(537), DATA_C => SUMMAND(538),
SAVE => INT_SUM(530), CARRY => INT_CARRY(421)
);
---- End FA stage
---- Begin NO stage
INT_SUM(531) <= SUMMAND(539); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_428:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(528), DATA_B => INT_SUM(529), DATA_C => INT_SUM(530),
SAVE => INT_SUM(532), CARRY => INT_CARRY(422)
);
---- End FA stage
---- Begin FA stage
FA_429:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(531), DATA_B => INT_CARRY(411), DATA_C => INT_CARRY(412),
SAVE => INT_SUM(533), CARRY => INT_CARRY(423)
);
---- End FA stage
---- Begin NO stage
INT_SUM(534) <= INT_CARRY(413); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_430:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(532), DATA_B => INT_SUM(533), DATA_C => INT_SUM(534),
SAVE => INT_SUM(535), CARRY => INT_CARRY(424)
);
---- End FA stage
---- Begin HA stage
HA_42:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(414), DATA_B => INT_CARRY(415),
SAVE => INT_SUM(536), CARRY => INT_CARRY(425)
);
---- End HA stage
---- Begin FA stage
FA_431:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(535), DATA_B => INT_SUM(536), DATA_C => INT_CARRY(416),
SAVE => INT_SUM(537), CARRY => INT_CARRY(426)
);
---- End FA stage
---- Begin NO stage
INT_SUM(538) <= INT_CARRY(417); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_432:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(537), DATA_B => INT_SUM(538), DATA_C => INT_CARRY(418),
SAVE => SUM(49), CARRY => CARRY(49)
);
---- End FA stage
-- End WT-branch 50
-- Begin WT-branch 51
---- Begin FA stage
FA_433:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(540), DATA_B => SUMMAND(541), DATA_C => SUMMAND(542),
SAVE => INT_SUM(539), CARRY => INT_CARRY(427)
);
---- End FA stage
---- Begin FA stage
FA_434:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(543), DATA_B => SUMMAND(544), DATA_C => SUMMAND(545),
SAVE => INT_SUM(540), CARRY => INT_CARRY(428)
);
---- End FA stage
---- Begin FA stage
FA_435:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(546), DATA_B => SUMMAND(547), DATA_C => SUMMAND(548),
SAVE => INT_SUM(541), CARRY => INT_CARRY(429)
);
---- End FA stage
---- Begin FA stage
FA_436:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(539), DATA_B => INT_SUM(540), DATA_C => INT_SUM(541),
SAVE => INT_SUM(542), CARRY => INT_CARRY(430)
);
---- End FA stage
---- Begin FA stage
FA_437:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(419), DATA_B => INT_CARRY(420), DATA_C => INT_CARRY(421),
SAVE => INT_SUM(543), CARRY => INT_CARRY(431)
);
---- End FA stage
---- Begin FA stage
FA_438:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(542), DATA_B => INT_SUM(543), DATA_C => INT_CARRY(422),
SAVE => INT_SUM(544), CARRY => INT_CARRY(432)
);
---- End FA stage
---- Begin NO stage
INT_SUM(545) <= INT_CARRY(423); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_439:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(544), DATA_B => INT_SUM(545), DATA_C => INT_CARRY(424),
SAVE => INT_SUM(546), CARRY => INT_CARRY(433)
);
---- End FA stage
---- Begin NO stage
INT_SUM(547) <= INT_CARRY(425); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_440:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(546), DATA_B => INT_SUM(547), DATA_C => INT_CARRY(426),
SAVE => SUM(50), CARRY => CARRY(50)
);
---- End FA stage
-- End WT-branch 51
-- Begin WT-branch 52
---- Begin FA stage
FA_441:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(549), DATA_B => SUMMAND(550), DATA_C => SUMMAND(551),
SAVE => INT_SUM(548), CARRY => INT_CARRY(434)
);
---- End FA stage
---- Begin FA stage
FA_442:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(552), DATA_B => SUMMAND(553), DATA_C => SUMMAND(554),
SAVE => INT_SUM(549), CARRY => INT_CARRY(435)
);
---- End FA stage
---- Begin FA stage
FA_443:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(555), DATA_B => SUMMAND(556), DATA_C => SUMMAND(557),
SAVE => INT_SUM(550), CARRY => INT_CARRY(436)
);
---- End FA stage
---- Begin FA stage
FA_444:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(548), DATA_B => INT_SUM(549), DATA_C => INT_SUM(550),
SAVE => INT_SUM(551), CARRY => INT_CARRY(437)
);
---- End FA stage
---- Begin FA stage
FA_445:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(427), DATA_B => INT_CARRY(428), DATA_C => INT_CARRY(429),
SAVE => INT_SUM(552), CARRY => INT_CARRY(438)
);
---- End FA stage
---- Begin FA stage
FA_446:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(551), DATA_B => INT_SUM(552), DATA_C => INT_CARRY(430),
SAVE => INT_SUM(553), CARRY => INT_CARRY(439)
);
---- End FA stage
---- Begin NO stage
INT_SUM(554) <= INT_CARRY(431); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_447:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(553), DATA_B => INT_SUM(554), DATA_C => INT_CARRY(432),
SAVE => INT_SUM(555), CARRY => INT_CARRY(440)
);
---- End FA stage
---- Begin HA stage
HA_43:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(555), DATA_B => INT_CARRY(433),
SAVE => SUM(51), CARRY => CARRY(51)
);
---- End HA stage
-- End WT-branch 52
-- Begin WT-branch 53
---- Begin FA stage
FA_448:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(558), DATA_B => SUMMAND(559), DATA_C => SUMMAND(560),
SAVE => INT_SUM(556), CARRY => INT_CARRY(441)
);
---- End FA stage
---- Begin FA stage
FA_449:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(561), DATA_B => SUMMAND(562), DATA_C => SUMMAND(563),
SAVE => INT_SUM(557), CARRY => INT_CARRY(442)
);
---- End FA stage
---- Begin FA stage
FA_450:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(564), DATA_B => SUMMAND(565), DATA_C => INT_CARRY(434),
SAVE => INT_SUM(558), CARRY => INT_CARRY(443)
);
---- End FA stage
---- Begin HA stage
HA_44:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(435), DATA_B => INT_CARRY(436),
SAVE => INT_SUM(559), CARRY => INT_CARRY(444)
);
---- End HA stage
---- Begin FA stage
FA_451:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(556), DATA_B => INT_SUM(557), DATA_C => INT_SUM(558),
SAVE => INT_SUM(560), CARRY => INT_CARRY(445)
);
---- End FA stage
---- Begin FA stage
FA_452:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(559), DATA_B => INT_CARRY(437), DATA_C => INT_CARRY(438),
SAVE => INT_SUM(561), CARRY => INT_CARRY(446)
);
---- End FA stage
---- Begin FA stage
FA_453:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(560), DATA_B => INT_SUM(561), DATA_C => INT_CARRY(439),
SAVE => INT_SUM(562), CARRY => INT_CARRY(447)
);
---- End FA stage
---- Begin HA stage
HA_45:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(562), DATA_B => INT_CARRY(440),
SAVE => SUM(52), CARRY => CARRY(52)
);
---- End HA stage
-- End WT-branch 53
-- Begin WT-branch 54
---- Begin FA stage
FA_454:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(566), DATA_B => SUMMAND(567), DATA_C => SUMMAND(568),
SAVE => INT_SUM(563), CARRY => INT_CARRY(448)
);
---- End FA stage
---- Begin FA stage
FA_455:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(569), DATA_B => SUMMAND(570), DATA_C => SUMMAND(571),
SAVE => INT_SUM(564), CARRY => INT_CARRY(449)
);
---- End FA stage
---- Begin NO stage
INT_SUM(565) <= SUMMAND(572); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(566) <= SUMMAND(573); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_456:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(563), DATA_B => INT_SUM(564), DATA_C => INT_SUM(565),
SAVE => INT_SUM(567), CARRY => INT_CARRY(450)
);
---- End FA stage
---- Begin NO stage
INT_SUM(568) <= INT_SUM(566); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_457:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(567), DATA_B => INT_SUM(568), DATA_C => INT_CARRY(441),
SAVE => INT_SUM(569), CARRY => INT_CARRY(451)
);
---- End FA stage
---- Begin FA stage
FA_458:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(442), DATA_B => INT_CARRY(443), DATA_C => INT_CARRY(444),
SAVE => INT_SUM(570), CARRY => INT_CARRY(452)
);
---- End FA stage
---- Begin FA stage
FA_459:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(569), DATA_B => INT_SUM(570), DATA_C => INT_CARRY(445),
SAVE => INT_SUM(571), CARRY => INT_CARRY(453)
);
---- End FA stage
---- Begin NO stage
INT_SUM(572) <= INT_CARRY(446); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_460:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(571), DATA_B => INT_SUM(572), DATA_C => INT_CARRY(447),
SAVE => SUM(53), CARRY => CARRY(53)
);
---- End FA stage
-- End WT-branch 54
-- Begin WT-branch 55
---- Begin FA stage
FA_461:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(574), DATA_B => SUMMAND(575), DATA_C => SUMMAND(576),
SAVE => INT_SUM(573), CARRY => INT_CARRY(454)
);
---- End FA stage
---- Begin FA stage
FA_462:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(577), DATA_B => SUMMAND(578), DATA_C => SUMMAND(579),
SAVE => INT_SUM(574), CARRY => INT_CARRY(455)
);
---- End FA stage
---- Begin FA stage
FA_463:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(580), DATA_B => INT_CARRY(448), DATA_C => INT_CARRY(449),
SAVE => INT_SUM(575), CARRY => INT_CARRY(456)
);
---- End FA stage
---- Begin FA stage
FA_464:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(573), DATA_B => INT_SUM(574), DATA_C => INT_SUM(575),
SAVE => INT_SUM(576), CARRY => INT_CARRY(457)
);
---- End FA stage
---- Begin NO stage
INT_SUM(577) <= INT_CARRY(450); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_465:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(576), DATA_B => INT_SUM(577), DATA_C => INT_CARRY(451),
SAVE => INT_SUM(578), CARRY => INT_CARRY(458)
);
---- End FA stage
---- Begin NO stage
INT_SUM(579) <= INT_CARRY(452); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_466:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(578), DATA_B => INT_SUM(579), DATA_C => INT_CARRY(453),
SAVE => SUM(54), CARRY => CARRY(54)
);
---- End FA stage
-- End WT-branch 55
-- Begin WT-branch 56
---- Begin FA stage
FA_467:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(581), DATA_B => SUMMAND(582), DATA_C => SUMMAND(583),
SAVE => INT_SUM(580), CARRY => INT_CARRY(459)
);
---- End FA stage
---- Begin FA stage
FA_468:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(584), DATA_B => SUMMAND(585), DATA_C => SUMMAND(586),
SAVE => INT_SUM(581), CARRY => INT_CARRY(460)
);
---- End FA stage
---- Begin NO stage
INT_SUM(582) <= SUMMAND(587); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_469:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(580), DATA_B => INT_SUM(581), DATA_C => INT_SUM(582),
SAVE => INT_SUM(583), CARRY => INT_CARRY(461)
);
---- End FA stage
---- Begin FA stage
FA_470:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(454), DATA_B => INT_CARRY(455), DATA_C => INT_CARRY(456),
SAVE => INT_SUM(584), CARRY => INT_CARRY(462)
);
---- End FA stage
---- Begin FA stage
FA_471:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(583), DATA_B => INT_SUM(584), DATA_C => INT_CARRY(457),
SAVE => INT_SUM(585), CARRY => INT_CARRY(463)
);
---- End FA stage
---- Begin HA stage
HA_46:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(585), DATA_B => INT_CARRY(458),
SAVE => SUM(55), CARRY => CARRY(55)
);
---- End HA stage
-- End WT-branch 56
-- Begin WT-branch 57
---- Begin FA stage
FA_472:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(588), DATA_B => SUMMAND(589), DATA_C => SUMMAND(590),
SAVE => INT_SUM(586), CARRY => INT_CARRY(464)
);
---- End FA stage
---- Begin FA stage
FA_473:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(591), DATA_B => SUMMAND(592), DATA_C => SUMMAND(593),
SAVE => INT_SUM(587), CARRY => INT_CARRY(465)
);
---- End FA stage
---- Begin FA stage
FA_474:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(586), DATA_B => INT_SUM(587), DATA_C => INT_CARRY(459),
SAVE => INT_SUM(588), CARRY => INT_CARRY(466)
);
---- End FA stage
---- Begin NO stage
INT_SUM(589) <= INT_CARRY(460); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_475:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(588), DATA_B => INT_SUM(589), DATA_C => INT_CARRY(461),
SAVE => INT_SUM(590), CARRY => INT_CARRY(467)
);
---- End FA stage
---- Begin NO stage
INT_SUM(591) <= INT_CARRY(462); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_476:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(590), DATA_B => INT_SUM(591), DATA_C => INT_CARRY(463),
SAVE => SUM(56), CARRY => CARRY(56)
);
---- End FA stage
-- End WT-branch 57
-- Begin WT-branch 58
---- Begin FA stage
FA_477:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(594), DATA_B => SUMMAND(595), DATA_C => SUMMAND(596),
SAVE => INT_SUM(592), CARRY => INT_CARRY(468)
);
---- End FA stage
---- Begin FA stage
FA_478:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(597), DATA_B => SUMMAND(598), DATA_C => SUMMAND(599),
SAVE => INT_SUM(593), CARRY => INT_CARRY(469)
);
---- End FA stage
---- Begin FA stage
FA_479:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(592), DATA_B => INT_SUM(593), DATA_C => INT_CARRY(464),
SAVE => INT_SUM(594), CARRY => INT_CARRY(470)
);
---- End FA stage
---- Begin NO stage
INT_SUM(595) <= INT_CARRY(465); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_480:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(594), DATA_B => INT_SUM(595), DATA_C => INT_CARRY(466),
SAVE => INT_SUM(596), CARRY => INT_CARRY(471)
);
---- End FA stage
---- Begin HA stage
HA_47:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(596), DATA_B => INT_CARRY(467),
SAVE => SUM(57), CARRY => CARRY(57)
);
---- End HA stage
-- End WT-branch 58
-- Begin WT-branch 59
---- Begin FA stage
FA_481:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(600), DATA_B => SUMMAND(601), DATA_C => SUMMAND(602),
SAVE => INT_SUM(597), CARRY => INT_CARRY(472)
);
---- End FA stage
---- Begin HA stage
HA_48:HALF_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(603), DATA_B => SUMMAND(604),
SAVE => INT_SUM(598), CARRY => INT_CARRY(473)
);
---- End HA stage
---- Begin FA stage
FA_482:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(597), DATA_B => INT_SUM(598), DATA_C => INT_CARRY(468),
SAVE => INT_SUM(599), CARRY => INT_CARRY(474)
);
---- End FA stage
---- Begin NO stage
INT_SUM(600) <= INT_CARRY(469); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_483:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(599), DATA_B => INT_SUM(600), DATA_C => INT_CARRY(470),
SAVE => INT_SUM(601), CARRY => INT_CARRY(475)
);
---- End FA stage
---- Begin HA stage
HA_49:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(601), DATA_B => INT_CARRY(471),
SAVE => SUM(58), CARRY => CARRY(58)
);
---- End HA stage
-- End WT-branch 59
-- Begin WT-branch 60
---- Begin FA stage
FA_484:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(605), DATA_B => SUMMAND(606), DATA_C => SUMMAND(607),
SAVE => INT_SUM(602), CARRY => INT_CARRY(476)
);
---- End FA stage
---- Begin HA stage
HA_50:HALF_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(608), DATA_B => SUMMAND(609),
SAVE => INT_SUM(603), CARRY => INT_CARRY(477)
);
---- End HA stage
---- Begin FA stage
FA_485:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(602), DATA_B => INT_SUM(603), DATA_C => INT_CARRY(472),
SAVE => INT_SUM(604), CARRY => INT_CARRY(478)
);
---- End FA stage
---- Begin NO stage
INT_SUM(605) <= INT_CARRY(473); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_486:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(604), DATA_B => INT_SUM(605), DATA_C => INT_CARRY(474),
SAVE => INT_SUM(606), CARRY => INT_CARRY(479)
);
---- End FA stage
---- Begin HA stage
HA_51:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(606), DATA_B => INT_CARRY(475),
SAVE => SUM(59), CARRY => CARRY(59)
);
---- End HA stage
-- End WT-branch 60
-- Begin WT-branch 61
---- Begin FA stage
FA_487:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(610), DATA_B => SUMMAND(611), DATA_C => SUMMAND(612),
SAVE => INT_SUM(607), CARRY => INT_CARRY(480)
);
---- End FA stage
---- Begin FA stage
FA_488:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(613), DATA_B => INT_CARRY(476), DATA_C => INT_CARRY(477),
SAVE => INT_SUM(608), CARRY => INT_CARRY(481)
);
---- End FA stage
---- Begin FA stage
FA_489:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(607), DATA_B => INT_SUM(608), DATA_C => INT_CARRY(478),
SAVE => INT_SUM(609), CARRY => INT_CARRY(482)
);
---- End FA stage
---- Begin HA stage
HA_52:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(609), DATA_B => INT_CARRY(479),
SAVE => SUM(60), CARRY => CARRY(60)
);
---- End HA stage
-- End WT-branch 61
-- Begin WT-branch 62
---- Begin FA stage
FA_490:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(614), DATA_B => SUMMAND(615), DATA_C => SUMMAND(616),
SAVE => INT_SUM(610), CARRY => INT_CARRY(483)
);
---- End FA stage
---- Begin NO stage
INT_SUM(611) <= SUMMAND(617); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_491:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(610), DATA_B => INT_SUM(611), DATA_C => INT_CARRY(480),
SAVE => INT_SUM(612), CARRY => INT_CARRY(484)
);
---- End FA stage
---- Begin NO stage
INT_SUM(613) <= INT_CARRY(481); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_492:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(612), DATA_B => INT_SUM(613), DATA_C => INT_CARRY(482),
SAVE => SUM(61), CARRY => CARRY(61)
);
---- End FA stage
-- End WT-branch 62
-- Begin WT-branch 63
---- Begin FA stage
FA_493:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(618), DATA_B => SUMMAND(619), DATA_C => SUMMAND(620),
SAVE => INT_SUM(614), CARRY => INT_CARRY(485)
);
---- End FA stage
---- Begin NO stage
INT_SUM(615) <= INT_SUM(614); -- At Level 5
---- End NO stage
---- Begin NO stage
INT_SUM(616) <= INT_CARRY(483); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_494:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(615), DATA_B => INT_SUM(616), DATA_C => INT_CARRY(484),
SAVE => SUM(62), CARRY => CARRY(62)
);
---- End FA stage
-- End WT-branch 63
-- Begin WT-branch 64
---- Begin FA stage
FA_495:FULL_ADDER -- At Level 5
port map
(
DATA_A => SUMMAND(621), DATA_B => SUMMAND(622), DATA_C => SUMMAND(623),
SAVE => INT_SUM(617), CARRY => INT_CARRY(486)
);
---- End FA stage
---- Begin NO stage
INT_SUM(618) <= INT_CARRY(485); -- At Level 5
---- End NO stage
---- Begin HA stage
HA_53:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(617), DATA_B => INT_SUM(618),
SAVE => SUM(63), CARRY => CARRY(63)
);
---- End HA stage
-- End WT-branch 64
-- Begin WT-branch 65
---- Begin NO stage
INT_SUM(619) <= SUMMAND(624); -- At Level 5
---- End NO stage
---- Begin NO stage
INT_SUM(620) <= SUMMAND(625); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_496:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(619), DATA_B => INT_SUM(620), DATA_C => INT_CARRY(486),
SAVE => SUM(64), CARRY => CARRY(64)
);
---- End FA stage
-- End WT-branch 65
-- Begin WT-branch 66
---- Begin HA stage
HA_54:HALF_ADDER -- At Level 6
port map
(
DATA_A => SUMMAND(626), DATA_B => SUMMAND(627),
SAVE => SUM(65), CARRY => CARRY(65)
);
---- End HA stage
-- End WT-branch 66
-- Begin WT-branch 67
---- Begin NO stage
SUM(66) <= SUMMAND(628); -- At Level 6
---- End NO stage
-- End WT-branch 67
end WALLACE;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MULTIPLIER_34_34 is
generic (mulpipe : integer := 0);
port
(
MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 33);
PHI: in std_logic;
holdn: in std_logic;
RESULT: out std_logic_vector(0 to 127)
);
end MULTIPLIER_34_34;
architecture MULTIPLIER of MULTIPLIER_34_34 is
signal PPBIT:std_logic_vector(0 to 628);
signal INT_CARRY: std_logic_vector(0 to 128);
signal INT_SUM: std_logic_vector(0 to 127);
signal LOGIC_ZERO: std_logic;
signal INT_CARRYR: std_logic_vector(0 to 128);
signal INT_SUMR: std_logic_vector(0 to 127);
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_34_34
port map
(
OPA(0 to 33) => MULTIPLICAND(0 to 33),
OPB(0 to 33) => MULTIPLIER(0 to 33),
SUMMAND(0 to 628) => PPBIT(0 to 628)
);
W:WALLACE_34_34
port map
(
SUMMAND(0 to 628) => PPBIT(0 to 628),
CARRY(0 to 65) => INT_CARRY(1 to 66),
SUM(0 to 66) => INT_SUM(0 to 66)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(67) <= LOGIC_ZERO;
INT_CARRY(68) <= LOGIC_ZERO;
INT_CARRY(69) <= LOGIC_ZERO;
INT_CARRY(70) <= LOGIC_ZERO;
INT_CARRY(71) <= LOGIC_ZERO;
INT_CARRY(72) <= LOGIC_ZERO;
INT_CARRY(73) <= LOGIC_ZERO;
INT_CARRY(74) <= LOGIC_ZERO;
INT_CARRY(75) <= LOGIC_ZERO;
INT_CARRY(76) <= LOGIC_ZERO;
INT_CARRY(77) <= LOGIC_ZERO;
INT_CARRY(78) <= LOGIC_ZERO;
INT_CARRY(79) <= LOGIC_ZERO;
INT_CARRY(80) <= LOGIC_ZERO;
INT_CARRY(81) <= LOGIC_ZERO;
INT_CARRY(82) <= LOGIC_ZERO;
INT_CARRY(83) <= LOGIC_ZERO;
INT_CARRY(84) <= LOGIC_ZERO;
INT_CARRY(85) <= LOGIC_ZERO;
INT_CARRY(86) <= LOGIC_ZERO;
INT_CARRY(87) <= LOGIC_ZERO;
INT_CARRY(88) <= LOGIC_ZERO;
INT_CARRY(89) <= LOGIC_ZERO;
INT_CARRY(90) <= LOGIC_ZERO;
INT_CARRY(91) <= LOGIC_ZERO;
INT_CARRY(92) <= LOGIC_ZERO;
INT_CARRY(93) <= LOGIC_ZERO;
INT_CARRY(94) <= LOGIC_ZERO;
INT_CARRY(95) <= LOGIC_ZERO;
INT_CARRY(96) <= LOGIC_ZERO;
INT_CARRY(97) <= LOGIC_ZERO;
INT_CARRY(98) <= LOGIC_ZERO;
INT_CARRY(99) <= LOGIC_ZERO;
INT_CARRY(100) <= LOGIC_ZERO;
INT_CARRY(101) <= LOGIC_ZERO;
INT_CARRY(102) <= LOGIC_ZERO;
INT_CARRY(103) <= LOGIC_ZERO;
INT_CARRY(104) <= LOGIC_ZERO;
INT_CARRY(105) <= LOGIC_ZERO;
INT_CARRY(106) <= LOGIC_ZERO;
INT_CARRY(107) <= LOGIC_ZERO;
INT_CARRY(108) <= LOGIC_ZERO;
INT_CARRY(109) <= LOGIC_ZERO;
INT_CARRY(110) <= LOGIC_ZERO;
INT_CARRY(111) <= LOGIC_ZERO;
INT_CARRY(112) <= LOGIC_ZERO;
INT_CARRY(113) <= LOGIC_ZERO;
INT_CARRY(114) <= LOGIC_ZERO;
INT_CARRY(115) <= LOGIC_ZERO;
INT_CARRY(116) <= LOGIC_ZERO;
INT_CARRY(117) <= LOGIC_ZERO;
INT_CARRY(118) <= LOGIC_ZERO;
INT_CARRY(119) <= LOGIC_ZERO;
INT_CARRY(120) <= LOGIC_ZERO;
INT_CARRY(121) <= LOGIC_ZERO;
INT_CARRY(122) <= LOGIC_ZERO;
INT_CARRY(123) <= LOGIC_ZERO;
INT_CARRY(124) <= LOGIC_ZERO;
INT_CARRY(125) <= LOGIC_ZERO;
INT_CARRY(126) <= LOGIC_ZERO;
INT_CARRY(127) <= LOGIC_ZERO;
INT_SUM(67) <= LOGIC_ZERO;
INT_SUM(68) <= LOGIC_ZERO;
INT_SUM(69) <= LOGIC_ZERO;
INT_SUM(70) <= LOGIC_ZERO;
INT_SUM(71) <= LOGIC_ZERO;
INT_SUM(72) <= LOGIC_ZERO;
INT_SUM(73) <= LOGIC_ZERO;
INT_SUM(74) <= LOGIC_ZERO;
INT_SUM(75) <= LOGIC_ZERO;
INT_SUM(76) <= LOGIC_ZERO;
INT_SUM(77) <= LOGIC_ZERO;
INT_SUM(78) <= LOGIC_ZERO;
INT_SUM(79) <= LOGIC_ZERO;
INT_SUM(80) <= LOGIC_ZERO;
INT_SUM(81) <= LOGIC_ZERO;
INT_SUM(82) <= LOGIC_ZERO;
INT_SUM(83) <= LOGIC_ZERO;
INT_SUM(84) <= LOGIC_ZERO;
INT_SUM(85) <= LOGIC_ZERO;
INT_SUM(86) <= LOGIC_ZERO;
INT_SUM(87) <= LOGIC_ZERO;
INT_SUM(88) <= LOGIC_ZERO;
INT_SUM(89) <= LOGIC_ZERO;
INT_SUM(90) <= LOGIC_ZERO;
INT_SUM(91) <= LOGIC_ZERO;
INT_SUM(92) <= LOGIC_ZERO;
INT_SUM(93) <= LOGIC_ZERO;
INT_SUM(94) <= LOGIC_ZERO;
INT_SUM(95) <= LOGIC_ZERO;
INT_SUM(96) <= LOGIC_ZERO;
INT_SUM(97) <= LOGIC_ZERO;
INT_SUM(98) <= LOGIC_ZERO;
INT_SUM(99) <= LOGIC_ZERO;
INT_SUM(100) <= LOGIC_ZERO;
INT_SUM(101) <= LOGIC_ZERO;
INT_SUM(102) <= LOGIC_ZERO;
INT_SUM(103) <= LOGIC_ZERO;
INT_SUM(104) <= LOGIC_ZERO;
INT_SUM(105) <= LOGIC_ZERO;
INT_SUM(106) <= LOGIC_ZERO;
INT_SUM(107) <= LOGIC_ZERO;
INT_SUM(108) <= LOGIC_ZERO;
INT_SUM(109) <= LOGIC_ZERO;
INT_SUM(110) <= LOGIC_ZERO;
INT_SUM(111) <= LOGIC_ZERO;
INT_SUM(112) <= LOGIC_ZERO;
INT_SUM(113) <= LOGIC_ZERO;
INT_SUM(114) <= LOGIC_ZERO;
INT_SUM(115) <= LOGIC_ZERO;
INT_SUM(116) <= LOGIC_ZERO;
INT_SUM(117) <= LOGIC_ZERO;
INT_SUM(118) <= LOGIC_ZERO;
INT_SUM(119) <= LOGIC_ZERO;
INT_SUM(120) <= LOGIC_ZERO;
INT_SUM(121) <= LOGIC_ZERO;
INT_SUM(122) <= LOGIC_ZERO;
INT_SUM(123) <= LOGIC_ZERO;
INT_SUM(124) <= LOGIC_ZERO;
INT_SUM(125) <= LOGIC_ZERO;
INT_SUM(126) <= LOGIC_ZERO;
INT_SUM(127) <= LOGIC_ZERO;
INT_SUMR(67 to 127) <= INT_SUM(67 to 127);
INT_CARRYR(67 to 127) <= INT_CARRY(67 to 127);
INT_CARRYR(0) <= INT_CARRY(0);
reg : if MULPIPE /= 0 generate
process (PHI) begin
if rising_edge(PHI ) then
if (holdn = '1') then
INT_SUMR(0 to 66) <= INT_SUM(0 to 66);
INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66);
end if;
end if;
end process;
end generate;
noreg : if MULPIPE = 0 generate
INT_SUMR(0 to 66) <= INT_SUM(0 to 66);
INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66);
end generate;
D:DBLCADDER_128_128
port map
(
OPA(0 to 127) => INT_SUMR(0 to 127),
OPB(0 to 127) => INT_CARRYR(0 to 127),
CIN => LOGIC_ZERO,
PHI => PHI,
SUM(0 to 127) => RESULT(0 to 127)
);
end MULTIPLIER;
------------------------------------------------------------
-- END: Architectures used with the multiplier
------------------------------------------------------------
--
-- Modgen multiplier created Fri Aug 16 16:35:11 2002
--
------------------------------------------------------------
-- START: Multiplier Entitiy
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- START: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MUL_33_33 is
generic (mulpipe : integer := 0);
port(clk : in std_ulogic;
holdn: in std_ulogic;
X: in std_logic_vector(32 downto 0);
Y: in std_logic_vector(32 downto 0);
P: out std_logic_vector(65 downto 0));
end MUL_33_33;
architecture A of MUL_33_33 is
signal A: std_logic_vector(0 to 33);
signal B: std_logic_vector(0 to 33);
signal Q: std_logic_vector(0 to 127);
begin
U1: MULTIPLIER_34_34 generic map (mulpipe) port map(A,B,CLK, holdn ,Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(17);
A(18) <= X(18);
A(19) <= X(19);
A(20) <= X(20);
A(21) <= X(21);
A(22) <= X(22);
A(23) <= X(23);
A(24) <= X(24);
A(25) <= X(25);
A(26) <= X(26);
A(27) <= X(27);
A(28) <= X(28);
A(29) <= X(29);
A(30) <= X(30);
A(31) <= X(31);
A(32) <= X(32);
A(33) <= X(32);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(9);
B(10) <= Y(10);
B(11) <= Y(11);
B(12) <= Y(12);
B(13) <= Y(13);
B(14) <= Y(14);
B(15) <= Y(15);
B(16) <= Y(16);
B(17) <= Y(17);
B(18) <= Y(18);
B(19) <= Y(19);
B(20) <= Y(20);
B(21) <= Y(21);
B(22) <= Y(22);
B(23) <= Y(23);
B(24) <= Y(24);
B(25) <= Y(25);
B(26) <= Y(26);
B(27) <= Y(27);
B(28) <= Y(28);
B(29) <= Y(29);
B(30) <= Y(30);
B(31) <= Y(31);
B(32) <= Y(32);
B(33) <= Y(32);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
P(34) <= Q(34);
P(35) <= Q(35);
P(36) <= Q(36);
P(37) <= Q(37);
P(38) <= Q(38);
P(39) <= Q(39);
P(40) <= Q(40);
P(41) <= Q(41);
P(42) <= Q(42);
P(43) <= Q(43);
P(44) <= Q(44);
P(45) <= Q(45);
P(46) <= Q(46);
P(47) <= Q(47);
P(48) <= Q(48);
P(49) <= Q(49);
P(50) <= Q(50);
P(51) <= Q(51);
P(52) <= Q(52);
P(53) <= Q(53);
P(54) <= Q(54);
P(55) <= Q(55);
P(56) <= Q(56);
P(57) <= Q(57);
P(58) <= Q(58);
P(59) <= Q(59);
P(60) <= Q(60);
P(61) <= Q(61);
P(62) <= Q(62);
P(63) <= Q(63);
P(64) <= Q(64);
P(65) <= Q(65);
end A;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity ADD32 is
port(X: in std_logic_vector(31 downto 0);
Y: in std_logic_vector(31 downto 0);
CI: in std_logic;
S: out std_logic_vector(31 downto 0);
CO: out std_logic);
end ADD32;
architecture A of ADD32 is
signal A,B,Q: std_logic_vector(0 to 31);
signal CLK: std_logic;
begin
U1: DBLCADDER_32_32 port map(A,B,CI,CLK,Q,CO);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
B(0) <= Y(0);
A(1) <= X(1);
B(1) <= Y(1);
A(2) <= X(2);
B(2) <= Y(2);
A(3) <= X(3);
B(3) <= Y(3);
A(4) <= X(4);
B(4) <= Y(4);
A(5) <= X(5);
B(5) <= Y(5);
A(6) <= X(6);
B(6) <= Y(6);
A(7) <= X(7);
B(7) <= Y(7);
A(8) <= X(8);
B(8) <= Y(8);
A(9) <= X(9);
B(9) <= Y(9);
A(10) <= X(10);
B(10) <= Y(10);
A(11) <= X(11);
B(11) <= Y(11);
A(12) <= X(12);
B(12) <= Y(12);
A(13) <= X(13);
B(13) <= Y(13);
A(14) <= X(14);
B(14) <= Y(14);
A(15) <= X(15);
B(15) <= Y(15);
A(16) <= X(16);
B(16) <= Y(16);
A(17) <= X(17);
B(17) <= Y(17);
A(18) <= X(18);
B(18) <= Y(18);
A(19) <= X(19);
B(19) <= Y(19);
A(20) <= X(20);
B(20) <= Y(20);
A(21) <= X(21);
B(21) <= Y(21);
A(22) <= X(22);
B(22) <= Y(22);
A(23) <= X(23);
B(23) <= Y(23);
A(24) <= X(24);
B(24) <= Y(24);
A(25) <= X(25);
B(25) <= Y(25);
A(26) <= X(26);
B(26) <= Y(26);
A(27) <= X(27);
B(27) <= Y(27);
A(28) <= X(28);
B(28) <= Y(28);
A(29) <= X(29);
B(29) <= Y(29);
A(30) <= X(30);
B(30) <= Y(30);
A(31) <= X(31);
B(31) <= Y(31);
S(0) <= Q(0);
S(1) <= Q(1);
S(2) <= Q(2);
S(3) <= Q(3);
S(4) <= Q(4);
S(5) <= Q(5);
S(6) <= Q(6);
S(7) <= Q(7);
S(8) <= Q(8);
S(9) <= Q(9);
S(10) <= Q(10);
S(11) <= Q(11);
S(12) <= Q(12);
S(13) <= Q(13);
S(14) <= Q(14);
S(15) <= Q(15);
S(16) <= Q(16);
S(17) <= Q(17);
S(18) <= Q(18);
S(19) <= Q(19);
S(20) <= Q(20);
S(21) <= Q(21);
S(22) <= Q(22);
S(23) <= Q(23);
S(24) <= Q(24);
S(25) <= Q(25);
S(26) <= Q(26);
S(27) <= Q(27);
S(28) <= Q(28);
S(29) <= Q(29);
S(30) <= Q(30);
S(31) <= Q(31);
end A;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MUL_17_17 is
generic (mulpipe : integer := 0);
port(clk : in std_ulogic;
holdn: in std_ulogic;
X: in std_logic_vector(16 downto 0);
Y: in std_logic_vector(16 downto 0);
P: out std_logic_vector(33 downto 0));
end MUL_17_17;
architecture A of MUL_17_17 is
signal A: std_logic_vector(0 to 17);
signal B: std_logic_vector(0 to 17);
signal Q: std_logic_vector(0 to 63);
begin
U1: MULTIPLIER_18_18 generic map (mulpipe) port map(A,B,CLK, holdn, Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(16);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(9);
B(10) <= Y(10);
B(11) <= Y(11);
B(12) <= Y(12);
B(13) <= Y(13);
B(14) <= Y(14);
B(15) <= Y(15);
B(16) <= Y(16);
B(17) <= Y(16);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
end A;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml403/ahbrom.vhd | 15 | 5978 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 272;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"87444000";
when 16#0002D# => romdata <= X"8730E01C";
when 16#0002E# => romdata <= X"8688E00F";
when 16#0002F# => romdata <= X"12800006";
when 16#00030# => romdata <= X"033FFC00";
when 16#00031# => romdata <= X"82106100";
when 16#00032# => romdata <= X"0539A81B";
when 16#00033# => romdata <= X"8410A260";
when 16#00034# => romdata <= X"C4204000";
when 16#00035# => romdata <= X"3D1003FF";
when 16#00036# => romdata <= X"BC17A3E0";
when 16#00037# => romdata <= X"9C27A060";
when 16#00038# => romdata <= X"03100000";
when 16#00039# => romdata <= X"81C04000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000000";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000000";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml501/ahbrom.vhd | 15 | 5978 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 272;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"87444000";
when 16#0002D# => romdata <= X"8730E01C";
when 16#0002E# => romdata <= X"8688E00F";
when 16#0002F# => romdata <= X"12800006";
when 16#00030# => romdata <= X"033FFC00";
when 16#00031# => romdata <= X"82106100";
when 16#00032# => romdata <= X"0539A81B";
when 16#00033# => romdata <= X"8410A260";
when 16#00034# => romdata <= X"C4204000";
when 16#00035# => romdata <= X"3D1003FF";
when 16#00036# => romdata <= X"BC17A3E0";
when 16#00037# => romdata <= X"9C27A060";
when 16#00038# => romdata <= X"03100000";
when 16#00039# => romdata <= X"81C04000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000000";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000000";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep3sl150/ahbrom.vhd | 28 | 6162 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
Bluetouffe/VHDL | Porte_AND/addN_testbench.vhd | 2 | 1515 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:30:03 02/06/2015
-- Design Name:
-- Module Name: addN_testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addN_tb is
generic( M: integer:=5);
end addN_tb;
architecture archi of addN_tb is
signal entree1, entree2, sortie: std_logic_vector(M-1 downto 0);
component addN
generic(N: integer := 5);
port (a,b: in std_logic_vector ( N-1 downto 0);
s: out std_logic_vector (N-1 downto 0));
end component;
begin
-- de la même manière que l'on fait un port map, on va faire un generic map pour
-- attribuer une valeur au paramètre N de AddN
uut: addN generic map (N => M) port map (a=> entree1, b => entree2, s => sortie);
stimuli_entree1: process
begin
entree1 <= (others => '0');
wait for 50 ns;
loop
entree1 <= entree1 + 1;
wait for 50 ns;
end loop;
end process;
stimuli_entree2: process
begin
entree2<= (others => '0') ;
loop
if entree1=0 then
entree2 <= entree2 + 1;
end if;
wait for 50 ns ;
end loop ;
end process;
end archi;
| gpl-2.0 |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/EscaladoPrePresentacion.vhd | 2 | 2959 | ----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity EscaladoPrePresentacion is
PORT(
entrada_frec: in std_logic_vector (31 downto 0);
salida_frec: out STD_LOGIC_VECTOR(15 downto 0);
salida_uds: out STD_LOGIC_VECTOR (1 downto 0)--introducir variables bcd
);
end EscaladoPrePresentacion;
architecture Behavioral of EscaladoPrePresentacion is
component bcd_g
Port (
entrada_int: in std_logic_vector (31 downto 0);
decenas_millones : out std_logic_vector (3 downto 0);
millones : out std_logic_vector (3 downto 0);
centenas_mill : out std_logic_vector (3 downto 0);
decenas_mill : out std_logic_vector (3 downto 0);
millares : out std_logic_vector (3 downto 0);
centenas : out std_logic_vector (3 downto 0);
decenas : out std_logic_vector (3 downto 0);
unidades : out std_logic_vector (3 downto 0)
);
end component;
signal temp : std_logic_vector (31 downto 0);
constant c1 : integer:=10000;
constant c2 : integer:=10000000;
signal unidades_esc: STD_LOGIC_VECTOR(1 downto 0);
signal sal : std_logic_vector(15 downto 0);
signal decenas_millones : std_logic_vector (3 downto 0);
signal millones : std_logic_vector (3 downto 0);
signal centenas_mill : std_logic_vector (3 downto 0);
signal decenas_mill : std_logic_vector (3 downto 0);
signal millares : std_logic_vector (3 downto 0);
signal centenas : std_logic_vector (3 downto 0);
signal decenas : std_logic_vector (3 downto 0);
signal unidades : std_logic_vector (3 downto 0);
begin
temp<=entrada_frec;
conversor: bcd_g PORT MAP(
entrada_int=>entrada_frec,
decenas_millones=>decenas_millones,
millones=>millones,
centenas_mill=>centenas_mill,
decenas_mill=>decenas_mill,
millares=>millares,
centenas=>centenas,
decenas=>decenas,
unidades=>unidades);
process(temp)
begin
if unsigned(temp)<c1 then
sal<=millares & centenas & decenas & unidades;
unidades_esc<="00";
elsif to_integer(unsigned(temp))>=c1 and to_integer(unsigned(temp))<c2 then
sal<=millones¢enas_mill&decenas_mill&millares;
unidades_esc<="01";
elsif to_integer(unsigned(temp))>=c2 then
unidades_esc<="10";
sal<="00000000" & decenas_millones & millones;
else
unidades_esc<="00";
sal<="0000000000000000";
end if;
end process;
salida_uds<=unidades_esc;
salida_frec<=sal;
end Behavioral;
| gpl-2.0 |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/top_TB.vhd | 2 | 2202 | ----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_TB IS
END top_TB;
ARCHITECTURE behavior OF top_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top
PORT(
entrada : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
led : OUT std_logic_vector(6 downto 0);
led_unidades : OUT std_logic_vector(1 downto 0);
selector : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal led : std_logic_vector(6 downto 0);
signal led_unidades : std_logic_vector(1 downto 0);
signal selector : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns; --50MHZ
constant s_entrada_period : time := 8 us; --125KHZ
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
entrada => entrada,
clk => clk,
reset => reset,
led => led,
led_unidades => led_unidades,
selector => selector
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
s_entrada_process :process
begin
entrada <= '0';
wait for s_entrada_period/2;
entrada <= '1';
wait for s_entrada_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset<='1';
wait for 100 ns;
reset<='0';
wait for 2000ms;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/RelojEscalado.vhd | 2 | 1268 | ----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_mod is
Port (
entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end clk_mod;
architecture Behavioral of clk_mod is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 20 := 0;
begin
divisor_frecuencia: process (reset, entrada) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(entrada) then
if (contador = 20) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
end process;
salida <= temporal;
end Behavioral; | gpl-2.0 |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/ttop_TB.vhd | 2 | 2650 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:03:48 07/08/2015
-- Design Name:
-- Module Name: D:/Descargas/Frecuencimentro - Presentacion/ttop_TB.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ttop_TB IS
END ttop_TB;
ARCHITECTURE behavior OF ttop_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top
PORT(
entrada : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
led : OUT std_logic_vector(6 downto 0);
led_unidades : OUT std_logic_vector(1 downto 0);
selector : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal led : std_logic_vector(6 downto 0);
signal led_unidades : std_logic_vector(1 downto 0);
signal selector : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
entrada => entrada,
clk => clk,
reset => reset,
led => led,
led_unidades => led_unidades,
selector => selector
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/ConversorBinToBCD_TB.vhd | 2 | 1867 | ----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ConversorBinToBCD_TB IS
END ConversorBinToBCD_TB;
ARCHITECTURE behavior OF ConversorBinToBCD_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd
PORT(
entrada_bin : IN std_logic_vector(15 downto 0);
millares : OUT std_logic_vector(3 downto 0);
centenas : OUT std_logic_vector(3 downto 0);
decenas : OUT std_logic_vector(3 downto 0);
unidades : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_bin : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal millares : std_logic_vector(3 downto 0);
signal centenas : std_logic_vector(3 downto 0);
signal decenas : std_logic_vector(3 downto 0);
signal unidades : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd PORT MAP (
entrada_bin => entrada_bin,
millares => millares,
centenas => centenas,
decenas => decenas,
unidades => unidades
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
entrada_bin<="0001111100101101";
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd | 2 | 13444 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $
--
-- $Date: 2004/03/14 10:17:03 $
-- $Revision: 1.7 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_top.vhd,v $
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_master_top is
generic(
ARST_LVL : std_logic := '0' -- asynchronous reset level
);
port (
-- wishbone signals
wb_clk_i : in std_logic; -- master clock input
wb_rst_i : in std_logic := '0'; -- synchronous active high reset
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
wb_adr_i : in unsigned(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic; -- Valid bus cycle input
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_top;
architecture structural of i2c_master_top is
component i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal rst_i : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
begin
-- generate internal reset signal
rst_i <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
wb_ack_o <= iack_o;
-- generate wishbone write access signal
wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
-- assign wb_dat_o
assign_dato : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
case wb_adr_i is
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
when "100" => wb_dat_o <= sr; -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= (others => '0');
when others => wb_dat_o <= (others => 'X'); -- for simulation only
end case;
end if;
end process assign_dato;
-- generate registers (CR, SR see below)
gen_regs: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case wb_adr_i is
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
when "010" => ctr <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when "100" => null; --write to CR, avoid executing the others clause
-- illegal cases, for simulation only
when others =>
report ("Illegal write address, setting all registers to unknown.");
prer <= (others => 'X');
ctr <= (others => 'X');
txr <= (others => 'X');
end case;
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
cr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = 4) ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i;
end if;
else
if (done = '1' or i2c_al = '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
cr(0) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
ien <= ctr(6);
-- hookup byte controller block
byte_ctrl: i2c_master_byte_ctrl port map (
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
ena => core_en,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
i2c_al => i2c_al,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block : block
begin
-- generate status register bits
gen_sr_bits: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al or (al and not sta);
rxack <= irxack;
tip <= (rd or wr);
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
| gpl-2.0 |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/axi_powerlink_v1_00_a/hdl/vhdl/axi_powerlink.vhd | 1 | 84136 | -------------------------------------------------------------------------------
-- Entity : axi_powerlink
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel file for using the POWERLINK IP-Core
-- with Xilinx AXI.
--
-------------------------------------------------------------------------------
--
-- 2012-01-12 V0.01 zelenkaj First version
-- 2012-01-26 V0.02 zelenkaj Added number of SMI generic feature
-- 2012-01-27 V0.10 zelenkaj Incremented PdiRev
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_master_burst_v1_00_a;
use axi_master_burst_v1_00_a.axi_master_burst;
-- standard libraries declarations
library UNISIM;
use UNISIM.vcomponents.all;
-- pragma synthesis_off
library IEEE;
use IEEE.vital_timing.all;
-- pragma synthesis_on
-- other libraries declarations
library AXI_LITE_IPIF_V1_01_A;
library AXI_MASTER_BURST_V1_00_A;
entity axi_powerlink is
generic(
-- general
C_GEN_PDI : boolean := false;
C_GEN_PAR_IF : boolean := false;
C_GEN_SPI_IF : boolean := false;
C_GEN_AXI_BUS_IF : boolean := false;
C_GEN_SIMPLE_IO : boolean := false;
-- openMAC
C_MAC_PKT_SIZE : integer := 1024;
C_MAC_PKT_SIZE_LOG2 : integer := 10;
C_MAC_RX_BUFFERS : integer := 16;
C_USE_RMII : boolean := false;
C_TX_INT_PKT : boolean := false;
C_RX_INT_PKT : boolean := false;
C_USE_2ND_PHY : boolean := true;
C_NUM_SMI : integer range 1 to 2 := 2;
--pdi
C_PDI_GEN_ASYNC_BUF_0 : boolean := true;
C_PDI_ASYNC_BUF_0 : integer := 50;
C_PDI_GEN_ASYNC_BUF_1 : boolean := true;
C_PDI_ASYNC_BUF_1 : integer := 50;
C_PDI_GEN_LED : boolean := false;
C_PDI_GEN_TIME_SYNC : boolean := true;
C_PDI_GEN_SECOND_TIMER : boolean := false;
C_PDI_GEN_EVENT : boolean := true;
--global pdi and mac
C_NUM_RPDO : integer := 3;
C_RPDO_0_BUF_SIZE : integer := 100;
C_RPDO_1_BUF_SIZE : integer := 100;
C_RPDO_2_BUF_SIZE : integer := 100;
C_NUM_TPDO : integer := 1;
C_TPDO_BUF_SIZE : integer := 100;
-- pap
C_PAP_DATA_WIDTH : integer := 16;
--C_PAP_BIG_END : boolean := false;
C_PAP_LOW_ACT : boolean := false;
-- spi
C_SPI_CPOL : boolean := false;
C_SPI_CPHA : boolean := false;
--C_SPI_BIG_END : boolean := false;
-- simpleIO
C_PIO_VAL_LENGTH : integer := 50;
-- debug
C_OBSERVER_ENABLE : boolean := false;
-- clock stabiliser
C_INSTANCE_ODDR2 : boolean := false;
-- PDI AP AXI Slave
C_S_AXI_PDI_AP_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_PDI_AP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_PDI_AP_DATA_WIDTH : integer := 32;
C_S_AXI_PDI_AP_ADDR_WIDTH : integer := 32;
C_S_AXI_PDI_AP_USE_WSTRB : integer := 1;
C_S_AXI_PDI_AP_DPHASE_TIMEOUT : integer := 8;
-- PDI AP AXI Slave
C_S_AXI_SMP_PCP_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_SMP_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_SMP_PCP_DATA_WIDTH : integer := 32;
C_S_AXI_SMP_PCP_ADDR_WIDTH : integer := 32;
C_S_AXI_SMP_PCP_USE_WSTRB : integer := 1;
C_S_AXI_SMP_PCP_DPHASE_TIMEOUT : integer := 8;
-- PDI PCP AXI Slave
C_S_AXI_PDI_PCP_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_PDI_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_PDI_PCP_DATA_WIDTH : integer := 32;
C_S_AXI_PDI_PCP_ADDR_WIDTH : integer := 32;
C_S_AXI_PDI_PCP_USE_WSTRB : integer := 1;
C_S_AXI_PDI_PCP_DPHASE_TIMEOUT : integer := 8;
-- openMAC DMA AXI Master
C_M_AXI_MAC_DMA_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_MAC_DMA_DATA_WIDTH : INTEGER := 32;
C_M_AXI_MAC_DMA_NATIVE_DWIDTH : INTEGER := 32;
C_M_AXI_MAC_DMA_LENGTH_WIDTH : INTEGER := 12;
C_M_AXI_MAC_DMA_MAX_BURST_LEN : INTEGER := 16;
C_MAC_DMA_BURST_SIZE_RX : INTEGER := 8; --in bytes
C_MAC_DMA_BURST_SIZE_TX : INTEGER := 8; --in bytes
C_MAC_DMA_FIFO_SIZE_RX : INTEGER := 32; --in bytes
C_MAC_DMA_FIFO_SIZE_TX : INTEGER := 32; --in bytes
-- openMAC PKT AXI Slave
C_S_AXI_MAC_PKT_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_MAC_PKT_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_MAC_PKT_DATA_WIDTH : integer := 32;
C_S_AXI_MAC_PKT_ADDR_WIDTH : integer := 32;
C_S_AXI_MAC_PKT_USE_WSTRB : integer := 1;
C_S_AXI_MAC_PKT_DPHASE_TIMEOUT : integer := 8;
-- openMAC REG AXI Slave
--- MAC_REG
C_S_AXI_MAC_REG_RNG0_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_MAC_REG_RNG0_HIGHADDR : std_logic_vector := X"0000FFFF";
--- MAC_CMP
C_S_AXI_MAC_REG_RNG1_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_MAC_REG_RNG1_HIGHADDR : std_logic_vector := X"0000FFFF";
C_S_AXI_MAC_REG_DATA_WIDTH : integer := 32;
C_S_AXI_MAC_REG_ADDR_WIDTH : integer := 32;
C_S_AXI_MAC_REG_USE_WSTRB : integer := 1;
C_S_AXI_MAC_REG_DPHASE_TIMEOUT : integer := 8;
C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 20 --clock frequency in Hz
);
port(
M_AXI_MAC_DMA_aclk : in std_logic;
M_AXI_MAC_DMA_aresetn : in std_logic;
M_AXI_MAC_DMA_arready : in std_logic;
M_AXI_MAC_DMA_awready : in std_logic;
M_AXI_MAC_DMA_bvalid : in std_logic;
M_AXI_MAC_DMA_rlast : in std_logic;
M_AXI_MAC_DMA_rvalid : in std_logic;
M_AXI_MAC_DMA_wready : in std_logic;
S_AXI_MAC_PKT_ACLK : in std_logic;
S_AXI_MAC_PKT_ARESETN : in std_logic;
S_AXI_MAC_PKT_ARVALID : in std_logic;
S_AXI_MAC_PKT_AWVALID : in std_logic;
S_AXI_MAC_PKT_BREADY : in std_logic;
S_AXI_MAC_PKT_RREADY : in std_logic;
S_AXI_MAC_PKT_WVALID : in std_logic;
S_AXI_MAC_REG_ACLK : in std_logic;
S_AXI_MAC_REG_ARESETN : in std_logic;
S_AXI_MAC_REG_ARVALID : in std_logic;
S_AXI_MAC_REG_AWVALID : in std_logic;
S_AXI_MAC_REG_BREADY : in std_logic;
S_AXI_MAC_REG_RREADY : in std_logic;
S_AXI_MAC_REG_WVALID : in std_logic;
S_AXI_PDI_AP_ACLK : in std_logic;
S_AXI_PDI_AP_ARESETN : in std_logic;
S_AXI_PDI_AP_ARVALID : in std_logic;
S_AXI_PDI_AP_AWVALID : in std_logic;
S_AXI_PDI_AP_BREADY : in std_logic;
S_AXI_PDI_AP_RREADY : in std_logic;
S_AXI_PDI_AP_WVALID : in std_logic;
S_AXI_PDI_PCP_ACLK : in std_logic;
S_AXI_PDI_PCP_ARESETN : in std_logic;
S_AXI_PDI_PCP_ARVALID : in std_logic;
S_AXI_PDI_PCP_AWVALID : in std_logic;
S_AXI_PDI_PCP_BREADY : in std_logic;
S_AXI_PDI_PCP_RREADY : in std_logic;
S_AXI_PDI_PCP_WVALID : in std_logic;
S_AXI_SMP_PCP_ACLK : in std_logic;
S_AXI_SMP_PCP_ARESETN : in std_logic;
S_AXI_SMP_PCP_ARVALID : in std_logic;
S_AXI_SMP_PCP_AWVALID : in std_logic;
S_AXI_SMP_PCP_BREADY : in std_logic;
S_AXI_SMP_PCP_RREADY : in std_logic;
S_AXI_SMP_PCP_WVALID : in std_logic;
clk100 : in std_logic;
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic;
phy0_link : in std_logic;
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic;
phy1_link : in std_logic;
phyMii0_RxClk : in std_logic;
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic;
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
M_AXI_MAC_DMA_bresp : in std_logic_vector(1 downto 0);
M_AXI_MAC_DMA_rdata : in std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
M_AXI_MAC_DMA_rresp : in std_logic_vector(1 downto 0);
S_AXI_MAC_PKT_ARADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_PKT_AWADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_PKT_WDATA : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
S_AXI_MAC_PKT_WSTRB : in std_logic_vector((C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0);
S_AXI_MAC_REG_ARADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_REG_AWADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_REG_WDATA : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
S_AXI_MAC_REG_WSTRB : in std_logic_vector((C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0);
S_AXI_PDI_AP_ARADDR : in std_logic_vector(C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_AP_AWADDR : in std_logic_vector(C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_AP_WDATA : in std_logic_vector(C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_AP_WSTRB : in std_logic_vector((C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0);
S_AXI_PDI_PCP_ARADDR : in std_logic_vector(C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_PCP_AWADDR : in std_logic_vector(C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_PCP_WDATA : in std_logic_vector(C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_PCP_WSTRB : in std_logic_vector((C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0);
S_AXI_SMP_PCP_ARADDR : in std_logic_vector(C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_SMP_PCP_AWADDR : in std_logic_vector(C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_SMP_PCP_WDATA : in std_logic_vector(C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
S_AXI_SMP_PCP_WSTRB : in std_logic_vector((C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_be_n : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_data_I : in std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy1_RxDat : in std_logic_vector(1 downto 0);
phyMii0_RxDat : in std_logic_vector(3 downto 0);
phyMii1_RxDat : in std_logic_vector(3 downto 0);
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0);
M_AXI_MAC_DMA_arvalid : out std_logic;
M_AXI_MAC_DMA_awvalid : out std_logic;
M_AXI_MAC_DMA_bready : out std_logic;
M_AXI_MAC_DMA_md_error : out std_logic;
M_AXI_MAC_DMA_rready : out std_logic;
M_AXI_MAC_DMA_wlast : out std_logic;
M_AXI_MAC_DMA_wvalid : out std_logic;
S_AXI_MAC_PKT_ARREADY : out std_logic;
S_AXI_MAC_PKT_AWREADY : out std_logic;
S_AXI_MAC_PKT_BVALID : out std_logic;
S_AXI_MAC_PKT_RVALID : out std_logic;
S_AXI_MAC_PKT_WREADY : out std_logic;
S_AXI_MAC_REG_ARREADY : out std_logic;
S_AXI_MAC_REG_AWREADY : out std_logic;
S_AXI_MAC_REG_BVALID : out std_logic;
S_AXI_MAC_REG_RVALID : out std_logic;
S_AXI_MAC_REG_WREADY : out std_logic;
S_AXI_PDI_AP_ARREADY : out std_logic;
S_AXI_PDI_AP_AWREADY : out std_logic;
S_AXI_PDI_AP_BVALID : out std_logic;
S_AXI_PDI_AP_RVALID : out std_logic;
S_AXI_PDI_AP_WREADY : out std_logic;
S_AXI_PDI_PCP_ARREADY : out std_logic;
S_AXI_PDI_PCP_AWREADY : out std_logic;
S_AXI_PDI_PCP_BVALID : out std_logic;
S_AXI_PDI_PCP_RVALID : out std_logic;
S_AXI_PDI_PCP_WREADY : out std_logic;
S_AXI_SMP_PCP_ARREADY : out std_logic;
S_AXI_SMP_PCP_AWREADY : out std_logic;
S_AXI_SMP_PCP_BVALID : out std_logic;
S_AXI_SMP_PCP_RVALID : out std_logic;
S_AXI_SMP_PCP_WREADY : out std_logic;
ap_asyncIrq : out std_logic;
ap_asyncIrq_n : out std_logic;
ap_syncIrq : out std_logic;
ap_syncIrq_n : out std_logic;
led_error : out std_logic;
led_status : out std_logic;
mac_irq : out std_logic;
pap_ack : out std_logic;
pap_ack_n : out std_logic;
pap_data_T : out std_logic;
phy0_Rst_n : out std_logic;
phy0_SMIClk : out std_logic;
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxEn : out std_logic;
phy0_clk : out std_logic;
phy1_Rst_n : out std_logic;
phy1_SMIClk : out std_logic;
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxEn : out std_logic;
phy1_clk : out std_logic;
phyMii0_TxEn : out std_logic;
phyMii0_TxEr : out std_logic;
phyMii1_TxEn : out std_logic;
phyMii1_TxEr : out std_logic;
phy_Rst_n : out std_logic;
phy_SMIClk : out std_logic;
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic;
spi_miso : out std_logic;
tcp_irq : out std_logic;
M_AXI_MAC_DMA_araddr : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
M_AXI_MAC_DMA_arburst : out std_logic_vector(1 downto 0);
M_AXI_MAC_DMA_arcache : out std_logic_vector(3 downto 0);
M_AXI_MAC_DMA_arlen : out std_logic_vector(7 downto 0);
M_AXI_MAC_DMA_arprot : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_arsize : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_awaddr : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
M_AXI_MAC_DMA_awburst : out std_logic_vector(1 downto 0);
M_AXI_MAC_DMA_awcache : out std_logic_vector(3 downto 0);
M_AXI_MAC_DMA_awlen : out std_logic_vector(7 downto 0);
M_AXI_MAC_DMA_awprot : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_awsize : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_wdata : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
M_AXI_MAC_DMA_wstrb : out std_logic_vector((C_M_AXI_MAC_DMA_DATA_WIDTH/8)-1 downto 0);
S_AXI_MAC_PKT_BRESP : out std_logic_vector(1 downto 0);
S_AXI_MAC_PKT_RDATA : out std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
S_AXI_MAC_PKT_RRESP : out std_logic_vector(1 downto 0);
S_AXI_MAC_REG_BRESP : out std_logic_vector(1 downto 0);
S_AXI_MAC_REG_RDATA : out std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
S_AXI_MAC_REG_RRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_AP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_AP_RDATA : out std_logic_vector(C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_AP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_PCP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_PCP_RDATA : out std_logic_vector(C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_PCP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_SMP_PCP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_SMP_PCP_RDATA : out std_logic_vector(C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
S_AXI_SMP_PCP_RRESP : out std_logic_vector(1 downto 0);
led_gpo : out std_logic_vector(7 downto 0);
led_opt : out std_logic_vector(1 downto 0);
led_phyAct : out std_logic_vector(1 downto 0);
led_phyLink : out std_logic_vector(1 downto 0);
pap_data_O : out std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
phy0_TxDat : out std_logic_vector(1 downto 0);
phy1_TxDat : out std_logic_vector(1 downto 0);
phyMii0_TxDat : out std_logic_vector(3 downto 0);
phyMii1_TxDat : out std_logic_vector(3 downto 0);
pio_portOutValid : out std_logic_vector(3 downto 0);
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
test_port : out std_logic_vector(255 downto 0) := (others => '0')
);
-- Entity declarations --
-- Click here to add additional declarations --
attribute SIGIS : string;
-- Entity attributes --
attribute SIGIS of M_AXI_MAC_DMA_aclk : signal is "Clk";
attribute SIGIS of M_AXI_MAC_DMA_aresetn : signal is "Rst";
attribute SIGIS of S_AXI_MAC_PKT_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_MAC_PKT_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_MAC_REG_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_MAC_REG_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_PDI_AP_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_PDI_AP_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_PDI_PCP_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_PDI_PCP_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_SMP_PCP_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_SMP_PCP_ARESETN : signal is "Rst";
attribute SIGIS of clk100 : signal is "Clk";
attribute SIGIS of phy0_clk : signal is "Clk";
attribute SIGIS of phy1_clk : signal is "Clk";
end axi_powerlink;
architecture struct of axi_powerlink is
---- Architecture declarations -----
function get_max( a, b : integer) return integer is
begin
if a < b then
return b;
else
return a;
end if;
end get_max;
---- Component declarations -----
component ipif_master_handler
generic(
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
dma_highadr_g : integer := 31;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4
);
port (
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : in std_logic_vector(3 downto 0);
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_writedata : in std_logic_vector(31 downto 0);
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
m_clk : out std_logic;
m_readdata : out std_logic_vector(31 downto 0);
m_readdatavalid : out std_logic := '0';
m_waitrequest : out std_logic := '1'
);
end component;
component openMAC_16to32conv
generic(
bus_address_width : integer := 10;
gEndian : string := "little"
);
port (
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_byteenable : in std_logic_vector(3 downto 0);
bus_read : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_writedata : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_waitrequest : in std_logic;
bus_ack_rd : out std_logic;
bus_ack_wr : out std_logic;
bus_readdata : out std_logic_vector(31 downto 0);
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_chipselect : out std_logic;
s_read : out std_logic;
s_write : out std_logic;
s_writedata : out std_logic_vector(15 downto 0)
);
end component;
component powerlink
generic(
Simulate : boolean := false;
endian_g : string := "little";
gNumSmi : integer range 1 to 2 := 2;
genABuf1_g : boolean := true;
genABuf2_g : boolean := true;
genEvent_g : boolean := false;
genInternalAp_g : boolean := true;
genIoBuf_g : boolean := true;
genLedGadget_g : boolean := false;
genOnePdiClkDomain_g : boolean := false;
genPdi_g : boolean := true;
genSimpleIO_g : boolean := false;
genSmiIO : boolean := true;
genSpiAp_g : boolean := false;
genTimeSync_g : boolean := false;
gen_dma_observer_g : boolean := true;
iAsyBuf1Size_g : integer := 100;
iAsyBuf2Size_g : integer := 100;
iBufSizeLOG2_g : integer := 10;
iBufSize_g : integer := 1024;
iPdiRev_g : integer := 21930;
iRpdo0BufSize_g : integer := 100;
iRpdo1BufSize_g : integer := 100;
iRpdo2BufSize_g : integer := 100;
iRpdos_g : integer := 3;
iTpdoBufSize_g : integer := 100;
iTpdos_g : integer := 1;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_data_width_g : integer := 16;
m_rx_burst_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_tx_fifo_size_g : integer := 16;
papBigEnd_g : boolean := false;
papDataWidth_g : integer := 8;
papLowAct_g : boolean := false;
pioValLen_g : integer := 50;
spiBigEnd_g : boolean := false;
spiCPHA_g : boolean := false;
spiCPOL_g : boolean := false;
use2ndCmpTimer_g : boolean := true;
use2ndPhy_g : boolean := true;
useIntPacketBuf_g : boolean := true;
useRmii_g : boolean := true;
useRxIntPacketBuf_g : boolean := true
);
port (
ap_address : in std_logic_vector(12 downto 0);
ap_byteenable : in std_logic_vector(3 downto 0);
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_writedata : in std_logic_vector(31 downto 0);
clk50 : in std_logic;
clkAp : in std_logic;
clkEth : in std_logic;
clkPcp : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
m_readdatavalid : in std_logic := '0';
m_waitrequest : in std_logic;
mac_address : in std_logic_vector(11 downto 0);
mac_byteenable : in std_logic_vector(1 downto 0);
mac_chipselect : in std_logic;
mac_read : in std_logic;
mac_write : in std_logic;
mac_writedata : in std_logic_vector(15 downto 0);
mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0);
mbf_byteenable : in std_logic_vector(3 downto 0);
mbf_chipselect : in std_logic;
mbf_read : in std_logic;
mbf_write : in std_logic;
mbf_writedata : in std_logic_vector(31 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
pcp_address : in std_logic_vector(12 downto 0);
pcp_byteenable : in std_logic_vector(3 downto 0);
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_writedata : in std_logic_vector(31 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic := '1';
phy0_link : in std_logic := '0';
phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0');
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic := '1';
phy1_link : in std_logic := '0';
phyMii0_RxClk : in std_logic;
phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic := '1';
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
pkt_clk : in std_logic;
rst : in std_logic;
rstAp : in std_logic;
rstPcp : in std_logic;
smp_address : in std_logic;
smp_byteenable : in std_logic_vector(3 downto 0);
smp_read : in std_logic;
smp_write : in std_logic;
smp_writedata : in std_logic_vector(31 downto 0);
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
tcp_address : in std_logic_vector(1 downto 0);
tcp_byteenable : in std_logic_vector(3 downto 0);
tcp_chipselect : in std_logic;
tcp_read : in std_logic;
tcp_write : in std_logic;
tcp_writedata : in std_logic_vector(31 downto 0);
ap_asyncIrq : out std_logic := '0';
ap_asyncIrq_n : out std_logic := '1';
ap_irq : out std_logic := '0';
ap_irq_n : out std_logic := '1';
ap_readdata : out std_logic_vector(31 downto 0) := (others => '0');
ap_syncIrq : out std_logic := '0';
ap_syncIrq_n : out std_logic := '1';
ap_waitrequest : out std_logic;
led_error : out std_logic := '0';
led_gpo : out std_logic_vector(7 downto 0) := (others => '0');
led_opt : out std_logic_vector(1 downto 0) := (others => '0');
led_phyAct : out std_logic_vector(1 downto 0) := (others => '0');
led_phyLink : out std_logic_vector(1 downto 0) := (others => '0');
led_status : out std_logic := '0';
m_address : out std_logic_vector(29 downto 0) := (others => '0');
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0) := (others => '0');
m_read : out std_logic := '0';
m_write : out std_logic := '0';
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
mac_irq : out std_logic := '0';
mac_readdata : out std_logic_vector(15 downto 0) := (others => '0');
mac_waitrequest : out std_logic;
mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0');
mbf_waitrequest : out std_logic;
pap_ack : out std_logic := '0';
pap_ack_n : out std_logic := '1';
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
pcp_waitrequest : out std_logic;
phy0_Rst_n : out std_logic := '1';
phy0_SMIClk : out std_logic := '0';
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy0_TxEn : out std_logic := '0';
phy1_Rst_n : out std_logic := '1';
phy1_SMIClk : out std_logic := '0';
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy1_TxEn : out std_logic := '0';
phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii0_TxEn : out std_logic := '0';
phyMii0_TxEr : out std_logic := '0';
phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii1_TxEn : out std_logic := '0';
phyMii1_TxEr : out std_logic := '0';
phy_Rst_n : out std_logic := '1';
phy_SMIClk : out std_logic := '0';
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic := '0';
pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0');
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
smp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
smp_waitrequest : out std_logic;
spi_miso : out std_logic := '0';
tcp_irq : out std_logic := '0';
tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
tcp_waitrequest : out std_logic;
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0');
phy0_SMIDat : inout std_logic := '1';
phy1_SMIDat : inout std_logic := '1';
phy_SMIDat : inout std_logic := '1';
pio_portio : inout std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component axi_lite_ipif
generic(
C_ARD_ADDR_RANGE_ARRAY : slv64_array_type := (X"0000_0000_7000_0000",X"0000_0000_7000_00FF",X"0000_0000_7000_0100",X"0000_0000_7000_01FF");
C_ARD_NUM_CE_ARRAY : integer_array_type := (4,12);
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_FAMILY : string := "virtex6";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) := X"000001FF";
C_USE_WSTRB : integer := 0
);
port (
IP2Bus_Data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
IP2Bus_Error : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_WrAck : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARESETN : in std_logic;
S_AXI_ARVALID : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
Bus2IP_Addr : out std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
Bus2IP_BE : out std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
Bus2IP_CS : out std_logic_vector((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
Bus2IP_Clk : out std_logic;
Bus2IP_Data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_RdCE : out std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
Bus2IP_Resetn : out std_logic;
Bus2IP_WrCE : out std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
S_AXI_ARREADY : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic
);
end component;
component axi_master_burst
generic(
C_ADDR_PIPE_DEPTH : integer range 1 to 14 := 1;
C_FAMILY : string := "virtex6";
C_LENGTH_WIDTH : integer range 12 to 20 := 12;
C_MAX_BURST_LEN : integer range 16 to 256 := 16;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 256 := 32;
C_NATIVE_DATA_WIDTH : integer range 32 to 128 := 32
);
port (
ip2bus_mst_addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
ip2bus_mst_be : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
ip2bus_mst_length : in std_logic_vector(C_LENGTH_WIDTH-1 downto 0);
ip2bus_mst_lock : in std_logic;
ip2bus_mst_reset : in std_logic;
ip2bus_mst_type : in std_logic;
ip2bus_mstrd_dst_dsc_n : in std_logic;
ip2bus_mstrd_dst_rdy_n : in std_logic;
ip2bus_mstrd_req : in std_logic;
ip2bus_mstwr_d : in std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
ip2bus_mstwr_eof_n : in std_logic;
ip2bus_mstwr_rem : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
ip2bus_mstwr_req : in std_logic;
ip2bus_mstwr_sof_n : in std_logic;
ip2bus_mstwr_src_dsc_n : in std_logic;
ip2bus_mstwr_src_rdy_n : in std_logic;
m_axi_aclk : in std_logic;
m_axi_aresetn : in std_logic;
m_axi_arready : in std_logic;
m_axi_awready : in std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0);
m_axi_bvalid : in std_logic;
m_axi_rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
m_axi_rlast : in std_logic;
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rvalid : in std_logic;
m_axi_wready : in std_logic;
bus2ip_mst_cmd_timeout : out std_logic;
bus2ip_mst_cmdack : out std_logic;
bus2ip_mst_cmplt : out std_logic;
bus2ip_mst_error : out std_logic;
bus2ip_mst_rearbitrate : out std_logic;
bus2ip_mstrd_d : out std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
bus2ip_mstrd_eof_n : out std_logic;
bus2ip_mstrd_rem : out std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
bus2ip_mstrd_sof_n : out std_logic;
bus2ip_mstrd_src_dsc_n : out std_logic;
bus2ip_mstrd_src_rdy_n : out std_logic;
bus2ip_mstwr_dst_dsc_n : out std_logic;
bus2ip_mstwr_dst_rdy_n : out std_logic;
m_axi_araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_arburst : out std_logic_vector(1 downto 0);
m_axi_arcache : out std_logic_vector(3 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arsize : out std_logic_vector(2 downto 0);
m_axi_arvalid : out std_logic;
m_axi_awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_awburst : out std_logic_vector(1 downto 0);
m_axi_awcache : out std_logic_vector(3 downto 0);
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_awsize : out std_logic_vector(2 downto 0);
m_axi_awvalid : out std_logic;
m_axi_bready : out std_logic;
m_axi_rready : out std_logic;
m_axi_wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
m_axi_wlast : out std_logic;
m_axi_wstrb : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
m_axi_wvalid : out std_logic;
md_error : out std_logic
);
end component;
---- Architecture declarations -----
constant C_FAMILY : string := "spartan6";
constant C_ADDR_PAD_ZERO : std_logic_vector(31 downto 0) := (others => '0');
-- openMAC REG PLB Slave
constant C_MAC_REG_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG0_BASEADDR;
constant C_MAC_REG_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG0_HIGHADDR;
constant C_MAC_REG_MINSIZE : std_logic_vector(31 downto 0) := conv_std_logic_vector(get_max(conv_integer(C_S_AXI_MAC_REG_RNG0_HIGHADDR), conv_integer(C_S_AXI_MAC_REG_RNG1_HIGHADDR)), 32);
-- openMAC CMP PLB Slave
constant C_MAC_CMP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG1_BASEADDR;
constant C_MAC_CMP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG1_HIGHADDR;
-- openMAC PKT PLB Slave
constant C_MAC_PKT_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_PKT_BASEADDR;
constant C_MAC_PKT_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_PKT_HIGHADDR;
constant C_MAC_PKT_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_MAC_PKT_HIGHADDR;
-- SimpleIO Slave
constant C_SMP_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_SMP_PCP_BASEADDR;
constant C_SMP_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_SMP_PCP_HIGHADDR;
constant C_SMP_PCP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_SMP_PCP_HIGHADDR;
-- PDI PCP Slave
constant C_PDI_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_PCP_BASEADDR;
constant C_PDI_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_PCP_HIGHADDR;
constant C_PDI_PCP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_PDI_PCP_HIGHADDR;
-- AP PCP Slave
constant C_PDI_AP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_AP_BASEADDR;
constant C_PDI_AP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_AP_HIGHADDR;
constant C_PDI_AP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_PDI_AP_HIGHADDR;
-- POWERLINK IP-core
constant C_MAC_PKT_EN : boolean := C_TX_INT_PKT or C_RX_INT_PKT;
constant C_MAC_PKT_RX_EN : boolean := C_RX_INT_PKT;
constant C_DMA_EN : boolean := not C_TX_INT_PKT or not C_RX_INT_PKT;
constant C_PKT_BUF_EN : boolean := C_MAC_PKT_EN;
constant C_M_BURSTCOUNT_WIDTH : integer := integer(ceil(log2(real(get_max(C_MAC_DMA_BURST_SIZE_RX,C_MAC_DMA_BURST_SIZE_TX)/4)))) + 1; --in dwords
constant C_M_FIFO_SIZE_RX : integer := C_MAC_DMA_FIFO_SIZE_RX/4; --in dwords
constant C_M_FIFO_SIZE_TX : integer := C_MAC_DMA_FIFO_SIZE_TX/4; --in dwords
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
constant GND_CONSTANT : std_logic := '0';
---- Signal declarations used on the diagram ----
signal ap_chipselect : std_logic;
signal ap_read : std_logic;
signal ap_waitrequest : std_logic;
signal ap_write : std_logic;
signal bus2MAC_DMA_mstrd_eof_n : std_logic;
signal bus2MAC_DMA_mstrd_sof_n : std_logic;
signal bus2MAC_DMA_mstrd_src_dsc_n : std_logic;
signal bus2MAC_DMA_mstrd_src_rdy_n : std_logic;
signal bus2MAC_DMA_mstwr_dst_dsc_n : std_logic;
signal bus2MAC_DMA_mstwr_dst_rdy_n : std_logic;
signal bus2MAC_DMA_mst_cmdack : std_logic;
signal bus2MAC_DMA_mst_cmd_timeout : std_logic;
signal bus2MAC_DMA_mst_cmplt : std_logic;
signal bus2MAC_DMA_mst_error : std_logic;
signal bus2MAC_DMA_mst_rearbitrate : std_logic;
signal Bus2MAC_PKT_Clk : std_logic;
signal Bus2MAC_PKT_Reset : std_logic := '0';
signal Bus2MAC_PKT_Resetn : std_logic;
signal Bus2MAC_PKT_RNW : std_logic;
signal Bus2MAC_REG_Clk : std_logic;
signal Bus2MAC_REG_Reset : std_logic := '0';
signal Bus2MAC_REG_Resetn : std_logic;
signal Bus2MAC_REG_RNW : std_logic;
signal Bus2MAC_REG_RNW_n : std_logic;
signal Bus2PDI_AP_Clk : std_logic;
signal Bus2PDI_AP_Reset : std_logic := '0';
signal Bus2PDI_AP_Resetn : std_logic;
signal Bus2PDI_AP_RNW : std_logic;
signal Bus2PDI_PCP_Clk : std_logic;
signal Bus2PDI_PCP_Reset : std_logic := '0';
signal Bus2PDI_PCP_Resetn : std_logic;
signal Bus2PDI_PCP_RNW : std_logic;
signal Bus2SMP_PCP_Clk : std_logic;
signal Bus2SMP_PCP_Reset : std_logic := '0';
signal Bus2SMP_PCP_Resetn : std_logic;
signal Bus2SMP_PCP_RNW : std_logic;
signal clk50 : std_logic;
signal clkAp : std_logic;
signal clkPcp : std_logic;
signal GND : std_logic;
signal IP2Bus_Error_s : std_logic;
signal IP2Bus_RdAck_s : std_logic;
signal IP2Bus_WrAck_s : std_logic;
signal mac_chipselect : std_logic;
signal MAC_CMP2Bus_Error : std_logic;
signal MAC_CMP2Bus_RdAck : std_logic;
signal MAC_CMP2Bus_WrAck : std_logic;
signal MAC_DMA2bus_mstrd_dst_dsc_n : std_logic;
signal MAC_DMA2bus_mstrd_dst_rdy_n : std_logic;
signal MAC_DMA2bus_mstrd_req : std_logic;
signal MAC_DMA2bus_mstwr_eof_n : std_logic;
signal MAC_DMA2bus_mstwr_req : std_logic;
signal MAC_DMA2bus_mstwr_sof_n : std_logic;
signal MAC_DMA2bus_mstwr_src_dsc_n : std_logic;
signal MAC_DMA2bus_mstwr_src_rdy_n : std_logic;
signal MAC_DMA2bus_mst_lock : std_logic;
signal MAC_DMA2bus_mst_reset : std_logic;
signal MAC_DMA2bus_mst_type : std_logic;
signal MAC_DMA_areset : std_logic;
signal mac_irq_s : std_logic;
signal MAC_PKT2Bus_Error : std_logic;
signal MAC_PKT2Bus_RdAck : std_logic;
signal MAC_PKT2Bus_WrAck : std_logic;
signal mac_read : std_logic;
signal MAC_REG2Bus_Error : std_logic;
signal MAC_REG2Bus_RdAck : std_logic;
signal MAC_REG2Bus_WrAck : std_logic;
signal mac_waitrequest : std_logic;
signal mac_write : std_logic;
signal mbf_chipselect : std_logic;
signal mbf_read : std_logic;
signal mbf_waitrequest : std_logic;
signal mbf_write : std_logic;
signal m_clk : std_logic;
signal m_read : std_logic;
signal m_readdatavalid : std_logic;
signal m_waitrequest : std_logic;
signal m_write : std_logic;
signal NET38418 : std_ulogic;
signal NET38470 : std_ulogic;
signal pcp_chipselect : std_logic;
signal pcp_read : std_logic;
signal pcp_waitrequest : std_logic;
signal pcp_write : std_logic;
signal PDI_AP2Bus_Error : std_logic;
signal PDI_AP2Bus_RdAck : std_logic;
signal PDI_AP2Bus_WrAck : std_logic;
signal PDI_PCP2Bus_Error : std_logic;
signal PDI_PCP2Bus_RdAck : std_logic;
signal PDI_PCP2Bus_WrAck : std_logic;
signal pkt_clk : std_logic;
signal rst : std_logic := '0';
signal rstAp : std_logic := '0';
signal rstPcp : std_logic := '0';
signal smp_address : std_logic;
signal smp_chipselect : std_logic;
signal SMP_PCP2Bus_Error : std_logic;
signal SMP_PCP2Bus_RdAck : std_logic;
signal SMP_PCP2Bus_WrAck : std_logic;
signal smp_read : std_logic;
signal smp_waitrequest : std_logic;
signal smp_write : std_logic;
signal tcp_chipselect : std_logic;
signal tcp_irq_s : std_logic;
signal tcp_read : std_logic;
signal tcp_waitrequest : std_logic;
signal tcp_write : std_logic;
signal VCC : std_logic;
signal ap_address : std_logic_vector (12 downto 0);
signal ap_byteenable : std_logic_vector (3 downto 0);
signal ap_readdata : std_logic_vector (31 downto 0);
signal ap_writedata : std_logic_vector (31 downto 0);
signal bus2MAC_DMA_mstrd_d : std_logic_vector (C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
signal bus2MAC_DMA_mstrd_rem : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_Addr : std_logic_vector (C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
signal Bus2MAC_PKT_BE : std_logic_vector ((C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_CS : std_logic_vector (0 downto 0);
signal Bus2MAC_PKT_Data : std_logic_vector (C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
signal Bus2MAC_REG_Addr : std_logic_vector (C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
signal Bus2MAC_REG_BE : std_logic_vector ((C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0);
signal Bus2MAC_REG_CS : std_logic_vector (1 downto 0);
signal Bus2MAC_REG_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal Bus2PDI_AP_Addr : std_logic_vector (C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0);
signal Bus2PDI_AP_BE : std_logic_vector ((C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0);
signal Bus2PDI_AP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_AP_Data : std_logic_vector (C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
signal Bus2PDI_PCP_Addr : std_logic_vector (C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0);
signal Bus2PDI_PCP_BE : std_logic_vector ((C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0);
signal Bus2PDI_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_PCP_Data : std_logic_vector (C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
signal Bus2SMP_PCP_Addr : std_logic_vector (C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0);
signal Bus2SMP_PCP_BE : std_logic_vector ((C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0);
signal Bus2SMP_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2SMP_PCP_Data : std_logic_vector (C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
signal IP2Bus_Data_s : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal mac_address : std_logic_vector (11 downto 0);
signal mac_address_full : std_logic_vector (C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
signal mac_byteenable : std_logic_vector (1 downto 0);
signal MAC_CMP2Bus_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d : std_logic_vector (C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2bus_mstwr_rem : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0);
signal MAC_DMA2bus_mst_addr : std_logic_vector (C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
signal MAC_DMA2bus_mst_be : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0);
signal MAC_DMA2bus_mst_length : std_logic_vector (C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
signal MAC_PKT2Bus_Data : std_logic_vector (C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
signal mac_readdata : std_logic_vector (15 downto 0);
signal MAC_REG2Bus_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal mac_writedata : std_logic_vector (15 downto 0);
signal mbf_address : std_logic_vector (C_MAC_PKT_SIZE_LOG2-3 downto 0);
signal mbf_byteenable : std_logic_vector (3 downto 0);
signal mbf_readdata : std_logic_vector (31 downto 0);
signal mbf_writedata : std_logic_vector (31 downto 0);
signal m_address : std_logic_vector (29 downto 0);
signal m_burstcount : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_burstcounter : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_byteenable : std_logic_vector (3 downto 0);
signal m_readdata : std_logic_vector (31 downto 0);
signal m_writedata : std_logic_vector (31 downto 0);
signal pcp_address : std_logic_vector (12 downto 0);
signal pcp_byteenable : std_logic_vector (3 downto 0);
signal pcp_readdata : std_logic_vector (31 downto 0);
signal pcp_writedata : std_logic_vector (31 downto 0);
signal PDI_AP2Bus_Data : std_logic_vector (C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
signal PDI_PCP2Bus_Data : std_logic_vector (C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
signal smp_byteenable : std_logic_vector (3 downto 0);
signal SMP_PCP2Bus_Data : std_logic_vector (C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
signal smp_readdata : std_logic_vector (31 downto 0);
signal smp_writedata : std_logic_vector (31 downto 0);
signal tcp_address : std_logic_vector (1 downto 0);
signal tcp_byteenable : std_logic_vector (3 downto 0);
signal tcp_readdata : std_logic_vector (31 downto 0);
signal tcp_writedata : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
-- connect mac reg with mac cmp or reg output signals
with Bus2MAC_REG_CS select
IP2Bus_Data_s <= MAC_CMP2Bus_Data when "01",
MAC_REG2Bus_Data when others; --"10" and others are decoded to MAC_REG
IP2Bus_WrAck_s <= MAC_REG2Bus_WrAck or MAC_CMP2Bus_WrAck;
IP2Bus_RdAck_s <= MAC_REG2Bus_RdAck or MAC_CMP2Bus_RdAck;
IP2Bus_Error_s <= MAC_REG2Bus_Error or MAC_CMP2Bus_Error;
mac_address <= mac_address_full(mac_address'range);
--mac_cmp assignments
---cmp_clk <= Bus2MAC_CMP_Clk;
tcp_writedata <= Bus2MAC_REG_Data;
tcp_read <= Bus2MAC_REG_RNW;
tcp_write <= not Bus2MAC_REG_RNW;
tcp_chipselect <= Bus2MAC_REG_CS(0);
tcp_byteenable <= Bus2MAC_REG_BE;
tcp_address <= Bus2MAC_REG_Addr(3 downto 2);
MAC_CMP2Bus_Data <= tcp_readdata;
MAC_CMP2Bus_RdAck <= tcp_chipselect and tcp_read and not tcp_waitrequest;
MAC_CMP2Bus_WrAck <= tcp_chipselect and tcp_write and not tcp_waitrequest;
MAC_CMP2Bus_Error <= '0';
--mac_pkt assignments
pkt_clk <= Bus2MAC_PKT_Clk;
Bus2MAC_PKT_Reset <= not Bus2MAC_PKT_Resetn;
mbf_writedata <= Bus2MAC_PKT_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
mbf_read <= Bus2MAC_PKT_RNW;
mbf_write <= not Bus2MAC_PKT_RNW;
mbf_chipselect <= Bus2MAC_PKT_CS(0);
mbf_byteenable <= Bus2MAC_PKT_BE;
mbf_address <= Bus2MAC_PKT_Addr(C_MAC_PKT_SIZE_LOG2-1 downto 2);
MAC_PKT2Bus_Data <= mbf_readdata;
MAC_PKT2Bus_RdAck <= mbf_chipselect and mbf_read and not mbf_waitrequest;
MAC_PKT2Bus_WrAck <= mbf_chipselect and mbf_write and not mbf_waitrequest;
MAC_PKT2Bus_Error <= '0';
--test_port
--test_port(181 downto 179) <= mac_chipselect & mac_write & mac_read;
--test_port(178) <= mac_waitrequest;
--test_port(177 downto 176) <= mac_byteenable;
--
--test_port(171 downto 160) <= mac_address;
--test_port(159 downto 144) <= mac_writedata;
--test_port(143 downto 128) <= mac_readdata;
--
--test_port(104 downto 102) <= Bus2MAC_REG_CS & Bus2MAC_REG_RNW;
--test_port(101 downto 100) <= IP2Bus_WrAck_s & IP2Bus_RdAck_s;
--test_port(99 downto 96) <= Bus2MAC_REG_BE;
--
--test_port(95 downto 64) <= Bus2MAC_REG_Addr;
--test_port(63 downto 32) <= Bus2MAC_REG_Data;
--test_port(31 downto 0) <= IP2Bus_Data_s;
test_port(255 downto 251) <= m_read & m_write & m_waitrequest & m_readdatavalid & MAC_DMA2Bus_Mst_Type;
test_port(244 downto 240) <= MAC_DMA2Bus_MstWr_Req & MAC_DMA2Bus_MstWr_sof_n & MAC_DMA2Bus_MstWr_eof_n & MAC_DMA2Bus_MstWr_src_rdy_n & Bus2MAC_DMA_MstWr_dst_rdy_n;
test_port(234 downto 230) <= MAC_DMA2Bus_MstRd_Req & Bus2MAC_DMA_MstRd_sof_n & Bus2MAC_DMA_MstRd_eof_n & Bus2MAC_DMA_MstRd_src_rdy_n & MAC_DMA2Bus_MstRd_dst_rdy_n;
test_port(142 downto 140) <= Bus2MAC_DMA_Mst_Cmplt & Bus2MAC_DMA_Mst_Error & Bus2MAC_DMA_Mst_Cmd_Timeout;
test_port(MAC_DMA2Bus_Mst_Length'length+120-1 downto 120) <= MAC_DMA2Bus_Mst_Length;
test_port(m_burstcount'length+110-1 downto 110) <= m_burstcount;
test_port(m_burstcounter'length+96-1 downto 96) <= m_burstcounter;
test_port(95 downto 64) <= "00" & m_address;
test_port(63 downto 32) <= m_writedata;
test_port(31 downto 0) <= m_readdata;
---- Component instantiations ----
MAC_REG_16to32 : openMAC_16to32conv
generic map (
bus_address_width => C_S_AXI_MAC_REG_ADDR_WIDTH,
gEndian => "little"
)
port map(
bus_ack_rd => MAC_REG2Bus_RdAck,
bus_ack_wr => MAC_REG2Bus_WrAck,
bus_address => Bus2MAC_REG_Addr( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
bus_byteenable => Bus2MAC_REG_BE( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ),
bus_read => Bus2MAC_REG_RNW,
bus_readdata => MAC_REG2Bus_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
bus_select => Bus2MAC_REG_CS(1),
bus_write => Bus2MAC_REG_RNW_n,
bus_writedata => Bus2MAC_REG_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
clk => Bus2MAC_REG_Clk,
rst => Bus2MAC_REG_Reset,
s_address => mac_address_full( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
s_byteenable => mac_byteenable,
s_chipselect => mac_chipselect,
s_read => mac_read,
s_readdata => mac_readdata,
s_waitrequest => mac_waitrequest,
s_write => mac_write,
s_writedata => mac_writedata
);
MAC_REG_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_REG_BASE,C_MAC_REG_HIGH,C_MAC_CMP_BASE,C_MAC_CMP_HIGH),
C_ARD_NUM_CE_ARRAY => (1,1),
C_DPHASE_TIMEOUT => C_S_AXI_MAC_REG_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_REG_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_REG_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_MAC_REG_MINSIZE,
C_USE_WSTRB => C_S_AXI_MAC_REG_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2MAC_REG_Addr( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_REG_BE( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_REG_CS( 1 downto 0 ),
Bus2IP_Clk => Bus2MAC_REG_Clk,
Bus2IP_Data => Bus2MAC_REG_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_REG_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2MAC_REG_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => IP2Bus_Data_s( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => IP2Bus_Error_s,
IP2Bus_RdAck => IP2Bus_RdAck_s,
IP2Bus_WrAck => IP2Bus_WrAck_s,
S_AXI_ACLK => S_AXI_MAC_REG_ACLK,
S_AXI_ARADDR => S_AXI_MAC_REG_ARADDR( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_MAC_REG_ARESETN,
S_AXI_ARREADY => S_AXI_MAC_REG_ARREADY,
S_AXI_ARVALID => S_AXI_MAC_REG_ARVALID,
S_AXI_AWADDR => S_AXI_MAC_REG_AWADDR( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_MAC_REG_AWREADY,
S_AXI_AWVALID => S_AXI_MAC_REG_AWVALID,
S_AXI_BREADY => S_AXI_MAC_REG_BREADY,
S_AXI_BRESP => S_AXI_MAC_REG_BRESP,
S_AXI_BVALID => S_AXI_MAC_REG_BVALID,
S_AXI_RDATA => S_AXI_MAC_REG_RDATA( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_MAC_REG_RREADY,
S_AXI_RRESP => S_AXI_MAC_REG_RRESP,
S_AXI_RVALID => S_AXI_MAC_REG_RVALID,
S_AXI_WDATA => S_AXI_MAC_REG_WDATA( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_MAC_REG_WREADY,
S_AXI_WSTRB => S_AXI_MAC_REG_WSTRB( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_MAC_REG_WVALID
);
THE_POWERLINK_IP_CORE : powerlink
generic map (
Simulate => false,
endian_g => "little",
gNumSmi => C_NUM_SMI,
genABuf1_g => C_PDI_GEN_ASYNC_BUF_0,
genABuf2_g => C_PDI_GEN_ASYNC_BUF_1,
genEvent_g => C_PDI_GEN_EVENT,
genInternalAp_g => C_GEN_AXI_BUS_IF,
genIoBuf_g => false,
genLedGadget_g => C_PDI_GEN_LED,
genOnePdiClkDomain_g => false,
genPdi_g => C_GEN_PDI,
genSimpleIO_g => C_GEN_SIMPLE_IO,
genSmiIO => false,
genSpiAp_g => C_GEN_SPI_IF,
genTimeSync_g => C_PDI_GEN_TIME_SYNC,
gen_dma_observer_g => C_OBSERVER_ENABLE,
iAsyBuf1Size_g => C_PDI_ASYNC_BUF_0,
iAsyBuf2Size_g => C_PDI_ASYNC_BUF_1,
iBufSizeLOG2_g => C_MAC_PKT_SIZE_LOG2,
iBufSize_g => C_MAC_PKT_SIZE,
iPdiRev_g => 2,
iRpdo0BufSize_g => C_RPDO_0_BUF_SIZE,
iRpdo1BufSize_g => C_RPDO_1_BUF_SIZE,
iRpdo2BufSize_g => C_RPDO_2_BUF_SIZE,
iRpdos_g => C_NUM_RPDO,
iTpdoBufSize_g => C_TPDO_BUF_SIZE,
iTpdos_g => C_NUM_TPDO,
m_burstcount_const_g => true,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH,
m_data_width_g => 32,
m_rx_burst_size_g => C_MAC_DMA_BURST_SIZE_RX/4,
m_rx_fifo_size_g => C_M_FIFO_SIZE_RX,
m_tx_burst_size_g => C_MAC_DMA_BURST_SIZE_TX/4,
m_tx_fifo_size_g => C_M_FIFO_SIZE_TX,
papBigEnd_g => false,
papDataWidth_g => C_PAP_DATA_WIDTH,
papLowAct_g => C_PAP_LOW_ACT,
pioValLen_g => C_PIO_VAL_LENGTH,
spiBigEnd_g => false,
spiCPHA_g => C_SPI_CPHA,
spiCPOL_g => C_SPI_CPOL,
use2ndCmpTimer_g => C_PDI_GEN_SECOND_TIMER,
use2ndPhy_g => C_USE_2ND_PHY,
useIntPacketBuf_g => C_MAC_PKT_EN,
useRmii_g => C_USE_RMII,
useRxIntPacketBuf_g => C_MAC_PKT_RX_EN
)
port map(
ap_address => ap_address,
ap_asyncIrq => ap_asyncIrq,
ap_asyncIrq_n => ap_asyncIrq_n,
ap_byteenable => ap_byteenable,
ap_chipselect => ap_chipselect,
ap_irq => open,
ap_irq_n => open,
ap_read => ap_read,
ap_readdata => ap_readdata,
ap_syncIrq => ap_syncIrq,
ap_syncIrq_n => ap_syncIrq_n,
ap_waitrequest => ap_waitrequest,
ap_write => ap_write,
ap_writedata => ap_writedata,
clk50 => clk50,
clkAp => clkAp,
clkEth => clk100,
clkPcp => clkPcp,
led_error => led_error,
led_gpo => led_gpo,
led_opt => led_opt,
led_phyAct => led_phyAct,
led_phyLink => led_phyLink,
led_status => led_status,
m_address => m_address,
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable( 3 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( 31 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( 31 downto 0 ),
mac_address => mac_address,
mac_byteenable => mac_byteenable,
mac_chipselect => mac_chipselect,
mac_irq => mac_irq_s,
mac_read => mac_read,
mac_readdata => mac_readdata,
mac_waitrequest => mac_waitrequest,
mac_write => mac_write,
mac_writedata => mac_writedata,
mbf_address => mbf_address( C_MAC_PKT_SIZE_LOG2-3 downto 0 ),
mbf_byteenable => mbf_byteenable,
mbf_chipselect => mbf_chipselect,
mbf_read => mbf_read,
mbf_readdata => mbf_readdata,
mbf_waitrequest => mbf_waitrequest,
mbf_write => mbf_write,
mbf_writedata => mbf_writedata,
pap_ack => pap_ack,
pap_ack_n => pap_ack_n,
pap_addr => pap_addr,
pap_be => pap_be( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_be_n => pap_be_n( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_cs => pap_cs,
pap_cs_n => pap_cs_n,
pap_data => open,
pap_data_I => pap_data_I( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_O => pap_data_O( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_T => pap_data_T,
pap_gpio => open,
pap_gpio_I => pap_gpio_I,
pap_gpio_O => pap_gpio_O,
pap_gpio_T => pap_gpio_T,
pap_rd => pap_rd,
pap_rd_n => pap_rd_n,
pap_wr => pap_wr,
pap_wr_n => pap_wr_n,
pcp_address => pcp_address,
pcp_byteenable => pcp_byteenable,
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_write => pcp_write,
pcp_writedata => pcp_writedata,
phy0_Rst_n => phy0_Rst_n,
phy0_RxDat => phy0_RxDat,
phy0_RxDv => phy0_RxDv,
phy0_RxErr => phy0_RxErr,
phy0_SMIClk => phy0_SMIClk,
phy0_SMIDat => open,
phy0_SMIDat_I => phy0_SMIDat_I,
phy0_SMIDat_O => phy0_SMIDat_O,
phy0_SMIDat_T => phy0_SMIDat_T,
phy0_TxDat => phy0_TxDat,
phy0_TxEn => phy0_TxEn,
phy0_link => phy0_link,
phy1_Rst_n => phy1_Rst_n,
phy1_RxDat => phy1_RxDat,
phy1_RxDv => phy1_RxDv,
phy1_RxErr => phy1_RxErr,
phy1_SMIClk => phy1_SMIClk,
phy1_SMIDat => open,
phy1_SMIDat_I => phy1_SMIDat_I,
phy1_SMIDat_O => phy1_SMIDat_O,
phy1_SMIDat_T => phy1_SMIDat_T,
phy1_TxDat => phy1_TxDat,
phy1_TxEn => phy1_TxEn,
phy1_link => phy1_link,
phyMii0_RxClk => phyMii0_RxClk,
phyMii0_RxDat => phyMii0_RxDat,
phyMii0_RxDv => phyMii0_RxDv,
phyMii0_RxEr => phyMii0_RxEr,
phyMii0_TxClk => phyMii0_TxClk,
phyMii0_TxDat => phyMii0_TxDat,
phyMii0_TxEn => phyMii0_TxEn,
phyMii0_TxEr => phyMii0_TxEr,
phyMii1_RxClk => phyMii1_RxClk,
phyMii1_RxDat => phyMii1_RxDat,
phyMii1_RxDv => phyMii1_RxDv,
phyMii1_RxEr => phyMii1_RxEr,
phyMii1_TxClk => phyMii1_TxClk,
phyMii1_TxDat => phyMii1_TxDat,
phyMii1_TxEn => phyMii1_TxEn,
phyMii1_TxEr => phyMii1_TxEr,
phy_Rst_n => phy_Rst_n,
phy_SMIClk => phy_SMIClk,
phy_SMIDat => open,
phy_SMIDat_I => phy_SMIDat_I,
phy_SMIDat_O => phy_SMIDat_O,
phy_SMIDat_T => phy_SMIDat_T,
pio_operational => pio_operational,
pio_pconfig => pio_pconfig,
pio_portInLatch => pio_portInLatch,
pio_portOutValid => pio_portOutValid,
pio_portio => open,
pio_portio_I => pio_portio_I,
pio_portio_O => pio_portio_O,
pio_portio_T => pio_portio_T,
pkt_clk => pkt_clk,
rst => rst,
rstAp => rstAp,
rstPcp => rstPcp,
smp_address => smp_address,
smp_byteenable => smp_byteenable,
smp_read => smp_read,
smp_readdata => smp_readdata,
smp_waitrequest => smp_waitrequest,
smp_write => smp_write,
smp_writedata => smp_writedata,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
spi_sel_n => spi_sel_n,
tcp_address => tcp_address,
tcp_byteenable => tcp_byteenable,
tcp_chipselect => tcp_chipselect,
tcp_irq => tcp_irq_s,
tcp_read => tcp_read,
tcp_readdata => tcp_readdata,
tcp_waitrequest => tcp_waitrequest,
tcp_write => tcp_write,
tcp_writedata => tcp_writedata
);
MAC_DMA_areset <= not(M_AXI_MAC_DMA_aresetn);
Bus2MAC_REG_RNW_n <= not(Bus2MAC_REG_RNW);
clk50 <= Bus2MAC_REG_Clk;
Bus2MAC_REG_Reset <= not(Bus2MAC_REG_Resetn);
rstPcp <= Bus2SMP_PCP_Reset or Bus2PDI_PCP_Reset or Bus2MAC_PKT_Reset;
rstAp <= Bus2PDI_AP_Reset;
rst <= Bus2MAC_REG_Reset;
---- Power , ground assignment ----
GND <= GND_CONSTANT;
VCC <= VCC_CONSTANT;
MAC_REG2Bus_Error <= GND;
---- Terminal assignment ----
-- Output\buffer terminals
mac_irq <= mac_irq_s;
tcp_irq <= tcp_irq_s;
---- Generate statements ----
genMacDmaPlbBurst : if C_DMA_EN = TRUE generate
begin
MAC_DMA_AXI_BURST_MASTER : axi_master_burst
generic map (
C_ADDR_PIPE_DEPTH => 1,
C_FAMILY => C_FAMILY,
C_LENGTH_WIDTH => C_M_AXI_MAC_DMA_LENGTH_WIDTH,
C_MAX_BURST_LEN => C_M_AXI_MAC_DMA_MAX_BURST_LEN,
C_M_AXI_ADDR_WIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_MAC_DMA_DATA_WIDTH,
C_NATIVE_DATA_WIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH
)
port map(
bus2ip_mst_cmd_timeout => bus2MAC_DMA_mst_cmd_timeout,
bus2ip_mst_cmdack => bus2MAC_DMA_mst_cmdack,
bus2ip_mst_cmplt => bus2MAC_DMA_mst_cmplt,
bus2ip_mst_error => bus2MAC_DMA_mst_error,
bus2ip_mst_rearbitrate => bus2MAC_DMA_mst_rearbitrate,
bus2ip_mstrd_d => bus2MAC_DMA_mstrd_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
bus2ip_mstrd_eof_n => bus2MAC_DMA_mstrd_eof_n,
bus2ip_mstrd_rem => bus2MAC_DMA_mstrd_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
bus2ip_mstrd_sof_n => bus2MAC_DMA_mstrd_sof_n,
bus2ip_mstrd_src_dsc_n => bus2MAC_DMA_mstrd_src_dsc_n,
bus2ip_mstrd_src_rdy_n => bus2MAC_DMA_mstrd_src_rdy_n,
bus2ip_mstwr_dst_dsc_n => bus2MAC_DMA_mstwr_dst_dsc_n,
bus2ip_mstwr_dst_rdy_n => bus2MAC_DMA_mstwr_dst_rdy_n,
ip2bus_mst_addr => MAC_DMA2bus_mst_addr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
ip2bus_mst_be => MAC_DMA2bus_mst_be( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
ip2bus_mst_length => MAC_DMA2bus_mst_length( C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0 ),
ip2bus_mst_lock => MAC_DMA2bus_mst_lock,
ip2bus_mst_reset => MAC_DMA2bus_mst_reset,
ip2bus_mst_type => MAC_DMA2bus_mst_type,
ip2bus_mstrd_dst_dsc_n => MAC_DMA2bus_mstrd_dst_dsc_n,
ip2bus_mstrd_dst_rdy_n => MAC_DMA2bus_mstrd_dst_rdy_n,
ip2bus_mstrd_req => MAC_DMA2bus_mstrd_req,
ip2bus_mstwr_d => MAC_DMA2bus_mstwr_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
ip2bus_mstwr_eof_n => MAC_DMA2bus_mstwr_eof_n,
ip2bus_mstwr_rem => MAC_DMA2bus_mstwr_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
ip2bus_mstwr_req => MAC_DMA2bus_mstwr_req,
ip2bus_mstwr_sof_n => MAC_DMA2bus_mstwr_sof_n,
ip2bus_mstwr_src_dsc_n => MAC_DMA2bus_mstwr_src_dsc_n,
ip2bus_mstwr_src_rdy_n => MAC_DMA2bus_mstwr_src_rdy_n,
m_axi_aclk => M_AXI_MAC_DMA_aclk,
m_axi_araddr => M_AXI_MAC_DMA_araddr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
m_axi_arburst => M_AXI_MAC_DMA_arburst,
m_axi_arcache => M_AXI_MAC_DMA_arcache,
m_axi_aresetn => M_AXI_MAC_DMA_aresetn,
m_axi_arlen => M_AXI_MAC_DMA_arlen,
m_axi_arprot => M_AXI_MAC_DMA_arprot,
m_axi_arready => M_AXI_MAC_DMA_arready,
m_axi_arsize => M_AXI_MAC_DMA_arsize,
m_axi_arvalid => M_AXI_MAC_DMA_arvalid,
m_axi_awaddr => M_AXI_MAC_DMA_awaddr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
m_axi_awburst => M_AXI_MAC_DMA_awburst,
m_axi_awcache => M_AXI_MAC_DMA_awcache,
m_axi_awlen => M_AXI_MAC_DMA_awlen,
m_axi_awprot => M_AXI_MAC_DMA_awprot,
m_axi_awready => M_AXI_MAC_DMA_awready,
m_axi_awsize => M_AXI_MAC_DMA_awsize,
m_axi_awvalid => M_AXI_MAC_DMA_awvalid,
m_axi_bready => M_AXI_MAC_DMA_bready,
m_axi_bresp => M_AXI_MAC_DMA_bresp,
m_axi_bvalid => M_AXI_MAC_DMA_bvalid,
m_axi_rdata => M_AXI_MAC_DMA_rdata( C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0 ),
m_axi_rlast => M_AXI_MAC_DMA_rlast,
m_axi_rready => M_AXI_MAC_DMA_rready,
m_axi_rresp => M_AXI_MAC_DMA_rresp,
m_axi_rvalid => M_AXI_MAC_DMA_rvalid,
m_axi_wdata => M_AXI_MAC_DMA_wdata( C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0 ),
m_axi_wlast => M_AXI_MAC_DMA_wlast,
m_axi_wready => M_AXI_MAC_DMA_wready,
m_axi_wstrb => M_AXI_MAC_DMA_wstrb( (C_M_AXI_MAC_DMA_DATA_WIDTH/8)-1 downto 0 ),
m_axi_wvalid => M_AXI_MAC_DMA_wvalid,
md_error => M_AXI_MAC_DMA_md_error
);
end generate genMacDmaPlbBurst;
genThePlbMaster : if C_DMA_EN = TRUE generate
begin
THE_IPIF_MASTER_HANDLER : ipif_master_handler
generic map (
C_MAC_DMA_IPIF_AWIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_MAC_DMA_IPIF_NATIVE_DWIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH,
dma_highadr_g => m_address'high,
gen_rx_fifo_g => not C_RX_INT_PKT,
gen_tx_fifo_g => not C_TX_INT_PKT,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH
)
port map(
Bus2MAC_DMA_MstRd_d => bus2MAC_DMA_mstrd_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
Bus2MAC_DMA_MstRd_eof_n => bus2MAC_DMA_mstrd_eof_n,
Bus2MAC_DMA_MstRd_rem => bus2MAC_DMA_mstrd_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
Bus2MAC_DMA_MstRd_sof_n => bus2MAC_DMA_mstrd_sof_n,
Bus2MAC_DMA_MstRd_src_dsc_n => bus2MAC_DMA_mstrd_src_dsc_n,
Bus2MAC_DMA_MstRd_src_rdy_n => bus2MAC_DMA_mstrd_src_rdy_n,
Bus2MAC_DMA_MstWr_dst_dsc_n => bus2MAC_DMA_mstwr_dst_dsc_n,
Bus2MAC_DMA_MstWr_dst_rdy_n => bus2MAC_DMA_mstwr_dst_rdy_n,
Bus2MAC_DMA_Mst_CmdAck => bus2MAC_DMA_mst_cmdack,
Bus2MAC_DMA_Mst_Cmd_Timeout => bus2MAC_DMA_mst_cmd_timeout,
Bus2MAC_DMA_Mst_Cmplt => bus2MAC_DMA_mst_cmplt,
Bus2MAC_DMA_Mst_Error => bus2MAC_DMA_mst_error,
Bus2MAC_DMA_Mst_Rearbitrate => bus2MAC_DMA_mst_rearbitrate,
MAC_DMA2Bus_MstRd_Req => MAC_DMA2bus_mstrd_req,
MAC_DMA2Bus_MstRd_dst_dsc_n => MAC_DMA2bus_mstrd_dst_dsc_n,
MAC_DMA2Bus_MstRd_dst_rdy_n => MAC_DMA2bus_mstrd_dst_rdy_n,
MAC_DMA2Bus_MstWr_Req => MAC_DMA2bus_mstwr_req,
MAC_DMA2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
MAC_DMA2Bus_MstWr_eof_n => MAC_DMA2bus_mstwr_eof_n,
MAC_DMA2Bus_MstWr_rem => MAC_DMA2bus_mstwr_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
MAC_DMA2Bus_MstWr_sof_n => MAC_DMA2bus_mstwr_sof_n,
MAC_DMA2Bus_MstWr_src_dsc_n => MAC_DMA2bus_mstwr_src_dsc_n,
MAC_DMA2Bus_MstWr_src_rdy_n => MAC_DMA2bus_mstwr_src_rdy_n,
MAC_DMA2Bus_Mst_Addr => MAC_DMA2bus_mst_addr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
MAC_DMA2Bus_Mst_BE => MAC_DMA2bus_mst_be( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
MAC_DMA2Bus_Mst_Length => MAC_DMA2bus_mst_length( C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0 ),
MAC_DMA2Bus_Mst_Lock => MAC_DMA2bus_mst_lock,
MAC_DMA2Bus_Mst_Reset => MAC_DMA2bus_mst_reset,
MAC_DMA2Bus_Mst_Type => MAC_DMA2bus_mst_type,
MAC_DMA_CLK => M_AXI_MAC_DMA_aclk,
MAC_DMA_Rst => MAC_DMA_areset,
m_address => m_address( 29 downto 0 ),
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable,
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata
);
end generate genThePlbMaster;
genMacPktPLbSingleSlave : if C_PKT_BUF_EN generate
begin
MAC_PKT_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_PKT_BASE,C_MAC_PKT_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_MAC_PKT_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_PKT_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_PKT_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_MAC_PKT_MINSIZE,
C_USE_WSTRB => C_S_AXI_MAC_PKT_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2MAC_PKT_Addr( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_PKT_BE( (C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_PKT_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2MAC_PKT_Clk,
Bus2IP_Data => Bus2MAC_PKT_Data( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_PKT_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2MAC_PKT_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => MAC_PKT2Bus_Data( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => MAC_PKT2Bus_Error,
IP2Bus_RdAck => MAC_PKT2Bus_RdAck,
IP2Bus_WrAck => MAC_PKT2Bus_WrAck,
S_AXI_ACLK => S_AXI_MAC_PKT_ACLK,
S_AXI_ARADDR => S_AXI_MAC_PKT_ARADDR( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_MAC_PKT_ARESETN,
S_AXI_ARREADY => S_AXI_MAC_PKT_ARREADY,
S_AXI_ARVALID => S_AXI_MAC_PKT_ARVALID,
S_AXI_AWADDR => S_AXI_MAC_PKT_AWADDR( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_MAC_PKT_AWREADY,
S_AXI_AWVALID => S_AXI_MAC_PKT_AWVALID,
S_AXI_BREADY => S_AXI_MAC_PKT_BREADY,
S_AXI_BRESP => S_AXI_MAC_PKT_BRESP,
S_AXI_BVALID => S_AXI_MAC_PKT_BVALID,
S_AXI_RDATA => S_AXI_MAC_PKT_RDATA( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_MAC_PKT_RREADY,
S_AXI_RRESP => S_AXI_MAC_PKT_RRESP,
S_AXI_RVALID => S_AXI_MAC_PKT_RVALID,
S_AXI_WDATA => S_AXI_MAC_PKT_WDATA( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_MAC_PKT_WREADY,
S_AXI_WSTRB => S_AXI_MAC_PKT_WSTRB( (C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_MAC_PKT_WVALID
);
end generate genMacPktPLbSingleSlave;
genPdiPcp : if (C_GEN_PDI) generate
begin
PDI_PCP_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_PCP_BASE,C_PDI_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_PDI_PCP_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_PDI_PCP_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_PDI_PCP_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_PDI_PCP_MINSIZE,
C_USE_WSTRB => C_S_AXI_PDI_PCP_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2PDI_PCP_Addr( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_PCP_BE( (C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_PCP_Clk,
Bus2IP_Data => Bus2PDI_PCP_Data( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_PCP_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2PDI_PCP_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => PDI_PCP2Bus_Data( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => PDI_PCP2Bus_Error,
IP2Bus_RdAck => PDI_PCP2Bus_RdAck,
IP2Bus_WrAck => PDI_PCP2Bus_WrAck,
S_AXI_ACLK => S_AXI_PDI_PCP_ACLK,
S_AXI_ARADDR => S_AXI_PDI_PCP_ARADDR( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_PDI_PCP_ARESETN,
S_AXI_ARREADY => S_AXI_PDI_PCP_ARREADY,
S_AXI_ARVALID => S_AXI_PDI_PCP_ARVALID,
S_AXI_AWADDR => S_AXI_PDI_PCP_AWADDR( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_PDI_PCP_AWREADY,
S_AXI_AWVALID => S_AXI_PDI_PCP_AWVALID,
S_AXI_BREADY => S_AXI_PDI_PCP_BREADY,
S_AXI_BRESP => S_AXI_PDI_PCP_BRESP,
S_AXI_BVALID => S_AXI_PDI_PCP_BVALID,
S_AXI_RDATA => S_AXI_PDI_PCP_RDATA( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_PDI_PCP_RREADY,
S_AXI_RRESP => S_AXI_PDI_PCP_RRESP,
S_AXI_RVALID => S_AXI_PDI_PCP_RVALID,
S_AXI_WDATA => S_AXI_PDI_PCP_WDATA( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_PDI_PCP_WREADY,
S_AXI_WSTRB => S_AXI_PDI_PCP_WSTRB( (C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_PDI_PCP_WVALID
);
end generate genPdiPcp;
genPcpPdiLink : if C_GEN_PDI generate
begin
--pdi_pcp assignments
clkPcp <= Bus2PDI_PCP_Clk;
Bus2PDI_PCP_Reset <= not Bus2PDI_PCP_Resetn;
pcp_writedata <= Bus2PDI_PCP_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
pcp_read <= Bus2PDI_PCP_RNW;
pcp_write <= not Bus2PDI_PCP_RNW;
pcp_chipselect <= Bus2PDI_PCP_CS(0);
pcp_byteenable <= Bus2PDI_PCP_BE;
pcp_address <= Bus2PDI_PCP_Addr(14 downto 2);
PDI_PCP2Bus_Data <= pcp_readdata;
PDI_PCP2Bus_RdAck <= pcp_chipselect and pcp_read and not pcp_waitrequest;
PDI_PCP2Bus_WrAck <= pcp_chipselect and pcp_write and not pcp_waitrequest;
PDI_PCP2Bus_Error <= '0';
end generate genPcpPdiLink;
genPdiAp : if (C_GEN_AXI_BUS_IF) generate
begin
PDI_AP_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_AP_BASE,C_PDI_AP_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_PDI_AP_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_PDI_AP_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_PDI_AP_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_PDI_AP_MINSIZE,
C_USE_WSTRB => C_S_AXI_PDI_AP_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2PDI_AP_Addr( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_AP_BE( (C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_AP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_AP_Clk,
Bus2IP_Data => Bus2PDI_AP_Data( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_AP_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2PDI_AP_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => PDI_AP2Bus_Data( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => PDI_AP2Bus_Error,
IP2Bus_RdAck => PDI_AP2Bus_RdAck,
IP2Bus_WrAck => PDI_AP2Bus_WrAck,
S_AXI_ACLK => S_AXI_PDI_AP_ACLK,
S_AXI_ARADDR => S_AXI_PDI_AP_ARADDR( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_PDI_AP_ARESETN,
S_AXI_ARREADY => S_AXI_PDI_AP_ARREADY,
S_AXI_ARVALID => S_AXI_PDI_AP_ARVALID,
S_AXI_AWADDR => S_AXI_PDI_AP_AWADDR( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_PDI_AP_AWREADY,
S_AXI_AWVALID => S_AXI_PDI_AP_AWVALID,
S_AXI_BREADY => S_AXI_PDI_AP_BREADY,
S_AXI_BRESP => S_AXI_PDI_AP_BRESP,
S_AXI_BVALID => S_AXI_PDI_AP_BVALID,
S_AXI_RDATA => S_AXI_PDI_AP_RDATA( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_PDI_AP_RREADY,
S_AXI_RRESP => S_AXI_PDI_AP_RRESP,
S_AXI_RVALID => S_AXI_PDI_AP_RVALID,
S_AXI_WDATA => S_AXI_PDI_AP_WDATA( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_PDI_AP_WREADY,
S_AXI_WSTRB => S_AXI_PDI_AP_WSTRB( (C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_PDI_AP_WVALID
);
end generate genPdiAp;
genApPdiLink : if C_GEN_PDI generate
begin
--ap_pcp assignments
clkAp <= Bus2PDI_AP_Clk;
Bus2PDI_AP_Reset <= not Bus2PDI_AP_Resetn;
ap_writedata <= Bus2PDI_AP_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
ap_read <= Bus2PDI_AP_RNW;
ap_write <= not Bus2PDI_AP_RNW;
ap_chipselect <= Bus2PDI_AP_CS(0);
ap_byteenable <= Bus2PDI_AP_BE;
ap_address <= Bus2PDI_AP_Addr(14 downto 2);
PDI_AP2Bus_Data <= ap_readdata;
PDI_AP2Bus_RdAck <= ap_chipselect and ap_read and not ap_waitrequest;
PDI_AP2Bus_WrAck <= ap_chipselect and ap_write and not ap_waitrequest;
PDI_AP2Bus_Error <= '0';
end generate genApPdiLink;
genSmpIo : if (C_GEN_SIMPLE_IO) generate
begin
SMP_IO_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_SMP_PCP_BASE,C_SMP_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_SMP_PCP_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_SMP_PCP_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_SMP_PCP_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_SMP_PCP_MINSIZE,
C_USE_WSTRB => C_S_AXI_SMP_PCP_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2SMP_PCP_Addr( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2SMP_PCP_BE( (C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2SMP_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2SMP_PCP_Clk,
Bus2IP_Data => Bus2SMP_PCP_Data( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2SMP_PCP_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2SMP_PCP_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => SMP_PCP2Bus_Data( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => SMP_PCP2Bus_Error,
IP2Bus_RdAck => SMP_PCP2Bus_RdAck,
IP2Bus_WrAck => SMP_PCP2Bus_WrAck,
S_AXI_ACLK => S_AXI_SMP_PCP_ACLK,
S_AXI_ARADDR => S_AXI_SMP_PCP_ARADDR( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_SMP_PCP_ARESETN,
S_AXI_ARREADY => S_AXI_SMP_PCP_ARREADY,
S_AXI_ARVALID => S_AXI_SMP_PCP_ARVALID,
S_AXI_AWADDR => S_AXI_SMP_PCP_AWADDR( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_SMP_PCP_AWREADY,
S_AXI_AWVALID => S_AXI_SMP_PCP_AWVALID,
S_AXI_BREADY => S_AXI_SMP_PCP_BREADY,
S_AXI_BRESP => S_AXI_SMP_PCP_BRESP,
S_AXI_BVALID => S_AXI_SMP_PCP_BVALID,
S_AXI_RDATA => S_AXI_SMP_PCP_RDATA( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_SMP_PCP_RREADY,
S_AXI_RRESP => S_AXI_SMP_PCP_RRESP,
S_AXI_RVALID => S_AXI_SMP_PCP_RVALID,
S_AXI_WDATA => S_AXI_SMP_PCP_WDATA( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_SMP_PCP_WREADY,
S_AXI_WSTRB => S_AXI_SMP_PCP_WSTRB( (C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_SMP_PCP_WVALID
);
end generate genSmpIo;
genSimpleIoSignals : if C_GEN_SIMPLE_IO generate
begin
--SMP_PCP assignments
clkPcp <= Bus2SMP_PCP_Clk;
Bus2SMP_PCP_Reset <= not Bus2SMP_PCP_Resetn;
smp_writedata <= Bus2SMP_PCP_Data;
smp_read <= Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_write <= not Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_chipselect <= Bus2SMP_PCP_CS(0);
smp_byteenable <= Bus2SMP_PCP_BE;
smp_address <= Bus2SMP_PCP_Addr(2);
SMP_PCP2Bus_Data <= smp_readdata;
SMP_PCP2Bus_RdAck <= smp_chipselect and smp_read and not smp_waitrequest;
SMP_PCP2Bus_WrAck <= smp_chipselect and smp_write and not smp_waitrequest;
SMP_PCP2Bus_Error <= '0';
end generate genSimpleIoSignals;
oddr2_0 : if not C_INSTANCE_ODDR2 generate
begin
phy0_clk <= clk50;
phy1_clk <= clk50;
end generate oddr2_0;
oddr2_1 : if C_INSTANCE_ODDR2 generate
begin
U10 : ODDR2
port map(
C0 => clk50,
C1 => NET38418,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy0_clk,
R => GND,
S => GND
);
U11 : ODDR2
port map(
C0 => clk50,
C1 => NET38470,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy1_clk,
R => GND,
S => GND
);
NET38470 <= not(clk50);
NET38418 <= not(clk50);
end generate oddr2_1;
end struct;
| gpl-2.0 |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAmaster.vhd | 3 | 21895 | -------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel of the openMAC DMA master component.
-- It introduces a generic master device applying burst transfers for
-- RX and TX packet data transfers via a common bus.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-10-13 V0.02 zelenkaj changed names of instances
-- 2011-11-28 V0.03 zelenkaj Added DMA observer
-- 2011-11-29 V0.04 zelenkaj Changed clkXing of Dma Addr
-- 2011-11-30 V0.05 zelenkaj Added generic for DMA observer
-- 2011-12-02 V0.06 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.07 zelenkaj Reduced Dma Req overflow
-- 2012-03-21 V0.10 zelenkaj Fixed 32 bit FIFO to support openMAC endian
-- 2012-04-17 V0.11 zelenkaj Added forwarding of DMA read length
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_new_len : out std_logic;
dma_rd_err : out std_logic;
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
dma_new_len_rd : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
component OpenMAC_DMAFifo
generic(
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port (
aclr : in std_logic;
rd_clk : in std_logic;
rd_req : in std_logic;
wr_clk : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end component;
component slow2fastSync
generic(
doSync_g : boolean := TRUE
);
port (
clkDst : in std_logic;
clkSrc : in std_logic;
dataSrc : in std_logic;
rstDst : in std_logic;
rstSrc : in std_logic;
dataDst : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal dma_new_rd_len : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_dma_new_rd_len : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_empty_s : std_logic;
signal tx_rd_empty_s_l : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal dma_rd_len_trans : std_logic_vector (11 downto 0);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_new_len => dma_new_rd_len,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_rd_len_out => dma_rd_len_trans,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_len_rd => dma_rd_len_trans,
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
dma_new_len_rd => m_dma_new_rd_len,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_tx_off,
dataSrc => mac_tx_off,
rstDst => rst,
rstSrc => rst
);
sync2 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_rx_off,
dataSrc => mac_rx_off,
rstDst => rst,
rstSrc => rst
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_empty_proc :
process(tx_aclr, tx_rd_clk)
begin
if tx_aclr = '1' then
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end process;
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
end generate rxFifoGen;
--
wr_data <= dma_dout;
dma_din <= rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_wr,
dataSrc => dma_new_addr_wr,
rstDst => rst,
rstSrc => rst
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_rd,
dataSrc => dma_new_addr_rd,
rstDst => rst,
rstSrc => rst
);
sync6 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_rd_len,
dataSrc => dma_new_rd_len,
rstDst => rst,
rstSrc => rst
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req_s,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
--workaround...
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else
rd_data(31 downto 16);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req_s,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= dma_dout & wr_data_s;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
| gpl-2.0 |
gauravks/i210dummy | Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_burst_0.vhd | 4 | 41369 | --Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
--synthesis translate_off
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_burst_0_fifo_module_fifo_ram_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity niosII_openMac_burst_0_fifo_module_fifo_ram_module;
architecture europa of niosII_openMac_burst_0_fifo_module_fifo_ram_module is
signal internal_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
TYPE mem_array is ARRAY( 3 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
signal read_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
begin
process (wrclock, clk) -- MG
VARIABLE rd_address_internal : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
VARIABLE wr_address_internal : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
variable Marc_Gaucherons_Memory_Variable : mem_array; -- MG
begin
-- Write data
if wrclock'event and wrclock = '1' then
wr_address_internal := wraddress;
if wren = '1' then
Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(wr_address_internal))) := data;
end if;
end if;
-- read data
q <= Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(rd_address_internal)));
IF clk'event AND clk = '1' AND rdclken = '1' THEN
rd_address_internal := rdaddress;
END IF;
end process;
end europa;
--synthesis translate_on
--synthesis read_comments_as_HDL on
--library altera;
--use altera.altera_europa_support_lib.all;
--
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--
--entity niosII_openMac_burst_0_fifo_module_fifo_ram_module is
-- port (
--
-- signal clk : IN STD_LOGIC;
-- signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal rdclken : IN STD_LOGIC;
-- signal reset_n : IN STD_LOGIC;
-- signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal wrclock : IN STD_LOGIC;
-- signal wren : IN STD_LOGIC;
--
--
-- signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-- );
--end entity niosII_openMac_burst_0_fifo_module_fifo_ram_module;
--
--
--architecture europa of niosII_openMac_burst_0_fifo_module_fifo_ram_module is
-- component lpm_ram_dp is
--GENERIC (
-- lpm_file : STRING;
-- lpm_hint : STRING;
-- lpm_indata : STRING;
-- lpm_outdata : STRING;
-- lpm_rdaddress_control : STRING;
-- lpm_width : NATURAL;
-- lpm_widthad : NATURAL;
-- lpm_wraddress_control : STRING;
-- suppress_memory_conversion_warnings : STRING
-- );
-- PORT (
-- signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal wren : IN STD_LOGIC;
-- signal rdclock : IN STD_LOGIC;
-- signal wrclock : IN STD_LOGIC;
-- signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdclken : IN STD_LOGIC
-- );
-- end component lpm_ram_dp;
-- signal internal_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- TYPE mem_array is ARRAY( 3 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
-- signal read_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
--
--begin
--
-- process (rdaddress)
-- begin
-- read_address <= rdaddress;
--
-- end process;
--
-- lpm_ram_dp_component : lpm_ram_dp
-- generic map(
-- lpm_file => "UNUSED",
-- lpm_hint => "USE_EAB=OFF",
-- lpm_indata => "REGISTERED",
-- lpm_outdata => "UNREGISTERED",
-- lpm_rdaddress_control => "REGISTERED",
-- lpm_width => 32,
-- lpm_widthad => 2,
-- lpm_wraddress_control => "REGISTERED",
-- suppress_memory_conversion_warnings => "ON"
-- )
-- port map(
-- data => data,
-- q => internal_q,
-- rdaddress => read_address,
-- rdclken => rdclken,
-- rdclock => clk,
-- wraddress => wraddress,
-- wrclock => wrclock,
-- wren => wren
-- );
--
--
-- q <= internal_q;
--end europa;
--
--synthesis read_comments_as_HDL off
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_burst_0_fifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal fifo_read : IN STD_LOGIC;
signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : IN STD_LOGIC;
signal flush_fifo : IN STD_LOGIC;
signal inc_pending_data : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal fifo_datavalid : OUT STD_LOGIC;
signal fifo_empty : OUT STD_LOGIC;
signal fifo_full : OUT STD_LOGIC;
signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal p1_fifo_empty : OUT STD_LOGIC
);
end entity niosII_openMac_burst_0_fifo_module;
architecture europa of niosII_openMac_burst_0_fifo_module is
component niosII_openMac_burst_0_fifo_module_fifo_ram_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component niosII_openMac_burst_0_fifo_module_fifo_ram_module;
signal estimated_rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal estimated_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_dec : STD_LOGIC;
signal fifo_inc : STD_LOGIC;
signal fifo_ram_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_fifo_empty : STD_LOGIC;
signal internal_fifo_full : STD_LOGIC;
signal internal_p1_fifo_empty : STD_LOGIC;
signal last_write_collision : STD_LOGIC;
signal last_write_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input : STD_LOGIC;
signal p1_estimated_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal p1_fifo_full : STD_LOGIC;
signal p1_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdaddress_reg : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal write_collision : STD_LOGIC;
begin
p1_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((fifo_write)) = '1'), ((std_logic_vector'("0000000000000000000000000000000") & (wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("0000000000000000000000000000000") & (wraddress))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
wraddress <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(flush_fifo) = '1' then
wraddress <= std_logic_vector'("00");
else
wraddress <= p1_wraddress;
end if;
end if;
end if;
end process;
rdaddress <= A_EXT (A_WE_StdLogicVector((std_logic'(flush_fifo) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(fifo_read) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001"))), (std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
rdaddress_reg <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
rdaddress_reg <= rdaddress;
end if;
end process;
fifo_datavalid <= NOT internal_fifo_empty;
fifo_inc <= fifo_write AND NOT fifo_read;
fifo_dec <= fifo_read AND NOT fifo_write;
estimated_rdaddress <= A_EXT (((std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001")), 2);
p1_estimated_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((inc_pending_data)) = '1'), ((std_logic_vector'("0000000000000000000000000000000") & (estimated_wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("0000000000000000000000000000000") & (estimated_wraddress))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
estimated_wraddress <= A_REP(std_logic'('1'), 2);
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(flush_fifo) = '1' then
estimated_wraddress <= A_REP(std_logic'('1'), 2);
else
estimated_wraddress <= p1_estimated_wraddress;
end if;
end if;
end if;
end process;
internal_p1_fifo_empty <= flush_fifo OR ((((NOT fifo_inc AND internal_fifo_empty)) OR ((fifo_dec AND to_std_logic(((wraddress = estimated_rdaddress)))))));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_fifo_empty <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
internal_fifo_empty <= internal_p1_fifo_empty;
end if;
end if;
end process;
p1_fifo_full <= NOT flush_fifo AND ((((NOT fifo_dec AND internal_fifo_full)) OR ((inc_pending_data AND to_std_logic(((estimated_wraddress = rdaddress)))))));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_fifo_full <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
internal_fifo_full <= p1_fifo_full;
end if;
end if;
end process;
write_collision <= fifo_write AND to_std_logic(((wraddress = rdaddress)));
process (clk, reset_n)
begin
if reset_n = '0' then
last_write_data <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(write_collision) = '1' then
last_write_data <= fifo_wr_data;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
last_write_collision <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(write_collision) = '1' then
last_write_collision <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(fifo_read) = '1' then
last_write_collision <= std_logic'('0');
end if;
end if;
end process;
fifo_rd_data <= A_WE_StdLogicVector((std_logic'(last_write_collision) = '1'), last_write_data, fifo_ram_q);
--niosII_openMac_burst_0_fifo_module_fifo_ram, which is an e_ram
niosII_openMac_burst_0_fifo_module_fifo_ram : niosII_openMac_burst_0_fifo_module_fifo_ram_module
port map(
q => fifo_ram_q,
clk => clk,
data => fifo_wr_data,
rdaddress => rdaddress,
rdclken => module_input,
reset_n => reset_n,
wraddress => wraddress,
wrclock => clk,
wren => fifo_write
);
module_input <= std_logic'('1');
--vhdl renameroo for output signals
fifo_empty <= internal_fifo_empty;
--vhdl renameroo for output signals
fifo_full <= internal_fifo_full;
--vhdl renameroo for output signals
p1_fifo_empty <= internal_p1_fifo_empty;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
--
--Burst adapter parameters:
--adapter is mastered by: powerlink_0/MAC_DMA
--adapter masters: SRAM_0/avalon_tristate_slave
--asp_debug: 0
--byteaddr_width: 23
--ceil_data_width: 32
--data_width: 32
--dbs_shift: -1
--dbs_upstream_burstcount_width: 3
--downstream_addr_shift: 2
--downstream_burstcount_width: 1
--downstream_max_burstcount: 1
--downstream_pipeline: 0
--dynamic_slave: 1
--master_always_burst_max_burst: 0
--master_burst_on_burst_boundaries_only: 0
--master_data_width: 16
--master_interleave: 0
--master_linewrap_bursts: 0
--nativeaddr_width: 21
--slave_always_burst_max_burst: 0
--slave_burst_on_burst_boundaries_only: 0
--slave_interleave: 0
--slave_linewrap_bursts: 0
--upstream_burstcount: upstream_burstcount
--upstream_burstcount_width: 3
--upstream_max_burstcount: 4
--zero_address_width: 0
entity niosII_openMac_burst_0 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal downstream_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal downstream_readdatavalid : IN STD_LOGIC;
signal downstream_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal upstream_address : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
signal upstream_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal upstream_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal upstream_debugaccess : IN STD_LOGIC;
signal upstream_nativeaddress : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
signal upstream_read : IN STD_LOGIC;
signal upstream_write : IN STD_LOGIC;
signal upstream_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal downstream_address : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
signal downstream_arbitrationshare : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal downstream_burstcount : OUT STD_LOGIC;
signal downstream_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal downstream_debugaccess : OUT STD_LOGIC;
signal downstream_nativeaddress : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
signal downstream_read : OUT STD_LOGIC;
signal downstream_write : OUT STD_LOGIC;
signal downstream_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal upstream_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal upstream_readdatavalid : OUT STD_LOGIC;
signal upstream_waitrequest : OUT STD_LOGIC
);
end entity niosII_openMac_burst_0;
architecture europa of niosII_openMac_burst_0 is
component niosII_openMac_burst_0_fifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal fifo_read : IN STD_LOGIC;
signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : IN STD_LOGIC;
signal flush_fifo : IN STD_LOGIC;
signal inc_pending_data : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal fifo_datavalid : OUT STD_LOGIC;
signal fifo_empty : OUT STD_LOGIC;
signal fifo_full : OUT STD_LOGIC;
signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal p1_fifo_empty : OUT STD_LOGIC
);
end component niosII_openMac_burst_0_fifo_module;
signal address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal atomic_counter : STD_LOGIC;
signal current_upstream_address : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal current_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal current_upstream_read : STD_LOGIC;
signal current_upstream_write : STD_LOGIC;
signal data_counter : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal downstream_address_base : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal downstream_burstdone : STD_LOGIC;
signal enable_state_change : STD_LOGIC;
signal fifo_datavalid : STD_LOGIC;
signal fifo_empty : STD_LOGIC;
signal fifo_full : STD_LOGIC;
signal fifo_rd_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_read : STD_LOGIC;
signal fifo_wr_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : STD_LOGIC;
signal flush_fifo : STD_LOGIC;
signal full_width_rdv_counter : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal internal_downstream_burstcount : STD_LOGIC;
signal internal_downstream_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_downstream_read : STD_LOGIC;
signal internal_downstream_write : STD_LOGIC;
signal internal_upstream_readdatavalid : STD_LOGIC;
signal internal_upstream_waitrequest : STD_LOGIC;
signal max_burst_size : STD_LOGIC;
signal module_input1 : STD_LOGIC;
signal negative_dbs_rdv_counter : STD_LOGIC;
signal negative_dbs_read_expression : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal p1_atomic_counter : STD_LOGIC;
signal p1_fifo_empty : STD_LOGIC;
signal p1_state_busy : STD_LOGIC;
signal p1_state_idle : STD_LOGIC;
signal pending_register_enable : STD_LOGIC;
signal pending_upstream_read : STD_LOGIC;
signal pending_upstream_read_reg : STD_LOGIC;
signal pending_upstream_write : STD_LOGIC;
signal pending_upstream_write_reg : STD_LOGIC;
signal quantized_burst_base : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal quantized_burst_limit : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal read_address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal read_update_count : STD_LOGIC;
signal read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_upstream_address : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal registered_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_upstream_nativeaddress : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal registered_upstream_read : STD_LOGIC;
signal registered_upstream_write : STD_LOGIC;
signal state_busy : STD_LOGIC;
signal state_idle : STD_LOGIC;
signal sync_nativeaddress : STD_LOGIC;
signal transactions_remaining : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal transactions_remaining_reg : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal update_count : STD_LOGIC;
signal upstream_burstdone : STD_LOGIC;
signal upstream_read_run : STD_LOGIC;
signal upstream_write_run : STD_LOGIC;
signal write_address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal write_update_count : STD_LOGIC;
begin
sync_nativeaddress <= or_reduce(upstream_nativeaddress);
--downstream, which is an e_avalon_master
--upstream, which is an e_avalon_slave
upstream_burstdone <= A_WE_StdLogic((std_logic'(current_upstream_read) = '1'), ((to_std_logic(((transactions_remaining = (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND internal_downstream_read) AND NOT downstream_waitrequest), ((to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (transactions_remaining)) = (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + std_logic_vector'("000000000000000000000000000000001")))))) AND internal_downstream_write) AND NOT downstream_waitrequest));
p1_atomic_counter <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + (std_logic_vector'("0") & ((A_WE_StdLogicVector((std_logic'(internal_downstream_read) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))), std_logic_vector'("00000000000000000000000000000001")))))));
downstream_burstdone <= (((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest) AND to_std_logic(((std_logic'(p1_atomic_counter) = std_logic'(internal_downstream_burstcount))));
quantized_burst_base <= A_EXT (((std_logic_vector'("000000000") & (upstream_address)) AND NOT std_logic_vector'("00000000000000000000000000000011")), 23);
quantized_burst_limit <= A_EXT (((std_logic_vector'("0") & ((((((std_logic_vector'("0") & (((std_logic_vector'("0") & ((((std_logic_vector'("000000000") & (upstream_address)) AND NOT std_logic_vector'("00000000000000000000000000000001"))))) + (std_logic_vector'("00000000000000000000000000000") & ((upstream_burstcount & A_ToStdLogicVector(std_logic'('0')))))))) - std_logic_vector'("0000000000000000000000000000000001"))) OR std_logic_vector'("0000000000000000000000000000000011"))))) + std_logic_vector'("00000000000000000000000000000000001")), 23);
negative_dbs_read_expression <= A_EXT (A_SRL((((std_logic_vector'("0") & (quantized_burst_limit)) - (std_logic_vector'("0") & (quantized_burst_base)))),std_logic_vector'("00000000000000000000000000000010")), 3);
dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), read_write_dbs_adjusted_upstream_burstcount, registered_read_write_dbs_adjusted_upstream_burstcount);
read_write_dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(upstream_read) = '1'), negative_dbs_read_expression, upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
registered_read_write_dbs_adjusted_upstream_burstcount <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_read_write_dbs_adjusted_upstream_burstcount <= read_write_dbs_adjusted_upstream_burstcount;
end if;
end if;
end process;
p1_state_idle <= ((state_idle AND NOT upstream_read) AND NOT upstream_write) OR ((((state_busy AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000"))))) AND p1_fifo_empty) AND NOT pending_upstream_read) AND NOT pending_upstream_write);
p1_state_busy <= (state_idle AND ((upstream_read OR upstream_write))) OR (state_busy AND ((((to_std_logic(NOT (((std_logic_vector'("00000000000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000")))) OR NOT p1_fifo_empty) OR pending_upstream_read) OR pending_upstream_write)));
enable_state_change <= NOT ((internal_downstream_read OR internal_downstream_write)) OR NOT downstream_waitrequest;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_read_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((upstream_read AND state_idle)) = '1' then
pending_upstream_read_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(downstream_readdatavalid) = '1' then
pending_upstream_read_reg <= std_logic'('0');
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_write_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(upstream_burstdone) = '1' then
pending_upstream_write_reg <= std_logic'('0');
elsif std_logic'((upstream_write AND ((state_idle OR NOT internal_upstream_waitrequest)))) = '1' then
pending_upstream_write_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_idle <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_idle <= p1_state_idle;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_busy <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_busy <= p1_state_busy;
end if;
end if;
end process;
pending_upstream_read <= pending_upstream_read_reg;
pending_upstream_write <= pending_upstream_write_reg AND NOT upstream_burstdone;
pending_register_enable <= state_idle OR ((((upstream_read OR upstream_write)) AND NOT internal_upstream_waitrequest));
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_read <= upstream_read;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_write <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_write <= upstream_write;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_burstcount <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_burstcount <= upstream_burstcount;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_address <= std_logic_vector'("00000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_address <= upstream_address;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_nativeaddress <= std_logic_vector'("000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_nativeaddress <= upstream_nativeaddress;
end if;
end if;
end process;
current_upstream_read <= registered_upstream_read AND NOT(internal_downstream_write);
current_upstream_write <= registered_upstream_write;
current_upstream_address <= registered_upstream_address;
current_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), upstream_burstcount, registered_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
atomic_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest)) = '1' then
atomic_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(downstream_burstdone) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_atomic_counter)))));
end if;
end if;
end process;
read_update_count <= current_upstream_read AND NOT downstream_waitrequest;
write_update_count <= (current_upstream_write AND internal_downstream_write) AND downstream_burstdone;
update_count <= read_update_count OR write_update_count;
transactions_remaining <= A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), dbs_adjusted_upstream_burstcount, transactions_remaining_reg);
process (clk, reset_n)
begin
if reset_n = '0' then
transactions_remaining_reg <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
transactions_remaining_reg <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), (std_logic_vector'("0") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(update_count) = '1'), ((std_logic_vector'("0") & (transactions_remaining_reg)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (transactions_remaining_reg)))), 3);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
data_counter <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
data_counter <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(downstream_readdatavalid) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (data_counter)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (data_counter)))), 3);
end if;
end process;
max_burst_size <= std_logic'('1');
internal_downstream_burstcount <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (std_logic_vector'("00000000000000000000000000000") & ((A_WE_StdLogicVector(((transactions_remaining>(std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(max_burst_size))))), (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(max_burst_size))), transactions_remaining)))), std_logic_vector'("00000000000000000000000000000001")));
downstream_arbitrationshare <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (dbs_adjusted_upstream_burstcount), dbs_adjusted_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
write_address_offset <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
write_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((internal_downstream_write AND NOT downstream_waitrequest) AND downstream_burstdone) AND or_reduce(internal_downstream_byteenable(3 DOWNTO 2))))) = '1'), ((std_logic_vector'("0") & (write_address_offset)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (write_address_offset)))))), 2);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
read_address_offset <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
read_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((internal_downstream_read AND NOT downstream_waitrequest))) = '1'), ((std_logic_vector'("0") & (read_address_offset)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (read_address_offset)))))), 2);
end if;
end process;
downstream_nativeaddress <= A_SRL(registered_upstream_nativeaddress,std_logic_vector'("00000000000000000000000000000001"));
address_offset <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), read_address_offset, write_address_offset);
downstream_address_base <= current_upstream_address;
downstream_address <= A_EXT (((std_logic_vector'("0") & (downstream_address_base)) + (std_logic_vector'("00000000000000000000") & ((address_offset & std_logic_vector'("00"))))), 21);
process (clk, reset_n)
begin
if reset_n = '0' then
internal_downstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((NOT internal_downstream_read OR NOT downstream_waitrequest)) = '1' then
internal_downstream_read <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector(((transactions_remaining = (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))))), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_read))))));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
negative_dbs_rdv_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
negative_dbs_rdv_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest))) = '1'), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(upstream_address(1)))), A_WE_StdLogicVector((std_logic'(fifo_datavalid) = '1'), ((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))) + std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))))));
end if;
end process;
fifo_read <= NOT fifo_empty AND to_std_logic((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))) = std_logic_vector'("00000000000000000000000000000001"))) OR (((((std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)) + std_logic_vector'("000000000000000000000000000000001"))) = (std_logic_vector'("000000000000000000000000000000") & (current_upstream_burstcount)))))));
fifo_write <= downstream_readdatavalid;
fifo_wr_data <= downstream_readdata;
flush_fifo <= std_logic'('0');
--the_niosII_openMac_burst_0_fifo_module, which is an e_instance
the_niosII_openMac_burst_0_fifo_module : niosII_openMac_burst_0_fifo_module
port map(
fifo_datavalid => fifo_datavalid,
fifo_empty => fifo_empty,
fifo_full => fifo_full,
fifo_rd_data => fifo_rd_data,
p1_fifo_empty => p1_fifo_empty,
clk => clk,
clk_en => module_input1,
fifo_read => fifo_read,
fifo_wr_data => fifo_wr_data,
fifo_write => fifo_write,
flush_fifo => flush_fifo,
inc_pending_data => fifo_write,
reset_n => reset_n
);
module_input1 <= std_logic'('1');
process (clk, reset_n)
begin
if reset_n = '0' then
full_width_rdv_counter <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
full_width_rdv_counter <= A_EXT (A_WE_StdLogicVector((std_logic'((((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest))) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(internal_upstream_readdatavalid) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)) + std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)))), 3);
end if;
end process;
internal_upstream_readdatavalid <= fifo_datavalid;
upstream_readdata <= A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000") = (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))))), Std_Logic_Vector'(fifo_rd_data(15 DOWNTO 0) & fifo_rd_data(15 DOWNTO 0)), Std_Logic_Vector'(fifo_rd_data(31 DOWNTO 16) & fifo_rd_data(31 DOWNTO 16)));
internal_downstream_byteenable <= upstream_byteenable;
internal_downstream_write <= ((upstream_write AND state_busy) AND NOT(pending_upstream_read)) AND fifo_empty;
downstream_writedata <= upstream_writedata;
upstream_read_run <= state_idle AND upstream_read;
upstream_write_run <= ((state_busy AND upstream_write) AND NOT downstream_waitrequest) AND NOT(internal_downstream_read);
internal_upstream_waitrequest <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((upstream_read OR current_upstream_read))) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_read_run))), A_WE_StdLogicVector((std_logic'(current_upstream_write) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_write_run))), std_logic_vector'("00000000000000000000000000000001"))));
downstream_debugaccess <= upstream_debugaccess;
--vhdl renameroo for output signals
downstream_burstcount <= internal_downstream_burstcount;
--vhdl renameroo for output signals
downstream_byteenable <= internal_downstream_byteenable;
--vhdl renameroo for output signals
downstream_read <= internal_downstream_read;
--vhdl renameroo for output signals
downstream_write <= internal_downstream_write;
--vhdl renameroo for output signals
upstream_readdatavalid <= internal_upstream_readdatavalid;
--vhdl renameroo for output signals
upstream_waitrequest <= internal_upstream_waitrequest;
--synthesis translate_off
process (clk)
VARIABLE write_line : line;
begin
if clk'event and clk = '1' then
if std_logic'((fifo_full AND fifo_write)) = '1' then
write(write_line, now);
write(write_line, string'(": "));
write(write_line, string'("simulation assertion failed: niosII_openMac_burst_0: illegal write into full fifo."));
write(output, write_line.all);
deallocate (write_line);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
| gpl-2.0 |
bert/geda-gaf | gnetlist/examples/vams/vhdl/new-vhdl/resistor.vhdl | 15 | 299 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 10000.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
| gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd | 2 | 10212 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Sample client for loading an image to asynchronous SRAM
--
-- $Id: ram_loader.vhd,v 1.2 2005/04/10 17:17:23 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ram_loader is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
lamp_o : out std_logic;
-- Config Interface -------------------------------------------------------
cfg_clk_i : in std_logic;
cfg_data_i : in std_logic;
start_o : out std_logic;
mode_o : out std_logic;
done_o : out std_logic;
detached_i : in std_logic;
-- Asynchronous RAM Interface ---------------------------------------------
ram_addr_o : out std_logic_vector(15 downto 0);
ram_data_b : out std_logic_vector( 7 downto 0);
ram_ce_no : out std_logic_vector( 3 downto 0);
ram_oe_no : out std_logic;
ram_we_no : out std_logic
);
end ram_loader;
library ieee;
use ieee.numeric_std.all;
architecture rtl of ram_loader is
signal addr_q : unsigned(17 downto 0);
signal inc_addr_s : boolean;
signal shift_dat_q : std_logic_vector(7 downto 0);
signal ser_dat_q : std_logic_vector(7 downto 0);
signal bit_q : unsigned(2 downto 0);
signal bit_ovfl_q : boolean;
type fsm_t is (IDLE,
WE_ON,
WE_OFF,
INC_ADDR1, INC_ADDR2,
FINISHED);
signal fsm_s,
fsm_q : fsm_t;
signal done_q : std_logic;
signal done_s : boolean;
signal mode_q,
mode_s : std_logic;
signal ram_we_n_q,
ram_we_n_s : std_logic;
signal ram_ce_n_q,
ram_ce_n_s : std_logic_vector(3 downto 0);
type start_fsm_t is (WAIT_DETACH,
CHECK_NO_DONE,
WAIT_DONE);
signal start_fsm_s,
start_fsm_q : start_fsm_t;
signal start_s,
start_q : std_logic;
signal enable_s,
enable_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements clocked with cfg_clk_i.
--
seq: process (cfg_clk_i, reset_i)
begin
if reset_i = '0' then
addr_q <= (others => '0');
shift_dat_q <= (others => '0');
ser_dat_q <= (others => '0');
bit_q <= (others => '0');
bit_ovfl_q <= false;
fsm_q <= IDLE;
ram_we_n_q <= '1';
ram_ce_n_q <= (others => '1');
done_q <= '0';
mode_q <= '0';
elsif cfg_clk_i'event and cfg_clk_i = '1' then
if inc_addr_s then
addr_q <= addr_q + 1;
end if;
if enable_q then
bit_q <= bit_q + 1;
bit_ovfl_q <= bit_q = 7;
shift_dat_q(0) <= cfg_data_i;
shift_dat_q(7 downto 1) <= shift_dat_q(6 downto 0);
end if;
-- update register when 8 serial bits have been shifted in
if bit_ovfl_q then
ser_dat_q <= shift_dat_q;
end if;
fsm_q <= fsm_s;
ram_we_n_q <= ram_we_n_s;
ram_ce_n_q <= ram_ce_n_s;
-- done only settable once
if done_s then
done_q <= '1';
end if;
mode_q <= mode_s;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process fsm
--
-- Purpose:
-- Implements the combinational logic of the RAM loader FSM.
--
fsm: process (fsm_q,
bit_ovfl_q,
start_q,
addr_q)
begin
-- default assignments
inc_addr_s <= false;
ram_we_n_s <= '1';
done_s <= false;
fsm_s <= IDLE;
lamp_o <= '1';
mode_s <= '0';
case fsm_q is
when IDLE =>
lamp_o <= '0';
if start_q = '1' then
if bit_ovfl_q then
fsm_s <= WE_ON;
end if;
end if;
when WE_ON =>
ram_we_n_s <= '0';
fsm_s <= WE_OFF;
when WE_OFF =>
fsm_s <= INC_ADDR1;
when INC_ADDR1 =>
fsm_s <= INC_ADDR2;
when INC_ADDR2 =>
if addr_q = "001111111111111111" then -- load only 64k
fsm_s <= FINISHED;
done_s <= true;
mode_s <= '1';
else
inc_addr_s <= true;
fsm_s <= IDLE;
end if;
when FINISHED =>
fsm_s <= FINISHED;
lamp_o <= '1';
mode_s <= '1';
when others =>
end case;
end process fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process ce_gen
--
-- Purpose:
-- Generates the four CE signals for the external RAM chips.
--
ce_gen: process (addr_q)
begin
ram_ce_n_s <= (others => '1');
ram_ce_n_s(to_integer(addr_q(17 downto 16))) <= '0';
end process ce_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process start_seq
--
-- Purpose:
-- Implements the sequential elements clocked with clk_i.
--
start_seq: process (clk_i, reset_i)
begin
if reset_i = '0' then
start_fsm_q <= WAIT_DETACH;
start_q <= '0';
enable_q <= false;
elsif clk_i'event and clk_i = '1' then
start_fsm_q <= start_fsm_s;
enable_q <= enable_s;
start_q <= start_s;
end if;
end process start_seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process start_comb
--
-- Purpose:
-- Implements the combinational logic of the start FSM.
--
start_comb: process (start_fsm_q,
detached_i,
done_q,
enable_q,
start_q)
begin
-- default assignments
start_fsm_s <= WAIT_DETACH;
enable_s <= enable_q;
start_s <= start_q;
case start_fsm_q is
-- Wait for detached_i to become '1'
-- This state is entered/left twice:
-- 1. after reset to start the data download
-- 2. after data download to start the next configuration cycle
when WAIT_DETACH =>
if detached_i = '1' then
start_fsm_s <= CHECK_NO_DONE;
enable_s <= true;
start_s <= '1';
else
start_fsm_s <= WAIT_DETACH;
end if;
-- Wait until done_q is '0'
-- This ensures that the FSM stalls when it has started the configuration
-- download. There must be no further action in this case.
when CHECK_NO_DONE =>
if done_q = '0' then
start_fsm_s <= WAIT_DONE;
else
start_fsm_s <= CHECK_NO_DONE;
end if;
-- Wait until done_q is '1'
-- done_q is the signal that the main FSM has finished its work. We
-- need to start the configuration download.
when WAIT_DONE =>
if done_q = '1' then
start_fsm_s <= WAIT_DETACH;
enable_s <= false;
start_s <= '0';
else
start_fsm_s <= WAIT_DONE;
end if;
when others =>
null;
end case;
end process start_comb;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
start_o <= start_q;
mode_o <= mode_q;
done_o <= done_q
when start_q = '1' else
'1';
ram_addr_o <= std_logic_vector(addr_q(15 downto 0));
ram_data_b <= ser_dat_q;
ram_oe_no <= '1';
ram_ce_no <= ram_ce_n_q;
ram_we_no <= ram_we_n_q;
end rtl;
| gpl-2.0 |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DPR_Xilinx.vhd | 2 | 12077 | ------------------------------------------------------------------------------------------------------------------------
-- OpenMAC - DPR for Xilinx FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 zelenkaj Converted to official version.
-- 2011-10-12 V0.10 zelenkaj Implementation is based on UG687 (v13.2)
-- 2012-03-01 V0.11 mairt added memory init for pdi dpr
------------------------------------------------------------------------------------------------------------------------
--
-- dual clocked DPRAM for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr is
generic (
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr;
architecture xilinx of dc_dpr is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with byte enables for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr_be is
generic (
gDoInit : boolean := false; -- if dpr is used in pdi init state field with invalid state
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
beA : in std_logic_vector(WIDTH/8-1 downto 0);
beB : in std_logic_vector(WIDTH/8-1 downto 0);
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr_be;
architecture xilinx of dc_dpr_be is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
function InitRam return ramType is
variable RAM : ramType := (others => (others => '0'));
begin
if gDoInit = true then
for i in ramType'range loop
RAM(i) := X"00000000";
if i = 4 then -- init state field with invalid state
RAM(i) := X"00EEFFFF";
end if;
end loop;
end if;
return RAM;
end function;
shared variable ram : ramType := InitRam;
constant BYTE : integer := 8;
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
for i in beA'range loop
if beA(i) = '1' then
ram(conv_integer(addrA))((i+1)*BYTE-1 downto i*BYTE) := diA((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
for i in beB'range loop
if beB(i) = '1' then
ram(conv_integer(addrB))((i+1)*BYTE-1 downto i*BYTE) := diB((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with 16x16 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 16,
SIZE => 2**AddrA'length,
ADDRWIDTH => AddrA'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => AddrA, addrB => AddrB,
diA => DiA, diB => DiB,
doA => DoA, doB => DoB,
weA => WeA, weB => WeB,
beA => BeA, beB => BeB
);
end struct;
-- dual clocked DPRAM with 16x32 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
signal addra_s : std_logic_vector(AddrB'range);
signal dia_s : std_logic_vector(DoB'range);
signal bea_s : std_logic_vector(DoB'length/8-1 downto 0);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
SIZE => 2**AddrB'length,
ADDRWIDTH => AddrB'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => addra_s, addrB => AddrB,
diA => dia_s, diB => (others => '0'),
doA => open, doB => DoB,
weA => weA, weB => '0',
beA => bea_s, beB => (others => '1')
);
addra_s <= AddrA(AddrA'left downto 1);
dia_s <= DiA & DiA;
bea_s(3) <= BeA(1) and AddrA(0);
bea_s(2) <= BeA(0) and AddrA(0);
bea_s(1) <= BeA(1) and not AddrA(0);
bea_s(0) <= BeA(0) and not AddrA(0);
end struct;
-- dual clocked DPRAM with 32x32 for packets --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
architecture struct of OpenMAC_DPRpackets is
signal address_a_s : std_logic_vector(address_b'range);
signal bea : std_logic_vector(byteena_b'range);
signal q_a_s, q_b_s, data_a_s : std_logic_vector(q_b'range);
signal q_a_s1 : std_logic_vector(q_a'range);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
SIZE => memSize_g/4,
ADDRWIDTH => memSizeLOG2_g-2
)
port map (
clkA => clock_a, clkB => clock_b,
enA => '1', enB => '1',
addrA => address_a_s, addrB => address_b,
diA => data_a_s, diB => data_b,
doA => q_a_s, doB => q_b_s,
weA => wren_a, weB => wren_b,
beA => bea, beB => byteena_b
);
address_a_s <= address_a(address_a'left downto 1);
bea(3) <= byteena_a(1) and address_a(0);
bea(2) <= byteena_a(0) and address_a(0);
bea(1) <= byteena_a(1) and not address_a(0);
bea(0) <= byteena_a(0) and not address_a(0);
data_a_s <= data_a & data_a;
q_a_s1 <= q_a_s(q_a'length*2-1 downto q_a'length) when address_a(0) = '1' else
q_a_s(q_a'range);
--sync outputs
process(clock_a)
begin
if rising_edge(clock_a) then
q_a <= q_a_s1;
end if;
end process;
process(clock_b)
begin
if rising_edge(clock_b) then
q_b <= q_b_s;
end if;
end process;
end struct;
| gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd | 1 | 716 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := '0';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 15;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"3ff8";
end zpu_config;
| gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd | 2 | 12848 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
--
-- $Date: 2004/02/18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhd,v $
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
| gpl-2.0 |
gauravks/i210dummy | Examples/altera_nios2/ipcore/powerlink/src/openMAC_16to32conv.vhd | 3 | 6853 | -------------------------------------------------------------------------------
--
-- Title : openMAC_16to32conv
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : openMAC_16to32conv.vhd
-- Generated : Mon Sep 12 15:35:37 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is a 32-to-16 bit converter which is necessary for e.g. Xilinx PLB.
-- The component has to be connected to openMAC_Ethernet or powerlink.
-- NOT use this directly with openMAC!
--
-------------------------------------------------------------------------------
-- 2011-09-12 V0.01 zelenkaj Initial creation
-- 2011-10-10 V0.02 zelenkaj Split bus ack into wr/rd and bug fix
-- 2012-03-21 V0.03 zelenkaj Added endian generic
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
entity openMAC_16to32conv is
generic(
gEndian : string := "little";
bus_address_width : integer := 10
);
port(
clk : in std_logic;
rst : in std_logic;
--port from 32bit bus
bus_select : in std_logic;
bus_write : in std_logic;
bus_read : in std_logic;
bus_byteenable : in std_logic_vector(3 downto 0);
bus_writedata : in std_logic_vector(31 downto 0);
bus_readdata : out std_logic_vector(31 downto 0);
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_ack_wr : out std_logic;
bus_ack_rd : out std_logic;
--port to openMAC_Ethernet
s_chipselect : out std_logic;
s_write : out std_logic;
s_read : out std_logic;
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_waitrequest : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_writedata : out std_logic_vector(15 downto 0)
);
end openMAC_16to32conv;
architecture rtl of openMAC_16to32conv is
-- types
type fsm_t is (idle, doAccess);
type bus_access_t is (none, dword, word);
-- fsm
signal fsm, fsm_next : fsm_t;
signal bus_access : bus_access_t;
-- cnt
signal cnt, cnt_next, cnt_load_val : std_logic_vector(1 downto 0);
signal cnt_load, cnt_dec, cnt_zero : std_logic;
signal bus_ack : std_logic;
-- word register
signal word_reg, word_reg_next : std_logic_vector(15 downto 0);
begin
process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
fsm <= idle;
word_reg <= (others => '0');
elsif clk = '1' and clk'event then
cnt <= cnt_next;
fsm <= fsm_next;
word_reg <= word_reg_next;
end if;
end process;
word_reg_next <= s_readdata when bus_access = dword and cnt = 2 and s_waitrequest = '0' else
word_reg;
s_chipselect <= bus_select; --not cnt_zero;
s_write <= bus_write and bus_select;
s_read <= bus_read and bus_select;
cnt_dec <= (not s_waitrequest) and bus_select;
bus_readdata <= s_readdata & word_reg when bus_access = dword else
s_readdata & s_readdata;
bus_ack <= '1' when cnt = 1 and s_waitrequest = '0' and bus_access = dword else
'1' when s_waitrequest = '0' and bus_access = word else
'0';
bus_ack_wr <= bus_ack and bus_write;
bus_ack_rd <= bus_ack and bus_read;
s_address(bus_address_width-1 downto 1) <= '0' & bus_address(bus_address_width-1 downto 2);
--word address set to +0 (little) when first dword access or word access with selected word/byte
s_address(0) <= '0' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "little" else --first word of dword access
'1' when bus_access = dword and cnt = 1 and gEndian = "little" else
'1' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "big" else
'0' when bus_access = dword and cnt = 1 and gEndian = "big" else --first word of dword access
bus_address(1);
s_byteenable <= "11" when bus_access = dword else
bus_byteenable(3 downto 2) or bus_byteenable(1 downto 0);
s_writedata <= bus_writedata(15 downto 0) when bus_access = dword and (cnt = 2 or cnt = 0) else
bus_writedata(31 downto 16) when bus_access = dword and cnt = 1 else
bus_writedata(15 downto 0) when bus_address(1) = '0' else
bus_writedata(31 downto 16); --when bus_address(1) = '1' else
--fsm
bus_access <= none when bus_select /= '1' else
dword when bus_byteenable = "1111" else
word;
fsm_next <= doAccess when fsm = idle and cnt_zero = '1' and bus_access = dword else
idle when fsm = doAccess and cnt_zero = '1' and bus_access = none else
fsm;
--if dword, access twice, otherwise (byte, word) access once
cnt_load_val <= "10" when bus_byteenable = "1111" and bus_read = '1' else "01";
cnt_load <= '1' when fsm_next = doAccess and fsm = idle else '0';
--counter
cnt_next <= cnt_load_val when cnt_load = '1' else
cnt - 1 when cnt_dec = '1' and bus_access = dword else
cnt;
cnt_zero <= '1' when cnt = 0 else '0';
end rtl;
| gpl-2.0 |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/axi_powerlink_v1_00_a/hdl/vhdl/pdi.vhd | 3 | 52824 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) for
-- POWERLINK Communication Processor (PCP): Avalon
-- Application Processor (AP): Avalon
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-06-28 V0.01 zelenkaj First version
-- 2010-08-16 V0.10 zelenkaj Added the possibility for more RPDOs
-- 2010-08-23 V0.11 zelenkaj Added IRQ generation
-- 2010-10-04 V0.12 zelenkaj Changed memory size calculation (e.g. generics must include header size)
-- 2010-10-11 V0.13 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.14 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2010-11-08 V0.15 zelenkaj Add 8 bytes to control reg of pdi mapped to dpr
-- 2010-11-23 V0.16 zelenkaj Omitted T/RPDO descriptor sections in DPR
-- Omitted "HEX Words" (e.g. DEADC0DE, C00FFEE) and replaced with ZEROS
-- 2011-03-21 V0.17 zelenkaj clean up
-- 2011-03-28 V0.20 zelenkaj Changed: Structure of Control/Status Register
-- Added: LED
-- Added: Events
-- Added/Changed: Asynchronous buffer 2x Ping-Pong
-- 2011-04-06 V0.21 zelenkaj minor fix: activity is only valid if link is present
-- 2011-04-26 V0.22 zelenkaj generic for clock domain selection
-- area optimization in Status/Control Register
-- 2011-04-28 V0.23 zelenkaj clean up to reduce Quartus II warnings
-- 2011-05-06 V0.24 zelenkaj some naming convention changes
-- 2011-05-09 V0.25 zelenkaj minor change in edge detector and syncs (reset to zero)
-- 2011-06-06 V0.26 zelenkaj status/control register enhanced by 8 bytes
-- 2011-06-10 V0.27 zelenkaj bug fix: if dpr size goes below 2**10, error of dpr address width
-- 2011-06-29 V0.28 zelenkaj bug fix: led control was gone and dpr addr width still buggy
-- 2011-07-25 V0.29 zelenkaj LED gadget and asynchronous buffer optional
-- 2011-08-08 V0.30 zelenkaj LED gadget enhancement -> added 8 general purpose outputs
-- 2011-08-16 V0.31 zelenkaj status/control register enhanced by 8 bytes (again...)
-- 2011-11-21 V0.32 zelenkaj added time synchronization feature
-- 2011-11-28 V0.33 zelenkaj added waitrequest signals
-- 2011-11-29 V0.34 zelenkaj event support is optional
-- 2011-12-20 V0.35 zelenkaj changed 2xbuf switch source to AP
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
USE work.memMap.all; --used for memory mapping (alignment, ...)
entity pdi is
generic (
genOnePdiClkDomain_g : boolean := false;
iPdiRev_g : integer := 0; --for HW/SW match verification (0..65535)
iRpdos_g : integer := 3;
iTpdos_g : integer := 1;
genABuf1_g : boolean := true; --if false iABuf1_g must be set to 0!
genABuf2_g : boolean := true; --if false iABuf2_g must be set to 0!
genLedGadget_g : boolean := false;
genTimeSync_g : boolean := false;
genEvent_g : boolean := false;
--PDO buffer size *3
iTpdoBufSize_g : integer := 100;
iRpdo0BufSize_g : integer := 116; --includes header
iRpdo1BufSize_g : integer := 116; --includes header
iRpdo2BufSize_g : integer := 116; --includes header
--asynchronous buffer size
iABuf1_g : integer := 512; --includes header
iABuf2_g : integer := 512 --includes header
);
port (
pcp_reset : in std_logic;
pcp_clk : in std_logic;
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for PCP
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_byteenable : in std_logic_vector(3 DOWNTO 0);
pcp_address : in std_logic_vector(12 DOWNTO 0);
pcp_writedata : in std_logic_vector(31 DOWNTO 0);
pcp_readdata : out std_logic_vector(31 DOWNTO 0);
pcp_waitrequest : out std_logic;
pcp_irq : in std_logic; --should be connected to the Time Cmp Toggle of openMAC!
-- Avalon Slave Interface for AP
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_byteenable : in std_logic_vector(3 DOWNTO 0);
ap_address : in std_logic_vector(12 DOWNTO 0);
ap_writedata : in std_logic_vector(31 DOWNTO 0);
ap_readdata : out std_logic_vector(31 DOWNTO 0);
ap_waitrequest : out std_logic;
ap_irq : out std_logic; --Sync Irq to the AP
-- async interrupt
ap_asyncIrq : out std_logic; --Async Irq to the Ap
-- LED
ledsOut : out std_logic_vector(15 downto 0) := (others => '0'); --LEDs: GPO7, ..., GPO0, O1, O0, PA1, PL1, PA0, PL0, E, S
phyLink : in std_logic_vector(1 downto 0); --link: phy1, phy0
phyAct : in std_logic_vector(1 downto 0); --acti: phy1, phy0
--PDI change buffer triggers
rpdo_change_tog : in std_logic_vector(2 downto 0);
tpdo_change_tog : in std_logic
);
end entity pdi;
architecture rtl of pdi is
------------------------------------------------------------------------------------------------------------------------
--types
---for pcp and ap side
type pdiSel_t is
record
pcp : std_logic;
ap : std_logic;
end record;
type pdiTrig_t is
record
pcp : std_logic_vector(3 downto 0);
ap : std_logic_vector(3 downto 0);
end record;
type pdi32Bit_t is
record
pcp : std_logic_vector(31 downto 0);
ap : std_logic_vector(31 downto 0);
end record;
------------------------------------------------------------------------------------------------------------------------
--constants
---memory mapping from outside (e.g. Avalon or SPI)
----max memory span of one space
constant extMaxOneSpan : integer := 2 * 1024; --2kB
constant extLog2MaxOneSpan : integer := integer(ceil(log2(real(extMaxOneSpan))));
----control / status register
constant extCntStReg_c : memoryMapping_t := (16#0000#, 16#98#);
----asynchronous buffers
constant extABuf1Tx_c : memoryMapping_t := (16#0800#, iABuf1_g); --header is included in generic value!
constant extABuf1Rx_c : memoryMapping_t := (16#1000#, iABuf1_g); --header is included in generic value!
constant extABuf2Tx_c : memoryMapping_t := (16#1800#, iABuf2_g); --header is included in generic value!
constant extABuf2Rx_c : memoryMapping_t := (16#2000#, iABuf2_g); --header is included in generic value!
----pdo buffer
constant extTpdoBuf_c : memoryMapping_t := (16#2800#, iTpdoBufSize_g); --header is included in generic value!
constant extRpdo0Buf_c : memoryMapping_t := (16#3000#, iRpdo0BufSize_g); --header is included in generic value!
constant extRpdo1Buf_c : memoryMapping_t := (16#3800#, iRpdo1BufSize_g); --header is included in generic value!
constant extRpdo2Buf_c : memoryMapping_t := (16#4000#, iRpdo2BufSize_g); --header is included in generic value!
---memory mapping inside the PDI's DPR
----control / status register
constant intCntStReg_c : memoryMapping_t := (16#0000#, 22 * 4); --bytes mapped to dpr (dword alignment!!!), note: 4 times a double buffer!
----asynchronous buffers
constant intABuf1Tx_c : memoryMapping_t := (intCntStReg_c.base + intCntStReg_c.span, align32(extABuf1Tx_c.span));
constant intABuf1Rx_c : memoryMapping_t := (intABuf1Tx_c.base + intABuf1Tx_c.span, align32(extABuf1Rx_c.span));
constant intABuf2Tx_c : memoryMapping_t := (intABuf1Rx_c.base + intABuf1Rx_c.span, align32(extABuf2Tx_c.span));
constant intABuf2Rx_c : memoryMapping_t := (intABuf2Tx_c.base + intABuf2Tx_c.span, align32(extABuf2Rx_c.span));
----pdo buffers (triple buffers considered!)
constant intTpdoBuf_c : memoryMapping_t := (intABuf2Rx_c.base + intABuf2Rx_c.span, align32(extTpdoBuf_c.span) *3);
constant intRpdo0Buf_c : memoryMapping_t := (intTpdoBuf_c.base + intTpdoBuf_c.span, align32(extRpdo0Buf_c.span)*3);
constant intRpdo1Buf_c : memoryMapping_t := (intRpdo0Buf_c.base + intRpdo0Buf_c.span, align32(extRpdo1Buf_c.span)*3);
constant intRpdo2Buf_c : memoryMapping_t := (intRpdo1Buf_c.base + intRpdo1Buf_c.span, align32(extRpdo2Buf_c.span)*3);
----obtain dpr size of different configurations
constant dprSize_c : integer := ( intCntStReg_c.span +
intABuf1Tx_c.span +
intABuf1Rx_c.span +
intABuf2Tx_c.span +
intABuf2Rx_c.span +
intTpdoBuf_c.span +
intRpdo0Buf_c.span +
intRpdo1Buf_c.span +
intRpdo2Buf_c.span );
constant dprAddrWidth_c : integer := integer(ceil(log2(real(dprSize_c))));
---other constants
constant magicNumber_c : integer := 16#50435000#;
constant pdiRev_c : integer := iPdiRev_g;
------------------------------------------------------------------------------------------------------------------------
--signals
---dpr
type dprSig_t is
record
addr : std_logic_vector(dprAddrWidth_c-2-1 downto 0); --double word address!
addrOff : std_logic_vector(dprAddrWidth_c-2 downto 0); --double word address!
be : std_logic_vector(3 downto 0);
din : std_logic_vector(31 downto 0);
wr : std_logic;
end record;
type dprPdi_t is
record
pcp : dprSig_t;
ap : dprSig_t;
end record;
----signals to the DPR
signal dpr : dprPdi_t;
signal dprOut : pdi32Bit_t;
----control / status register
signal dprCntStReg_s : dprPdi_t;
----asynchronous buffers
signal dprABuf1Tx_s : dprPdi_t;
signal dprABuf1Rx_s : dprPdi_t;
signal dprABuf2Tx_s : dprPdi_t;
signal dprABuf2Rx_s : dprPdi_t;
----pdo buffers (triple buffers considered!)
signal dprTpdoBuf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'),
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'));
signal dprRpdo0Buf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'),
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'));
signal dprRpdo1Buf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'),
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'));
signal dprRpdo2Buf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'),
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'));
---chip select
----control / status register
signal selCntStReg_s : pdiSel_t;
----asynchronous buffers
signal selABuf1Tx_s : pdiSel_t;
signal selABuf1Rx_s : pdiSel_t;
signal selABuf2Tx_s : pdiSel_t;
signal selABuf2Rx_s : pdiSel_t;
----pdo buffers (triple buffers considered!)
signal selTpdoBuf_s : pdiSel_t;
signal selRpdo0Buf_s : pdiSel_t;
signal selRpdo1Buf_s : pdiSel_t;
signal selRpdo2Buf_s : pdiSel_t;
---data output
----control / status register
signal outCntStReg_s : pdi32Bit_t;
----asynchronous buffers
signal outABuf1Tx_s : pdi32Bit_t;
signal outABuf1Rx_s : pdi32Bit_t;
signal outABuf2Tx_s : pdi32Bit_t;
signal outABuf2Rx_s : pdi32Bit_t;
----pdo buffers (triple buffers considered!)
signal outTpdoBuf_s : pdi32Bit_t := ((others => '0'), (others => '0'));
signal outRpdo0Buf_s : pdi32Bit_t := ((others => '0'), (others => '0'));
signal outRpdo1Buf_s : pdi32Bit_t := ((others => '0'), (others => '0'));
signal outRpdo2Buf_s : pdi32Bit_t := ((others => '0'), (others => '0'));
---virtual buffer control/state
signal vBufTriggerPdo_s : pdiTrig_t; --tpdo, rpdo2, rpdo1, rpdo0
signal vBufSel_s : pdi32Bit_t := ((others => '1'), (others => '1')); --TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK
---ap irq generation
signal apIrqValue : std_logic_vector(31 downto 0);
signal apIrqControlPcp,
apIrqControlPcp2,
apIrqControlApOut,
apIrqControlApIn : std_logic_vector(15 downto 0);
signal ap_irq_s : std_logic;
---address calulation result
signal pcp_addrRes : std_logic_vector(dprAddrWidth_c-2 downto 0);
signal ap_addrRes : std_logic_vector(dprAddrWidth_c-2 downto 0);
---EVENT stuff
signal pcp_eventSet_s, --pulse to set event
pcp_eventRead : std_logic_vector(15 downto 0);
signal ap_eventAck_p, --pulse to ack event
ap_eventAck : std_logic_vector(15 downto 0);
signal asyncIrqCtrlOut_s,
asyncIrqCtrlIn_s : std_logic_vector(15 downto 0);
signal ap_asyncIrq_s : std_logic; --Async Irq to the Ap
signal phyLink_s,
phyLinkEvent : std_logic_vector(phyLink'range);
--LED stuff
signal pcp_ledForce_s,
pcp_ledSet_s : std_logic_vector(15 downto 0) := (others => '0');
signal ap_ledForce_s,
ap_ledSet_s : std_logic_vector(15 downto 0) := (others => '0');
signal hw_ledForce_s,
hw_ledSet_s : std_logic_vector(15 downto 0) := (others => '0');
--TIME SYNCHRONIZATION
signal pcp_timeSyncDBufSel : std_logic;
signal ap_timeSyncDBufSel : std_logic;
begin
ASSERT NOT(iRpdos_g < 1 or iRpdos_g > 3)
REPORT "Only 1, 2 or 3 Rpdos are supported!"
severity failure;
ASSERT NOT(iTpdos_g /= 1)
REPORT "Only 1 Tpdo is supported!"
severity failure;
------------------------------------------------------------------------------------------------------------------------
-- merge data to pcp/ap
theMerger : block
begin
pcp_readdata <= outCntStReg_s.pcp when selCntStReg_s.pcp = '1' else
outABuf1Tx_s.pcp when selABuf1Tx_s.pcp = '1' else
outABuf1Rx_s.pcp when selABuf1Rx_s.pcp = '1' else
outABuf2Tx_s.pcp when selABuf2Tx_s.pcp = '1' else
outABuf2Rx_s.pcp when selABuf2Rx_s.pcp = '1' else
outTpdoBuf_s.pcp when selTpdoBuf_s.pcp = '1' else
outRpdo0Buf_s.pcp when selRpdo0Buf_s.pcp = '1' else
outRpdo1Buf_s.pcp when selRpdo1Buf_s.pcp = '1' else
outRpdo2Buf_s.pcp when selRpdo2Buf_s.pcp = '1' else
(others => '0');
ap_readdata <= outCntStReg_s.ap when selCntStReg_s.ap = '1' else
outABuf1Tx_s.ap when selABuf1Tx_s.ap = '1' else
outABuf1Rx_s.ap when selABuf1Rx_s.ap = '1' else
outABuf2Tx_s.ap when selABuf2Tx_s.ap = '1' else
outABuf2Rx_s.ap when selABuf2Rx_s.ap = '1' else
outTpdoBuf_s.ap when selTpdoBuf_s.ap = '1' else
outRpdo0Buf_s.ap when selRpdo0Buf_s.ap = '1' else
outRpdo1Buf_s.ap when selRpdo1Buf_s.ap = '1' else
outRpdo2Buf_s.ap when selRpdo2Buf_s.ap = '1' else
(others => '0');
end block;
--
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- dual ported RAM
theDpr : entity work.pdi_dpr
generic map (
NUM_WORDS => (dprSize_c/4),
LOG2_NUM_WORDS => dprAddrWidth_c-2
)
port map (
address_a => pcp_addrRes(dprAddrWidth_c-2-1 downto 0),
address_b => ap_addrRes(dprAddrWidth_c-2-1 downto 0),
byteena_a => dpr.pcp.be,
byteena_b => dpr.ap.be,
clock_a => pcp_clk,
clock_b => ap_clk,
data_a => dpr.pcp.din,
data_b => dpr.ap.din,
wren_a => dpr.pcp.wr,
wren_b => dpr.ap.wr,
q_a => dprOut.pcp,
q_b => dprOut.ap
);
pcp_addrRes <= '0' & pcp_address(dprAddrWidth_c-2-1 downto 0) + dpr.pcp.addrOff;
dpr.pcp <= dprCntStReg_s.pcp when selCntStReg_s.pcp = '1' else
dprABuf1Tx_s.pcp when selABuf1Tx_s.pcp = '1' else
dprABuf1Rx_s.pcp when selABuf1Rx_s.pcp = '1' else
dprABuf2Tx_s.pcp when selABuf2Tx_s.pcp = '1' else
dprABuf2Rx_s.pcp when selABuf2Rx_s.pcp = '1' else
dprTpdoBuf_s.pcp when selTpdoBuf_s.pcp = '1' else
dprRpdo0Buf_s.pcp when selRpdo0Buf_s.pcp = '1' and iRpdos_g >= 1 else
dprRpdo1Buf_s.pcp when selRpdo1Buf_s.pcp = '1' and iRpdos_g >= 2 else
dprRpdo2Buf_s.pcp when selRpdo2Buf_s.pcp = '1' and iRpdos_g >= 3 else
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0');
ap_addrRes <= '0' & ap_address(dprAddrWidth_c-2-1 downto 0) + dpr.ap.addrOff;
dpr.ap <= dprCntStReg_s.ap when selCntStReg_s.ap = '1' else
dprABuf1Tx_s.ap when selABuf1Tx_s.ap = '1' else
dprABuf1Rx_s.ap when selABuf1Rx_s.ap = '1' else
dprABuf2Tx_s.ap when selABuf2Tx_s.ap = '1' else
dprABuf2Rx_s.ap when selABuf2Rx_s.ap = '1' else
dprTpdoBuf_s.ap when selTpdoBuf_s.ap = '1' else
dprRpdo0Buf_s.ap when selRpdo0Buf_s.ap = '1' and iRpdos_g >= 1 else
dprRpdo1Buf_s.ap when selRpdo1Buf_s.ap = '1' and iRpdos_g >= 2 else
dprRpdo2Buf_s.ap when selRpdo2Buf_s.ap = '1' and iRpdos_g >= 3 else
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0');
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- address decoder to generate select signals for different memory ranges
theAddressDecoder : block
begin
--pcp side
---control / status register
selCntStReg_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extCntStReg_c.base and
(conv_integer(pcp_address)*4 < extCntStReg_c.base + extCntStReg_c.span))
else '0';
---asynchronous buffers
selABuf1Tx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf1Tx_c.base and
(conv_integer(pcp_address)*4 < extABuf1Tx_c.base + extABuf1Tx_c.span))
else '0';
selABuf1Rx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf1Rx_c.base and
(conv_integer(pcp_address)*4 < extABuf1Rx_c.base + extABuf1Rx_c.span))
else '0';
selABuf2Tx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf2Tx_c.base and
(conv_integer(pcp_address)*4 < extABuf2Tx_c.base + extABuf2Tx_c.span))
else '0';
selABuf2Rx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf2Rx_c.base and
(conv_integer(pcp_address)*4 < extABuf2Rx_c.base + extABuf2Rx_c.span))
else '0';
---pdo buffers (triple buffers considered!)
selTpdoBuf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extTpdoBuf_c.base and
(conv_integer(pcp_address)*4 < extTpdoBuf_c.base + extTpdoBuf_c.span))
else '0';
selRpdo0Buf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extRpdo0Buf_c.base and
(conv_integer(pcp_address)*4 < extRpdo0Buf_c.base + extRpdo0Buf_c.span))
else '0';
selRpdo1Buf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extRpdo1Buf_c.base and
(conv_integer(pcp_address)*4 < extRpdo1Buf_c.base + extRpdo1Buf_c.span))
else '0';
selRpdo2Buf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extRpdo2Buf_c.base and
(conv_integer(pcp_address)*4 < extRpdo2Buf_c.base + extRpdo2Buf_c.span))
else '0';
--ap side
---control / status register
selCntStReg_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extCntStReg_c.base and
(conv_integer(ap_address)*4 < extCntStReg_c.base + extCntStReg_c.span))
else '0';
---asynchronous buffers
selABuf1Tx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf1Tx_c.base and
(conv_integer(ap_address)*4 < extABuf1Tx_c.base + extABuf1Tx_c.span))
else '0';
selABuf1Rx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf1Rx_c.base and
(conv_integer(ap_address)*4 < extABuf1Rx_c.base + extABuf1Rx_c.span))
else '0';
selABuf2Tx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf2Tx_c.base and
(conv_integer(ap_address)*4 < extABuf2Tx_c.base + extABuf2Tx_c.span))
else '0';
selABuf2Rx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf2Rx_c.base and
(conv_integer(ap_address)*4 < extABuf2Rx_c.base + extABuf2Rx_c.span))
else '0';
---pdo buffers (triple buffers considered!)
selTpdoBuf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extTpdoBuf_c.base and
(conv_integer(ap_address)*4 < extTpdoBuf_c.base + extTpdoBuf_c.span))
else '0';
selRpdo0Buf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extRpdo0Buf_c.base and
(conv_integer(ap_address)*4 < extRpdo0Buf_c.base + extRpdo0Buf_c.span))
else '0';
selRpdo1Buf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extRpdo1Buf_c.base and
(conv_integer(ap_address)*4 < extRpdo1Buf_c.base + extRpdo1Buf_c.span))
else '0';
selRpdo2Buf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extRpdo2Buf_c.base and
(conv_integer(ap_address)*4 < extRpdo2Buf_c.base + extRpdo2Buf_c.span))
else '0';
end block theAddressDecoder;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- control / status register
theCntrlStatReg4Pcp : entity work.pdiControlStatusReg
generic map (
bIsPcp => true,
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseDpr_g => 16#8#/4, --base address of content to be mapped to dpr
iSpanDpr_g => intCntStReg_c.span/4, --size of content to be mapped to dpr
iBaseMap2_g => intCntStReg_c.base/4, --base address in dpr
iDprAddrWidth_g => dprCntStReg_s.pcp.addr'length,
iRpdos_g => iRpdos_g,
genLedGadget_g => genLedGadget_g,
genTimeSync_g => genTimeSync_g,
genEvent_g => genEvent_g,
--register content
---constant values
magicNumber => conv_std_logic_vector(magicNumber_c, 32),
pdiRev => conv_std_logic_vector(pdiRev_c, 16),
tPdoBuffer => conv_std_logic_vector(extTpdoBuf_c.base, 16) &
conv_std_logic_vector(extTpdoBuf_c.span, 16),
rPdo0Buffer => conv_std_logic_vector(extRpdo0Buf_c.base, 16) &
conv_std_logic_vector(extRpdo0Buf_c.span, 16),
rPdo1Buffer => conv_std_logic_vector(extRpdo1Buf_c.base, 16) &
conv_std_logic_vector(extRpdo1Buf_c.span, 16),
rPdo2Buffer => conv_std_logic_vector(extRpdo2Buf_c.base, 16) &
conv_std_logic_vector(extRpdo2Buf_c.span, 16),
asyncBuffer1Tx => conv_std_logic_vector(extABuf1Tx_c.base, 16) &
conv_std_logic_vector(extABuf1Tx_c.span, 16),
asyncBuffer1Rx => conv_std_logic_vector(extABuf1Rx_c.base, 16) &
conv_std_logic_vector(extABuf1Rx_c.span, 16),
asyncBuffer2Tx => conv_std_logic_vector(extABuf2Tx_c.base, 16) &
conv_std_logic_vector(extABuf2Tx_c.span, 16),
asyncBuffer2Rx => conv_std_logic_vector(extABuf2Rx_c.base, 16) &
conv_std_logic_vector(extABuf2Rx_c.span, 16)
)
port map (
--memory mapped interface
clk => pcp_clk,
rst => pcp_reset,
sel => selCntStReg_s.pcp,
wr => pcp_write,
rd => pcp_read,
addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0),
be => pcp_byteenable,
din => pcp_writedata,
dout => outCntStReg_s.pcp,
--register content
---virtual buffer control signals
pdoVirtualBufferSel => vBufSel_s.pcp,
tPdoTrigger => vBufTriggerPdo_s.pcp(3),
rPdoTrigger => vBufTriggerPdo_s.pcp(2 downto 0),
---event registers
eventAckIn => pcp_eventRead,
eventAckOut => pcp_eventSet_s,
---async irq (by event)
asyncIrqCtrlIn => (others => '0'), --not for pcp
asyncIrqCtrlOut => open, --not for pcp
---led stuff
ledCnfgIn => pcp_ledForce_s,
ledCnfgOut => pcp_ledForce_s,
ledCtrlIn => pcp_ledSet_s,
ledCtrlOut => pcp_ledSet_s,
---time synchronization
doubleBufSel_out => open, --PCP is the sink
doubleBufSel_in => pcp_timeSyncDBufSel,
timeSyncIrq => '0', --pcp is not interested
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprCntStReg_s.pcp.addrOff,
dprDin => dprCntStReg_s.pcp.din,
dprDout => dprOut.pcp,
dprBe => dprCntStReg_s.pcp.be,
dprWr => dprCntStReg_s.pcp.wr,
--ap irq generation
apIrqControlOut => apIrqControlPcp,
--SW is blind, thus, use the transferred enable signal from AP!
apIrqControlIn => apIrqControlPcp2,
--hw acc triggering
rpdo_change_tog => rpdo_change_tog,
tpdo_change_tog => tpdo_change_tog
);
--only read 15 bits of the written, the msbit is read from transferred AP bit
apIrqControlPcp2(14 downto 0) <= apIrqControlPcp(14 downto 0);
--transfer the AP's enable signal to PCP, since SW is blind... :)
syncApEnable2Pcp : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => apIrqControlApOut(15),
dout => apIrqControlPcp2(15),
clk => pcp_clk,
rst => pcp_reset
);
--sync double buffer select for time sync to AP if the feature is enabled
-- note: signal toggles on PCP side when NETTIME [seconds] is written
syncDBuf_TimeSync : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
dout => pcp_timeSyncDBufSel,
din => ap_timeSyncDBufSel,
clk => pcp_clk,
rst => pcp_reset
);
theCntrlStatReg4Ap : entity work.pdiControlStatusReg
generic map (
bIsPcp => false,
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseDpr_g => 16#8#/4, --base address of content to be mapped to dpr
iSpanDpr_g => intCntStReg_c.span/4, --size of content to be mapped to dpr
iBaseMap2_g => intCntStReg_c.base/4, --base address in dpr
iDprAddrWidth_g => dprCntStReg_s.ap.addr'length,
iRpdos_g => iRpdos_g,
genLedGadget_g => genLedGadget_g,
genTimeSync_g => genTimeSync_g,
genEvent_g => genEvent_g,
--register content
---constant values
magicNumber => conv_std_logic_vector(magicNumber_c, 32),
pdiRev => conv_std_logic_vector(pdiRev_c, 16),
tPdoBuffer => conv_std_logic_vector(extTpdoBuf_c.base, 16) &
conv_std_logic_vector(extTpdoBuf_c.span, 16),
rPdo0Buffer => conv_std_logic_vector(extRpdo0Buf_c.base, 16) &
conv_std_logic_vector(extRpdo0Buf_c.span, 16),
rPdo1Buffer => conv_std_logic_vector(extRpdo1Buf_c.base, 16) &
conv_std_logic_vector(extRpdo1Buf_c.span, 16),
rPdo2Buffer => conv_std_logic_vector(extRpdo2Buf_c.base, 16) &
conv_std_logic_vector(extRpdo2Buf_c.span, 16),
asyncBuffer1Tx => conv_std_logic_vector(extABuf1Tx_c.base, 16) &
conv_std_logic_vector(extABuf1Tx_c.span, 16),
asyncBuffer1Rx => conv_std_logic_vector(extABuf1Rx_c.base, 16) &
conv_std_logic_vector(extABuf1Rx_c.span, 16),
asyncBuffer2Tx => conv_std_logic_vector(extABuf2Tx_c.base, 16) &
conv_std_logic_vector(extABuf2Tx_c.span, 16),
asyncBuffer2Rx => conv_std_logic_vector(extABuf2Rx_c.base, 16) &
conv_std_logic_vector(extABuf2Rx_c.span, 16)
)
port map (
--memory mapped interface
clk => ap_clk,
rst => ap_reset,
sel => selCntStReg_s.ap,
wr => ap_write,
rd => ap_read,
addr => ap_address(extLog2MaxOneSpan-1-2 downto 0),
be => ap_byteenable,
din => ap_writedata,
dout => outCntStReg_s.ap,
--register content
---virtual buffer control signals
pdoVirtualBufferSel => vBufSel_s.ap,
tPdoTrigger => vBufTriggerPdo_s.ap(3),
rPdoTrigger => vBufTriggerPdo_s.ap(2 downto 0),
---event registers
eventAckIn => ap_eventAck,
eventAckOut => ap_eventAck_p,
---async irq (by event)
asyncIrqCtrlIn => asyncIrqCtrlIn_s,
asyncIrqCtrlOut => asyncIrqCtrlOut_s,
---led stuff
ledCnfgIn => ap_ledForce_s,
ledCnfgOut => ap_ledForce_s,
ledCtrlIn => ap_ledSet_s,
ledCtrlOut => ap_ledSet_s,
---time synchronization
doubleBufSel_out => ap_timeSyncDBufSel,
doubleBufSel_in => '0', --AP is the source
timeSyncIrq => ap_irq_s,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprCntStReg_s.ap.addrOff,
dprDin => dprCntStReg_s.ap.din,
dprDout => dprOut.ap,
dprBe => dprCntStReg_s.ap.be,
dprWr => dprCntStReg_s.ap.wr,
--ap irq generation
--apIrqValue =>
apIrqControlOut => apIrqControlApOut,
apIrqControlIn => apIrqControlApIn,
rpdo_change_tog => (others => '0'),
tpdo_change_tog => '0'
);
theApIrqGenerator : entity work.apIrqGen
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g
)
port map (
--CLOCK DOMAIN PCP
clkA => pcp_clk,
rstA => pcp_reset,
irqA => pcp_irq,
--preValA => apIrqValue,
enableA => apIrqControlPcp(7),
modeA => apIrqControlPcp(6),
setA => apIrqControlPcp(0),
--CLOCK DOMAIN AP
clkB => ap_clk,
rstB => ap_reset,
ackB => apIrqControlApOut(0),
irqB => ap_irq_s
);
--irq enabled by apIrqControlApOut(15)
ap_irq <= ap_irq_s and apIrqControlApOut(15);
apIrqControlApIn <= apIrqControlApOut(15) & "000" & x"00" & "000" & ap_irq_s;
--the LED stuff
genLedGadget : if genLedGadget_g generate
--first set the hw leds
hw_ledForce_s <= x"00" & "00111100"; --phy1 and 0 act and link
hw_ledSet_s <= x"00" & "00" & (phyAct(1) and phyLink(1)) & phyLink(1) & (phyAct(0) and phyLink(0)) & phyLink(0) & "00";
theLedGadget : entity work.pdiLed
generic map (
iLedWidth_g => ledsOut'length
)
port map (
--src A (lowest priority)
srcAled => hw_ledSet_s(ledsOut'range),
srcAforce => hw_ledForce_s(ledsOut'range),
--src B
srcBled => pcp_ledSet_s(ledsOut'range),
srcBforce => pcp_ledForce_s(ledsOut'range),
--src C (highest priority)
srcCled => ap_ledSet_s(ledsOut'range),
srcCforce => ap_ledForce_s(ledsOut'range),
--led output
ledOut => ledsOut
);
end generate;
genEventComp : if genEvent_g generate
begin
theEventBlock : block
--set here the number of events
constant iSwEvent_c : integer := 1;
constant iHwEvent_c : integer := 2;
signal eventSetA : std_logic_vector(iSwEvent_c-1 downto 0);
signal eventReadA : std_logic_vector(iSwEvent_c+iHwEvent_c-1 downto 0);
signal eventAckB : std_logic_vector(iSwEvent_c+iHwEvent_c-1 downto 0);
signal eventReadB : std_logic_vector(iSwEvent_c+iHwEvent_c-1 downto 0);
begin
--event mapping: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- in register x x x x x x x x hw hw x x x x x sw
-- in pdiEvent hw hw sw
eventSetA <= pcp_eventSet_s(0 downto 0); --pcp sets sw event (I know, its called generic event, bla...)
pcp_eventRead <= x"00" & eventReadA(iSwEvent_c+iHwEvent_c-1 downto iSwEvent_c) &
"00000" & eventReadA(iSwEvent_c-1 downto 0);
eventAckB <= ap_eventAck_p(7 downto 6) & ap_eventAck_p(0); --ap acks events
ap_eventAck <= x"00" & eventReadB(iSwEvent_c+iHwEvent_c-1 downto iSwEvent_c) &
"00000" & eventReadB(iSwEvent_c-1 downto 0);
theEventStuff : entity work.pdiEvent
--16 bit
-- sw is at bit 0
-- hw is at bit 6 and 7
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
iSwEvent_g => 1,
iHwEvent_g => 2
)
port map (
--port A -> PCP
clkA => pcp_clk,
rstA => pcp_reset,
eventSetA => eventSetA,
eventReadA => eventReadA,
--port B -> AP
clkB => ap_clk,
rstB => ap_reset,
eventAckB => eventAckB,
eventReadB => eventReadB,
--hw event set pulse (must be synchronous to clkB!)
hwEventSetPulseB => phyLinkEvent
);
--generate async interrupt
asyncIrq : process(ap_eventAck)
variable tmp : std_logic;
begin
tmp := '0';
for i in ap_eventAck'range loop
tmp := tmp or ap_eventAck(i);
end loop;
ap_asyncIrq_s <= tmp;
end process;
--IRQ is asserted if enabled by AP
ap_asyncIrq <= ap_asyncIrq_s and asyncIrqCtrlOut_s(15);
asyncIrqCtrlIn_s(15) <= asyncIrqCtrlOut_s(15);
asyncIrqCtrlIn_s(14 downto 1) <= (others => '0'); --ignoring the rest
asyncIrqCtrlIn_s(0) <= ap_asyncIrq_s; --AP may poll IRQ level
syncPhyLinkGen : for i in phyLink'range generate
syncPhyLink : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => phyLink(i),
dout => phyLink_s(i),
clk => ap_clk,
rst => ap_reset
);
detPhyLinkEdge : entity work.edgeDet
port map (
din => phyLink_s(i),
rising => open,
falling => phyLinkEvent(i), --if phy link deasserts - EVENT!!!
any => open,
clk => ap_clk,
rst => ap_reset
);
end generate;
end block;
end generate;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- asynchronous Buffer 1 Tx
genABuf1Tx : if genABuf1_g generate
theAsyncBuf1Tx4Pcp : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf1Tx_c.base/4,
iDprAddrWidth_g => dprABuf1Tx_s.pcp.addr'length
)
port map (
--memory mapped interface
sel => selABuf1Tx_s.pcp,
wr => pcp_write,
rd => pcp_read,
addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0),
be => pcp_byteenable,
din => pcp_writedata,
dout => outABuf1Tx_s.pcp,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf1Tx_s.pcp.addrOff,
dprDin => dprABuf1Tx_s.pcp.din,
dprDout => dprOut.pcp,
dprBe => dprABuf1Tx_s.pcp.be,
dprWr => dprABuf1Tx_s.pcp.wr
);
theAsyncBuf1Tx4Ap : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf1Tx_c.base/4,
iDprAddrWidth_g => dprABuf1Tx_s.ap.addr'length
)
port map (
--memory mapped interface
sel => selABuf1Tx_s.ap,
wr => ap_write,
rd => ap_read,
addr => ap_address(extLog2MaxOneSpan-1-2 downto 0),
be => ap_byteenable,
din => ap_writedata,
dout => outABuf1Tx_s.ap,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf1Tx_s.ap.addrOff,
dprDin => dprABuf1Tx_s.ap.din,
dprDout => dprOut.ap,
dprBe => dprABuf1Tx_s.ap.be,
dprWr => dprABuf1Tx_s.ap.wr
);
end generate;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- asynchronous Buffer 1 Rx
genABuf1Rx : if genABuf1_g generate
theAsyncBuf1Rx4Pcp : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf1Rx_c.base/4,
iDprAddrWidth_g => dprABuf1Rx_s.pcp.addr'length
)
port map (
--memory mapped interface
sel => selABuf1Rx_s.pcp,
wr => pcp_write,
rd => pcp_read,
addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0),
be => pcp_byteenable,
din => pcp_writedata,
dout => outABuf1Rx_s.pcp,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf1Rx_s.pcp.addrOff,
dprDin => dprABuf1Rx_s.pcp.din,
dprDout => dprOut.pcp,
dprBe => dprABuf1Rx_s.pcp.be,
dprWr => dprABuf1Rx_s.pcp.wr
);
theAsyncBuf1Rx4Ap : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf1Rx_c.base/4,
iDprAddrWidth_g => dprABuf1Rx_s.ap.addr'length
)
port map (
--memory mapped interface
sel => selABuf1Rx_s.ap,
wr => ap_write,
rd => ap_read,
addr => ap_address(extLog2MaxOneSpan-1-2 downto 0),
be => ap_byteenable,
din => ap_writedata,
dout => outABuf1Rx_s.ap,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf1Rx_s.ap.addrOff,
dprDin => dprABuf1Rx_s.ap.din,
dprDout => dprOut.ap,
dprBe => dprABuf1Rx_s.ap.be,
dprWr => dprABuf1Rx_s.ap.wr
);
end generate;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- asynchronous Buffer 2 Tx
genABuf2Tx : if genABuf2_g generate
theAsyncBuf2Tx4Pcp : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf2Tx_c.base/4,
iDprAddrWidth_g => dprABuf2Tx_s.pcp.addr'length
)
port map (
--memory mapped interface
sel => selABuf2Tx_s.pcp,
wr => pcp_write,
rd => pcp_read,
addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0),
be => pcp_byteenable,
din => pcp_writedata,
dout => outABuf2Tx_s.pcp,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf2Tx_s.pcp.addrOff,
dprDin => dprABuf2Tx_s.pcp.din,
dprDout => dprOut.pcp,
dprBe => dprABuf2Tx_s.pcp.be,
dprWr => dprABuf2Tx_s.pcp.wr
);
theAsyncBuf2Tx4Ap : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf2Tx_c.base/4,
iDprAddrWidth_g => dprABuf2Tx_s.ap.addr'length
)
port map (
--memory mapped interface
sel => selABuf2Tx_s.ap,
wr => ap_write,
rd => ap_read,
addr => ap_address(extLog2MaxOneSpan-1-2 downto 0),
be => ap_byteenable,
din => ap_writedata,
dout => outABuf2Tx_s.ap,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf2Tx_s.ap.addrOff,
dprDin => dprABuf2Tx_s.ap.din,
dprDout => dprOut.ap,
dprBe => dprABuf2Tx_s.ap.be,
dprWr => dprABuf2Tx_s.ap.wr
);
end generate;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- asynchronous Buffer 2 Rx
genABuf2Rx : if genABuf2_g generate
theAsyncBuf2Rx4Pcp : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf2Rx_c.base/4,
iDprAddrWidth_g => dprABuf2Rx_s.pcp.addr'length
)
port map (
--memory mapped interface
sel => selABuf2Rx_s.pcp,
wr => pcp_write,
rd => pcp_read,
addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0),
be => pcp_byteenable,
din => pcp_writedata,
dout => outABuf2Rx_s.pcp,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf2Rx_s.pcp.addrOff,
dprDin => dprABuf2Rx_s.pcp.din,
dprDout => dprOut.pcp,
dprBe => dprABuf2Rx_s.pcp.be,
dprWr => dprABuf2Rx_s.pcp.wr
);
theAsyncBuf2Rx4Ap : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf2Rx_c.base/4,
iDprAddrWidth_g => dprABuf2Rx_s.ap.addr'length
)
port map (
--memory mapped interface
sel => selABuf2Rx_s.ap,
wr => ap_write,
rd => ap_read,
addr => ap_address(extLog2MaxOneSpan-1-2 downto 0),
be => ap_byteenable,
din => ap_writedata,
dout => outABuf2Rx_s.ap,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf2Rx_s.ap.addrOff,
dprDin => dprABuf2Rx_s.ap.din,
dprDout => dprOut.ap,
dprBe => dprABuf2Rx_s.ap.be,
dprWr => dprABuf2Rx_s.ap.wr
);
end generate;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
--TPDO buffer
theTpdoTrippleBuffer : block
signal selVBufPcpOneHot : std_logic_vector(2 downto 0);
signal selVBufApOneHot : std_logic_vector(2 downto 0);
begin
vBufSel_s.pcp(31 downto 24) <= x"00" when selVBufPcpOneHot = "001" else
x"11" when selVBufPcpOneHot = "010" else
x"22" when selVBufPcpOneHot = "100" else
x"FF";
vBufSel_s.ap(31 downto 24) <= x"00" when selVBufApOneHot = "001" else
x"11" when selVBufApOneHot = "010" else
x"22" when selVBufApOneHot = "100" else
x"FF";
dprTpdoBuf_s.pcp.din <= pcp_writedata;
outTpdoBuf_s.pcp <= dprOut.pcp;
dprTpdoBuf_s.pcp.be <= pcp_byteenable;
dprTpdoBuf_s.pcp.wr <= pcp_write;
dprTpdoBuf_s.ap.din <= ap_writedata;
outTpdoBuf_s.ap <= dprOut.ap;
dprTpdoBuf_s.ap.be <= ap_byteenable;
dprTpdoBuf_s.ap.wr <= ap_write;
theTrippleMechanism : entity work.tripleVBufLogic
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
--base address of virtual buffers in DPR
iVirtualBufferBase_g => intTpdoBuf_c.base/4, --double word!
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g => intTpdoBuf_c.span/3/4, --double word!
--out address width
iOutAddrWidth_g => dprTpdoBuf_s.pcp.addr'length,
--in address width
iInAddrWidth_g => extLog2MaxOneSpan-2,
--ap is producer
bApIsProducer => true
)
port map (
pcpClk => pcp_clk,
pcpReset => pcp_reset,
pcpTrigger => vBufTriggerPdo_s.pcp(3),
pcpOutAddrOff => dprTpdoBuf_s.pcp.addrOff,
pcpOutSelVBuf => selVBufPcpOneHot,
apClk => ap_clk,
apReset => ap_reset,
apTrigger => vBufTriggerPdo_s.ap(3),
apOutAddrOff => dprTpdoBuf_s.ap.addrOff,
apOutSelVBuf => selVBufApOneHot
);
end block;
--
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
--RPDO0 buffer
theRpdo0TrippleBuffer : block
signal selVBufPcpOneHot : std_logic_vector(2 downto 0);
signal selVBufApOneHot : std_logic_vector(2 downto 0);
begin
vBufSel_s.pcp(7 downto 0) <= x"00" when selVBufPcpOneHot = "001" else
x"11" when selVBufPcpOneHot = "010" else
x"22" when selVBufPcpOneHot = "100" else
x"FF";
vBufSel_s.ap(7 downto 0) <= x"00" when selVBufApOneHot = "001" else
x"11" when selVBufApOneHot = "010" else
x"22" when selVBufApOneHot = "100" else
x"FF";
dprRpdo0Buf_s.pcp.din <= pcp_writedata;
outRpdo0Buf_s.pcp <= dprOut.pcp;
dprRpdo0Buf_s.pcp.be <= pcp_byteenable;
dprRpdo0Buf_s.pcp.wr <= pcp_write;
dprRpdo0Buf_s.ap.din <= ap_writedata;
outRpdo0Buf_s.ap <= dprOut.ap;
dprRpdo0Buf_s.ap.be <= ap_byteenable;
dprRpdo0Buf_s.ap.wr <= ap_write;
theTrippleMechanism : entity work.tripleVBufLogic
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
--base address of virtual buffers in DPR
iVirtualBufferBase_g => intRpdo0Buf_c.base/4, --double word!
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g => intRpdo0Buf_c.span/3/4, --double word!
--out address width
iOutAddrWidth_g => dprRpdo0Buf_s.pcp.addr'length,
--in address width
iInAddrWidth_g => extLog2MaxOneSpan-2,
--ap is NOT producer
bApIsProducer => false
)
port map (
pcpClk => pcp_clk,
pcpReset => pcp_reset,
pcpTrigger => vBufTriggerPdo_s.pcp(0),
pcpOutAddrOff => dprRpdo0Buf_s.pcp.addrOff,
pcpOutSelVBuf => selVBufPcpOneHot,
apClk => ap_clk,
apReset => ap_reset,
apTrigger => vBufTriggerPdo_s.ap(0),
apOutAddrOff => dprRpdo0Buf_s.ap.addrOff,
apOutSelVBuf => selVBufApOneHot
);
end block;
--
------------------------------------------------------------------------------------------------------------------------
genRpdo1 : if iRpdos_g >= 2 generate
------------------------------------------------------------------------------------------------------------------------
--RPDO1 buffer
theRpdo1TrippleBuffer : block
signal selVBufPcpOneHot : std_logic_vector(2 downto 0);
signal selVBufApOneHot : std_logic_vector(2 downto 0);
begin
vBufSel_s.pcp(15 downto 8) <= x"00" when selVBufPcpOneHot = "001" else
x"11" when selVBufPcpOneHot = "010" else
x"22" when selVBufPcpOneHot = "100" else
x"FF";
vBufSel_s.ap(15 downto 8) <= x"00" when selVBufApOneHot = "001" else
x"11" when selVBufApOneHot = "010" else
x"22" when selVBufApOneHot = "100" else
x"FF";
dprRpdo1Buf_s.pcp.din <= pcp_writedata;
outRpdo1Buf_s.pcp <= dprOut.pcp;
dprRpdo1Buf_s.pcp.be <= pcp_byteenable;
dprRpdo1Buf_s.pcp.wr <= pcp_write;
dprRpdo1Buf_s.ap.din <= ap_writedata;
outRpdo1Buf_s.ap <= dprOut.ap;
dprRpdo1Buf_s.ap.be <= ap_byteenable;
dprRpdo1Buf_s.ap.wr <= ap_write;
theTrippleMechanism : entity work.tripleVBufLogic
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
--base address of virtual buffers in DPR
iVirtualBufferBase_g => intRpdo1Buf_c.base/4, --double word!
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g => intRpdo1Buf_c.span/3/4, --double word!
--out address width
iOutAddrWidth_g => dprRpdo1Buf_s.pcp.addr'length,
--in address width
iInAddrWidth_g => extLog2MaxOneSpan-2,
--ap is NOT producer
bApIsProducer => false
)
port map (
pcpClk => pcp_clk,
pcpReset => pcp_reset,
pcpTrigger => vBufTriggerPdo_s.pcp(1),
pcpOutAddrOff => dprRpdo1Buf_s.pcp.addrOff,
pcpOutSelVBuf => selVBufPcpOneHot,
apClk => ap_clk,
apReset => ap_reset,
apTrigger => vBufTriggerPdo_s.ap(1),
apOutAddrOff => dprRpdo1Buf_s.ap.addrOff,
apOutSelVBuf => selVBufApOneHot
);
end block;
--
------------------------------------------------------------------------------------------------------------------------
end generate;
genRpdo2 : if iRpdos_g >= 3 generate
------------------------------------------------------------------------------------------------------------------------
--RPDO2 buffer
theRpdo2TrippleBuffer : block
signal selVBufPcpOneHot : std_logic_vector(2 downto 0);
signal selVBufApOneHot : std_logic_vector(2 downto 0);
begin
vBufSel_s.pcp(23 downto 16) <= x"00" when selVBufPcpOneHot = "001" else
x"11" when selVBufPcpOneHot = "010" else
x"22" when selVBufPcpOneHot = "100" else
x"FF";
vBufSel_s.ap(23 downto 16) <= x"00" when selVBufApOneHot = "001" else
x"11" when selVBufApOneHot = "010" else
x"22" when selVBufApOneHot = "100" else
x"FF";
dprRpdo2Buf_s.pcp.din <= pcp_writedata;
outRpdo2Buf_s.pcp <= dprOut.pcp;
dprRpdo2Buf_s.pcp.be <= pcp_byteenable;
dprRpdo2Buf_s.pcp.wr <= pcp_write;
dprRpdo2Buf_s.ap.din <= ap_writedata;
outRpdo2Buf_s.ap <= dprOut.ap;
dprRpdo2Buf_s.ap.be <= ap_byteenable;
dprRpdo2Buf_s.ap.wr <= ap_write;
theTrippleMechanism : entity work.tripleVBufLogic
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
--base address of virtual buffers in DPR
iVirtualBufferBase_g => intRpdo2Buf_c.base/4, --double word!
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g => intRpdo2Buf_c.span/3/4, --double word!
--out address width
iOutAddrWidth_g => dprRpdo2Buf_s.pcp.addr'length,
--in address width
iInAddrWidth_g => extLog2MaxOneSpan-2,
--ap is NOT producer
bApIsProducer => false
)
port map (
pcpClk => pcp_clk,
pcpReset => pcp_reset,
pcpTrigger => vBufTriggerPdo_s.pcp(2),
pcpOutAddrOff => dprRpdo2Buf_s.pcp.addrOff,
pcpOutSelVBuf => selVBufPcpOneHot,
apClk => ap_clk,
apReset => ap_reset,
apTrigger => vBufTriggerPdo_s.ap(2),
apOutAddrOff => dprRpdo2Buf_s.ap.addrOff,
apOutSelVBuf => selVBufApOneHot
);
end block;
--
------------------------------------------------------------------------------------------------------------------------
end generate;
------------------------------------------------------------------------------------------------------------------------
-- waitrequest signals
theWaitrequestGenerators : block
signal pcp_wr, pcp_rd, pcp_rd_ack, pcp_wr_ack : std_logic;
signal ap_wr, ap_rd, ap_rd_ack, ap_wr_ack : std_logic;
begin
-- PCP
thePcpWrWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => pcp_clk,
rst => pcp_reset,
enable => pcp_wr,
ack => pcp_wr_ack
);
thePcpRdWaitReqAckGen : entity work.req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map (
clk => pcp_clk,
rst => pcp_reset,
enable => pcp_rd,
ack => pcp_rd_ack
);
pcp_wr <= pcp_chipselect and pcp_write;
pcp_rd <= pcp_chipselect and pcp_read;
pcp_waitrequest <= not(pcp_rd_ack or pcp_wr_ack);
-- AP
theApWrWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => ap_clk,
rst => ap_reset,
enable => ap_wr,
ack => ap_wr_ack
);
theApRdWaitReqAckGen : entity work.req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map (
clk => ap_clk,
rst => ap_reset,
enable => ap_rd,
ack => ap_rd_ack
);
ap_wr <= ap_chipselect and ap_write;
ap_rd <= ap_chipselect and ap_read;
ap_waitrequest <= not(ap_rd_ack or ap_wr_ack);
end block;
--
------------------------------------------------------------------------------------------------------------------------
end architecture rtl;
| gpl-2.0 |
Charlesworth/Albot | Albot VHDL/lpm_compare1_inst.vhd | 1 | 114 | lpm_compare1_inst : lpm_compare1 PORT MAP (
dataa => dataa_sig,
datab => datab_sig,
AleB => AleB_sig
);
| gpl-2.0 |
bert/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/resistor_arc.vhdl | 15 | 113 | ARCHITECTURE beh OF resistor IS
QUANTITY v ACROSS i THROUGH lt to rt;
BEGIN
v == r * i;
END ARCHITECTURE beh;
| gpl-2.0 |
bert/geda-gaf | gnetlist/docs/README.vhdl | 7 | 598 |
The VHDL backend
Written by Magnus Danielson and improved by Thomas Heidel
A few things you have to care about:
1. In order to generate valid component declarations, you
have to add an additional attribute to each pin.
"type=IN" or "type=OUT" or "type=INOUT"
2. The "device" attribute must be unique to a symbol!
The verilog symbols of the same type for example, have all
the same device attribute and will therefore not work.
3. Make sure your component-library picks up the vhdl symbols instead
of the verilog symbols Library paths that show up last are searched
first!
| gpl-2.0 |
bert/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/sp_diode_arc.vhdl | 15 | 663 | -- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE SPICE_Diode_Model OF sp_Diode IS
terminal unnamed_net2 : electrical;
BEGIN
-- Architecture statement part
CS1 : ENTITY CURRENT_SOURCE(voltage_dependend)
GENERIC MAP (
N => N,
VT => VT,
ISS => ISS)
PORT MAP ( LT => unnamed_net2,
RT => kathode);
VD_CAP : ENTITY VOLTAGE_DEPENDEND_CAPACITOR
GENERIC MAP (
PB => PB,
M => M,
VT => VT,
ISS => ISS,
TT => TT,
CJ0 => CJ0)
PORT MAP ( LT => kathode,
RT => unnamed_net2);
RES : ENTITY RESISTOR
GENERIC MAP (
r => RS)
PORT MAP ( RT => anode,
LT => unnamed_net2);
END ARCHITECTURE;
| gpl-2.0 |
shunlir/ctags | Units/review-needed.r/bug2374109.vhd.t/input.vhd | 98 | 196 | function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
| gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd | 2 | 354 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: spi_counter-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $
--
-------------------------------------------------------------------------------
configuration spi_counter_rtl_c0 of spi_counter is
for rtl
end for;
end spi_counter_rtl_c0;
| gpl-2.0 |
Charlesworth/Albot | Albot VHDL/StateMachine.vhd | 1 | 1565 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity StateMachine is
port (
clk : in std_logic;
nReset : in std_logic;
Dout : out std_logic_vector(7 downto 0); -- data read from ds1621
error : out std_logic; -- no correct ack received
SCL : inout std_logic;
SDA : inout std_logic
);
end entity StateMachine;
architecture structural of StateMachine is
---------------------------------------------------------------------------
YUVmachine: process (Hsync, Vsync, YUV_Cstate)
begin
case YUV_Cstate is
when "000" =>
YUV_Nstate <="001";
YUVclk<= '0';
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
when "001" =>
YUV_Nstate <="010";
YUVclk<='1' ; --and Hsync;
Yclk<='1';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
when "010" =>
YUV_Nstate <="011";
YUVclk<='0';
Yclk<='0';
Uclk<='1';
Y1clk<='0';
Vclk<='0';
when "011" =>
YUV_Nstate <="100";
YUVclk<='0';
Yclk<='0';
Uclk<='0';
Y1clk<='1';
Vclk<='0';
when "100" =>
YUV_Nstate <="001";
YUVclk<='0';
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='1';
when others =>
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
YUV_Nstate <="001";
YUVclk<='0';
end case;
-- genregs
if (Hsync='0') then
YUV_Cstate <="000";
elsif (clk'event) and (clk = '0') then -- PC 04.08.06 was '1'
YUV_Cstate<=YUV_Nstate;
end if;
end process structural;
--------------------------------------------------------------------------- | gpl-2.0 |
AngelLM/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/clkTB.vhd | 2 | 1619 | ----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clkTB IS
END clkTB;
ARCHITECTURE behavior OF clkTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clk_mod
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada : std_logic := '0';
signal reset : std_logic := '0';
-- Salidas
signal salida : std_logic;
constant entrada_t : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: clk_mod PORT MAP (
entrada => entrada,
reset => reset,
salida => salida
);
-- Definición del reloj.
entrada_process :process
begin
entrada <= '0';
wait for entrada_t / 2;
entrada <= '1';
wait for entrada_t / 2;
end process;
-- Procesamiento de estímulos.
estimulos: process
begin
reset <= '1'; -- Condiciones iniciales.
wait for 100 ns;
reset <= '0'; -- ¡A trabajar!
wait;
end process;
END; | gpl-2.0 |
AngelLM/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/ContadorEventos.vhd | 2 | 1329 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:38:47 01/07/2015
-- Design Name:
-- Module Name: ContadorEventos - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ContadorEventos is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(3 downto 0));
end ContadorEventos;
architecture behavioral of ContadorEventos is
signal q_i: std_logic_vector(q'range):=(others => '0');
begin
p1:process(reset, clk)
begin
if reset = '1' then
q_i <= (others => '0');
elsif rising_edge(clk) then
q_i <= std_logic_vector(unsigned(q_i) + 1);
end if;
end process;
q <= q_i;
end behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_CRLF/CLOCK_SINGLE_RUN_SRC.vhd | 26 | 2585 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLOCK_SINGLE_RUN_SRC is
Port ( CLK: in std_logic; -- (System) Takt
SINGLE: in std_logic; -- 1: Einzeltakt
RUN_R: in std_logic; -- 1: Dauerbetrieb
-- mit Eingangsregister
RESET: in std_logic; -- 1: Initialzustand soll angenommen werden
OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand
end CLOCK_SINGLE_RUN_SRC;
architecture Behavioral of CLOCK_SINGLE_RUN_SRC is
type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände
signal SV: TYPE_STATE; --Zustangsvariable
signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master
signal RUN_S: std_logic;
signal not_CLK : std_logic;
begin
NOT_CLK_PROC: process (CLK)
begin
not_CLK <= not CLK;
end process;
IREG_PROC: process (RUN_R, not_CLK)
begin
if (not_CLK'event and not_CLK = '1')
then RUN_S <= RUN_R;
end if;
end process;
IL_OL_PROC: process (SINGLE, RUN_S, SV)
begin
case SV is
when CSR_0 =>
if (SINGLE = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2;
else
if (RUN_S = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
end if;
when CSR_1 => OUT_NEXT_STATE <= '0';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
end if;
when CSR_2 => OUT_NEXT_STATE <= '1';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
when others => OUT_NEXT_STATE <= '0';
end case;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) -- Master
begin
if(RESET = '1')
then SV_M <= CSR_0;
else
if (CLK'event and CLK = '1')
then SV_M <= n_SV;
else SV_M <= SV_M;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave
begin
if(RESET = '1')
then SV <= CSR_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/PROFIBUS_MONITOR/CLOCK_SINGLE_RUN_SRC.vhd | 26 | 2585 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLOCK_SINGLE_RUN_SRC is
Port ( CLK: in std_logic; -- (System) Takt
SINGLE: in std_logic; -- 1: Einzeltakt
RUN_R: in std_logic; -- 1: Dauerbetrieb
-- mit Eingangsregister
RESET: in std_logic; -- 1: Initialzustand soll angenommen werden
OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand
end CLOCK_SINGLE_RUN_SRC;
architecture Behavioral of CLOCK_SINGLE_RUN_SRC is
type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände
signal SV: TYPE_STATE; --Zustangsvariable
signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master
signal RUN_S: std_logic;
signal not_CLK : std_logic;
begin
NOT_CLK_PROC: process (CLK)
begin
not_CLK <= not CLK;
end process;
IREG_PROC: process (RUN_R, not_CLK)
begin
if (not_CLK'event and not_CLK = '1')
then RUN_S <= RUN_R;
end if;
end process;
IL_OL_PROC: process (SINGLE, RUN_S, SV)
begin
case SV is
when CSR_0 =>
if (SINGLE = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2;
else
if (RUN_S = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
end if;
when CSR_1 => OUT_NEXT_STATE <= '0';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
end if;
when CSR_2 => OUT_NEXT_STATE <= '1';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
when others => OUT_NEXT_STATE <= '0';
end case;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) -- Master
begin
if(RESET = '1')
then SV_M <= CSR_0;
else
if (CLK'event and CLK = '1')
then SV_M <= n_SV;
else SV_M <= SV_M;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave
begin
if(RESET = '1')
then SV <= CSR_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/TEST_CTRL_RS232_TX/CLOCK_SINGLE_RUN_SRC.vhd | 26 | 2585 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLOCK_SINGLE_RUN_SRC is
Port ( CLK: in std_logic; -- (System) Takt
SINGLE: in std_logic; -- 1: Einzeltakt
RUN_R: in std_logic; -- 1: Dauerbetrieb
-- mit Eingangsregister
RESET: in std_logic; -- 1: Initialzustand soll angenommen werden
OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand
end CLOCK_SINGLE_RUN_SRC;
architecture Behavioral of CLOCK_SINGLE_RUN_SRC is
type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände
signal SV: TYPE_STATE; --Zustangsvariable
signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master
signal RUN_S: std_logic;
signal not_CLK : std_logic;
begin
NOT_CLK_PROC: process (CLK)
begin
not_CLK <= not CLK;
end process;
IREG_PROC: process (RUN_R, not_CLK)
begin
if (not_CLK'event and not_CLK = '1')
then RUN_S <= RUN_R;
end if;
end process;
IL_OL_PROC: process (SINGLE, RUN_S, SV)
begin
case SV is
when CSR_0 =>
if (SINGLE = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2;
else
if (RUN_S = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
end if;
when CSR_1 => OUT_NEXT_STATE <= '0';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
end if;
when CSR_2 => OUT_NEXT_STATE <= '1';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
when others => OUT_NEXT_STATE <= '0';
end case;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) -- Master
begin
if(RESET = '1')
then SV_M <= CSR_0;
else
if (CLK'event and CLK = '1')
then SV_M <= n_SV;
else SV_M <= SV_M;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave
begin
if(RESET = '1')
then SV <= CSR_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine/TEST_CTRL_TELEGRAM_CHECK/CLOCK_SINGLE_RUN_SRC.vhd | 26 | 2585 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLOCK_SINGLE_RUN_SRC is
Port ( CLK: in std_logic; -- (System) Takt
SINGLE: in std_logic; -- 1: Einzeltakt
RUN_R: in std_logic; -- 1: Dauerbetrieb
-- mit Eingangsregister
RESET: in std_logic; -- 1: Initialzustand soll angenommen werden
OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand
end CLOCK_SINGLE_RUN_SRC;
architecture Behavioral of CLOCK_SINGLE_RUN_SRC is
type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände
signal SV: TYPE_STATE; --Zustangsvariable
signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master
signal RUN_S: std_logic;
signal not_CLK : std_logic;
begin
NOT_CLK_PROC: process (CLK)
begin
not_CLK <= not CLK;
end process;
IREG_PROC: process (RUN_R, not_CLK)
begin
if (not_CLK'event and not_CLK = '1')
then RUN_S <= RUN_R;
end if;
end process;
IL_OL_PROC: process (SINGLE, RUN_S, SV)
begin
case SV is
when CSR_0 =>
if (SINGLE = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2;
else
if (RUN_S = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
end if;
when CSR_1 => OUT_NEXT_STATE <= '0';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
end if;
when CSR_2 => OUT_NEXT_STATE <= '1';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
when others => OUT_NEXT_STATE <= '0';
end case;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) -- Master
begin
if(RESET = '1')
then SV_M <= CSR_0;
else
if (CLK'event and CLK = '1')
then SV_M <= n_SV;
else SV_M <= SV_M;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave
begin
if(RESET = '1')
then SV <= CSR_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_19_12_2012/TEST_CTRL_9P6_50MHZ_SCH/CLOCK_SINGLE_RUN_SRC.vhd | 12 | 2560 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLOCK_SINGLE_RUN_SRC is
Port ( CLK: in std_logic; -- (System) Takt
SINGLE: in std_logic; -- 1: Einzeltakt
RUN_R: in std_logic; -- 1: Dauerbetrieb
-- mit Eingangsregister
RESET: in std_logic; -- 1: Initialzustand soll angenommen werden
OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand
end CLOCK_SINGLE_RUN_SRC;
architecture Behavioral of CLOCK_SINGLE_RUN_SRC is
type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände
signal SV: TYPE_STATE; --Zustangsvariable
signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master
signal RUN_S: std_logic;
signal not_CLK : std_logic;
begin
NOT_CLK_PROC: process (CLK)
begin
not_CLK <= not CLK;
end process;
IREG_PROC: process (RUN_R, not_CLK)
begin
if (not_CLK'event and not_CLK = '1')
then RUN_S <= RUN_R;
end if;
end process;
IL_OL_PROC: process (SINGLE, RUN_S, SV)
begin
case SV is
when CSR_0 =>
if (SINGLE = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2;
else
if (RUN_S = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
end if;
when CSR_1 => OUT_NEXT_STATE <= '0';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
end if;
when CSR_2 => OUT_NEXT_STATE <= '1';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
when others => OUT_NEXT_STATE <= '0';
end case;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) -- Master
begin
if(RESET = '1')
then SV_M <= CSR_0;
else
if (CLK'event and CLK = '1')
then SV_M <= n_SV;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave
begin
if(RESET = '1')
then SV <= CSR_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine/PROFIBUS_MONITOR/CTRL_InAB_INPUT_VHDL.vhd | 4 | 27282 | -- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_InAB_INPUT_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
EN_BIT_i : out std_logic_vector (8 downto 0); --Ausgangsvariable, Enable Bit i, 9bit
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_CMPLT: out std_logic; --Ausgangsvariabel, Byte empfangen und komplett
PAUSE_END : out std_logic; --Ausgangssignal, Pause zu Ende
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_InAB_INPUT_VHDL;
architecture Behavioral of CTRL_InAB_INPUT_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F);--15
signal SV : TYPE_STATE := ST_CTRL_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, Ausgang Master
signal COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal InAB_S : std_logic := '0'; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal EN_BIT_0 : std_logic := '0'; --BIT0
signal EN_BIT_1 : std_logic := '0'; --BIT1
signal EN_BIT_2 : std_logic := '0'; --BIT2
signal EN_BIT_3 : std_logic := '0'; --BIT3
signal EN_BIT_4 : std_logic := '0'; --BIT4
signal EN_BIT_5 : std_logic := '0'; --BIT5
signal EN_BIT_6 : std_logic := '0'; --BIT6
signal EN_BIT_7 : std_logic := '0'; --BIT7
signal EN_BIT_8 : std_logic := '0'; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0) := x"00000"; --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT02 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT03 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT04 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT05 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT06 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT07 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT08 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT09 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT10 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT11 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT12 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT13 : std_logic_vector (15 downto 0) := x"0000";
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"D9B1";
constant long_CNTT13 : std_logic_vector := x"E5E6";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
---NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
COUNT_L_M <= x"00000";
COUNT_S_M <= x"0000";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
COUNT_L <= x"00000";
COUNT_S <= x"0000";
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (InAB_S = '1')
then
if (COUNT_L = CNTS30) --156250 -- if (COUNT >=3)
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --not COUNT_L = CNTS30
--VAS01
PAUSE_END <= '0';
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
else --InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Zustandsuebgergang
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '1';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte ab bis InAB wieder NUll wird
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end if;
else
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when ST_CTRL_04 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; --Zaehlschleife
end if;
when ST_CTRL_05 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Zaehlschleife
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT11) --54687
then
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit, vormals ST_CTRL_05
else --InAB_S = '1'
-- VAS13
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_0E; --Stoppbit erkannt
end if; --InAB_S = '0'
else --not COUNT_S = CNTT11
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if; --COUNT_S = CNTT11
when ST_CTRL_0E =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (InAB_S = '1') --Startbot bisher ncoh nicht gefunden
then
if (COUNT_S = CNTT13) --64062
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else --not COUNT_S = CNTT13
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if; --COUNT_S = CNTT13
else --InAB_S = '0'
-- Startbit gefunden
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when others =>
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
--BYTE_IN_PROC: process (EN_BIT_0, EN_BIT_1, EN_BIT_2, EN_BIT_3, EN_BIT_4, EN_BIT_5, EN_BIT_6, EN_BIT_7, EN_BIT_8) --Umwandlung einzelnes Bit EIN_BIT_0_S bis 8_S in Vector EN_BIT_i
-- begin
EN_BIT_i(0) <= EN_BIT_0;
EN_BIT_i(1) <= EN_BIT_1;
EN_BIT_i(2) <= EN_BIT_2;
EN_BIT_i(3) <= EN_BIT_3;
EN_BIT_i(4) <= EN_BIT_4;
EN_BIT_i(5) <= EN_BIT_5;
EN_BIT_i(6) <= EN_BIT_6;
EN_BIT_i(7) <= EN_BIT_7;
EN_BIT_i(8) <= EN_BIT_8;
--end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine/PROFIBUS_MONITOR/CTRL_TELEGRAM_FILTER_VHDL.vhd | 8 | 10937 | -- CTRL_TELEGRAM_FILTER
-- Voreingestellten Profibus Telegramtyp ermitteln und Bytes ausgeben, alternativ alle Bytes durchlassen
-- Ersteller: Martin Harndt
-- Erstellt: 22.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 22.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_FILTER_VHDL is
Port (BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
FILTER_ON : in std_logic; --Eingangsvariable, Filter einschalten
FILTER_T : in std_logic_vector (2 downto 0); --Eingangsvariable, Telegramfilter einstellen, 3bit
FILTER_BYTE_OUT : out std_logic_vector (7 downto 0);--Ausgangsvariable, gefilterte Telegramme
SEND_OUT : out std_logic; --Ausgangsvariable, Byte senden
T_CMPLT: out std_logic; --Ausgangsvariable, Telegramm komplett
DISPL_COUNT : in std_logic; --Eingangsvariable, Folgeszustand oder Bytezaehler anzeigen
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_FILTER_VHDL;
architecture Behavioral of CTRL_TELEGRAM_FILTER_VHDL is
type TYPE_STATE is
(ST_FI_00, --Zustaende TELEGRAM_CHECK
ST_FI_01,
ST_FI_02,
ST_FI_03,
ST_FI_04,
ST_FI_05,
ST_FI_06,
ST_FI_07,
ST_FI_08,
ST_FI_09,
ST_FI_10,
ST_FI_11,
ST_FI_12,
ST_FI_13,
ST_FI_14,
ST_FI_15);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (7 downto 0); -- Vektor, Zaehler, 8bit
signal n_COUNT : std_logic_vector (7 downto 0); -- Vektor, Zaehler, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Zaehler, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal not_CLK : std_logic; --negierte Taktvariable
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_FI_00;
COUNT_M <= x"00";
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_FI_00;
COUNT <= x"00";
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_FILTER_PROC:process (FILTER_ON, FILTER_T, BYTE_IN, SV, COUNT) --Telegramme Filtern und ausgeben
begin
case SV is
when ST_FI_00 =>
if (FILTER_ON = '1')
then
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_01;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_01 =>
if (FILTER_T = "000")
then
--FI01
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI01
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_02;
end if;
when ST_FI_02 =>
if (FILTER_T = "001")
then
--FI01
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_03;
else
--FI01
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_05;
end if;
when ST_FI_03 =>
if (BYTE_IN = x"10")
then
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_04;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_04 =>
if (COUNT = x"06")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '1';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_04;
end if;
when ST_FI_05 =>
if (FILTER_T= "010")
then
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_06;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_08;
end if;
when ST_FI_06 =>
if (BYTE_IN = x"68")
then
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_07;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_07 =>
if (COUNT = x"F9" OR BYTE_IN = x"16")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '1';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_07;
end if;
when ST_FI_08 =>
if (FILTER_T= "011")
then
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_09;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_11;
end if;
when ST_FI_09 =>
if (BYTE_IN = x"A2")
then
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_10;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_10 =>
if (COUNT = x"0E")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '1';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_10;
end if;
when ST_FI_11 =>
if (FILTER_T= "100")
then
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_12;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_14;
end if;
when ST_FI_12 =>
if (BYTE_IN = x"DC")
then
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_13;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_13 =>
if (COUNT = x"03")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '1';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_13;
end if;
when ST_FI_14 =>
if (FILTER_T= "101")
then
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_15;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_15 =>
if (BYTE_IN = x"E5")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '1';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when others =>
-- FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, STATE_SV, STATE_n_SV, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
--anktuellen Zustand anzeigen
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT ='0') --Original
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
else --Telegrammzaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
end if;
end process;
end Behavioral;
| gpl-2.0 |
Hoernchen/hackrf | firmware/cpld/sgpio_if/top.vhd | 1 | 4061 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic;
B1AUX : inout std_logic_vector(16 downto 9);
B2AUX : inout std_logic_vector(16 downto 1)
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
begin
B1AUX <= (others => '0');
B2AUX <= (others => '0');
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
------------------------------------------------
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
data_to_host_o <= adc_data_i;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
dac_data_o <= data_from_host_i & "00";
else
dac_data_o <= (dac_data_o'high => '1', others => '0');
end if;
end if;
end process;
process(host_clk_i, codec_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i;
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_14_12_2012/TEST2_SRAM_25MHZ_255_BYTE/SRAM_25MHZ_255_BYTE.vhd | 4 | 10382 | -- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_OUT : out std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; --Chip Enable
UB1 : out std_logic; --Upper Byte Enable
LB1 : out std_logic; --Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT)
begin
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
ADR_DAT_OUT_PROC: process (n_COUNT_ADR, n_COUNT_DAT) --Ausgabe Adresse und Daten
begin
--Adressen
COUNT_ADR_OUT(0) <= n_COUNT_ADR(0);
COUNT_ADR_OUT(1) <= n_COUNT_ADR(1);
COUNT_ADR_OUT(2) <= n_COUNT_ADR(2);
COUNT_ADR_OUT(3) <= n_COUNT_ADR(3);
COUNT_ADR_OUT(4) <= n_COUNT_ADR(4);
COUNT_ADR_OUT(5) <= n_COUNT_ADR(5);
COUNT_ADR_OUT(6) <= n_COUNT_ADR(6);
COUNT_ADR_OUT(7) <= n_COUNT_ADR(7);
COUNT_ADR_OUT(8) <= n_COUNT_ADR(8);
COUNT_ADR_OUT(9) <= n_COUNT_ADR(9);
COUNT_ADR_OUT(10) <= n_COUNT_ADR(10);
COUNT_ADR_OUT(11) <= n_COUNT_ADR(11);
COUNT_ADR_OUT(12) <= n_COUNT_ADR(12);
COUNT_ADR_OUT(13) <= n_COUNT_ADR(13);
COUNT_ADR_OUT(14) <= n_COUNT_ADR(14);
COUNT_ADR_OUT(15) <= n_COUNT_ADR(15);
COUNT_ADR_OUT(16) <= n_COUNT_ADR(16);
COUNT_ADR_OUT(17) <= n_COUNT_ADR(17);
COUNT_ADR_OUT(18) <= n_COUNT_ADR(18);
--Daten
COUNT_DAT_OUT(0) <= n_COUNT_DAT(0);
COUNT_DAT_OUT(1) <= n_COUNT_DAT(1);
COUNT_DAT_OUT(2) <= n_COUNT_DAT(2);
COUNT_DAT_OUT(3) <= n_COUNT_DAT(3);
COUNT_DAT_OUT(4) <= n_COUNT_DAT(4);
COUNT_DAT_OUT(5) <= n_COUNT_DAT(5);
COUNT_DAT_OUT(6) <= n_COUNT_DAT(6);
COUNT_DAT_OUT(7) <= n_COUNT_DAT(7);
COUNT_DAT_OUT(8) <= n_COUNT_DAT(8);
COUNT_DAT_OUT(9) <= n_COUNT_DAT(9);
COUNT_DAT_OUT(10) <= n_COUNT_DAT(10);
COUNT_DAT_OUT(11) <= n_COUNT_DAT(11);
COUNT_DAT_OUT(12) <= n_COUNT_DAT(12);
COUNT_DAT_OUT(13) <= n_COUNT_DAT(13);
COUNT_DAT_OUT(14) <= n_COUNT_DAT(14);
COUNT_DAT_OUT(15) <= n_COUNT_DAT(15);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_14_12_2012/TEST2_SRAM_25MHZ_255_BYTE/F_DIV50000_SRC.vhd | 38 | 917 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_DIV50000 is
Port ( F_IN : in std_logic; -- Eingangsfrequenz
F_OUT : out std_logic); -- Ausgangsfrequen
-- FOUT ändert sich mit der
-- 0/1-Flanke von F_IN
end F_DIV50000;
architecture Behavioral of F_DIV50000 is
signal COUNTER : integer;
-- Maximalwert: Teilungsfaktor - 1
begin
process (F_IN,COUNTER )
begin
if (F_IN'event and F_IN = '1')
then -- am Eingang des Frequenzteilers ist eine 0/1-Flanke aufgetreten
if COUNTER = 0
then COUNTER <= 49999; -- Teilungsfaktor -1
else COUNTER <= COUNTER -1;
end if;
end if;
if COUNTER < 25000 -- Teilungsfaktor / 2 (abgerundet)
then F_OUT <= '0';
else F_OUT <= '1';
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_TELEGRAM_FILTER_SD1/F_DIV50000_SRC.vhd | 38 | 917 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_DIV50000 is
Port ( F_IN : in std_logic; -- Eingangsfrequenz
F_OUT : out std_logic); -- Ausgangsfrequen
-- FOUT ändert sich mit der
-- 0/1-Flanke von F_IN
end F_DIV50000;
architecture Behavioral of F_DIV50000 is
signal COUNTER : integer;
-- Maximalwert: Teilungsfaktor - 1
begin
process (F_IN,COUNTER )
begin
if (F_IN'event and F_IN = '1')
then -- am Eingang des Frequenzteilers ist eine 0/1-Flanke aufgetreten
if COUNTER = 0
then COUNTER <= 49999; -- Teilungsfaktor -1
else COUNTER <= COUNTER -1;
end if;
end if;
if COUNTER < 25000 -- Teilungsfaktor / 2 (abgerundet)
then F_OUT <= '0';
else F_OUT <= '1';
end if;
end process;
end Behavioral;
| gpl-2.0 |
camelpunch/ctags | Test/bug2374109.vhd | 98 | 196 | function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/TEST_CTRL_TELEGRAM_CHECK/DEB_50MZ_100MS_SRC.vhd | 38 | 2643 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50MZ_100MS_SRC;
architecture Behavioral of DEB_50MZ_100MS_SRC is
type SV_TYPE is (DEB0, DEB1);
signal SV, n_SV, SV_M : SV_TYPE;
signal COUNT_DEB, n_COUNT_DEB, COUNT_DEB_M: std_logic_vector (23 downto 0);
signal NOT_F_50MHZ : std_logic;
signal IN_DEB_S : std_logic;
constant CONST_DEB_max: std_logic_vector := x"4C4B40";
begin
IREG_PROC: process (IN_DEB, NOT_F_50MHZ)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then IN_DEB_S <= IN_DEB;
end if;
end process;
SREG_M_PROC: process (F_50MHZ, n_SV, n_COUNT_DEB, SV_M)
begin
if (F_50MHZ'event and F_50MHZ = '1')
then
SV_M <= n_SV;
COUNT_DEB_M <= n_COUNT_DEB;
else
COUNT_DEB_M <= COUNT_DEB_M;
end if;
end process;
NOT_F_50MHZ_PROC: process (F_50MHZ)
begin
NOT_F_50MHZ <= not F_50MHZ;
end process;
SREG_S_PROC: process (NOT_F_50MHZ, SV_M, COUNT_DEB_M)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then
SV <= SV_M;
COUNT_DEB <= COUNT_DEB_M;
end if;
end process;
IL_OL_PROC: process (IN_DEB_S, SV, COUNT_DEB)
begin
case SV is
when DEB0 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB1;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB0;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB0;
end if;
end if;
when DEB1 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB1;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB1;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB1;
end if;
end if;
when Others =>
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB0;
end case;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_BYTE_CHECK/DEB_50MZ_100MS_SRC.vhd | 38 | 2643 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50MZ_100MS_SRC;
architecture Behavioral of DEB_50MZ_100MS_SRC is
type SV_TYPE is (DEB0, DEB1);
signal SV, n_SV, SV_M : SV_TYPE;
signal COUNT_DEB, n_COUNT_DEB, COUNT_DEB_M: std_logic_vector (23 downto 0);
signal NOT_F_50MHZ : std_logic;
signal IN_DEB_S : std_logic;
constant CONST_DEB_max: std_logic_vector := x"4C4B40";
begin
IREG_PROC: process (IN_DEB, NOT_F_50MHZ)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then IN_DEB_S <= IN_DEB;
end if;
end process;
SREG_M_PROC: process (F_50MHZ, n_SV, n_COUNT_DEB, SV_M)
begin
if (F_50MHZ'event and F_50MHZ = '1')
then
SV_M <= n_SV;
COUNT_DEB_M <= n_COUNT_DEB;
else
COUNT_DEB_M <= COUNT_DEB_M;
end if;
end process;
NOT_F_50MHZ_PROC: process (F_50MHZ)
begin
NOT_F_50MHZ <= not F_50MHZ;
end process;
SREG_S_PROC: process (NOT_F_50MHZ, SV_M, COUNT_DEB_M)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then
SV <= SV_M;
COUNT_DEB <= COUNT_DEB_M;
end if;
end process;
IL_OL_PROC: process (IN_DEB_S, SV, COUNT_DEB)
begin
case SV is
when DEB0 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB1;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB0;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB0;
end if;
end if;
when DEB1 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB1;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB1;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB1;
end if;
end if;
when Others =>
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB0;
end case;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/TEST2_SRAM_25MHZ_255_BYTE/DEB_50MZ_100MS_SRC.vhd | 38 | 2643 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50MZ_100MS_SRC;
architecture Behavioral of DEB_50MZ_100MS_SRC is
type SV_TYPE is (DEB0, DEB1);
signal SV, n_SV, SV_M : SV_TYPE;
signal COUNT_DEB, n_COUNT_DEB, COUNT_DEB_M: std_logic_vector (23 downto 0);
signal NOT_F_50MHZ : std_logic;
signal IN_DEB_S : std_logic;
constant CONST_DEB_max: std_logic_vector := x"4C4B40";
begin
IREG_PROC: process (IN_DEB, NOT_F_50MHZ)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then IN_DEB_S <= IN_DEB;
end if;
end process;
SREG_M_PROC: process (F_50MHZ, n_SV, n_COUNT_DEB, SV_M)
begin
if (F_50MHZ'event and F_50MHZ = '1')
then
SV_M <= n_SV;
COUNT_DEB_M <= n_COUNT_DEB;
else
COUNT_DEB_M <= COUNT_DEB_M;
end if;
end process;
NOT_F_50MHZ_PROC: process (F_50MHZ)
begin
NOT_F_50MHZ <= not F_50MHZ;
end process;
SREG_S_PROC: process (NOT_F_50MHZ, SV_M, COUNT_DEB_M)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then
SV <= SV_M;
COUNT_DEB <= COUNT_DEB_M;
end if;
end process;
IL_OL_PROC: process (IN_DEB_S, SV, COUNT_DEB)
begin
case SV is
when DEB0 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB1;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB0;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB0;
end if;
end if;
when DEB1 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB1;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB1;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB1;
end if;
end if;
when Others =>
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB0;
end case;
end process;
end Behavioral;
| gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_CPU_jtag_debug_module_wrapper.vhd | 1 | 14911 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_jtag_debug_module_wrapper is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal st_ready_test_idle : OUT STD_LOGIC;
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end entity Video_System_CPU_jtag_debug_module_wrapper;
architecture europa of Video_System_CPU_jtag_debug_module_wrapper is
component Video_System_CPU_jtag_debug_module_tck is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jtag_state_rti : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tck : IN STD_LOGIC;
signal tdi : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal vs_cdr : IN STD_LOGIC;
signal vs_sdr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal ir_out : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal sr : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal st_ready_test_idle : OUT STD_LOGIC;
signal tdo : OUT STD_LOGIC
);
end component Video_System_CPU_jtag_debug_module_tck;
component Video_System_CPU_jtag_debug_module_sysclk is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sr : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vs_udr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end component Video_System_CPU_jtag_debug_module_sysclk;
--synthesis read_comments_as_HDL on
-- component sld_virtual_jtag_basic is
--GENERIC (
-- sld_auto_instance_index : STRING;
-- sld_instance_index : NATURAL;
-- sld_ir_width : NATURAL;
-- sld_mfg_id : NATURAL;
-- sld_sim_action : STRING;
-- sld_sim_n_scan : NATURAL;
-- sld_sim_total_length : NATURAL;
-- sld_type_id : NATURAL;
-- sld_version : NATURAL
-- );
-- PORT (
-- signal virtual_state_udr : OUT STD_LOGIC;
-- signal ir_in : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal tdi : OUT STD_LOGIC;
-- signal virtual_state_sdr : OUT STD_LOGIC;
-- signal jtag_state_rti : OUT STD_LOGIC;
-- signal tck : OUT STD_LOGIC;
-- signal virtual_state_cdr : OUT STD_LOGIC;
-- signal virtual_state_uir : OUT STD_LOGIC;
-- signal ir_out : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal tdo : IN STD_LOGIC
-- );
-- end component sld_virtual_jtag_basic;
--synthesis read_comments_as_HDL off
signal internal_jdo : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal internal_jrst_n : STD_LOGIC;
signal internal_st_ready_test_idle : STD_LOGIC;
signal internal_take_action_break_a : STD_LOGIC;
signal internal_take_action_break_b : STD_LOGIC;
signal internal_take_action_break_c : STD_LOGIC;
signal internal_take_action_ocimem_a : STD_LOGIC;
signal internal_take_action_ocimem_b : STD_LOGIC;
signal internal_take_action_tracectrl : STD_LOGIC;
signal internal_take_action_tracemem_a : STD_LOGIC;
signal internal_take_action_tracemem_b : STD_LOGIC;
signal internal_take_no_action_break_a : STD_LOGIC;
signal internal_take_no_action_break_b : STD_LOGIC;
signal internal_take_no_action_break_c : STD_LOGIC;
signal internal_take_no_action_ocimem_a : STD_LOGIC;
signal internal_take_no_action_tracemem_a : STD_LOGIC;
signal sr : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vji_cdr : STD_LOGIC;
signal vji_ir_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal vji_ir_out : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal vji_rti : STD_LOGIC;
signal vji_sdr : STD_LOGIC;
signal vji_tck : STD_LOGIC;
signal vji_tdi : STD_LOGIC;
signal vji_tdo : STD_LOGIC;
signal vji_udr : STD_LOGIC;
signal vji_uir : STD_LOGIC;
begin
--Change the sld_virtual_jtag_basic's defparams to
--switch between a regular Nios II or an internally embedded Nios II.
--For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
--For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
--the_Video_System_CPU_jtag_debug_module_tck, which is an e_instance
the_Video_System_CPU_jtag_debug_module_tck : Video_System_CPU_jtag_debug_module_tck
port map(
ir_out => vji_ir_out,
jrst_n => internal_jrst_n,
sr => sr,
st_ready_test_idle => internal_st_ready_test_idle,
tdo => vji_tdo,
MonDReg => MonDReg,
break_readreg => break_readreg,
dbrk_hit0_latch => dbrk_hit0_latch,
dbrk_hit1_latch => dbrk_hit1_latch,
dbrk_hit2_latch => dbrk_hit2_latch,
dbrk_hit3_latch => dbrk_hit3_latch,
debugack => debugack,
ir_in => vji_ir_in,
jtag_state_rti => vji_rti,
monitor_error => monitor_error,
monitor_ready => monitor_ready,
reset_n => reset_n,
resetlatch => resetlatch,
tck => vji_tck,
tdi => vji_tdi,
tracemem_on => tracemem_on,
tracemem_trcdata => tracemem_trcdata,
tracemem_tw => tracemem_tw,
trc_im_addr => trc_im_addr,
trc_on => trc_on,
trc_wrap => trc_wrap,
trigbrktype => trigbrktype,
trigger_state_1 => trigger_state_1,
vs_cdr => vji_cdr,
vs_sdr => vji_sdr,
vs_uir => vji_uir
);
--the_Video_System_CPU_jtag_debug_module_sysclk, which is an e_instance
the_Video_System_CPU_jtag_debug_module_sysclk : Video_System_CPU_jtag_debug_module_sysclk
port map(
jdo => internal_jdo,
take_action_break_a => internal_take_action_break_a,
take_action_break_b => internal_take_action_break_b,
take_action_break_c => internal_take_action_break_c,
take_action_ocimem_a => internal_take_action_ocimem_a,
take_action_ocimem_b => internal_take_action_ocimem_b,
take_action_tracectrl => internal_take_action_tracectrl,
take_action_tracemem_a => internal_take_action_tracemem_a,
take_action_tracemem_b => internal_take_action_tracemem_b,
take_no_action_break_a => internal_take_no_action_break_a,
take_no_action_break_b => internal_take_no_action_break_b,
take_no_action_break_c => internal_take_no_action_break_c,
take_no_action_ocimem_a => internal_take_no_action_ocimem_a,
take_no_action_tracemem_a => internal_take_no_action_tracemem_a,
clk => clk,
ir_in => vji_ir_in,
sr => sr,
vs_udr => vji_udr,
vs_uir => vji_uir
);
--vhdl renameroo for output signals
jdo <= internal_jdo;
--vhdl renameroo for output signals
jrst_n <= internal_jrst_n;
--vhdl renameroo for output signals
st_ready_test_idle <= internal_st_ready_test_idle;
--vhdl renameroo for output signals
take_action_break_a <= internal_take_action_break_a;
--vhdl renameroo for output signals
take_action_break_b <= internal_take_action_break_b;
--vhdl renameroo for output signals
take_action_break_c <= internal_take_action_break_c;
--vhdl renameroo for output signals
take_action_ocimem_a <= internal_take_action_ocimem_a;
--vhdl renameroo for output signals
take_action_ocimem_b <= internal_take_action_ocimem_b;
--vhdl renameroo for output signals
take_action_tracectrl <= internal_take_action_tracectrl;
--vhdl renameroo for output signals
take_action_tracemem_a <= internal_take_action_tracemem_a;
--vhdl renameroo for output signals
take_action_tracemem_b <= internal_take_action_tracemem_b;
--vhdl renameroo for output signals
take_no_action_break_a <= internal_take_no_action_break_a;
--vhdl renameroo for output signals
take_no_action_break_b <= internal_take_no_action_break_b;
--vhdl renameroo for output signals
take_no_action_break_c <= internal_take_no_action_break_c;
--vhdl renameroo for output signals
take_no_action_ocimem_a <= internal_take_no_action_ocimem_a;
--vhdl renameroo for output signals
take_no_action_tracemem_a <= internal_take_no_action_tracemem_a;
--synthesis translate_off
vji_tck <= std_logic'('0');
vji_tdi <= std_logic'('0');
vji_sdr <= std_logic'('0');
vji_cdr <= std_logic'('0');
vji_rti <= std_logic'('0');
vji_uir <= std_logic'('0');
vji_udr <= std_logic'('0');
vji_ir_in <= std_logic_vector'("00");
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- Video_System_CPU_jtag_debug_module_phy : sld_virtual_jtag_basic
-- generic map(
-- sld_auto_instance_index => "YES",
-- sld_instance_index => 0,
-- sld_ir_width => 2,
-- sld_mfg_id => 70,
-- sld_sim_action => "",
-- sld_sim_n_scan => 0,
-- sld_sim_total_length => 0,
-- sld_type_id => 34,
-- sld_version => 3
-- )
-- port map(
-- ir_in => vji_ir_in,
-- ir_out => vji_ir_out,
-- jtag_state_rti => vji_rti,
-- tck => vji_tck,
-- tdi => vji_tdi,
-- tdo => vji_tdo,
-- virtual_state_cdr => vji_cdr,
-- virtual_state_sdr => vji_sdr,
-- virtual_state_udr => vji_udr,
-- virtual_state_uir => vji_uir
-- );
--
--synthesis read_comments_as_HDL off
end europa;
| gpl-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_green_leds.vhd | 1 | 2868 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_green_leds is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal write_n : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal out_port : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity tracking_camera_system_green_leds;
architecture europa of tracking_camera_system_green_leds is
signal clk_en : STD_LOGIC;
signal data_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal read_mux_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
begin
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
read_mux_out <= A_REP(to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 8) AND data_out;
process (clk, reset_n)
begin
if reset_n = '0' then
data_out <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
if std_logic'(((chipselect AND NOT write_n) AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))))) = '1' then
data_out <= writedata(7 DOWNTO 0);
end if;
end if;
end process;
readdata <= std_logic_vector'("00000000000000000000000000000000") OR (std_logic_vector'("000000000000000000000000") & (read_mux_out));
out_port <= data_out;
end europa;
| gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/memory/src/dpRamSplxNbe-rtl-a.vhd | 3 | 4018 | -------------------------------------------------------------------------------
--! @file dpRamSplxNbe-a.vhd
--
--! @brief Simplex Dual Port Ram without byteenables
--
--! @details This is the Simplex DPRAM without byteenables for Xilinx platforms.
--! The DPRAM has one write and one read port only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of dpRamSplxNbe is
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port B readport
signal readdataB : tDataPort;
begin
-- assign readdata to ports
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
if iWriteEnable_A = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A))) := iWritedata_A;
end if; --writeenable
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The read process is done
--! with every rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/nShiftRegRtl.vhd | 3 | 5408 | -------------------------------------------------------------------------------
--! @file nShiftRegRtl.vhd
--
--! @brief Shift register with n-bit-width
--
--! @details This shift register implementation provides a configurable width.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity nShiftReg is
generic (
--! Data width
gWidth : natural := 8;
--! Number of tabs
gTabs : natural := 4;
--! Shift direction ("left" or "right")
gShiftDir : string := "left"
);
port (
--! Asynchronous reset
iArst : in std_logic;
--! Clock
iClk : in std_logic;
--! Parallel Load
iLoad : in std_logic;
--! Shift Enable
iShift : in std_logic;
--! Load Data (gTabs x gWidth)
iLoadData : in std_logic_vector(gWidth*gTabs-1 downto 0);
--! Parallel Output Data
oParData : out std_logic_vector(gWidth*gTabs-1 downto 0);
--! Input Shift Data
iData : in std_logic_vector(gWidth-1 downto 0);
--! Ouptut Shift Data
oData : out std_logic_vector(gWidth-1 downto 0)
);
end nShiftReg;
architecture rtl of nShiftReg is
--! Shift register type
type tShiftReg is
array (gTabs-1 downto 0) of std_logic_vector(gWidth-1 downto 0);
--! Function to convert std_logic_vector into tShiftReg
function convStdLogicToShiftReg (din : std_logic_vector)
return tShiftReg is
variable vTmp : tShiftReg;
begin
--default
vTmp := (others => (others => cInactivated));
--loop tab-wise
for i in gTabs-1 downto 0 loop
vTmp(i) := din((i+1)*gWidth-1 downto i*gWidth);
end loop;
return vTmp;
end function;
--! Function to convert tShiftReg into std_logic_vector
function convShiftRegToStdLogic (din : tShiftReg)
return std_logic_vector is
variable vTmp : std_logic_vector(gWidth*gTabs-1 downto 0);
begin
--default
vTmp := (others => cInactivated);
--loop tab-wise
for i in gTabs-1 downto 0 loop
vTmp((i+1)*gWidth-1 downto i*gWidth) := din(i);
end loop;
return vTmp;
end function;
--! Shift register
signal reg, reg_next : tShiftReg;
begin
assert (gShiftDir = "left" or gShiftDir = "right") report
"Set either left or right for shift direction!" severity failure;
--serial output
oData <= reg(reg'right) when gShiftDir = "right" else
reg(reg'left);
--parallel output
oParData <= convShiftRegToStdLogic(reg);
--! Process doing loading and shifting
comb : process (
reg,
iLoad, iShift,
iLoadData, iData
)
begin
--default
reg_next <= reg;
if iLoad = cActivated then
reg_next <= convStdLogicToShiftReg(iLoadData);
elsif iShift = cActivated then
if gShiftDir = "right" then
reg_next <= iData & reg(reg'left downto 1);
else
reg_next <= reg(reg'left-1 downto 0) & iData;
end if;
end if;
end process;
--! Register process
regClk : process(iArst, iClk)
begin
if iArst = cActivated then
reg <= (others => (others => cInactivated));
elsif rising_edge(iClk) then
reg <= reg_next;
end if;
end process;
end rtl;
| gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/parallelinterface/src/prlMaster-rtl-ea.vhd | 3 | 13028 | -------------------------------------------------------------------------------
--! @file prlMaster-rtl-ea.vhd
--! @brief Multiplexed memory mapped master
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use numeric std
use ieee.numeric_std.all;
--! Use libcommon library
library libcommon;
--! Use global package
use libcommon.global.all;
entity prlMaster is
generic (
--! Enable multiplexed address/data-bus mode (0 = FALSE)
gEnableMux : natural := 0;
--! Data bus width
gDataWidth : natural := 16;
--! Address bus width
gAddrWidth : natural := 16;
--! Address low
gAddrLow : natural := 0;
--! Ad bus width (valid when gEnableMux /= FALSE)
gAdWidth : natural := 16
);
port (
--! Clock
iClk : in std_logic;
--! Reset
iRst : in std_logic;
-- Memory mapped slave
--! Address
iSlv_address : in std_logic_vector(gAddrWidth-1 downto gAddrLow);
--! Read strobe
iSlv_read : in std_logic;
--! Readdata
oSlv_readdata : out std_logic_vector(gDataWidth-1 downto 0);
--! Write strobe
iSlv_write : in std_logic;
--! Writedata
iSlv_writedata : in std_logic_vector(gDataWidth-1 downto 0);
--! Waitrequest
oSlv_waitrequest : out std_logic;
--! Byteenable
iSlv_byteenable : in std_logic_vector(gDataWidth/8-1 downto 0);
-- Memory mapped multiplexed master
--! Chipselect
oPrlMst_cs : out std_logic;
-- Multiplexed AD-bus
--! Multiplexed address data bus input
iPrlMst_ad_i : in std_logic_vector(gAdWidth-1 downto 0);
--! Multiplexed address data bus output
oPrlMst_ad_o : out std_logic_vector(gAdWidth-1 downto 0);
--! Multiplexed address data bus enable
oPrlMst_ad_oen : out std_logic;
-- Demultiplexed AD-bus
--! Address bus
oPrlMst_addr : out std_logic_vector(gAddrWidth-1 downto 0);
--! Data bus in
iPrlMst_data_i : in std_logic_vector(gDataWidth-1 downto 0);
--! Data bus out
oPrlMst_data_o : out std_logic_vector(gDataWidth-1 downto 0);
--! Data bus outenable
oPrlMst_data_oen : out std_logic;
--! Byteenable
oPrlMst_be : out std_logic_vector(gDataWidth/8-1 downto 0);
--! Address latch enable
oPrlMst_ale : out std_logic;
--! Write strobe
oPrlMst_wr : out std_logic;
--! Read strobe
oPrlMst_rd : out std_logic;
--! Acknowledge
iPrlMst_ack : in std_logic
);
end entity prlMaster;
architecture rtl of prlMaster is
constant cCount_AleDisable : std_logic_vector := "011";
constant cCount_AleExit : std_logic_vector := "101";
constant cCount_max : std_logic_vector := "111";
constant cCountWidth : natural := cCount_max'length;
-- State machine for bus timing
type tFsm is (
sIdle,
sAle,
sWrd,
sHold
);
-- Synchronized ack signal
signal ack : std_logic;
-- Rising edge of ack signal
signal ack_p : std_logic;
--! This record holds all output registers to the bus.
type tReg is record
address : std_logic_vector(gAddrWidth-1 downto 0);
byteenable : std_logic_vector(gDataWidth/8-1 downto 0);
write : std_logic;
read : std_logic;
chipselect : std_logic;
data : std_logic_vector(gDataWidth-1 downto 0);
data_oen : std_logic;
data_in : std_logic_vector(gDataWidth-1 downto 0);
ad : std_logic_vector(gAdWidth-1 downto 0);
ad_oen : std_logic;
ale : std_logic;
fsm : tFsm;
count : std_logic_vector(cCountWidth-1 downto 0);
count_rst : std_logic;
end record;
-- Initialization vector of output registers
constant cRegInit : tReg := (
address => (others => cInactivated),
byteenable => (others => cInactivated),
write => cInactivated,
read => cInactivated,
chipselect => cInactivated,
data => (others => cInactivated),
data_oen => cInactivated,
data_in => (others => cInactivated),
ad => (others => cInactivated),
ad_oen => cInactivated,
ale => cInactivated,
fsm => sIdle,
count => (others => cInactivated),
count_rst => cInactivated
);
-- Register state
signal reg : tReg;
-- Next register state
signal reg_next : tReg;
begin
-- MAP IOs
oSlv_waitrequest <= not ack_p;
oSlv_readdata <= reg.data_in;
oPrlMst_be <= reg.byteenable;
oPrlMst_wr <= reg.write;
oPrlMst_rd <= reg.read;
oPrlMst_cs <= reg.chipselect;
--! Generate mux bus IOs. Demux bus is incactive.
genMux : if gEnableMux /= 0 generate
-- MUX
oPrlMst_ale <= reg.ale;
oPrlMst_ad_o <= reg.ad;
oPrlMst_ad_oen <= reg.ad_oen;
oPrlMst_addr <= (others => cInactivated);
oPrlMst_data_o <= (others => cInactivated);
oPrlMst_data_oen <= cInactivated;
-- iPrlMst_data_i is ignored
end generate genMux;
--! Generate demux bus IOs. Mux bus is incactive.
genDemux : if gEnableMux = 0 generate
-- DEMUX
oPrlMst_addr <= reg.address;
oPrlMst_data_o <= reg.data;
oPrlMst_data_oen <= reg.data_oen;
oPrlMst_ale <= cInactivated;
oPrlMst_ad_o <= (others => cInactivated);
oPrlMst_ad_oen <= cInactivated;
-- iPrlMst_ad_i is ignored
end generate genDemux;
--! This is the clock register process.
regClk : process(iRst, iClk)
begin
if iRst = cActivated then
reg <= cRegInit;
elsif rising_edge(iClk) then
reg <= reg_next;
end if;
end process regClk;
--! This is the next register state process.
combReg : process (
reg, ack,
iSlv_read,
iSlv_write,
iSlv_byteenable,
iSlv_address,
iSlv_writedata,
iPrlMst_ad_i,
iPrlMst_data_i
)
begin
-- default
reg_next <= reg;
-- counter reset active by default
reg_next.count_rst <= cActivated;
if reg.count_rst = cActivated then
reg_next.count <= (others => cInactivated);
else
reg_next.count <= std_logic_vector(unsigned(reg.count) + 1);
end if;
case reg.fsm is
when sIdle =>
reg_next.chipselect <= cInactivated;
reg_next.ale <= cInactivated;
reg_next.ad_oen <= cInactivated;
reg_next.data_oen <= cInactivated;
reg_next.read <= cInactivated;
reg_next.write <= cInactivated;
-- Start transaction if there is either a read or write.
if iSlv_write = cActivated or iSlv_read = cActivated then
reg_next.chipselect <= cActivated;
reg_next.byteenable <= iSlv_byteenable;
if gEnableMux /= 0 then
-- MUX mode
reg_next.fsm <= sAle;
reg_next.ale <= cActivated;
reg_next.ad_oen <= cActivated;
reg_next.ad <= (others => cInactivated);
reg_next.ad(iSlv_address'range) <= iSlv_address;
else
-- DEMUX mode
reg_next.fsm <= sWrd;
reg_next.write <= iSlv_write;
reg_next.read <= iSlv_read;
reg_next.data <= iSlv_writedata;
reg_next.data_oen <= iSlv_write;
reg_next.address <= iSlv_address;
end if;
end if;
when sAle =>
-- Use counter to generate ale timing.
reg_next.count_rst <= cInactivated;
if reg.count = cCount_AleDisable then
reg_next.ale <= cInactivated;
elsif reg.count = cCount_AleExit then
reg_next.count_rst <= cActivated;
reg_next.fsm <= sWrd;
reg_next.write <= iSlv_write;
reg_next.read <= iSlv_read;
reg_next.ad_oen <= iSlv_write;
reg_next.ad <= (others => cInactivated);
reg_next.ad(iSlv_writedata'range) <= iSlv_writedata;
end if;
when sWrd =>
if ack = cActivated then
reg_next.fsm <= sHold;
reg_next.count_rst <= cActivated;
reg_next.chipselect <= cInactivated;
reg_next.read <= cInactivated;
reg_next.write <= cInactivated;
reg_next.ad_oen <= cInactivated;
reg_next.data_oen <= cInactivated;
if reg.read = cActivated then
if gEnableMux /= 0 then
reg_next.data_in <= iPrlMst_ad_i(reg.data_in'range);
else
reg_next.data_in <= iPrlMst_data_i(reg.data_in'range);
end if;
end if;
end if;
when sHold =>
if ack = cInactivated then
reg_next.fsm <= sIdle;
reg_next.count_rst <= cActivated;
end if;
end case;
end process combReg;
--! Synchronizer to sync ack input.
syncAck : entity libcommon.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iPrlMst_ack,
oSync => ack
);
--! Detect rising edge of ack signal to generate waitrequest neg. pulse.
edgeAck : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => ack,
oRising => ack_p,
oFalling => open,
oAny => open
);
end architecture rtl;
| gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/openmac/src/axi_openmac-rtl-ea.vhd | 3 | 72507 | -------------------------------------------------------------------------------
--! @file axi_openmac-rtl-ea.vhd
--
--! @brief OpenMAC toplevel for Xilinx
--
--! @details This is the openMAC toplevel for Xilinx platform with AXI.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
--! Common Xilinx library
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
--! AXI Lite IPIF library
library axi_lite_ipif_v1_01_a;
--! Use AXI lite ipif
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
--! AXI Master Burst library
library axi_master_burst_v1_00_a;
--! Use AXI master burst
use axi_master_burst_v1_00_a.axi_master_burst;
--! Unisim library
library unisim;
--! Use ODDR2 instance primitive
use unisim.vcomponents.oddr2;
entity axi_openmac is
generic (
-----------------------------------------------------------------------
-- General parameters
-----------------------------------------------------------------------
--! Xilinx FPGA familiy
C_FAMILY : string := "spartan6";
-----------------------------------------------------------------------
-- AXI DMA
-----------------------------------------------------------------------
--! AXI master DMA address width
C_M_AXI_MAC_DMA_ADDR_WIDTH : integer := 32;
--! AXI master DMA data width
C_M_AXI_MAC_DMA_DATA_WIDTH : integer := 32;
--! AXI master DMA native data width
C_M_AXI_MAC_DMA_NATIVE_DWIDTH : integer := 32;
--! AXI master DMA burst length width
C_M_AXI_MAC_DMA_LENGTH_WIDTH : integer := 12;
--! AXI master DMA burst length
C_M_AXI_MAC_DMA_MAX_BURST_LEN : integer := 16;
-----------------------------------------------------------------------
-- AXI REG
-----------------------------------------------------------------------
--! AXI slave REG address ranges
C_S_AXI_MAC_REG_NUM_ADDR_RANGES : integer := 2;
--! AXI slave REG range 0 base
C_S_AXI_MAC_REG_RNG0_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave REG range 0 high
C_S_AXI_MAC_REG_RNG0_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG range 1 base
C_S_AXI_MAC_REG_RNG1_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave REG range 1 high
C_S_AXI_MAC_REG_RNG1_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG minimum size
C_S_AXI_MAC_REG_MIN_SIZE : std_logic_vector := x"00001fff";
--! AXI slave REG data width
C_S_AXI_MAC_REG_DATA_WIDTH : integer := 32;
--! AXI slave REG address width
C_S_AXI_MAC_REG_ADDR_WIDTH : integer := 32;
--! AXI slave REG clock frequency
C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 50000000;
--! AXI slave REG use write strobes
C_S_AXI_MAC_REG_USE_WSTRB : integer := 1;
--! AXI slave REG enable data phase timeout timer
C_S_AXI_MAC_REG_DPHASE_TIMEOUT : integer := 0;
-----------------------------------------------------------------------
-- AXI REG
-----------------------------------------------------------------------
--! AXI slave PKT base
C_S_AXI_MAC_PKT_BASEADDR : std_logic_vector := x"ffffffff";
--! AXI slave PKT high
C_S_AXI_MAC_PKT_HIGHADDR : std_logic_vector := x"00000000";
--! AXI slave REG minimum size
C_S_AXI_MAC_PKT_MIN_SIZE : std_logic_vector := x"0000ffff";
--! AXI slave PKT data width
C_S_AXI_MAC_PKT_DATA_WIDTH : integer := 32;
--! AXI slave PKT address width
C_S_AXI_MAC_PKT_ADDR_WIDTH : integer := 32;
--! AXI slave PKT use write strobes
C_S_AXI_MAC_PKT_USE_WSTRB : integer := 1;
--! AXI slave PKT enable data phase timeout timer
C_S_AXI_MAC_PKT_DPHASE_TIMEOUT : integer := 0;
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := cPhyPortRmii;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := cFalse;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := cFalse;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := cPktBufLocal;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := cPktBufLocal;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Enable pulse timer
gTimerEnablePulse : natural := cFalse;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := cFalse;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
iClk50 : in std_logic;
--! Twice main clock used for Rmii Tx path
iClk100 : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! AXI slave REG clock
S_AXI_MAC_REG_ACLK : in std_logic;
--! AXI slave REG reset (low-active)
S_AXI_MAC_REG_ARESETN : in std_logic;
--! AXI slave REG address read valid
S_AXI_MAC_REG_ARVALID : in std_logic;
--! AXI slave REG address write valid
S_AXI_MAC_REG_AWVALID : in std_logic;
--! AXI slave REG response ready
S_AXI_MAC_REG_BREADY : in std_logic;
--! AXI slave REG read ready
S_AXI_MAC_REG_RREADY : in std_logic;
--! AXI slave REG write valid
S_AXI_MAC_REG_WVALID : in std_logic;
--! AXI slave REG read address
S_AXI_MAC_REG_ARADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
--! AXI slave REG write address
S_AXI_MAC_REG_AWADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
--! AXI slave REG write data
S_AXI_MAC_REG_WDATA : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
--! AXI slave REG write strobe
S_AXI_MAC_REG_WSTRB : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
--! AXI slave REG read address ready
S_AXI_MAC_REG_ARREADY : out std_logic;
--! AXI slave REG write address ready
S_AXI_MAC_REG_AWREADY : out std_logic;
--! AXI slave REG write response valid
S_AXI_MAC_REG_BVALID : out std_logic;
--! AXI slave REG read valid
S_AXI_MAC_REG_RVALID : out std_logic;
--! AXI slave REG write ready
S_AXI_MAC_REG_WREADY : out std_logic;
--! AXI slave REG write response
S_AXI_MAC_REG_BRESP : out std_logic_vector(1 downto 0);
--! AXI slave REG read data
S_AXI_MAC_REG_RDATA : out std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
--! AXI slave REG read response
S_AXI_MAC_REG_RRESP : out std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! AXI slave PKT clock
S_AXI_MAC_PKT_ACLK : in std_logic;
--! AXI slave PKT reset (low-active)
S_AXI_MAC_PKT_ARESETN : in std_logic;
--! AXI slave PKT address read valid
S_AXI_MAC_PKT_ARVALID : in std_logic;
--! AXI slave PKT address write valid
S_AXI_MAC_PKT_AWVALID : in std_logic;
--! AXI slave PKT response ready
S_AXI_MAC_PKT_BREADY : in std_logic;
--! AXI slave PKT read ready
S_AXI_MAC_PKT_RREADY : in std_logic;
--! AXI slave PKT write valid
S_AXI_MAC_PKT_WVALID : in std_logic;
--! AXI slave PKT read address
S_AXI_MAC_PKT_ARADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
--! AXI slave PKT write address
S_AXI_MAC_PKT_AWADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
--! AXI slave PKT write data
S_AXI_MAC_PKT_WDATA : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
--! AXI slave PKT write strobe
S_AXI_MAC_PKT_WSTRB : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
--! AXI slave PKT read address ready
S_AXI_MAC_PKT_ARREADY : out std_logic;
--! AXI slave PKT write address ready
S_AXI_MAC_PKT_AWREADY : out std_logic;
--! AXI slave PKT write response valid
S_AXI_MAC_PKT_BVALID : out std_logic;
--! AXI slave PKT read valid
S_AXI_MAC_PKT_RVALID : out std_logic;
--! AXI slave PKT write ready
S_AXI_MAC_PKT_WREADY : out std_logic;
--! AXI slave PKT write response
S_AXI_MAC_PKT_BRESP : out std_logic_vector(1 downto 0);
--! AXI slave PKT read data
S_AXI_MAC_PKT_RDATA : out std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
--! AXI slave PKT read response
S_AXI_MAC_PKT_RRESP : out std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! DMA master clock
M_AXI_MAC_DMA_ACLK : in std_logic;
--! DMA master reset (low-active)
M_AXI_MAC_DMA_ARESETN : in std_logic;
--! AXI master DMA error
M_AXI_MAC_DMA_MD_ERROR : out std_logic;
--! AXI master DMA read address ready
M_AXI_MAC_DMA_ARREADY : in std_logic;
--! AXI master DMA write address ready
M_AXI_MAC_DMA_AWREADY : in std_logic;
--! AXI master DMA write response ready
M_AXI_MAC_DMA_BVALID : in std_logic;
--! AXI master DMA read last
M_AXI_MAC_DMA_RLAST : in std_logic;
--! AXI master DMA read valid
M_AXI_MAC_DMA_RVALID : in std_logic;
--! AXI master DMA write ready
M_AXI_MAC_DMA_WREADY : in std_logic;
--! AXI master DMA write response
M_AXI_MAC_DMA_BRESP : in std_logic_vector(1 downto 0);
--! AXI master DMA read data
M_AXI_MAC_DMA_RDATA : in std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
--! AXI master DMA read response
M_AXI_MAC_DMA_RRESP : in std_logic_vector(1 downto 0);
--! AXI master DMA read address valid
M_AXI_MAC_DMA_ARVALID : out std_logic;
--! AXI master DMA write address valid
M_AXI_MAC_DMA_AWVALID : out std_logic;
--! AXI master DMA response ready
M_AXI_MAC_DMA_BREADY : out std_logic;
--! AXI master DMA read ready
M_AXI_MAC_DMA_RREADY : out std_logic;
--! AXI master DMA write last
M_AXI_MAC_DMA_WLAST : out std_logic;
--! AXI master DMA write valid
M_AXI_MAC_DMA_WVALID : out std_logic;
--! AXI master DMA read address
M_AXI_MAC_DMA_ARADDR : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
--! AXI master DMA burst type
M_AXI_MAC_DMA_ARBURST : out std_logic_vector(1 downto 0);
--! AXI master DMA memory type
M_AXI_MAC_DMA_ARCACHE : out std_logic_vector(3 downto 0);
--! AXI master DMA burst length
M_AXI_MAC_DMA_ARLEN : out std_logic_vector(7 downto 0);
--! AXI master DMA protection type
M_AXI_MAC_DMA_ARPROT : out std_logic_vector(2 downto 0);
--! AXI master DMA burst size
M_AXI_MAC_DMA_ARSIZE : out std_logic_vector(2 downto 0);
--! AXI master DMA write address
M_AXI_MAC_DMA_AWADDR : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
--! AXI master DMA burst type
M_AXI_MAC_DMA_AWBURST : out std_logic_vector(1 downto 0);
--! AXI master DMA memory type
M_AXI_MAC_DMA_AWCACHE : out std_logic_vector(3 downto 0);
--! AXI master DMA burst length
M_AXI_MAC_DMA_AWLEN : out std_logic_vector(7 downto 0);
--! AXI master DMA protection type
M_AXI_MAC_DMA_AWPROT : out std_logic_vector(2 downto 0);
--! AXI master DMA burst size
M_AXI_MAC_DMA_AWSIZE : out std_logic_vector(2 downto 0);
--! AXI master DMA write data
M_AXI_MAC_DMA_WDATA : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
--! AXI master DMA write strobe
M_AXI_MAC_DMA_WSTRB : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH/8-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
TIMER_IRQ : out std_logic;
--! MAC interrupt
MAC_IRQ : out std_logic;
--! MAC TIMER pulse interrupt
TIMER_PULSE_IRQ : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Clock ports (optional)
oRmii_clk : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx Crs data valid ports
iRmii_rxCrsDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx data ports
iRmii_rxData : in std_logic_vector(gPhyPortCount*2-1 downto 0);
--! Rmii Rx error ports
iRmii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx enable ports
oRmii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx data ports
oRmii_txData : out std_logic_vector(gPhyPortCount*2-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx data valid ports
iMii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx data ports
iMii_rxData : in std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Rx error ports
iMii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
iMii_rxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx enable ports
oMii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx data ports
oMii_txData : out std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Tx Clocks
iMii_txClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
oSmi_nPhyRst : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
oSmi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O input
iSmi_dio : in std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O output
oSmi_dio : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/O tristate
oSmi_dio_tri : out std_logic;
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
oPktActivity : out std_logic
);
end axi_openmac;
architecture rtl of axi_openmac is
--! Address zero padding vector
constant cZeroPadAddress : std_logic_vector(31 downto 0) := (others => cInactivated);
--! Address array for MAC REG IPIF
constant cMacReg_addressArray : SLV64_ARRAY_TYPE := (
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG0_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG0_HIGHADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG1_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_REG_RNG1_HIGHADDR)
);
--! Address array for PKT BUF IPIF
constant cPktBuf_addressArray : SLV64_ARRAY_TYPE := (
(cZeroPadAddress & C_S_AXI_MAC_PKT_BASEADDR),
(cZeroPadAddress & C_S_AXI_MAC_PKT_HIGHADDR)
);
--! Chipselect for MAC REG --> MAC REG
constant cMacReg_csMacReg : natural := 1;
--! Chipselect for MAC REG --> MAC TIMER
constant cMacReg_csMacTimer : natural := 0;
--! Chipselect for PKT BUF
constant cPktBuf_cs : natural := 0;
--! Clock Reset type
type tClkRst is record
clk : std_logic;
rst : std_logic;
regClk : std_logic;
regRst : std_logic;
dmaClk : std_logic;
dmaRst : std_logic;
pktClk : std_logic;
pktRst : std_logic;
clk2x : std_logic;
end record;
--! Mac Reg type
type tMacReg is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
byteenable : std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(cMacRegAddrWidth-1 downto 0);
writedata : std_logic_vector(cMacRegDataWidth-1 downto 0);
readdata : std_logic_vector(cMacRegDataWidth-1 downto 0);
end record;
--! Mac Timer type
type tMacTimer is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
address : std_logic_vector(cMacTimerAddrWidth-1 downto 0);
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
writedata : std_logic_vector(cMacTimerDataWidth-1 downto 0);
readdata : std_logic_vector(cMacTimerDataWidth-1 downto 0);
end record;
--! Pkt Buf type
type tPktBuf is record
chipselect : std_logic;
write : std_logic;
read : std_logic;
waitrequest : std_logic;
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(gPacketBufferLog2Size-1 downto 0);
writedata : std_logic_vector(cPktBufDataWidth-1 downto 0);
readdata : std_logic_vector(cPktBufDataWidth-1 downto 0);
end record;
--! Dma type
type tDma is record
write : std_logic;
read : std_logic;
waitrequest : std_logic;
readdatavalid : std_logic;
byteenable : std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
address : std_logic_vector(gDmaAddrWidth-1 downto 0);
burstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
burstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
writedata : std_logic_vector(gDmaDataWidth-1 downto 0);
readdata : std_logic_vector(gDmaDataWidth-1 downto 0);
end record;
--! AXI lite slave for MAC REG
type tAxiSlaveMacReg is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
axi_awaddr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
axi_awvalid : std_logic;
axi_awready : std_logic;
axi_wdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
axi_wvalid : std_logic;
axi_wready : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
axi_bvalid : std_logic;
axi_bready : std_logic;
axi_araddr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
axi_arvalid : std_logic;
axi_arready : std_logic;
axi_rdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rvalid : std_logic;
axi_rready : std_logic;
ipif_clk : std_logic;
ipif_resetn : std_logic;
ipif_addr : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
ipif_rnw : std_logic;
ipif_be : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH/8-1 downto 0);
ipif_cs : std_logic_vector(((cMacReg_addressArray'length)/2-1) downto 0);
ipif_wrdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
ipif_rddata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
ipif_wrack : std_logic;
ipif_rdack : std_logic;
ipif_error : std_logic;
end record;
--! AXI lite slave for PKT BUF
type tAxiSlavePktBuf is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
axi_awaddr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
axi_awvalid : std_logic;
axi_awready : std_logic;
axi_wdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
axi_wvalid : std_logic;
axi_wready : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
axi_bvalid : std_logic;
axi_bready : std_logic;
axi_araddr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
axi_arvalid : std_logic;
axi_arready : std_logic;
axi_rdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rvalid : std_logic;
axi_rready : std_logic;
ipif_clk : std_logic;
ipif_resetn : std_logic;
ipif_addr : std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
ipif_rnw : std_logic;
ipif_be : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH/8-1 downto 0);
ipif_cs : std_logic_vector(((cPktBuf_addressArray'length)/2-1) downto 0);
ipif_wrdata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
ipif_rddata : std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
ipif_wrack : std_logic;
ipif_rdack : std_logic;
ipif_error : std_logic;
end record;
--! AXI master for DMA
type tAxiMasterDma is record
axi_aclk : std_logic;
axi_aresetn : std_logic;
md_error : std_logic;
axi_arready : std_logic;
axi_arvalid : std_logic;
axi_araddr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
axi_arlen : std_logic_vector(7 downto 0);
axi_arsize : std_logic_vector(2 downto 0);
axi_arburst : std_logic_vector(1 downto 0);
axi_arprot : std_logic_vector(2 downto 0);
axi_arcache : std_logic_vector(3 downto 0);
axi_rready : std_logic;
axi_rvalid : std_logic;
axi_rdata : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
axi_rresp : std_logic_vector(1 downto 0);
axi_rlast : std_logic;
axi_awready : std_logic;
axi_awvalid : std_logic;
axi_awaddr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
axi_awlen : std_logic_vector(7 downto 0);
axi_awsize : std_logic_vector(2 downto 0);
axi_awburst : std_logic_vector(1 downto 0);
axi_awprot : std_logic_vector(2 downto 0);
axi_awcache : std_logic_vector(3 downto 0);
axi_wready : std_logic;
axi_wvalid : std_logic;
axi_wdata : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
axi_wstrb : std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH/8-1 downto 0);
axi_wlast : std_logic;
axi_bready : std_logic;
axi_bvalid : std_logic;
axi_bresp : std_logic_vector(1 downto 0);
ipif_mstrd_req : std_logic;
ipif_mstwr_req : std_logic;
ipif_mst_addr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
ipif_mst_length : std_logic_vector(C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
ipif_mst_be : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mst_type : std_logic;
ipif_mst_lock : std_logic;
ipif_mst_reset : std_logic;
ipif_mst_cmdack : std_logic;
ipif_mst_cmplt : std_logic;
ipif_mst_error : std_logic;
ipif_mst_rearbitrate : std_logic;
ipif_mst_cmd_timeout : std_logic;
ipif_mstrd_d : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 );
ipif_mstrd_rem : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mstrd_sof_n : std_logic;
ipif_mstrd_eof_n : std_logic;
ipif_mstrd_src_rdy_n : std_logic;
ipif_mstrd_src_dsc_n : std_logic;
ipif_mstrd_dst_rdy_n : std_logic;
ipif_mstrd_dst_dsc_n : std_logic;
ipif_mstwr_d : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
ipif_mstwr_rem : std_logic_vector(C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8-1 downto 0);
ipif_mstwr_sof_n : std_logic;
ipif_mstwr_eof_n : std_logic;
ipif_mstwr_src_rdy_n : std_logic;
ipif_mstwr_src_dsc_n : std_logic;
ipif_mstwr_dst_rdy_n : std_logic;
ipif_mstwr_dst_dsc_n : std_logic;
end record;
--! Clock xing for MAC REG port
type tClkXingMacRegPort is record
clk : std_logic;
cs : std_logic_vector(((cMacReg_addressArray'length)/2-1) downto 0);
rnw : std_logic;
readdata : std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
wrAck : std_logic;
rdAck : std_logic;
end record;
--! Clock xing for MAC REG
type tClkXingMacReg is record
rst : std_logic;
fast : tClkXingMacRegPort;
slow : tClkXingMacRegPort;
end record;
--! Data width converter for MAC REG
type tConvMacReg is record
rst : std_logic;
clk : std_logic;
master_select : std_logic;
master_write : std_logic;
master_read : std_logic;
master_byteenable : std_logic_vector(3 downto 0);
master_writedata : std_logic_vector(31 downto 0);
master_readdata : std_logic_vector(31 downto 0);
master_address : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
master_WriteAck : std_logic;
master_ReadAck : std_logic;
slave_select : std_logic;
slave_write : std_logic;
slave_read : std_logic;
slave_address : std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
slave_byteenable : std_logic_vector(1 downto 0);
slave_readdata : std_logic_vector(15 downto 0);
slave_writedata : std_logic_vector(15 downto 0);
slave_ack : std_logic;
end record;
--! IPIF handler for MAC DMA
type tIpifMasterHandler is record
rst : std_logic;
clk : std_logic;
ipif_cmdAck : std_logic;
ipif_cmplt : std_logic;
ipif_error : std_logic;
ipif_rearbitrate : std_logic;
ipif_cmdTimeout : std_logic;
ipif_type : std_logic;
ipif_addr : std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
ipif_length : std_logic_vector(C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
ipif_be : std_logic_vector(3 downto 0);
ipif_lock : std_logic;
ipif_reset : std_logic;
ipif_rdData : std_logic_vector(31 downto 0);
ipif_rdRem : std_logic_vector(3 downto 0);
ipif_rdReq : std_logic;
nIpif_rdSof : std_logic;
nIpif_rdEof : std_logic;
nIpif_rdSrcRdy : std_logic;
nIpif_rdSrcDsc : std_logic;
nIpif_rdDstRdy : std_logic;
nIpif_rdDstDsc : std_logic;
ipif_wrData : std_logic_vector(31 downto 0);
ipif_wrRem : std_logic_vector(3 downto 0);
ipif_wrReq : std_logic;
nIpif_wrSof : std_logic;
nIpif_wrEof : std_logic;
nIpif_wrSrcRdy : std_logic;
nIpif_wrSrcDsc : std_logic;
nIpif_wrDstRdy : std_logic;
nIpif_wrDstDsc : std_logic;
masterRead : std_logic;
masterWrite : std_logic;
masterAddress : std_logic_vector(gDmaAddrWidth-1 downto 0);
masterWritedata : std_logic_vector(31 downto 0);
masterBurstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
masterBurstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
masterReaddata : std_logic_vector(31 downto 0);
masterWaitrequest : std_logic;
masterReaddatavalid : std_logic;
end record;
--! Clock and resets
signal intf_clkRst : tClkRst;
--! Mac Reg
signal intf_macReg : tMacReg;
--! Mac Timer
signal intf_macTimer : tMacTimer;
--! Packet buffer
signal intf_pktBuf : tPktBuf;
--! Dma
signal intf_dma : tDma;
--! Mac Reg IPIF
signal ipif_macReg : tAxiSlaveMacReg;
--! Packet buffer IPIF
signal ipif_pktBuf : tAxiSlavePktBuf;
--! Dma IPIF
signal ipif_dma : tAxiMasterDma;
--! Clock Xing for MAC REG IPIF
signal xing_macReg : tClkXingMacReg;
--! Dara width converter for MAC REG IPIF
signal conv_macReg : tConvMacReg;
--! Dma IPIF master handler
signal ipif_dmaMasterHdler : tIpifMasterHandler;
--! Mac Tx interrupt
signal macTx_interrupt : std_logic;
--! Mac Rx interrupt
signal macRx_interrupt : std_logic;
--! Rmii Tx path
signal rmiiTx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx path
signal rmiiRx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx path
signal miiTx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx path
signal miiRx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Smi tri-state-buffer input
signal smi_data_in : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output
signal smi_data_out : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output enable
signal smi_data_outEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Map outputs
---------------------------------------------------------------------------
-- Mac interrupts are or'd to single line.
MAC_IRQ <= macTx_interrupt or macRx_interrupt;
-- Phy Tx path
rmiiPathArrayToStdLogicVector(
iVector => rmiiTx,
oEnable => oRmii_txEnable,
oData => oRmii_txData
);
miiPathArrayToStdLogicVector(
iVector => miiTx,
oEnable => oMii_txEnable,
oData => oMii_txData
);
---------------------------------------------------------------------------
-- Map inputs
---------------------------------------------------------------------------
-- Clock and resets
intf_clkRst.clk <= iClk50;
intf_clkRst.clk2x <= iClk100;
intf_clkRst.regClk <= S_AXI_MAC_REG_ACLK;
intf_clkRst.pktClk <= S_AXI_MAC_PKT_ACLK;
intf_clkRst.dmaClk <= M_AXI_MAC_DMA_ACLK;
intf_clkRst.rst <= not S_AXI_MAC_REG_ARESETN;
intf_clkRst.regRst <= not S_AXI_MAC_REG_ARESETN;
intf_clkRst.pktRst <= not S_AXI_MAC_PKT_ARESETN;
intf_clkRst.dmaRst <= not M_AXI_MAC_DMA_ARESETN;
-- Phy Rx path
stdLogicVectorToRmiiPathArray(
iEnable => iRmii_rxCrsDataValid,
iData => iRmii_rxData,
oVector => rmiiRx
);
stdLogicVectorToMiiPathArray(
iEnable => iMii_rxDataValid,
iData => iMii_rxData,
oVector => miiRx
);
---------------------------------------------------------------------------
-- Map IOs
---------------------------------------------------------------------------
-- Assign SMI IO (the tristate buffer shall be assigned by toplevel)
oSmi_dio <= smi_data_out;
oSmi_dio_tri <= not smi_data_outEnable;
smi_data_in <= iSmi_dio;
---------------------------------------------------------------------------
-- Map Instances
---------------------------------------------------------------------------
-- MAC REG --> ipif_macReg
ipif_macReg.axi_aclk <= intf_clkRst.regClk;
ipif_macReg.axi_aresetn <= not intf_clkRst.regRst;
ipif_macReg.axi_awaddr <= S_AXI_MAC_REG_AWADDR;
ipif_macReg.axi_awvalid <= S_AXI_MAC_REG_AWVALID;
S_AXI_MAC_REG_AWREADY <= ipif_macReg.axi_awready;
ipif_macReg.axi_wdata <= S_AXI_MAC_REG_WDATA;
ipif_macReg.axi_wstrb <= S_AXI_MAC_REG_WSTRB;
ipif_macReg.axi_wvalid <= S_AXI_MAC_REG_WVALID;
S_AXI_MAC_REG_WREADY <= ipif_macReg.axi_wready;
S_AXI_MAC_REG_BRESP <= ipif_macReg.axi_bresp;
S_AXI_MAC_REG_BVALID <= ipif_macReg.axi_bvalid;
ipif_macReg.axi_bready <= S_AXI_MAC_REG_BREADY;
ipif_macReg.axi_araddr <= S_AXI_MAC_REG_ARADDR;
ipif_macReg.axi_arvalid <= S_AXI_MAC_REG_ARVALID;
S_AXI_MAC_REG_ARREADY <= ipif_macReg.axi_arready;
S_AXI_MAC_REG_RDATA <= ipif_macReg.axi_rdata;
S_AXI_MAC_REG_RRESP <= ipif_macReg.axi_rresp;
S_AXI_MAC_REG_RVALID <= ipif_macReg.axi_rvalid;
ipif_macReg.axi_rready <= S_AXI_MAC_REG_RREADY;
-- xing_macReg <-- conv_macReg or intf_macTimer
--! This process assigns the read and ack path from macReg and macTimer
--! to the clock crossing slow inputs, depending on the selected target.
ASSIGN_XING_MACREG : process (conv_macReg, intf_macTimer)
begin
-- default is MAC REG source
xing_macReg.slow.readdata <= conv_macReg.master_readdata;
xing_macReg.slow.wrAck <= conv_macReg.master_WriteAck;
xing_macReg.slow.rdAck <= conv_macReg.master_ReadAck;
if intf_macTimer.chipselect = cActivated then
xing_macReg.slow.readdata <= intf_macTimer.readdata;
xing_macReg.slow.wrAck <= intf_macTimer.write and not intf_macTimer.waitrequest;
xing_macReg.slow.rdAck <= intf_macTimer.read and not intf_macTimer.waitrequest;
end if;
end process ASSIGN_XING_MACREG;
-- ipif_macReg --> xing_macReg
--unused output: ipif_macReg.ipif_resetn;
xing_macReg.rst <= intf_clkRst.regRst;
xing_macReg.fast.clk <= ipif_macReg.ipif_clk;
xing_macReg.slow.clk <= intf_clkRst.clk;
xing_macReg.fast.rnw <= ipif_macReg.ipif_rnw;
xing_macReg.fast.cs <= ipif_macReg.ipif_cs;
ipif_macReg.ipif_rddata <= xing_macReg.fast.readdata;
ipif_macReg.ipif_wrack <= xing_macReg.fast.wrAck;
ipif_macReg.ipif_rdack <= xing_macReg.fast.rdAck;
ipif_macReg.ipif_error <= cInactivated; --unused
-- ipif_macReg --> conv_macReg | xing_macReg --> conv_macReg
conv_macReg.rst <= intf_clkRst.rst;
conv_macReg.clk <= intf_clkRst.clk;
conv_macReg.master_select <= xing_macReg.slow.cs(cMacReg_csMacReg);
conv_macReg.master_write <= not xing_macReg.slow.rnw;
conv_macReg.master_read <= xing_macReg.slow.rnw;
conv_macReg.master_byteenable <= ipif_macReg.ipif_be;
conv_macReg.master_writedata <= ipif_macReg.ipif_wrdata;
conv_macReg.master_address <= ipif_macReg.ipif_addr(conv_macReg.master_address'range);
-- conv_macReg --> intf_macReg
intf_macReg.chipselect <= conv_macReg.slave_select;
intf_macReg.write <= conv_macReg.slave_write;
intf_macReg.read <= conv_macReg.slave_read;
intf_macReg.address <= conv_macReg.slave_address(intf_macReg.address'range);
intf_macReg.byteenable <= conv_macReg.slave_byteenable;
conv_macReg.slave_readdata <= intf_macReg.readdata;
intf_macReg.writedata <= conv_macReg.slave_writedata;
conv_macReg.slave_ack <= not intf_macReg.waitrequest;
-- ipif_macReg --> intf_macTimer | xing_macReg --> intf_macTimer
intf_macTimer.chipselect <= xing_macReg.slow.cs(cMacReg_csMacTimer);
intf_macTimer.write <= not xing_macReg.slow.rnw;
intf_macTimer.read <= xing_macReg.slow.rnw;
intf_macTimer.address <= ipif_macReg.ipif_addr(intf_macTimer.address'range);
intf_macTimer.byteenable <= ipif_macReg.ipif_be;
intf_macTimer.writedata <= ipif_macReg.ipif_wrdata;
-- MAC PKT --> ipif_pktBuf
ipif_pktBuf.axi_aclk <= intf_clkRst.pktClk;
ipif_pktBuf.axi_aresetn <= not intf_clkRst.pktRst;
ipif_pktBuf.axi_awaddr <= S_AXI_MAC_PKT_AWADDR;
ipif_pktBuf.axi_awvalid <= S_AXI_MAC_PKT_AWVALID;
S_AXI_MAC_PKT_AWREADY <= ipif_pktBuf.axi_awready;
ipif_pktBuf.axi_wdata <= S_AXI_MAC_PKT_WDATA;
ipif_pktBuf.axi_wstrb <= S_AXI_MAC_PKT_WSTRB;
ipif_pktBuf.axi_wvalid <= S_AXI_MAC_PKT_WVALID;
S_AXI_MAC_PKT_WREADY <= ipif_pktBuf.axi_wready;
S_AXI_MAC_PKT_BRESP <= ipif_pktBuf.axi_bresp;
S_AXI_MAC_PKT_BVALID <= ipif_pktBuf.axi_bvalid;
ipif_pktBuf.axi_bready <= S_AXI_MAC_PKT_BREADY;
ipif_pktBuf.axi_araddr <= S_AXI_MAC_PKT_ARADDR;
ipif_pktBuf.axi_arvalid <= S_AXI_MAC_PKT_ARVALID;
S_AXI_MAC_PKT_ARREADY <= ipif_pktBuf.axi_arready;
S_AXI_MAC_PKT_RDATA <= ipif_pktBuf.axi_rdata;
S_AXI_MAC_PKT_RRESP <= ipif_pktBuf.axi_rresp;
S_AXI_MAC_PKT_RVALID <= ipif_pktBuf.axi_rvalid;
ipif_pktBuf.axi_rready <= S_AXI_MAC_PKT_RREADY;
-- ipif_pktBuf --> intf_pktBuf
--unused output: ipif_pktBuf.ipif_clk
--unused output: ipif_pktBuf.ipif_resetn
intf_pktBuf.address <= ipif_pktBuf.ipif_addr(intf_pktBuf.address'range);
intf_pktBuf.write <= not ipif_pktBuf.ipif_rnw;
intf_pktBuf.read <= ipif_pktBuf.ipif_rnw;
intf_pktBuf.byteenable <= ipif_pktBuf.ipif_be;
intf_pktBuf.chipselect <= ipif_pktBuf.ipif_cs(cPktBuf_cs);
intf_pktBuf.writedata <= ipif_pktBuf.ipif_wrdata;
ipif_pktBuf.ipif_rddata <= intf_pktBuf.readdata;
ipif_pktBuf.ipif_wrack <= intf_pktBuf.chipselect and intf_pktBuf.write and not intf_pktBuf.waitrequest;
ipif_pktBuf.ipif_rdack <= intf_pktBuf.chipselect and intf_pktBuf.read and not intf_pktBuf.waitrequest;
ipif_pktBuf.ipif_error <= cInactivated; --unused
-- MAC DMA --> ipif_dma
ipif_dma.axi_aclk <= intf_clkRst.dmaClk;
ipif_dma.axi_aresetn <= not intf_clkRst.dmaRst;
M_AXI_MAC_DMA_MD_ERROR <= ipif_dma.md_error;
ipif_dma.axi_arready <= M_AXI_MAC_DMA_ARREADY;
M_AXI_MAC_DMA_ARVALID <= ipif_dma.axi_arvalid;
M_AXI_MAC_DMA_ARADDR <= ipif_dma.axi_araddr;
M_AXI_MAC_DMA_ARLEN <= ipif_dma.axi_arlen;
M_AXI_MAC_DMA_ARSIZE <= ipif_dma.axi_arsize;
M_AXI_MAC_DMA_ARBURST <= ipif_dma.axi_arburst;
M_AXI_MAC_DMA_ARPROT <= ipif_dma.axi_arprot;
M_AXI_MAC_DMA_ARCACHE <= ipif_dma.axi_arcache;
M_AXI_MAC_DMA_RREADY <= ipif_dma.axi_rready;
ipif_dma.axi_rvalid <= M_AXI_MAC_DMA_RVALID;
ipif_dma.axi_rdata <= M_AXI_MAC_DMA_RDATA;
ipif_dma.axi_rresp <= M_AXI_MAC_DMA_RRESP;
ipif_dma.axi_rlast <= M_AXI_MAC_DMA_RLAST;
ipif_dma.axi_awready <= M_AXI_MAC_DMA_AWREADY;
M_AXI_MAC_DMA_AWVALID <= ipif_dma.axi_awvalid;
M_AXI_MAC_DMA_AWADDR <= ipif_dma.axi_awaddr;
M_AXI_MAC_DMA_AWLEN <= ipif_dma.axi_awlen;
M_AXI_MAC_DMA_AWSIZE <= ipif_dma.axi_awsize;
M_AXI_MAC_DMA_AWBURST <= ipif_dma.axi_awburst;
M_AXI_MAC_DMA_AWPROT <= ipif_dma.axi_awprot;
M_AXI_MAC_DMA_AWCACHE <= ipif_dma.axi_awcache;
ipif_dma.axi_wready <= M_AXI_MAC_DMA_WREADY;
M_AXI_MAC_DMA_WVALID <= ipif_dma.axi_wvalid;
M_AXI_MAC_DMA_WDATA <= ipif_dma.axi_wdata;
M_AXI_MAC_DMA_WSTRB <= ipif_dma.axi_wstrb;
M_AXI_MAC_DMA_WLAST <= ipif_dma.axi_wlast;
M_AXI_MAC_DMA_BREADY <= ipif_dma.axi_bready;
ipif_dma.axi_bvalid <= M_AXI_MAC_DMA_BVALID;
ipif_dma.axi_bresp <= M_AXI_MAC_DMA_BRESP;
-- ipif_dma --> ipif_dmaMasterHdler
ipif_dmaMasterHdler.rst <= intf_clkRst.dmaRst;
ipif_dmaMasterHdler.clk <= intf_clkRst.dmaClk;
ipif_dma.ipif_mstrd_req <= ipif_dmaMasterHdler.ipif_rdReq;
ipif_dma.ipif_mstwr_req <= ipif_dmaMasterHdler.ipif_wrReq;
ipif_dma.ipif_mst_addr <= ipif_dmaMasterHdler.ipif_addr(ipif_dma.ipif_mst_addr'range);
ipif_dma.ipif_mst_length <= ipif_dmaMasterHdler.ipif_length;
ipif_dma.ipif_mst_be <= ipif_dmaMasterHdler.ipif_be;
ipif_dma.ipif_mst_type <= ipif_dmaMasterHdler.ipif_type;
ipif_dma.ipif_mst_lock <= ipif_dmaMasterHdler.ipif_lock;
ipif_dma.ipif_mst_reset <= ipif_dmaMasterHdler.ipif_reset;
ipif_dmaMasterHdler.ipif_cmdAck <= ipif_dma.ipif_mst_cmdack;
ipif_dmaMasterHdler.ipif_cmplt <= ipif_dma.ipif_mst_cmplt;
ipif_dmaMasterHdler.ipif_error <= ipif_dma.ipif_mst_error;
ipif_dmaMasterHdler.ipif_rearbitrate <= ipif_dma.ipif_mst_rearbitrate;
ipif_dmaMasterHdler.ipif_cmdTimeout <= ipif_dma.ipif_mst_cmd_timeout;
ipif_dmaMasterHdler.ipif_rdData <= ipif_dma.ipif_mstrd_d;
ipif_dmaMasterHdler.ipif_rdRem <= ipif_dma.ipif_mstrd_rem;
ipif_dmaMasterHdler.nIpif_rdSof <= ipif_dma.ipif_mstrd_sof_n;
ipif_dmaMasterHdler.nIpif_rdEof <= ipif_dma.ipif_mstrd_eof_n;
ipif_dmaMasterHdler.nIpif_rdSrcRdy <= ipif_dma.ipif_mstrd_src_rdy_n;
ipif_dmaMasterHdler.nIpif_rdSrcDsc <= ipif_dma.ipif_mstrd_src_dsc_n;
ipif_dma.ipif_mstrd_dst_rdy_n <= ipif_dmaMasterHdler.nIpif_rdDstRdy;
ipif_dma.ipif_mstrd_dst_dsc_n <= ipif_dmaMasterHdler.nIpif_rdDstDsc;
ipif_dma.ipif_mstwr_d <= ipif_dmaMasterHdler.ipif_wrData;
ipif_dma.ipif_mstwr_rem <= ipif_dmaMasterHdler.ipif_wrRem;
ipif_dma.ipif_mstwr_sof_n <= ipif_dmaMasterHdler.nIpif_wrSof;
ipif_dma.ipif_mstwr_eof_n <= ipif_dmaMasterHdler.nIpif_wrEof;
ipif_dma.ipif_mstwr_src_rdy_n <= ipif_dmaMasterHdler.nIpif_wrSrcRdy;
ipif_dma.ipif_mstwr_src_dsc_n <= ipif_dmaMasterHdler.nIpif_wrSrcDsc;
ipif_dmaMasterHdler.nIpif_wrDstRdy <= ipif_dma.ipif_mstwr_dst_rdy_n;
ipif_dmaMasterHdler.nIpif_wrDstDsc <= ipif_dma.ipif_mstwr_dst_dsc_n;
-- ipif_dmaMasterHdler --> intf_dma
ipif_dmaMasterHdler.masterRead <= intf_dma.read;
ipif_dmaMasterHdler.masterWrite <= intf_dma.write;
ipif_dmaMasterHdler.masterAddress <= intf_dma.address;
ipif_dmaMasterHdler.masterWritedata <= intf_dma.writedata;
ipif_dmaMasterHdler.masterBurstcount <= intf_dma.burstcount;
ipif_dmaMasterHdler.masterBurstcounter <= intf_dma.burstcounter;
intf_dma.readdata <= ipif_dmaMasterHdler.masterReaddata;
intf_dma.waitrequest <= ipif_dmaMasterHdler.masterWaitrequest;
intf_dma.readdatavalid <= ipif_dmaMasterHdler.masterReaddatavalid;
---------------------------------------------------------------------------
-- Instantiations
---------------------------------------------------------------------------
--! This is the openMAC toplevel instantiation.
THEOPENMACTOP : entity work.openmacTop
generic map (
gPhyPortCount => gPhyPortCount,
gPhyPortType => gPhyPortType,
gSmiPortCount => gSmiPortCount,
gEndianness => gEndianness,
gEnableActivity => gEnableActivity,
gEnableDmaObserver => gEnableDmaObserver,
gDmaAddrWidth => gDmaAddrWidth,
gDmaDataWidth => gDmaDataWidth,
gDmaBurstCountWidth => gDmaBurstCountWidth,
gDmaWriteBurstLength => gDmaWriteBurstLength,
gDmaReadBurstLength => gDmaReadBurstLength,
gDmaWriteFifoLength => gDmaWriteFifoLength,
gDmaReadFifoLength => gDmaReadFifoLength,
gPacketBufferLocTx => gPacketBufferLocTx,
gPacketBufferLocRx => gPacketBufferLocRx,
gPacketBufferLog2Size => gPacketBufferLog2Size,
gTimerEnablePulse => gTimerEnablePulse,
gTimerEnablePulseWidth => gTimerEnablePulseWidth,
gTimerPulseRegWidth => gTimerPulseRegWidth
)
port map (
iClk => intf_clkRst.clk,
iRst => intf_clkRst.rst,
iDmaClk => intf_clkRst.dmaClk,
iDmaRst => intf_clkRst.dmaRst,
iPktBufClk => intf_clkRst.pktClk,
iPktBufRst => intf_clkRst.pktRst,
iClk2x => intf_clkRst.clk2x,
iMacReg_chipselect => intf_macReg.chipselect,
iMacReg_write => intf_macReg.write,
iMacReg_read => intf_macReg.read,
oMacReg_waitrequest => intf_macReg.waitrequest,
iMacReg_byteenable => intf_macReg.byteenable,
iMacReg_address => intf_macReg.address,
iMacReg_writedata => intf_macReg.writedata,
oMacReg_readdata => intf_macReg.readdata,
iMacTimer_chipselect => intf_macTimer.chipselect,
iMacTimer_write => intf_macTimer.write,
iMacTimer_read => intf_macTimer.read,
oMacTimer_waitrequest => intf_macTimer.waitrequest,
iMacTimer_address => intf_macTimer.address,
iMacTimer_byteenable => intf_macTimer.byteenable,
iMacTimer_writedata => intf_macTimer.writedata,
oMacTimer_readdata => intf_macTimer.readdata,
iPktBuf_chipselect => intf_pktBuf.chipselect,
iPktBuf_write => intf_pktBuf.write,
iPktBuf_read => intf_pktBuf.read,
oPktBuf_waitrequest => intf_pktBuf.waitrequest,
iPktBuf_byteenable => intf_pktBuf.byteenable,
iPktBuf_address => intf_pktBuf.address,
iPktBuf_writedata => intf_pktBuf.writedata,
oPktBuf_readdata => intf_pktBuf.readdata,
oDma_write => intf_dma.write,
oDma_read => intf_dma.read,
iDma_waitrequest => intf_dma.waitrequest,
iDma_readdatavalid => intf_dma.readdatavalid,
oDma_byteenable => intf_dma.byteenable,
oDma_address => intf_dma.address,
oDma_burstcount => intf_dma.burstcount,
oDma_burstcounter => intf_dma.burstcounter,
oDma_writedata => intf_dma.writedata,
iDma_readdata => intf_dma.readdata,
oMacTimer_interrupt => TIMER_IRQ,
oMacTimer_pulse => TIMER_PULSE_IRQ,
oMacTx_interrupt => macTx_interrupt,
oMacRx_interrupt => macRx_interrupt,
iRmii_Rx => rmiiRx,
iRmii_RxError => iRmii_rxError,
oRmii_Tx => rmiiTx,
iMii_Rx => miiRx,
iMii_RxError => iMii_rxError,
iMii_RxClk => iMii_rxClk,
oMii_Tx => miiTx,
iMii_TxClk => iMii_txClk,
onPhy_reset => oSmi_nPhyRst,
oSmi_clk => oSmi_clk,
oSmi_data_outEnable => smi_data_outEnable,
oSmi_data_out => smi_data_out,
iSmi_data_in => smi_data_in,
oActivity => oPktActivity
);
--! The MAC REG AXI lite IPIF converts the AXI interface to IPIF.
THEMACREG_AXILITE : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_REG_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_REG_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MAC_REG_MIN_SIZE,
C_USE_WSTRB => C_S_AXI_MAC_REG_USE_WSTRB,
C_DPHASE_TIMEOUT => C_S_AXI_MAC_REG_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => cMacReg_addressArray,
C_ARD_NUM_CE_ARRAY => (1, 1),
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => ipif_macReg.axi_aclk,
S_AXI_ARESETN => ipif_macReg.axi_aresetn,
S_AXI_AWADDR => ipif_macReg.axi_awaddr,
S_AXI_AWVALID => ipif_macReg.axi_awvalid,
S_AXI_AWREADY => ipif_macReg.axi_awready,
S_AXI_WDATA => ipif_macReg.axi_wdata,
S_AXI_WSTRB => ipif_macReg.axi_wstrb,
S_AXI_WVALID => ipif_macReg.axi_wvalid,
S_AXI_WREADY => ipif_macReg.axi_wready,
S_AXI_BRESP => ipif_macReg.axi_bresp,
S_AXI_BVALID => ipif_macReg.axi_bvalid,
S_AXI_BREADY => ipif_macReg.axi_bready,
S_AXI_ARADDR => ipif_macReg.axi_araddr,
S_AXI_ARVALID => ipif_macReg.axi_arvalid,
S_AXI_ARREADY => ipif_macReg.axi_arready,
S_AXI_RDATA => ipif_macReg.axi_rdata,
S_AXI_RRESP => ipif_macReg.axi_rresp,
S_AXI_RVALID => ipif_macReg.axi_rvalid,
S_AXI_RREADY => ipif_macReg.axi_rready,
Bus2IP_Clk => ipif_macReg.ipif_clk,
Bus2IP_Resetn => ipif_macReg.ipif_resetn,
Bus2IP_Addr => ipif_macReg.ipif_addr,
Bus2IP_RNW => ipif_macReg.ipif_rnw,
Bus2IP_BE => ipif_macReg.ipif_be,
Bus2IP_CS => ipif_macReg.ipif_cs,
Bus2IP_RdCE => open, --don't need that feature
Bus2IP_WrCE => open, --don't need that feature
Bus2IP_Data => ipif_macReg.ipif_wrdata,
IP2Bus_Data => ipif_macReg.ipif_rddata,
IP2Bus_WrAck => ipif_macReg.ipif_wrack,
IP2Bus_RdAck => ipif_macReg.ipif_rdack,
IP2Bus_Error => ipif_macReg.ipif_error
);
--! The clock Xing ipcore transfers the signals in the AXI clock domain to
--! the iClk50 domain.
THEMACREG_CLKXING : entity libcommon.clkXing
generic map (
gCsNum => xing_macReg.fast.cs'length,
gDataWidth => xing_macReg.fast.readdata'length
)
port map (
iArst => xing_macReg.rst,
iFastClk => xing_macReg.fast.clk,
iFastCs => xing_macReg.fast.cs,
iFastRNW => xing_macReg.fast.rnw,
oFastReaddata => xing_macReg.fast.readdata,
oFastWrAck => xing_macReg.fast.wrAck,
oFastRdAck => xing_macReg.fast.rdAck,
iSlowClk => xing_macReg.slow.clk,
oSlowCs => xing_macReg.slow.cs,
oSlowRNW => xing_macReg.slow.rnw,
iSlowReaddata => xing_macReg.slow.readdata,
iSlowWrAck => xing_macReg.slow.wrAck,
iSlowRdAck => xing_macReg.slow.rdAck
);
--! The memory mapped slave converter changes from AXI's data width to 16 bit.
THEMACREG_MMCONV : entity work.mmSlaveConv
generic map (
gEndian => gEndianness,
gMasterAddrWidth => conv_macReg.master_address'length
)
port map (
iRst => conv_macReg.rst,
iClk => conv_macReg.clk,
iMaster_select => conv_macReg.master_select,
iMaster_write => conv_macReg.master_write,
iMaster_read => conv_macReg.master_read,
iMaster_byteenable => conv_macReg.master_byteenable,
iMaster_writedata => conv_macReg.master_writedata,
oMaster_readdata => conv_macReg.master_readdata,
iMaster_address => conv_macReg.master_address,
oMaster_WriteAck => conv_macReg.master_WriteAck,
oMaster_ReadAck => conv_macReg.master_ReadAck,
oSlave_select => conv_macReg.slave_select,
oSlave_write => conv_macReg.slave_write,
oSlave_read => conv_macReg.slave_read,
oSlave_address => conv_macReg.slave_address,
oSlave_byteenable => conv_macReg.slave_byteenable,
iSlave_readdata => conv_macReg.slave_readdata,
oSlave_writedata => conv_macReg.slave_writedata,
iSlave_ack => conv_macReg.slave_ack
);
--! Generate the packet buffer IPIF if any location is set to local.
GEN_THEMACPKT : if gPacketBufferLocRx = cPktBufLocal or gPacketBufferLocTx = cPktBufLocal generate
--! The MAC PKT BUF AXI lite IPIF converts the AXI interface to IPIF.
THEMACREG_AXILITE : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_PKT_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_PKT_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MAC_PKT_MIN_SIZE,
C_USE_WSTRB => C_S_AXI_MAC_PKT_USE_WSTRB,
C_DPHASE_TIMEOUT => C_S_AXI_MAC_PKT_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => cPktBuf_addressArray,
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => ipif_pktBuf.axi_aclk,
S_AXI_ARESETN => ipif_pktBuf.axi_aresetn,
S_AXI_AWADDR => ipif_pktBuf.axi_awaddr,
S_AXI_AWVALID => ipif_pktBuf.axi_awvalid,
S_AXI_AWREADY => ipif_pktBuf.axi_awready,
S_AXI_WDATA => ipif_pktBuf.axi_wdata,
S_AXI_WSTRB => ipif_pktBuf.axi_wstrb,
S_AXI_WVALID => ipif_pktBuf.axi_wvalid,
S_AXI_WREADY => ipif_pktBuf.axi_wready,
S_AXI_BRESP => ipif_pktBuf.axi_bresp,
S_AXI_BVALID => ipif_pktBuf.axi_bvalid,
S_AXI_BREADY => ipif_pktBuf.axi_bready,
S_AXI_ARADDR => ipif_pktBuf.axi_araddr,
S_AXI_ARVALID => ipif_pktBuf.axi_arvalid,
S_AXI_ARREADY => ipif_pktBuf.axi_arready,
S_AXI_RDATA => ipif_pktBuf.axi_rdata,
S_AXI_RRESP => ipif_pktBuf.axi_rresp,
S_AXI_RVALID => ipif_pktBuf.axi_rvalid,
S_AXI_RREADY => ipif_pktBuf.axi_rready,
Bus2IP_Clk => ipif_pktBuf.ipif_clk,
Bus2IP_Resetn => ipif_pktBuf.ipif_resetn,
Bus2IP_Addr => ipif_pktBuf.ipif_addr,
Bus2IP_RNW => ipif_pktBuf.ipif_rnw,
Bus2IP_BE => ipif_pktBuf.ipif_be,
Bus2IP_CS => ipif_pktBuf.ipif_cs,
Bus2IP_RdCE => open, --don't need that feature
Bus2IP_WrCE => open, --don't need that feature
Bus2IP_Data => ipif_pktBuf.ipif_wrdata,
IP2Bus_Data => ipif_pktBuf.ipif_rddata,
IP2Bus_WrAck => ipif_pktBuf.ipif_wrack,
IP2Bus_RdAck => ipif_pktBuf.ipif_rdack,
IP2Bus_Error => ipif_pktBuf.ipif_error
);
end generate GEN_THEMACPKT;
GEN_THEMACDMA : if gPacketBufferLocRx = cPktBufExtern or gPacketBufferLocTx = cPktBufExtern generate
--! The MAC DMA AXI master IPIF converts the AXI interface to IPIF.
THEMACDMA_AXI : entity axi_master_burst_v1_00_a.axi_master_burst
generic map (
C_M_AXI_ADDR_WIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_MAC_DMA_DATA_WIDTH,
C_MAX_BURST_LEN => C_M_AXI_MAC_DMA_MAX_BURST_LEN,
C_ADDR_PIPE_DEPTH => 1,
C_NATIVE_DATA_WIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH,
C_LENGTH_WIDTH => C_M_AXI_MAC_DMA_LENGTH_WIDTH,
C_FAMILY => C_FAMILY
)
port map (
m_axi_aclk => ipif_dma.axi_aclk,
m_axi_aresetn => ipif_dma.axi_aresetn,
md_error => ipif_dma.md_error,
m_axi_arready => ipif_dma.axi_arready,
m_axi_arvalid => ipif_dma.axi_arvalid,
m_axi_araddr => ipif_dma.axi_araddr,
m_axi_arlen => ipif_dma.axi_arlen,
m_axi_arsize => ipif_dma.axi_arsize,
m_axi_arburst => ipif_dma.axi_arburst,
m_axi_arprot => ipif_dma.axi_arprot,
m_axi_arcache => ipif_dma.axi_arcache,
m_axi_rready => ipif_dma.axi_rready,
m_axi_rvalid => ipif_dma.axi_rvalid,
m_axi_rdata => ipif_dma.axi_rdata,
m_axi_rresp => ipif_dma.axi_rresp,
m_axi_rlast => ipif_dma.axi_rlast,
m_axi_awready => ipif_dma.axi_awready,
m_axi_awvalid => ipif_dma.axi_awvalid,
m_axi_awaddr => ipif_dma.axi_awaddr,
m_axi_awlen => ipif_dma.axi_awlen,
m_axi_awsize => ipif_dma.axi_awsize,
m_axi_awburst => ipif_dma.axi_awburst,
m_axi_awprot => ipif_dma.axi_awprot,
m_axi_awcache => ipif_dma.axi_awcache,
m_axi_wready => ipif_dma.axi_wready,
m_axi_wvalid => ipif_dma.axi_wvalid,
m_axi_wdata => ipif_dma.axi_wdata,
m_axi_wstrb => ipif_dma.axi_wstrb,
m_axi_wlast => ipif_dma.axi_wlast,
m_axi_bready => ipif_dma.axi_bready,
m_axi_bvalid => ipif_dma.axi_bvalid,
m_axi_bresp => ipif_dma.axi_bresp,
ip2bus_mstrd_req => ipif_dma.ipif_mstrd_req,
ip2bus_mstwr_req => ipif_dma.ipif_mstwr_req,
ip2bus_mst_addr => ipif_dma.ipif_mst_addr,
ip2bus_mst_length => ipif_dma.ipif_mst_length,
ip2bus_mst_be => ipif_dma.ipif_mst_be,
ip2bus_mst_type => ipif_dma.ipif_mst_type,
ip2bus_mst_lock => ipif_dma.ipif_mst_lock,
ip2bus_mst_reset => ipif_dma.ipif_mst_reset,
bus2ip_mst_cmdack => ipif_dma.ipif_mst_cmdack,
bus2ip_mst_cmplt => ipif_dma.ipif_mst_cmplt,
bus2ip_mst_error => ipif_dma.ipif_mst_error,
bus2ip_mst_rearbitrate => ipif_dma.ipif_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_dma.ipif_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_dma.ipif_mstrd_d,
bus2ip_mstrd_rem => ipif_dma.ipif_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_dma.ipif_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_dma.ipif_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_dma.ipif_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_dma.ipif_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_dma.ipif_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_dma.ipif_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_dma.ipif_mstwr_d,
ip2bus_mstwr_rem => ipif_dma.ipif_mstwr_rem,
ip2bus_mstwr_sof_n => ipif_dma.ipif_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_dma.ipif_mstwr_eof_n,
ip2bus_mstwr_src_rdy_n => ipif_dma.ipif_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_dma.ipif_mstwr_src_dsc_n,
bus2ip_mstwr_dst_rdy_n => ipif_dma.ipif_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_dma.ipif_mstwr_dst_dsc_n
);
--! The IPIF master handler converts the IPIF master signals to the
--! openMAC's DMA interface.
THEMACDMA_IPIF_HANDLER : entity work.ipifMasterHandler
generic map (
gMasterAddrWidth => ipif_dmaMasterHdler.masterAddress'length,
gMasterBurstCountWidth => ipif_dmaMasterHdler.masterBurstcount'length,
gIpifAddrWidth => ipif_dmaMasterHdler.ipif_addr'length,
gIpifLength => ipif_dmaMasterHdler.ipif_length'length
)
port map (
iRst => ipif_dmaMasterHdler.rst,
iClk => ipif_dmaMasterHdler.clk,
iIpif_cmdAck => ipif_dmaMasterHdler.ipif_cmdAck,
iIpif_cmplt => ipif_dmaMasterHdler.ipif_cmplt,
iIpif_error => ipif_dmaMasterHdler.ipif_error,
iIpif_rearbitrate => ipif_dmaMasterHdler.ipif_rearbitrate,
iIpif_cmdTimeout => ipif_dmaMasterHdler.ipif_cmdTimeout,
oIpif_type => ipif_dmaMasterHdler.ipif_type,
oIpif_addr => ipif_dmaMasterHdler.ipif_addr,
oIpif_length => ipif_dmaMasterHdler.ipif_length,
oIpif_be => ipif_dmaMasterHdler.ipif_be,
oIpif_lock => ipif_dmaMasterHdler.ipif_lock,
oIpif_reset => ipif_dmaMasterHdler.ipif_reset,
iIpif_rdData => ipif_dmaMasterHdler.ipif_rdData,
iIpif_rdRem => ipif_dmaMasterHdler.ipif_rdRem,
oIpif_rdReq => ipif_dmaMasterHdler.ipif_rdReq,
inIpif_rdSof => ipif_dmaMasterHdler.nIpif_rdSof,
inIpif_rdEof => ipif_dmaMasterHdler.nIpif_rdEof,
inIpif_rdSrcRdy => ipif_dmaMasterHdler.nIpif_rdSrcRdy,
inIpif_rdSrcDsc => ipif_dmaMasterHdler.nIpif_rdSrcDsc,
onIpif_rdDstRdy => ipif_dmaMasterHdler.nIpif_rdDstRdy,
onIpif_rdDstDsc => ipif_dmaMasterHdler.nIpif_rdDstDsc,
oIpif_wrData => ipif_dmaMasterHdler.ipif_wrData,
oIpif_wrRem => ipif_dmaMasterHdler.ipif_wrRem,
oIpif_wrReq => ipif_dmaMasterHdler.ipif_wrReq,
onIpif_wrSof => ipif_dmaMasterHdler.nIpif_wrSof,
onIpif_wrEof => ipif_dmaMasterHdler.nIpif_wrEof,
onIpif_wrSrcRdy => ipif_dmaMasterHdler.nIpif_wrSrcRdy,
onIpif_wrSrcDsc => ipif_dmaMasterHdler.nIpif_wrSrcDsc,
inIpif_wrDstRdy => ipif_dmaMasterHdler.nIpif_wrDstRdy,
inIpif_wrDstDsc => ipif_dmaMasterHdler.nIpif_wrDstDsc,
iMasterRead => ipif_dmaMasterHdler.masterRead,
iMasterWrite => ipif_dmaMasterHdler.masterWrite,
iMasterAddress => ipif_dmaMasterHdler.masterAddress,
iMasterWritedata => ipif_dmaMasterHdler.masterWritedata,
iMasterBurstcount => ipif_dmaMasterHdler.masterBurstcount,
iMasterBurstcounter => ipif_dmaMasterHdler.masterBurstcounter,
oMasterReaddata => ipif_dmaMasterHdler.masterReaddata,
oMasterWaitrequest => ipif_dmaMasterHdler.masterWaitrequest,
oMasterReaddatavalid => ipif_dmaMasterHdler.masterReaddatavalid
);
end generate GEN_THEMACDMA;
GEN_RMII_CLK : if gPhyPortType = cPhyPortRmii generate
GEN_ODDR2 : for i in oRmii_clk'range generate
signal rmiiClk : std_logic;
signal nRmiiClk : std_logic;
begin
-- Assign rmii clock (used by openMAC) and the inverted to ODDR2.
rmiiClk <= intf_clkRst.clk;
nRmiiClk <= not rmiiClk;
--! This is a dual data rate output FF used to output the internal
--! RMII clock.
THEODDR2 : oddr2
generic map (
DDR_ALIGNMENT => "NONE", -- align D0 with C0 and D1 with C1 edge
INIT => '0', -- initialize Q with '0'
SRTYPE => "SYNC" -- take default, since RS are unused
)
port map (
D0 => cActivated,
D1 => cInactivated,
C0 => rmiiClk,
C1 => nRmiiClk,
CE => cActivated,
R => cInactivated, --unused
S => cInactivated, --unused
Q => oRmii_clk(i)
);
end generate GEN_ODDR2;
end generate GEN_RMII_CLK;
end rtl;
| gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/latch/src/dataLatch-e.vhd | 3 | 2688 | -------------------------------------------------------------------------------
--! @file dataLatch-e.vhd
--! @brief Data latch entity
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use libcommon library
library libcommon;
--! Use global package
use libcommon.global.all;
--! This is the entity of the data latch component with clear and preset inputs.
entity dataLatch is
generic (
--! Data width
gDataWidth : natural := 1
);
port (
--! Clear input
iClear : in std_logic;
--! Enable latch
iEnable : in std_logic;
--! Data input
iData : in std_logic_vector(gDataWidth-1 downto 0);
--! Data output
oData : out std_logic_vector(gDataWidth-1 downto 0)
);
end dataLatch;
| gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_CPU_test_bench.vhd | 1 | 58977 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity Video_System_CPU_test_bench is
port (
-- inputs:
signal D_iw : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal D_iw_op : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal D_iw_opx : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal D_valid : IN STD_LOGIC;
signal E_alu_result : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_mem_byte_en : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_valid : IN STD_LOGIC;
signal F_pcb : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal F_valid : IN STD_LOGIC;
signal R_ctrl_exception : IN STD_LOGIC;
signal R_ctrl_ld : IN STD_LOGIC;
signal R_ctrl_ld_non_io : IN STD_LOGIC;
signal R_dst_regnum : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal R_wr_dst_reg : IN STD_LOGIC;
signal W_bstatus_reg : IN STD_LOGIC;
signal W_cmp_result : IN STD_LOGIC;
signal W_estatus_reg : IN STD_LOGIC;
signal W_ienable_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_ipending_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_mem_baddr : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal W_rf_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_status_reg : IN STD_LOGIC;
signal W_valid : IN STD_LOGIC;
signal W_vinst : IN STD_LOGIC_VECTOR (55 DOWNTO 0);
signal W_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_data_aligned_unfiltered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_write_nxt : IN STD_LOGIC;
signal i_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal i_read : IN STD_LOGIC;
signal i_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal i_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal av_ld_data_aligned_filtered : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal d_write : OUT STD_LOGIC;
signal test_has_ended : OUT STD_LOGIC
);
end entity Video_System_CPU_test_bench;
architecture europa of Video_System_CPU_test_bench is
signal D_op_add : STD_LOGIC;
signal D_op_addi : STD_LOGIC;
signal D_op_and : STD_LOGIC;
signal D_op_andhi : STD_LOGIC;
signal D_op_andi : STD_LOGIC;
signal D_op_beq : STD_LOGIC;
signal D_op_bge : STD_LOGIC;
signal D_op_bgeu : STD_LOGIC;
signal D_op_blt : STD_LOGIC;
signal D_op_bltu : STD_LOGIC;
signal D_op_bne : STD_LOGIC;
signal D_op_br : STD_LOGIC;
signal D_op_break : STD_LOGIC;
signal D_op_bret : STD_LOGIC;
signal D_op_call : STD_LOGIC;
signal D_op_callr : STD_LOGIC;
signal D_op_cmpeq : STD_LOGIC;
signal D_op_cmpeqi : STD_LOGIC;
signal D_op_cmpge : STD_LOGIC;
signal D_op_cmpgei : STD_LOGIC;
signal D_op_cmpgeu : STD_LOGIC;
signal D_op_cmpgeui : STD_LOGIC;
signal D_op_cmplt : STD_LOGIC;
signal D_op_cmplti : STD_LOGIC;
signal D_op_cmpltu : STD_LOGIC;
signal D_op_cmpltui : STD_LOGIC;
signal D_op_cmpne : STD_LOGIC;
signal D_op_cmpnei : STD_LOGIC;
signal D_op_crst : STD_LOGIC;
signal D_op_custom : STD_LOGIC;
signal D_op_div : STD_LOGIC;
signal D_op_divu : STD_LOGIC;
signal D_op_eret : STD_LOGIC;
signal D_op_flushd : STD_LOGIC;
signal D_op_flushda : STD_LOGIC;
signal D_op_flushi : STD_LOGIC;
signal D_op_flushp : STD_LOGIC;
signal D_op_hbreak : STD_LOGIC;
signal D_op_initd : STD_LOGIC;
signal D_op_initda : STD_LOGIC;
signal D_op_initi : STD_LOGIC;
signal D_op_intr : STD_LOGIC;
signal D_op_jmp : STD_LOGIC;
signal D_op_jmpi : STD_LOGIC;
signal D_op_ldb : STD_LOGIC;
signal D_op_ldbio : STD_LOGIC;
signal D_op_ldbu : STD_LOGIC;
signal D_op_ldbuio : STD_LOGIC;
signal D_op_ldh : STD_LOGIC;
signal D_op_ldhio : STD_LOGIC;
signal D_op_ldhu : STD_LOGIC;
signal D_op_ldhuio : STD_LOGIC;
signal D_op_ldl : STD_LOGIC;
signal D_op_ldw : STD_LOGIC;
signal D_op_ldwio : STD_LOGIC;
signal D_op_mul : STD_LOGIC;
signal D_op_muli : STD_LOGIC;
signal D_op_mulxss : STD_LOGIC;
signal D_op_mulxsu : STD_LOGIC;
signal D_op_mulxuu : STD_LOGIC;
signal D_op_nextpc : STD_LOGIC;
signal D_op_nor : STD_LOGIC;
signal D_op_opx : STD_LOGIC;
signal D_op_or : STD_LOGIC;
signal D_op_orhi : STD_LOGIC;
signal D_op_ori : STD_LOGIC;
signal D_op_rdctl : STD_LOGIC;
signal D_op_rdprs : STD_LOGIC;
signal D_op_ret : STD_LOGIC;
signal D_op_rol : STD_LOGIC;
signal D_op_roli : STD_LOGIC;
signal D_op_ror : STD_LOGIC;
signal D_op_rsv02 : STD_LOGIC;
signal D_op_rsv09 : STD_LOGIC;
signal D_op_rsv10 : STD_LOGIC;
signal D_op_rsv17 : STD_LOGIC;
signal D_op_rsv18 : STD_LOGIC;
signal D_op_rsv25 : STD_LOGIC;
signal D_op_rsv26 : STD_LOGIC;
signal D_op_rsv33 : STD_LOGIC;
signal D_op_rsv34 : STD_LOGIC;
signal D_op_rsv41 : STD_LOGIC;
signal D_op_rsv42 : STD_LOGIC;
signal D_op_rsv49 : STD_LOGIC;
signal D_op_rsv57 : STD_LOGIC;
signal D_op_rsv61 : STD_LOGIC;
signal D_op_rsv62 : STD_LOGIC;
signal D_op_rsv63 : STD_LOGIC;
signal D_op_rsvx00 : STD_LOGIC;
signal D_op_rsvx10 : STD_LOGIC;
signal D_op_rsvx15 : STD_LOGIC;
signal D_op_rsvx17 : STD_LOGIC;
signal D_op_rsvx21 : STD_LOGIC;
signal D_op_rsvx25 : STD_LOGIC;
signal D_op_rsvx33 : STD_LOGIC;
signal D_op_rsvx34 : STD_LOGIC;
signal D_op_rsvx35 : STD_LOGIC;
signal D_op_rsvx42 : STD_LOGIC;
signal D_op_rsvx43 : STD_LOGIC;
signal D_op_rsvx44 : STD_LOGIC;
signal D_op_rsvx47 : STD_LOGIC;
signal D_op_rsvx50 : STD_LOGIC;
signal D_op_rsvx51 : STD_LOGIC;
signal D_op_rsvx55 : STD_LOGIC;
signal D_op_rsvx56 : STD_LOGIC;
signal D_op_rsvx60 : STD_LOGIC;
signal D_op_rsvx63 : STD_LOGIC;
signal D_op_sll : STD_LOGIC;
signal D_op_slli : STD_LOGIC;
signal D_op_sra : STD_LOGIC;
signal D_op_srai : STD_LOGIC;
signal D_op_srl : STD_LOGIC;
signal D_op_srli : STD_LOGIC;
signal D_op_stb : STD_LOGIC;
signal D_op_stbio : STD_LOGIC;
signal D_op_stc : STD_LOGIC;
signal D_op_sth : STD_LOGIC;
signal D_op_sthio : STD_LOGIC;
signal D_op_stw : STD_LOGIC;
signal D_op_stwio : STD_LOGIC;
signal D_op_sub : STD_LOGIC;
signal D_op_sync : STD_LOGIC;
signal D_op_trap : STD_LOGIC;
signal D_op_wrctl : STD_LOGIC;
signal D_op_wrprs : STD_LOGIC;
signal D_op_xor : STD_LOGIC;
signal D_op_xorhi : STD_LOGIC;
signal D_op_xori : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_0_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_10_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_11_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_12_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_13_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_14_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_15_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_16_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_17_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_18_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_19_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_1_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_20_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_21_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_22_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_23_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_24_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_25_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_26_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_27_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_28_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_29_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_2_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_30_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_31_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_3_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_4_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_5_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_6_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_7_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_8_is_x : STD_LOGIC;
signal av_ld_data_aligned_unfiltered_9_is_x : STD_LOGIC;
signal internal_d_write1 : STD_LOGIC;
signal internal_test_has_ended : STD_LOGIC;
file trace_handle : TEXT ;
begin
D_op_call <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000000")));
D_op_jmpi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000001")));
D_op_ldbu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000011")));
D_op_addi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000100")));
D_op_stb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000101")));
D_op_br <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000110")));
D_op_ldb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000111")));
D_op_cmpgei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001000")));
D_op_ldhu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001011")));
D_op_andi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001100")));
D_op_sth <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001101")));
D_op_bge <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001110")));
D_op_ldh <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001111")));
D_op_cmplti <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010000")));
D_op_initda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010011")));
D_op_ori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010100")));
D_op_stw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010101")));
D_op_blt <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010110")));
D_op_ldw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010111")));
D_op_cmpnei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011000")));
D_op_flushda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011011")));
D_op_xori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011100")));
D_op_stc <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011101")));
D_op_bne <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011110")));
D_op_ldl <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011111")));
D_op_cmpeqi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100000")));
D_op_ldbuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100011")));
D_op_muli <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100100")));
D_op_stbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100101")));
D_op_beq <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100110")));
D_op_ldbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100111")));
D_op_cmpgeui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101000")));
D_op_ldhuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101011")));
D_op_andhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101100")));
D_op_sthio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101101")));
D_op_bgeu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101110")));
D_op_ldhio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101111")));
D_op_cmpltui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110000")));
D_op_initd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110011")));
D_op_orhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110100")));
D_op_stwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110101")));
D_op_bltu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110110")));
D_op_ldwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110111")));
D_op_rdprs <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111000")));
D_op_flushd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111011")));
D_op_xorhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111100")));
D_op_rsv02 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000010")));
D_op_rsv09 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001001")));
D_op_rsv10 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001010")));
D_op_rsv17 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010001")));
D_op_rsv18 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010010")));
D_op_rsv25 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011001")));
D_op_rsv26 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011010")));
D_op_rsv33 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100001")));
D_op_rsv34 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100010")));
D_op_rsv41 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101001")));
D_op_rsv42 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101010")));
D_op_rsv49 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110001")));
D_op_rsv57 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111001")));
D_op_rsv61 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111101")));
D_op_rsv62 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111110")));
D_op_rsv63 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111111")));
D_op_eret <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000001"))));
D_op_roli <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000010"))));
D_op_rol <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000011"))));
D_op_flushp <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000100"))));
D_op_ret <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000101"))));
D_op_nor <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000110"))));
D_op_mulxuu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000111"))));
D_op_cmpge <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001000"))));
D_op_bret <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001001"))));
D_op_ror <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001011"))));
D_op_flushi <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001100"))));
D_op_jmp <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001101"))));
D_op_and <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001110"))));
D_op_cmplt <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010000"))));
D_op_slli <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010010"))));
D_op_sll <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010011"))));
D_op_wrprs <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010100"))));
D_op_or <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010110"))));
D_op_mulxsu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010111"))));
D_op_cmpne <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011000"))));
D_op_srli <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011010"))));
D_op_srl <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011011"))));
D_op_nextpc <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011100"))));
D_op_callr <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011101"))));
D_op_xor <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011110"))));
D_op_mulxss <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011111"))));
D_op_cmpeq <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100000"))));
D_op_divu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100100"))));
D_op_div <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100101"))));
D_op_rdctl <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100110"))));
D_op_mul <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100111"))));
D_op_cmpgeu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101000"))));
D_op_initi <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101001"))));
D_op_trap <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101101"))));
D_op_wrctl <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101110"))));
D_op_cmpltu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110000"))));
D_op_add <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110001"))));
D_op_break <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110100"))));
D_op_hbreak <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110101"))));
D_op_sync <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110110"))));
D_op_sub <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111001"))));
D_op_srai <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111010"))));
D_op_sra <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111011"))));
D_op_intr <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111101"))));
D_op_crst <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111110"))));
D_op_rsvx00 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000000"))));
D_op_rsvx10 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001010"))));
D_op_rsvx15 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001111"))));
D_op_rsvx17 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010001"))));
D_op_rsvx21 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010101"))));
D_op_rsvx25 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011001"))));
D_op_rsvx33 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100001"))));
D_op_rsvx34 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100010"))));
D_op_rsvx35 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100011"))));
D_op_rsvx42 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101010"))));
D_op_rsvx43 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101011"))));
D_op_rsvx44 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101100"))));
D_op_rsvx47 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101111"))));
D_op_rsvx50 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110010"))));
D_op_rsvx51 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110011"))));
D_op_rsvx55 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110111"))));
D_op_rsvx56 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111000"))));
D_op_rsvx60 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111100"))));
D_op_rsvx63 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111111"))));
D_op_opx <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111010")));
D_op_custom <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110010")));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_d_write1 <= std_logic'('0');
elsif clk'event and clk = '1' then
internal_d_write1 <= d_write_nxt;
end if;
end process;
internal_test_has_ended <= std_logic'('0');
--vhdl renameroo for output signals
d_write <= internal_d_write1;
--vhdl renameroo for output signals
test_has_ended <= internal_test_has_ended;
--synthesis translate_off
--Clearing 'X' data bits
av_ld_data_aligned_unfiltered_0_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(0))), '1','0');
av_ld_data_aligned_filtered(0) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_0_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(0));
av_ld_data_aligned_unfiltered_1_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(1))), '1','0');
av_ld_data_aligned_filtered(1) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_1_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(1));
av_ld_data_aligned_unfiltered_2_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(2))), '1','0');
av_ld_data_aligned_filtered(2) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_2_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(2));
av_ld_data_aligned_unfiltered_3_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(3))), '1','0');
av_ld_data_aligned_filtered(3) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_3_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(3));
av_ld_data_aligned_unfiltered_4_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(4))), '1','0');
av_ld_data_aligned_filtered(4) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_4_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(4));
av_ld_data_aligned_unfiltered_5_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(5))), '1','0');
av_ld_data_aligned_filtered(5) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_5_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(5));
av_ld_data_aligned_unfiltered_6_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(6))), '1','0');
av_ld_data_aligned_filtered(6) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_6_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(6));
av_ld_data_aligned_unfiltered_7_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(7))), '1','0');
av_ld_data_aligned_filtered(7) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_7_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(7));
av_ld_data_aligned_unfiltered_8_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(8))), '1','0');
av_ld_data_aligned_filtered(8) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_8_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(8));
av_ld_data_aligned_unfiltered_9_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(9))), '1','0');
av_ld_data_aligned_filtered(9) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_9_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(9));
av_ld_data_aligned_unfiltered_10_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(10))), '1','0');
av_ld_data_aligned_filtered(10) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_10_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(10));
av_ld_data_aligned_unfiltered_11_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(11))), '1','0');
av_ld_data_aligned_filtered(11) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_11_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(11));
av_ld_data_aligned_unfiltered_12_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(12))), '1','0');
av_ld_data_aligned_filtered(12) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_12_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(12));
av_ld_data_aligned_unfiltered_13_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(13))), '1','0');
av_ld_data_aligned_filtered(13) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_13_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(13));
av_ld_data_aligned_unfiltered_14_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(14))), '1','0');
av_ld_data_aligned_filtered(14) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_14_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(14));
av_ld_data_aligned_unfiltered_15_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(15))), '1','0');
av_ld_data_aligned_filtered(15) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_15_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(15));
av_ld_data_aligned_unfiltered_16_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(16))), '1','0');
av_ld_data_aligned_filtered(16) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_16_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(16));
av_ld_data_aligned_unfiltered_17_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(17))), '1','0');
av_ld_data_aligned_filtered(17) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_17_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(17));
av_ld_data_aligned_unfiltered_18_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(18))), '1','0');
av_ld_data_aligned_filtered(18) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_18_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(18));
av_ld_data_aligned_unfiltered_19_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(19))), '1','0');
av_ld_data_aligned_filtered(19) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_19_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(19));
av_ld_data_aligned_unfiltered_20_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(20))), '1','0');
av_ld_data_aligned_filtered(20) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_20_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(20));
av_ld_data_aligned_unfiltered_21_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(21))), '1','0');
av_ld_data_aligned_filtered(21) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_21_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(21));
av_ld_data_aligned_unfiltered_22_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(22))), '1','0');
av_ld_data_aligned_filtered(22) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_22_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(22));
av_ld_data_aligned_unfiltered_23_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(23))), '1','0');
av_ld_data_aligned_filtered(23) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_23_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(23));
av_ld_data_aligned_unfiltered_24_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(24))), '1','0');
av_ld_data_aligned_filtered(24) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_24_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(24));
av_ld_data_aligned_unfiltered_25_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(25))), '1','0');
av_ld_data_aligned_filtered(25) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_25_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(25));
av_ld_data_aligned_unfiltered_26_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(26))), '1','0');
av_ld_data_aligned_filtered(26) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_26_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(26));
av_ld_data_aligned_unfiltered_27_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(27))), '1','0');
av_ld_data_aligned_filtered(27) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_27_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(27));
av_ld_data_aligned_unfiltered_28_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(28))), '1','0');
av_ld_data_aligned_filtered(28) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_28_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(28));
av_ld_data_aligned_unfiltered_29_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(29))), '1','0');
av_ld_data_aligned_filtered(29) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_29_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(29));
av_ld_data_aligned_unfiltered_30_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(30))), '1','0');
av_ld_data_aligned_filtered(30) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_30_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(30));
av_ld_data_aligned_unfiltered_31_is_x <= A_WE_StdLogic(is_x(std_ulogic(av_ld_data_aligned_unfiltered(31))), '1','0');
av_ld_data_aligned_filtered(31) <= A_WE_StdLogic((std_logic'(((av_ld_data_aligned_unfiltered_31_is_x AND (R_ctrl_ld_non_io)))) = '1'), std_logic'('0'), av_ld_data_aligned_unfiltered(31));
process (clk)
VARIABLE write_line : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(F_valid)) then
write(write_line, now);
write(write_line, string'(": "));
write(write_line, string'("ERROR: Video_System_CPU_test_bench/F_valid is 'x'"));
write(output, write_line.all & CR);
deallocate (write_line);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line1 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(D_valid)) then
write(write_line1, now);
write(write_line1, string'(": "));
write(write_line1, string'("ERROR: Video_System_CPU_test_bench/D_valid is 'x'"));
write(output, write_line1.all & CR);
deallocate (write_line1);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line2 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(E_valid)) then
write(write_line2, now);
write(write_line2, string'(": "));
write(write_line2, string'("ERROR: Video_System_CPU_test_bench/E_valid is 'x'"));
write(output, write_line2.all & CR);
deallocate (write_line2);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line3 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(W_valid)) then
write(write_line3, now);
write(write_line3, string'(": "));
write(write_line3, string'("ERROR: Video_System_CPU_test_bench/W_valid is 'x'"));
write(output, write_line3.all & CR);
deallocate (write_line3);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line4 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(W_valid) = '1' then
if is_x(std_ulogic(R_wr_dst_reg)) then
write(write_line4, now);
write(write_line4, string'(": "));
write(write_line4, string'("ERROR: Video_System_CPU_test_bench/R_wr_dst_reg is 'x'"));
write(output, write_line4.all & CR);
deallocate (write_line4);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line5 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((W_valid AND R_wr_dst_reg)) = '1' then
if is_x(W_wr_data) then
write(write_line5, now);
write(write_line5, string'(": "));
write(write_line5, string'("ERROR: Video_System_CPU_test_bench/W_wr_data is 'x'"));
write(output, write_line5.all & CR);
deallocate (write_line5);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line6 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((W_valid AND R_wr_dst_reg)) = '1' then
if is_x(R_dst_regnum) then
write(write_line6, now);
write(write_line6, string'(": "));
write(write_line6, string'("ERROR: Video_System_CPU_test_bench/R_dst_regnum is 'x'"));
write(output, write_line6.all & CR);
deallocate (write_line6);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line7 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(internal_d_write1)) then
write(write_line7, now);
write(write_line7, string'(": "));
write(write_line7, string'("ERROR: Video_System_CPU_test_bench/internal_d_write1 is 'x'"));
write(output, write_line7.all & CR);
deallocate (write_line7);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line8 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(internal_d_write1) = '1' then
if is_x(d_byteenable) then
write(write_line8, now);
write(write_line8, string'(": "));
write(write_line8, string'("ERROR: Video_System_CPU_test_bench/d_byteenable is 'x'"));
write(output, write_line8.all & CR);
deallocate (write_line8);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line9 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((internal_d_write1 OR d_read)) = '1' then
if is_x(d_address) then
write(write_line9, now);
write(write_line9, string'(": "));
write(write_line9, string'("ERROR: Video_System_CPU_test_bench/d_address is 'x'"));
write(output, write_line9.all & CR);
deallocate (write_line9);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line10 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(d_read)) then
write(write_line10, now);
write(write_line10, string'(": "));
write(write_line10, string'("ERROR: Video_System_CPU_test_bench/d_read is 'x'"));
write(output, write_line10.all & CR);
deallocate (write_line10);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line11 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(i_read)) then
write(write_line11, now);
write(write_line11, string'(": "));
write(write_line11, string'("ERROR: Video_System_CPU_test_bench/i_read is 'x'"));
write(output, write_line11.all & CR);
deallocate (write_line11);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line12 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(i_read) = '1' then
if is_x(i_address) then
write(write_line12, now);
write(write_line12, string'(": "));
write(write_line12, string'("ERROR: Video_System_CPU_test_bench/i_address is 'x'"));
write(output, write_line12.all & CR);
deallocate (write_line12);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line13 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((i_read AND NOT i_waitrequest)) = '1' then
if is_x(i_readdata) then
write(write_line13, now);
write(write_line13, string'(": "));
write(write_line13, string'("ERROR: Video_System_CPU_test_bench/i_readdata is 'x'"));
write(output, write_line13.all & CR);
deallocate (write_line13);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line14 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((W_valid AND R_ctrl_ld)) = '1' then
if is_x(av_ld_data_aligned_unfiltered) then
write(write_line14, now);
write(write_line14, string'(": "));
write(write_line14, string'("WARNING: Video_System_CPU_test_bench/av_ld_data_aligned_unfiltered is 'x'"));
write(output, write_line14.all & CR);
deallocate (write_line14);
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line15 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((W_valid AND R_wr_dst_reg)) = '1' then
if is_x(W_wr_data) then
write(write_line15, now);
write(write_line15, string'(": "));
write(write_line15, string'("WARNING: Video_System_CPU_test_bench/W_wr_data is 'x'"));
write(output, write_line15.all & CR);
deallocate (write_line15);
end if;
end if;
end if;
end process;
process is
variable status : file_open_status; -- status for fopen
VARIABLE write_line16 : line;
VARIABLE write_line17 : line;
begin -- process
file_open(status, trace_handle, "Video_System_CPU.tr", WRITE_MODE);
write(write_line16, string'("version 3"));
write(trace_handle, write_line16.all & LF);
deallocate (write_line16);
write(write_line17, string'("numThreads 1"));
write(trace_handle, write_line17.all & LF);
deallocate (write_line17);
wait; -- wait forever
end process;
process (clk)
VARIABLE write_line18 : line;
begin
if clk'event and clk = '1' then
if std_logic'((((NOT reset_n OR (W_valid))) AND NOT internal_test_has_ended)) = '1' then
write(write_line18, now);
write(write_line18, string'(": "));
write(write_line18, to_hex_string(NOT reset_n, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(F_pcb, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(D_op_intr, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(D_op_hbreak, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(D_iw, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(NOT ((D_op_intr OR D_op_hbreak)), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(R_wr_dst_reg, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(R_dst_regnum, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(W_rf_wr_data, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(W_mem_baddr, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(E_st_data, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(E_mem_byte_en, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(W_cmp_result, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(E_alu_result, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(W_status_reg, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(W_estatus_reg, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(W_bstatus_reg, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(W_ienable_reg, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(W_ipending_reg, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(R_ctrl_exception, pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(","));
write(write_line18, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line18, string'(""));
write(trace_handle, write_line18.all & LF);
deallocate (write_line18);
end if;
end if;
end process;
--synthesis translate_on
--synthesis read_comments_as_HDL on
--
-- av_ld_data_aligned_filtered <= av_ld_data_aligned_unfiltered;
--synthesis read_comments_as_HDL off
end europa;
| gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/Video_System.vhd | 1 | 468537 | -- Video_System.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.09.14:34:20
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Video_System is
port (
VGA_CLK_from_the_VGA_Controller : out std_logic; -- VGA_Controller_external_interface.CLK
VGA_HS_from_the_VGA_Controller : out std_logic; -- .HS
VGA_VS_from_the_VGA_Controller : out std_logic; -- .VS
VGA_BLANK_from_the_VGA_Controller : out std_logic; -- .BLANK
VGA_SYNC_from_the_VGA_Controller : out std_logic; -- .SYNC
VGA_R_from_the_VGA_Controller : out std_logic_vector(9 downto 0); -- .R
VGA_G_from_the_VGA_Controller : out std_logic_vector(9 downto 0); -- .G
VGA_B_from_the_VGA_Controller : out std_logic_vector(9 downto 0); -- .B
clk_0 : in std_logic := '0'; -- clk_0_clk_in.clk
reset_n : in std_logic := '0'; -- clk_0_clk_in_reset.reset_n
I2C_SDAT_to_and_from_the_AV_Config : inout std_logic := '0'; -- AV_Config_external_interface.SDAT
I2C_SCLK_from_the_AV_Config : out std_logic; -- .SCLK
SRAM_DQ_to_and_from_the_Pixel_Buffer : inout std_logic_vector(15 downto 0) := (others => '0'); -- Pixel_Buffer_external_interface.DQ
SRAM_ADDR_from_the_Pixel_Buffer : out std_logic_vector(17 downto 0); -- .ADDR
SRAM_LB_N_from_the_Pixel_Buffer : out std_logic; -- .LB_N
SRAM_UB_N_from_the_Pixel_Buffer : out std_logic; -- .UB_N
SRAM_CE_N_from_the_Pixel_Buffer : out std_logic; -- .CE_N
SRAM_OE_N_from_the_Pixel_Buffer : out std_logic; -- .OE_N
SRAM_WE_N_from_the_Pixel_Buffer : out std_logic; -- .WE_N
TD_CLK27_to_the_Video_In_Decoder : in std_logic := '0'; -- Video_In_Decoder_external_interface.TD_CLK27
TD_DATA_to_the_Video_In_Decoder : in std_logic_vector(7 downto 0) := (others => '0'); -- .TD_DATA
TD_HS_to_the_Video_In_Decoder : in std_logic := '0'; -- .TD_HS
TD_VS_to_the_Video_In_Decoder : in std_logic := '0'; -- .TD_VS
TD_RESET_from_the_Video_In_Decoder : out std_logic; -- .TD_RESET
overflow_flag_from_the_Video_In_Decoder : out std_logic -- .overflow_flag
);
end entity Video_System;
architecture rtl of Video_System is
component Video_System_Onchip_Memory is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
chipselect : in std_logic := 'X'; -- chipselect
clken : in std_logic := 'X'; -- clken
readdata : out std_logic_vector(31 downto 0); -- readdata
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X' -- reset
);
end component Video_System_Onchip_Memory;
component Video_System_Dual_Clock_FIFO is
port (
clk_stream_in : in std_logic := 'X'; -- clk
reset_stream_in : in std_logic := 'X'; -- reset
clk_stream_out : in std_logic := 'X'; -- clk
reset_stream_out : in std_logic := 'X'; -- reset
stream_in_ready : out std_logic; -- ready
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_data : in std_logic_vector(29 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(29 downto 0) -- data
);
end component Video_System_Dual_Clock_FIFO;
component Video_System_Pixel_Buffer is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
SRAM_DQ : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
SRAM_ADDR : out std_logic_vector(17 downto 0); -- export
SRAM_LB_N : out std_logic; -- export
SRAM_UB_N : out std_logic; -- export
SRAM_CE_N : out std_logic; -- export
SRAM_OE_N : out std_logic; -- export
SRAM_WE_N : out std_logic; -- export
address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
readdatavalid : out std_logic -- readdatavalid
);
end component Video_System_Pixel_Buffer;
component Video_System_Pixel_Buffer_DMA is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
master_readdatavalid : in std_logic := 'X'; -- readdatavalid
master_waitrequest : in std_logic := 'X'; -- waitrequest
master_address : out std_logic_vector(31 downto 0); -- address
master_arbiterlock : out std_logic; -- lock
master_read : out std_logic; -- read
master_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
slave_read : in std_logic := 'X'; -- read
slave_write : in std_logic := 'X'; -- write
slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
slave_readdata : out std_logic_vector(31 downto 0); -- readdata
stream_ready : in std_logic := 'X'; -- ready
stream_startofpacket : out std_logic; -- startofpacket
stream_endofpacket : out std_logic; -- endofpacket
stream_valid : out std_logic; -- valid
stream_data : out std_logic_vector(15 downto 0) -- data
);
end component Video_System_Pixel_Buffer_DMA;
component Video_System_Pixel_RGB_Resampler is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(29 downto 0) -- data
);
end component Video_System_Pixel_RGB_Resampler;
component Video_System_Pixel_Scaler is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(29 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(29 downto 0) -- data
);
end component Video_System_Pixel_Scaler;
component Video_System_VGA_Controller is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
data : in std_logic_vector(29 downto 0) := (others => 'X'); -- data
startofpacket : in std_logic := 'X'; -- startofpacket
endofpacket : in std_logic := 'X'; -- endofpacket
valid : in std_logic := 'X'; -- valid
ready : out std_logic; -- ready
VGA_CLK : out std_logic; -- export
VGA_HS : out std_logic; -- export
VGA_VS : out std_logic; -- export
VGA_BLANK : out std_logic; -- export
VGA_SYNC : out std_logic; -- export
VGA_R : out std_logic_vector(9 downto 0); -- export
VGA_G : out std_logic_vector(9 downto 0); -- export
VGA_B : out std_logic_vector(9 downto 0) -- export
);
end component Video_System_VGA_Controller;
component Video_System_Video_In_Decoder is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(15 downto 0); -- data
TD_CLK27 : in std_logic := 'X'; -- export
TD_DATA : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
TD_HS : in std_logic := 'X'; -- export
TD_VS : in std_logic := 'X'; -- export
TD_RESET : out std_logic; -- export
overflow_flag : out std_logic -- export
);
end component Video_System_Video_In_Decoder;
component Video_System_Chroma_Resampler is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(23 downto 0) -- data
);
end component Video_System_Chroma_Resampler;
component Video_System_Color_Space_Converter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(23 downto 0) -- data
);
end component Video_System_Color_Space_Converter;
component Video_System_Video_RGB_Resampler is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(15 downto 0) -- data
);
end component Video_System_Video_RGB_Resampler;
component Video_System_Video_Clipper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_data : out std_logic_vector(15 downto 0); -- data
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic -- valid
);
end component Video_System_Video_Clipper;
component Video_System_Video_Scaler is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(15 downto 0) -- data
);
end component Video_System_Video_Scaler;
component Video_System_Video_DMA is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_startofpacket : in std_logic := 'X'; -- startofpacket
stream_endofpacket : in std_logic := 'X'; -- endofpacket
stream_valid : in std_logic := 'X'; -- valid
stream_ready : out std_logic; -- ready
slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
slave_read : in std_logic := 'X'; -- read
slave_write : in std_logic := 'X'; -- write
slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
slave_readdata : out std_logic_vector(31 downto 0); -- readdata
master_address : out std_logic_vector(31 downto 0); -- address
master_waitrequest : in std_logic := 'X'; -- waitrequest
master_write : out std_logic; -- write
master_writedata : out std_logic_vector(15 downto 0) -- writedata
);
end component Video_System_Video_DMA;
component Video_System_AV_Config is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(31 downto 0); -- readdata
waitrequest : out std_logic; -- waitrequest
I2C_SDAT : inout std_logic := 'X'; -- export
I2C_SCLK : out std_logic -- export
);
end component Video_System_AV_Config;
component Video_System_CPU is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
d_address : out std_logic_vector(19 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_debug_module_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(19 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
d_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
jtag_debug_module_resetrequest : out std_logic; -- reset
jtag_debug_module_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
jtag_debug_module_begintransfer : in std_logic := 'X'; -- begintransfer
jtag_debug_module_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
jtag_debug_module_debugaccess : in std_logic := 'X'; -- debugaccess
jtag_debug_module_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_debug_module_select : in std_logic := 'X'; -- chipselect
jtag_debug_module_write : in std_logic := 'X'; -- write
jtag_debug_module_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
no_ci_readra : out std_logic -- readra
);
end component Video_System_CPU;
component Video_System_Clock_Signals is
port (
CLOCK_50 : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sys_clk : out std_logic; -- clk
sys_reset_n : out std_logic; -- reset_n
VGA_CLK : out std_logic -- clk
);
end component Video_System_Clock_Signals;
component Video_System_CPU_instruction_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(31 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component Video_System_CPU_instruction_master_translator;
component Video_System_CPU_data_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(31 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_debugaccess : in std_logic := 'X' -- debugaccess
);
end component Video_System_CPU_data_master_translator;
component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(31 downto 0); -- address
uav_burstcount : out std_logic_vector(1 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(1 downto 0); -- byteenable
uav_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(15 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_readdatavalid : out std_logic; -- readdatavalid
av_lock : in std_logic := 'X' -- lock
);
end component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator;
component Video_System_Video_DMA_avalon_dma_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(31 downto 0); -- address
uav_burstcount : out std_logic_vector(1 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(1 downto 0); -- byteenable
uav_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(15 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X') -- writedata
);
end component Video_System_Video_DMA_avalon_dma_master_translator;
component Video_System_CPU_instruction_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(104 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component Video_System_CPU_instruction_master_translator_avalon_universal_master_0_agent;
component Video_System_CPU_data_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(104 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component Video_System_CPU_data_master_translator_avalon_universal_master_0_agent;
component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(86 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent;
component Video_System_Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(86 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component Video_System_Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent;
component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(104 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(105 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent;
component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(105 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo;
component Video_System_Onchip_Memory_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(104 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(105 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component Video_System_Onchip_Memory_s1_translator_avalon_universal_slave_0_agent;
component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(1 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(1 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(15 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(86 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(87 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(15 downto 0) -- data
);
end component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent;
component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo;
component Video_System_AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(104 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(105 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component Video_System_AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent;
component Video_System_Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(104 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(105 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component Video_System_Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent;
component Video_System_Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(31 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(104 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(105 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(105 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component Video_System_Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent;
component Video_System_addr_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_addr_router;
component Video_System_addr_router_001 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_addr_router_001;
component Video_System_addr_router_002 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(86 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_addr_router_002;
component Video_System_id_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_id_router;
component Video_System_id_router_002 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(86 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_id_router_002;
component Video_System_id_router_003 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component Video_System_id_router_003;
component Video_System_burst_adapter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(86 downto 0); -- data
source0_channel : out std_logic_vector(5 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component Video_System_burst_adapter;
component Video_System_rst_controller is
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic -- reset
);
end component Video_System_rst_controller;
component Video_System_cmd_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(104 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(104 downto 0); -- data
src1_channel : out std_logic_vector(5 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic -- endofpacket
);
end component Video_System_cmd_xbar_demux;
component Video_System_cmd_xbar_demux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(104 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(104 downto 0); -- data
src1_channel : out std_logic_vector(5 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(104 downto 0); -- data
src2_channel : out std_logic_vector(5 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(104 downto 0); -- data
src3_channel : out std_logic_vector(5 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(104 downto 0); -- data
src4_channel : out std_logic_vector(5 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic; -- endofpacket
src5_ready : in std_logic := 'X'; -- ready
src5_valid : out std_logic; -- valid
src5_data : out std_logic_vector(104 downto 0); -- data
src5_channel : out std_logic_vector(5 downto 0); -- channel
src5_startofpacket : out std_logic; -- startofpacket
src5_endofpacket : out std_logic -- endofpacket
);
end component Video_System_cmd_xbar_demux_001;
component Video_System_cmd_xbar_demux_002 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(86 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component Video_System_cmd_xbar_demux_002;
component Video_System_cmd_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X' -- endofpacket
);
end component Video_System_cmd_xbar_mux;
component Video_System_cmd_xbar_mux_002 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(86 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X' -- endofpacket
);
end component Video_System_cmd_xbar_mux_002;
component Video_System_rsp_xbar_demux_002 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(86 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(86 downto 0); -- data
src1_channel : out std_logic_vector(5 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(86 downto 0); -- data
src2_channel : out std_logic_vector(5 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic -- endofpacket
);
end component Video_System_rsp_xbar_demux_002;
component Video_System_rsp_xbar_demux_003 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(104 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component Video_System_rsp_xbar_demux_003;
component Video_System_rsp_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X' -- endofpacket
);
end component Video_System_rsp_xbar_mux;
component Video_System_rsp_xbar_mux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(104 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X'; -- endofpacket
sink5_ready : out std_logic; -- ready
sink5_valid : in std_logic := 'X'; -- valid
sink5_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink5_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
sink5_startofpacket : in std_logic := 'X'; -- startofpacket
sink5_endofpacket : in std_logic := 'X' -- endofpacket
);
end component Video_System_rsp_xbar_mux_001;
component Video_System_width_adapter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(104 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(86 downto 0); -- data
out_channel : out std_logic_vector(5 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component Video_System_width_adapter;
component Video_System_width_adapter_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(86 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(104 downto 0); -- data
out_channel : out std_logic_vector(5 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component Video_System_width_adapter_001;
component Video_System_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component Video_System_irq_mapper;
component video_system_cpu_jtag_debug_module_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(8 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_debugaccess : out std_logic; -- debugaccess
av_read : out std_logic; -- read
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic -- outputenable
);
end component video_system_cpu_jtag_debug_module_translator;
component video_system_onchip_memory_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(11 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component video_system_onchip_memory_s1_translator;
component video_system_pixel_buffer_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component video_system_pixel_buffer_avalon_sram_slave_translator;
component video_system_av_config_avalon_av_config_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component video_system_av_config_avalon_av_config_slave_translator;
signal pixel_scaler_avalon_scaler_source_endofpacket : std_logic; -- Pixel_Scaler:stream_out_endofpacket -> Dual_Clock_FIFO:stream_in_endofpacket
signal pixel_scaler_avalon_scaler_source_valid : std_logic; -- Pixel_Scaler:stream_out_valid -> Dual_Clock_FIFO:stream_in_valid
signal pixel_scaler_avalon_scaler_source_startofpacket : std_logic; -- Pixel_Scaler:stream_out_startofpacket -> Dual_Clock_FIFO:stream_in_startofpacket
signal pixel_scaler_avalon_scaler_source_data : std_logic_vector(29 downto 0); -- Pixel_Scaler:stream_out_data -> Dual_Clock_FIFO:stream_in_data
signal pixel_scaler_avalon_scaler_source_ready : std_logic; -- Dual_Clock_FIFO:stream_in_ready -> Pixel_Scaler:stream_out_ready
signal pixel_rgb_resampler_avalon_rgb_source_endofpacket : std_logic; -- Pixel_RGB_Resampler:stream_out_endofpacket -> Pixel_Scaler:stream_in_endofpacket
signal pixel_rgb_resampler_avalon_rgb_source_valid : std_logic; -- Pixel_RGB_Resampler:stream_out_valid -> Pixel_Scaler:stream_in_valid
signal pixel_rgb_resampler_avalon_rgb_source_startofpacket : std_logic; -- Pixel_RGB_Resampler:stream_out_startofpacket -> Pixel_Scaler:stream_in_startofpacket
signal pixel_rgb_resampler_avalon_rgb_source_data : std_logic_vector(29 downto 0); -- Pixel_RGB_Resampler:stream_out_data -> Pixel_Scaler:stream_in_data
signal pixel_rgb_resampler_avalon_rgb_source_ready : std_logic; -- Pixel_Scaler:stream_in_ready -> Pixel_RGB_Resampler:stream_out_ready
signal pixel_buffer_dma_avalon_pixel_source_endofpacket : std_logic; -- Pixel_Buffer_DMA:stream_endofpacket -> Pixel_RGB_Resampler:stream_in_endofpacket
signal pixel_buffer_dma_avalon_pixel_source_valid : std_logic; -- Pixel_Buffer_DMA:stream_valid -> Pixel_RGB_Resampler:stream_in_valid
signal pixel_buffer_dma_avalon_pixel_source_startofpacket : std_logic; -- Pixel_Buffer_DMA:stream_startofpacket -> Pixel_RGB_Resampler:stream_in_startofpacket
signal pixel_buffer_dma_avalon_pixel_source_data : std_logic_vector(15 downto 0); -- Pixel_Buffer_DMA:stream_data -> Pixel_RGB_Resampler:stream_in_data
signal pixel_buffer_dma_avalon_pixel_source_ready : std_logic; -- Pixel_RGB_Resampler:stream_in_ready -> Pixel_Buffer_DMA:stream_ready
signal dual_clock_fifo_avalon_dc_buffer_source_endofpacket : std_logic; -- Dual_Clock_FIFO:stream_out_endofpacket -> VGA_Controller:endofpacket
signal dual_clock_fifo_avalon_dc_buffer_source_valid : std_logic; -- Dual_Clock_FIFO:stream_out_valid -> VGA_Controller:valid
signal dual_clock_fifo_avalon_dc_buffer_source_startofpacket : std_logic; -- Dual_Clock_FIFO:stream_out_startofpacket -> VGA_Controller:startofpacket
signal dual_clock_fifo_avalon_dc_buffer_source_data : std_logic_vector(29 downto 0); -- Dual_Clock_FIFO:stream_out_data -> VGA_Controller:data
signal dual_clock_fifo_avalon_dc_buffer_source_ready : std_logic; -- VGA_Controller:ready -> Dual_Clock_FIFO:stream_out_ready
signal video_in_decoder_avalon_decoder_source_endofpacket : std_logic; -- Video_In_Decoder:stream_out_endofpacket -> Chroma_Resampler:stream_in_endofpacket
signal video_in_decoder_avalon_decoder_source_valid : std_logic; -- Video_In_Decoder:stream_out_valid -> Chroma_Resampler:stream_in_valid
signal video_in_decoder_avalon_decoder_source_startofpacket : std_logic; -- Video_In_Decoder:stream_out_startofpacket -> Chroma_Resampler:stream_in_startofpacket
signal video_in_decoder_avalon_decoder_source_data : std_logic_vector(15 downto 0); -- Video_In_Decoder:stream_out_data -> Chroma_Resampler:stream_in_data
signal video_in_decoder_avalon_decoder_source_ready : std_logic; -- Chroma_Resampler:stream_in_ready -> Video_In_Decoder:stream_out_ready
signal chroma_resampler_avalon_chroma_source_endofpacket : std_logic; -- Chroma_Resampler:stream_out_endofpacket -> Color_Space_Converter:stream_in_endofpacket
signal chroma_resampler_avalon_chroma_source_valid : std_logic; -- Chroma_Resampler:stream_out_valid -> Color_Space_Converter:stream_in_valid
signal chroma_resampler_avalon_chroma_source_startofpacket : std_logic; -- Chroma_Resampler:stream_out_startofpacket -> Color_Space_Converter:stream_in_startofpacket
signal chroma_resampler_avalon_chroma_source_data : std_logic_vector(23 downto 0); -- Chroma_Resampler:stream_out_data -> Color_Space_Converter:stream_in_data
signal chroma_resampler_avalon_chroma_source_ready : std_logic; -- Color_Space_Converter:stream_in_ready -> Chroma_Resampler:stream_out_ready
signal color_space_converter_avalon_csc_source_endofpacket : std_logic; -- Color_Space_Converter:stream_out_endofpacket -> Video_RGB_Resampler:stream_in_endofpacket
signal color_space_converter_avalon_csc_source_valid : std_logic; -- Color_Space_Converter:stream_out_valid -> Video_RGB_Resampler:stream_in_valid
signal color_space_converter_avalon_csc_source_startofpacket : std_logic; -- Color_Space_Converter:stream_out_startofpacket -> Video_RGB_Resampler:stream_in_startofpacket
signal color_space_converter_avalon_csc_source_data : std_logic_vector(23 downto 0); -- Color_Space_Converter:stream_out_data -> Video_RGB_Resampler:stream_in_data
signal color_space_converter_avalon_csc_source_ready : std_logic; -- Video_RGB_Resampler:stream_in_ready -> Color_Space_Converter:stream_out_ready
signal video_rgb_resampler_avalon_rgb_source_endofpacket : std_logic; -- Video_RGB_Resampler:stream_out_endofpacket -> Video_Clipper:stream_in_endofpacket
signal video_rgb_resampler_avalon_rgb_source_valid : std_logic; -- Video_RGB_Resampler:stream_out_valid -> Video_Clipper:stream_in_valid
signal video_rgb_resampler_avalon_rgb_source_startofpacket : std_logic; -- Video_RGB_Resampler:stream_out_startofpacket -> Video_Clipper:stream_in_startofpacket
signal video_rgb_resampler_avalon_rgb_source_data : std_logic_vector(15 downto 0); -- Video_RGB_Resampler:stream_out_data -> Video_Clipper:stream_in_data
signal video_rgb_resampler_avalon_rgb_source_ready : std_logic; -- Video_Clipper:stream_in_ready -> Video_RGB_Resampler:stream_out_ready
signal video_clipper_avalon_clipper_source_endofpacket : std_logic; -- Video_Clipper:stream_out_endofpacket -> Video_Scaler:stream_in_endofpacket
signal video_clipper_avalon_clipper_source_valid : std_logic; -- Video_Clipper:stream_out_valid -> Video_Scaler:stream_in_valid
signal video_clipper_avalon_clipper_source_startofpacket : std_logic; -- Video_Clipper:stream_out_startofpacket -> Video_Scaler:stream_in_startofpacket
signal video_clipper_avalon_clipper_source_data : std_logic_vector(15 downto 0); -- Video_Clipper:stream_out_data -> Video_Scaler:stream_in_data
signal video_clipper_avalon_clipper_source_ready : std_logic; -- Video_Scaler:stream_in_ready -> Video_Clipper:stream_out_ready
signal video_scaler_avalon_scaler_source_endofpacket : std_logic; -- Video_Scaler:stream_out_endofpacket -> Video_DMA:stream_endofpacket
signal video_scaler_avalon_scaler_source_valid : std_logic; -- Video_Scaler:stream_out_valid -> Video_DMA:stream_valid
signal video_scaler_avalon_scaler_source_startofpacket : std_logic; -- Video_Scaler:stream_out_startofpacket -> Video_DMA:stream_startofpacket
signal video_scaler_avalon_scaler_source_data : std_logic_vector(15 downto 0); -- Video_Scaler:stream_out_data -> Video_DMA:stream_data
signal video_scaler_avalon_scaler_source_ready : std_logic; -- Video_DMA:stream_ready -> Video_Scaler:stream_out_ready
signal clock_signals_sys_clk_clk : std_logic; -- Clock_Signals:sys_clk -> [AV_Config:clk, AV_Config_avalon_av_config_slave_translator:clk, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:clk, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, CPU:clk, CPU_data_master_translator:clk, CPU_data_master_translator_avalon_universal_master_0_agent:clk, CPU_instruction_master_translator:clk, CPU_instruction_master_translator_avalon_universal_master_0_agent:clk, CPU_jtag_debug_module_translator:clk, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Chroma_Resampler:clk, Color_Space_Converter:clk, Dual_Clock_FIFO:clk_stream_in, Onchip_Memory:clk, Onchip_Memory_s1_translator:clk, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:clk, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_Buffer:clk, Pixel_Buffer_DMA:clk, Pixel_Buffer_DMA_avalon_control_slave_translator:clk, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:clk, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:clk, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:clk, Pixel_Buffer_avalon_sram_slave_translator:clk, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_RGB_Resampler:clk, Pixel_Scaler:clk, Video_Clipper:clk, Video_DMA:clk, Video_DMA_avalon_dma_control_slave_translator:clk, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:clk, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Video_DMA_avalon_dma_master_translator:clk, Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:clk, Video_In_Decoder:clk, Video_RGB_Resampler:clk, Video_Scaler:clk, addr_router:clk, addr_router_001:clk, addr_router_002:clk, addr_router_003:clk, burst_adapter:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_demux_002:clk, cmd_xbar_demux_003:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, irq_mapper:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, width_adapter:clk, width_adapter_001:clk]
signal clock_signals_vga_clk_clk : std_logic; -- Clock_Signals:VGA_CLK -> [Dual_Clock_FIFO:clk_stream_out, VGA_Controller:clk, rst_controller_001:clk]
signal cpu_instruction_master_waitrequest : std_logic; -- CPU_instruction_master_translator:av_waitrequest -> CPU:i_waitrequest
signal cpu_instruction_master_address : std_logic_vector(19 downto 0); -- CPU:i_address -> CPU_instruction_master_translator:av_address
signal cpu_instruction_master_read : std_logic; -- CPU:i_read -> CPU_instruction_master_translator:av_read
signal cpu_instruction_master_readdata : std_logic_vector(31 downto 0); -- CPU_instruction_master_translator:av_readdata -> CPU:i_readdata
signal cpu_data_master_waitrequest : std_logic; -- CPU_data_master_translator:av_waitrequest -> CPU:d_waitrequest
signal cpu_data_master_writedata : std_logic_vector(31 downto 0); -- CPU:d_writedata -> CPU_data_master_translator:av_writedata
signal cpu_data_master_address : std_logic_vector(19 downto 0); -- CPU:d_address -> CPU_data_master_translator:av_address
signal cpu_data_master_write : std_logic; -- CPU:d_write -> CPU_data_master_translator:av_write
signal cpu_data_master_read : std_logic; -- CPU:d_read -> CPU_data_master_translator:av_read
signal cpu_data_master_readdata : std_logic_vector(31 downto 0); -- CPU_data_master_translator:av_readdata -> CPU:d_readdata
signal cpu_data_master_debugaccess : std_logic; -- CPU:jtag_debug_module_debugaccess_to_roms -> CPU_data_master_translator:av_debugaccess
signal cpu_data_master_byteenable : std_logic_vector(3 downto 0); -- CPU:d_byteenable -> CPU_data_master_translator:av_byteenable
signal pixel_buffer_dma_avalon_pixel_dma_master_waitrequest : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_waitrequest -> Pixel_Buffer_DMA:master_waitrequest
signal pixel_buffer_dma_avalon_pixel_dma_master_address : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA:master_address -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_address
signal pixel_buffer_dma_avalon_pixel_dma_master_lock : std_logic; -- Pixel_Buffer_DMA:master_arbiterlock -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_lock
signal pixel_buffer_dma_avalon_pixel_dma_master_read : std_logic; -- Pixel_Buffer_DMA:master_read -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_read
signal pixel_buffer_dma_avalon_pixel_dma_master_readdata : std_logic_vector(15 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_readdata -> Pixel_Buffer_DMA:master_readdata
signal pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_readdatavalid -> Pixel_Buffer_DMA:master_readdatavalid
signal video_dma_avalon_dma_master_waitrequest : std_logic; -- Video_DMA_avalon_dma_master_translator:av_waitrequest -> Video_DMA:master_waitrequest
signal video_dma_avalon_dma_master_writedata : std_logic_vector(15 downto 0); -- Video_DMA:master_writedata -> Video_DMA_avalon_dma_master_translator:av_writedata
signal video_dma_avalon_dma_master_address : std_logic_vector(31 downto 0); -- Video_DMA:master_address -> Video_DMA_avalon_dma_master_translator:av_address
signal video_dma_avalon_dma_master_write : std_logic; -- Video_DMA:master_write -> Video_DMA_avalon_dma_master_translator:av_write
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- CPU_jtag_debug_module_translator:av_writedata -> CPU:jtag_debug_module_writedata
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_address : std_logic_vector(8 downto 0); -- CPU_jtag_debug_module_translator:av_address -> CPU:jtag_debug_module_address
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect : std_logic; -- CPU_jtag_debug_module_translator:av_chipselect -> CPU:jtag_debug_module_select
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_write : std_logic; -- CPU_jtag_debug_module_translator:av_write -> CPU:jtag_debug_module_write
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- CPU:jtag_debug_module_readdata -> CPU_jtag_debug_module_translator:av_readdata
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer : std_logic; -- CPU_jtag_debug_module_translator:av_begintransfer -> CPU:jtag_debug_module_begintransfer
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess : std_logic; -- CPU_jtag_debug_module_translator:av_debugaccess -> CPU:jtag_debug_module_debugaccess
signal cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- CPU_jtag_debug_module_translator:av_byteenable -> CPU:jtag_debug_module_byteenable
signal onchip_memory_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- Onchip_Memory_s1_translator:av_writedata -> Onchip_Memory:writedata
signal onchip_memory_s1_translator_avalon_anti_slave_0_address : std_logic_vector(11 downto 0); -- Onchip_Memory_s1_translator:av_address -> Onchip_Memory:address
signal onchip_memory_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- Onchip_Memory_s1_translator:av_chipselect -> Onchip_Memory:chipselect
signal onchip_memory_s1_translator_avalon_anti_slave_0_clken : std_logic; -- Onchip_Memory_s1_translator:av_clken -> Onchip_Memory:clken
signal onchip_memory_s1_translator_avalon_anti_slave_0_write : std_logic; -- Onchip_Memory_s1_translator:av_write -> Onchip_Memory:write
signal onchip_memory_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- Onchip_Memory:readdata -> Onchip_Memory_s1_translator:av_readdata
signal onchip_memory_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- Onchip_Memory_s1_translator:av_byteenable -> Onchip_Memory:byteenable
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator:av_writedata -> Pixel_Buffer:writedata
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address : std_logic_vector(17 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator:av_address -> Pixel_Buffer:address
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator:av_write -> Pixel_Buffer:write
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator:av_read -> Pixel_Buffer:read
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- Pixel_Buffer:readdata -> Pixel_Buffer_avalon_sram_slave_translator:av_readdata
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- Pixel_Buffer:readdatavalid -> Pixel_Buffer_avalon_sram_slave_translator:av_readdatavalid
signal pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator:av_byteenable -> Pixel_Buffer:byteenable
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- AV_Config:waitrequest -> AV_Config_avalon_av_config_slave_translator:av_waitrequest
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- AV_Config_avalon_av_config_slave_translator:av_writedata -> AV_Config:writedata
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- AV_Config_avalon_av_config_slave_translator:av_address -> AV_Config:address
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write : std_logic; -- AV_Config_avalon_av_config_slave_translator:av_write -> AV_Config:write
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read : std_logic; -- AV_Config_avalon_av_config_slave_translator:av_read -> AV_Config:read
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- AV_Config:readdata -> AV_Config_avalon_av_config_slave_translator:av_readdata
signal av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- AV_Config_avalon_av_config_slave_translator:av_byteenable -> AV_Config:byteenable
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_control_slave_translator:av_writedata -> Video_DMA:slave_writedata
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- Video_DMA_avalon_dma_control_slave_translator:av_address -> Video_DMA:slave_address
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write : std_logic; -- Video_DMA_avalon_dma_control_slave_translator:av_write -> Video_DMA:slave_write
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read : std_logic; -- Video_DMA_avalon_dma_control_slave_translator:av_read -> Video_DMA:slave_read
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- Video_DMA:slave_readdata -> Video_DMA_avalon_dma_control_slave_translator:av_readdata
signal video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- Video_DMA_avalon_dma_control_slave_translator:av_byteenable -> Video_DMA:slave_byteenable
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator:av_writedata -> Pixel_Buffer_DMA:slave_writedata
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator:av_address -> Pixel_Buffer_DMA:slave_address
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator:av_write -> Pixel_Buffer_DMA:slave_write
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator:av_read -> Pixel_Buffer_DMA:slave_read
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA:slave_readdata -> Pixel_Buffer_DMA_avalon_control_slave_translator:av_readdata
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator:av_byteenable -> Pixel_Buffer_DMA:slave_byteenable
signal cpu_instruction_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> CPU_instruction_master_translator:uav_waitrequest
signal cpu_instruction_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- CPU_instruction_master_translator:uav_burstcount -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
signal cpu_instruction_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- CPU_instruction_master_translator:uav_writedata -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
signal cpu_instruction_master_translator_avalon_universal_master_0_address : std_logic_vector(31 downto 0); -- CPU_instruction_master_translator:uav_address -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_address
signal cpu_instruction_master_translator_avalon_universal_master_0_lock : std_logic; -- CPU_instruction_master_translator:uav_lock -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_lock
signal cpu_instruction_master_translator_avalon_universal_master_0_write : std_logic; -- CPU_instruction_master_translator:uav_write -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_write
signal cpu_instruction_master_translator_avalon_universal_master_0_read : std_logic; -- CPU_instruction_master_translator:uav_read -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_read
signal cpu_instruction_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- CPU_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> CPU_instruction_master_translator:uav_readdata
signal cpu_instruction_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- CPU_instruction_master_translator:uav_debugaccess -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal cpu_instruction_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- CPU_instruction_master_translator:uav_byteenable -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
signal cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> CPU_instruction_master_translator:uav_readdatavalid
signal cpu_data_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> CPU_data_master_translator:uav_waitrequest
signal cpu_data_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- CPU_data_master_translator:uav_burstcount -> CPU_data_master_translator_avalon_universal_master_0_agent:av_burstcount
signal cpu_data_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- CPU_data_master_translator:uav_writedata -> CPU_data_master_translator_avalon_universal_master_0_agent:av_writedata
signal cpu_data_master_translator_avalon_universal_master_0_address : std_logic_vector(31 downto 0); -- CPU_data_master_translator:uav_address -> CPU_data_master_translator_avalon_universal_master_0_agent:av_address
signal cpu_data_master_translator_avalon_universal_master_0_lock : std_logic; -- CPU_data_master_translator:uav_lock -> CPU_data_master_translator_avalon_universal_master_0_agent:av_lock
signal cpu_data_master_translator_avalon_universal_master_0_write : std_logic; -- CPU_data_master_translator:uav_write -> CPU_data_master_translator_avalon_universal_master_0_agent:av_write
signal cpu_data_master_translator_avalon_universal_master_0_read : std_logic; -- CPU_data_master_translator:uav_read -> CPU_data_master_translator_avalon_universal_master_0_agent:av_read
signal cpu_data_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- CPU_data_master_translator_avalon_universal_master_0_agent:av_readdata -> CPU_data_master_translator:uav_readdata
signal cpu_data_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- CPU_data_master_translator:uav_debugaccess -> CPU_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal cpu_data_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- CPU_data_master_translator:uav_byteenable -> CPU_data_master_translator_avalon_universal_master_0_agent:av_byteenable
signal cpu_data_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> CPU_data_master_translator:uav_readdatavalid
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_waitrequest -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_waitrequest
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(1 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_burstcount -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_burstcount
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata : std_logic_vector(15 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_writedata -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_writedata
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_address -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_address
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_lock -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_lock
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_write -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_write
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_read -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_read
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata : std_logic_vector(15 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_readdata -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_readdata
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_debugaccess -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(1 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_byteenable -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_byteenable
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_readdatavalid
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_waitrequest -> Video_DMA_avalon_dma_master_translator:uav_waitrequest
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(1 downto 0); -- Video_DMA_avalon_dma_master_translator:uav_burstcount -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_burstcount
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata : std_logic_vector(15 downto 0); -- Video_DMA_avalon_dma_master_translator:uav_writedata -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_writedata
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_address : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_master_translator:uav_address -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_address
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock : std_logic; -- Video_DMA_avalon_dma_master_translator:uav_lock -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_lock
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_write : std_logic; -- Video_DMA_avalon_dma_master_translator:uav_write -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_write
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_read : std_logic; -- Video_DMA_avalon_dma_master_translator:uav_read -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_read
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata : std_logic_vector(15 downto 0); -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_readdata -> Video_DMA_avalon_dma_master_translator:uav_readdata
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- Video_DMA_avalon_dma_master_translator:uav_debugaccess -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(1 downto 0); -- Video_DMA_avalon_dma_master_translator:uav_byteenable -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_byteenable
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> Video_DMA_avalon_dma_master_translator:uav_readdatavalid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- CPU_jtag_debug_module_translator:uav_waitrequest -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> CPU_jtag_debug_module_translator:uav_burstcount
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> CPU_jtag_debug_module_translator:uav_writedata
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> CPU_jtag_debug_module_translator:uav_address
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> CPU_jtag_debug_module_translator:uav_write
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> CPU_jtag_debug_module_translator:uav_lock
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> CPU_jtag_debug_module_translator:uav_read
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- CPU_jtag_debug_module_translator:uav_readdata -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- CPU_jtag_debug_module_translator:uav_readdatavalid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> CPU_jtag_debug_module_translator:uav_debugaccess
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> CPU_jtag_debug_module_translator:uav_byteenable
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(105 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(105 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- Onchip_Memory_s1_translator:uav_waitrequest -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> Onchip_Memory_s1_translator:uav_burstcount
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> Onchip_Memory_s1_translator:uav_writedata
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> Onchip_Memory_s1_translator:uav_address
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> Onchip_Memory_s1_translator:uav_write
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> Onchip_Memory_s1_translator:uav_lock
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> Onchip_Memory_s1_translator:uav_read
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- Onchip_Memory_s1_translator:uav_readdata -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- Onchip_Memory_s1_translator:uav_readdatavalid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Onchip_Memory_s1_translator:uav_debugaccess
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> Onchip_Memory_s1_translator:uav_byteenable
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(105 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(105 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator:uav_waitrequest -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Pixel_Buffer_avalon_sram_slave_translator:uav_burstcount
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Pixel_Buffer_avalon_sram_slave_translator:uav_writedata
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> Pixel_Buffer_avalon_sram_slave_translator:uav_address
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> Pixel_Buffer_avalon_sram_slave_translator:uav_write
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Pixel_Buffer_avalon_sram_slave_translator:uav_lock
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> Pixel_Buffer_avalon_sram_slave_translator:uav_read
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator:uav_readdata -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator:uav_readdatavalid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Pixel_Buffer_avalon_sram_slave_translator:uav_debugaccess
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Pixel_Buffer_avalon_sram_slave_translator:uav_byteenable
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(87 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(87 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(15 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- AV_Config_avalon_av_config_slave_translator:uav_waitrequest -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> AV_Config_avalon_av_config_slave_translator:uav_burstcount
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> AV_Config_avalon_av_config_slave_translator:uav_writedata
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_address -> AV_Config_avalon_av_config_slave_translator:uav_address
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_write -> AV_Config_avalon_av_config_slave_translator:uav_write
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_lock -> AV_Config_avalon_av_config_slave_translator:uav_lock
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_read -> AV_Config_avalon_av_config_slave_translator:uav_read
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- AV_Config_avalon_av_config_slave_translator:uav_readdata -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- AV_Config_avalon_av_config_slave_translator:uav_readdatavalid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> AV_Config_avalon_av_config_slave_translator:uav_debugaccess
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> AV_Config_avalon_av_config_slave_translator:uav_byteenable
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(105 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(105 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- Video_DMA_avalon_dma_control_slave_translator:uav_waitrequest -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Video_DMA_avalon_dma_control_slave_translator:uav_burstcount
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Video_DMA_avalon_dma_control_slave_translator:uav_writedata
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> Video_DMA_avalon_dma_control_slave_translator:uav_address
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> Video_DMA_avalon_dma_control_slave_translator:uav_write
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Video_DMA_avalon_dma_control_slave_translator:uav_lock
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> Video_DMA_avalon_dma_control_slave_translator:uav_read
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_control_slave_translator:uav_readdata -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- Video_DMA_avalon_dma_control_slave_translator:uav_readdatavalid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Video_DMA_avalon_dma_control_slave_translator:uav_debugaccess
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Video_DMA_avalon_dma_control_slave_translator:uav_byteenable
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(105 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(105 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator:uav_waitrequest -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_burstcount
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_writedata
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_address
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_write
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_lock
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_read
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator:uav_readdata -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator:uav_readdatavalid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_debugaccess
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_byteenable
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(105 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(105 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
signal cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
signal cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
signal cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(104 downto 0); -- CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
signal cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
signal cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
signal cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
signal cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
signal cpu_data_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(104 downto 0); -- CPU_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
signal cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_001:sink_ready -> CPU_data_master_translator_avalon_universal_master_0_agent:cp_ready
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(86 downto 0); -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
signal pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_002:sink_ready -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_ready
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_003:sink_endofpacket
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_003:sink_valid
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_003:sink_startofpacket
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(86 downto 0); -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_003:sink_data
signal video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_003:sink_ready -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_ready
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(104 downto 0); -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
signal cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(104 downto 0); -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
signal onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(86 downto 0); -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
signal pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(104 downto 0); -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
signal av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(104 downto 0); -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
signal video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(104 downto 0); -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
signal pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal burst_adapter_source0_endofpacket : std_logic; -- burst_adapter:source0_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_source0_valid : std_logic; -- burst_adapter:source0_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_source0_startofpacket : std_logic; -- burst_adapter:source0_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_source0_data : std_logic_vector(86 downto 0); -- burst_adapter:source0_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_source0_ready : std_logic; -- Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
signal burst_adapter_source0_channel : std_logic_vector(5 downto 0); -- burst_adapter:source0_channel -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [AV_Config:reset, AV_Config_avalon_av_config_slave_translator:reset, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:reset, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, CPU_data_master_translator:reset, CPU_data_master_translator_avalon_universal_master_0_agent:reset, CPU_instruction_master_translator:reset, CPU_instruction_master_translator_avalon_universal_master_0_agent:reset, CPU_jtag_debug_module_translator:reset, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Chroma_Resampler:reset, Color_Space_Converter:reset, Dual_Clock_FIFO:reset_stream_in, Onchip_Memory:reset, Onchip_Memory_s1_translator:reset, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:reset, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_Buffer:reset, Pixel_Buffer_DMA:reset, Pixel_Buffer_DMA_avalon_control_slave_translator:reset, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:reset, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:reset, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:reset, Pixel_Buffer_avalon_sram_slave_translator:reset, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_RGB_Resampler:reset, Pixel_Scaler:reset, Video_Clipper:reset, Video_DMA:reset, Video_DMA_avalon_dma_control_slave_translator:reset, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:reset, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Video_DMA_avalon_dma_master_translator:reset, Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:reset, Video_In_Decoder:reset, Video_RGB_Resampler:reset, Video_Scaler:reset, addr_router:reset, addr_router_001:reset, addr_router_002:reset, addr_router_003:reset, burst_adapter:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_demux_002:reset, cmd_xbar_demux_003:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, irq_mapper:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, rst_controller_reset_out_reset:in, width_adapter:reset, width_adapter_001:reset]
signal cpu_jtag_debug_module_reset_reset : std_logic; -- CPU:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [Dual_Clock_FIFO:reset_stream_out, VGA_Controller:reset]
signal rst_controller_002_reset_out_reset : std_logic; -- rst_controller_002:reset_out -> Clock_Signals:reset
signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
signal cmd_xbar_demux_src0_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
signal cmd_xbar_demux_src0_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
signal cmd_xbar_demux_src0_ready : std_logic; -- cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
signal cmd_xbar_demux_src1_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
signal cmd_xbar_demux_src1_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
signal cmd_xbar_demux_src1_ready : std_logic; -- cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
signal cmd_xbar_demux_001_src0_endofpacket : std_logic; -- cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
signal cmd_xbar_demux_001_src0_valid : std_logic; -- cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
signal cmd_xbar_demux_001_src0_startofpacket : std_logic; -- cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
signal cmd_xbar_demux_001_src0_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
signal cmd_xbar_demux_001_src0_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
signal cmd_xbar_demux_001_src0_ready : std_logic; -- cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
signal cmd_xbar_demux_001_src1_endofpacket : std_logic; -- cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
signal cmd_xbar_demux_001_src1_valid : std_logic; -- cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
signal cmd_xbar_demux_001_src1_startofpacket : std_logic; -- cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
signal cmd_xbar_demux_001_src1_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
signal cmd_xbar_demux_001_src1_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
signal cmd_xbar_demux_001_src1_ready : std_logic; -- cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
signal cmd_xbar_demux_001_src3_endofpacket : std_logic; -- cmd_xbar_demux_001:src3_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src3_valid : std_logic; -- cmd_xbar_demux_001:src3_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src3_startofpacket : std_logic; -- cmd_xbar_demux_001:src3_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src3_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src3_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src3_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src3_channel -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src4_endofpacket : std_logic; -- cmd_xbar_demux_001:src4_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src4_valid : std_logic; -- cmd_xbar_demux_001:src4_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src4_startofpacket : std_logic; -- cmd_xbar_demux_001:src4_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src4_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src4_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src4_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src4_channel -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src5_endofpacket : std_logic; -- cmd_xbar_demux_001:src5_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src5_valid : std_logic; -- cmd_xbar_demux_001:src5_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src5_startofpacket : std_logic; -- cmd_xbar_demux_001:src5_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src5_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src5_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src5_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src5_channel -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_002_src0_endofpacket : std_logic; -- cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket
signal cmd_xbar_demux_002_src0_valid : std_logic; -- cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux_002:sink1_valid
signal cmd_xbar_demux_002_src0_startofpacket : std_logic; -- cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket
signal cmd_xbar_demux_002_src0_data : std_logic_vector(86 downto 0); -- cmd_xbar_demux_002:src0_data -> cmd_xbar_mux_002:sink1_data
signal cmd_xbar_demux_002_src0_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux_002:sink1_channel
signal cmd_xbar_demux_002_src0_ready : std_logic; -- cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_002:src0_ready
signal cmd_xbar_demux_003_src0_endofpacket : std_logic; -- cmd_xbar_demux_003:src0_endofpacket -> cmd_xbar_mux_002:sink2_endofpacket
signal cmd_xbar_demux_003_src0_valid : std_logic; -- cmd_xbar_demux_003:src0_valid -> cmd_xbar_mux_002:sink2_valid
signal cmd_xbar_demux_003_src0_startofpacket : std_logic; -- cmd_xbar_demux_003:src0_startofpacket -> cmd_xbar_mux_002:sink2_startofpacket
signal cmd_xbar_demux_003_src0_data : std_logic_vector(86 downto 0); -- cmd_xbar_demux_003:src0_data -> cmd_xbar_mux_002:sink2_data
signal cmd_xbar_demux_003_src0_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_003:src0_channel -> cmd_xbar_mux_002:sink2_channel
signal cmd_xbar_demux_003_src0_ready : std_logic; -- cmd_xbar_mux_002:sink2_ready -> cmd_xbar_demux_003:src0_ready
signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
signal rsp_xbar_demux_src0_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
signal rsp_xbar_demux_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
signal rsp_xbar_demux_src0_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
signal rsp_xbar_demux_src1_endofpacket : std_logic; -- rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
signal rsp_xbar_demux_src1_valid : std_logic; -- rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
signal rsp_xbar_demux_src1_startofpacket : std_logic; -- rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
signal rsp_xbar_demux_src1_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
signal rsp_xbar_demux_src1_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
signal rsp_xbar_demux_src1_ready : std_logic; -- rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
signal rsp_xbar_demux_001_src0_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
signal rsp_xbar_demux_001_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
signal rsp_xbar_demux_001_src0_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
signal rsp_xbar_demux_001_src1_endofpacket : std_logic; -- rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
signal rsp_xbar_demux_001_src1_valid : std_logic; -- rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
signal rsp_xbar_demux_001_src1_startofpacket : std_logic; -- rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
signal rsp_xbar_demux_001_src1_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
signal rsp_xbar_demux_001_src1_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
signal rsp_xbar_demux_001_src1_ready : std_logic; -- rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
signal rsp_xbar_demux_002_src1_endofpacket : std_logic; -- rsp_xbar_demux_002:src1_endofpacket -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_demux_002_src1_valid : std_logic; -- rsp_xbar_demux_002:src1_valid -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_demux_002_src1_startofpacket : std_logic; -- rsp_xbar_demux_002:src1_startofpacket -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_demux_002_src1_data : std_logic_vector(86 downto 0); -- rsp_xbar_demux_002:src1_data -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_demux_002_src1_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_002:src1_channel -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_demux_002_src2_endofpacket : std_logic; -- rsp_xbar_demux_002:src2_endofpacket -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_demux_002_src2_valid : std_logic; -- rsp_xbar_demux_002:src2_valid -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_demux_002_src2_startofpacket : std_logic; -- rsp_xbar_demux_002:src2_startofpacket -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_demux_002_src2_data : std_logic_vector(86 downto 0); -- rsp_xbar_demux_002:src2_data -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_demux_002_src2_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_002:src2_channel -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid
signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
signal rsp_xbar_demux_003_src0_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data
signal rsp_xbar_demux_003_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel
signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready
signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
signal rsp_xbar_demux_004_src0_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
signal rsp_xbar_demux_004_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
signal rsp_xbar_demux_004_src0_ready : std_logic; -- rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
signal rsp_xbar_demux_005_src0_data : std_logic_vector(104 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
signal rsp_xbar_demux_005_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> cmd_xbar_demux:sink_valid
signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
signal addr_router_src_data : std_logic_vector(104 downto 0); -- addr_router:src_data -> cmd_xbar_demux:sink_data
signal addr_router_src_channel : std_logic_vector(5 downto 0); -- addr_router:src_channel -> cmd_xbar_demux:sink_channel
signal addr_router_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> addr_router:src_ready
signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_src_data : std_logic_vector(104 downto 0); -- rsp_xbar_mux:src_data -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_src_channel : std_logic_vector(5 downto 0); -- rsp_xbar_mux:src_channel -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_src_ready : std_logic; -- CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
signal addr_router_001_src_endofpacket : std_logic; -- addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
signal addr_router_001_src_valid : std_logic; -- addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
signal addr_router_001_src_startofpacket : std_logic; -- addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
signal addr_router_001_src_data : std_logic_vector(104 downto 0); -- addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
signal addr_router_001_src_channel : std_logic_vector(5 downto 0); -- addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
signal addr_router_001_src_ready : std_logic; -- cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
signal rsp_xbar_mux_001_src_endofpacket : std_logic; -- rsp_xbar_mux_001:src_endofpacket -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_001_src_valid : std_logic; -- rsp_xbar_mux_001:src_valid -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_001_src_startofpacket : std_logic; -- rsp_xbar_mux_001:src_startofpacket -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_001_src_data : std_logic_vector(104 downto 0); -- rsp_xbar_mux_001:src_data -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_001_src_channel : std_logic_vector(5 downto 0); -- rsp_xbar_mux_001:src_channel -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_001_src_ready : std_logic; -- CPU_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready
signal addr_router_002_src_endofpacket : std_logic; -- addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
signal addr_router_002_src_valid : std_logic; -- addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
signal addr_router_002_src_startofpacket : std_logic; -- addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
signal addr_router_002_src_data : std_logic_vector(86 downto 0); -- addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
signal addr_router_002_src_channel : std_logic_vector(5 downto 0); -- addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
signal addr_router_002_src_ready : std_logic; -- cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
signal rsp_xbar_demux_002_src1_ready : std_logic; -- Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_002:src1_ready
signal addr_router_003_src_endofpacket : std_logic; -- addr_router_003:src_endofpacket -> cmd_xbar_demux_003:sink_endofpacket
signal addr_router_003_src_valid : std_logic; -- addr_router_003:src_valid -> cmd_xbar_demux_003:sink_valid
signal addr_router_003_src_startofpacket : std_logic; -- addr_router_003:src_startofpacket -> cmd_xbar_demux_003:sink_startofpacket
signal addr_router_003_src_data : std_logic_vector(86 downto 0); -- addr_router_003:src_data -> cmd_xbar_demux_003:sink_data
signal addr_router_003_src_channel : std_logic_vector(5 downto 0); -- addr_router_003:src_channel -> cmd_xbar_demux_003:sink_channel
signal addr_router_003_src_ready : std_logic; -- cmd_xbar_demux_003:sink_ready -> addr_router_003:src_ready
signal rsp_xbar_demux_002_src2_ready : std_logic; -- Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_002:src2_ready
signal cmd_xbar_mux_src_endofpacket : std_logic; -- cmd_xbar_mux:src_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_src_valid : std_logic; -- cmd_xbar_mux:src_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_src_startofpacket : std_logic; -- cmd_xbar_mux:src_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_src_data : std_logic_vector(104 downto 0); -- cmd_xbar_mux:src_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_src_channel : std_logic_vector(5 downto 0); -- cmd_xbar_mux:src_channel -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_src_ready : std_logic; -- CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
signal id_router_src_valid : std_logic; -- id_router:src_valid -> rsp_xbar_demux:sink_valid
signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
signal id_router_src_data : std_logic_vector(104 downto 0); -- id_router:src_data -> rsp_xbar_demux:sink_data
signal id_router_src_channel : std_logic_vector(5 downto 0); -- id_router:src_channel -> rsp_xbar_demux:sink_channel
signal id_router_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> id_router:src_ready
signal cmd_xbar_mux_001_src_endofpacket : std_logic; -- cmd_xbar_mux_001:src_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_001_src_valid : std_logic; -- cmd_xbar_mux_001:src_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_001_src_startofpacket : std_logic; -- cmd_xbar_mux_001:src_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_001_src_data : std_logic_vector(104 downto 0); -- cmd_xbar_mux_001:src_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_001_src_channel : std_logic_vector(5 downto 0); -- cmd_xbar_mux_001:src_channel -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_001_src_ready : std_logic; -- Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
signal id_router_001_src_data : std_logic_vector(104 downto 0); -- id_router_001:src_data -> rsp_xbar_demux_001:sink_data
signal id_router_001_src_channel : std_logic_vector(5 downto 0); -- id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
signal id_router_001_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
signal cmd_xbar_mux_002_src_endofpacket : std_logic; -- cmd_xbar_mux_002:src_endofpacket -> burst_adapter:sink0_endofpacket
signal cmd_xbar_mux_002_src_valid : std_logic; -- cmd_xbar_mux_002:src_valid -> burst_adapter:sink0_valid
signal cmd_xbar_mux_002_src_startofpacket : std_logic; -- cmd_xbar_mux_002:src_startofpacket -> burst_adapter:sink0_startofpacket
signal cmd_xbar_mux_002_src_data : std_logic_vector(86 downto 0); -- cmd_xbar_mux_002:src_data -> burst_adapter:sink0_data
signal cmd_xbar_mux_002_src_channel : std_logic_vector(5 downto 0); -- cmd_xbar_mux_002:src_channel -> burst_adapter:sink0_channel
signal cmd_xbar_mux_002_src_ready : std_logic; -- burst_adapter:sink0_ready -> cmd_xbar_mux_002:src_ready
signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
signal id_router_002_src_data : std_logic_vector(86 downto 0); -- id_router_002:src_data -> rsp_xbar_demux_002:sink_data
signal id_router_002_src_channel : std_logic_vector(5 downto 0); -- id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
signal id_router_002_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
signal cmd_xbar_demux_001_src3_ready : std_logic; -- AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
signal id_router_003_src_data : std_logic_vector(104 downto 0); -- id_router_003:src_data -> rsp_xbar_demux_003:sink_data
signal id_router_003_src_channel : std_logic_vector(5 downto 0); -- id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
signal id_router_003_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
signal cmd_xbar_demux_001_src4_ready : std_logic; -- Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
signal id_router_004_src_data : std_logic_vector(104 downto 0); -- id_router_004:src_data -> rsp_xbar_demux_004:sink_data
signal id_router_004_src_channel : std_logic_vector(5 downto 0); -- id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
signal id_router_004_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
signal cmd_xbar_demux_001_src5_ready : std_logic; -- Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
signal id_router_005_src_data : std_logic_vector(104 downto 0); -- id_router_005:src_data -> rsp_xbar_demux_005:sink_data
signal id_router_005_src_channel : std_logic_vector(5 downto 0); -- id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
signal id_router_005_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
signal cmd_xbar_demux_001_src2_endofpacket : std_logic; -- cmd_xbar_demux_001:src2_endofpacket -> width_adapter:in_endofpacket
signal cmd_xbar_demux_001_src2_valid : std_logic; -- cmd_xbar_demux_001:src2_valid -> width_adapter:in_valid
signal cmd_xbar_demux_001_src2_startofpacket : std_logic; -- cmd_xbar_demux_001:src2_startofpacket -> width_adapter:in_startofpacket
signal cmd_xbar_demux_001_src2_data : std_logic_vector(104 downto 0); -- cmd_xbar_demux_001:src2_data -> width_adapter:in_data
signal cmd_xbar_demux_001_src2_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux_001:src2_channel -> width_adapter:in_channel
signal cmd_xbar_demux_001_src2_ready : std_logic; -- width_adapter:in_ready -> cmd_xbar_demux_001:src2_ready
signal width_adapter_src_endofpacket : std_logic; -- width_adapter:out_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
signal width_adapter_src_valid : std_logic; -- width_adapter:out_valid -> cmd_xbar_mux_002:sink0_valid
signal width_adapter_src_startofpacket : std_logic; -- width_adapter:out_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
signal width_adapter_src_data : std_logic_vector(86 downto 0); -- width_adapter:out_data -> cmd_xbar_mux_002:sink0_data
signal width_adapter_src_ready : std_logic; -- cmd_xbar_mux_002:sink0_ready -> width_adapter:out_ready
signal width_adapter_src_channel : std_logic_vector(5 downto 0); -- width_adapter:out_channel -> cmd_xbar_mux_002:sink0_channel
signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> width_adapter_001:in_endofpacket
signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> width_adapter_001:in_valid
signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> width_adapter_001:in_startofpacket
signal rsp_xbar_demux_002_src0_data : std_logic_vector(86 downto 0); -- rsp_xbar_demux_002:src0_data -> width_adapter_001:in_data
signal rsp_xbar_demux_002_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_002:src0_channel -> width_adapter_001:in_channel
signal rsp_xbar_demux_002_src0_ready : std_logic; -- width_adapter_001:in_ready -> rsp_xbar_demux_002:src0_ready
signal width_adapter_001_src_endofpacket : std_logic; -- width_adapter_001:out_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
signal width_adapter_001_src_valid : std_logic; -- width_adapter_001:out_valid -> rsp_xbar_mux_001:sink2_valid
signal width_adapter_001_src_startofpacket : std_logic; -- width_adapter_001:out_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
signal width_adapter_001_src_data : std_logic_vector(104 downto 0); -- width_adapter_001:out_data -> rsp_xbar_mux_001:sink2_data
signal width_adapter_001_src_ready : std_logic; -- rsp_xbar_mux_001:sink2_ready -> width_adapter_001:out_ready
signal width_adapter_001_src_channel : std_logic_vector(5 downto 0); -- width_adapter_001:out_channel -> rsp_xbar_mux_001:sink2_channel
signal cpu_d_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> CPU:d_irq
signal reset_n_ports_inv : std_logic; -- reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0]
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> CPU:reset_n
begin
onchip_memory : component Video_System_Onchip_Memory
port map (
clk => clock_signals_sys_clk_clk, -- clk1.clk
address => onchip_memory_s1_translator_avalon_anti_slave_0_address, -- s1.address
chipselect => onchip_memory_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
clken => onchip_memory_s1_translator_avalon_anti_slave_0_clken, -- .clken
readdata => onchip_memory_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
write => onchip_memory_s1_translator_avalon_anti_slave_0_write, -- .write
writedata => onchip_memory_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
byteenable => onchip_memory_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset -- reset1.reset
);
dual_clock_fifo : component Video_System_Dual_Clock_FIFO
port map (
clk_stream_in => clock_signals_sys_clk_clk, -- clock_stream_in.clk
reset_stream_in => rst_controller_reset_out_reset, -- clock_stream_in_reset.reset
clk_stream_out => clock_signals_vga_clk_clk, -- clock_stream_out.clk
reset_stream_out => rst_controller_001_reset_out_reset, -- clock_stream_out_reset.reset
stream_in_ready => pixel_scaler_avalon_scaler_source_ready, -- avalon_dc_buffer_sink.ready
stream_in_startofpacket => pixel_scaler_avalon_scaler_source_startofpacket, -- .startofpacket
stream_in_endofpacket => pixel_scaler_avalon_scaler_source_endofpacket, -- .endofpacket
stream_in_valid => pixel_scaler_avalon_scaler_source_valid, -- .valid
stream_in_data => pixel_scaler_avalon_scaler_source_data, -- .data
stream_out_ready => dual_clock_fifo_avalon_dc_buffer_source_ready, -- avalon_dc_buffer_source.ready
stream_out_startofpacket => dual_clock_fifo_avalon_dc_buffer_source_startofpacket, -- .startofpacket
stream_out_endofpacket => dual_clock_fifo_avalon_dc_buffer_source_endofpacket, -- .endofpacket
stream_out_valid => dual_clock_fifo_avalon_dc_buffer_source_valid, -- .valid
stream_out_data => dual_clock_fifo_avalon_dc_buffer_source_data -- .data
);
pixel_buffer : component Video_System_Pixel_Buffer
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
SRAM_DQ => SRAM_DQ_to_and_from_the_Pixel_Buffer, -- external_interface.export
SRAM_ADDR => SRAM_ADDR_from_the_Pixel_Buffer, -- .export
SRAM_LB_N => SRAM_LB_N_from_the_Pixel_Buffer, -- .export
SRAM_UB_N => SRAM_UB_N_from_the_Pixel_Buffer, -- .export
SRAM_CE_N => SRAM_CE_N_from_the_Pixel_Buffer, -- .export
SRAM_OE_N => SRAM_OE_N_from_the_Pixel_Buffer, -- .export
SRAM_WE_N => SRAM_WE_N_from_the_Pixel_Buffer, -- .export
address => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_sram_slave.address
byteenable => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
read => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
write => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
readdatavalid => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid -- .readdatavalid
);
pixel_buffer_dma : component Video_System_Pixel_Buffer_DMA
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
master_readdatavalid => pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid, -- avalon_pixel_dma_master.readdatavalid
master_waitrequest => pixel_buffer_dma_avalon_pixel_dma_master_waitrequest, -- .waitrequest
master_address => pixel_buffer_dma_avalon_pixel_dma_master_address, -- .address
master_arbiterlock => pixel_buffer_dma_avalon_pixel_dma_master_lock, -- .lock
master_read => pixel_buffer_dma_avalon_pixel_dma_master_read, -- .read
master_readdata => pixel_buffer_dma_avalon_pixel_dma_master_readdata, -- .readdata
slave_address => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address, -- avalon_control_slave.address
slave_byteenable => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
slave_read => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read, -- .read
slave_write => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write, -- .write
slave_writedata => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
slave_readdata => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
stream_ready => pixel_buffer_dma_avalon_pixel_source_ready, -- avalon_pixel_source.ready
stream_startofpacket => pixel_buffer_dma_avalon_pixel_source_startofpacket, -- .startofpacket
stream_endofpacket => pixel_buffer_dma_avalon_pixel_source_endofpacket, -- .endofpacket
stream_valid => pixel_buffer_dma_avalon_pixel_source_valid, -- .valid
stream_data => pixel_buffer_dma_avalon_pixel_source_data -- .data
);
pixel_rgb_resampler : component Video_System_Pixel_RGB_Resampler
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => pixel_buffer_dma_avalon_pixel_source_startofpacket, -- avalon_rgb_sink.startofpacket
stream_in_endofpacket => pixel_buffer_dma_avalon_pixel_source_endofpacket, -- .endofpacket
stream_in_valid => pixel_buffer_dma_avalon_pixel_source_valid, -- .valid
stream_in_ready => pixel_buffer_dma_avalon_pixel_source_ready, -- .ready
stream_in_data => pixel_buffer_dma_avalon_pixel_source_data, -- .data
stream_out_ready => pixel_rgb_resampler_avalon_rgb_source_ready, -- avalon_rgb_source.ready
stream_out_startofpacket => pixel_rgb_resampler_avalon_rgb_source_startofpacket, -- .startofpacket
stream_out_endofpacket => pixel_rgb_resampler_avalon_rgb_source_endofpacket, -- .endofpacket
stream_out_valid => pixel_rgb_resampler_avalon_rgb_source_valid, -- .valid
stream_out_data => pixel_rgb_resampler_avalon_rgb_source_data -- .data
);
pixel_scaler : component Video_System_Pixel_Scaler
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => pixel_rgb_resampler_avalon_rgb_source_startofpacket, -- avalon_scaler_sink.startofpacket
stream_in_endofpacket => pixel_rgb_resampler_avalon_rgb_source_endofpacket, -- .endofpacket
stream_in_valid => pixel_rgb_resampler_avalon_rgb_source_valid, -- .valid
stream_in_ready => pixel_rgb_resampler_avalon_rgb_source_ready, -- .ready
stream_in_data => pixel_rgb_resampler_avalon_rgb_source_data, -- .data
stream_out_ready => pixel_scaler_avalon_scaler_source_ready, -- avalon_scaler_source.ready
stream_out_startofpacket => pixel_scaler_avalon_scaler_source_startofpacket, -- .startofpacket
stream_out_endofpacket => pixel_scaler_avalon_scaler_source_endofpacket, -- .endofpacket
stream_out_valid => pixel_scaler_avalon_scaler_source_valid, -- .valid
stream_out_data => pixel_scaler_avalon_scaler_source_data -- .data
);
vga_controller : component Video_System_VGA_Controller
port map (
clk => clock_signals_vga_clk_clk, -- clock_reset.clk
reset => rst_controller_001_reset_out_reset, -- clock_reset_reset.reset
data => dual_clock_fifo_avalon_dc_buffer_source_data, -- avalon_vga_sink.data
startofpacket => dual_clock_fifo_avalon_dc_buffer_source_startofpacket, -- .startofpacket
endofpacket => dual_clock_fifo_avalon_dc_buffer_source_endofpacket, -- .endofpacket
valid => dual_clock_fifo_avalon_dc_buffer_source_valid, -- .valid
ready => dual_clock_fifo_avalon_dc_buffer_source_ready, -- .ready
VGA_CLK => VGA_CLK_from_the_VGA_Controller, -- external_interface.export
VGA_HS => VGA_HS_from_the_VGA_Controller, -- .export
VGA_VS => VGA_VS_from_the_VGA_Controller, -- .export
VGA_BLANK => VGA_BLANK_from_the_VGA_Controller, -- .export
VGA_SYNC => VGA_SYNC_from_the_VGA_Controller, -- .export
VGA_R => VGA_R_from_the_VGA_Controller, -- .export
VGA_G => VGA_G_from_the_VGA_Controller, -- .export
VGA_B => VGA_B_from_the_VGA_Controller -- .export
);
video_in_decoder : component Video_System_Video_In_Decoder
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_out_ready => video_in_decoder_avalon_decoder_source_ready, -- avalon_decoder_source.ready
stream_out_startofpacket => video_in_decoder_avalon_decoder_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_in_decoder_avalon_decoder_source_endofpacket, -- .endofpacket
stream_out_valid => video_in_decoder_avalon_decoder_source_valid, -- .valid
stream_out_data => video_in_decoder_avalon_decoder_source_data, -- .data
TD_CLK27 => TD_CLK27_to_the_Video_In_Decoder, -- external_interface.export
TD_DATA => TD_DATA_to_the_Video_In_Decoder, -- .export
TD_HS => TD_HS_to_the_Video_In_Decoder, -- .export
TD_VS => TD_VS_to_the_Video_In_Decoder, -- .export
TD_RESET => TD_RESET_from_the_Video_In_Decoder, -- .export
overflow_flag => overflow_flag_from_the_Video_In_Decoder -- .export
);
chroma_resampler : component Video_System_Chroma_Resampler
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => video_in_decoder_avalon_decoder_source_startofpacket, -- avalon_chroma_sink.startofpacket
stream_in_endofpacket => video_in_decoder_avalon_decoder_source_endofpacket, -- .endofpacket
stream_in_valid => video_in_decoder_avalon_decoder_source_valid, -- .valid
stream_in_ready => video_in_decoder_avalon_decoder_source_ready, -- .ready
stream_in_data => video_in_decoder_avalon_decoder_source_data, -- .data
stream_out_ready => chroma_resampler_avalon_chroma_source_ready, -- avalon_chroma_source.ready
stream_out_startofpacket => chroma_resampler_avalon_chroma_source_startofpacket, -- .startofpacket
stream_out_endofpacket => chroma_resampler_avalon_chroma_source_endofpacket, -- .endofpacket
stream_out_valid => chroma_resampler_avalon_chroma_source_valid, -- .valid
stream_out_data => chroma_resampler_avalon_chroma_source_data -- .data
);
color_space_converter : component Video_System_Color_Space_Converter
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => chroma_resampler_avalon_chroma_source_startofpacket, -- avalon_csc_sink.startofpacket
stream_in_endofpacket => chroma_resampler_avalon_chroma_source_endofpacket, -- .endofpacket
stream_in_valid => chroma_resampler_avalon_chroma_source_valid, -- .valid
stream_in_ready => chroma_resampler_avalon_chroma_source_ready, -- .ready
stream_in_data => chroma_resampler_avalon_chroma_source_data, -- .data
stream_out_ready => color_space_converter_avalon_csc_source_ready, -- avalon_csc_source.ready
stream_out_startofpacket => color_space_converter_avalon_csc_source_startofpacket, -- .startofpacket
stream_out_endofpacket => color_space_converter_avalon_csc_source_endofpacket, -- .endofpacket
stream_out_valid => color_space_converter_avalon_csc_source_valid, -- .valid
stream_out_data => color_space_converter_avalon_csc_source_data -- .data
);
video_rgb_resampler : component Video_System_Video_RGB_Resampler
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => color_space_converter_avalon_csc_source_startofpacket, -- avalon_rgb_sink.startofpacket
stream_in_endofpacket => color_space_converter_avalon_csc_source_endofpacket, -- .endofpacket
stream_in_valid => color_space_converter_avalon_csc_source_valid, -- .valid
stream_in_ready => color_space_converter_avalon_csc_source_ready, -- .ready
stream_in_data => color_space_converter_avalon_csc_source_data, -- .data
stream_out_ready => video_rgb_resampler_avalon_rgb_source_ready, -- avalon_rgb_source.ready
stream_out_startofpacket => video_rgb_resampler_avalon_rgb_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_rgb_resampler_avalon_rgb_source_endofpacket, -- .endofpacket
stream_out_valid => video_rgb_resampler_avalon_rgb_source_valid, -- .valid
stream_out_data => video_rgb_resampler_avalon_rgb_source_data -- .data
);
video_clipper : component Video_System_Video_Clipper
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_data => video_rgb_resampler_avalon_rgb_source_data, -- avalon_clipper_sink.data
stream_in_startofpacket => video_rgb_resampler_avalon_rgb_source_startofpacket, -- .startofpacket
stream_in_endofpacket => video_rgb_resampler_avalon_rgb_source_endofpacket, -- .endofpacket
stream_in_valid => video_rgb_resampler_avalon_rgb_source_valid, -- .valid
stream_in_ready => video_rgb_resampler_avalon_rgb_source_ready, -- .ready
stream_out_ready => video_clipper_avalon_clipper_source_ready, -- avalon_clipper_source.ready
stream_out_data => video_clipper_avalon_clipper_source_data, -- .data
stream_out_startofpacket => video_clipper_avalon_clipper_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_clipper_avalon_clipper_source_endofpacket, -- .endofpacket
stream_out_valid => video_clipper_avalon_clipper_source_valid -- .valid
);
video_scaler : component Video_System_Video_Scaler
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_in_startofpacket => video_clipper_avalon_clipper_source_startofpacket, -- avalon_scaler_sink.startofpacket
stream_in_endofpacket => video_clipper_avalon_clipper_source_endofpacket, -- .endofpacket
stream_in_valid => video_clipper_avalon_clipper_source_valid, -- .valid
stream_in_ready => video_clipper_avalon_clipper_source_ready, -- .ready
stream_in_data => video_clipper_avalon_clipper_source_data, -- .data
stream_out_ready => video_scaler_avalon_scaler_source_ready, -- avalon_scaler_source.ready
stream_out_startofpacket => video_scaler_avalon_scaler_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_scaler_avalon_scaler_source_endofpacket, -- .endofpacket
stream_out_valid => video_scaler_avalon_scaler_source_valid, -- .valid
stream_out_data => video_scaler_avalon_scaler_source_data -- .data
);
video_dma : component Video_System_Video_DMA
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
stream_data => video_scaler_avalon_scaler_source_data, -- avalon_dma_sink.data
stream_startofpacket => video_scaler_avalon_scaler_source_startofpacket, -- .startofpacket
stream_endofpacket => video_scaler_avalon_scaler_source_endofpacket, -- .endofpacket
stream_valid => video_scaler_avalon_scaler_source_valid, -- .valid
stream_ready => video_scaler_avalon_scaler_source_ready, -- .ready
slave_address => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address, -- avalon_dma_control_slave.address
slave_byteenable => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
slave_read => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read, -- .read
slave_write => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write, -- .write
slave_writedata => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
slave_readdata => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
master_address => video_dma_avalon_dma_master_address, -- avalon_dma_master.address
master_waitrequest => video_dma_avalon_dma_master_waitrequest, -- .waitrequest
master_write => video_dma_avalon_dma_master_write, -- .write
master_writedata => video_dma_avalon_dma_master_writedata -- .writedata
);
av_config : component Video_System_AV_Config
port map (
clk => clock_signals_sys_clk_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
address => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address, -- avalon_av_config_slave.address
byteenable => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
read => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read, -- .read
write => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
waitrequest => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
I2C_SDAT => I2C_SDAT_to_and_from_the_AV_Config, -- external_interface.export
I2C_SCLK => I2C_SCLK_from_the_AV_Config -- .export
);
cpu : component Video_System_CPU
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
d_address => cpu_data_master_address, -- data_master.address
d_byteenable => cpu_data_master_byteenable, -- .byteenable
d_read => cpu_data_master_read, -- .read
d_readdata => cpu_data_master_readdata, -- .readdata
d_waitrequest => cpu_data_master_waitrequest, -- .waitrequest
d_write => cpu_data_master_write, -- .write
d_writedata => cpu_data_master_writedata, -- .writedata
jtag_debug_module_debugaccess_to_roms => cpu_data_master_debugaccess, -- .debugaccess
i_address => cpu_instruction_master_address, -- instruction_master.address
i_read => cpu_instruction_master_read, -- .read
i_readdata => cpu_instruction_master_readdata, -- .readdata
i_waitrequest => cpu_instruction_master_waitrequest, -- .waitrequest
d_irq => cpu_d_irq_irq, -- d_irq.irq
jtag_debug_module_resetrequest => cpu_jtag_debug_module_reset_reset, -- jtag_debug_module_reset.reset
jtag_debug_module_address => cpu_jtag_debug_module_translator_avalon_anti_slave_0_address, -- jtag_debug_module.address
jtag_debug_module_begintransfer => cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer, -- .begintransfer
jtag_debug_module_byteenable => cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
jtag_debug_module_debugaccess => cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
jtag_debug_module_readdata => cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
jtag_debug_module_select => cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect, -- .chipselect
jtag_debug_module_write => cpu_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
jtag_debug_module_writedata => cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
no_ci_readra => open -- custom_instruction_master.readra
);
clock_signals : component Video_System_Clock_Signals
port map (
CLOCK_50 => clk_0, -- clk_in_primary.clk
reset => rst_controller_002_reset_out_reset, -- clk_in_primary_reset.reset
sys_clk => clock_signals_sys_clk_clk, -- sys_clk.clk
sys_reset_n => open, -- sys_clk_reset.reset_n
VGA_CLK => clock_signals_vga_clk_clk -- vga_clk.clk
);
cpu_instruction_master_translator : component Video_System_CPU_instruction_master_translator
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => cpu_instruction_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => cpu_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => cpu_instruction_master_translator_avalon_universal_master_0_read, -- .read
uav_write => cpu_instruction_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => cpu_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => cpu_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => cpu_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => cpu_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => cpu_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => cpu_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => cpu_instruction_master_address, -- avalon_anti_master_0.address
av_waitrequest => cpu_instruction_master_waitrequest, -- .waitrequest
av_read => cpu_instruction_master_read, -- .read
av_readdata => cpu_instruction_master_readdata -- .readdata
);
cpu_data_master_translator : component Video_System_CPU_data_master_translator
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => cpu_data_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => cpu_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => cpu_data_master_translator_avalon_universal_master_0_read, -- .read
uav_write => cpu_data_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => cpu_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => cpu_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => cpu_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => cpu_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => cpu_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => cpu_data_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => cpu_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => cpu_data_master_address, -- avalon_anti_master_0.address
av_waitrequest => cpu_data_master_waitrequest, -- .waitrequest
av_byteenable => cpu_data_master_byteenable, -- .byteenable
av_read => cpu_data_master_read, -- .read
av_readdata => cpu_data_master_readdata, -- .readdata
av_write => cpu_data_master_write, -- .write
av_writedata => cpu_data_master_writedata, -- .writedata
av_debugaccess => cpu_data_master_debugaccess -- .debugaccess
);
pixel_buffer_dma_avalon_pixel_dma_master_translator : component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read, -- .read
uav_write => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => pixel_buffer_dma_avalon_pixel_dma_master_address, -- avalon_anti_master_0.address
av_waitrequest => pixel_buffer_dma_avalon_pixel_dma_master_waitrequest, -- .waitrequest
av_read => pixel_buffer_dma_avalon_pixel_dma_master_read, -- .read
av_readdata => pixel_buffer_dma_avalon_pixel_dma_master_readdata, -- .readdata
av_readdatavalid => pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid, -- .readdatavalid
av_lock => pixel_buffer_dma_avalon_pixel_dma_master_lock -- .lock
);
video_dma_avalon_dma_master_translator : component Video_System_Video_DMA_avalon_dma_master_translator
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => video_dma_avalon_dma_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => video_dma_avalon_dma_master_translator_avalon_universal_master_0_read, -- .read
uav_write => video_dma_avalon_dma_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => video_dma_avalon_dma_master_address, -- avalon_anti_master_0.address
av_waitrequest => video_dma_avalon_dma_master_waitrequest, -- .waitrequest
av_write => video_dma_avalon_dma_master_write, -- .write
av_writedata => video_dma_avalon_dma_master_writedata -- .writedata
);
cpu_jtag_debug_module_translator : component video_system_cpu_jtag_debug_module_translator
generic map (
AV_ADDRESS_W => 9,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => cpu_jtag_debug_module_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => cpu_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
av_readdata => cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
av_begintransfer => cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer, -- .begintransfer
av_byteenable => cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_debugaccess => cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
av_read => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open -- (terminated)
);
onchip_memory_s1_translator : component video_system_onchip_memory_s1_translator
generic map (
AV_ADDRESS_W => 12,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => onchip_memory_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => onchip_memory_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => onchip_memory_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => onchip_memory_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => onchip_memory_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => onchip_memory_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_clken => onchip_memory_s1_translator_avalon_anti_slave_0_clken, -- .clken
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
pixel_buffer_avalon_sram_slave_translator : component video_system_pixel_buffer_avalon_sram_slave_translator
generic map (
AV_ADDRESS_W => 18,
AV_DATA_W => 16,
UAV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 2,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
av_config_avalon_av_config_slave_translator : component video_system_av_config_avalon_av_config_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
video_dma_avalon_dma_control_slave_translator : component video_system_av_config_avalon_av_config_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
pixel_buffer_dma_avalon_control_slave_translator : component video_system_av_config_avalon_av_config_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 32,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
cpu_instruction_master_translator_avalon_universal_master_0_agent : component Video_System_CPU_instruction_master_translator_avalon_universal_master_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => cpu_instruction_master_translator_avalon_universal_master_0_address, -- av.address
av_write => cpu_instruction_master_translator_avalon_universal_master_0_write, -- .write
av_read => cpu_instruction_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => cpu_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => cpu_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => cpu_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => cpu_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => cpu_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => cpu_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => cpu_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_src_data, -- .data
rp_channel => rsp_xbar_mux_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_src_ready -- .ready
);
cpu_data_master_translator_avalon_universal_master_0_agent : component Video_System_CPU_data_master_translator_avalon_universal_master_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => cpu_data_master_translator_avalon_universal_master_0_address, -- av.address
av_write => cpu_data_master_translator_avalon_universal_master_0_write, -- .write
av_read => cpu_data_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => cpu_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => cpu_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => cpu_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => cpu_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => cpu_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => cpu_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => cpu_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => cpu_data_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => cpu_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_001_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_001_src_data, -- .data
rp_channel => rsp_xbar_mux_001_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_001_src_ready -- .ready
);
pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent : component Video_System_Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address, -- av.address
av_write => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write, -- .write
av_read => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_demux_002_src1_valid, -- rp.valid
rp_data => rsp_xbar_demux_002_src1_data, -- .data
rp_channel => rsp_xbar_demux_002_src1_channel, -- .channel
rp_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_demux_002_src1_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_demux_002_src1_ready -- .ready
);
video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent : component Video_System_Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => video_dma_avalon_dma_master_translator_avalon_universal_master_0_address, -- av.address
av_write => video_dma_avalon_dma_master_translator_avalon_universal_master_0_write, -- .write
av_read => video_dma_avalon_dma_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_demux_002_src2_valid, -- rp.valid
rp_data => rsp_xbar_demux_002_src2_data, -- .data
rp_channel => rsp_xbar_demux_002_src2_channel, -- .channel
rp_startofpacket => rsp_xbar_demux_002_src2_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_demux_002_src2_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_demux_002_src2_ready -- .ready
);
cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_src_valid, -- .valid
cp_data => cmd_xbar_mux_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_src_channel, -- .channel
rf_sink_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
onchip_memory_s1_translator_avalon_universal_slave_0_agent : component Video_System_Onchip_Memory_s1_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_001_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_001_src_valid, -- .valid
cp_data => cmd_xbar_mux_001_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_001_src_channel, -- .channel
rf_sink_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent : component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_source0_ready, -- cp.ready
cp_valid => burst_adapter_source0_valid, -- .valid
cp_data => burst_adapter_source0_data, -- .data
cp_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_source0_channel, -- .channel
rf_sink_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent : component Video_System_AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src3_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src3_valid, -- .valid
cp_data => cmd_xbar_demux_001_src3_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src3_channel, -- .channel
rf_sink_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent : component Video_System_Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src4_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src4_valid, -- .valid
cp_data => cmd_xbar_demux_001_src4_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src4_channel, -- .channel
rf_sink_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent : component Video_System_Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src5_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src5_valid, -- .valid
cp_data => cmd_xbar_demux_001_src5_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src5_channel, -- .channel
rf_sink_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component Video_System_CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
addr_router : component Video_System_addr_router
port map (
sink_ready => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_src_ready, -- src.ready
src_valid => addr_router_src_valid, -- .valid
src_data => addr_router_src_data, -- .data
src_channel => addr_router_src_channel, -- .channel
src_startofpacket => addr_router_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_src_endofpacket -- .endofpacket
);
addr_router_001 : component Video_System_addr_router_001
port map (
sink_ready => cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => cpu_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_001_src_ready, -- src.ready
src_valid => addr_router_001_src_valid, -- .valid
src_data => addr_router_001_src_data, -- .data
src_channel => addr_router_001_src_channel, -- .channel
src_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_001_src_endofpacket -- .endofpacket
);
addr_router_002 : component Video_System_addr_router_002
port map (
sink_ready => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_002_src_ready, -- src.ready
src_valid => addr_router_002_src_valid, -- .valid
src_data => addr_router_002_src_data, -- .data
src_channel => addr_router_002_src_channel, -- .channel
src_startofpacket => addr_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_002_src_endofpacket -- .endofpacket
);
addr_router_003 : component Video_System_addr_router_002
port map (
sink_ready => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_003_src_ready, -- src.ready
src_valid => addr_router_003_src_valid, -- .valid
src_data => addr_router_003_src_data, -- .data
src_channel => addr_router_003_src_channel, -- .channel
src_startofpacket => addr_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_003_src_endofpacket -- .endofpacket
);
id_router : component Video_System_id_router
port map (
sink_ready => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_src_ready, -- src.ready
src_valid => id_router_src_valid, -- .valid
src_data => id_router_src_data, -- .data
src_channel => id_router_src_channel, -- .channel
src_startofpacket => id_router_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_src_endofpacket -- .endofpacket
);
id_router_001 : component Video_System_id_router
port map (
sink_ready => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_001_src_ready, -- src.ready
src_valid => id_router_001_src_valid, -- .valid
src_data => id_router_001_src_data, -- .data
src_channel => id_router_001_src_channel, -- .channel
src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_001_src_endofpacket -- .endofpacket
);
id_router_002 : component Video_System_id_router_002
port map (
sink_ready => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_002_src_ready, -- src.ready
src_valid => id_router_002_src_valid, -- .valid
src_data => id_router_002_src_data, -- .data
src_channel => id_router_002_src_channel, -- .channel
src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_002_src_endofpacket -- .endofpacket
);
id_router_003 : component Video_System_id_router_003
port map (
sink_ready => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_003_src_ready, -- src.ready
src_valid => id_router_003_src_valid, -- .valid
src_data => id_router_003_src_data, -- .data
src_channel => id_router_003_src_channel, -- .channel
src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_003_src_endofpacket -- .endofpacket
);
id_router_004 : component Video_System_id_router_003
port map (
sink_ready => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_004_src_ready, -- src.ready
src_valid => id_router_004_src_valid, -- .valid
src_data => id_router_004_src_data, -- .data
src_channel => id_router_004_src_channel, -- .channel
src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_004_src_endofpacket -- .endofpacket
);
id_router_005 : component Video_System_id_router_003
port map (
sink_ready => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_005_src_ready, -- src.ready
src_valid => id_router_005_src_valid, -- .valid
src_data => id_router_005_src_data, -- .data
src_channel => id_router_005_src_channel, -- .channel
src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_005_src_endofpacket -- .endofpacket
);
burst_adapter : component Video_System_burst_adapter
port map (
clk => clock_signals_sys_clk_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => cmd_xbar_mux_002_src_valid, -- sink0.valid
sink0_data => cmd_xbar_mux_002_src_data, -- .data
sink0_channel => cmd_xbar_mux_002_src_channel, -- .channel
sink0_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_mux_002_src_ready, -- .ready
source0_valid => burst_adapter_source0_valid, -- source0.valid
source0_data => burst_adapter_source0_data, -- .data
source0_channel => burst_adapter_source0_channel, -- .channel
source0_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_source0_ready -- .ready
);
rst_controller : component Video_System_rst_controller
port map (
reset_in0 => reset_n_ports_inv, -- reset_in0.reset
reset_in1 => cpu_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clock_signals_sys_clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset -- reset_out.reset
);
rst_controller_001 : component Video_System_rst_controller
port map (
reset_in0 => reset_n_ports_inv, -- reset_in0.reset
reset_in1 => cpu_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clock_signals_vga_clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset -- reset_out.reset
);
rst_controller_002 : component Video_System_rst_controller
port map (
reset_in0 => reset_n_ports_inv, -- reset_in0.reset
reset_in1 => cpu_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clk_0, -- clk.clk
reset_out => rst_controller_002_reset_out_reset -- reset_out.reset
);
cmd_xbar_demux : component Video_System_cmd_xbar_demux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_src_ready, -- sink.ready
sink_channel => addr_router_src_channel, -- .channel
sink_data => addr_router_src_data, -- .data
sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_src_valid, -- .valid
src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_src0_valid, -- .valid
src0_data => cmd_xbar_demux_src0_data, -- .data
src0_channel => cmd_xbar_demux_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_src1_valid, -- .valid
src1_data => cmd_xbar_demux_src1_data, -- .data
src1_channel => cmd_xbar_demux_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_src1_endofpacket -- .endofpacket
);
cmd_xbar_demux_001 : component Video_System_cmd_xbar_demux_001
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_001_src_ready, -- sink.ready
sink_channel => addr_router_001_src_channel, -- .channel
sink_data => addr_router_001_src_data, -- .data
sink_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_001_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_001_src_valid, -- .valid
src0_ready => cmd_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_001_src0_valid, -- .valid
src0_data => cmd_xbar_demux_001_src0_data, -- .data
src0_channel => cmd_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
src1_data => cmd_xbar_demux_001_src1_data, -- .data
src1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_001_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_001_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_001_src2_valid, -- .valid
src2_data => cmd_xbar_demux_001_src2_data, -- .data
src2_channel => cmd_xbar_demux_001_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_001_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_001_src3_valid, -- .valid
src3_data => cmd_xbar_demux_001_src3_data, -- .data
src3_channel => cmd_xbar_demux_001_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_001_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_001_src4_valid, -- .valid
src4_data => cmd_xbar_demux_001_src4_data, -- .data
src4_channel => cmd_xbar_demux_001_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
src5_ready => cmd_xbar_demux_001_src5_ready, -- src5.ready
src5_valid => cmd_xbar_demux_001_src5_valid, -- .valid
src5_data => cmd_xbar_demux_001_src5_data, -- .data
src5_channel => cmd_xbar_demux_001_src5_channel, -- .channel
src5_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
src5_endofpacket => cmd_xbar_demux_001_src5_endofpacket -- .endofpacket
);
cmd_xbar_demux_002 : component Video_System_cmd_xbar_demux_002
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_002_src_ready, -- sink.ready
sink_channel => addr_router_002_src_channel, -- .channel
sink_data => addr_router_002_src_data, -- .data
sink_startofpacket => addr_router_002_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_002_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_002_src_valid, -- .valid
src0_ready => cmd_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_002_src0_valid, -- .valid
src0_data => cmd_xbar_demux_002_src0_data, -- .data
src0_channel => cmd_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_002_src0_endofpacket -- .endofpacket
);
cmd_xbar_demux_003 : component Video_System_cmd_xbar_demux_002
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_003_src_ready, -- sink.ready
sink_channel => addr_router_003_src_channel, -- .channel
sink_data => addr_router_003_src_data, -- .data
sink_startofpacket => addr_router_003_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_003_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_003_src_valid, -- .valid
src0_ready => cmd_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_003_src0_valid, -- .valid
src0_data => cmd_xbar_demux_003_src0_data, -- .data
src0_channel => cmd_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_003_src0_endofpacket -- .endofpacket
);
cmd_xbar_mux : component Video_System_cmd_xbar_mux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_src_ready, -- src.ready
src_valid => cmd_xbar_mux_src_valid, -- .valid
src_data => cmd_xbar_mux_src_data, -- .data
src_channel => cmd_xbar_mux_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src0_valid, -- .valid
sink0_channel => cmd_xbar_demux_src0_channel, -- .channel
sink0_data => cmd_xbar_demux_src0_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src0_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src0_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src0_endofpacket -- .endofpacket
);
cmd_xbar_mux_001 : component Video_System_cmd_xbar_mux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_001_src_ready, -- src.ready
src_valid => cmd_xbar_mux_001_src_valid, -- .valid
src_data => cmd_xbar_mux_001_src_data, -- .data
src_channel => cmd_xbar_mux_001_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src1_valid, -- .valid
sink0_channel => cmd_xbar_demux_src1_channel, -- .channel
sink0_data => cmd_xbar_demux_src1_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src1_endofpacket -- .endofpacket
);
cmd_xbar_mux_002 : component Video_System_cmd_xbar_mux_002
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_002_src_ready, -- src.ready
src_valid => cmd_xbar_mux_002_src_valid, -- .valid
src_data => cmd_xbar_mux_002_src_data, -- .data
src_channel => cmd_xbar_mux_002_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_src_ready, -- sink0.ready
sink0_valid => width_adapter_src_valid, -- .valid
sink0_channel => width_adapter_src_channel, -- .channel
sink0_data => width_adapter_src_data, -- .data
sink0_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_src_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_002_src0_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_002_src0_valid, -- .valid
sink1_channel => cmd_xbar_demux_002_src0_channel, -- .channel
sink1_data => cmd_xbar_demux_002_src0_data, -- .data
sink1_startofpacket => cmd_xbar_demux_002_src0_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_002_src0_endofpacket, -- .endofpacket
sink2_ready => cmd_xbar_demux_003_src0_ready, -- sink2.ready
sink2_valid => cmd_xbar_demux_003_src0_valid, -- .valid
sink2_channel => cmd_xbar_demux_003_src0_channel, -- .channel
sink2_data => cmd_xbar_demux_003_src0_data, -- .data
sink2_startofpacket => cmd_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink2_endofpacket => cmd_xbar_demux_003_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux : component Video_System_cmd_xbar_demux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_src_ready, -- sink.ready
sink_channel => id_router_src_channel, -- .channel
sink_data => id_router_src_data, -- .data
sink_startofpacket => id_router_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_src_valid, -- .valid
src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_src0_valid, -- .valid
src0_data => rsp_xbar_demux_src0_data, -- .data
src0_channel => rsp_xbar_demux_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_src1_valid, -- .valid
src1_data => rsp_xbar_demux_src1_data, -- .data
src1_channel => rsp_xbar_demux_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_001 : component Video_System_cmd_xbar_demux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_001_src_ready, -- sink.ready
sink_channel => id_router_001_src_channel, -- .channel
sink_data => id_router_001_src_data, -- .data
sink_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_001_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid
src0_data => rsp_xbar_demux_001_src0_data, -- .data
src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
src1_data => rsp_xbar_demux_001_src1_data, -- .data
src1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_001_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_002 : component Video_System_rsp_xbar_demux_002
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_002_src_ready, -- sink.ready
sink_channel => id_router_002_src_channel, -- .channel
sink_data => id_router_002_src_data, -- .data
sink_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_002_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_002_src_valid, -- .valid
src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
src0_data => rsp_xbar_demux_002_src0_data, -- .data
src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_002_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_002_src1_valid, -- .valid
src1_data => rsp_xbar_demux_002_src1_data, -- .data
src1_channel => rsp_xbar_demux_002_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_002_src1_endofpacket, -- .endofpacket
src2_ready => rsp_xbar_demux_002_src2_ready, -- src2.ready
src2_valid => rsp_xbar_demux_002_src2_valid, -- .valid
src2_data => rsp_xbar_demux_002_src2_data, -- .data
src2_channel => rsp_xbar_demux_002_src2_channel, -- .channel
src2_startofpacket => rsp_xbar_demux_002_src2_startofpacket, -- .startofpacket
src2_endofpacket => rsp_xbar_demux_002_src2_endofpacket -- .endofpacket
);
rsp_xbar_demux_003 : component Video_System_rsp_xbar_demux_003
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_003_src_ready, -- sink.ready
sink_channel => id_router_003_src_channel, -- .channel
sink_data => id_router_003_src_data, -- .data
sink_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_003_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_003_src_valid, -- .valid
src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid
src0_data => rsp_xbar_demux_003_src0_data, -- .data
src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_004 : component Video_System_rsp_xbar_demux_003
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_004_src_ready, -- sink.ready
sink_channel => id_router_004_src_channel, -- .channel
sink_data => id_router_004_src_data, -- .data
sink_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_004_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_004_src_valid, -- .valid
src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid
src0_data => rsp_xbar_demux_004_src0_data, -- .data
src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_005 : component Video_System_rsp_xbar_demux_003
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_005_src_ready, -- sink.ready
sink_channel => id_router_005_src_channel, -- .channel
sink_data => id_router_005_src_data, -- .data
sink_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_005_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid
src0_data => rsp_xbar_demux_005_src0_data, -- .data
src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux : component Video_System_rsp_xbar_mux
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_src_ready, -- src.ready
src_valid => rsp_xbar_mux_src_valid, -- .valid
src_data => rsp_xbar_mux_src_data, -- .data
src_channel => rsp_xbar_mux_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src0_valid, -- .valid
sink0_channel => rsp_xbar_demux_src0_channel, -- .channel
sink0_data => rsp_xbar_demux_src0_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src0_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src0_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux_001 : component Video_System_rsp_xbar_mux_001
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_001_src_ready, -- src.ready
src_valid => rsp_xbar_mux_001_src_valid, -- .valid
src_data => rsp_xbar_mux_001_src_data, -- .data
src_channel => rsp_xbar_mux_001_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src1_valid, -- .valid
sink0_channel => rsp_xbar_demux_src1_channel, -- .channel
sink0_data => rsp_xbar_demux_src1_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src1_endofpacket, -- .endofpacket
sink2_ready => width_adapter_001_src_ready, -- sink2.ready
sink2_valid => width_adapter_001_src_valid, -- .valid
sink2_channel => width_adapter_001_src_channel, -- .channel
sink2_data => width_adapter_001_src_data, -- .data
sink2_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
sink2_endofpacket => width_adapter_001_src_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src0_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src0_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src0_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src0_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
sink4_ready => rsp_xbar_demux_004_src0_ready, -- sink4.ready
sink4_valid => rsp_xbar_demux_004_src0_valid, -- .valid
sink4_channel => rsp_xbar_demux_004_src0_channel, -- .channel
sink4_data => rsp_xbar_demux_004_src0_data, -- .data
sink4_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
sink4_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket
sink5_ready => rsp_xbar_demux_005_src0_ready, -- sink5.ready
sink5_valid => rsp_xbar_demux_005_src0_valid, -- .valid
sink5_channel => rsp_xbar_demux_005_src0_channel, -- .channel
sink5_data => rsp_xbar_demux_005_src0_data, -- .data
sink5_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
sink5_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
width_adapter : component Video_System_width_adapter
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_001_src2_valid, -- sink.valid
in_channel => cmd_xbar_demux_001_src2_channel, -- .channel
in_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_001_src2_ready, -- .ready
in_data => cmd_xbar_demux_001_src2_data, -- .data
out_endofpacket => width_adapter_src_endofpacket, -- src.endofpacket
out_data => width_adapter_src_data, -- .data
out_channel => width_adapter_src_channel, -- .channel
out_valid => width_adapter_src_valid, -- .valid
out_ready => width_adapter_src_ready, -- .ready
out_startofpacket => width_adapter_src_startofpacket -- .startofpacket
);
width_adapter_001 : component Video_System_width_adapter_001
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => rsp_xbar_demux_002_src0_valid, -- sink.valid
in_channel => rsp_xbar_demux_002_src0_channel, -- .channel
in_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
in_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
in_ready => rsp_xbar_demux_002_src0_ready, -- .ready
in_data => rsp_xbar_demux_002_src0_data, -- .data
out_endofpacket => width_adapter_001_src_endofpacket, -- src.endofpacket
out_data => width_adapter_001_src_data, -- .data
out_channel => width_adapter_001_src_channel, -- .channel
out_valid => width_adapter_001_src_valid, -- .valid
out_ready => width_adapter_001_src_ready, -- .ready
out_startofpacket => width_adapter_001_src_startofpacket -- .startofpacket
);
irq_mapper : component Video_System_irq_mapper
port map (
clk => clock_signals_sys_clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sender_irq => cpu_d_irq_irq -- sender.irq
);
reset_n_ports_inv <= not reset_n;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of Video_System
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc899.vhd | 4 | 2776 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc899.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s03b00x00p04n01i00899pkg_1 is
type T is (one,two,three,four);
subtype SS is INTEGER;
function F return REAL;
end c10s03b00x00p04n01i00899pkg_1;
package body c10s03b00x00p04n01i00899pkg_1 is
function F return REAL is
begin
return 0.0;
end F;
end c10s03b00x00p04n01i00899pkg_1;
package c10s03b00x00p04n01i00899pkg_2 is
type T is (one,two,three,four);
subtype SS is INTEGER;
function F return REAL;
end c10s03b00x00p04n01i00899pkg_2;
package body c10s03b00x00p04n01i00899pkg_2 is
function F return REAL is
begin
return 0.0;
end F;
end c10s03b00x00p04n01i00899pkg_2;
use work.c10s03b00x00p04n01i00899pkg_1.all,work.c10s03b00x00p04n01i00899_pkg_2.all;
ENTITY c10s03b00x00p04n01i00899ent IS
port (P:BOOLEAN) ;
subtype S2 is SS; -- Failure_here
-- SEMANTIC ERROR: ambiguous reference to subtype SS
type R is range F to F; -- Failure_here
-- SEMANTIC ERROR: ambiguous reference to function F
END c10s03b00x00p04n01i00899ent;
ARCHITECTURE c10s03b00x00p04n01i00899arch OF c10s03b00x00p04n01i00899ent IS
BEGIN
TESTING: PROCESS
variable V1 : T; -- Failure_here
-- SEMANTIC ERROR: ambiguous reference to type T
variable V2 : SS; -- Failure_here
-- SEMANTIC ERROR: ambiguous reference to subtype SS
BEGIN
V1 := one; -- Failure_here
-- SEMANTIC ERROR: ambiguous reference to literal "one"
assert FALSE
report "***FAILED TEST: c10s03b00x00p04n01i00899 - Ambiguous references not permitted."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p04n01i00899arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd | 4 | 1210 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
use work.counter_types.all;
architecture test of tb_counter is
signal clk, clr : bit := '0';
signal q0, q1 : digit;
begin
dut : entity work.counter(registered)
port map ( clk => clk, clr => clr,
q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 20 ns;
clr_gen : clr <= '1' after 95 ns,
'0' after 135 ns;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/add_170.vhd | 2 | 796 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_170 is
port (
result : out std_logic_vector(8 downto 0);
in_a : in std_logic_vector(8 downto 0);
in_b : in std_logic_vector(8 downto 0)
);
end add_170;
architecture augh of add_170 is
signal carry_inA : std_logic_vector(10 downto 0);
signal carry_inB : std_logic_vector(10 downto 0);
signal carry_res : std_logic_vector(10 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(9 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc116.vhd | 4 | 2021 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc116.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n10i00116ent IS
END c04s03b02x00p29n10i00116ent;
ARCHITECTURE c04s03b02x00p29n10i00116arch OF c04s03b02x00p29n10i00116ent IS
PROCEDURE p1 ( prm_inout : INOUT INTEGER ) IS
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF prm_inout : VARIABLE IS 300;
BEGIN
ASSERT prm_inout'attr1 = 300 REPORT "ERROR: Bad value for prm_inout'attr1" SEVERITY FAILURE;
assert NOT( prm_inout'attr1 = 300 )
report "***PASSED TEST: c04s03b02x00p29n10i00116"
severity NOTE;
assert ( prm_inout'attr1 = 300 )
report "***FAILED TEST: c04s03b02x00p29n10i00116 - Interface object attribute reading in a subprogram test failed."
severity ERROR;
END;
BEGIN
TESTING: PROCESS
VARIABLE tmp : INTEGER;
BEGIN
--
p1 ( tmp );
--
wait;
END PROCESS TESTING;
END c04s03b02x00p29n10i00116arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3116.vhd | 4 | 3217 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3116.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p03n01i03116ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p03n01i03116ent_a;
ARCHITECTURE c05s02b01x01p03n01i03116arch_a OF c05s02b01x01p03n01i03116ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p03n01i03116arch_a;
ARCHITECTURE c05s02b01x01p03n01i03116arch_b OF c05s02b01x01p03n01i03116ent_a IS
BEGIN
p2 <= p1 after 15 ns;
END c05s02b01x01p03n01i03116arch_b;
configuration c05s02b01x01p03n01i03116cfg_a of c05s02b01x01p03n01i03116ent_a is
for c05s02b01x01p03n01i03116arch_a
end for;
end c05s02b01x01p03n01i03116cfg_a;
configuration c05s02b01x01p03n01i03116cfg_b of c05s02b01x01p03n01i03116ent_a is
for c05s02b01x01p03n01i03116arch_b
end for;
end c05s02b01x01p03n01i03116cfg_b;
--
ENTITY c05s02b01x01p03n01i03116ent IS
END c05s02b01x01p03n01i03116ent;
ARCHITECTURE c05s02b01x01p03n01i03116arch OF c05s02b01x01p03n01i03116ent IS
component ic_socket
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
for all : ic_socket use entity work.c05s02b01x01p03n01i03116ent_a;
BEGIN
u1 : ic_socket
generic map ( true )
port map (s1, s2);
u2 : ic_socket
generic map ( true )
port map (s2, s3);
u3 : ic_socket
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 60 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p03n01i03116"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p03n01i03116 - Absense of an explicit architecture test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p03n01i03116arch;
configuration c05s02b01x01p03n01i03116cfg of c05s02b01x01p03n01i03116ent is
for c05s02b01x01p03n01i03116arch
end for;
end c05s02b01x01p03n01i03116cfg;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1144/issue.vhdl | 1 | 340 | library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (i_data : in std_logic_vector(8 downto 0);
o_data : out std_logic_vector(3 downto 0);
clock : in std_logic);
end issue;
architecture rtl of issue is
alias i_hi is i_data(3 downto 0);
begin
o_data <= i_hi;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_13.vhd | 4 | 1108 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_13.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package tb_05_13 is
subtype word is integer;
end package tb_05_13;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2271.vhd | 4 | 1778 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2271.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02271ent IS
END c07s02b06x00p14n01i02271ent;
ARCHITECTURE c07s02b06x00p14n01i02271arch OF c07s02b06x00p14n01i02271ent IS
BEGIN
TESTING: PROCESS
variable k : time := 2 * 10 ns;
BEGIN
assert NOT(k = 20 ns)
report "***PASSED TEST: c07s02b06x00p14n01i02271"
severity NOTE;
assert (k = 20 ns)
report "***FAILED TEST: c07s02b06x00p14n01i02271 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02271arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/oper01/tb_snum03.vhdl | 1 | 297 | entity tb_snum03 is
end tb_snum03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_snum03 is
signal r : boolean;
begin
cmp03_1: entity work.snum03
port map (r);
process
begin
wait for 1 ns;
assert r severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_205.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_205 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_205;
architecture augh of add_205 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc910.vhd | 4 | 1944 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc910.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00910ent IS
END c10s03b00x00p05n01i00910ent;
ARCHITECTURE c10s03b00x00p05n01i00910arch OF c10s03b00x00p05n01i00910ent IS
BEGIN
B2:block
type A is (A1, A2, A3);
signal S : A;
begin
S <= A1;
end block B2;
B3:block
signal S1 : A; -- Failure_here
-- error: entity not within the region it is immediately declared
begin
S1 <= A1; -- Failure_here
-- error: entity nor within the region it is immediately declated
end block B3;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: /c10s03b00x00p05n01i00910 - Entity is not within the region it is immediately declared in."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00910arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2738.vhd | 4 | 1801 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2738.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p03n02i02738ent IS
END c13s06b00x00p03n02i02738ent;
ARCHITECTURE c13s06b00x00p03n02i02738arch OF c13s06b00x00p03n02i02738ent IS
constant c : string := ('"',' ');
constant s : string := """ ";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c=s )
report "***PASSED TEST: c13s06b00x00p03n02i02738"
severity NOTE;
assert ( c=s )
report "***FAILED TEST: c13s06b00x00p03n02i02738 - A string literal that includes two adjacent quotation characters is interpreted as one quotation character."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p03n02i02738arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue872/alu.vhdl | 1 | 873 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port (
clk : in std_logic;
rst : in std_logic;
opcode : in std_logic_vector(15 downto 0);
a : in std_logic;
b : in std_logic;
y : out std_logic
);
end alu;
architecture mux of alu is
signal ci : std_logic;
signal co : std_logic;
signal mux1, mux2: std_logic_vector(7 downto 0);
begin
process(a, b, ci, mux1, mux2)
variable sel : unsigned(2 downto 0);
begin
sel := a & b & ci;
y <= mux1(to_integer(sel));
co <= mux2(to_integer(sel));
end process;
process(clk, rst)
begin
if(rst = '0') then
ci <= '0';
mux1 <= (others => '0');
mux2 <= (others => '0');
elsif(rising_edge(clk)) then
ci <= co;
mux1 <= opcode(15 downto 8);
mux2 <= opcode(7 downto 0);
end if;
end process;
end mux;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1485.vhd | 4 | 1925 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1485.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n03i01485ent IS
END c08s08b00x00p04n03i01485ent;
ARCHITECTURE c08s08b00x00p04n03i01485arch OF c08s08b00x00p04n03i01485ent IS
BEGIN
TESTING: PROCESS
variable m : severity_level := NOTE;
variable k : integer := 0;
BEGIN
case m is
when severity_level'low | severity_level'high => k := 5;
when others => NULL;
end case;
assert NOT( k = 5 )
report "***PASSED TEST: c08s08b00x00p04n03i01485"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s08b00x00p04n03i01485 - Each choice in a case statement alternative must be of the same type as the expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n03i01485arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3170.vhd | 4 | 1819 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3170.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03170ent IS
END c14s01b00x00p17n01i03170ent;
ARCHITECTURE c14s01b00x00p17n01i03170arch OF c14s01b00x00p17n01i03170ent IS
constant L : REAL := -10.0;
constant R : REAL := 10.0;
type RT1 is range L to R;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( RT1'right = RT1(R) )
report "***PASSED TEST: c14s01b00x00p17n01i03170"
severity NOTE;
assert ( RT1'right = RT1(R) )
report "***FAILED TEST: c14s01b00x00p17n01i03170 - Predefined attribute RIGHT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03170arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug035/my_config_ML505.vhdl | 4 | 1763 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML505"; -- ML505 - Xilinx Virtex 5 reference design board: XC5VLX50T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug019/PoC/src/common/fileio.vhdl | 4 | 3036 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: File I/O-related Functions.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- Exploring the options for providing a more convenient API than std.textio.
-- Not yet recommended for adoption as it depends on the VHDL generation and
-- still is under discussion.
--
-- Open problems:
-- - verify that std.textio.write(text, string) is, indeed, specified and
-- that it does *not* print a trailing \newline
-- -> would help to eliminate line buffering in shared variables
-- - move C_LINEBREAK to my_config to keep platform dependency out?
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library PoC;
use PoC.my_project.all;
package FileIO is
-- Constant declarations
constant C_LINEBREAK : STRING;
-- =============================================================================
procedure stdout_write (str : STRING);
procedure stdout_writeline(str : STRING := "");
end package;
package body FileIO is
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
-- =============================================================================
constant C_LINEBREAK : STRING := ite(str_equal(MY_OPERATING_SYSTEM, "WINDOWS"), (CR & LF), (1 => LF));
-- =============================================================================
shared variable stdout_line : line;
shared variable stderr_line : line;
procedure stdout_write(str : STRING) is
begin
write(stdout_line, str);
end procedure;
procedure stdout_writeline(str : STRING := "") is
begin
write(stdout_line, str);
writeline(output, stdout_line);
end procedure;
end package body;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1091.vhd | 4 | 2346 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1091.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s05b00x00p02n01i01091pkg is
type FIVE is range 1 to 5;
type ABASE is array (FIVE range <>) of BOOLEAN;
subtype A1 is ABASE(FIVE);
attribute AT1 : A1;
function fat1(i:integer) return a1;
end c06s05b00x00p02n01i01091pkg;
package body c06s05b00x00p02n01i01091pkg is
function fat1(i:integer) return a1 is
variable va1 : a1;
begin
return Va1;
end fat1;
end c06s05b00x00p02n01i01091pkg;
use work.c06s05b00x00p02n01i01091pkg.all;
ENTITY c06s05b00x00p02n01i01091ent IS
port (PT: BOOLEAN) ;
attribute AT1 of PT : signal is fat1(8);
END c06s05b00x00p02n01i01091ent;
ARCHITECTURE c06s05b00x00p02n01i01091arch OF c06s05b00x00p02n01i01091ent IS
BEGIN
TESTING: PROCESS
variable V1 : A1;
BEGIN
V1(2 to 4) := PT'AT1(2 to 4);
assert NOT(V1(2 to 4)=(false,false,false))
report "***PASSED TEST: c06s05b00x00p02n01i01091"
severity NOTE;
assert (V1(2 to 4)=(false,false,false))
report "***FAILED TEST: c06s05b00x00p02n01i01091 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01091arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue167/pkg2.vhdl | 2 | 442 | package p is
component c is
generic (
-- None of these work in GHDL 1a1d378dcafeca5a18dfa8862ebe412efa1e9718
-- together with the ports defined below.
-- g : bit_vector
-- g : bit_vector := x"0"
-- g : bit_vector(3 downto 0) := x"0"
g : bit_vector(3 downto 0)
);
port (
-- fails if generic 'g' is referenced
x : bit_vector(g'length-1 downto 0)
);
end component;
end package;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket39/test.vhd | 3 | 839 | entity test is
end entity test;
library ieee;
use ieee.std_logic_1164.all;
architecture test of test is
type state_t is record
a : real;
end record state_t;
procedure p1 (
variable state : inout state_t;
a : in std_ulogic_vector(1 downto 0)) is
begin
report "test " & std_ulogic'image(a(1)) & std_ulogic'image(a(0)) severity note;
end procedure p1;
procedure p2 (
variable state : inout state_t;
n : in natural) is
variable b : std_ulogic;
begin
b := '0';
for i in 0 to n loop
p1(state => state, a(0) => b, a(1) => 'X');
b := not b;
state.a := state.a + 1.0;
end loop;
end procedure p2;
begin
p_p: process is
variable state : state_t;
begin
state.a := 0.0;
p2(state, 2);
p2(state, 2);
wait;
end process p_p;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug053/tb1.vhdl | 2 | 262 | entity tb1 is
package pkg1 is
constant c : natural := 5;
function f return natural;
end pkg1;
end tb1;
architecture behav of tb1 is
begin
assert pkg1.c = 5 severity failure;
assert pkg1.c /= 5 report "value is correct" severity note;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1154.vhd | 4 | 2121 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1154.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s06b00x00p02n01i01154pkg is
type A1 is array (1 to 2) of BOOLEAN;
type A2 is array (1 to 2) of A1;
end c06s06b00x00p02n01i01154pkg;
use work.c06s06b00x00p02n01i01154pkg.all;
ENTITY c06s06b00x00p02n01i01154ent IS
port (PT: A2) ;
attribute AT1 : BOOLEAN;
attribute AT1 of PT : signal is TRUE;
END c06s06b00x00p02n01i01154ent;
ARCHITECTURE c06s06b00x00p02n01i01154arch OF c06s06b00x00p02n01i01154ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 5;
BEGIN
if PT'AT1 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01154"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01154 - The attribute name consists of a prefix, an apostrophe('), an attribute designator, and (optionally) a static expression enclosed with parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01154arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd | 4 | 1427 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity and_or_inv is
port ( a1, a2, b1, b2 : in bit := '1';
y : out bit );
end entity and_or_inv;
-- end not in book
architecture primitive of and_or_inv is
signal and_a, and_b : bit;
signal or_a_b : bit;
begin
and_gate_a : process (a1, a2) is
begin
and_a <= a1 and a2;
end process and_gate_a;
and_gate_b : process (b1, b2) is
begin
and_b <= b1 and b2;
end process and_gate_b;
or_gate : process (and_a, and_b) is
begin
or_a_b <= and_a or and_b;
end process or_gate;
inv : process (or_a_b) is
begin
y <= not or_a_b;
end process inv;
end architecture primitive;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2517.vhd | 4 | 1703 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2517.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p03n03i02517ent IS
END c07s03b05x00p03n03i02517ent;
ARCHITECTURE c07s03b05x00p03n03i02517arch OF c07s03b05x00p03n03i02517ent IS
BEGIN
TESTING: PROCESS
subtype Grapes is STRING;
constant Green : Grapes := Grapes ("CLSI"); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b05x00p03n03i02517 - Operand cannot be the literal null, an alloator, an aggregate, or a string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p03n03i02517arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_05.vhd | 4 | 2951 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_18_05_a is
end entity fg_18_05_a;
architecture writer of fg_18_05_a is
begin
process is
type integer_file is file of integer;
file data_file : integer_file open write_mode is "coeff-data";
begin
write(data_file, 0);
write(data_file, 1);
write(data_file, 2);
write(data_file, 3);
write(data_file, 4);
write(data_file, 5);
write(data_file, 6);
write(data_file, 7);
write(data_file, 8);
write(data_file, 9);
write(data_file, 10);
write(data_file, 11);
write(data_file, 12);
write(data_file, 13);
write(data_file, 14);
write(data_file, 15);
write(data_file, 16);
write(data_file, 17);
write(data_file, 18);
wait;
end process;
end architecture writer;
entity fg_18_05 is
end entity fg_18_05;
architecture test of fg_18_05 is
begin
process is
-- code from book (in text)
type integer_vector is array (integer range <>) of integer;
-- end code from book
-- code from book (Figure 18-5)
impure function read_array ( file_name : string; array_length : natural )
return integer_vector is
type integer_file is file of integer;
file data_file : integer_file open read_mode is file_name;
variable result : integer_vector(1 to array_length) := (others => 0);
variable index : integer := 1;
begin
while not endfile(data_file) and index <= array_length loop
read(data_file, result(index));
index := index + 1;
end loop;
return result;
end function read_array;
-- end code from book
-- code from book (in text)
constant coeffs : integer_vector := read_array("coeff-data", 16);
-- end code from book
begin
wait;
end process;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/iassoc01/tb_iassoc04.vhdl | 1 | 483 | entity tb_iassoc04 is
end tb_iassoc04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc04 is
signal a, b : bit_vector (3 downto 0);
signal res : bit;
begin
dut: entity work.iassoc04
port map (a, b, res);
process
begin
a <= "0001";
b <= "0000";
wait for 1 ns;
assert res = '1' severity failure;
a <= "0000";
b <= "0000";
wait for 1 ns;
assert res = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/mul_192.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_192 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(10 downto 0)
);
end mul_192;
architecture augh of mul_192 is
signal tmp_res : signed(40 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(29 downto 0));
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bb.vhd | 4 | 3254 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bb.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_behavioral of mac_test is
signal clk, clr, ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
s_real, s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag, s_real, s_imag,
ovf );
s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
end architecture bench_behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue810/my_time_pkg.vhdl | 1 | 257 | package my_time_pkg is
type my_time is range -integer'low to integer'high units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
end package my_time_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd | 4 | 1257 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity counter is
port ( clk : in bit; count : out natural );
end entity counter;
--------------------------------------------------
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
wait until clk = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
end process incrementer;
end architecture behavior;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/cmp_132.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_132 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_132;
architecture augh of cmp_132 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1133/foo.vhdl | 1 | 554 | library ieee;
use ieee.std_logic_1164.all;
entity foo is
port (
input : in std_logic_vector(7 downto 0);
output_ok : out std_logic_vector(7 downto 0);
output_error : out std_logic_vector(7 downto 0)
);
end foo;
architecture foo of foo is
signal null_vector : std_logic_vector(-1 downto 0) := (others => '0');
begin
-- This works fine
null_vector <= input(null_vector'range);
output_ok <= null_vector & (7 downto 0 => '0');
-- This doesn't
output_error <= input(-1 downto 0) & (7 downto 0 => '0');
end foo;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue301/packages/pkg_helper.vhd | 7 | 1274 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Helper package with useful functions
--! @author Markus Fehrenz
--! @date 2011/12/02
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_helper is
--!
--! Return the log_2 of an natural value, i.e. the number of bits required
--! to represent this unsigned value.
--!
function no_bits_natural(value_in : natural) return natural;
--! Return maximum of two input values
function max(value_in_a, value_in_b : natural) return natural;
end pkg_helper;
package body pkg_helper is
function no_bits_natural(value_in: natural) return natural is
variable v_n_bit : unsigned(31 downto 0);
begin
if value_in = 0 then
return 0;
end if;
v_n_bit := to_unsigned(value_in, 32);
for i in 31 downto 0 loop
if v_n_bit(i) = '1' then
return i + 1;
end if;
end loop;
return 1;
end no_bits_natural;
function max(value_in_a, value_in_b : natural) return natural is
begin
if value_in_a > value_in_b then
return value_in_a;
else
return value_in_b;
end if;
end function;
end pkg_helper;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/simple01/tb_simple01.vhdl | 1 | 681 | entity tb_simple01 is
end tb_simple01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_simple01 is
signal a : std_logic;
signal b : std_logic;
signal c : std_logic;
signal z : std_logic;
begin
dut: entity work.simple01
port map (a, b, c, z);
process
constant av : std_logic_vector := b"1101";
constant bv : std_logic_vector := b"0111";
constant cv : std_logic_vector := b"0011";
constant zv : std_logic_vector := b"0111";
begin
for i in av'range loop
a <= av (i);
b <= bv (i);
c <= cv (i);
wait for 1 ns;
assert z = zv(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc877.vhd | 4 | 1800 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc877.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b02x00p02n01i00877ent IS
END c01s03b02x00p02n01i00877ent;
ARCHITECTURE c01s03b02x00p02n01i00877arch OF c01s03b02x00p02n01i00877ent IS
BEGIN
BB : block
component LOCAL
end component;
begin
CIS : LOCAL;
assert FALSE
report "***PASSED TEST: c01s03b02x00p02n01i00877"
severity NOTE;
end block BB;
END c01s03b02x00p02n01i00877arch;
configuration c01s03b02x00p02n01i00877cfg of c01s03b02x00p02n01i00877ent is
for c01s03b02x00p02n01i00877arch
for BB
for CIS : LOCAL -- Success_here
end for;
end for;
end for ;
end c01s03b02x00p02n01i00877cfg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2193.vhd | 4 | 1833 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2193.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02193ent IS
END c07s02b00x00p01n02i02193ent;
ARCHITECTURE c07s02b00x00p01n02i02193arch OF c07s02b00x00p01n02i02193ent IS
BEGIN
TESTING: PROCESS
type A_ARRAY is array (1 to 2) of CHARACTER;
variable I : INTEGER;
variable R : REAL;
variable B : BOOLEAN;
variable A : A_ARRAY;
BEGIN
R := R * + R; -- Failure_here
-- SYNTAX ERROR: signed operator cannot follow multiplying operator.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02193 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02193arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_180.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_180 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_180;
architecture augh of add_180 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_255.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_255 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_255;
architecture augh of add_255 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1056.vhd | 4 | 1896 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1056.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01056ent IS
END c06s04b00x00p03n02i01056ent;
ARCHITECTURE c06s04b00x00p03n02i01056arch OF c06s04b00x00p03n02i01056ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (EN1, EN2, EN3);
type A22 is array (ENUM1, ENUM1) of BOOLEAN;
variable V1 : BOOLEAN;
variable V22: A22 ;
BEGIN
V1 := V22(EN2); -- ONE LESS
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01056 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01056arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qt.vhd | 4 | 1318 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_qt.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
use qsim.qsim_types.all;
package queue_types is
type waiting_token_type is record
token : token_type;
time_when_enqueued : time;
end record waiting_token_type;
end package queue_types;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1625.vhd | 4 | 1817 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1625.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p03n01i01625pkg is
end c08s12b00x00p03n01i01625pkg;
package body c08s12b00x00p03n01i01625pkg is
return true; -- illegal in package
body
end c08s12b00x00p03n01i01625pkg;
ENTITY c08s12b00x00p03n01i01625ent IS
END c08s12b00x00p03n01i01625ent;
ARCHITECTURE c08s12b00x00p03n01i01625arch OF c08s12b00x00p03n01i01625ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01625 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01625arch;
| gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.