repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc680.vhd | 4 | 3130 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc680.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:00 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:32 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00680ent IS
END c03s04b01x00p23n01i00680ent;
ARCHITECTURE c03s04b01x00p23n01i00680arch OF c03s04b01x00p23n01i00680ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of INTEGER;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.08";
-- Declare a variable into which we will read.
constant CON : INTEGER := 1;
variable VAR : INTEGER;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00680"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00680 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00680arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2346.vhd | 4 | 1713 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2346.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02346ent IS
END c07s02b07x00p02n02i02346ent;
ARCHITECTURE c07s02b07x00p02n02i02346arch OF c07s02b07x00p02n02i02346ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
variable SWITCHV : SWITCH_LEVEL := '0';
variable INTV : INTEGER;
BEGIN
INTV := 2 ** SWITCHV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02346 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02346arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-right-attribute.vhdl | 4 | 300 | entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'right = 3 report "TEST FAILED right = 3" severity failure;
report "TEST PASSED right = 3";
wait;
end process p;
end only;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd | 4 | 1655 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity mixer_wa is
port ( terminal inputs : electrical_vector(1 to 8);
terminal output : electrical );
end entity mixer_wa;
----------------------------------------------------------------
architecture weighted of mixer_wa is
quantity v_in across inputs;
quantity v_out across i_out through output;
quantity v1, v2, v3, v4, v5, v6, v7, v8 : real;
constant gains : real_vector(1 to 8)
:= ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 );
begin
v1 == v_in(1) * gains(1);
v2 == v_in(2) * gains(2);
v3 == v_in(3) * gains(3);
v4 == v_in(4) * gains(4);
v5 == v_in(5) * gains(5);
v6 == v_in(6) * gains(6);
v7 == v_in(7) * gains(7);
v8 == v_in(8) * gains(8);
v_out == v1 + v2 + v3 + v4 + v5 + v6 + v7 + v8;
end architecture weighted;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd | 4 | 2765 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- Pendulum example. Look at velocity quantity, phi_dot, to see effects of
-- discontinuity. Run simulation for about 20 sec.
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
library ieee; use ieee.math_real.all;
entity pendulum_wa is
end entity pendulum_wa;
-- ======================================================================================
-- constrained architecture
-- ======================================================================================
architecture constrained of pendulum_wa is
constant mass : real := 10.0;
constant arm_length : real := 5.0;
constant pin_angle : real := 0.25*math_pi;
constant pin_distance : real := 2.5;
constant damping : real := 1.0;
constant gravity : real := 9.81;
constant short_length : real := arm_length-pin_distance;
quantity phi : real := -0.5*math_pi;
signal current_length : real := arm_length;
quantity acceleration, velocity : real;
quantity phi_dot : real;
signal pin_thresh : boolean;
signal phi_dot_at_pin_thresh : real := 0.0;
signal transition : boolean := false;
begin
if domain = quiescent_domain use
phi == -0.5*math_pi;
phi'dot == 0.0;
elsif transition and pin_thresh use
phi == pin_angle;
phi'dot == phi_dot_at_pin_thresh*arm_length/short_length;
elsif transition and not pin_thresh use
phi == pin_angle;
phi'dot == phi_dot_at_pin_thresh*short_length/arm_length;
else
mass*acceleration == -mass*gravity*sin(phi)-damping*velocity;
velocity == current_length*phi'dot;
end use;
acceleration == velocity'dot;
phi_dot == phi'dot;
pin_thresh <= phi'above(pin_angle);
process
begin
wait on pin_thresh;
phi_dot_at_pin_thresh <= phi_dot;
if pin_thresh = true then
current_length <= short_length;
transition <= true;
else
current_length <= arm_length;
transition <= true;
end if;
wait for 1 us;
transition <= false;
end process;
break on pin_thresh;
break on transition;
end architecture constrained;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1290.vhd | 4 | 1696 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1290.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01290ent IS
port (X : in BIT; COUT : out BIT);
END c08s04b00x00p04n01i01290ent;
ARCHITECTURE c08s04b00x00p04n01i01290arch OF c08s04b00x00p04n01i01290ent IS
signal S1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
X(2) <= S1;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01290 - A port whose mode is "IN" can not be on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01290arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc883.vhd | 4 | 2328 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc883.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s01b00x00p08n01i00883ent IS
END c10s01b00x00p08n01i00883ent;
ARCHITECTURE c10s01b00x00p08n01i00883arch OF c10s01b00x00p08n01i00883ent IS
signal S1 : INTEGER;
signal S2 : INTEGER;
signal GS1 : INTEGER;
signal GS2 : INTEGER;
signal PS1 : INTEGER;
signal PS2 : INTEGER;
BEGIN
-- initialization block and process
ALIST1SUB:
block
generic (
GS1: INTEGER := 3;
GS2: INTEGER := 9
);
generic map ( 3, 9 );
port (
PS1: out INTEGER;
PS2: out INTEGER
);
port map ( S1, S2 );
begin
process
begin
PS1 <= GS1 + 1;
PS2 <= GS2 + 2;
wait;
end process; -- forever, initialization complete
end block ALIST1SUB;
-- verification process
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT( S1=4 and S2=11 )
report "***PASSED TEST: c10s01b00x00p08n01i00883"
severity NOTE;
assert ( S1=4 and S2=11 )
report "***FAILED TEST: c10s01b00x00p08n01i00883 - A single declaration region is formed by the text of a block statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p08n01i00883arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc378.vhd | 4 | 1962 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc378.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n03i00378ent IS
END c03s02b01x01p03n03i00378ent;
ARCHITECTURE c03s02b01x01p03n03i00378arch OF c03s02b01x01p03n03i00378ent IS
type M1 is array (positive range <>) of integer;
subtype M2 is M1 (2 to 200); -- No_failure_here
BEGIN
TESTING: PROCESS
variable k : M2;
BEGIN
k(2) := 2;
k(200) := 200;
assert NOT ( k(2) = 2 and
k(200) = 200)
report "***PASSED TEST: c03s02b01x01p03n03i00378"
severity NOTE;
assert ( k(2) = 2 and
k(200) = 200)
report "***FAILED TEST: c03s02b01x01p03n03i00378 - The index constraint must provide a discrete range for each index of the array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n03i00378arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2347.vhd | 4 | 1771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2347.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02347ent IS
END c07s02b07x00p02n02i02347ent;
ARCHITECTURE c07s02b07x00p02n02i02347arch OF c07s02b07x00p02n02i02347ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
variable INTV : integer;
BEGIN
INTV := 2 ** LOGICV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02347 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02347arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_04.vhd | 4 | 2786 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_ch_09_04.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package arithmetic_ops is
-- code from book
procedure increment ( bv : inout bit_vector; by : in integer := 1 );
procedure increment ( int : inout integer; by : in integer := 1 );
-- end code from book
end package arithmetic_ops;
package body arithmetic_ops is
procedure increment ( bv : inout bit_vector; by : in integer := 1 ) is
begin
end procedure increment;
procedure increment ( int : inout integer; by : in integer := 1 ) is
begin
end procedure increment;
end package body arithmetic_ops;
entity ch_09_04 is
end entity ch_09_04;
library stimulus;
use stimulus.stimulus_generators.all;
architecture test of ch_09_04 is
-- code from book
-- MTI bug mt017
-- alias bv_increment is work.arithmetic_ops.increment [ bit_vector, integer ];
alias int_increment is work.arithmetic_ops.increment [ integer, integer ];
-- workaround to avoid MTI bug mt018
-- alias "*" is "and" [ bit, bit return bit ];
alias "*" is std.standard."and" [ bit, bit return bit ];
-- alias "+" is "or" [ bit, bit return bit ];
alias "+" is std.standard."or" [ bit, bit return bit ];
-- alias "-" is "not" [ bit return bit ];
alias "-" is std.standard."not" [ bit return bit ];
-- end workaround
alias high is std.standard.'1' [ return bit ];
-- end code from book
signal a, b, c, s : bit := '0';
signal test_vector : bit_vector(1 to 3);
signal test_high : bit := high;
begin
-- code from book
-- workaround to avoid MTI bug mt018
-- s <= a * b + (-a) * c;
s <= (a and b) or ((not a) and c);
-- end workaround
-- end code from book
stimulus : all_possible_values ( bv => test_vector,
delay_between_values => 10 ns );
(a, b, c) <= test_vector;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1615.vhd | 4 | 1682 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1615.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p02n01i01615ent IS
END c08s12b00x00p02n01i01615ent;
ARCHITECTURE c08s12b00x00p02n01i01615arch OF c08s12b00x00p02n01i01615ent IS
function ts (x1:bit) return integer is
begin
return(1)
end ts;
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
k := ts('1');
assert FALSE
report "***FAILED TEST: c08s12b00x00p02n01i01615 - Missing semicolon in the loop statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p02n01i01615arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug15702/example.vhd | 3 | 1573 | library ieee;
use ieee.std_logic_1164.all;
-- COMPONENT
entity a is
-- N_BITS_DATA is nowhere initialized. This problem should be catched during
-- elaboration but it isn't !
-- During simulation I found that the value of N_BITS_DATA is -2147483648 and
-- that the value of N_BITS_DATA-1 is 2147483647 !!!!
generic (N_BITS_DATA : integer);
end entity;
architecture arch_a of a is
--~ -- Here data_s will have 4_194_305 elements and this will make ghdl
--~ -- take about 650 MB of memory. According to that, each element take about 150 B
--~ signal data_s : std_logic_vector((N_BITS_DATA-1)/512 downto 0);
-- This line make ghdl eat all the free memory because it is trying to make a
-- vector of 2**31 elements !!!! And there isn't enough memory because we need
-- about 2**31 * 150 B = ~ 300 GB !!!!
signal data_s : std_logic_vector(N_BITS_DATA-1 downto 0);
--~ -- Strangely this line doesn't make the simulation failed because N_BITS_DATA
--~ -- is negativ, but it doesn't increase the use of memory either.
--~ signal data_s : std_logic_vector(N_BITS_DATA downto 0);
begin
process begin
-- N_BITS_DATA = -2147483648 = -2**31
report integer'image(N_BITS_DATA);
--
-- N_BITS_DATA-1 = 2147483647 = 2**31 - 1
report integer'image(N_BITS_DATA-1);
--
-- (N_BITS_DATA-1)/512 = 4_194_304 = 2**22
report integer'image((N_BITS_DATA-1)/512);
--
end process;
end;
--
-- TESTBENCH
entity tb is end entity;
architecture arch_tb of tb is
begin
X1: entity work.a;
end;
--
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2860.vhd | 4 | 1740 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2860.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p04n02i02860ent IS
END c13s10b00x00p04n02i02860ent;
ARCHITECTURE c13s10b00x00p04n02i02860arch OF c13s10b00x00p04n02i02860ent IS
constant a : string := %%%%;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a'length=1 and a="%" )
report "***PASSED TEST: c13s10b00x00p04n02i02860"
severity NOTE;
assert ( a'length=1 and a="%" )
report "***FAILED TEST: c13s10b00x00p04n02i02860 - Double percent will be treated as single character."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p04n02i02860arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_06.vhd | 4 | 4392 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book (in text)
entity computer_system is
generic ( instrumented : boolean := false );
port ( -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end entity computer_system;
-- end code from book
-- code from book
architecture block_level of computer_system is
-- . . . -- type and component declarations for cpu and memory, etc
signal clock : bit; -- the system clock
signal mem_req : bit; -- cpu access request to memory
signal ifetch : bit; -- indicates access is to fetch an instruction
signal write : bit; -- indicates access is a write
-- . . . -- other signal declarations
begin
-- . . . -- component instances for cpu and memory, etc
instrumentation : if instrumented generate
signal ifetch_freq, write_freq, read_freq : real := 0.0;
begin
access_monitor : process is
variable access_count, ifetch_count,
write_count, read_count : natural := 0;
begin
wait until mem_req = '1';
if ifetch = '1' then
ifetch_count := ifetch_count + 1;
elsif write = '1' then
write_count := write_count + 1;
else
read_count := read_count + 1;
end if;
access_count := access_count + 1;
ifetch_freq <= real(ifetch_count) / real(access_count);
write_freq <= real(write_count) / real(access_count);
read_freq <= real(read_count) / real(access_count);
end process access_monitor;
end generate instrumentation;
-- not in book
stimulus : process is
begin
ifetch <= '1'; write <= '0';
mem_req <= '1', '0' after 10 ns;
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '1';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
wait;
end process stimulus;
-- end not in book
end architecture block_level;
-- end code from book
entity fg_14_06 is
end entity fg_14_06;
architecture test of fg_14_06 is
component computer_system is
port ( other_port : in bit := '0' );
end component computer_system;
begin
system_under_test : component computer_system
port map ( other_port => open );
end architecture test;
configuration fg_14_06_test of fg_14_06 is
for test
-- code from book (in text)
for system_under_test : computer_system
use entity work.computer_system(block_level)
generic map ( instrumented => true )
-- . . .
-- not in book
;
-- end not in book
end for;
-- end code from book
end for;
end configuration fg_14_06_test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1813.vhd | 4 | 2292 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1813.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01813ent IS
END c07s01b00x00p08n01i01813ent;
ARCHITECTURE c07s01b00x00p08n01i01813arch OF c07s01b00x00p08n01i01813ent IS
type A1 is array (1 to 5) of integer;
type Acc is access A1;
BEGIN
TESTING: PROCESS
variable V1 : Acc := new A1'(1,2,3,4,5);
variable V2 : integer;
variable V3 : integer;
variable V4 : integer;
variable V5 : integer;
variable V6 : integer;
BEGIN
V2 := V1(1); -- No_failure_here
V3 := V1(2); -- No_failure_here
V4 := V1(3); -- No_failure_here
V5 := V1(4); -- No_failure_here
V6 := V1(5); -- No_failure_here
assert NOT(V2=1 and V3=2 and V4=3 and V5=4 and V6=5)
report "***PASSED TEST: c07s01b00x00p08n01i01813"
severity NOTE;
assert (V2=1 and V3=2 and V4=3 and V5=4 and V6=5)
report "***FAILED TEST: c07s01b00x00p08n01i01813 - The primary must be a name, a literal, an aggregate, a function call, a qualified expression, a type conversion, an allocator, or an expression enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01813arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_01.vhd | 4 | 2074 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_fg_12_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- code from book
entity control_unit is
generic ( Tpd_clk_out, Tpw_clk : delay_length;
debug : boolean := false );
port ( clk : in bit;
ready : in bit;
control1, control2 : out bit );
end entity control_unit;
-- end code from book
architecture test of control_unit is
begin
end architecture test;
entity fg_12_01 is
end entity fg_12_01;
architecture test of fg_12_01 is
signal clk, ready : bit;
begin
dut1 : entity work.control_unit
-- code from book (in text)
generic map ( 200 ps, 1500 ps, false )
-- end code from book
port map ( clk, ready, open, open );
dut2 : entity work.control_unit
-- code from book (in text)
generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
-- end code from book
port map ( clk, ready, open, open );
dut3 : entity work.control_unit
-- code from book (in text)
generic map ( 200 ps, 1500 ps, debug => open )
-- end code from book
port map ( clk, ready, open, open );
end architecture test;
| gpl-2.0 |
emogenet/ghdl | libraries/ieee/std_logic_1164.vhdl | 4 | 9549 | -- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/92 |
-- --------------------------------------------------------------------
PACKAGE std_logic_1164 IS
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-------------------------------------------------------------------
TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
-------------------------------------------------------------------
-- *** industry standard logic type ***
-------------------------------------------------------------------
SUBTYPE std_logic IS resolved std_ulogic;
-------------------------------------------------------------------
-- unconstrained array of std_logic for use in declaring signal arrays
-------------------------------------------------------------------
TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1')
SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z')
SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')
SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; --!V87
FUNCTION "not" ( l : std_ulogic ) RETURN UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
FUNCTION "xnor" ( l, r : std_logic_vector ) RETURN std_logic_vector; --!V87
FUNCTION "xnor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;--!V87
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT;
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic;
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector;
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( b : BIT ) RETURN X01;
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z;
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( b : BIT ) RETURN UX01;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN;
END std_logic_1164;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/vector.d/muxb_117.vhd | 2 | 355 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity muxb_117 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end muxb_117;
architecture augh of muxb_117 is
begin
out_data <= in_data0 when in_sel = '0' else in_data1;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2597.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2597.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02597ent IS
END c13s03b01x00p02n01i02597ent;
ARCHITECTURE c13s03b01x00p02n01i02597arch OF c13s03b01x00p02n01i02597ent IS
BEGIN
TESTING: PROCESS
variable k] : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02597 - Identifier can not end with ']'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02597arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2422.vhd | 4 | 1933 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2422.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n01i02422ent IS
END c07s03b02x01p01n01i02422ent;
ARCHITECTURE c07s03b02x01p01n01i02422arch OF c07s03b02x01p01n01i02422ent IS
BEGIN
TESTING: PROCESS
type A_RECORD is record
A : CHARACTER;
end record;
type B_RECORD is record
B : CHARACTER;
end record;
variable A : A_RECORD;
variable B : B_RECORD;
BEGIN
A := A_RECORD'(B=>'E'); -- Failure_here
-- SEMANTICS ERROR: choice does not denote record element
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n01i02422 - Given element name does not match the record type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n01i02422arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2488.vhd | 4 | 1717 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2488.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p02n01i02488ent IS
END c07s03b03x00p02n01i02488ent;
ARCHITECTURE c07s03b03x00p02n01i02488arch OF c07s03b03x00p02n01i02488ent IS
BEGIN
TESTING: PROCESS
function func1 (a2 : integer) return integer is
begin
return 5;
end func1;
variable x: integer := 1;
variable y: integer;
BEGIN
y := func1 ();
assert FALSE
report "***FAILED TEST: c07s03b03x00p02n01i02488 - Missing parameter list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p02n01i02488arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_23.vhd | 4 | 1237 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_23.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity S_R_flipflop is
port ( s, r : in bit; q, q_n : out bit );
begin
check : assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
end entity S_R_flipflop;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc676.vhd | 4 | 2186 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc676.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00676ent IS
END c03s04b01x00p23n01i00676ent;
ARCHITECTURE c03s04b01x00p23n01i00676arch OF c03s04b01x00p23n01i00676ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type POSITIVE_R is range 0.0 to REAL'HIGH;
type FT is file of POSITIVE_R;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.54";
-- Declare a variable.
constant CON : POSITIVE_R := 1.0;
variable VAR : POSITIVE_R := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00676 - The output file will tested by test file s010422.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00676arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/perf02/decis_levl.vhd | 3 | 2193 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity decis_levl is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end decis_levl;
architecture augh of decis_levl is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("00000000000000000000000100011000", "00000000000000000000001001000000", "00000000000000000000001101110000", "00000000000000000000010010110000", "00000000000000000000010111110000", "00000000000000000000011101001000", "00000000000000000000100010100000", "00000000000000000000101000011000", "00000000000000000000101110010000", "00000000000000000000110100110000", "00000000000000000000111011001000", "00000000000000000001000010010000", "00000000000000000001001001011000", "00000000000000000001010001010000", "00000000000000000001011001010000", "00000000000000000001100010010000", "00000000000000000001101011010000", "00000000000000000001110101100000", "00000000000000000001111111111000", "00000000000000000010001100001000", "00000000000000000010011000011000", "00000000000000000010100111011000", "00000000000000000010110110010000", "00000000000000000011001001100000", "00000000000000000011011100101000", "00000000000000000011110111100000", "00000000000000000100010010011000", "00000000000000000100111111101000", "00000000000000000101101100111000", "00000000000000000111111111111111", "00000000000000000000000000000000", "00000000000000000000000000000000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2672.vhd | 4 | 1676 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2672.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02672ent IS
END c13s03b01x00p02n01i02672ent;
ARCHITECTURE c13s03b01x00p02n01i02672arch OF c13s03b01x00p02n01i02672ent IS
BEGIN
TESTING: PROCESS
variable {k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02672 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02672arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc594.vhd | 4 | 2890 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc594.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:56 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:17 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00594ent IS
END c03s04b01x00p01n01i00594ent;
ARCHITECTURE c03s04b01x00p01n01i00594arch OF c03s04b01x00p01n01i00594ent IS
type integer_vector is array (natural range <>) of integer;
type integer_vector_file is file of integer_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : integer_vector_file open read_mode is "iofile.25";
variable v : integer_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1,2,3,4)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00594"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00594 - File reading operation (integer_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00594arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1808.vhd | 4 | 1762 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1808.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p07n01i01808ent IS
END c07s01b00x00p07n01i01808ent;
ARCHITECTURE c07s01b00x00p07n01i01808arch OF c07s01b00x00p07n01i01808ent IS
signal POS : integer;
signal P1 : integer := -2;
BEGIN
TESTING: PROCESS
BEGIN
POS <= abs P1 after 20 ns;
wait for 35 ns;
assert NOT(POS = 2)
report "***PASSED TEST: c07s01b00x00p07n01i01808"
severity NOTE;
assert (POS = 2)
report "***FAILED TEST: c07s01b00x00p07n01i01808 - abs Primary test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p07n01i01808arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc896.vhd | 4 | 1749 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc896.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s02b00x00p02n02i00896ent IS
generic ( x : integer := 2 );
END c10s02b00x00p02n02i00896ent;
ARCHITECTURE c10s02b00x00p02n02i00896arch OF c10s02b00x00p02n02i00896ent IS
BEGIN
-- extended use of declared generic.
assert NOT( x = 2 )
report "***PASSED TEST: c10s02b00x00p02n02i00896"
severity NOTE;
assert ( x = 2 )
report "***FAILED TEST: c10s02b00x00p02n02i00896 - The scope of the declaration that occurs immediately within a formal generic declaration extends beyond the immediate scope."
severity ERROR;
END c10s02b00x00p02n02i00896arch;
| gpl-2.0 |
emogenet/ghdl | libraries/synopsys/std_logic_arith.vhdl | 5 | 70211 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
package body std_logic_arith is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in integer range 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in integer range 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 296
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 295
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 297
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 298
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 301
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 300
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 302
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length+1), CONV_SIGNED(R, R'length)));
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 303
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length+1)));
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 236
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 237
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 238
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 239
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 240
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 241
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 242
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 243
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 244
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 245
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 246
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 247
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 260
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 261
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 262
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 263
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 264
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 265
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 266
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 267
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 268
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length))) ;
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 269
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 270
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 271
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 248
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 249
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 250
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 251
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 252
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 253
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 254
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 255
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 256
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 257
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 258
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 259
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 272
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_minus(-- pragma label minus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 273
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 274
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 275
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 276
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 277
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 278
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 279
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 280
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 281
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 282
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 283
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 284
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 285
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 286
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 287
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 289
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 290
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 292
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 294
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 305
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 306
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 307
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 308
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 309
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 310
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 311
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 312
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 314
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 315
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 316
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 317
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 318
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 319
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 320
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 321
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 323
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 324
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 325
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 326
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 327
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 328
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 329
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 330
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 332
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 333
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 334
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 335
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 336
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 337
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 338
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 339
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 341
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 342
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 343
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 344
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 345
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 346
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 347
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 348
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 350
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 351
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 352
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 353
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 354
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 355
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 356
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 357
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 358
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 359
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 360
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 361
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
-- synopsys subpgm_id 365
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
-- synopsys subpgm_id 366
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
-- synopsys subpgm_id 367
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
-- synopsys subpgm_id 370
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
-- synopsys subpgm_id 371
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 372
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 373
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 375
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 376
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 377
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 378
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 380
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 381
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 382
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 383
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 384
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 385
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 386
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1337.vhd | 4 | 1775 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1337.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01337ent IS
END c08s04b01x00p04n01i01337ent;
ARCHITECTURE c08s04b01x00p04n01i01337arch OF c08s04b01x00p04n01i01337ent IS
signal X : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
X <= 15 after 10 ps;
wait for 10 ps;
assert NOT( X=15 )
report "***PASSED TEST: c08s04b01x00p04n01i01337"
severity NOTE;
assert ( X=15 )
report "***FAILED TEST: c08s04b01x00p04n01i01337 - Predefined TIME unit ps as the base type of the time expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01337arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_04.vhd | 4 | 1667 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity counter is
port ( clk, reset : in bit; count : out natural );
end entity counter;
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
loop
wait until clk = '1' or reset = '1';
exit when reset = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
-- at this point, reset = '1'
count_value := 0;
count <= count_value;
wait until reset = '0';
end loop;
end process incrementer;
end architecture behavior;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_2.vhdl | 4 | 2021 |
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity fopen_test_3 is
end fopen_test_3;
architecture test0 of fopen_test_3 is
constant StringLength: integer := 16;
constant NumOfStrings: integer := 5;
subtype str16 is string (1 to StringLength);
type string_table is array (1 to NumOfStrings) of str16;
constant string_array: string_table :=
( "This is string 1"
,"__Hello World__"
,"This is string " & "3"
,"_Bird is a word_"
,"_Goodbye (ciao)_"
);
type ft is file of string;
begin
doit: process
file file_desc : ft;
begin
file_open(file_desc, "fopen_test_2.out", write_mode);
for i in NumOfStrings downto 1 loop
write(file_desc, string_array(i));
end loop;
file_close(file_desc);
file_open(file_desc, "fopen_test_2.out", append_mode);
for i in 1 to NumOfStrings loop
write(file_desc, string_array(i));
end loop;
file_close(file_desc);
wait;
end process;
end test0;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3153.vhd | 4 | 2895 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3153.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p01n01i03153ent IS
END c05s03b00x00p01n01i03153ent;
ARCHITECTURE c05s03b00x00p01n01i03153arch OF c05s03b00x00p01n01i03153ent IS
begin
--Enclose the whole schematic in a block
L : block
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Define the disconnect specification.
disconnect SIG : RBIT after 0 ns;
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable pass : integer := 0;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
wait on SIG;
assert( SIG = '1' );
if ( SIG = '1' ) then
pass := pass + 1;
end if;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
wait on SIG;
assert( SIG = '0' );
if ( SIG = '0' ) then
pass := pass + 1;
end if;
wait for 50 ns;
assert NOT( pass = 2 )
report "***PASSED TEST: c05s03b00x00p01n01i03153"
severity NOTE;
assert ( pass = 2 )
report "***FAILED TEST: c05s03b00x00p01n01i03153 - Disconnect in block statement does not work properly."
severity ERROR;
wait;
END PROCESS TESTING;
end block L;
END c05s03b00x00p01n01i03153arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire.vhd | 4 | 1477 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_ire.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.dlx_types.all;
entity ir_extender is
generic ( Tpd : delay_length );
port ( d : in dlx_word;
q : out dlx_word;
immed_size_26 : in std_logic;
immed_unsigned : in std_logic;
immed_en : in std_logic );
end entity ir_extender;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_02.vhd | 4 | 2897 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_02 is
end entity ap_a_02;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_02 is
-- code from book
-- end code from book
begin
b1 : block is
signal sulv : std_ulogic_vector(7 downto 0);
signal slv : std_logic_vector(7 downto 0);
begin
-- code from book
sulv <= To_stdulogicvector ( slv );
-- end code from book
slv <= "10101010";
end block b1;
b2 : block is
signal sulv : std_ulogic_vector(7 downto 0);
signal slv : std_logic_vector(7 downto 0);
begin
-- code from book
slv <= To_stdlogicvector ( sulv );
-- end code from book
sulv <= "00001111";
end block b2;
b3 : block is
signal a, ena, y : std_logic;
begin
-- code from book
y <= a when ena = '1' else
'Z';
-- end code from book
ena <= '0', '1' after 20 ns, '0' after 40 ns;
a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
end block b3;
b4 : block is
signal a, ena, y : std_logic;
begin
-- code from book
y <= a when ena = '1' else
'H';
-- end code from book
ena <= '0', '1' after 20 ns, '0' after 40 ns;
a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
end block b4;
b5 : block is
signal a, b, x, s, y : std_logic;
begin
-- code from book
y <= a when x = '1' else
b when s = '1' else
'-';
-- end code from book
x <= '0', '1' after 20 ns, '0' after 40 ns;
s <= '0', '1' after 60 ns, '0' after 80 ns;
a <= '0', '1' after 10 ns, '0' after 30 ns,
'1' after 50 ns, '0' after 70 ns,
'1' after 90 ns;
b <= '0', '1' after 15 ns, '0' after 35 ns,
'1' after 55 ns, '0' after 75 ns,
'1' after 95 ns;
end block b5;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1052.vhd | 4 | 1739 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1052.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01052ent IS
END c06s04b00x00p03n02i01052ent;
ARCHITECTURE c06s04b00x00p03n02i01052arch OF c06s04b00x00p03n02i01052ent IS
type arrtype is array (positive range 1 to 10, bit range '0' to '1') of real;
BEGIN
TESTING: PROCESS
variable k : arrtype ;
BEGIN
str (1 + 2, 0 + 2) := 1.2; -- illegal.
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01052 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01052arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3036.vhd | 4 | 2114 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3036.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p01n02i03036ent IS
END c12s02b02x00p01n02i03036ent;
ARCHITECTURE c12s02b02x00p01n02i03036arch OF c12s02b02x00p01n02i03036ent IS
BEGIN
-- test for no associations
bl1: block
generic(i:integer:=10; r:real:=3.4; b:bit:='1');
begin
assert (i=10)
report "Default value for integer generic not correct"
severity failure;
assert (r=3.4)
report "Default value for real generic not correct"
severity failure;
assert (b='1')
report "Default value for bit generic not correct"
severity failure;
assert NOT( i=10 and r=3.4 and b='1')
report "***PASSED TEST: c12s02b02x00p01n02i03036"
severity NOTE;
assert ( i=10 and r=3.4 and b='1')
report "***FAILED TEST: c12s02b02x00p01n02i03036 - The actual part of an implicit association element is the default expression test failed."
severity ERROR;
end block;
END c12s02b02x00p01n02i03036arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1977.vhd | 4 | 1841 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1977.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p01n02i01977ent IS
END c07s02b02x00p01n02i01977ent;
ARCHITECTURE c07s02b02x00p01n02i01977arch OF c07s02b02x00p01n02i01977ent IS
BEGIN
TESTING: PROCESS
type array_type is array (1 to 10) of integer;
constant x : integer := 3;
variable y : array_type := (0,9,8,7,6,5,4,3,2,1);
BEGIN
if (x = y) then -- Failure_here
--operands should be of the same type.
NULL;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p01n02i01977 - Operands of a relational operator should be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p01n02i01977arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug046/bug_pkg.vhdl | 2 | 459 | package bug_pkg is
procedure proc_bug(constant t : in time := 8.68 us);
procedure proc_ok1(constant t : in time);
procedure proc_ok2(constant t : in integer := 5);
end bug_pkg;
package body bug_pkg is
procedure proc_bug(constant t : in time := 8.68 us) is
begin
end proc_bug;
procedure proc_ok1(constant t : in time) is
begin
end proc_ok1;
procedure proc_ok2(constant t : in integer := 5) is
begin
end proc_ok2;
end bug_pkg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc888.vhd | 4 | 1888 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc888.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s02b00x00p10n01i00888ent IS
END c10s02b00x00p10n01i00888ent;
ARCHITECTURE c10s02b00x00p10n01i00888arch OF c10s02b00x00p10n01i00888ent IS
procedure xyz ( a : integer; b : real ) is
begin
assert NOT( b = 2.0 * real(a) )
report "***PASSED TEST: c10s02b00x00p10n01i00888"
severity NOTE;
assert ( b = 2.0 * real(a) )
report "***FAILED TEST: c10s02b00x00p10n01i00888 - When in the absence of a separate subprogram declaration, the subprogram specification given in the subprogram body acts as the declaration."
severity ERROR;
end xyz;
BEGIN
TESTING: PROCESS
BEGIN
xyz ( a => 20, b => 40.0 );
wait;
END PROCESS TESTING;
END c10s02b00x00p10n01i00888arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1962.vhd | 4 | 1770 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1962.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01962ent IS
END c07s02b01x00p02n02i01962ent;
ARCHITECTURE c07s02b01x00p02n02i01962arch OF c07s02b01x00p02n02i01962ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := FALSE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01962"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01962 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01962arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/vector.d/cmp_176.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_176 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_176;
architecture augh of cmp_176 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2014.vhd | 4 | 1911 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2014.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p11n02i02014ent IS
END c07s02b02x00p11n02i02014ent;
ARCHITECTURE c07s02b02x00p11n02i02014arch OF c07s02b02x00p11n02i02014ent IS
signal S1 : BIT_VECTOR(0 downto 7);
signal S2 : BIT_VECTOR(0 to 7) := "10101010";
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if (S1 < S2) then
k := 5;
end if;
wait for 1 ns;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p11n02i02014"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p11n02i02014 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p11n02i02014arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3045.vhd | 4 | 2296 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3045.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p02n03i03045ent IS
END c12s02b02x00p02n03i03045ent;
ARCHITECTURE c12s02b02x00p02n03i03045arch OF c12s02b02x00p02n03i03045ent IS
BEGIN
bl1: block
generic (i1:integer; i2:integer; i3:integer; i4:integer);
generic map(3, -5, i4=>-4, i3=>6);
begin
assert (i1=3)
report "Generic association for first element I1 incorrect"
severity failure;
assert (i2=-5)
report "Generic association for second element I2 incorrect"
severity failure;
assert (i3=6)
report "Generic association for third element I3 incorrect"
severity failure;
assert (i4=-4)
report "Generic association for fourth element I4 incorrect"
severity failure;
assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***PASSED TEST: c12s02b02x00p02n03i03045"
severity NOTE;
assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***FAILED TEST: c12s02b02x00p02n03i03045 - Named association and positional association of generics creates constnats without the correct values."
severity ERROR;
end block;
END c12s02b02x00p02n03i03045arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug015/phys2.vhdl | 3 | 213 | entity tb2 is
end;
use work.physical.all;
architecture test of tb2 is
constant CLOCK_FREQ : FREQ := MHz;
procedure p (a : freq) is
begin
end p;
begin
p (clock_freq);
-- empty
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc569.vhd | 4 | 2341 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc569.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:33 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:31 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:05 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00569ent IS
END c03s04b01x00p01n01i00569ent;
ARCHITECTURE c03s04b01x00p01n01i00569arch OF c03s04b01x00p01n01i00569ent IS
type real_file is file of real;
BEGIN
TESTING: PROCESS
file filein : real_file open write_mode is "iofile.19";
BEGIN
for i in 1 to 100 loop
write(filein,3.0);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00569 - The output file will be verified by test s010212.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00569arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/enumeration-for-loop-constrained.vhdl | 4 | 369 | entity test is
end test;
architecture only of test is
begin -- only
p: process
type color is ( red, blue, green );
variable x : color;
begin -- process p
for i in red to blue loop
x := i;
end loop; -- i
assert x = blue report "TEST FAILED x was " & color'image(x) severity ERROR;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc450.vhd | 4 | 3091 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc450.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00450ent IS
END c03s02b01x01p19n01i00450ent;
ARCHITECTURE c03s02b01x01p19n01i00450arch OF c03s02b01x01p19n01i00450ent IS
type four_value is ('Z','0','1','X'); --enumerated type
constant C77 : four_value := 'Z';
function complex_scalar(s : four_value) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return four_value is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : four_value;
signal S2 : four_value;
signal S3 : four_value := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00450"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00450 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00450arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1890.vhd | 4 | 1890 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1890.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01890ent IS
END c07s01b00x00p08n01i01890ent;
ARCHITECTURE c07s01b00x00p08n01i01890arch OF c07s01b00x00p08n01i01890ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int'(TESTING)) after 5 ns;
-- process label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01890 - Process labels are not permitted as primaries in a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01890arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1444.vhd | 4 | 1860 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1444.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01444ent IS
END c08s07b00x00p02n01i01444ent;
ARCHITECTURE c08s07b00x00p02n01i01444arch OF c08s07b00x00p02n01i01444ent IS
begin
transmit: process
variable k : integer := 10;
variable m : integer := 6;
variable n : integer ;
begin
if m > 5 then
for n in 1 to 5 loop
k := k - 1;
end loop;
end if;
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01444 - FOR LOOP statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01444"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01444arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_02.vhd | 4 | 1852 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_ch_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
entity reg is
port ( d : in bit_vector; q : out bit_vector; -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end entity reg;
-- end code from book
architecture test of reg is
begin
q <= d;
end architecture test;
entity ch_12_02 is
end entity ch_12_02;
----------------------------------------------------------------
architecture test of ch_12_02 is
-- code from book
signal small_data : bit_vector(0 to 7);
signal large_data : bit_vector(0 to 15);
-- . . .
-- end code from book
begin
-- code from book
problem_reg : entity work.reg
port map ( d => small_data, q => large_data, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- end code from book
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc997.vhd | 4 | 1770 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc997.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i00997pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i00997pkg;
use work.c06s03b00x00p09n01i00997pkg.all;
ENTITY c06s03b00x00p09n01i00997ent IS
END c06s03b00x00p09n01i00997ent;
ARCHITECTURE c06s03b00x00p09n01i00997arch OF c06s03b00x00p09n01i00997ent IS
BEGIN
TESTING: PROCESS
subtype ST1 is Q.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i00997 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i00997arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/add_382.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_382 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_382;
architecture augh of add_382 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd | 4 | 1736 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp is
port ( terminal positive_supply, negative_supply : electrical;
terminal plus_in, minus_in, output : electrical );
end entity opamp;
----------------------------------------------------------------
architecture saturating of opamp is
constant gain : real := 50.0;
quantity v_pos across positive_supply;
quantity v_neg across negative_supply;
quantity v_in across plus_in to minus_in;
quantity v_out across i_out through output;
quantity v_amplified : voltage;
begin
if v_in'above(v_pos / gain) use
v_amplified == v_pos;
elsif not v_in'above(v_neg / gain) use
v_amplified == v_neg;
else
v_amplified == gain * v_in;
end use;
break on v_in'above(v_pos/gain), v_in'above(v_neg/gain);
v_out == v_amplified'slew(1.0e6,-1.0e6);
end architecture saturating;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc251.vhd | 4 | 1881 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc251.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00251ent IS
END c03s01b02x00p04n01i00251ent;
ARCHITECTURE c03s01b02x00p04n01i00251arch OF c03s01b02x00p04n01i00251ent IS
type I1 is range 1 to 10;
type I2 is range 11 to 20;
constant V1: I1 := 1;
constant V2: I2 := 20;
type I5 is range V1 to V2;
BEGIN
TESTING: PROCESS
variable k : integer := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p04n01i00251"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p04n01i00251 - Range constraints in integer type definition need not be of the same integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00251arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug08/paren10.vhdl | 3 | 309 | entity paren10 is
end paren10;
architecture behav of paren10
is
begin
process
type string_acc is access string;
function a return string_acc is
begin
return new string'("hello");
end a;
constant b : natural := 2;
begin
assert a(b) = 'e';
wait;
end process;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc701.vhd | 4 | 3130 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc701.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:07 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:41 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:45 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00701ent IS
END c03s04b01x00p23n01i00701ent;
ARCHITECTURE c03s04b01x00p23n01i00701arch OF c03s04b01x00p23n01i00701ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of NATURAL;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.08";
-- Declare a variable into which we will read.
constant CON : NATURAL := 1;
variable VAR : NATURAL;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00701"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00701 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00701arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2742.vhd | 4 | 1792 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2742.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p04n01i02742ent IS
END c13s06b00x00p04n01i02742ent;
ARCHITECTURE c13s06b00x00p04n01i02742arch OF c13s06b00x00p04n01i02742ent IS
constant mystring : string := "123456789";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( mystring'length = 9 )
report "***PASSED TEST: c13s06b00x00p04n01i02742"
severity NOTE;
assert ( mystring'length = 9 )
report "***FAILED TEST: c13s06b00x00p04n01i02742 - The length of a digit string is the number of character values in the sequence represented."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p04n01i02742arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc4.vhd | 4 | 1655 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc4.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p04n01i00004ent IS
END c04s01b00x00p04n01i00004ent;
ARCHITECTURE c04s01b00x00p04n01i00004arch OF c04s01b00x00p04n01i00004ent IS
-- a constrained array declaration
type my_word is array (one => 0 to 31) of bit; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s01b00x00p04n01i00004 - Syntax error in type declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p04n01i00004arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc334.vhd | 4 | 1815 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc334.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00334ent IS
END c03s02b01x00p06n01i00334ent;
ARCHITECTURE c03s02b01x00p06n01i00334arch OF c03s02b01x00p06n01i00334ent IS
type bit_vctor is array (1 to 8, 8 downto 1) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1,8) := 56;
assert NOT(k(1,8)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00334"
severity NOTE;
assert (k(1,8)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00334 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00334arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/sync_ram.vhd | 4 | 980 | -- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector;
datain : in std_logic_vector;
dataout : out std_logic_vector
);
end entity sync_ram;
architecture rtl of sync_ram is
type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
signal ram : ram_type;
signal read_address : std_logic_vector(address'range);
begin
ramproc: process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
read_address <= address;
end if;
end process ramproc;
dataout <= ram(to_integer(unsigned(read_address)));
end architecture rtl;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2499.vhd | 4 | 1914 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2499.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p05n01i02499ent IS
END c07s03b03x00p05n01i02499ent;
ARCHITECTURE c07s03b03x00p05n01i02499arch OF c07s03b03x00p05n01i02499ent IS
BEGIN
TESTING: PROCESS
function check (x : boolean) return boolean is
begin
return false;
end;
variable q1: boolean := true;
variable q2: boolean ;
BEGIN
q2 := check (check (q1)); -- q2 should be false
assert NOT(q2=FALSE)
report "***PASSED TEST: c07s03b03x00p05n01i02499"
severity NOTE;
assert (q2=FALSE)
report "***FAILED TEST: c07s03b03x00p05n01i02499 - Actual parameter must belong to the subtype of the associated formal parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p05n01i02499arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_24.vhd | 4 | 1379 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_24.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ROM is
port ( address : in natural;
data : out bit_vector(0 to 7);
enable : in bit );
begin
trace_reads : process (enable) is
begin
if enable = '1' then
report "ROM read at time " & time'image(now)
& " from address " & natural'image(address);
end if;
end process trace_reads;
end entity ROM;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2797.vhd | 4 | 1602 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2797.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity EXIT is
end EXIT;
ENTITY c13s09b00x00p99n01i02797ent IS
END c13s09b00x00p99n01i02797ent;
ARCHITECTURE c13s09b00x00p99n01i02797arch OF c13s09b00x00p99n01i02797ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02797 - Reserved word EXIT can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02797arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1401.vhd | 4 | 1760 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1401.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p06n01i01401ent IS
END c08s05b00x00p06n01i01401ent;
ARCHITECTURE c08s05b00x00p06n01i01401arch OF c08s05b00x00p06n01i01401ent IS
BEGIN
TESTING: PROCESS
subtype ST is REAL range 1.0 to 10.0;
variable ILL : REAL := 11.0;
variable V : ST;
BEGIN
V := ILL; -- should catch error here
assert FALSE
report "***FAILED TEST: c08s05b00x00p06n01i01401 - Variable assignment scalar subtype (real type) check test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p06n01i01401arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2158.vhd | 4 | 2177 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2158.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02158ent IS
END c07s02b04x00p21n01i02158ent;
ARCHITECTURE c07s02b04x00p21n01i02158arch OF c07s02b04x00p21n01i02158ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_1 is severity_level_v (1 to 1);
SUBTYPE severity_level_null is severity_level_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : severity_level_1;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level_null;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=NOTE)
report "***PASSED TEST: c07s02b04x00p21n01i02158"
severity NOTE;
assert (result(1)=NOTE)
report "***FAILED TEST: c07s02b04x00p21n01i02158 - Concatenation of null and SEVERITY_LEVEL element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02158arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd | 4 | 2015 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
begin
block_1_a : block is
-- code from book:
type word is array (0 to 31) of bit;
--
type controller_state is (initial, idle, active, error);
type state_counts is array (idle to error) of natural;
-- end of code from book
begin
end block block_1_a;
process_1_a : process is
-- code from book:
type word is array (31 downto 0) of bit;
--
type controller_state is (initial, idle, active, error);
--
type state_counts is
array (controller_state range idle to error) of natural;
--
subtype coeff_ram_address is integer range 0 to 63;
type coeff_array is array (coeff_ram_address) of real;
--
variable buffer_register, data_register : word;
variable counters : state_counts;
variable coeff : coeff_array;
-- end of code from book
begin
-- code from book:
coeff(0) := 0.0;
counters(active) := counters(active) + 1;
data_register := buffer_register;
-- end of code from book
wait;
end process process_1_a;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2036.vhd | 4 | 1661 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2036.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02036ent IS
END c07s02b04x00p01n01i02036ent;
ARCHITECTURE c07s02b04x00p01n01i02036arch OF c07s02b04x00p01n01i02036ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
BEGIN
BOOLV := BOOLV + BOOLV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02036 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02036arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc577.vhd | 4 | 2850 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc577.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:35 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:48 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:12 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00577ent IS
END c03s04b01x00p01n01i00577ent;
ARCHITECTURE c03s04b01x00p01n01i00577arch OF c03s04b01x00p01n01i00577ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type boolean_cons_vector_file is file of boolean_cons_vector;
constant C19 : boolean_cons_vector := (others => true);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : boolean_cons_vector_file open read_mode is "iofile.28";
variable v : boolean_cons_vector;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C19) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00577"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00577 - File reading operation (boolean_cons_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00577arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu-b.vhd | 4 | 2944 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_alu-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture behavior of alu is
begin
alu_op: process ( s1, s2, func ) is
variable bv_s1, bv_s2 : dlx_bv_word;
variable temp_result : dlx_bv_word;
variable temp_overflow : boolean;
type boolean_to_X01_table is array (boolean) of X01;
constant boolean_to_X01 : boolean_to_X01_table := ( '0', '1' );
begin
bv_s1 := To_bitvector(s1);
bv_s2 := To_bitvector(s2);
temp_overflow := false;
case func is
when alu_pass_s1 =>
temp_result := bv_s1;
when alu_pass_s2 =>
temp_result := bv_s2;
when alu_and =>
temp_result := bv_s1 and bv_s2;
when alu_or =>
temp_result := bv_s1 or bv_s2;
when alu_xor =>
temp_result := bv_s1 xor bv_s2;
when alu_sll =>
temp_result := bv_s1 sll bv_to_natural(bv_s2(27 to 31));
when alu_srl =>
temp_result := bv_s1 srl bv_to_natural(bv_s2(27 to 31));
when alu_sra =>
temp_result := bv_s1 sra bv_to_natural(bv_s2(27 to 31));
when alu_add =>
bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_addu =>
bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_sub =>
bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_subu =>
bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
when others =>
report "illegal function code" severity error;
temp_result := X"0000_0000";
end case;
result <= To_X01(temp_result) after Tpd;
zero <= boolean_to_X01(temp_result = X"0000_0000") after Tpd;
negative <= To_X01(temp_result(0)) after Tpd;
overflow <= boolean_to_X01(temp_overflow) after Tpd;
end process alu_op;
end architecture behavior;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1523.vhd | 4 | 3438 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1523.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s09b00x00p07n01i01523pkg is
-- Global procedure.
procedure proc1;
-- Global function.
function func1 return INTEGER;
end c08s09b00x00p07n01i01523pkg;
package body c08s09b00x00p07n01i01523pkg is
procedure proc1 is
-- Local variables
variable INTV : INTEGER := 0;
begin
-- Check initialization.
assert (INTV = 0);
-- Loop until the indicated condition has been met.
loop
-- Execute some meaningful function.
null;
-- Increment the counter.
INTV := INTV + 1;
-- If the condition has been met, terminate the loop.
if (INTV = 10) then
return;
end if;
-- Verify that we have not exceeded the limits of the loop.
assert (INTV < 10);
end loop;
-- Should NEVER get to this step.
assert (FALSE)
report "Return has not exited the procedure.";
end proc1;
function func1 return INTEGER is
-- Local variables
variable INTV : INTEGER := 0;
begin
-- Check initialization.
assert (INTV = 0);
-- Loop until the indicated condition has been met.
loop
-- Execute some meaningful function.
null;
-- Increment the counter.
INTV := INTV + 1;
-- If the condition has been met, terminate the loop.
if (INTV = 10) then
return( INTV );
end if;
-- Verify that we have not exceeded the limits of the loop.
assert (INTV < 10);
end loop;
-- Should NEVER get to this step.
assert (FALSE)
report "Return has not exited the procedure.";
end func1;
end c08s09b00x00p07n01i01523pkg;
use work.c08s09b00x00p07n01i01523pkg.all;
ENTITY c08s09b00x00p07n01i01523ent IS
END c08s09b00x00p07n01i01523ent;
ARCHITECTURE c08s09b00x00p07n01i01523arch OF c08s09b00x00p07n01i01523ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
-- Call procedure to loop/return.
proc1;
assert NOT(func1=10)
report "***PASSED TEST: c08s09b00x00p07n01i01523"
severity NOTE;
assert (func1=10)
report "***PASSED TEST: c08s09b00x00p07n01i01523 - Function did not return proper value."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s09b00x00p07n01i01523arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_03.vhd | 4 | 1512 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
function pulled_up ( drivers : bit_vector ) return bit is
begin
for index in drivers'range loop
if drivers(index) = '0' then
return '0';
end if;
end loop;
return '1';
end function pulled_up;
signal s : pulled_up bit bus;
begin
process is
begin
s <= '1' after 11 ns, '0' after 16 ns, '1' after 18 ns,
null after 19 ns, '0' after 25 ns;
wait for 10 ns;
-- code from book:
s <= reject 3 ns inertial null after 10 ns;
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1503.vhd | 4 | 1745 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1503.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n03i01503ent IS
END c08s08b00x00p14n03i01503ent;
ARCHITECTURE c08s08b00x00p14n03i01503arch OF c08s08b00x00p14n03i01503ent IS
BEGIN
TESTING: PROCESS
variable x : integer;
BEGIN
case x is
when 1 => NULL;
when 2 => NULL;
when 3 => NULL;
when 4 => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p14n03i01503 - OTHERS choice is required as an alternative in a CASE statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n03i01503arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc697.vhd | 4 | 2153 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc697.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:05 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00697ent IS
END c03s04b01x00p23n01i00697ent;
ARCHITECTURE c03s04b01x00p23n01i00697arch OF c03s04b01x00p23n01i00697ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of SEVERITY_LEVEL;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.55";
-- Declare a variable.
constant CON : SEVERITY_LEVEL := WARNING;
variable VAR : SEVERITY_LEVEL := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00697 - The output file will tested by test file s010426.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00697arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2433.vhd | 4 | 1712 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2433.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02433ent IS
END c07s03b02x02p01n01i02433ent;
ARCHITECTURE c07s03b02x02p01n01i02433arch OF c07s03b02x02p01n01i02433ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant C18 : BV1 := (3 => '1', others => '0');
-- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02433 - Expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02433arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1698.vhd | 4 | 1589 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1698.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p05n01i01698ent IS
END c09s02b00x00p05n01i01698ent;
ARCHITECTURE c09s02b00x00p05n01i01698arch OF c09s02b00x00p05n01i01698ent IS
signal s : integer;
BEGIN
TEST : PROCESS(s)
BEGIN
END PROCESS TEST;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s02b00x00p05n01i01698"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s02b00x00p05n01i01698arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1684.vhd | 4 | 1611 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1684.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p02n01i01684ent IS
END c09s02b00x00p02n01i01684ent;
ARCHITECTURE c09s02b00x00p02n01i01684arch OF c09s02b00x00p02n01i01684ent IS
signal done : bit;
signal bomb : bit;
BEGIN
process (done, bomb)
begin
end process;
TESTING : PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s02b00x00p02n01i01684"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s02b00x00p02n01i01684arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/add_206.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_206 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_206;
architecture augh of add_206 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2647.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2647.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02647ent IS
END c13s03b01x00p02n01i02647ent;
ARCHITECTURE c13s03b01x00p02n01i02647arch OF c13s03b01x00p02n01i02647ent IS
BEGIN
TESTING: PROCESS
variable 'k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02647 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02647arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1278.vhd | 4 | 1646 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1278.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01278ent IS
END c08s04b00x00p04n01i01278ent;
ARCHITECTURE c08s04b00x00p04n01i01278arch OF c08s04b00x00p04n01i01278ent IS
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
abs S1 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01278 - Simple expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01278arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1009.vhd | 4 | 2273 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1009.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01009pkg is
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
end c06s03b00x00p09n01i01009pkg;
use work.c06s03b00x00p09n01i01009pkg.all;
ENTITY c06s03b00x00p09n01i01009ent IS
END c06s03b00x00p09n01i01009ent;
ARCHITECTURE c06s03b00x00p09n01i01009arch OF c06s03b00x00p09n01i01009ent IS
BEGIN
TESTING: PROCESS
variable V1 : work.c06s03b00x00p09n01i01009pkg.T2 ; -- No_failure_here
BEGIN
V1.S11 := '1';
V1.S12.S1 := '1';
V1.S12.S2 := 1 ;
assert NOT(V1.S11 = '1' and
V1.S12.S1 = '1' and
V1.S12.S2 = 1 )
report "***PASSED TEST: c06s03b00x00p09n01i01009"
severity NOTE;
assert (V1.S11 = '1' and
V1.S12.S1 = '1' and
V1.S12.S2 = 1 )
report "***FAILED TEST: c06s03b00x00p09n01i01009 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01009arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc122.vhd | 4 | 1761 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc122.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n15i00122ent IS
port (PT: linkage BOOLEAN);
END c04s03b02x00p29n15i00122ent;
ARCHITECTURE c04s03b02x00p29n15i00122arch OF c04s03b02x00p29n15i00122ent IS
BEGIN
TESTING: PROCESS
Variable I2 : BOOLEAN;
BEGIN
I2 := PT'STABLE; -- Failure_here
-- ERROR: ATTRIBUTES OF INTERFACE ELEMENTS OF MODE LINKAGE CANNOT BE READ
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n15i00122 - Attributes of interface elements of mode linkage can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n15i00122arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc501.vhd | 4 | 1942 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc501.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p02n01i00501ent IS
END c03s02b02x00p02n01i00501ent;
ARCHITECTURE c03s02b02x00p02n01i00501arch OF c03s02b02x00p02n01i00501ent IS
type rec_type is
record
x : integer;
y : integer;
end record;
BEGIN
TESTING: PROCESS
variable v1 : rec_type;
BEGIN
v1.x := 12;
v1.y := v1.x * 111;
assert NOT(v1.x=12 and v1.y=1332)
report "***PASSED TEST: c03s02b02x00p02n01i00501"
severity NOTE;
assert (v1.x=12 and v1.y=1332)
report "***FAILED TEST: c03s02b02x00p02n01i00501 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p02n01i00501arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2815.vhd | 4 | 1599 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2815.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity NOR is
end NOR;
ENTITY c13s09b00x00p99n01i02815ent IS
END c13s09b00x00p99n01i02815ent;
ARCHITECTURE c13s09b00x00p99n01i02815arch OF c13s09b00x00p99n01i02815ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02815 - Reserved word NOR can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02815arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc451.vhd | 4 | 3192 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc451.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00451ent IS
END c03s02b01x01p19n01i00451ent;
ARCHITECTURE c03s02b01x01p19n01i00451arch OF c03s02b01x01p19n01i00451ent IS
type four_value is ('Z','0','1','X'); --enumerated type
type four_value_map is array(four_value) of boolean;
constant C77 : four_value_map := (true,true,true,true);
function complex_scalar(s : four_value_map) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return four_value_map is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : four_value_map;
signal S2 : four_value_map;
signal S3 : four_value_map := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00451"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00451 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00451arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd | 4 | 1956 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity do_arith_op is
end entity do_arith_op;
architecture test of do_arith_op is
type func_code is (add, subtract);
signal op1 : integer := 10;
signal op2 : integer := 3;
signal dest : integer := 0;
signal func : func_code := add;
signal Z_flag : boolean := false;
constant Tpd : delay_length := 3 ns;
begin
stimulus : process is
-- code from book
procedure do_arith_op ( op : in func_code ) is
variable result : integer;
begin
case op is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
-- end code from book
begin
wait for 10 ns;
-- code from book (in text)
do_arith_op ( add );
-- end code from book
wait for 10 ns;
-- code from book (in text)
do_arith_op ( func );
-- end code from book
wait for 10 ns;
do_arith_op ( subtract );
wait for 10 ns;
op2 <= 10;
wait for 10 ns;
do_arith_op ( subtract );
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1466.vhd | 4 | 1638 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1466.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p02n01i01466ent IS
END c08s08b00x00p02n01i01466ent;
ARCHITECTURE c08s08b00x00p02n01i01466arch OF c08s08b00x00p02n01i01466ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
BEGIN
case x is
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p02n01i01466 - missing case statement alternatives in case statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p02n01i01466arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/sub_362.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_362 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_362;
architecture augh of sub_362 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc796.vhd | 4 | 1623 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc796.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00796ent IS
begin
wait 3 ns; -- illegal location for wait
END c01s01b03x00p03n01i00796ent;
ARCHITECTURE c01s01b03x00p03n01i00796arch OF c01s01b03x00p03n01i00796ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00796 - Wait statement can not appear in entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00796arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2470.vhd | 4 | 2082 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2470.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02470ent IS
END c07s03b02x02p03n02i02470ent;
ARCHITECTURE c07s03b02x02p03n02i02470arch OF c07s03b02x02p03n02i02470ent IS
BEGIN
TESTING: PROCESS
type ENUM is ( ONE );
type C_ARRAY is array ( ENUM range <>, ENUM range <> ) of bit;
subtype C_CON is C_ARRAY ( ONE to ONE, ONE to ONE );
function F_C ( PAR : C_CON ) return C_CON is
begin
return (ONE=>(ONE=>'0'));
end F_C;
variable V_C : C_CON ;
BEGIN
V_C := F_C( C_ARRAY'(ONE=>('1',others=>'0')) ); -- Failure_here
-- SEMANTIC ERROR: "others" used in aggregate in qualified expression
-- whose type mark denotes an unconstrained array type.
assert FALSE
report "***FAILED TEST: c07s03b02x02p03n02i02470 - Others cannot be used with an unconstrained array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02470arch;
| gpl-2.0 |
openfpga/xc3sprog | bscan_spi/bscan_xc5_spi.vhd | 5 | 4932 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
MOSI_ext : out std_logic;
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE: std_logic;
signal DRCK1: std_logic;
signal TDI: std_logic;
signal TDO1: std_logic;
signal CSB: std_logic := '1';
signal header: std_logic_vector(47 downto 0);
signal len: std_logic_vector(15 downto 0);
signal have_header : std_logic := '0';
signal MISO: std_logic;
signal MOSI: std_logic;
signal SEL1: std_logic;
signal SHIFT: std_logic;
signal RESET: std_logic;
signal CS_GO: std_logic := '0';
signal CS_GO_PREP: std_logic := '0';
signal CS_STOP: std_logic := '0';
signal CS_STOP_PREP: std_logic := '0';
signal RAM_RADDR: std_logic_vector(13 downto 0);
signal RAM_WADDR: std_logic_vector(13 downto 0);
signal DRCK1_INV : std_logic;
signal RAM_DO: std_logic_vector(0 downto 0);
signal RAM_DI: std_logic_vector(0 downto 0);
signal RAM_WE: std_logic := '0';
begin
MOSI_ext <= MOSI;
CSB_ext <= CSB;
DRCK1_INV <= not DRCK1;
RAMB16_S1_S1_inst : RAMB16_S1_S1
port map (
DOA => RAM_DO, -- Port A 1-bit Data Output
DOB => open, -- Port B 1-bit Data Output
ADDRA => RAM_RADDR, -- Port A 14-bit Address Input
ADDRB => RAM_WADDR, -- Port B 14-bit Address Input
CLKA => DRCK1_inv, -- Port A Clock
CLKB => DRCK1, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => RAM_DI, -- Port B 1-bit Data Input
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => '0', -- Port A Write Enable Input
WEB => RAM_WE -- Port B Write Enable Input
);
BSCAN_VIRTEX5_inst : BSCAN_VIRTEX5
generic map (
JTAG_CHAIN => 1 -- Value for USER command. Possible values: (1,2,3 or 4)
)
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK => DRCK1, -- Data register output for USER functions
RESET => RESET, -- Reset output from TAP controller
SEL => SEL1, -- USER active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO => TDO1 -- Data input for USER function
);
-- see XAPP1020
STARTUP_VIRTEX5_inst : STARTUP_VIRTEX5
port map (
CFGCLK => open, -- Config logic clock 1-bit output
CFGMCLK => open, -- Config internal osc clock 1-bit output
DINSPI => MISO, -- DIN SPI PROM access 1-bit output
EOS => open, -- End of Startup 1-bit output
TCKSPI => open, -- TCK SPI PROM access 1-bit output
CLK => open, -- Clock input for start-up sequence
GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- Global 3-state input (GTS cannot be used for the port name)
USRCCLKO => DRCK1, -- User CCLK 1-bit input
USRCCLKTS => '0', -- User CCLK 3-state, 1-bit input
USRDONEO => open, -- User Done 1-bit input
USRDONETS => open -- User Done 3-state, 1-bit input
);
MOSI <= TDI;
CSB <= '0' when CS_GO = '1' and CS_STOP = '0' else '1';
RAM_DI <= MISO & "";
TDO1 <= RAM_DO(0);
-- falling edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
have_header <= '0';
-- disable CSB
CS_GO_PREP <= '0';
CS_STOP <= '0';
elsif falling_edge(DRCK1) then
-- disable CSB?
CS_STOP <= CS_STOP_PREP;
-- waiting for header?
if have_header='0' then
-- got magic + len
if header(46 downto 15) = x"59a659a6" then
len <= header(14 downto 0) & "0";
have_header <= '1';
-- enable CSB on rising edge (if len > 0?)
if (header(14 downto 0) & "0") /= x"0000" then
CS_GO_PREP <= '1';
end if;
end if;
elsif len /= x"0000" then
len <= len - 1;
end if;
end if;
end process;
-- rising edges
process(DRCK1, CAPTURE, RESET, UPDATE, SEL1)
begin
if CAPTURE = '1' or RESET='1' or UPDATE='1' or SEL1='0' then
-- disable CSB
CS_GO <= '0';
CS_STOP_PREP <= '0';
RAM_WADDR <= (others => '0');
RAM_RADDR <= (others => '0');
RAM_WE <= '0';
elsif rising_edge(DRCK1) then
RAM_RADDR <= RAM_RADDR + 1;
RAM_WE <= not CSB;
if RAM_WE='1' then
RAM_WADDR <= RAM_WADDR + 1;
end if;
header <= header(46 downto 0) & TDI;
-- enable CSB?
CS_GO <= CS_GO_PREP;
-- disable CSB on falling edge
if CS_GO = '1' and len = x"0000" then
CS_STOP_PREP <= '1';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1653.vhd | 4 | 2451 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1653.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c09s00b00x00p02n01i01653ent_a is
port (signal ss : in integer);
end c09s00b00x00p02n01i01653ent_a;
architecture c09s00b00x00p02n01i01653arch_a of c09s00b00x00p02n01i01653ent_a is
begin
process
begin
wait;
end process;
end c09s00b00x00p02n01i01653arch_a;
ENTITY c09s00b00x00p02n01i01653ent IS
port ( Pt : in BOOLEAN;
PTO : out BIT) ;
END c09s00b00x00p02n01i01653ent;
ARCHITECTURE c09s00b00x00p02n01i01653arch OF c09s00b00x00p02n01i01653ent IS
component FO
port (signal ss : in INTEGER);
end component ;
for Ls : FO use entity work.c09s00b00x00p02n01i01653ent_a(c09s00b00x00p02n01i01653arch_a);
signal S1, S2 : Integer;
signal S : INTEGER;
BEGIN
-- concurrent signal statement
S <= transport 5;
-- concurrent assertion statement
assert ( not PT)
report " dead wire "
severity WARNING;
-- generate
L_G_1: for I in 1 to 1 generate
L_X_2: block
signal S3 : Bit;
begin
S2 <= transport 1;
end block;
end generate;
-- component instatiation
Ls : FO port map (S1);
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s00b00x00p02n01i01653"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s00b00x00p02n01i01653arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2834.vhd | 4 | 1608 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2834.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RETURN is
end RETURN;
ENTITY c13s09b00x00p99n01i02834ent IS
END c13s09b00x00p99n01i02834ent;
ARCHITECTURE c13s09b00x00p99n01i02834arch OF c13s09b00x00p99n01i02834ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02834 - Reserved word RETURN can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02834arch;
| gpl-2.0 |
drxzcl/neppielight | dvid_out/dvid_out_clocking.vhd | 2 | 4094 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Description: Generate clocking for sending TMDS data use the OSERDES2
--
-- REMEMBER TO CHECK CLKIN_PERIOD ON PLL_BASE
-- For pixel rates between 25Mhz and 50MHz use the following PLL settings:
-- CLKFBOUT_MULT => 20,
-- CLKOUT0_DIVIDE => 2, CLKOUT0_PHASE => 0.0, -- Output 10x original frequency
-- CLKOUT1_DIVIDE => 10, CLKOUT1_PHASE => 0.0, -- Output 2x original frequency
-- CLKOUT2_DIVIDE => 20, CLKOUT2_PHASE => 0.0, -- Output 1x original frequency
-- CLKIN_PERIOD => 20.0,
--
-- For pixel rates between 40Mhz and 100MHz use the following PLL settings:
-- CLKFBOUT_MULT => 10,
-- CLKOUT0_DIVIDE => 1, CLKOUT0_PHASE => 0.0, -- Output 10x original frequency
-- CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.0, -- Output 2x original frequency
-- CLKOUT2_DIVIDE => 10, CLKOUT2_PHASE => 0.0, -- Output 1x original frequency
-- CLKIN_PERIOD => 10.0,
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity dvid_out_clocking is
Port ( clk_pixel : in STD_LOGIC;
clk_x1 : out STD_LOGIC;
clk_x2 : out STD_LOGIC;
clk_x10 : out STD_LOGIC;
serdes_strobe : out STD_LOGIC);
end dvid_out_clocking;
architecture Behavioral of dvid_out_clocking is
signal clock_local_x1 : std_logic;
signal clock_local_x2 : std_logic;
signal clock_local_x10 : std_logic;
signal clock_x10_unbuffered : std_logic;
signal clock_x2_unbuffered : std_logic;
signal clock_x1_unbuffered : std_logic;
signal clk_feedback : std_logic;
signal clk50_buffered : std_logic;
signal pll_locked : std_logic;
begin
clk_x1 <= clock_local_x1;
clk_x2 <= clock_local_x2;
clk_x10 <= clock_local_x10;
-- Multiply clk50m by 10, then :
-- * divide by 1 for the bit clock (pixel clock x10)
-- * divide by 5 for the pixel clock x2
-- * divide by 10 for the pixel clock
-- Because the all come from the same PLL the will all be in phase
PLL_BASE_inst : PLL_BASE
generic map (
CLKFBOUT_MULT => 10,
CLKOUT0_DIVIDE => 1, CLKOUT0_PHASE => 0.0, -- Output 10x original frequency
CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.0, -- Output 2x original frequency
CLKOUT2_DIVIDE => 10, CLKOUT2_PHASE => 0.0, -- Output 1x original frequency
CLK_FEEDBACK => "CLKFBOUT",
CLKIN_PERIOD => 10.0,
DIVCLK_DIVIDE => 1
)
port map (
CLKFBOUT => clk_feedback,
CLKOUT0 => clock_x10_unbuffered,
CLKOUT1 => clock_x2_unbuffered,
CLKOUT2 => clock_x1_unbuffered,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => pll_locked,
CLKFBIN => clk_feedback,
CLKIN => clk_pixel,
RST => '0'
);
BUFG_pclockx2 : BUFG port map ( I => clock_x2_unbuffered, O => clock_local_x2);
BUFG_pclock : BUFG port map ( I => clock_x1_unbuffered, O => clock_local_x1);
BUFPLL_inst : BUFPLL
generic map (
DIVIDE => 5, -- DIVCLK divider (1-8) !!!! IMPORTANT TO CHANGE THIS AS NEEDED !!!!
ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) -- should be true
)
port map (
IOCLK => clock_local_x10, -- Clock used to send bits
LOCK => open,
SERDESSTROBE => serdes_strobe, -- Clock use to load data into SERDES
GCLK => clock_local_x2, -- Global clock use as a reference for serdes_strobe
LOCKED => pll_locked, -- When the upstream PLL is locked
PLLIN => clock_x10_unbuffered -- What clock to use - this must be unbuffered
);
end Behavioral; | gpl-2.0 |
mati75/ghdl | libraries/ieee/math_complex.vhdl | 4 | 40109 | ------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_COMPLEX)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common COMPLEX
-- constants and common COMPLEX mathematical functions and
-- operators.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_COMPLEX.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_COMPLEX package declaration. The purpose of the
-- MATH_COMPLEX package body is to provide a guideline for
-- implementations to verify their implementation of MATH_COMPLEX.
-- Tool developers may choose to implement the package body in
-- the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
use WORK.MATH_REAL.all;
package MATH_COMPLEX is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Type Definitions
--
type COMPLEX is
record
RE: REAL; -- Real part
IM: REAL; -- Imaginary part
end record;
subtype POSITIVE_REAL is REAL range 0.0 to REAL'HIGH;
subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI;
type COMPLEX_POLAR is
record
MAG: POSITIVE_REAL; -- Magnitude
ARG: PRINCIPAL_VALUE; -- Angle in radians; -MATH_PI is illegal
end record;
--
-- Constant Definitions
--
constant MATH_CBASE_1: COMPLEX := COMPLEX'(1.0, 0.0);
constant MATH_CBASE_J: COMPLEX := COMPLEX'(0.0, 1.0);
constant MATH_CZERO: COMPLEX := COMPLEX'(0.0, 0.0);
--
-- Overloaded equality and inequality operators for COMPLEX_POLAR
-- (equality and inequality operators for COMPLEX are predefined)
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN;
-- Purpose:
-- Returns TRUE if L is equal to R and returns FALSE otherwise
-- Special values:
-- COMPLEX_POLAR'(0.0, X) = COMPLEX_POLAR'(0.0, Y) returns TRUE
-- regardless of the value of X and Y.
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- "="(L,R) is either TRUE or FALSE
-- Notes:
-- None
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN;
-- Purpose:
-- Returns TRUE if L is not equal to R and returns FALSE
-- otherwise
-- Special values:
-- COMPLEX_POLAR'(0.0, X) /= COMPLEX_POLAR'(0.0, Y) returns
-- FALSE regardless of the value of X and Y.
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- "/="(L,R) is either TRUE or FALSE
-- Notes:
-- None
--
-- Function Declarations
--
function CMPLX(X: in REAL; Y: in REAL:= 0.0 ) return COMPLEX;
-- Purpose:
-- Returns COMPLEX number X + iY
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- CMPLX(X,Y) is mathematically unbounded
-- Notes:
-- None
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns principal value of angle X; X in radians
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- -MATH_PI < GET_PRINCIPAL_VALUE(X) <= MATH_PI
-- Notes:
-- None
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value COMPLEX_POLAR of Z
-- Special values:
-- COMPLEX_TO_POLAR(MATH_CZERO) = COMPLEX_POLAR'(0.0, 0.0)
-- COMPLEX_TO_POLAR(Z) = COMPLEX_POLAR'(ABS(Z.IM),
-- SIGN(Z.IM)*MATH_PI_OVER_2) if Z.RE = 0.0
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX;
-- Purpose:
-- Returns COMPLEX value of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- POLAR_TO_COMPLEX(Z) is mathematically unbounded
-- Notes:
-- None
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL;
-- Purpose:
-- Returns absolute value (magnitude) of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(Z) is mathematically unbounded
-- Notes:
-- ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL;
-- Purpose:
-- Returns absolute value (magnitude) of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- ABS(Z) >= 0.0
-- Notes:
-- ABS(Z) = Z.MAG
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns argument (angle) in radians of the principal
-- value of Z
-- Special values:
-- ARG(Z) = 0.0 if Z.RE >= 0.0 and Z.IM = 0.0
-- ARG(Z) = SIGN(Z.IM)*MATH_PI_OVER_2 if Z.RE = 0.0
-- ARG(Z) = MATH_PI if Z.RE < 0.0 and Z.IM = 0.0
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- -MATH_PI < ARG(Z) <= MATH_PI
-- Notes:
-- ARG(Z) = ARCTAN(Z.IM, Z.RE)
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns argument (angle) in radians of the principal
-- value of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- -MATH_PI < ARG(Z) <= MATH_PI
-- Notes:
-- ARG(Z) = Z.ARG
function "-" (Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns unary minus of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- Returns -x -jy for Z= x + jy
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of unary minus of Z
-- Special values:
-- "-"(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- Returns COMPLEX_POLAR'(Z.MAG, Z.ARG - SIGN(Z.ARG)*MATH_PI) if
-- Z.ARG /= 0.0
function CONJ (Z: in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns complex conjugate of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- CONJ(Z) is mathematically unbounded
-- Notes:
-- Returns x -jy for Z= x + jy
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of complex conjugate of Z
-- Special values:
-- CONJ(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = MATH_PI
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- Returns COMPLEX_POLAR'(Z.MAG, -Z.ARG) if Z.ARG /= MATH_PI
function SQRT(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns square root of Z with positive real part
-- or, if the real part is zero, the one with nonnegative
-- imaginary part
-- Special values:
-- SQRT(MATH_CZERO) = MATH_CZERO
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- SQRT(Z) is mathematically unbounded
-- Notes:
-- None
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns square root of Z with positive real part
-- or, if the real part is zero, the one with nonnegative
-- imaginary part
-- Special values:
-- SQRT(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function EXP(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns exponential of Z
-- Special values:
-- EXP(MATH_CZERO) = MATH_CBASE_1
-- EXP(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and ABS(Z.IM) = MATH_PI
-- EXP(Z) = SIGN(Z.IM)*MATH_CBASE_J if Z.RE = 0.0 and
-- ABS(Z.IM) = MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- EXP(Z) is mathematically unbounded
-- Notes:
-- None
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of exponential of Z
-- Special values:
-- EXP(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG =0.0 and
-- Z.ARG = 0.0
-- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and
-- ABS(Z.ARG) = MATH_PI_OVER_2
-- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if
-- Z.MAG = MATH_PI_OVER_2 and
-- Z.ARG = MATH_PI_OVER_2
-- EXP(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if
-- Z.MAG = MATH_PI_OVER_2 and
-- Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns natural logarithm of Z
-- Special values:
-- LOG(MATH_CBASE_1) = MATH_CZERO
-- LOG(-MATH_CBASE_1) = COMPLEX'(0.0, MATH_PI)
-- LOG(MATH_CBASE_J) = COMPLEX'(0.0, MATH_PI_OVER_2)
-- LOG(-MATH_CBASE_J) = COMPLEX'(0.0, -MATH_PI_OVER_2)
-- LOG(Z) = MATH_CBASE_1 if Z = COMPLEX'(MATH_E, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG(Z) is mathematically unbounded
-- Notes:
-- None
function LOG2(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns logarithm base 2 of Z
-- Special values:
-- LOG2(MATH_CBASE_1) = MATH_CZERO
-- LOG2(Z) = MATH_CBASE_1 if Z = COMPLEX'(2.0, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG2(Z) is mathematically unbounded
-- Notes:
-- None
function LOG10(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns logarithm base 10 of Z
-- Special values:
-- LOG10(MATH_CBASE_1) = MATH_CZERO
-- LOG10(Z) = MATH_CBASE_1 if Z = COMPLEX'(10.0, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG10(Z) is mathematically unbounded
-- Notes:
-- None
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of natural logarithm of Z
-- Special values:
-- LOG(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = MATH_PI
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = MATH_PI_OVER_2
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = -MATH_PI_OVER_2
-- LOG(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = MATH_E and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base 2 of Z
-- Special values:
-- LOG2(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG2(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 2.0 and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base 10 of Z
-- Special values:
-- LOG10(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG10(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 10.0 and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG(Z: in COMPLEX; BASE: in REAL) return COMPLEX;
-- Purpose:
-- Returns logarithm base BASE of Z
-- Special values:
-- LOG(MATH_CBASE_1, BASE) = MATH_CZERO
-- LOG(Z,BASE) = MATH_CBASE_1 if Z = COMPLEX'(BASE, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(Z,BASE) is mathematically unbounded
-- Notes:
-- None
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base BASE of Z
-- Special values:
-- LOG(Z, BASE) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG(Z, BASE) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = BASE and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function SIN (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns sine of Z
-- Special values:
-- SIN(MATH_CZERO) = MATH_CZERO
-- SIN(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI, 0.0)
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(Z)) <= SQRT(SIN(Z.RE)*SIN(Z.RE) +
-- SINH(Z.IM)*SINH(Z.IM))
-- Notes:
-- None
function SIN (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of sine of Z
-- Special values:
-- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function COS (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns cosine of Z
-- Special values:
-- COS(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI_OVER_2, 0.0)
-- COS(Z) = MATH_CZERO if Z = COMPLEX'(-MATH_PI_OVER_2, 0.0)
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(COS(Z)) <= SQRT(COS(Z.RE)*COS(Z.RE) +
-- SINH(Z.IM)*SINH(Z.IM))
-- Notes:
-- None
function COS (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of cosine of Z
-- Special values:
-- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2
-- and Z.ARG = 0.0
-- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2
-- and Z.ARG = MATH_PI
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function SINH (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns hyperbolic sine of Z
-- Special values:
-- SINH(MATH_CZERO) = MATH_CZERO
-- SINH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI
-- SINH(Z) = MATH_CBASE_J if Z.RE = 0.0 and
-- Z.IM = MATH_PI_OVER_2
-- SINH(Z) = -MATH_CBASE_J if Z.RE = 0.0 and
-- Z.IM = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(SINH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) +
-- SIN(Z.IM)*SIN(Z.IM))
-- Notes:
-- None
function SINH (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of hyperbolic sine of Z
-- Special values:
-- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and
-- Z.ARG = MATH_PI_OVER_2
-- SINH(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2
-- SINH(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function COSH (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns hyperbolic cosine of Z
-- Special values:
-- COSH(MATH_CZERO) = MATH_CBASE_1
-- COSH(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and Z.IM = MATH_PI
-- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI_OVER_2
-- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(COSH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) +
-- COS(Z.IM)*COS(Z.IM))
-- Notes:
-- None
function COSH (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of hyperbolic cosine of Z
-- Special values:
-- COSH(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- COSH(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and
-- Z.ARG = MATH_PI_OVER_2
-- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2
-- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX and R /= MATH_CZERO
-- Error conditions:
-- Error if R = MATH_CZERO
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX and R /= MATH_CZERO
-- Error conditions:
-- Error if R = MATH_CZERO
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL and R /= 0.0
-- Error conditions:
-- Error if R = 0.0
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- R.MAG > 0.0
-- Error conditions:
-- Error if R.MAG <= 0.0
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- R.MAG > 0.0
-- Error conditions:
-- Error if R.MAG <= 0.0
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R /= 0.0
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
end MATH_COMPLEX;
| gpl-2.0 |
drxzcl/neppielight | dvid_out/output_serialiser.vhd | 2 | 5345 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: output_serialiser - Behavioral
-- Description: A 5-bit SDR output serialiser
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity output_serialiser is
Port ( clk_load : in STD_LOGIC;
clk_output : in STD_LOGIC;
strobe : in STD_LOGIC;
ser_data : in STD_LOGIC_VECTOR (4 downto 0);
ser_output : out STD_LOGIC);
end output_serialiser;
architecture Behavioral of output_serialiser is
signal clk0, clk1, clkdiv : std_logic;
signal cascade1, cascade2, cascade3, cascade4 : std_logic;
begin
clkdiv <= clk_load;
clk0 <= clk_output;
clk1 <= '0';
OSERDES2_master : OSERDES2
generic map (
BYPASS_GCLK_FF => FALSE, -- Bypass CLKDIV syncronization registers (TRUE/FALSE)
DATA_RATE_OQ => "SDR", -- Output Data Rate ("SDR" or "DDR")
DATA_RATE_OT => "SDR", -- 3-state Data Rate ("SDR" or "DDR")
DATA_WIDTH => 5, -- Parallel data width (2-8)
OUTPUT_MODE => "SINGLE_ENDED", -- "SINGLE_ENDED" or "DIFFERENTIAL"
SERDES_MODE => "MASTER", -- "NONE", "MASTER" or "SLAVE"
TRAIN_PATTERN => 0 -- Training Pattern (0-15)
) port map (
OQ => ser_output, -- 1-bit output: Data output to pad or IODELAY2
SHIFTOUT1 => cascade1, -- 1-bit output: Cascade data output
SHIFTOUT2 => cascade2, -- 1-bit output: Cascade 3-state output
SHIFTOUT3 => open, -- 1-bit output: Cascade differential data output
SHIFTOUT4 => open, -- 1-bit output: Cascade differential 3-state output
SHIFTIN1 => '1', -- 1-bit input: Cascade data input
SHIFTIN2 => '1', -- 1-bit input: Cascade 3-state input
SHIFTIN3 => cascade3, -- 1-bit input: Cascade differential data input
SHIFTIN4 => cascade4, -- 1-bit input: Cascade differential 3-state input
TQ => open, -- 1-bit output: 3-state output to pad or IODELAY2
CLK0 => CLK0, -- 1-bit input: I/O clock input
CLK1 => CLK1, -- 1-bit input: Secondary I/O clock input
CLKDIV => CLKDIV, -- 1-bit input: Logic domain clock input
-- D1 - D4: 1-bit (each) input: Parallel data inputs
D1 => ser_data(4),
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => strobe, -- 1-bit input: Data strobe input
OCE => '1', -- 1-bit input: Clock enable input
RST => '0', -- 1-bit input: Asynchrnous reset input
-- T1 - T4: 1-bit (each) input: 3-state control inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1', -- 1-bit input: 3-state clock enable input
TRAIN => '0' -- 1-bit input: Training pattern enable input
);
OSERDES2_slave : OSERDES2
generic map (
BYPASS_GCLK_FF => FALSE, -- Bypass CLKDIV syncronization registers (TRUE/FALSE)
DATA_RATE_OQ => "SDR", -- Output Data Rate ("SDR" or "DDR")
DATA_RATE_OT => "SDR", -- 3-state Data Rate ("SDR" or "DDR")
DATA_WIDTH => 5, -- Parallel data width (2-8)
OUTPUT_MODE => "SINGLE_ENDED", -- "SINGLE_ENDED" or "DIFFERENTIAL"
SERDES_MODE => "SLAVE", -- "NONE", "MASTER" or "SLAVE"
TRAIN_PATTERN => 0 -- Training Pattern (0-15)
) port map (
OQ => open, -- 1-bit output: Data output to pad or IODELAY2
SHIFTOUT1 => open, -- 1-bit output: Cascade data output
SHIFTOUT2 => open, -- 1-bit output: Cascade 3-state output
SHIFTOUT3 => cascade3, -- 1-bit output: Cascade differential data output
SHIFTOUT4 => cascade4, -- 1-bit output: Cascade differential 3-state output
SHIFTIN1 => cascade1, -- 1-bit input: Cascade data input
SHIFTIN2 => cascade2, -- 1-bit input: Cascade 3-state input
SHIFTIN3 => '1', -- 1-bit input: Cascade differential data input
SHIFTIN4 => '1', -- 1-bit input: Cascade differential 3-state input
TQ => open, -- 1-bit output: 3-state output to pad or IODELAY2
CLK0 => CLK0, -- 1-bit input: I/O clock input
CLK1 => CLK1, -- 1-bit input: Secondary I/O clock input
CLKDIV => CLKDIV, -- 1-bit input: Logic domain clock input
-- D1 - D4: 1-bit (each) input: Parallel data inputs
D1 => ser_data(0),
D2 => ser_data(1),
D3 => ser_data(2),
D4 => ser_data(3),
IOCE => strobe, -- 1-bit input: Data strobe input
OCE => '1', -- 1-bit input: Clock enable input
RST => '0', -- 1-bit input: Asynchrnous reset input
-- T1 - T4: 1-bit (each) input: 3-state control inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1', -- 1-bit input: 3-state clock enable input
TRAIN => '0' -- 1-bit input: Training pattern enable input
);
end Behavioral;
| gpl-2.0 |
mati75/ghdl | libraries/vital2000/prmtvs_p.vhdl | 7 | 68530 | -- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
| gpl-2.0 |
mati75/ghdl | libraries/ieee2008/fixed_float_types.vhdl | 4 | 2686 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Fixed Point and Floating Point types package
--
-- Library : This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
--
-- Purpose : Definitions for use in fixed point and floating point
-- arithmetic packages
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package fixed_float_types is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package fixed_float_types;
| gpl-2.0 |
mati75/ghdl | libraries/ieee2008/std_logic_1164-body.vhdl | 4 | 57352 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body std_logic_1164 is
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
type stdlogic_1d is array (STD_ULOGIC) of STD_ULOGIC;
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
constant resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 |
('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z |
('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W |
('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L |
('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := 'Z'; -- weakest state default
begin
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
if (s'length = 1) then return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
constant and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- | U |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | X |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 1 |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | Z |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | W |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | H |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X') -- | - |
);
-- truth table for "or" function
constant or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U'), -- | U |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | Z |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | H |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X') -- | - |
);
-- truth table for "xor" function
constant xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- truth table for "not" function
constant not_table : stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X');
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (and_table(l, r));
end function "and";
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (and_table(l, r)));
end function "nand";
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (or_table(l, r));
end function "or";
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (or_table(l, r)));
end function "nor";
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (xor_table(l, r));
end function "xor";
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return ux01 is
begin
return not_table(xor_table(l, r));
end function "xnor";
function "not" (l : STD_ULOGIC) return UX01 is
begin
return (not_table(l));
end function "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := and_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(and_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := or_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(or_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := xor_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(xor_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "xnor";
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => 'X');
begin
for i in result'range loop
result(i) := not_table(lv(i));
end loop;
return result;
end function "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := and_table (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := and_table (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(and_table (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(and_table (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := or_table (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := or_table (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(or_table (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(or_table (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := xor_table (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := xor_table (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(xor_table (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(xor_table (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := and_table (l(i), result);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := and_table (l(i), result);
end loop;
return not_table(result);
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := or_table (l(i), result);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := or_table (l(i), result);
end loop;
return not_table(result);
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := xor_table (l(i), result);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := xor_table (l(i), result);
end loop;
return not_table(result);
end function "xnor";
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
type logic_x01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01;
type logic_x01z_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01Z;
type logic_ux01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT is
begin
case s is
when '0' | 'L' => return ('0');
when '1' | 'H' => return ('1');
when others => return xmap;
end case;
end function To_bit;
--------------------------------------------------------------------
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0')
return BIT_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : BIT_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
case sv(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := xmap;
end case;
end loop;
return result;
end function To_bitvector;
--------------------------------------------------------------------
function To_StdULogic (b : BIT) return STD_ULOGIC is
begin
case b is
when '0' => return '0';
when '1' => return '1';
end case;
end function To_StdULogic;
--------------------------------------------------------------------
function To_StdLogicVector (b : BIT_VECTOR)
return STD_LOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_LOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_StdLogicVector;
--------------------------------------------------------------------
function To_StdLogicVector (s : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_LOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end function To_StdLogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (b : BIT_VECTOR)
return STD_ULOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_ULOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_StdULogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (s : STD_LOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_ULOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end function To_StdULogicVector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR
is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0') return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR
is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0') return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01 (sv(i));
end loop;
return result;
end function To_X01;
--------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC) return X01 is
begin
return (cvt_to_x01(s));
end function To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT) return X01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_X01;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01z (sv(i));
end loop;
return result;
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC) return X01Z is
begin
return (cvt_to_x01z(s));
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT) return X01Z is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_X01Z;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_ux01 (sv(i));
end loop;
return result;
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC) return UX01 is
begin
return (cvt_to_ux01(s));
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT) return UX01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN is
begin
return l = '1' or l = 'H';
end function "??";
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '1') and
(To_X01(s'last_value) = '0'));
end function rising_edge;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '0') and
(To_X01(s'last_value) = '1'));
end function falling_edge;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
for i in s'range loop
case s(i) is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
end loop;
return false;
end function Is_X;
--------------------------------------------------------------------
function Is_X (s : STD_ULOGIC) return BOOLEAN is
begin
case s is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
return false;
end function Is_X;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant result_length : NATURAL := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(1 to result_length*3 - value'length);
variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*3);
variable result : STRING(1 to result_length);
variable tri : STD_ULOGIC_VECTOR(1 to 3);
begin
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
padded_value := pad & value;
for i in 1 to result_length loop
tri := To_X01Z(padded_value(3*i-2 to 3*i));
case tri is
when o"0" => result(i) := '0';
when o"1" => result(i) := '1';
when o"2" => result(i) := '2';
when o"3" => result(i) := '3';
when o"4" => result(i) := '4';
when o"5" => result(i) := '5';
when o"6" => result(i) := '6';
when o"7" => result(i) := '7';
when "ZZZ" => result(i) := 'Z';
when others => result(i) := 'X';
end case;
end loop;
return result;
end function to_ostring;
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant result_length : NATURAL := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(1 to result_length*4 - value'length);
variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*4);
variable result : STRING(1 to result_length);
variable quad : STD_ULOGIC_VECTOR(1 to 4);
begin
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
padded_value := pad & value;
for i in 1 to result_length loop
quad := To_X01Z(padded_value(4*i-3 to 4*i));
case quad is
when x"0" => result(i) := '0';
when x"1" => result(i) := '1';
when x"2" => result(i) := '2';
when x"3" => result(i) := '3';
when x"4" => result(i) := '4';
when x"5" => result(i) := '5';
when x"6" => result(i) := '6';
when x"7" => result(i) := '7';
when x"8" => result(i) := '8';
when x"9" => result(i) := '9';
when x"A" => result(i) := 'A';
when x"B" => result(i) := 'B';
when x"C" => result(i) := 'C';
when x"D" => result(i) := 'D';
when x"E" => result(i) := 'E';
when x"F" => result(i) := 'F';
when "ZZZZ" => result(i) := 'Z';
when others => result(i) := 'X';
end case;
end loop;
return result;
end function to_hstring;
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
c := l (l'left);
if c = ' ' or c = NBSP or c = HT then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := true;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then
good := false; -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
alias m : STD_ULOGIC_VECTOR(1 to VALUE'length) is VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
procedure Char2TriBits (C : in CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
end package body std_logic_1164;
| gpl-2.0 |
mati75/ghdl | libraries/std/env.vhdl | 5 | 1071 | -- Std.Env package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2014 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING. If not, write to the Free
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
package Env is
procedure Stop (Status : Integer);
procedure Stop;
procedure Finish (status : Integer);
procedure Finish;
function Resolution_Limit return Delay_Length;
end package Env;
| gpl-2.0 |
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