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emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1349.vhd | 4 | 6500 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1349.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p10n01i01349ent IS
END c08s04b01x00p10n01i01349ent;
ARCHITECTURE c08s04b01x00p10n01i01349arch OF c08s04b01x00p10n01i01349ent IS
-- Local signals.
signal S : BIT := '0';
BEGIN
TESTING: PROCESS
-- local variables.
variable S_INITIAL : BIT;
variable ShouldBeTime : TIME;
variable k : integer := 0;
BEGIN
-- 0. Keep around the initial value of S.
S_INITIAL := S;
-- 1. When no preemption necessary, verify the results. INERTIAL SAME AS TRANSPORT.
S <= (not S) after 10 ns, (S) after 20 ns;
-- a. Wait for first transaction.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Wait for second transaction.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- 2. Preempt a transaction which is to occur at the same time as second one.
-- INERTIAL SAME AS TRANSPORT.
S_INITIAL := S;
S <= (S) after 10 ns;
S <= (not S) after 10 ns; -- Should preempt first transaction.
-- a. Verify that the second transaction comes as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Verify that the first transaction has been preempted.
ShouldBeTime := NOW + 10 ns;
wait on S for 10 ns;
if (ShouldBeTime /= now ) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 3. Preempt a transaction which is to occur at a later time than second one.
-- INERTIAL SAME AS TRANSPORT.
S_INITIAL := S;
S <= (S) after 15 ns;
S <= (not S) after 10 ns; -- Should preempt first transaction.
-- a. Verify that the second transaction comes as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Verify that the first transaction has been preempted.
ShouldBeTime := NOW + 10 ns;
wait on S for 10 ns;
if (ShouldBeTime /= now ) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 4. Preempt multiple transactions. INERTIAL SAME AS TRANSPORT.
S_INITIAL := S;
S <= (S) after 15 ns, (not S) after 30 ns;
S <= (not S) after 10 ns, (S) after 20 ns;
-- a. Verify that the second transactions come as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- b. Verify that the first transactions have been preempted.
ShouldBeTime := NOW + 40 ns;
wait on S for 40 ns;
if (ShouldBeTime /= now ) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 5. Preempt transactions which occur before the second inertial assignment.
S_INITIAL := S;
S <= (S) after 5 ns;
S <= (not S) after 10 ns, (S) after 20 ns;
-- a. Verify that the second transactions come as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- b. Verify that the first transactions have been preempted.
ShouldBeTime := NOW + 40 ns;
wait on S for 40 ns;
if (ShouldBeTime /= now ) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 6. Don't preempt transactions which occur before the second inertial assignment.
S_INITIAL := S;
S <= (not S) after 5 ns;
S <= (not S) after 10 ns, (S) after 20 ns;
-- a. Verify that the first transaction was NOT preempted.
ShouldBeTime := NOW + 5 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
ShouldBeTime := NOW + 15 ns;
wait on S;
if (ShouldBeTime /= now and S /= S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- b. Verify that there are no more transactions.
ShouldBeTime := NOW + 40 ns;
wait on S for 40 ns;
if (ShouldBeTime /= now ) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert NOT( k=0 )
report "***PASSED TEST: c08s04b01x00p10n01i01349"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s04b01x00p10n01i01349 - Interial signal assignment test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p10n01i01349arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1884.vhd | 4 | 1934 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1884.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01884ent IS
END c07s01b00x00p08n01i01884ent;
ARCHITECTURE c07s01b00x00p08n01i01884arch OF c07s01b00x00p08n01i01884ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal s_int : small_int;
signal obus : cmd_bus(small_int);
BEGIN
blk : block (s_int = 0)
begin
end block blk;
TESTING : PROCESS
BEGIN
obus <= (0 => blk, others => 5) after 5 ns; -- block label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01884 - Block labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01884arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1334.vhd | 4 | 1618 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1334.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n03i01334ent IS
END c08s04b01x00p04n03i01334ent;
ARCHITECTURE c08s04b01x00p04n03i01334arch OF c08s04b01x00p04n03i01334ent IS
signal S : Bit;
BEGIN
TESTING: PROCESS
BEGIN
S <= '0' after -5 ns;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p04n03i01334 - Time expression must be positive"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n03i01334arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_standard/simple-now-test.vhdl | 4 | 344 | entity test is
end test;
architecture only of test is
begin -- only
p: process
begin -- process p
wait for 1 ns;
assert now = 1 ns report "TEST FAILED" severity FAILURE;
wait for 10 ns;
assert now = 11 ns report "TEST FAILED" severity FAILURE;
report "PASSED TEST" severity NOTE;
wait;
end process p;
end only;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1210.vhd | 4 | 1796 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1210.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p25n01i01210ent IS
END c08s01b00x00p25n01i01210ent;
ARCHITECTURE c08s01b00x00p25n01i01210arch OF c08s01b00x00p25n01i01210ent IS
signal T1 : BIT := '0';
BEGIN
TESTING: PROCESS
BEGIN
T1 <= '1' after 15 ns;
wait on T1 until (T1 = '1');
assert NOT( T1 = '1' )
report "***PASSED TEST: c08s01b00x00p25n01i01210"
severity NOTE;
assert ( T1 = '1' )
report "***FAILED TEST: c08s01b00x00p25n01i01210 - Process resumes execution when the condition clause in a wait statement is met"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p25n01i01210arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2273.vhd | 4 | 1799 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2273.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02273ent IS
END c07s02b06x00p14n01i02273ent;
ARCHITECTURE c07s02b06x00p14n01i02273arch OF c07s02b06x00p14n01i02273ent IS
BEGIN
TESTING: PROCESS
variable T : TIME := 1 sec;
BEGIN
T := T * 10 sec; -- Failure_here
-- SEMANTIC ERROR: if one operand is physical, then the other must
-- an integer or floating point type.
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02273 - If one operand is of type physical, the other has to be of type integer or real."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02273arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd | 4 | 1228 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
port ( terminal node1, node2 : electrical );
end entity capacitor;
architecture leakage of capacitor is
constant c : real := 1.0E-6;
constant r_leak : real := 10.0E6;
quantity v_cap across i_cap, i_leak through node1 to node2;
begin
i_cap == c * v_cap'dot;
i_leak == v_cap / r_leak;
end architecture leakage;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/fsm_23.vhd | 2 | 115488 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_23 is
port (
clock : in std_logic;
reset : in std_logic;
in0 : in std_logic;
out181 : out std_logic;
out182 : out std_logic;
out183 : out std_logic;
out184 : out std_logic;
out185 : out std_logic;
out8 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out16 : out std_logic;
out18 : out std_logic;
out19 : out std_logic;
out20 : out std_logic;
out21 : out std_logic;
out22 : out std_logic;
in2 : in std_logic;
out23 : out std_logic;
out24 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
out27 : out std_logic;
out28 : out std_logic;
out29 : out std_logic;
out30 : out std_logic;
out31 : out std_logic;
out33 : out std_logic;
out35 : out std_logic;
out36 : out std_logic;
out38 : out std_logic;
out40 : out std_logic;
out42 : out std_logic;
in3 : in std_logic;
out44 : out std_logic;
out46 : out std_logic;
out48 : out std_logic;
out49 : out std_logic;
out50 : out std_logic;
out52 : out std_logic;
out54 : out std_logic;
out56 : out std_logic;
out57 : out std_logic;
out58 : out std_logic;
in4 : in std_logic;
out60 : out std_logic;
in5 : in std_logic;
out164 : out std_logic;
out165 : out std_logic;
out167 : out std_logic;
out168 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out174 : out std_logic;
out176 : out std_logic;
out178 : out std_logic;
out0 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
in1 : in std_logic;
out4 : out std_logic;
out90 : out std_logic;
out91 : out std_logic;
out97 : out std_logic;
out99 : out std_logic;
out101 : out std_logic;
in6 : in std_logic;
out103 : out std_logic;
out105 : out std_logic;
out106 : out std_logic;
out107 : out std_logic;
out108 : out std_logic;
out135 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
out138 : out std_logic;
in11 : in std_logic;
out140 : out std_logic;
out141 : out std_logic;
out142 : out std_logic;
out143 : out std_logic;
out145 : out std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out153 : out std_logic;
out154 : out std_logic;
out155 : out std_logic;
out156 : out std_logic;
out157 : out std_logic;
out158 : out std_logic;
out159 : out std_logic;
out160 : out std_logic;
out161 : out std_logic;
out162 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
out116 : out std_logic;
out118 : out std_logic;
out120 : out std_logic;
out121 : out std_logic;
out122 : out std_logic;
out123 : out std_logic;
out124 : out std_logic;
out125 : out std_logic;
out126 : out std_logic;
in7 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
in8 : in std_logic;
out131 : out std_logic;
in9 : in std_logic;
out132 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
in10 : in std_logic;
out186 : out std_logic;
out187 : out std_logic;
out190 : out std_logic;
out195 : out std_logic;
out197 : out std_logic;
out198 : out std_logic;
out199 : out std_logic;
out200 : out std_logic;
out201 : out std_logic;
out203 : out std_logic;
out204 : out std_logic;
out206 : out std_logic;
out207 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
out215 : out std_logic;
out217 : out std_logic;
out220 : out std_logic;
out221 : out std_logic;
out222 : out std_logic;
out223 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out226 : out std_logic;
out227 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out231 : out std_logic;
out232 : out std_logic;
out234 : out std_logic;
out235 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out243 : out std_logic;
out245 : out std_logic;
out248 : out std_logic;
out249 : out std_logic;
out250 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out254 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out257 : out std_logic;
out259 : out std_logic;
out260 : out std_logic;
out262 : out std_logic;
out263 : out std_logic;
out265 : out std_logic;
out266 : out std_logic;
out268 : out std_logic;
out269 : out std_logic;
out271 : out std_logic;
out273 : out std_logic;
out276 : out std_logic;
out277 : out std_logic;
out278 : out std_logic;
out279 : out std_logic;
out280 : out std_logic;
out281 : out std_logic;
out282 : out std_logic;
out283 : out std_logic;
out284 : out std_logic;
out285 : out std_logic;
out286 : out std_logic;
out287 : out std_logic;
out288 : out std_logic;
out289 : out std_logic;
out290 : out std_logic;
out291 : out std_logic;
out292 : out std_logic;
out293 : out std_logic;
out294 : out std_logic;
out295 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out298 : out std_logic;
out311 : out std_logic;
out312 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
out315 : out std_logic;
out316 : out std_logic;
out318 : out std_logic;
out321 : out std_logic;
out322 : out std_logic;
out323 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out327 : out std_logic;
out328 : out std_logic;
out329 : out std_logic;
out333 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out343 : out std_logic;
out344 : out std_logic;
out345 : out std_logic;
out346 : out std_logic;
out349 : out std_logic;
out350 : out std_logic;
out351 : out std_logic;
out352 : out std_logic;
out353 : out std_logic;
out354 : out std_logic;
out355 : out std_logic;
out357 : out std_logic;
out361 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out366 : out std_logic;
out367 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out382 : out std_logic;
out383 : out std_logic;
out385 : out std_logic;
out393 : out std_logic;
out394 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out398 : out std_logic;
out400 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out404 : out std_logic;
out406 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
out411 : out std_logic;
out412 : out std_logic;
out413 : out std_logic;
out414 : out std_logic;
out416 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out422 : out std_logic;
out423 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
out428 : out std_logic;
out429 : out std_logic;
out430 : out std_logic;
out431 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out435 : out std_logic;
out436 : out std_logic;
out437 : out std_logic;
out438 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
out443 : out std_logic;
out444 : out std_logic;
out445 : out std_logic;
out446 : out std_logic;
out447 : out std_logic;
out450 : out std_logic;
out451 : out std_logic;
out454 : out std_logic;
out455 : out std_logic;
out457 : out std_logic;
out458 : out std_logic;
out459 : out std_logic;
out460 : out std_logic;
out461 : out std_logic;
out462 : out std_logic;
out463 : out std_logic;
out464 : out std_logic;
out465 : out std_logic;
out466 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out469 : out std_logic;
out472 : out std_logic;
out475 : out std_logic;
out481 : out std_logic;
out482 : out std_logic;
out483 : out std_logic;
out484 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
out491 : out std_logic;
out495 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out499 : out std_logic;
out500 : out std_logic;
out501 : out std_logic;
out512 : out std_logic;
out513 : out std_logic;
out517 : out std_logic;
out518 : out std_logic;
out519 : out std_logic;
out521 : out std_logic;
out522 : out std_logic;
out524 : out std_logic;
out525 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out531 : out std_logic;
out540 : out std_logic;
out542 : out std_logic;
out544 : out std_logic;
out545 : out std_logic;
out554 : out std_logic;
out555 : out std_logic;
out559 : out std_logic;
out560 : out std_logic;
out561 : out std_logic;
out562 : out std_logic;
out563 : out std_logic;
out566 : out std_logic;
out567 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
out578 : out std_logic;
out580 : out std_logic;
out581 : out std_logic
);
end fsm_23;
architecture augh of fsm_23 is
signal state_cur : std_logic_vector(0 to 240) := (7 => '1', others => '0');
signal state_next : std_logic_vector(0 to 240) := (7 => '1', others => '0');
-- Buffers for outputs
signal out122_buf : std_logic := '0';
signal out122_bufn : std_logic;
signal out36_buf : std_logic := '0';
signal out36_bufn : std_logic;
signal out49_buf : std_logic := '0';
signal out49_bufn : std_logic;
signal out35_buf : std_logic := '0';
signal out35_bufn : std_logic;
signal out27_buf : std_logic := '0';
signal out27_bufn : std_logic;
signal out16_buf : std_logic := '0';
signal out16_bufn : std_logic;
signal out25_buf : std_logic := '0';
signal out25_bufn : std_logic;
signal out20_buf : std_logic := '0';
signal out20_bufn : std_logic;
signal out57_buf : std_logic := '0';
signal out57_bufn : std_logic;
signal out23_buf : std_logic := '0';
signal out23_bufn : std_logic;
signal out136_buf : std_logic := '0';
signal out136_bufn : std_logic;
signal out0_buf : std_logic := '0';
signal out0_bufn : std_logic;
signal out134_buf : std_logic := '0';
signal out134_bufn : std_logic;
signal out13_buf : std_logic := '0';
signal out13_bufn : std_logic;
signal out131_buf : std_logic := '0';
signal out131_bufn : std_logic;
signal out129_buf : std_logic := '0';
signal out129_bufn : std_logic;
signal out111_buf : std_logic := '0';
signal out111_bufn : std_logic;
signal out31_buf : std_logic := '0';
signal out31_bufn : std_logic;
signal out126_buf : std_logic := '0';
signal out126_bufn : std_logic;
signal out106_buf : std_logic := '0';
signal out106_bufn : std_logic;
signal out124_buf : std_logic := '0';
signal out124_bufn : std_logic;
signal out138_buf : std_logic := '0';
signal out138_bufn : std_logic;
signal out141_buf : std_logic := '0';
signal out141_bufn : std_logic;
signal out143_buf : std_logic := '0';
signal out143_bufn : std_logic;
signal out146_buf : std_logic := '0';
signal out146_bufn : std_logic;
signal out150_buf : std_logic := '0';
signal out150_bufn : std_logic;
signal out153_buf : std_logic := '0';
signal out153_bufn : std_logic;
signal out155_buf : std_logic := '0';
signal out155_bufn : std_logic;
signal out158_buf : std_logic := '0';
signal out158_bufn : std_logic;
signal out162_buf : std_logic := '0';
signal out162_bufn : std_logic;
signal out165_buf : std_logic := '0';
signal out165_bufn : std_logic;
signal out168_buf : std_logic := '0';
signal out168_bufn : std_logic;
signal out171_buf : std_logic := '0';
signal out171_bufn : std_logic;
signal out174_buf : std_logic := '0';
signal out174_bufn : std_logic;
signal out178_buf : std_logic := '0';
signal out178_bufn : std_logic;
signal out181_buf : std_logic := '0';
signal out181_bufn : std_logic;
signal out183_buf : std_logic := '0';
signal out183_bufn : std_logic;
signal out197_buf : std_logic := '0';
signal out197_bufn : std_logic;
signal out201_buf : std_logic := '0';
signal out201_bufn : std_logic;
signal out204_buf : std_logic := '0';
signal out204_bufn : std_logic;
signal out207_buf : std_logic := '0';
signal out207_bufn : std_logic;
signal out210_buf : std_logic := '0';
signal out210_bufn : std_logic;
signal out213_buf : std_logic := '0';
signal out213_bufn : std_logic;
signal out217_buf : std_logic := '0';
signal out217_bufn : std_logic;
signal out220_buf : std_logic := '0';
signal out220_bufn : std_logic;
signal out222_buf : std_logic := '0';
signal out222_bufn : std_logic;
signal out225_buf : std_logic := '0';
signal out225_bufn : std_logic;
signal out229_buf : std_logic := '0';
signal out229_bufn : std_logic;
signal out232_buf : std_logic := '0';
signal out232_bufn : std_logic;
signal out235_buf : std_logic := '0';
signal out235_bufn : std_logic;
signal out238_buf : std_logic := '0';
signal out238_bufn : std_logic;
signal out241_buf : std_logic := '0';
signal out241_bufn : std_logic;
signal out245_buf : std_logic := '0';
signal out245_bufn : std_logic;
signal out248_buf : std_logic := '0';
signal out248_bufn : std_logic;
signal out250_buf : std_logic := '0';
signal out250_bufn : std_logic;
signal out253_buf : std_logic := '0';
signal out253_bufn : std_logic;
signal out257_buf : std_logic := '0';
signal out257_bufn : std_logic;
signal out260_buf : std_logic := '0';
signal out260_bufn : std_logic;
signal out263_buf : std_logic := '0';
signal out263_bufn : std_logic;
signal out266_buf : std_logic := '0';
signal out266_bufn : std_logic;
signal out269_buf : std_logic := '0';
signal out269_bufn : std_logic;
signal out273_buf : std_logic := '0';
signal out273_bufn : std_logic;
signal out276_buf : std_logic := '0';
signal out276_bufn : std_logic;
signal out278_buf : std_logic := '0';
signal out278_bufn : std_logic;
signal out280_buf : std_logic := '0';
signal out280_bufn : std_logic;
signal out281_buf : std_logic := '0';
signal out281_bufn : std_logic;
signal out282_buf : std_logic := '0';
signal out282_bufn : std_logic;
signal out284_buf : std_logic := '0';
signal out284_bufn : std_logic;
signal out285_buf : std_logic := '0';
signal out285_bufn : std_logic;
signal out287_buf : std_logic := '0';
signal out287_bufn : std_logic;
signal out288_buf : std_logic := '0';
signal out288_bufn : std_logic;
signal out289_buf : std_logic := '0';
signal out289_bufn : std_logic;
signal out290_buf : std_logic := '0';
signal out290_bufn : std_logic;
signal out291_buf : std_logic := '0';
signal out291_bufn : std_logic;
signal out292_buf : std_logic := '0';
signal out292_bufn : std_logic;
signal out293_buf : std_logic := '0';
signal out293_bufn : std_logic;
signal out294_buf : std_logic := '0';
signal out294_bufn : std_logic;
signal out295_buf : std_logic := '0';
signal out295_bufn : std_logic;
signal out296_buf : std_logic := '0';
signal out296_bufn : std_logic;
signal out312_buf : std_logic := '0';
signal out312_bufn : std_logic;
signal out313_buf : std_logic := '0';
signal out313_bufn : std_logic;
signal out314_buf : std_logic := '0';
signal out314_bufn : std_logic;
signal out315_buf : std_logic := '0';
signal out315_bufn : std_logic;
signal out318_buf : std_logic := '0';
signal out318_bufn : std_logic;
signal out322_buf : std_logic := '0';
signal out322_bufn : std_logic;
signal out323_buf : std_logic := '0';
signal out323_bufn : std_logic;
signal out324_buf : std_logic := '0';
signal out324_bufn : std_logic;
signal out325_buf : std_logic := '0';
signal out325_bufn : std_logic;
signal out326_buf : std_logic := '0';
signal out326_bufn : std_logic;
signal out327_buf : std_logic := '0';
signal out327_bufn : std_logic;
signal out328_buf : std_logic := '0';
signal out328_bufn : std_logic;
signal out333_buf : std_logic := '0';
signal out333_bufn : std_logic;
signal out341_buf : std_logic := '0';
signal out341_bufn : std_logic;
signal out342_buf : std_logic := '0';
signal out342_bufn : std_logic;
signal out343_buf : std_logic := '0';
signal out343_bufn : std_logic;
signal out344_buf : std_logic := '0';
signal out344_bufn : std_logic;
signal out346_buf : std_logic := '0';
signal out346_bufn : std_logic;
signal out349_buf : std_logic := '0';
signal out349_bufn : std_logic;
signal out351_buf : std_logic := '0';
signal out351_bufn : std_logic;
signal out352_buf : std_logic := '0';
signal out352_bufn : std_logic;
signal out353_buf : std_logic := '0';
signal out353_bufn : std_logic;
signal out354_buf : std_logic := '0';
signal out354_bufn : std_logic;
signal out357_buf : std_logic := '0';
signal out357_bufn : std_logic;
signal out361_buf : std_logic := '0';
signal out361_bufn : std_logic;
signal out364_buf : std_logic := '0';
signal out364_bufn : std_logic;
signal out366_buf : std_logic := '0';
signal out366_bufn : std_logic;
signal out371_buf : std_logic := '0';
signal out371_bufn : std_logic;
signal out393_buf : std_logic := '0';
signal out393_bufn : std_logic;
signal out394_buf : std_logic := '0';
signal out394_bufn : std_logic;
signal out395_buf : std_logic := '0';
signal out395_bufn : std_logic;
signal out400_buf : std_logic := '0';
signal out400_bufn : std_logic;
signal out401_buf : std_logic := '0';
signal out401_bufn : std_logic;
signal out404_buf : std_logic := '0';
signal out404_bufn : std_logic;
signal out407_buf : std_logic := '0';
signal out407_bufn : std_logic;
signal out408_buf : std_logic := '0';
signal out408_bufn : std_logic;
signal out409_buf : std_logic := '0';
signal out409_bufn : std_logic;
signal out410_buf : std_logic := '0';
signal out410_bufn : std_logic;
signal out413_buf : std_logic := '0';
signal out413_bufn : std_logic;
signal out414_buf : std_logic := '0';
signal out414_bufn : std_logic;
signal out417_buf : std_logic := '0';
signal out417_bufn : std_logic;
signal out418_buf : std_logic := '0';
signal out418_bufn : std_logic;
signal out422_buf : std_logic := '0';
signal out422_bufn : std_logic;
signal out426_buf : std_logic := '0';
signal out426_bufn : std_logic;
signal out428_buf : std_logic := '0';
signal out428_bufn : std_logic;
signal out431_buf : std_logic := '0';
signal out431_bufn : std_logic;
signal out433_buf : std_logic := '0';
signal out433_bufn : std_logic;
signal out434_buf : std_logic := '0';
signal out434_bufn : std_logic;
signal out435_buf : std_logic := '0';
signal out435_bufn : std_logic;
signal out436_buf : std_logic := '0';
signal out436_bufn : std_logic;
signal out437_buf : std_logic := '0';
signal out437_bufn : std_logic;
signal out438_buf : std_logic := '0';
signal out438_bufn : std_logic;
signal out440_buf : std_logic := '0';
signal out440_bufn : std_logic;
signal out444_buf : std_logic := '0';
signal out444_bufn : std_logic;
signal out446_buf : std_logic := '0';
signal out446_bufn : std_logic;
signal out451_buf : std_logic := '0';
signal out451_bufn : std_logic;
signal out457_buf : std_logic := '0';
signal out457_bufn : std_logic;
signal out458_buf : std_logic := '0';
signal out458_bufn : std_logic;
signal out459_buf : std_logic := '0';
signal out459_bufn : std_logic;
signal out460_buf : std_logic := '0';
signal out460_bufn : std_logic;
signal out461_buf : std_logic := '0';
signal out461_bufn : std_logic;
signal out463_buf : std_logic := '0';
signal out463_bufn : std_logic;
signal out464_buf : std_logic := '0';
signal out464_bufn : std_logic;
signal out466_buf : std_logic := '0';
signal out466_bufn : std_logic;
signal out468_buf : std_logic := '0';
signal out468_bufn : std_logic;
signal out472_buf : std_logic := '0';
signal out472_bufn : std_logic;
signal out475_buf : std_logic := '0';
signal out475_bufn : std_logic;
signal out481_buf : std_logic := '0';
signal out481_bufn : std_logic;
signal out482_buf : std_logic := '0';
signal out482_bufn : std_logic;
signal out483_buf : std_logic := '0';
signal out483_bufn : std_logic;
signal out487_buf : std_logic := '0';
signal out487_bufn : std_logic;
signal out495_buf : std_logic := '0';
signal out495_bufn : std_logic;
signal out496_buf : std_logic := '0';
signal out496_bufn : std_logic;
signal out497_buf : std_logic := '0';
signal out497_bufn : std_logic;
signal out499_buf : std_logic := '0';
signal out499_bufn : std_logic;
signal out500_buf : std_logic := '0';
signal out500_bufn : std_logic;
signal out512_buf : std_logic := '0';
signal out512_bufn : std_logic;
signal out517_buf : std_logic := '0';
signal out517_bufn : std_logic;
signal out518_buf : std_logic := '0';
signal out518_bufn : std_logic;
signal out521_buf : std_logic := '0';
signal out521_bufn : std_logic;
signal out524_buf : std_logic := '0';
signal out524_bufn : std_logic;
signal out525_buf : std_logic := '0';
signal out525_bufn : std_logic;
signal out526_buf : std_logic := '0';
signal out526_bufn : std_logic;
signal out531_buf : std_logic := '0';
signal out531_bufn : std_logic;
signal out554_buf : std_logic := '0';
signal out554_bufn : std_logic;
signal out562_buf : std_logic := '0';
signal out562_bufn : std_logic;
signal out566_buf : std_logic := '0';
signal out566_bufn : std_logic;
-- Retiming: counters
signal rtmcounter0 : unsigned(4 downto 0) := (others => '0');
signal rtmcounter0_next : unsigned(4 downto 0);
-- Retiming: Output of comparators
signal rtmcmp90 : std_logic;
signal rtmcmp95 : std_logic;
signal rtmcmp98 : std_logic;
signal rtmcmp104 : std_logic;
signal rtmcmp148 : std_logic;
signal rtmcmp167 : std_logic;
signal rtmcmp174 : std_logic;
signal rtmcmp181 : std_logic;
signal rtmcmp183 : std_logic;
signal rtmcmp194 : std_logic;
signal rtmcmp197 : std_logic;
signal rtmcmp203 : std_logic;
signal rtmcmp205 : std_logic;
signal rtmcmp215 : std_logic;
-- Function calls: return IDs
begin
-- Sequential process
-- Set the current state
process (clock)
begin
if rising_edge(clock) then
-- Next state
state_cur <= state_next;
-- Buffers for outputs
out122_buf <= out122_bufn;
out36_buf <= out36_bufn;
out49_buf <= out49_bufn;
out35_buf <= out35_bufn;
out27_buf <= out27_bufn;
out16_buf <= out16_bufn;
out25_buf <= out25_bufn;
out20_buf <= out20_bufn;
out57_buf <= out57_bufn;
out23_buf <= out23_bufn;
out136_buf <= out136_bufn;
out0_buf <= out0_bufn;
out134_buf <= out134_bufn;
out13_buf <= out13_bufn;
out131_buf <= out131_bufn;
out129_buf <= out129_bufn;
out111_buf <= out111_bufn;
out31_buf <= out31_bufn;
out126_buf <= out126_bufn;
out106_buf <= out106_bufn;
out124_buf <= out124_bufn;
out138_buf <= out138_bufn;
out141_buf <= out141_bufn;
out143_buf <= out143_bufn;
out146_buf <= out146_bufn;
out150_buf <= out150_bufn;
out153_buf <= out153_bufn;
out155_buf <= out155_bufn;
out158_buf <= out158_bufn;
out162_buf <= out162_bufn;
out165_buf <= out165_bufn;
out168_buf <= out168_bufn;
out171_buf <= out171_bufn;
out174_buf <= out174_bufn;
out178_buf <= out178_bufn;
out181_buf <= out181_bufn;
out183_buf <= out183_bufn;
out197_buf <= out197_bufn;
out201_buf <= out201_bufn;
out204_buf <= out204_bufn;
out207_buf <= out207_bufn;
out210_buf <= out210_bufn;
out213_buf <= out213_bufn;
out217_buf <= out217_bufn;
out220_buf <= out220_bufn;
out222_buf <= out222_bufn;
out225_buf <= out225_bufn;
out229_buf <= out229_bufn;
out232_buf <= out232_bufn;
out235_buf <= out235_bufn;
out238_buf <= out238_bufn;
out241_buf <= out241_bufn;
out245_buf <= out245_bufn;
out248_buf <= out248_bufn;
out250_buf <= out250_bufn;
out253_buf <= out253_bufn;
out257_buf <= out257_bufn;
out260_buf <= out260_bufn;
out263_buf <= out263_bufn;
out266_buf <= out266_bufn;
out269_buf <= out269_bufn;
out273_buf <= out273_bufn;
out276_buf <= out276_bufn;
out278_buf <= out278_bufn;
out280_buf <= out280_bufn;
out281_buf <= out281_bufn;
out282_buf <= out282_bufn;
out284_buf <= out284_bufn;
out285_buf <= out285_bufn;
out287_buf <= out287_bufn;
out288_buf <= out288_bufn;
out289_buf <= out289_bufn;
out290_buf <= out290_bufn;
out291_buf <= out291_bufn;
out292_buf <= out292_bufn;
out293_buf <= out293_bufn;
out294_buf <= out294_bufn;
out295_buf <= out295_bufn;
out296_buf <= out296_bufn;
out312_buf <= out312_bufn;
out313_buf <= out313_bufn;
out314_buf <= out314_bufn;
out315_buf <= out315_bufn;
out318_buf <= out318_bufn;
out322_buf <= out322_bufn;
out323_buf <= out323_bufn;
out324_buf <= out324_bufn;
out325_buf <= out325_bufn;
out326_buf <= out326_bufn;
out327_buf <= out327_bufn;
out328_buf <= out328_bufn;
out333_buf <= out333_bufn;
out341_buf <= out341_bufn;
out342_buf <= out342_bufn;
out343_buf <= out343_bufn;
out344_buf <= out344_bufn;
out346_buf <= out346_bufn;
out349_buf <= out349_bufn;
out351_buf <= out351_bufn;
out352_buf <= out352_bufn;
out353_buf <= out353_bufn;
out354_buf <= out354_bufn;
out357_buf <= out357_bufn;
out361_buf <= out361_bufn;
out364_buf <= out364_bufn;
out366_buf <= out366_bufn;
out371_buf <= out371_bufn;
out393_buf <= out393_bufn;
out394_buf <= out394_bufn;
out395_buf <= out395_bufn;
out400_buf <= out400_bufn;
out401_buf <= out401_bufn;
out404_buf <= out404_bufn;
out407_buf <= out407_bufn;
out408_buf <= out408_bufn;
out409_buf <= out409_bufn;
out410_buf <= out410_bufn;
out413_buf <= out413_bufn;
out414_buf <= out414_bufn;
out417_buf <= out417_bufn;
out418_buf <= out418_bufn;
out422_buf <= out422_bufn;
out426_buf <= out426_bufn;
out428_buf <= out428_bufn;
out431_buf <= out431_bufn;
out433_buf <= out433_bufn;
out434_buf <= out434_bufn;
out435_buf <= out435_bufn;
out436_buf <= out436_bufn;
out437_buf <= out437_bufn;
out438_buf <= out438_bufn;
out440_buf <= out440_bufn;
out444_buf <= out444_bufn;
out446_buf <= out446_bufn;
out451_buf <= out451_bufn;
out457_buf <= out457_bufn;
out458_buf <= out458_bufn;
out459_buf <= out459_bufn;
out460_buf <= out460_bufn;
out461_buf <= out461_bufn;
out463_buf <= out463_bufn;
out464_buf <= out464_bufn;
out466_buf <= out466_bufn;
out468_buf <= out468_bufn;
out472_buf <= out472_bufn;
out475_buf <= out475_bufn;
out481_buf <= out481_bufn;
out482_buf <= out482_bufn;
out483_buf <= out483_bufn;
out487_buf <= out487_bufn;
out495_buf <= out495_bufn;
out496_buf <= out496_bufn;
out497_buf <= out497_bufn;
out499_buf <= out499_bufn;
out500_buf <= out500_bufn;
out512_buf <= out512_bufn;
out517_buf <= out517_bufn;
out518_buf <= out518_bufn;
out521_buf <= out521_bufn;
out524_buf <= out524_bufn;
out525_buf <= out525_bufn;
out526_buf <= out526_bufn;
out531_buf <= out531_bufn;
out554_buf <= out554_bufn;
out562_buf <= out562_bufn;
out566_buf <= out566_bufn;
-- Retiming: counters
rtmcounter0 <= rtmcounter0_next;
-- Function calls: return IDs
end if;
end process;
-- Combinatorial process
-- Compute the next state
-- Compute the outputs
process (
-- Inputs of the FSM
reset, in0, in2, in3, in4, in5, in1, in6, in11, in7, in8, in9, in10,
-- Retiming: outputs of the comparators
rtmcmp90, rtmcmp95, rtmcmp98, rtmcmp104, rtmcmp148, rtmcmp167, rtmcmp174, rtmcmp181, rtmcmp183, rtmcmp194, rtmcmp197, rtmcmp203, rtmcmp205, rtmcmp215,
-- Retiming: the counters
rtmcounter0,
-- Function calls: return IDs
-- Current state
state_cur
)
begin
-- Reset the next state value
state_next <= (others => '0');
-- Default value to the outputs or output buffers
out22 <= '0';
out4 <= '0';
out122_bufn <= '0';
out50 <= '0';
out121 <= '0';
out36_bufn <= '0';
out49_bufn <= '0';
out35_bufn <= '0';
out99 <= '0';
out52 <= '0';
out18 <= '0';
out33 <= '0';
out123 <= '0';
out101 <= '0';
out90 <= '0';
out91 <= '0';
out27_bufn <= '0';
out16_bufn <= '0';
out26 <= '0';
out21 <= '0';
out24 <= '0';
out54 <= '0';
out25_bufn <= '0';
out20_bufn <= '0';
out58 <= '0';
out30 <= '0';
out8 <= '0';
out57_bufn <= '0';
out48 <= '0';
out56 <= '0';
out23_bufn <= '0';
out29 <= '0';
out19 <= '0';
out136_bufn <= '0';
out2 <= '0';
out1 <= '0';
out46 <= '0';
out0_bufn <= '0';
out135 <= '0';
out118 <= '0';
out116 <= '0';
out14 <= '0';
out134_bufn <= '0';
out28 <= '0';
out13_bufn <= '0';
out133 <= '0';
out131_bufn <= '0';
out132 <= '0';
out114 <= '0';
out130 <= '0';
out112 <= '0';
out38 <= '0';
out44 <= '0';
out97 <= '0';
out129_bufn <= '0';
out111_bufn <= '0';
out31_bufn <= '0';
out126_bufn <= '0';
out107 <= '0';
out108 <= '0';
out105 <= '0';
out106_bufn <= '0';
out125 <= '0';
out120 <= '0';
out124_bufn <= '0';
out103 <= '0';
out42 <= '0';
out40 <= '0';
out60 <= '0';
out137 <= '0';
out138_bufn <= '0';
out140 <= '0';
out141_bufn <= '0';
out142 <= '0';
out143_bufn <= '0';
out145 <= '0';
out146_bufn <= '0';
out148 <= '0';
out150_bufn <= '0';
out153_bufn <= '0';
out154 <= '0';
out155_bufn <= '0';
out156 <= '0';
out157 <= '0';
out158_bufn <= '0';
out159 <= '0';
out160 <= '0';
out161 <= '0';
out162_bufn <= '0';
out164 <= '0';
out165_bufn <= '0';
out167 <= '0';
out168_bufn <= '0';
out170 <= '0';
out171_bufn <= '0';
out173 <= '0';
out174_bufn <= '0';
out176 <= '0';
out178_bufn <= '0';
out181_bufn <= '0';
out182 <= '0';
out183_bufn <= '0';
out184 <= '0';
out185 <= '0';
out186 <= '0';
out187 <= '0';
out190 <= '0';
out195 <= '0';
out197_bufn <= '0';
out198 <= '0';
out199 <= '0';
out200 <= '0';
out201_bufn <= '0';
out203 <= '0';
out204_bufn <= '0';
out206 <= '0';
out207_bufn <= '0';
out209 <= '0';
out210_bufn <= '0';
out212 <= '0';
out213_bufn <= '0';
out215 <= '0';
out217_bufn <= '0';
out220_bufn <= '0';
out221 <= '0';
out222_bufn <= '0';
out223 <= '0';
out224 <= '0';
out225_bufn <= '0';
out226 <= '0';
out227 <= '0';
out228 <= '0';
out229_bufn <= '0';
out231 <= '0';
out232_bufn <= '0';
out234 <= '0';
out235_bufn <= '0';
out237 <= '0';
out238_bufn <= '0';
out240 <= '0';
out241_bufn <= '0';
out243 <= '0';
out245_bufn <= '0';
out248_bufn <= '0';
out249 <= '0';
out250_bufn <= '0';
out251 <= '0';
out252 <= '0';
out253_bufn <= '0';
out254 <= '0';
out255 <= '0';
out256 <= '0';
out257_bufn <= '0';
out259 <= '0';
out260_bufn <= '0';
out262 <= '0';
out263_bufn <= '0';
out265 <= '0';
out266_bufn <= '0';
out268 <= '0';
out269_bufn <= '0';
out271 <= '0';
out273_bufn <= '0';
out276_bufn <= '0';
out277 <= '0';
out278_bufn <= '0';
out279 <= '0';
out280_bufn <= '0';
out281_bufn <= '0';
out282_bufn <= '0';
out283 <= '0';
out284_bufn <= '0';
out285_bufn <= '0';
out286 <= '0';
out287_bufn <= '0';
out288_bufn <= '0';
out289_bufn <= '0';
out290_bufn <= '0';
out291_bufn <= '0';
out292_bufn <= '0';
out293_bufn <= '0';
out294_bufn <= '0';
out295_bufn <= '0';
out296_bufn <= '0';
out297 <= '0';
out298 <= '0';
out311 <= '0';
out312_bufn <= '0';
out313_bufn <= '0';
out314_bufn <= '0';
out315_bufn <= '0';
out316 <= '0';
out318_bufn <= '0';
out321 <= '0';
out322_bufn <= '0';
out323_bufn <= '0';
out324_bufn <= '0';
out325_bufn <= '0';
out326_bufn <= '0';
out327_bufn <= '0';
out328_bufn <= '0';
out329 <= '0';
out333_bufn <= '0';
out341_bufn <= '0';
out342_bufn <= '0';
out343_bufn <= '0';
out344_bufn <= '0';
out345 <= '0';
out346_bufn <= '0';
out349_bufn <= '0';
out350 <= '0';
out351_bufn <= '0';
out352_bufn <= '0';
out353_bufn <= '0';
out354_bufn <= '0';
out355 <= '0';
out357_bufn <= '0';
out361_bufn <= '0';
out362 <= '0';
out363 <= '0';
out364_bufn <= '0';
out366_bufn <= '0';
out367 <= '0';
out371_bufn <= '0';
out372 <= '0';
out373 <= '0';
out382 <= '0';
out383 <= '0';
out385 <= '0';
out393_bufn <= '0';
out394_bufn <= '0';
out395_bufn <= '0';
out396 <= '0';
out398 <= '0';
out400_bufn <= '0';
out401_bufn <= '0';
out402 <= '0';
out404_bufn <= '0';
out406 <= '0';
out407_bufn <= '0';
out408_bufn <= '0';
out409_bufn <= '0';
out410_bufn <= '0';
out411 <= '0';
out412 <= '0';
out413_bufn <= '0';
out414_bufn <= '0';
out416 <= '0';
out417_bufn <= '0';
out418_bufn <= '0';
out419 <= '0';
out422_bufn <= '0';
out423 <= '0';
out425 <= '0';
out426_bufn <= '0';
out428_bufn <= '0';
out429 <= '0';
out430 <= '0';
out431_bufn <= '0';
out433_bufn <= '0';
out434_bufn <= '0';
out435_bufn <= '0';
out436_bufn <= '0';
out437_bufn <= '0';
out438_bufn <= '0';
out440_bufn <= '0';
out441 <= '0';
out443 <= '0';
out444_bufn <= '0';
out445 <= '0';
out446_bufn <= '0';
out447 <= '0';
out450 <= '0';
out451_bufn <= '0';
out454 <= '0';
out455 <= '0';
out457_bufn <= '0';
out458_bufn <= '0';
out459_bufn <= '0';
out460_bufn <= '0';
out461_bufn <= '0';
out462 <= '0';
out463_bufn <= '0';
out464_bufn <= '0';
out465 <= '0';
out466_bufn <= '0';
out467 <= '0';
out468_bufn <= '0';
out469 <= '0';
out472_bufn <= '0';
out475_bufn <= '0';
out481_bufn <= '0';
out482_bufn <= '0';
out483_bufn <= '0';
out484 <= '0';
out487_bufn <= '0';
out488 <= '0';
out491 <= '0';
out495_bufn <= '0';
out496_bufn <= '0';
out497_bufn <= '0';
out498 <= '0';
out499_bufn <= '0';
out500_bufn <= '0';
out501 <= '0';
out512_bufn <= '0';
out513 <= '0';
out517_bufn <= '0';
out518_bufn <= '0';
out519 <= '0';
out521_bufn <= '0';
out522 <= '0';
out524_bufn <= '0';
out525_bufn <= '0';
out526_bufn <= '0';
out527 <= '0';
out528 <= '0';
out531_bufn <= '0';
out540 <= '0';
out542 <= '0';
out544 <= '0';
out545 <= '0';
out554_bufn <= '0';
out555 <= '0';
out559 <= '0';
out560 <= '0';
out561 <= '0';
out562_bufn <= '0';
out563 <= '0';
out566_bufn <= '0';
out567 <= '0';
out570 <= '0';
out572 <= '0';
out575 <= '0';
out577 <= '0';
out578 <= '0';
out580 <= '0';
out581 <= '0';
-- Retiming: default value for counters
rtmcounter0_next <= (others => '0');
-- Function calls: default values (no change)
-- For all states, compute the next state bits
-- And the outputs, and the next value for buffered outputs
if state_cur(0) = '1' then
-- Next state
state_next(109) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out1 <= '1';
out2 <= '1';
end if;
if state_cur(1) = '1' then
-- Next state
if (in0) = '1' then
state_next(1) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
else
-- Return from function: memextrct_0
state_next(88) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out14 <= '1';
out8 <= '1';
out4 <= '1';
end if;
if state_cur(2) = '1' then
-- Next state
state_next(1) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
-- Assignment of non-buffered outputs
out18 <= '1';
end if;
if state_cur(3) = '1' then
-- Next state
state_next(0) <= '1';
-- Next values for buffered outputs
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out19 <= '1';
end if;
if state_cur(4) = '1' then
-- Next state
state_next(3) <= '1';
-- Next values for buffered outputs
out20_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out22 <= '1';
end if;
if state_cur(5) = '1' then
-- Next state
state_next(4) <= '1';
-- Next values for buffered outputs
out23_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out24 <= '1';
end if;
if state_cur(6) = '1' then
-- Next state
state_next(5) <= '1';
-- Next values for buffered outputs
out25_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out26 <= '1';
end if;
-- Info: This is the init/reset state
if state_cur(7) = '1' then
-- Next state
if (not (in2)) = '1' then
state_next(7) <= '1';
-- Next values for buffered outputs
else
if (in1) = '1' then
state_next(60) <= '1';
-- Next values for buffered outputs
else
state_next(154) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out28 <= '1';
out29 <= '1';
end if;
if state_cur(8) = '1' then
-- Next state
state_next(6) <= '1';
-- Next values for buffered outputs
out27_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out30 <= '1';
end if;
if state_cur(9) = '1' then
-- Next state
state_next(9) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
end if;
if state_cur(10) = '1' then
-- Next state
state_next(8) <= '1';
-- Next values for buffered outputs
out31_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out33 <= '1';
out2 <= '1';
end if;
if state_cur(11) = '1' then
-- Next state
state_next(10) <= '1';
-- Next values for buffered outputs
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
end if;
if state_cur(12) = '1' then
-- Next state
state_next(11) <= '1';
-- Next values for buffered outputs
out35_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
end if;
if state_cur(13) = '1' then
-- Next state
state_next(12) <= '1';
-- Next values for buffered outputs
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out50 <= '1';
out48 <= '1';
out46 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(14) = '1' then
-- Next state
state_next(13) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(15) = '1' then
-- Next state
if (in3) = '1' then
state_next(15) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
else
-- Return from function: memextrct_1
state_next(88) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out14 <= '1';
out91 <= '1';
out90 <= '1';
end if;
if state_cur(16) = '1' then
-- Next state
if (in5) = '1' then
-- Function call: memextrct_1
state_next(19) <= '1';
-- Next values for buffered outputs
out16_bufn <= '1';
else
if (in4) = '1' then
-- Function call: memextrct_0
state_next(2) <= '1';
-- Next values for buffered outputs
out16_bufn <= '1';
else
state_next(88) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out97 <= '1';
end if;
if state_cur(17) = '1' then
-- Next state
state_next(14) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(18) = '1' then
-- Next state
state_next(17) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out108 <= '1';
out107 <= '1';
end if;
if state_cur(19) = '1' then
-- Next state
state_next(15) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
-- Assignment of non-buffered outputs
out18 <= '1';
end if;
if state_cur(20) = '1' then
-- Next state
state_next(18) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out108 <= '1';
out121 <= '1';
end if;
if state_cur(21) = '1' then
-- Next state
state_next(20) <= '1';
-- Next values for buffered outputs
out126_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out132 <= '1';
out50 <= '1';
out21 <= '1';
out130 <= '1';
out108 <= '1';
end if;
if state_cur(22) = '1' then
-- Next state
state_next(21) <= '1';
-- Next values for buffered outputs
out131_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out108 <= '1';
out133 <= '1';
end if;
if state_cur(23) = '1' then
-- Next state
state_next(22) <= '1';
-- Next values for buffered outputs
out138_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out140 <= '1';
out108 <= '1';
end if;
if state_cur(24) = '1' then
-- Next state
state_next(23) <= '1';
-- Next values for buffered outputs
out143_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out145 <= '1';
out108 <= '1';
end if;
if state_cur(25) = '1' then
-- Next state
state_next(24) <= '1';
-- Next values for buffered outputs
out146_bufn <= '1';
out31_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out148 <= '1';
out108 <= '1';
end if;
if state_cur(26) = '1' then
-- Next state
state_next(25) <= '1';
-- Next values for buffered outputs
out150_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out154 <= '1';
out40 <= '1';
out21 <= '1';
out108 <= '1';
end if;
if state_cur(27) = '1' then
-- Next state
state_next(26) <= '1';
-- Next values for buffered outputs
out153_bufn <= '1';
out35_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out156 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(28) = '1' then
-- Next state
state_next(27) <= '1';
-- Next values for buffered outputs
out155_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(29) = '1' then
-- Next state
state_next(28) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out157 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(30) = '1' then
-- Next state
state_next(29) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(31) = '1' then
-- Next state
state_next(30) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out160 <= '1';
out159 <= '1';
end if;
if state_cur(32) = '1' then
-- Next state
state_next(31) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out161 <= '1';
out160 <= '1';
end if;
if state_cur(33) = '1' then
-- Next state
state_next(32) <= '1';
-- Next values for buffered outputs
out162_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out164 <= '1';
out160 <= '1';
end if;
if state_cur(34) = '1' then
-- Next state
state_next(33) <= '1';
-- Next values for buffered outputs
out165_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out167 <= '1';
out160 <= '1';
end if;
if state_cur(35) = '1' then
-- Next state
state_next(34) <= '1';
-- Next values for buffered outputs
out168_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out170 <= '1';
out160 <= '1';
end if;
if state_cur(36) = '1' then
-- Next state
state_next(35) <= '1';
-- Next values for buffered outputs
out171_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out173 <= '1';
out160 <= '1';
end if;
if state_cur(37) = '1' then
-- Next state
state_next(36) <= '1';
-- Next values for buffered outputs
out174_bufn <= '1';
out31_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out176 <= '1';
out160 <= '1';
end if;
if state_cur(38) = '1' then
-- Next state
state_next(37) <= '1';
-- Next values for buffered outputs
out178_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out182 <= '1';
out40 <= '1';
out21 <= '1';
out160 <= '1';
end if;
if state_cur(39) = '1' then
-- Next state
state_next(38) <= '1';
-- Next values for buffered outputs
out181_bufn <= '1';
out35_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out184 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(40) = '1' then
-- Next state
state_next(39) <= '1';
-- Next values for buffered outputs
out183_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(41) = '1' then
-- Next state
state_next(40) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out185 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(42) = '1' then
-- Next state
state_next(41) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(43) = '1' then
-- Next state
if (in7) = '1' then
state_next(60) <= '1';
-- Next values for buffered outputs
else
if (not (in6)) = '1' then
state_next(43) <= '1';
-- Next values for buffered outputs
else
state_next(108) <= '1';
-- Next values for buffered outputs
out371_bufn <= '1';
end if;
end if;
-- Assignment of non-buffered outputs
out190 <= '1';
out187 <= '1';
out186 <= '1';
end if;
if state_cur(44) = '1' then
-- Next state
if (in7) = '1' then
state_next(60) <= '1';
-- Next values for buffered outputs
else
if (not (in8)) = '1' then
state_next(44) <= '1';
-- Next values for buffered outputs
else
state_next(110) <= '1';
-- Next values for buffered outputs
out371_bufn <= '1';
end if;
end if;
-- Assignment of non-buffered outputs
out195 <= '1';
out187 <= '1';
end if;
if state_cur(45) = '1' then
-- Next state
state_next(42) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out199 <= '1';
out198 <= '1';
end if;
if state_cur(46) = '1' then
-- Next state
state_next(45) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out200 <= '1';
out199 <= '1';
end if;
if state_cur(47) = '1' then
-- Next state
state_next(46) <= '1';
-- Next values for buffered outputs
out201_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out203 <= '1';
out199 <= '1';
end if;
if state_cur(48) = '1' then
-- Next state
state_next(47) <= '1';
-- Next values for buffered outputs
out204_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out206 <= '1';
out199 <= '1';
end if;
if state_cur(49) = '1' then
-- Next state
state_next(48) <= '1';
-- Next values for buffered outputs
out207_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out209 <= '1';
out199 <= '1';
end if;
if state_cur(50) = '1' then
-- Next state
state_next(49) <= '1';
-- Next values for buffered outputs
out210_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out212 <= '1';
out199 <= '1';
end if;
if state_cur(51) = '1' then
-- Next state
state_next(50) <= '1';
-- Next values for buffered outputs
out213_bufn <= '1';
out31_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out215 <= '1';
out199 <= '1';
end if;
if state_cur(52) = '1' then
-- Next state
state_next(51) <= '1';
-- Next values for buffered outputs
out217_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out221 <= '1';
out40 <= '1';
out21 <= '1';
out199 <= '1';
end if;
if state_cur(53) = '1' then
-- Next state
state_next(52) <= '1';
-- Next values for buffered outputs
out220_bufn <= '1';
out35_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out223 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(54) = '1' then
-- Next state
state_next(53) <= '1';
-- Next values for buffered outputs
out222_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(55) = '1' then
-- Next state
state_next(54) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out224 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(56) = '1' then
-- Next state
state_next(55) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(57) = '1' then
-- Next state
state_next(56) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out227 <= '1';
out226 <= '1';
end if;
if state_cur(58) = '1' then
-- Next state
state_next(57) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out228 <= '1';
out227 <= '1';
end if;
if state_cur(59) = '1' then
-- Next state
state_next(58) <= '1';
-- Next values for buffered outputs
out229_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out231 <= '1';
out227 <= '1';
end if;
if state_cur(60) = '1' then
-- Next state
state_next(87) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out18 <= '1';
end if;
if state_cur(61) = '1' then
-- Next state
state_next(59) <= '1';
-- Next values for buffered outputs
out232_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out234 <= '1';
out227 <= '1';
end if;
if state_cur(62) = '1' then
-- Next state
state_next(61) <= '1';
-- Next values for buffered outputs
out235_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out237 <= '1';
out227 <= '1';
end if;
if state_cur(63) = '1' then
-- Next state
state_next(62) <= '1';
-- Next values for buffered outputs
out238_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out240 <= '1';
out227 <= '1';
end if;
if state_cur(64) = '1' then
-- Next state
state_next(63) <= '1';
-- Next values for buffered outputs
out241_bufn <= '1';
out31_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out243 <= '1';
out227 <= '1';
end if;
if state_cur(65) = '1' then
-- Next state
state_next(64) <= '1';
-- Next values for buffered outputs
out245_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out249 <= '1';
out40 <= '1';
out21 <= '1';
out227 <= '1';
end if;
if state_cur(66) = '1' then
-- Next state
state_next(65) <= '1';
-- Next values for buffered outputs
out248_bufn <= '1';
out35_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out251 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(67) = '1' then
-- Next state
state_next(66) <= '1';
-- Next values for buffered outputs
out250_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(68) = '1' then
-- Next state
state_next(67) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out252 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(69) = '1' then
-- Next state
state_next(68) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(70) = '1' then
-- Next state
state_next(69) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out255 <= '1';
out254 <= '1';
end if;
if state_cur(71) = '1' then
-- Next state
state_next(70) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out256 <= '1';
out255 <= '1';
end if;
if state_cur(72) = '1' then
-- Next state
state_next(71) <= '1';
-- Next values for buffered outputs
out257_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out259 <= '1';
out255 <= '1';
end if;
if state_cur(73) = '1' then
-- Next state
state_next(72) <= '1';
-- Next values for buffered outputs
out260_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out262 <= '1';
out255 <= '1';
end if;
if state_cur(74) = '1' then
-- Next state
state_next(73) <= '1';
-- Next values for buffered outputs
out263_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out265 <= '1';
out255 <= '1';
end if;
if state_cur(75) = '1' then
-- Next state
state_next(74) <= '1';
-- Next values for buffered outputs
out266_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out268 <= '1';
out255 <= '1';
end if;
if state_cur(76) = '1' then
-- Next state
state_next(75) <= '1';
-- Next values for buffered outputs
out269_bufn <= '1';
out31_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out271 <= '1';
out255 <= '1';
end if;
if state_cur(77) = '1' then
-- Next state
state_next(76) <= '1';
-- Next values for buffered outputs
out273_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out277 <= '1';
out40 <= '1';
out21 <= '1';
out255 <= '1';
end if;
if state_cur(78) = '1' then
-- Next state
state_next(77) <= '1';
-- Next values for buffered outputs
out276_bufn <= '1';
out35_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out279 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(79) = '1' then
-- Next state
state_next(80) <= '1';
-- Next values for buffered outputs
out285_bufn <= '1';
out284_bufn <= '1';
out269_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(80) = '1' then
-- Next state
state_next(113) <= '1';
-- Next values for buffered outputs
out395_bufn <= '1';
out284_bufn <= '1';
out146_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(81) = '1' then
-- Next state
state_next(82) <= '1';
-- Next values for buffered outputs
out290_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(82) = '1' then
-- Next state
state_next(83) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out292_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(83) = '1' then
-- Next state
state_next(85) <= '1';
-- Next values for buffered outputs
out295_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out286 <= '1';
end if;
if state_cur(84) = '1' then
-- Next state
state_next(89) <= '1';
-- Next values for buffered outputs
out313_bufn <= '1';
out281_bufn <= '1';
out312_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(85) = '1' then
-- Next state
state_next(86) <= '1';
-- Next values for buffered outputs
out296_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(86) = '1' then
-- Next state
state_next(90) <= '1';
-- Next values for buffered outputs
out318_bufn <= '1';
out280_bufn <= '1';
out315_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(87) = '1' then
-- Next state
if (in9) = '1' then
state_next(87) <= '1';
-- Next values for buffered outputs
else
state_next(16) <= '1';
-- Next values for buffered outputs
out16_bufn <= '1';
end if;
-- Assignment of non-buffered outputs
out14 <= '1';
out298 <= '1';
out297 <= '1';
end if;
if state_cur(88) = '1' then
-- Next state
if (in1) = '1' then
if (in5) = '1' then
state_next(43) <= '1';
-- Next values for buffered outputs
else
state_next(44) <= '1';
-- Next values for buffered outputs
end if;
else
state_next(9) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out311 <= '1';
end if;
if state_cur(89) = '1' then
-- Next state
state_next(112) <= '1';
-- Next values for buffered outputs
out394_bufn <= '1';
out284_bufn <= '1';
out393_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(90) = '1' then
if rtmcmp90 = '1' then
-- Next state
state_next(93) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out325_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out56 <= '1';
out137 <= '1';
out125 <= '1';
out116 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(90) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out318_bufn <= '1';
out280_bufn <= '1';
out315_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out316 <= '1';
end if;
if state_cur(91) = '1' then
-- Next state
state_next(170) <= '1';
-- Next values for buffered outputs
out487_bufn <= '1';
out284_bufn <= '1';
out266_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
out321 <= '1';
end if;
if state_cur(92) = '1' then
-- Next state
state_next(240) <= '1';
-- Next values for buffered outputs
out217_bufn <= '1';
out295_bufn <= '1';
out281_bufn <= '1';
out562_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(93) = '1' then
-- Next state
state_next(101) <= '1';
-- Next values for buffered outputs
out323_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out118 <= '1';
out58 <= '1';
out286 <= '1';
end if;
if state_cur(94) = '1' then
-- Next state
state_next(96) <= '1';
-- Next values for buffered outputs
out341_bufn <= '1';
out281_bufn <= '1';
out241_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(95) = '1' then
if rtmcmp95 = '1' then
-- Next state
state_next(210) <= '1';
-- Next values for buffered outputs
out418_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out142 <= '1';
out112 <= '1';
out99 <= '1';
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(95) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out333_bufn <= '1';
out245_bufn <= '1';
out318_bufn <= '1';
out328_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out329 <= '1';
end if;
if state_cur(96) = '1' then
-- Next state
state_next(91) <= '1';
-- Next values for buffered outputs
out322_bufn <= '1';
out281_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(97) = '1' then
-- Next state
state_next(95) <= '1';
-- Next values for buffered outputs
out333_bufn <= '1';
out245_bufn <= '1';
out318_bufn <= '1';
out328_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(98) = '1' then
if rtmcmp98 = '1' then
-- Next state
state_next(97) <= '1';
-- Next values for buffered outputs
out342_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out137 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(98) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out343_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out345 <= '1';
end if;
if state_cur(99) = '1' then
-- Next state
state_next(119) <= '1';
-- Next values for buffered outputs
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(100) = '1' then
-- Next state
state_next(233) <= '1';
-- Next values for buffered outputs
out566_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out125 <= '1';
out286 <= '1';
end if;
if state_cur(101) = '1' then
-- Next state
state_next(98) <= '1';
-- Next values for buffered outputs
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out343_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(102) = '1' then
-- Next state
state_next(239) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out350 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(103) = '1' then
-- Next state
state_next(146) <= '1';
-- Next values for buffered outputs
out401_bufn <= '1';
out444_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out283 <= '1';
end if;
if state_cur(104) = '1' then
if rtmcmp104 = '1' then
-- Next state
state_next(103) <= '1';
-- Next values for buffered outputs
out352_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out142 <= '1';
out99 <= '1';
out130 <= '1';
out101 <= '1';
out54 <= '1';
out135 <= '1';
out123 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(104) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out129_bufn <= '1';
out357_bufn <= '1';
out354_bufn <= '1';
out353_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out355 <= '1';
end if;
if state_cur(105) = '1' then
-- Next state
state_next(133) <= '1';
-- Next values for buffered outputs
out431_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out363 <= '1';
out362 <= '1';
end if;
if state_cur(106) = '1' then
-- Next state
state_next(186) <= '1';
-- Next values for buffered outputs
out518_bufn <= '1';
out284_bufn <= '1';
out153_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(107) = '1' then
-- Next state
state_next(148) <= '1';
-- Next values for buffered outputs
out446_bufn <= '1';
out413_bufn <= '1';
out281_bufn <= '1';
out250_bufn <= '1';
-- Assignment of non-buffered outputs
out112 <= '1';
out367 <= '1';
out283 <= '1';
end if;
if state_cur(108) = '1' then
-- Next state
if (in10) = '1' then
state_next(109) <= '1';
-- Next values for buffered outputs
else
state_next(154) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out372 <= '1';
end if;
if state_cur(109) = '1' then
-- Next state
state_next(43) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out382 <= '1';
out373 <= '1';
end if;
if state_cur(110) = '1' then
-- Next state
if (in11) = '1' then
state_next(44) <= '1';
-- Next values for buffered outputs
else
state_next(111) <= '1';
-- Next values for buffered outputs
out284_bufn <= '1';
end if;
-- Assignment of non-buffered outputs
out372 <= '1';
out385 <= '1';
out383 <= '1';
end if;
if state_cur(111) = '1' then
-- Next state
state_next(153) <= '1';
-- Next values for buffered outputs
out422_bufn <= '1';
out284_bufn <= '1';
out278_bufn <= '1';
-- Assignment of non-buffered outputs
out372 <= '1';
out286 <= '1';
end if;
if state_cur(112) = '1' then
-- Next state
state_next(94) <= '1';
-- Next values for buffered outputs
out326_bufn <= '1';
out284_bufn <= '1';
out210_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(113) = '1' then
-- Next state
state_next(160) <= '1';
-- Next values for buffered outputs
out461_bufn <= '1';
out281_bufn <= '1';
out178_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(114) = '1' then
-- Next state
state_next(196) <= '1';
-- Next values for buffered outputs
out328_bufn <= '1';
out284_bufn <= '1';
out155_bufn <= '1';
-- Assignment of non-buffered outputs
out142 <= '1';
out396 <= '1';
out286 <= '1';
end if;
if state_cur(115) = '1' then
-- Next state
state_next(105) <= '1';
-- Next values for buffered outputs
out364_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out398 <= '1';
out363 <= '1';
end if;
if state_cur(116) = '1' then
-- Next state
state_next(120) <= '1';
-- Next values for buffered outputs
out407_bufn <= '1';
out281_bufn <= '1';
out168_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(117) = '1' then
-- Next state
state_next(211) <= '1';
-- Next values for buffered outputs
out458_bufn <= '1';
out475_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(118) = '1' then
-- Next state
state_next(151) <= '1';
-- Next values for buffered outputs
out333_bufn <= '1';
out31_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out402 <= '1';
out363 <= '1';
end if;
if state_cur(119) = '1' then
-- Next state
state_next(150) <= '1';
-- Next values for buffered outputs
out366_bufn <= '1';
out35_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out406 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(120) = '1' then
-- Next state
state_next(121) <= '1';
-- Next values for buffered outputs
out409_bufn <= '1';
out281_bufn <= '1';
out408_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(121) = '1' then
-- Next state
state_next(139) <= '1';
-- Next values for buffered outputs
out438_bufn <= '1';
out284_bufn <= '1';
out431_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(122) = '1' then
-- Next state
state_next(123) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out412 <= '1';
out411 <= '1';
end if;
if state_cur(123) = '1' then
-- Next state
state_next(212) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out99 <= '1';
out101 <= '1';
end if;
if state_cur(124) = '1' then
-- Next state
state_next(81) <= '1';
-- Next values for buffered outputs
out288_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out283 <= '1';
end if;
if state_cur(125) = '1' then
-- Next state
state_next(128) <= '1';
-- Next values for buffered outputs
out422_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(126) = '1' then
-- Next state
state_next(125) <= '1';
-- Next values for buffered outputs
out414_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out416 <= '1';
out38 <= '1';
out286 <= '1';
end if;
if state_cur(127) = '1' then
-- Next state
state_next(169) <= '1';
-- Next values for buffered outputs
out417_bufn <= '1';
out483_bufn <= '1';
out482_bufn <= '1';
out318_bufn <= '1';
-- Assignment of non-buffered outputs
out112 <= '1';
out419 <= '1';
out283 <= '1';
end if;
if state_cur(128) = '1' then
-- Next state
state_next(124) <= '1';
-- Next values for buffered outputs
out413_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(129) = '1' then
-- Next state
state_next(130) <= '1';
-- Next values for buffered outputs
out426_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out423 <= '1';
out412 <= '1';
end if;
if state_cur(130) = '1' then
-- Next state
state_next(143) <= '1';
-- Next values for buffered outputs
out435_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out425 <= '1';
out412 <= '1';
end if;
if state_cur(131) = '1' then
-- Next state
state_next(102) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out99 <= '1';
out101 <= '1';
end if;
if state_cur(132) = '1' then
-- Next state
state_next(144) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
-- Assignment of non-buffered outputs
out114 <= '1';
out429 <= '1';
out52 <= '1';
out286 <= '1';
end if;
if state_cur(133) = '1' then
-- Next state
state_next(237) <= '1';
-- Next values for buffered outputs
out475_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out430 <= '1';
out363 <= '1';
end if;
if state_cur(134) = '1' then
-- Next state
state_next(227) <= '1';
-- Next values for buffered outputs
out496_bufn <= '1';
out284_bufn <= '1';
out263_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(135) = '1' then
-- Next state
state_next(117) <= '1';
-- Next values for buffered outputs
out352_bufn <= '1';
out281_bufn <= '1';
out401_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(136) = '1' then
-- Next state
state_next(135) <= '1';
-- Next values for buffered outputs
out434_bufn <= '1';
out281_bufn <= '1';
out165_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(137) = '1' then
-- Next state
state_next(228) <= '1';
-- Next values for buffered outputs
out463_bufn <= '1';
out284_bufn <= '1';
out260_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(138) = '1' then
-- Next state
state_next(137) <= '1';
-- Next values for buffered outputs
out436_bufn <= '1';
out281_bufn <= '1';
out435_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(139) = '1' then
-- Next state
state_next(229) <= '1';
-- Next values for buffered outputs
out495_bufn <= '1';
out284_bufn <= '1';
out204_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(140) = '1' then
-- Next state
state_next(126) <= '1';
-- Next values for buffered outputs
out324_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(141) = '1' then
-- Next state
state_next(142) <= '1';
-- Next values for buffered outputs
out122_bufn <= '1';
out134_bufn <= '1';
out400_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out116 <= '1';
out283 <= '1';
end if;
if state_cur(142) = '1' then
-- Next state
state_next(168) <= '1';
-- Next values for buffered outputs
out481_bufn <= '1';
out351_bufn <= '1';
-- Assignment of non-buffered outputs
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
end if;
if state_cur(143) = '1' then
-- Next state
state_next(149) <= '1';
-- Next values for buffered outputs
out451_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out441 <= '1';
out412 <= '1';
end if;
if state_cur(144) = '1' then
-- Next state
state_next(178) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out112 <= '1';
end if;
if state_cur(145) = '1' then
-- Next state
state_next(99) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out443 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(146) = '1' then
-- Next state
state_next(100) <= '1';
-- Next values for buffered outputs
out124_bufn <= '1';
out349_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out445 <= '1';
out50 <= '1';
out283 <= '1';
end if;
if state_cur(147) = '1' then
-- Next state
state_next(78) <= '1';
-- Next values for buffered outputs
out278_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(148) = '1' then
if rtmcmp148 = '1' then
-- Next state
state_next(172) <= '1';
-- Next values for buffered outputs
out296_bufn <= '1';
out284_bufn <= '1';
out220_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out103 <= '1';
out125 <= '1';
out99 <= '1';
out123 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(148) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out446_bufn <= '1';
out413_bufn <= '1';
out281_bufn <= '1';
out250_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out447 <= '1';
end if;
if state_cur(149) = '1' then
-- Next state
state_next(226) <= '1';
-- Next values for buffered outputs
out354_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out450 <= '1';
out412 <= '1';
end if;
if state_cur(150) = '1' then
-- Next state
state_next(118) <= '1';
-- Next values for buffered outputs
out404_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out454 <= '1';
out40 <= '1';
out21 <= '1';
out363 <= '1';
end if;
if state_cur(151) = '1' then
-- Next state
state_next(115) <= '1';
-- Next values for buffered outputs
out393_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out455 <= '1';
out363 <= '1';
end if;
if state_cur(152) = '1' then
-- Next state
state_next(230) <= '1';
-- Next values for buffered outputs
out512_bufn <= '1';
out281_bufn <= '1';
out171_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(153) = '1' then
-- Next state
state_next(114) <= '1';
-- Next values for buffered outputs
out292_bufn <= '1';
out284_bufn <= '1';
out222_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(154) = '1' then
-- Next state
state_next(44) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out372 <= '1';
end if;
if state_cur(155) = '1' then
-- Next state
state_next(232) <= '1';
-- Next values for buffered outputs
out517_bufn <= '1';
out284_bufn <= '1';
out207_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(156) = '1' then
-- Next state
state_next(104) <= '1';
-- Next values for buffered outputs
out129_bufn <= '1';
out357_bufn <= '1';
out354_bufn <= '1';
out353_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(157) = '1' then
-- Next state
state_next(156) <= '1';
-- Next values for buffered outputs
out458_bufn <= '1';
out324_bufn <= '1';
-- Assignment of non-buffered outputs
out56 <= '1';
out137 <= '1';
out116 <= '1';
out283 <= '1';
end if;
if state_cur(158) = '1' then
-- Next state
state_next(157) <= '1';
-- Next values for buffered outputs
out136_bufn <= '1';
out434_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(159) = '1' then
-- Next state
state_next(158) <= '1';
-- Next values for buffered outputs
out459_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(160) = '1' then
-- Next state
state_next(189) <= '1';
-- Next values for buffered outputs
out525_bufn <= '1';
out281_bufn <= '1';
out245_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(161) = '1' then
-- Next state
state_next(106) <= '1';
-- Next values for buffered outputs
out288_bufn <= '1';
out284_bufn <= '1';
out276_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
out462 <= '1';
out283 <= '1';
end if;
if state_cur(162) = '1' then
-- Next state
state_next(159) <= '1';
-- Next values for buffered outputs
out460_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(163) = '1' then
-- Next state
state_next(162) <= '1';
-- Next values for buffered outputs
out463_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out118 <= '1';
out58 <= '1';
out465 <= '1';
out48 <= '1';
out283 <= '1';
end if;
if state_cur(164) = '1' then
-- Next state
state_next(163) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out408_bufn <= '1';
out464_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(165) = '1' then
-- Next state
state_next(166) <= '1';
-- Next values for buffered outputs
out273_bufn <= '1';
out343_bufn <= '1';
out281_bufn <= '1';
out181_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(166) = '1' then
-- Next state
state_next(215) <= '1';
-- Next values for buffered outputs
out562_bufn <= '1';
out342_bufn <= '1';
out284_bufn <= '1';
out404_bufn <= '1';
-- Assignment of non-buffered outputs
out467 <= '1';
out142 <= '1';
out283 <= '1';
end if;
if state_cur(167) = '1' then
if rtmcmp167 = '1' then
-- Next state
state_next(164) <= '1';
-- Next values for buffered outputs
out409_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out112 <= '1';
out142 <= '1';
out99 <= '1';
out54 <= '1';
out135 <= '1';
out123 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(167) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out475_bufn <= '1';
out257_bufn <= '1';
out472_bufn <= '1';
out451_bufn <= '1';
out468_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out469 <= '1';
end if;
if state_cur(168) = '1' then
-- Next state
state_next(132) <= '1';
-- Next values for buffered outputs
out357_bufn <= '1';
out428_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out283 <= '1';
end if;
if state_cur(169) = '1' then
-- Next state
state_next(225) <= '1';
-- Next values for buffered outputs
out554_bufn <= '1';
out284_bufn <= '1';
out333_bufn <= '1';
-- Assignment of non-buffered outputs
out137 <= '1';
out135 <= '1';
out484 <= '1';
out283 <= '1';
end if;
if state_cur(170) = '1' then
-- Next state
state_next(152) <= '1';
-- Next values for buffered outputs
out353_bufn <= '1';
out284_bufn <= '1';
out138_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(171) = '1' then
-- Next state
state_next(167) <= '1';
-- Next values for buffered outputs
out475_bufn <= '1';
out257_bufn <= '1';
out472_bufn <= '1';
out451_bufn <= '1';
out468_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(172) = '1' then
-- Next state
state_next(187) <= '1';
-- Next values for buffered outputs
out521_bufn <= '1';
out284_bufn <= '1';
out150_bufn <= '1';
-- Assignment of non-buffered outputs
out137 <= '1';
out135 <= '1';
out488 <= '1';
out286 <= '1';
end if;
if state_cur(173) = '1' then
-- Next state
state_next(84) <= '1';
-- Next values for buffered outputs
out293_bufn <= '1';
out281_bufn <= '1';
out174_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(174) = '1' then
if rtmcmp174 = '1' then
-- Next state
state_next(171) <= '1';
-- Next values for buffered outputs
out438_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out137 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(174) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out229_bufn <= '1';
out357_bufn <= '1';
out407_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out491 <= '1';
end if;
if state_cur(175) = '1' then
-- Next state
state_next(174) <= '1';
-- Next values for buffered outputs
out229_bufn <= '1';
out357_bufn <= '1';
out407_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(176) = '1' then
-- Next state
state_next(175) <= '1';
-- Next values for buffered outputs
out495_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(177) = '1' then
-- Next state
state_next(176) <= '1';
-- Next values for buffered outputs
out437_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(178) = '1' then
-- Next state
state_next(145) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out99 <= '1';
out101 <= '1';
end if;
if state_cur(179) = '1' then
-- Next state
state_next(177) <= '1';
-- Next values for buffered outputs
out496_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out498 <= '1';
out46 <= '1';
out283 <= '1';
end if;
if state_cur(180) = '1' then
-- Next state
state_next(179) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out497_bufn <= '1';
out436_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(181) = '1' then
if rtmcmp181 = '1' then
-- Next state
state_next(180) <= '1';
-- Next values for buffered outputs
out499_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out112 <= '1';
out142 <= '1';
out99 <= '1';
out54 <= '1';
out135 <= '1';
out123 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(181) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out260_bufn <= '1';
out500_bufn <= '1';
out435_bufn <= '1';
out395_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out501 <= '1';
end if;
if state_cur(182) = '1' then
-- Next state
state_next(181) <= '1';
-- Next values for buffered outputs
out260_bufn <= '1';
out500_bufn <= '1';
out435_bufn <= '1';
out395_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(183) = '1' then
if rtmcmp183 = '1' then
-- Next state
state_next(182) <= '1';
-- Next values for buffered outputs
out457_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out137 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(183) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out472_bufn <= '1';
out401_bufn <= '1';
out512_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out513 <= '1';
end if;
if state_cur(184) = '1' then
-- Next state
state_next(183) <= '1';
-- Next values for buffered outputs
out472_bufn <= '1';
out401_bufn <= '1';
out512_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(185) = '1' then
-- Next state
state_next(92) <= '1';
-- Next values for buffered outputs
out323_bufn <= '1';
out284_bufn <= '1';
out217_bufn <= '1';
-- Assignment of non-buffered outputs
out105 <= '1';
out101 <= '1';
out283 <= '1';
end if;
if state_cur(186) = '1' then
-- Next state
state_next(107) <= '1';
-- Next values for buffered outputs
out366_bufn <= '1';
out315_bufn <= '1';
out281_bufn <= '1';
out183_bufn <= '1';
-- Assignment of non-buffered outputs
out142 <= '1';
out519 <= '1';
out286 <= '1';
end if;
if state_cur(187) = '1' then
-- Next state
state_next(185) <= '1';
-- Next values for buffered outputs
out290_bufn <= '1';
out281_bufn <= '1';
out248_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out130 <= '1';
out522 <= '1';
out286 <= '1';
end if;
if state_cur(188) = '1' then
-- Next state
state_next(184) <= '1';
-- Next values for buffered outputs
out517_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(189) = '1' then
-- Next state
state_next(190) <= '1';
-- Next values for buffered outputs
out526_bufn <= '1';
out284_bufn <= '1';
out213_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(190) = '1' then
-- Next state
state_next(173) <= '1';
-- Next values for buffered outputs
out468_bufn <= '1';
out284_bufn <= '1';
out143_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(191) = '1' then
-- Next state
state_next(188) <= '1';
-- Next values for buffered outputs
out524_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(192) = '1' then
-- Next state
state_next(191) <= '1';
-- Next values for buffered outputs
out487_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out527 <= '1';
out44 <= '1';
out283 <= '1';
end if;
if state_cur(193) = '1' then
-- Next state
state_next(192) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out312_bufn <= '1';
out433_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(194) = '1' then
if rtmcmp194 = '1' then
-- Next state
state_next(193) <= '1';
-- Next values for buffered outputs
out351_bufn <= '1';
out313_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out112 <= '1';
out142 <= '1';
out99 <= '1';
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(194) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out263_bufn <= '1';
out531_bufn <= '1';
out497_bufn <= '1';
out521_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out528 <= '1';
end if;
if state_cur(195) = '1' then
-- Next state
state_next(194) <= '1';
-- Next values for buffered outputs
out263_bufn <= '1';
out531_bufn <= '1';
out497_bufn <= '1';
out521_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(196) = '1' then
-- Next state
state_next(221) <= '1';
-- Next values for buffered outputs
out281_bufn <= '1';
-- Assignment of non-buffered outputs
out130 <= '1';
out540 <= '1';
out286 <= '1';
end if;
if state_cur(197) = '1' then
if rtmcmp197 = '1' then
-- Next state
state_next(195) <= '1';
-- Next values for buffered outputs
out394_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out137 <= '1';
out125 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(197) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out500_bufn <= '1';
out435_bufn <= '1';
out314_bufn <= '1';
out293_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out542 <= '1';
end if;
if state_cur(198) = '1' then
-- Next state
state_next(197) <= '1';
-- Next values for buffered outputs
out500_bufn <= '1';
out435_bufn <= '1';
out314_bufn <= '1';
out293_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(199) = '1' then
-- Next state
state_next(198) <= '1';
-- Next values for buffered outputs
out326_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(200) = '1' then
-- Next state
state_next(199) <= '1';
-- Next values for buffered outputs
out341_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(201) = '1' then
-- Next state
state_next(200) <= '1';
-- Next values for buffered outputs
out287_bufn <= '1';
out285_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out544 <= '1';
out42 <= '1';
out283 <= '1';
end if;
if state_cur(202) = '1' then
-- Next state
state_next(201) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out318_bufn <= '1';
out322_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(203) = '1' then
if rtmcmp203 = '1' then
-- Next state
state_next(202) <= '1';
-- Next values for buffered outputs
out483_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out142 <= '1';
out112 <= '1';
out99 <= '1';
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(203) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out393_bufn <= '1';
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out518_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out545 <= '1';
end if;
if state_cur(204) = '1' then
-- Next state
state_next(203) <= '1';
-- Next values for buffered outputs
out393_bufn <= '1';
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out518_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(205) = '1' then
if rtmcmp205 = '1' then
-- Next state
state_next(204) <= '1';
-- Next values for buffered outputs
out554_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out137 <= '1';
out125 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(205) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out531_bufn <= '1';
out426_bufn <= '1';
out461_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out555 <= '1';
end if;
if state_cur(206) = '1' then
-- Next state
state_next(205) <= '1';
-- Next values for buffered outputs
out531_bufn <= '1';
out426_bufn <= '1';
out461_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(207) = '1' then
-- Next state
state_next(206) <= '1';
-- Next values for buffered outputs
out526_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(208) = '1' then
-- Next state
state_next(207) <= '1';
-- Next values for buffered outputs
out525_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(209) = '1' then
-- Next state
state_next(208) <= '1';
-- Next values for buffered outputs
out466_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out559 <= '1';
out40 <= '1';
out283 <= '1';
end if;
if state_cur(210) = '1' then
-- Next state
state_next(209) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out417_bufn <= '1';
out294_bufn <= '1';
out282_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(211) = '1' then
-- Next state
state_next(224) <= '1';
-- Next values for buffered outputs
out459_bufn <= '1';
out284_bufn <= '1';
out201_bufn <= '1';
-- Assignment of non-buffered outputs
out560 <= '1';
out286 <= '1';
end if;
if state_cur(212) = '1' then
-- Next state
state_next(147) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out561 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(213) = '1' then
-- Next state
state_next(134) <= '1';
-- Next values for buffered outputs
out433_bufn <= '1';
out281_bufn <= '1';
out426_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(214) = '1' then
-- Next state
state_next(140) <= '1';
-- Next values for buffered outputs
out351_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(215) = '1' then
if rtmcmp215 = '1' then
-- Next state
state_next(127) <= '1';
-- Next values for buffered outputs
out404_bufn <= '1';
out418_bufn <= '1';
out281_bufn <= '1';
out417_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out123 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(215) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out562_bufn <= '1';
out342_bufn <= '1';
out284_bufn <= '1';
out404_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out563 <= '1';
end if;
if state_cur(216) = '1' then
-- Next state
state_next(214) <= '1';
-- Next values for buffered outputs
out482_bufn <= '1';
out481_bufn <= '1';
out357_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(217) = '1' then
-- Next state
state_next(216) <= '1';
-- Next values for buffered outputs
out444_bufn <= '1';
out281_bufn <= '1';
out354_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(218) = '1' then
-- Next state
state_next(217) <= '1';
-- Next values for buffered outputs
out566_bufn <= '1';
out281_bufn <= '1';
out229_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(219) = '1' then
-- Next state
state_next(218) <= '1';
-- Next values for buffered outputs
out440_bufn <= '1';
out281_bufn <= '1';
out162_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(220) = '1' then
-- Next state
state_next(219) <= '1';
-- Next values for buffered outputs
out349_bufn <= '1';
out284_bufn <= '1';
out257_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(221) = '1' then
-- Next state
state_next(223) <= '1';
-- Next values for buffered outputs
out325_bufn <= '1';
out284_bufn <= '1';
out366_bufn <= '1';
-- Assignment of non-buffered outputs
out112 <= '1';
out567 <= '1';
out283 <= '1';
end if;
if state_cur(222) = '1' then
-- Next state
state_next(220) <= '1';
-- Next values for buffered outputs
out464_bufn <= '1';
out281_bufn <= '1';
out451_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(223) = '1' then
-- Next state
state_next(161) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out414_bufn <= '1';
out446_bufn <= '1';
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
out286 <= '1';
end if;
if state_cur(224) = '1' then
-- Next state
state_next(222) <= '1';
-- Next values for buffered outputs
out460_bufn <= '1';
out281_bufn <= '1';
out232_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(225) = '1' then
-- Next state
state_next(79) <= '1';
-- Next values for buffered outputs
out282_bufn <= '1';
out281_bufn <= '1';
out280_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(226) = '1' then
-- Next state
state_next(122) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out570 <= '1';
out412 <= '1';
end if;
if state_cur(227) = '1' then
-- Next state
state_next(116) <= '1';
-- Next values for buffered outputs
out400_bufn <= '1';
out284_bufn <= '1';
out131_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(228) = '1' then
-- Next state
state_next(136) <= '1';
-- Next values for buffered outputs
out428_bufn <= '1';
out284_bufn <= '1';
out126_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(229) = '1' then
-- Next state
state_next(138) <= '1';
-- Next values for buffered outputs
out437_bufn <= '1';
out281_bufn <= '1';
out235_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(230) = '1' then
-- Next state
state_next(231) <= '1';
-- Next values for buffered outputs
out499_bufn <= '1';
out281_bufn <= '1';
out497_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(231) = '1' then
-- Next state
state_next(155) <= '1';
-- Next values for buffered outputs
out457_bufn <= '1';
out284_bufn <= '1';
out364_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(232) = '1' then
-- Next state
state_next(213) <= '1';
-- Next values for buffered outputs
out524_bufn <= '1';
out281_bufn <= '1';
out238_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(233) = '1' then
-- Next state
state_next(141) <= '1';
-- Next values for buffered outputs
out440_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out118 <= '1';
out283 <= '1';
end if;
if state_cur(234) = '1' then
-- Next state
state_next(129) <= '1';
-- Next values for buffered outputs
out346_bufn <= '1';
out31_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out572 <= '1';
out412 <= '1';
end if;
if state_cur(235) = '1' then
-- Next state
state_next(131) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out575 <= '1';
out363 <= '1';
end if;
if state_cur(236) = '1' then
-- Next state
state_next(234) <= '1';
-- Next values for buffered outputs
out280_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out577 <= '1';
out40 <= '1';
out21 <= '1';
out412 <= '1';
end if;
if state_cur(237) = '1' then
-- Next state
state_next(235) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out578 <= '1';
out363 <= '1';
end if;
if state_cur(238) = '1' then
-- Next state
state_next(236) <= '1';
-- Next values for buffered outputs
out562_bufn <= '1';
out35_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out580 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(239) = '1' then
-- Next state
state_next(238) <= '1';
-- Next values for buffered outputs
out446_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(240) = '1' then
-- Next state
state_next(165) <= '1';
-- Next values for buffered outputs
out466_bufn <= '1';
out284_bufn <= '1';
out273_bufn <= '1';
-- Assignment of non-buffered outputs
out581 <= '1';
out130 <= '1';
out283 <= '1';
end if;
-- Reset input
if reset = '1' then
-- Set the reset state
state_next <= (7 => '1', others => '0');
-- Note: Resetting all buffers for outputs here is not necessary.
-- It would cost hardware. They will be reset at the next clock front.
-- Retiming: counters
rtmcounter0_next <= (others => '0');
-- Reset state: set the buffered outputs
end if;
end process;
-- Assignment of buffered outputs
out122 <= out122_buf;
out36 <= out36_buf;
out49 <= out49_buf;
out35 <= out35_buf;
out27 <= out27_buf;
out16 <= out16_buf;
out25 <= out25_buf;
out20 <= out20_buf;
out57 <= out57_buf;
out23 <= out23_buf;
out136 <= out136_buf;
out0 <= out0_buf;
out134 <= out134_buf;
out13 <= out13_buf;
out131 <= out131_buf;
out129 <= out129_buf;
out111 <= out111_buf;
out31 <= out31_buf;
out126 <= out126_buf;
out106 <= out106_buf;
out124 <= out124_buf;
out138 <= out138_buf;
out141 <= out141_buf;
out143 <= out143_buf;
out146 <= out146_buf;
out150 <= out150_buf;
out153 <= out153_buf;
out155 <= out155_buf;
out158 <= out158_buf;
out162 <= out162_buf;
out165 <= out165_buf;
out168 <= out168_buf;
out171 <= out171_buf;
out174 <= out174_buf;
out178 <= out178_buf;
out181 <= out181_buf;
out183 <= out183_buf;
out197 <= out197_buf;
out201 <= out201_buf;
out204 <= out204_buf;
out207 <= out207_buf;
out210 <= out210_buf;
out213 <= out213_buf;
out217 <= out217_buf;
out220 <= out220_buf;
out222 <= out222_buf;
out225 <= out225_buf;
out229 <= out229_buf;
out232 <= out232_buf;
out235 <= out235_buf;
out238 <= out238_buf;
out241 <= out241_buf;
out245 <= out245_buf;
out248 <= out248_buf;
out250 <= out250_buf;
out253 <= out253_buf;
out257 <= out257_buf;
out260 <= out260_buf;
out263 <= out263_buf;
out266 <= out266_buf;
out269 <= out269_buf;
out273 <= out273_buf;
out276 <= out276_buf;
out278 <= out278_buf;
out280 <= out280_buf;
out281 <= out281_buf;
out282 <= out282_buf;
out284 <= out284_buf;
out285 <= out285_buf;
out287 <= out287_buf;
out288 <= out288_buf;
out289 <= out289_buf;
out290 <= out290_buf;
out291 <= out291_buf;
out292 <= out292_buf;
out293 <= out293_buf;
out294 <= out294_buf;
out295 <= out295_buf;
out296 <= out296_buf;
out312 <= out312_buf;
out313 <= out313_buf;
out314 <= out314_buf;
out315 <= out315_buf;
out318 <= out318_buf;
out322 <= out322_buf;
out323 <= out323_buf;
out324 <= out324_buf;
out325 <= out325_buf;
out326 <= out326_buf;
out327 <= out327_buf;
out328 <= out328_buf;
out333 <= out333_buf;
out341 <= out341_buf;
out342 <= out342_buf;
out343 <= out343_buf;
out344 <= out344_buf;
out346 <= out346_buf;
out349 <= out349_buf;
out351 <= out351_buf;
out352 <= out352_buf;
out353 <= out353_buf;
out354 <= out354_buf;
out357 <= out357_buf;
out361 <= out361_buf;
out364 <= out364_buf;
out366 <= out366_buf;
out371 <= out371_buf;
out393 <= out393_buf;
out394 <= out394_buf;
out395 <= out395_buf;
out400 <= out400_buf;
out401 <= out401_buf;
out404 <= out404_buf;
out407 <= out407_buf;
out408 <= out408_buf;
out409 <= out409_buf;
out410 <= out410_buf;
out413 <= out413_buf;
out414 <= out414_buf;
out417 <= out417_buf;
out418 <= out418_buf;
out422 <= out422_buf;
out426 <= out426_buf;
out428 <= out428_buf;
out431 <= out431_buf;
out433 <= out433_buf;
out434 <= out434_buf;
out435 <= out435_buf;
out436 <= out436_buf;
out437 <= out437_buf;
out438 <= out438_buf;
out440 <= out440_buf;
out444 <= out444_buf;
out446 <= out446_buf;
out451 <= out451_buf;
out457 <= out457_buf;
out458 <= out458_buf;
out459 <= out459_buf;
out460 <= out460_buf;
out461 <= out461_buf;
out463 <= out463_buf;
out464 <= out464_buf;
out466 <= out466_buf;
out468 <= out468_buf;
out472 <= out472_buf;
out475 <= out475_buf;
out481 <= out481_buf;
out482 <= out482_buf;
out483 <= out483_buf;
out487 <= out487_buf;
out495 <= out495_buf;
out496 <= out496_buf;
out497 <= out497_buf;
out499 <= out499_buf;
out500 <= out500_buf;
out512 <= out512_buf;
out517 <= out517_buf;
out518 <= out518_buf;
out521 <= out521_buf;
out524 <= out524_buf;
out525 <= out525_buf;
out526 <= out526_buf;
out531 <= out531_buf;
out554 <= out554_buf;
out562 <= out562_buf;
out566 <= out566_buf;
-- Retiming: the comparators
rtmcmp90 <= '1' when state_cur(90) = '1' and rtmcounter0 = 1 else '0';
rtmcmp95 <= '1' when state_cur(95) = '1' and rtmcounter0 = 1 else '0';
rtmcmp98 <= '1' when state_cur(98) = '1' and rtmcounter0 = 1 else '0';
rtmcmp104 <= '1' when state_cur(104) = '1' and rtmcounter0 = 1 else '0';
rtmcmp148 <= '1' when state_cur(148) = '1' and rtmcounter0 = 1 else '0';
rtmcmp167 <= '1' when state_cur(167) = '1' and rtmcounter0 = 1 else '0';
rtmcmp174 <= '1' when state_cur(174) = '1' and rtmcounter0 = 1 else '0';
rtmcmp181 <= '1' when state_cur(181) = '1' and rtmcounter0 = 1 else '0';
rtmcmp183 <= '1' when state_cur(183) = '1' and rtmcounter0 = 1 else '0';
rtmcmp194 <= '1' when state_cur(194) = '1' and rtmcounter0 = 1 else '0';
rtmcmp197 <= '1' when state_cur(197) = '1' and rtmcounter0 = 1 else '0';
rtmcmp203 <= '1' when state_cur(203) = '1' and rtmcounter0 = 1 else '0';
rtmcmp205 <= '1' when state_cur(205) = '1' and rtmcounter0 = 1 else '0';
rtmcmp215 <= '1' when state_cur(215) = '1' and rtmcounter0 = 1 else '0';
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug017/loop1.vhdl | 2 | 286 | entity loop1 is
end;
architecture behav of loop1 is
begin
process
variable i : natural := 0;
begin
report "hello";
while i < 10 loop
wait for 1 ns;
report "hello2";
i := i + 1;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2090.vhd | 4 | 2275 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2090.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02090ent IS
END c07s02b04x00p20n01i02090ent;
ARCHITECTURE c07s02b04x00p20n01i02090arch OF c07s02b04x00p20n01i02090ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_8 is boolean_v (1 to 8);
SUBTYPE boolean_4 is boolean_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : boolean_4;
variable l_operand : boolean_4 := (true,false,true,false);
variable r_operand : boolean_4 := (false,false,true,true);
alias l_alias : boolean_v (1 to 2) is l_operand (2 to 3);
alias r_alias : boolean_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 5 ns;
assert NOT((result = (false,true,true,true)) and (result(1) = false))
report "***PASSED TEST: c07s02b04x00p20n01i02090"
severity NOTE;
assert ((result = (false,true,true,true)) and (result(1) = false))
report "***FAILED TEST: c07s02b04x00p20n01i02090 - Concatenation of two BOOLEAN aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02090arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc632.vhd | 4 | 2083 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc632.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:48 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00632ent IS
END c03s04b01x00p01n01i00632ent;
ARCHITECTURE c03s04b01x00p01n01i00632arch OF c03s04b01x00p01n01i00632ent IS
type four_value is ('Z','0','1','X');
subtype binary is four_value range '0' to '1';
type binary_file is file of binary;
constant C38 : binary := '0';
BEGIN
TESTING: PROCESS
file filein : binary_file open write_mode is "iofile.38";
BEGIN
for i in 1 to 100 loop
write(filein, C38);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00632 - The output file will be verified by test s010278.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00632arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/perf02/qq2_code2_table.vhd | 3 | 1199 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq2_code2_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end qq2_code2_table;
architecture augh of qq2_code2_table is
-- Embedded RAM
type ram_type is array (0 to 3) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111110001100010000", "11111111111111111111100110110000", "00000000000000000001110011110000", "00000000000000000000011001010000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg-b.vhd | 4 | 1222 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_reg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk) is
begin
if rising_edge(clk) then
q <= d;
end if;
end process behavior;
end architecture behavioral;
| gpl-2.0 |
pmh92/Proyecto-OFDM | test/PRBS_tb.vhd | 1 | 1211 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY prbs_tb IS
END prbs_tb;
ARCHITECTURE behavior OF prbs_tb IS
-- Component Declaration
COMPONENT PRBS
PORT ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
output : out STD_LOGIC);
END COMPONENT;
SIGNAL clk : std_logic;
SIGNAL rst : std_logic;
SIGNAL enable : std_logic;
SIGNAL output : STD_LOGIC;
CONSTANT clk_period: TIME := 10 ns;
BEGIN
-- Component Instantiation
uut: PRBS PORT MAP(
clk => clk,
rst => rst,
enable => enable,
output => output
);
-- Generar los estimulos
stim_process : PROCESS
BEGIN
rst <= '1';
enable <= '0';
wait for 100 ns;
rst <= '0';
wait until rising_edge(clk);
FOR i IN 1 TO 25 LOOP
enable <= '1';
wait for clk_period;
enable <= '0';
wait for 3*clk_period;
END LOOP;
END PROCESS stim_process;
-- Generar el reloj
clk_process : PROCESS
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
END PROCESS clk_process;
END;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue238/rec2.vhdl | 2 | 384 | entity rec2 is
end;
architecture behav of rec2 is
type rec1 is record
a : natural;
end record;
type rec1_arr is array (natural range <>) of rec1;
function resolve (a : rec1_arr) return rec1 is
begin
return (a => 0);
end resolve;
subtype srec1 is resolve rec1;
begin
process
variable a : srec1;
begin
a.a := 5;
wait;
end process;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1746.vhd | 4 | 2047 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1746.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p06n03i01746ent IS
END c09s05b00x00p06n03i01746ent;
ARCHITECTURE c09s05b00x00p06n03i01746arch OF c09s05b00x00p06n03i01746ent IS
type a is array (1 to 4) of boolean;
type arrbool is array (positive range <>) of boolean;
function F (BB: arrbool) return boolean is
begin
return false;
end;
signal i, j : F boolean bus := true;
signal k, l : boolean := true;
signal m : a := (true, false, true, false);
BEGIN
(i, j, k, l) <= transport a'(m(1), m(2), m(3), m(4)) after 10 ns;
-- Failure_here
-- i and j are guarded signals and k and l are unguarded signals.
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b00x00p06n03i01746 - Guarded signal and Ungarded signal is mixed used."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b00x00p06n03i01746arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc3124.vhd | 4 | 6569 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3124.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x02p01n01i03124ent_a IS
generic ( socket_g1 : Boolean;
socket_g2 : Bit;
socket_g3 : character;
socket_g4 : severity_level;
socket_g5 : integer;
socket_g6 : real;
socket_g7 : time;
socket_g8 : natural;
socket_g9 : positive
);
port ( socket_p1 : inout Boolean;
socket_p2 : inout Bit;
socket_p3 : inout character;
socket_p4 : inout severity_level;
socket_p5 : inout integer;
socket_p6 : inout real;
socket_p7 : inout time;
socket_p8 : inout natural;
socket_p9 : inout positive
);
END c05s02b01x02p01n01i03124ent_a;
ARCHITECTURE c05s02b01x02p01n01i03124arch_a OF c05s02b01x02p01n01i03124ent_a IS
BEGIN
socket_p1 <= socket_g1 after 22 ns;
socket_p2 <= socket_g2 after 22 ns;
socket_p3 <= socket_g3 after 22 ns;
socket_p4 <= socket_g4 after 22 ns;
socket_p5 <= socket_g5 after 22 ns;
socket_p6 <= socket_g6 after 22 ns;
socket_p7 <= socket_g7 after 22 ns;
socket_p8 <= socket_g8 after 22 ns;
socket_p9 <= socket_g9 after 22 ns;
END c05s02b01x02p01n01i03124arch_a;
ENTITY c05s02b01x02p01n01i03124ent IS
END c05s02b01x02p01n01i03124ent;
ARCHITECTURE c05s02b01x02p01n01i03124arch OF c05s02b01x02p01n01i03124ent IS
component ic_socket
generic ( socket_g1 : Boolean;
socket_g2 : Bit;
socket_g3 : character;
socket_g4 : severity_level;
socket_g5 : integer;
socket_g6 : real;
socket_g7 : time;
socket_g8 : natural;
socket_g9 : positive
);
port ( socket_p1 : inout Boolean;
socket_p2 : inout Bit;
socket_p3 : inout character;
socket_p4 : inout severity_level;
socket_p5 : inout integer;
socket_p6 : inout real;
socket_p7 : inout time;
socket_p8 : inout natural;
socket_p9 : inout positive
);
end component;
signal socket_p1 : Boolean;
signal socket_p2 : Bit;
signal socket_p3 : character;
signal socket_p4 : severity_level;
signal socket_p5 : integer;
signal socket_p6 : real;
signal socket_p7 : time;
signal socket_p8 : natural;
signal socket_p9 : positive;
BEGIN
instance : ic_socket
generic map ( true,
'1',
'$',
warning,
-100002,
-9.999,
20 ns,
23423,
4564576
)
port map ( socket_p1,
socket_p2,
socket_p3,
socket_p4,
socket_p5,
socket_p6,
socket_p7,
socket_p8,
socket_p9
);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( socket_p1 = true and
socket_p2 = '1' and
socket_p3 = '$' and
socket_p4 = warning and
socket_p5 = -100002 and
socket_p6 = -9.999 and
socket_p7 = 20 ns and
socket_p8 = 23423 and
socket_p9 = 4564576 )
report "***PASSED TEST: c05s02b01x02p01n01i03124"
severity NOTE;
assert ( socket_p1 = true and
socket_p2 = '1' and
socket_p3 = '$' and
socket_p4 = warning and
socket_p5 = -100002 and
socket_p6 = -9.999 and
socket_p7 = 20 ns and
socket_p8 = 23423 and
socket_p9 = 4564576 )
report "***FAILED TEST: c05s02b01x02p01n01i03124 - Positional association generic and port list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x02p01n01i03124arch;
configuration c05s02b01x02p01n01i03124cfg of c05s02b01x02p01n01i03124ent is
for c05s02b01x02p01n01i03124arch
for instance : ic_socket use entity work.c05s02b01x02p01n01i03124ent_a (c05s02b01x02p01n01i03124arch_a)
generic map ( true,
'1',
'$',
warning,
-100002,
-9.999,
20 ns,
23423,
4564576
)
port map ( socket_p1,
socket_p2,
socket_p3,
socket_p4,
socket_p5,
socket_p6,
socket_p7,
socket_p8,
socket_p9
);
end for;
end for;
end c05s02b01x02p01n01i03124cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1654.vhd | 4 | 2146 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1654.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s00b00x00p04n01i01654ent IS
END c09s00b00x00p04n01i01654ent;
ARCHITECTURE c09s00b00x00p04n01i01654arch OF c09s00b00x00p04n01i01654ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE -- force assertion violation
report "PASS: process TESTING executes."
severity NOTE;
assert FALSE
report "***PASSED TEST: c09s00b00x00p04n01i01654 - it is really uncertain that which assertion note appear first for different simulator."
severity NOTE;
wait;
END PROCESS TESTING;
TEST: PROCESS
begin
assert FALSE
report "PASS: process TEST executes."
severity NOTE;
-- Note: It does not matter which process executes first. (The order
-- of process execution is not defined by the LRM, and dependence
-- on the execution order is not allowed.)
wait; -- wait forever
END PROCESS TEST;
END c09s00b00x00p04n01i01654arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2749.vhd | 4 | 1634 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2749.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p03n01i02749ent IS
END c13s07b00x00p03n01i02749ent;
ARCHITECTURE c13s07b00x00p03n01i02749arch OF c13s07b00x00p03n01i02749ent IS
BEGIN
TESTING: PROCESS
variable bit_str : bit_vector (1 to 8) := b"_0101_0101";
BEGIN
assert FALSE
report "***FAILED TEST: c13s07b00x00p03n01i02749 - Leading underscores are not allowed in bit values."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p03n01i02749arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd | 4 | 1617 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book
entity reg is
port ( d : in bit_vector; q : out bit_vector; -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end entity reg;
-- end code from book
architecture test of reg is
begin
q <= d;
end architecture test;
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
-- code from book
signal small_data : bit_vector(0 to 7);
signal large_data : bit_vector(0 to 15);
-- . . .
-- end code from book
begin
-- code from book
problem_reg : entity work.reg
port map ( d => small_data, q => large_data, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- end code from book
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/vector.d/v_split7.vhd | 2 | 1357 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split7 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v_split7;
architecture augh of v_split7 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue258/range_tb.vhdl | 2 | 468 | entity range_tb is
end range_tb;
architecture tb of range_tb is
begin
process
variable i : integer;
begin
-- Behaves like 32-bit arithmetic with modular truncation
i := integer'low;
report integer'image(i);
i := integer'low-1;
report integer'image(i);
-- Produces the error "overflow detected"
i := integer'low;
report integer'image(i);
i := i-1;
report integer'image(i);
wait; -- forever
end process;
end tb;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2197.vhd | 4 | 1828 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2197.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02197ent IS
END c07s02b00x00p01n02i02197ent;
ARCHITECTURE c07s02b00x00p01n02i02197arch OF c07s02b00x00p01n02i02197ent IS
BEGIN
TESTING: PROCESS
type A_ARRAY is array (1 to 2) of CHARACTER;
variable I : INTEGER;
variable R : REAL;
variable B : BOOLEAN;
variable A : A_ARRAY;
BEGIN
R := abs - R; -- Failure_here
-- SYNTAX ERROR: signed operator cannot follow misc. operator.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02197 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02197arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc618.vhd | 4 | 2929 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc618.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:44 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:06 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:23 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00618ent IS
END c03s04b01x00p01n01i00618ent;
ARCHITECTURE c03s04b01x00p01n01i00618arch OF c03s04b01x00p01n01i00618ent IS
constant C4 : real := 3.0;
type real_vector is array (natural range <>) of real;
subtype real_vector_st is real_vector(0 to 15);
type real_vector_st_file is file of real_vector_st;
constant C27 : real_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : real_vector_st_file open read_mode is "iofile.31";
variable v : real_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00618"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00618 - File reading operation (real_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00618arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1729.vhd | 4 | 1808 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1729.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s03b00x00p02n01i01729ent IS
END c09s03b00x00p02n01i01729ent;
ARCHITECTURE c09s03b00x00p02n01i01729arch OF c09s03b00x00p02n01i01729ent IS
procedure check (x: in integer; y: in boolean) is
begin
assert NOT( x=3 and y=true )
report "***PASSED TEST: c09s03b00x00p02n01i01729"
severity NOTE;
assert ( x=3 and y=true )
report "***FAILED TEST: c09s03b00x00p02n01i01729 - A label can be used before a procedure call statement."
severity ERROR;
end;
signal p: integer := 3;
signal q: boolean := true;
BEGIN
L1 : check (p,q); -- No_failure_here
END c09s03b00x00p02n01i01729arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3123.vhd | 4 | 6633 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3123.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x02p01n01i03123ent_a IS
generic ( socket_g1 : Boolean;
socket_g2 : Bit;
socket_g3 : character;
socket_g4 : severity_level;
socket_g5 : integer;
socket_g6 : real;
socket_g7 : time;
socket_g8 : natural;
socket_g9 : positive
);
port ( socket_p1 : inout Boolean;
socket_p2 : inout Bit;
socket_p3 : inout character;
socket_p4 : inout severity_level;
socket_p5 : inout integer;
socket_p6 : inout real;
socket_p7 : inout time;
socket_p8 : inout natural;
socket_p9 : inout positive
);
END c05s02b01x02p01n01i03123ent_a;
ARCHITECTURE c05s02b01x02p01n01i03123arch_a OF c05s02b01x02p01n01i03123ent_a IS
BEGIN
socket_p1 <= socket_g1 after 22 ns;
socket_p2 <= socket_g2 after 22 ns;
socket_p3 <= socket_g3 after 22 ns;
socket_p4 <= socket_g4 after 22 ns;
socket_p5 <= socket_g5 after 22 ns;
socket_p6 <= socket_g6 after 22 ns;
socket_p7 <= socket_g7 after 22 ns;
socket_p8 <= socket_g8 after 22 ns;
socket_p9 <= socket_g9 after 22 ns;
END c05s02b01x02p01n01i03123arch_a;
ENTITY c05s02b01x02p01n01i03123ent IS
END c05s02b01x02p01n01i03123ent;
ARCHITECTURE c05s02b01x02p01n01i03123arch OF c05s02b01x02p01n01i03123ent IS
component ic_socket
generic ( socket_g1 : Boolean;
socket_g2 : Bit;
socket_g3 : character;
socket_g4 : severity_level;
socket_g5 : integer;
socket_g6 : real;
socket_g7 : time;
socket_g8 : natural;
socket_g9 : positive
);
port ( socket_p1 : inout Boolean;
socket_p2 : inout Bit;
socket_p3 : inout character;
socket_p4 : inout severity_level;
socket_p5 : inout integer;
socket_p6 : inout real;
socket_p7 : inout time;
socket_p8 : inout natural;
socket_p9 : inout positive
);
end component;
signal socket_p1 : Boolean;
signal socket_p2 : Bit;
signal socket_p3 : character;
signal socket_p4 : severity_level;
signal socket_p5 : integer;
signal socket_p6 : real;
signal socket_p7 : time;
signal socket_p8 : natural;
signal socket_p9 : positive;
BEGIN
instance : ic_socket
generic map ( true,
'1',
'$',
warning,
-100002,
-9.999,
20 ns,
23423,
4564576
)
port map ( socket_p1,
socket_p2,
socket_p3,
socket_p4,
socket_p5,
socket_p6,
socket_p7,
socket_p8,
socket_p9
);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( socket_p1 = true and
socket_p2 = '1' and
socket_p3 = '$' and
socket_p4 = warning and
socket_p5 = -100002 and
socket_p6 = -9.999 and
socket_p7 = 20 ns and
socket_p8 = 23423 and
socket_p9 = 4564576 )
report "***PASSED TEST: c05s02b01x02p01n01i03123"
severity NOTE;
assert ( socket_p1 = true and
socket_p2 = '1' and
socket_p3 = '$' and
socket_p4 = warning and
socket_p5 = -100002 and
socket_p6 = -9.999 and
socket_p7 = 20 ns and
socket_p8 = 23423 and
socket_p9 = 4564576 )
report "***FAILED TEST: c05s02b01x02p01n01i03123 - Positional association generic and port list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x02p01n01i03123arch;
configuration c05s02b01x02p01n01i03123cfg of c05s02b01x02p01n01i03123ent is
for c05s02b01x02p01n01i03123arch
for instance : ic_socket use entity work.c05s02b01x02p01n01i03123ent_a (c05s02b01x02p01n01i03123arch_a)
generic map ( socket_g1,
socket_g2,
socket_g3,
socket_g4,
socket_g5,
socket_g6,
socket_g7,
socket_g8,
socket_g9
)
port map ( socket_p1,
socket_p2,
socket_p3,
socket_p4,
socket_p5,
socket_p6,
socket_p7,
socket_p8,
socket_p9
);
end for;
end for;
end c05s02b01x02p01n01i03123cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc730.vhd | 4 | 1657 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc730.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p04n01i00730ent IS
port ( signal s : bit
);
port ( signal t : bit -- illegal second port clause
);
END c01s01b01x00p04n01i00730ent;
ARCHITECTURE c01s01b01x00p04n01i00730arch OF c01s01b01x00p04n01i00730ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p04n01i00730 - Extra port clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p04n01i00730arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/prog.vhd | 2 | 2867 | --test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity prog is
port(
clock : in std_logic;
reset : in std_logic;
step : in std_logic;
instr_next : out instruction
);
end prog;
architecture rtl of prog is
signal instr_n : instruction := instr_rst;
--Table describing fsm behavior
constant fsm_behavior : table_behavior := (
--##PROGRAM_GOES_DOWN_HERE##--
0 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
1 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
2 => (state => Sig_start, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
3 => (state => Ack_data, context_uut => "01", arg => to_unsigned(64,ARG_WIDTH)),
4 => (state => Cp_search, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
5 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
6 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
7 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
8 => (state => Sig_start, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
9 => (state => Ack_data, context_uut => "10", arg => to_unsigned(64,ARG_WIDTH)),
10 => (state => Running, context_uut => "10", arg => to_unsigned(20,ARG_WIDTH)),
11 => (state => Cp_search, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
12 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
13 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
14 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
15 => (state => Rest_ini0, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
16 => (state => Waitfor, context_uut => "01", arg => to_unsigned(64,ARG_WIDTH)),
17 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
18 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
19 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
20 => (state => Rest_ini0, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
21 => (state => Waitfor, context_uut => "10", arg => to_unsigned(64,ARG_WIDTH)),
22 => (state => Stop, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
--##PROGRAM_GOES_OVER_HERE##--
others => instr_rst);
signal pc : unsigned(PC_SIZE - 1 downto 0) := (others => '0');
begin
drive_state : process (reset,clock) is
begin
if reset = '1' then
instr_n <= instr_rst;
pc <= (others => '0');
elsif rising_edge(clock) then
if (step = '1') then
pc <= pc + 1;
end if;
instr_n <= fsm_behavior(to_integer(pc));
end if;
end process drive_state;
--instr_next <= instr_n;
instr_next <= fsm_behavior(to_integer(pc));
end rtl;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1597.vhd | 4 | 1945 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1597.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01597ent IS
END c08s11b00x00p03n01i01597ent;
ARCHITECTURE c08s11b00x00p03n01i01597arch OF c08s11b00x00p03n01i01597ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
BEGIN
L1 :
for i in boolean loop
p := 5 + p;
L2 :
for j in 1 to 3 loop
exit ;
p := 0;
end loop L2 ;
end loop L1;
assert NOT( p=10 )
report "***PASSED TEST: c08s11b00x00p03n01i01597"
severity NOTE;
assert ( p=10 )
report "***FAILED TEST: c08s11b00x00p03n01i01597 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01597arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc718.vhd | 4 | 1540 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc718.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY IS
END c01s01b00x00p02n01i00718ent;
-- missing identifier
ARCHITECTURE c01s01b00x00p02n01i00718arch OF c01s01b00x00p02n01i00718ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b00x00p02n01i00718 - Missing identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b00x00p02n01i00718arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd | 4 | 2844 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
library IEEE; use IEEE.std_logic_1164.all;
entity tb_timer_w_stim is
end tb_timer_w_stim;
architecture TB_timer_w_stim of tb_timer_w_stim is
-- Component declarations
-- Signal declarations
terminal in_src, rc_ext : electrical;
signal trig, rst : std_ulogic;
signal tim_out : std_ulogic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_constant(ideal)
generic map(
level => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
R1 : entity work.resistor(simple)
generic map(
resistance => 10.0e3
)
port map(
pos => in_src,
neg => rc_ext
);
C1 : entity work.capacitor(ideal)
generic map(
cap => 10.0e-6
)
port map(
p1 => rc_ext,
p2 => electrical_ref
);
timer1 : entity work.timer(behavioral)
generic map(
threshold => 2.0,
clamp_on_resistance => 1.0e-3,
clamp_off_resistance => 1.0e6
)
port map(
trigger_n => trig,
reset => rst,
q => tim_out,
rc_ext => rc_ext
);
-- rst
P_rst :
process
begin
wait for 0.000 ns; rst <= '1';
wait for 1.000 ms; rst <= '0';
wait for 100.000 ms; rst <= '1';
wait for 1.000 ms; rst <= '0';
wait;
end process;
-- trig
P_trig :
process
begin
wait for 0.0 ns; trig <= '0';
wait for 5.000 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait for 40.0 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait for 40.0 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait;
end process;
end TB_timer_w_stim;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/vector.d/sub_189.vhd | 2 | 1740 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_189 is
port (
lt : out std_logic;
sign : in std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_189;
architecture augh of sub_189 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
lt <= not(tmp_ge);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2687.vhd | 4 | 1678 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2687.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p02n01i02687ent IS
--ERROR: only 1 decimal point allowed in real literal
constant A1: REAL:=3..57; -- failure_here
END c13s04b01x00p02n01i02687ent;
ARCHITECTURE c13s04b01x00p02n01i02687arch OF c13s04b01x00p02n01i02687ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b01x00p02n01i02687 - Two decimal points are not permitted in real literals."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p02n01i02687arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue258/length_tb1.vhdl | 2 | 285 | entity length_tb1 is
end length_tb1;
architecture tb of length_tb1 is
begin
process
variable s : string (1 to 4);
constant c : string := "hello";
begin
-- Behaves like 32-bit arithmetic with modular truncation
s := c;
wait; -- forever
end process;
end tb;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2567.vhd | 4 | 1730 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2567.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p02n01i02567ent IS
END c07s05b00x00p02n01i02567ent;
ARCHITECTURE c07s05b00x00p02n01i02567arch OF c07s05b00x00p02n01i02567ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(2E6 = (2E3*1E3))
report "***PASSED TEST: c07s05b00x00p02n01i02567"
severity NOTE;
assert (2E6 = (2E3*1E3))
report "***FAILED TEST: c07s05b00x00p02n01i02567 - The same operations are defined for the type universal_integer as for any integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p02n01i02567arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1863.vhd | 4 | 1934 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1863.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01863ent IS
END c07s01b00x00p08n01i01863ent;
ARCHITECTURE c07s01b00x00p08n01i01863arch OF c07s01b00x00p08n01i01863ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
blk : block(s_int = 0)
begin
s_int <= obus'right(blk) after 5 ns; -- block label illegal here
end block blk;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01863 - Block labels are not permitted as primaries in an attribute expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01863arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/dynamic_package_procedure_for_loop.vhdl | 4 | 658 | package pkg is
procedure iterate (
input : in bit_vector);
end pkg;
package body pkg is
procedure iterate (
input : in bit_vector) is
variable j : integer := input'range'left;
begin -- iterate
for i in input'range loop
assert i = j report "TEST FAILED" severity failure;
j := j + 1;
end loop; -- i in 1 to 10
assert j = input'range'right + 1 report "TEST FAILED" severity failure;
end iterate;
end pkg;
entity test is
end test;
architecture only of test is
begin -- only
doit: process
begin -- process doit
work.pkg.iterate("0000");
report "TEST PASSED";
wait;
end process doit;
end only;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_07.vhd | 4 | 1373 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_05_07 is
end entity fg_05_07;
architecture test of fg_05_07 is
constant T_pw : time := 10 ns;
signal clk : bit;
begin
-- code from book
clock_gen : process is
begin
clk <= '1' after T_pw, '0' after 2*T_pw;
wait until clk = '0';
end process clock_gen;
-- end code from book
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue293/repro.vhdl | 2 | 552 | library ieee;
use ieee.float_pkg.all;
entity tb_test is
generic (
runner_cfg : string := "h");
end tb_test;
architecture tb of tb_test is
begin
test_runner : process
-- Makes the implicit "=" directly visible.
alias fp32 is float32;
begin
assert not (zerofp = neg_zerofp) severity failure;
wait;
end process test_runner;
test_runner2 : process
-- Only the user-defined "=" is visible.
begin
assert zerofp = neg_zerofp severity failure;
wait;
end process test_runner2;
end;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug017/case2.vhdl | 2 | 615 | entity case1 is
end;
architecture behav of case1 is
type vec2 is array (natural range <>) of bit_vector (1 to 4);
constant vects : vec2 := (x"0", x"4", x"9", x"3", x"a");
begin
process
variable i : natural := 0;
begin
for i in vects'range loop
case vects (i) is
when "0100" =>
report "value is 4";
wait for 4 ns;
when "0011" =>
report "value is 3";
wait for 3 ns;
when others =>
report "unknown value";
wait for 1 ns;
end case;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket31/tb2.vhdl | 3 | 276 | entity Tb2 is
end;
architecture top of Tb2 is
function get_m15 return real is
begin
return -1.5;
end get_m15;
constant int_2 : INTEGER := natural(get_m15);
begin
assert FALSE report "17 - int_2 (natural(-1.5)): " & INTEGER'image(int_2) severity note;
end;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc722.vhd | 4 | 1767 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc722.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p03n01i00722ent IS
generic (( constant i : integer ); -- extra parenthesis
END c01s01b01x00p03n01i00722ent;
ARCHITECTURE c01s01b01x00p03n01i00722arch OF c01s01b01x00p03n01i00722ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p03n01i00722 - Unbalanced parenthesis in generic clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p03n01i00722arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2840.vhd | 4 | 1596 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2840.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity TO is
end TO;
ENTITY c13s09b00x00p99n01i02840ent IS
END c13s09b00x00p99n01i02840ent;
ARCHITECTURE c13s09b00x00p99n01i02840arch OF c13s09b00x00p99n01i02840ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02840 - Reserved word TO can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02840arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd | 4 | 1495 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_freq_detect is
end tb_freq_detect;
architecture TB_freq_detect of tb_freq_detect is
terminal in_src, freq_out : electrical;
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 200.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
freq1 : entity work.freq_detect(threshold_crossing)
port map(
input => in_src,
freq_out => freq_out
);
end TB_freq_detect;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2988.vhd | 4 | 1882 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2988.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p06n01i02988pkg is
constant var : integer := 5;
end c02s05b00x00p06n01i02988pkg;
ENTITY c02s05b00x00p06n01i02988ent IS
END c02s05b00x00p06n01i02988ent;
ARCHITECTURE c02s05b00x00p06n01i02988arch OF c02s05b00x00p06n01i02988ent IS
use work.c02s05b00x00p06n01i02988pkg.var;
BEGIN
TESTING: PROCESS
variable fin : time := 1 ns;
BEGIN
fin := fin * var;
assert NOT( fin = 5 ns )
report "***PASSED TEST: c02s05b00x00p06n01i02988"
severity NOTE;
assert ( fin = 5 ns )
report "***FAILED TEST: c02s05b00x00p06n01i02988 - Package declaration visibility test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p06n01i02988arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc967.vhd | 4 | 1803 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc967.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00967ent IS
END c06s03b00x00p05n01i00967ent;
ARCHITECTURE c06s03b00x00p05n01i00967arch OF c06s03b00x00p05n01i00967ent IS
BEGIN
TESTING: PROCESS
type rec_type is
record
x : bit;
y : integer;
z : boolean;
end record;
variable S1, S2 :rec_type;
variable h :bit;
BEGIN
S1.h := '1' ; -- h is not a field of the record.
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00967 - Suffix should denote an element of a record object or value."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00967arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_08.vhd | 4 | 2125 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
library star_lib;
--use star_lib.edge_triggered_dff;
use star_lib.all;
configuration full of counter is
for registered -- architecture of counter
for all : digit_register
use entity work.reg4(struct);
for struct -- architecture of reg4
for bit0 : flipflop
use entity edge_triggered_Dff(hi_fanout);
end for;
for others : flipflop
use entity edge_triggered_Dff(basic);
end for;
end for; -- end of architecture struct
end for;
-- . . . -- bindings for other component instances
end for; -- end of architecture registered
end configuration full;
-- not in book
entity fg_13_08 is
end entity fg_13_08;
use work.counter_types.all;
architecture test of fg_13_08 is
signal clk, clr : bit := '0';
signal q0, q1 : digit;
begin
dut : configuration work.full
port map ( clk => clk, clr => clr,
q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 20 ns;
clr_gen : clr <= '1' after 95 ns,
'0' after 135 ns;
end architecture test;
-- end not in book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_03.vhd | 4 | 1279 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_ch_21_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity controller is
end entity controller;
-- code from book
architecture instrumented of controller is
shared variable operation_count : natural := 0;
-- . . .
begin
-- . . .
end architecture instrumented;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc879.vhd | 4 | 2956 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc879.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s01b00x00p04n01i00879pkg_a is
-- define a subtype to be used elsewhere
subtype EIGHTIES is INTEGER range 1980 to 1989;
end c10s01b00x00p04n01i00879pkg_a;
package c10s01b00x00p04n01i00879pkg_b is
use WORK.c10s01b00x00p04n01i00879pkg_a.EIGHTIES;
function INTO_EIGHTIES ( ARG: in INTEGER ) return EIGHTIES;
end c10s01b00x00p04n01i00879pkg_b;
package body c10s01b00x00p04n01i00879pkg_b is
-- map any integer into range 1980 : 1989 based on one's digit
function INTO_EIGHTIES ( ARG: in INTEGER ) return EIGHTIES is
variable RETVAL: EIGHTIES;
begin
RETVAL := ( ( abs ARG ) mod 10 ) + 1980;
return RETVAL;
end INTO_EIGHTIES;
end c10s01b00x00p04n01i00879pkg_b;
ENTITY c10s01b00x00p04n01i00879ent IS
END c10s01b00x00p04n01i00879ent;
use WORK.c10s01b00x00p04n01i00879pkg_a.all;
use WORK.c10s01b00x00p04n01i00879pkg_b.all;
ARCHITECTURE c10s01b00x00p04n01i00879arch OF c10s01b00x00p04n01i00879ent IS
signal THE_INPUT : INTEGER;
signal THE_OUTPUT : INTEGER;
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for I in 120 to 149 loop
THE_INPUT <= I;
THE_OUTPUT <= INTO_EIGHTIES( I );
wait for 1 ns;
if ( THE_OUTPUT < 1980 or THE_OUTPUT > 1989 ) then
k := 1;
end if;
assert ( ( THE_OUTPUT >= 1980 ) and ( THE_OUTPUT <= 1989 ) )
report "output is out of range"
severity FAILURE;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c10s01b00x00p04n01i00879"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c10s01b00x00p04n01i00879 - Declaration is formed by the subprogram declaration together with the corresponding subprogram body."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p04n01i00879arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1406.vhd | 4 | 1692 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1406.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p07n01i01406ent IS
END c08s05b00x00p07n01i01406ent;
ARCHITECTURE c08s05b00x00p07n01i01406arch OF c08s05b00x00p07n01i01406ent IS
BEGIN
TESTING: PROCESS
type arr is array (1 to 3) of integer;
variable p : arr;
BEGIN
p := (1=>3, 2=>2.3, 3=>3);
assert FALSE
report "***FAILED TEST: c08s05b00x00p07n01i01406 - Type of the subelement does not match the type of the aggregate element."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p07n01i01406arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket89/project/src93/types_pkg.vhd | 3 | 4681 | --========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : types_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.standard_textio_additions.all;
package types_pkg is
file ALERT_FILE : text;
file LOG_FILE : text;
constant C_LOG_HDR_FOR_WAVEVIEW_WIDTH : natural := 100; -- For string in waveview indicating last log header
type t_void is (VOID);
type t_natural_array is array (natural range <>) of natural;
type t_integer_array is array (natural range <>) of integer;
-- Note: Most types below have a matching to_string() in 'string_methods_pkg.vhd'
type t_info_target is (LOG_INFO, ALERT_INFO, USER_INFO);
type t_alert_level is (NOTE, TB_NOTE, WARNING, TB_WARNING, MANUAL_CHECK, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
type t_enabled is (ENABLED, DISABLED);
type t_attention is (REGARD, EXPECT, IGNORE);
type t_radix is (BIN, HEX, DEC, HEX_BIN_IF_INVALID);
type t_radix_prefix is (EXCL_RADIX, INCL_RADIX);
type t_order is (INTERMEDIATE, FINAL);
type t_ascii_allow is (ALLOW_ALL, ALLOW_PRINTABLE_ONLY);
type t_blocking_mode is (BLOCKING, NON_BLOCKING);
type t_from_point_in_time is (FROM_NOW, FROM_LAST_EVENT);
type t_format_zeros is (AS_IS, SKIP_LEADING_0);
type t_format_string is (AS_IS, TRUNCATE, SKIP_LEADING_SPACE);
type t_log_format is (FORMATTED, UNFORMATTED);
type t_log_if_block_empty is (WRITE_HDR_IF_BLOCK_EMPTY, SKIP_LOG_IF_BLOCK_EMPTY, NOTIFY_IF_BLOCK_EMPTY);
type t_alert_counters is array (t_alert_level'left to t_alert_level'right) of natural;
type t_alert_attention is array (t_alert_level'left to t_alert_level'right) of t_attention;
type t_attention_counters is array (t_attention'left to t_attention'right) of natural; -- Only used to build below type
type t_alert_attention_counters is array (t_alert_level'left to t_alert_level'right) of t_attention_counters;
type t_quietness is (NON_QUIET, QUIET);
type t_deprecate_setting is (NO_DEPRECATE, DEPRECATE_ONCE, ALWAYS_DEPRECATE);
type t_deprecate_list is array(0 to 9) of string(1 to 100);
type t_global_ctrl is record
attention : t_alert_attention;
stop_limit : t_alert_counters;
end record;
type t_current_log_hdr is record
normal : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
large : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
xl : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
end record;
-------------------------------------
-- BFMs and above
-------------------------------------
type t_transaction_result is (ACK, NAK, ERROR); -- add more when needed
end package types_pkg;
package body types_pkg is
end package body types_pkg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc172.vhd | 4 | 1903 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc172.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00172ent IS
END c04s03b03x01p03n02i00172ent;
ARCHITECTURE c04s03b03x01p03n02i00172arch OF c04s03b03x01p03n02i00172ent IS
signal Data : integer;
alias SIGN2 : integer is Data; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
Data <= 100 after 50 ns;
wait for 50 ns;
assert NOT( SIGN2 = 100 )
report "***PASSED TEST: c04s03b03x01p03n02i00172" severity NOTE;
assert ( SIGN2 = 100 )
report "***FAILED TEST: c04s03b03x01p03n02i00172 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00172arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc388.vhd | 4 | 2246 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc388.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p04n03i00388ent IS
END c03s02b01x01p04n03i00388ent;
ARCHITECTURE c03s02b01x01p04n03i00388arch OF c03s02b01x01p04n03i00388ent IS
type SQ_ARR is array(0 to 1, 0 to 2) of BIT;
BEGIN
TESTING: PROCESS
variable M2 : SQ_ARR := (('0','1','1'),('1','0','0')); -- No_failure_here
BEGIN
assert NOT( M2(0,0)='0' and
M2(0,1)='1' and
M2(0,2)='1' and
M2(1,0)='1' and
M2(1,1)='0' and
M2(1,2)='0')
report "***PASSED TEST: c03s02b01x01p04n03i00388"
severity NOTE;
assert ( M2(0,0)='0' and
M2(0,1)='1' and
M2(0,2)='1' and
M2(1,0)='1' and
M2(1,1)='0' and
M2(1,2)='0')
report "***FAILED TEST: c03s02b01x01p04n03i00388 - An array value staisfies an index constraint if at each index position the array value and the index constrint have the same index range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p04n03i00388arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc662.vhd | 4 | 2348 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc662.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:56 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00662ent IS
END c03s04b01x00p01n01i00662ent;
ARCHITECTURE c03s04b01x00p01n01i00662arch OF c03s04b01x00p01n01i00662ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type positive_vector is array (natural range <>) of positive;
subtype positive_vector_range is positive_vector(hi_to_low_range);
constant C1 : positive_vector_range := (others => 3);
type positive_vector_range_file is file of positive_vector_range;
BEGIN
TESTING: PROCESS
file filein : positive_vector_range_file open write_mode is "iofile.03";
BEGIN
for i in 1 to 100 loop
write(filein,C1);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00662 - The output file will be verified by test s010112.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00662arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1852.vhd | 4 | 1745 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1852.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01852ent IS
END c07s01b00x00p08n01i01852ent;
ARCHITECTURE c07s01b00x00p08n01i01852arch OF c07s01b00x00p08n01i01852ent IS
signal sma_int : integer;
BEGIN
sig : sma_int <= 6 after 5 ns;
TESTING : PROCESS
type byte is range sig to 33; -- process label illegal here
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01852 - Signal assignment labels are not permitted as primaries in a range expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01852arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2099.vhd | 4 | 2465 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2099.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02099ent IS
END c07s02b04x00p20n01i02099ent;
ARCHITECTURE c07s02b04x00p20n01i02099arch OF c07s02b04x00p20n01i02099ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_8 is record_v (1 to 8);
SUBTYPE record_4 is record_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : record_4;
variable l_operand : record_4 := ( (12,34) , (56,78) , (12,34) , (56,78) );
variable r_operand : record_4 := ( (56,78) , (56,78) , (12,34) , (12,34) );
alias l_alias : record_v (1 to 2) is l_operand (2 to 3);
alias r_alias : record_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT(result = ( (56,78) , (12,34) , (12,34) , (12,34) ))
report "***PASSED TEST: c07s02b04x00p20n01i02099"
severity NOTE;
assert (result = ( (56,78) , (12,34) , (12,34) , (12,34) ))
report "***FAILED TEST: c07s02b04x00p20n01i02099 - Concatenation of two RECORD aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02099arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2159.vhd | 4 | 2296 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2159.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02159ent IS
END c07s02b04x00p21n01i02159ent;
ARCHITECTURE c07s02b04x00p21n01i02159arch OF c07s02b04x00p21n01i02159ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_5 is severity_level_v (1 to 5);
SUBTYPE severity_level_4 is severity_level_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : severity_level_5;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
report "***PASSED TEST: c07s02b04x00p21n01i02159"
severity NOTE;
assert ((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
report "***FAILED TEST: c07s02b04x00p21n01i02159 - Concatenation of element and SEVERITY_LEVEL array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02159arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd | 4 | 3287 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity bus_monitor is
end entity bus_monitor;
architecture test of bus_monitor is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (natural range <>) of byte;
function resolve_bytes ( drivers : in byte_array ) return byte is
begin
return drivers(drivers'left);
end function resolve_bytes;
function resolve_bits ( drivers : in bit_vector ) return bit is
begin
return drivers(drivers'left);
end function resolve_bits;
-- code from book (in text)
signal address : bit_vector(15 downto 0);
signal data : resolve_bytes byte;
signal rd, wr, io : bit; -- read, write, io/mem select
signal ready : resolve_bits bit;
-- end code from book
begin
-- code from book
bus_monitor : process is
constant header : string(1 to 44)
:= FF & " Time R/W I/M Address Data";
use std.textio.all;
file log : text open write_mode is "buslog";
variable trace_line : line;
variable line_count : natural := 0;
begin
if line_count mod 60 = 0 then
write ( trace_line, header );
writeline ( log, trace_line );
writeline ( log, trace_line ); -- empty line
end if;
wait until (rd = '1' or wr = '1') and ready = '1';
write ( trace_line, now, justified => right, field => 10, unit => us );
write ( trace_line, string'(" ") );
if rd = '1' then
write ( trace_line, 'R' );
else
write ( trace_line, 'W' );
end if;
write ( trace_line, string'(" ") );
if io = '1' then
write ( trace_line, 'I' );
else
write ( trace_line, 'M' );
end if;
write ( trace_line, string'(" ") );
write ( trace_line, address );
write ( trace_line, ' ');
write ( trace_line, data );
writeline ( log, trace_line );
line_count := line_count + 1;
end process bus_monitor;
-- end code from book
stimulus : process is
begin
wait for 0.4 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0000";
data <= B"10011110";
ready <= '1', '0' after 10 ns;
wait for 0.9 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0001";
data <= B"00010010";
ready <= '1', '0' after 10 ns;
wait for 2.0 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0014";
data <= B"11100111";
ready <= '1', '0' after 10 ns;
wait for 2.7 us - now;
wr <= '1', '0' after 10 ns;
io <= '1', '0' after 10 ns;
address <= X"0007";
data <= X"00";
ready <= '1', '0' after 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd | 4 | 3147 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
package pwl_functions is
function pwl_dim1_extrap ( x : in real; xdata, ydata : in real_vector )
return real;
function interpolate (x,y2,y1,x2,x1 : in real)
return real;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real;
end package pwl_functions;
package body pwl_functions is
-- code from book
function pwl_dim1_extrap ( x : in real; xdata, ydata : in real_vector )
return real is
variable xvalue, yvalue, m : real;
variable start, fin, mid: integer;
begin
if x <= xdata(0) then
yvalue := extrapolate ( x, ydata(1), ydata(0), xdata(1), xdata(0) );
return yvalue;
end if;
if x >= xdata(xdata'right) then
yvalue := extrapolate( x, ydata(ydata'right), ydata(ydata'right - 1),
xdata(xdata'right), xdata(xdata'right - 1) );
return yvalue;
end if;
start := 0;
fin := xdata'right;
while start <= fin loop
mid := (start + fin) / 2;
if xdata(mid) < x then
start := mid + 1;
else
fin := mid - 1;
end if;
end loop;
if xdata(mid) > x then
mid := mid - 1;
end if;
yvalue := interpolate( x, ydata(mid + 1), ydata(mid),
xdata(mid + 1), xdata(mid) );
return yvalue;
end function pwl_dim1_extrap;
-- end code from book
function interpolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "interpolate: x1 cannot be equal to x2"
severity error;
assert (x >= x1) and (x <= x2)
report "interpolate: x must be between x1 and x2, inclusively "
severity error;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function interpolate;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "extrapolate: x1 cannot be equal to x2"
severity error;
assert (x <= x1) or (x >= x2)
report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
severity warning;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function extrapolate;
end package body pwl_functions;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc73.vhd | 4 | 1660 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc73.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p09n02i00073ent IS
END c04s03b01x02p09n02i00073ent;
ARCHITECTURE c04s03b01x02p09n02i00073arch OF c04s03b01x02p09n02i00073ent IS
signal s1 : bit register; -- Failure_here
-- a guarded signal, but is not a resolved signal.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x02p09n02i00073- Guarded signal should be a resolved signal."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x02p09n02i00073arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2237.vhd | 4 | 1761 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2237.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02237ent IS
END c07s02b06x00p01n01i02237ent;
ARCHITECTURE c07s02b06x00p01n01i02237arch OF c07s02b06x00p01n01i02237ent IS
BEGIN
TESTING: PROCESS
-- array types.
type MEMORY is array(INTEGER range <>) of BIT;
variable MEMORYV : MEMORY( 0 to 31 );
variable k : integer;
BEGIN
k := MEMORYV mod MEMORYV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02237 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02237arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd | 4 | 1713 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_inv_integrator is
end tb_inv_integrator;
architecture TB_inv_integrator of tb_inv_integrator is
-- Component declarations
-- Signal declarations
terminal vin : electrical;
terminal vout : electrical;
begin
-- Signal assignments
-- Component instances
v1 : entity work.v_sine(ideal)
generic map(
amplitude => 0.2,
freq => 1.0e3
)
port map(
pos => vin,
neg => ELECTRICAL_REF
);
inverting_integ1 : entity work.inverting_integrator(structural)
port map(
output => vout,
input => vin
);
RLoad : entity work.load_res(ideal)
generic map(
R => 100.0
)
port map(
node1 => vout,
node2 => ELECTRICAL_REF
);
end TB_inv_integrator;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc3065.vhd | 4 | 2091 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3065.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s04b02x00p02n01i03065ent IS
END c12s04b02x00p02n01i03065ent;
ARCHITECTURE c12s04b02x00p02n01i03065arch OF c12s04b02x00p02n01i03065ent IS
type intvector is array (natural range <>) of integer;
signal V2 : intvector(1 to 5);
signal V0 : integer := 66;
BEGIN
FG2: for i in V2'range generate
IG1: if i = V2'left generate
V2(i) <= V0 after 1 ns;
end generate;
IG2: if i /= V2'left generate
V2(i) <= V2(i-1) after 1 ns;
end generate;
-- ..., V2(2) <= V2(1), V2(1) <= V0
end generate;
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert NOT( V2 = (66,66,66,66,66) )
report "***PASSED TEST: c12s04b02x00p02n01i03065"
severity NOTE;
assert ( V2 = (66,66,66,66,66) )
report "***FAILED TEST: c12s04b02x00p02n01i03065 - Generate statement semantic test failed."
severity ERROR;
END PROCESS TESTING;
END c12s04b02x00p02n01i03065arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/sr2676/reset.vhdl | 3 | 426 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.reset_types.all;
entity power_on_reset is
generic(
clk_period_ns: unsigned := X"14"
);
port (
clk: in std_logic;
reset: in std_logic;
core_en: out std_logic;
sys_clken: out std_logic;
clk_33mhz_en: out std_logic;
cfg_drv: out std_logic;
rd_pmbrd_rev : out std_logic;
cur_state: out reset_state
);
end power_on_reset;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_03.vhd | 4 | 1321 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
begin
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
procedure write ( file f : file_type; value : in element_type );
-- end of code from book
procedure write ( file f : file_type; value : in element_type ) is
begin
end;
begin
wait;
end process;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_06.vhd | 4 | 2295 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_06.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_06 is
end entity ch_07_06;
library bv_utilities;
use bv_utilities.bv_arithmetic;
architecture test of ch_07_06 is
begin
process_07_5_b : process is
-- code from book:
function "+" ( left, right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bv_arithmetic."+"(left, right);
-- end not in book
end function "+";
variable addr_reg : bit_vector(31 downto 0);
-- . . .
-- end of code from book
-- code from book:
function "abs" ( right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
if right(right'left) = '0' then
return right;
else
return bv_arithmetic."-"(right);
end if;
-- end not in book
end function "abs";
variable accumulator : bit_vector(31 downto 0);
-- . . .
-- end of code from book
begin
-- code from book:
addr_reg := addr_reg + X"0000_0004";
-- end of code from book
accumulator := X"000000FF";
-- code from book:
accumulator := abs accumulator;
-- end of code from book
accumulator := X"FFFFFFFE";
accumulator := abs accumulator;
wait;
end process process_07_5_b;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/reg_ctrl.vhd | 4 | 1267 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity reg_ctrl is
port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
reg_rd, reg_wr : out std_ulogic );
end entity reg_ctrl;
--------------------------------------------------
architecture bool_eqn of reg_ctrl is
begin
rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
and not cpu_clk;
end architecture bool_eqn;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/74x138.vhd | 4 | 1559 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package physical_attributes is
-- code from book (in text)
attribute layout_ignore : boolean;
attribute pin_number : positive;
-- end code from book
end package physical_attributes;
-- code from book
library ieee; use ieee.std_logic_1164.all;
use work.physical_attributes.all;
entity \74x138\ is
generic ( Tpd : time );
port ( en1, en2a_n, en2b_n : in std_logic;
s0, s1, s2 : in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7 : out std_logic );
attribute layout_ignore of Tpd : constant is true;
attribute pin_number of s0 : signal is 1;
attribute pin_number of s1 : signal is 2;
attribute pin_number of s2 : signal is 3;
attribute pin_number of en2a_n : signal is 4;
-- . . .
end entity \74x138\;
-- code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc7.vhd | 4 | 1801 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc7.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p08n01i00007ent IS
END c04s01b00x00p08n01i00007ent;
ARCHITECTURE c04s01b00x00p08n01i00007arch OF c04s01b00x00p08n01i00007ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is ('1');
type ENUM2 is ('1');
variable V5: ENUM1;
variable V6: ENUM2;
BEGIN
if V5 = V6 then -- Failure_here
-- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
null ;
end if;
assert FALSE
report "***FAILED TEST: c04s01b00x00p08n01i00007 - Types are different and hence incompatible."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p08n01i00007arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2137.vhd | 4 | 2160 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2137.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02137ent IS
END c07s02b04x00p21n01i02137ent;
ARCHITECTURE c07s02b04x00p21n01i02137arch OF c07s02b04x00p21n01i02137ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_5 is positive_v (1 to 5);
SUBTYPE positive_4 is positive_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : positive_5;
variable l_operand : positive_4 := ( 12, 56, 12, 56 );
variable r_operand : positive := 12;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result = ( 12, 56, 12, 56, 12 ))
report "***PASSED TEST: c07s02b04x00p21n01i02137"
severity NOTE;
assert ( result = ( 12, 56, 12, 56, 12 ))
report "***FAILED TEST: c07s02b04x00p21n01i02137 - Concatenation of element and POSITIVE array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02137arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_05.vhd | 4 | 3059 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity bus_sequencer is
port ( rd, wr, sel, width, burst : out std_ulogic;
addr_low_2 : out std_ulogic_vector(1 downto 0);
ready : out std_ulogic;
control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
other_signal : out std_ulogic );
end entity bus_sequencer;
----------------
library ieee; use ieee.std_logic_1164.all;
entity state_register is
port ( phi1, phi2 : in std_ulogic;
next_state : in std_ulogic_vector(3 downto 0);
current_state : out std_ulogic_vector(3 downto 0) );
end entity state_register;
architecture std_cell of state_register is
begin
end architecture std_cell;
-- end not in book
architecture fsm of bus_sequencer is
-- This architecture implements the sequencer as a finite state machine.
-- NOTE: it uses the clock signals from clock_pkg to synchronize the fsm.
signal next_state_vector : -- . . .;
-- not in book
std_ulogic_vector(3 downto 0);
signal current_state_vector : std_ulogic_vector(3 downto 0);
-- end not in book
begin
bus_sequencer_state_register : entity work.state_register(std_cell)
port map ( phi1 => work.clock_pkg.clock_phase1,
phi2 => work.clock_pkg.clock_phase2,
next_state => next_state_vector,
-- . . . );
-- not in book
current_state => current_state_vector );
-- end not in book
-- . . .
end architecture fsm;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_07.vhd | 4 | 2491 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_07.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity top is
end entity top;
architecture top_arch of top is
signal top_sig : -- . . .; -- 1
--
bit;
--
begin
stimulus : process
is
variable var : -- . . .; -- 2
--
bit;
--
begin
-- . . .
--
report "--1: " & top'path_name;
report "--1: " & top'instance_name;
report "--1: " & top_sig'path_name;
report "--1: " & top_sig'instance_name;
report "--2: " & stimulus'path_name;
report "--2: " & stimulus'instance_name;
report "--2: " & var'path_name;
report "--2: " & var'instance_name;
wait;
--
end process stimulus;
rep_gen : for index in 0 to 7 generate
begin
end_gen : if index = 7 generate
signal end_sig : -- . . .; -- 3
--
bit;
--
begin
-- . . .
assert false report "--3: " & end_sig'path_name;
assert false report "--3: " & end_sig'instance_name;
--
end generate end_gen;
other_gen : if index /= 7 generate
signal other_sig : -- . . .; -- 4
--
bit;
--
begin
other_comp : entity work.bottom(bottom_arch)
port map ( -- . . . );
--
port_name => open );
assert false report "--4: " & other_sig'path_name;
assert false report "--4: " & other_sig'instance_name;
--
end generate other_gen;
end generate rep_gen;
end architecture top_arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1167.vhd | 4 | 1989 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1167.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p04n02i01167ent IS
END c06s06b00x00p04n02i01167ent;
ARCHITECTURE c06s06b00x00p04n02i01167arch OF c06s06b00x00p04n02i01167ent IS
attribute p: POSITIVE;
signal s: integer;
attribute p of s: signal is 10;
BEGIN
TESTING: PROCESS
BEGIN
if s'p = 10 then -- Success_here
s <= 12;
else
s <= 0;
end if;
wait for 10 ns;
assert NOT( s=12 )
report "***PASSED TEST: c06s06b00x00p04n02i01167"
severity NOTE;
assert ( s=12 )
report "***FAILED TEST: c06s06b00x00p04n02i01167 - The meaning of the prefix of an attribute must be determinable independently of the attribute designator and independently of the fact that it is the prefix of an attribute."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p04n02i01167arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug08/paren3.vhdl | 3 | 151 | entity paren3 is
end paren3;
architecture behav of paren3
is
subtype a is integer;
constant b : real := 3.15;
begin
assert a(b) = 3;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_03.vhd | 4 | 1463 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity counter is
port ( clk : in bit; count : out natural );
end entity counter;
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
wait until clk = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
end process incrementer;
end architecture behavior;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2804.vhd | 4 | 1687 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2804.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity IF is
end IF;
ENTITY c13s09b00x00p99n01i02804ent IS
END c13s09b00x00p99n01i02804ent;
ARCHITECTURE c13s09b00x00p99n01i02804arch OF c13s09b00x00p99n01i02804ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02804 - Reserved word IF can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02804arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_07.vhd | 4 | 2052 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_ch_17_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_17_07 is
end entity ch_17_07;
----------------------------------------------------------------
architecture test of ch_17_07 is
begin
process is
-- code from book:
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list : value_ptr;
-- end of code from book
begin
-- code from book:
if value_list /= null then
-- . . . -- do something with the list
-- not in book
report "value_list /= null";
-- end not in book
end if;
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_20.vhd | 4 | 2156 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_20.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package pk_05_20 is
-- code from book:
type FIFO_status is record
nearly_full, nearly_empty, full, empty : bit;
end record FIFO_status;
-- end of code from book
end package pk_05_20;
----------------------------------------------------------------
use work.pk_05_20.all;
entity FIFO is
port ( status : out FIFO_status;
other_ports : out bit );
end entity FIFO;
----------------------------------------------------------------
entity ch_05_20 is
end entity ch_05_20;
----------------------------------------------------------------
use work.pk_05_20.all;
architecture test of ch_05_20 is
signal start_flush, end_flush, DMA_buffer_full, DMA_buffer_empty : bit;
begin
-- code from book:
DMA_buffer : entity work.FIFO
port map ( -- . . .,
status.nearly_full => start_flush,
status.nearly_empty => end_flush,
status.full => DMA_buffer_full,
status.empty => DMA_buffer_empty, -- . . . );
-- not in book
other_ports => open );
-- end not in book
-- end of code from book
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2580.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2580.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02580ent IS
END c13s03b01x00p02n01i02580ent;
ARCHITECTURE c13s03b01x00p02n01i02580arch OF c13s03b01x00p02n01i02580ent IS
BEGIN
TESTING: PROCESS
variable "k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02580 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02580arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_05.vhd | 4 | 2634 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_05.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity SR_flipflop is
port ( s_n, r_n : in bit; q, q_n : inout bit );
begin
postponed process (q, q_n) is
begin
assert now = 0 fs or q = not q_n
report "implementation error: q /= not q_n";
end postponed process;
end entity SR_flipflop;
--------------------------------------------------
architecture dataflow of SR_flipflop is
begin
gate_1 : q <= s_n nand q_n;
gate_2 : q_n <= r_n nand q;
end architecture dataflow;
-- not in book
entity fg_21_05 is
end entity fg_21_05;
architecture test of fg_21_05 is
signal s_n, r_n, q, q_n : bit;
begin
dut : entity work.SR_flipflop
port map ( s_n, r_n, q, q_n );
s_n <= '1',
'0' after 10 ns, '1' after 15 ns,
'0' after 30 ns, '1' after 40 ns;
r_n <= '0', '1' after 5 ns,
'0' after 20 ns, '1' after 25 ns,
'0' after 30 ns, '1' after 35 ns;
end architecture test;
-- end not in book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1329.vhd | 4 | 1666 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1329.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p03n05i01329ent IS
END c08s04b01x00p03n05i01329ent;
ARCHITECTURE c08s04b01x00p03n05i01329arch OF c08s04b01x00p03n05i01329ent IS
signal S1, S2, S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
S3 <= S1 after 10 ns, null after 100 ns, S2 after 150 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p03n05i01329 - Null waveform can not be assigned to unguarded signals."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p03n05i01329arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last_event-attribute.vhdl | 4 | 600 | entity test is
end test;
architecture only of test is
signal s : bit;
begin
s <= '1' after 5 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
p: process
variable v: time;
begin
wait for 15 ns;
v:=s'last_event;
assert v = 10 ns report "TEST FAILED - s previous value incorrect!" severity failure;
report "TEST PASSED elapsed time is 10 ns" ;
wait for 14 ns;
v:=s'last_event;
assert v = 9 ns report "TEST FAILED - s previous value incorrect!" severity failure;
report "TEST PASSED elapsed time is 9 ns" ;
wait;
end process;
end architecture only;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2471.vhd | 4 | 2058 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2471.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02471ent IS
END c07s03b02x02p03n02i02471ent;
ARCHITECTURE c07s03b02x02p03n02i02471arch OF c07s03b02x02p03n02i02471ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 4 );
function F return CONSTRAINED_ARRAY is
begin
return CONSTRAINED_ARRAY'(others => '7');
-- check in function return statement.
end F;
variable k : CONSTRAINED_ARRAY;
BEGIN
k := F;
wait for 5 ns;
assert NOT(k = "7777")
report "***PASSED TEST: c07s03b02x02p03n02i02471"
severity NOTE;
assert (k = "7777")
report "***FAILED TEST: c07s03b02x02p03n02i02471 - Others cannot be used with an unconstrained array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02471arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/sr2940/GCD.vhd | 3 | 5298 | -- module GCD where
--
--
-- $wmygcd::*Int# -> *Int# -> *Int#
-- $wmygcd ww ww1 =
-- let wild::GHC.Types.Bool = (GHC.Prim.==# ww ww1) in
-- case wild of :: *Int#
-- GHC.Types.False ->
-- let wild1::GHC.Types.Bool = (GHC.Prim.<# ww ww1) in
-- case wild1 of :: *Int#
-- GHC.Types.False -> ($wmygcd (GHC.Prim.-# ww ww1) ww1)
-- GHC.Types.True -> ($wmygcd ww (GHC.Prim.-# ww1 ww))
-- GHC.Types.True -> ww
--
-- mygcd::GHC.Types.Int -> GHC.Types.Int -> GHC.Types.Int
-- mygcd w w1 =
-- let w2::GHC.Types.Int = w in
-- case w2 of :: GHC.Types.Int
-- GHC.Types.I# ww::*Int# ->
-- let w3::GHC.Types.Int = w1 in
-- case w3 of :: GHC.Types.Int
-- GHC.Types.I# ww1::*Int# ->
-- let ww2::*Int# = ($wmygcd ww ww1) in
-- case ww2 of :: GHC.Types.Int DEFAULT -> (GHC.Types.I# ww2)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.\Prim\.all;
package \GCD\ is
end \GCD\;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.\Prim\.all;
use work.\GCD\.all;
entity \$wmygcd\ is
port (clk : in std_logic;
s1_call : in std_logic;
s1_ret : out std_logic;
s1_ww : in \Int#\;
s1_ww1 : in \Int#\;
res : out \Int#\);
end entity;
architecture rtl of \$wmygcd\ is
signal tail_call : std_logic;
signal tail_ww : \Int#\;
signal tail_ww1 : \Int#\;
signal core_call : std_logic;
signal core_ret : std_logic;
signal core_ww : \Int#\;
signal core_ww1 : \Int#\;
signal s1_act : std_logic;
signal s1_wait : std_logic;
signal s1_saved_ww : \Int#\;
signal s1_saved_ww1 : \Int#\;
begin
process (core_call, core_ww, core_ww1)
variable wild : \GHC.Types.Bool\;
variable wild1 : \GHC.Types.Bool\;
variable ww : \Int#\;
variable ww1 : \Int#\;
begin
ww := core_ww;
ww1 := core_ww1;
wild := \GHC.Prim.==#\(ww, ww1);
if \is_GHC.Types.False\(wild) then
wild1 := \GHC.Prim.<#\(ww, ww1);
if \is_GHC.Types.False\(wild1) then
res <= \$wmygcd\(\GHC.Prim.-#\(ww, ww1), ww1);
elsif \is_GHC.Types.True\(wild1) then
res <= \$wmygcd\(ww, \GHC.Prim.-#\(ww1, ww));
end if;
elsif \is_GHC.Types.True\(wild) then res <= ww;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
core_call <= '0';
if s1_call = '1' then
s1_wait <= '1';
s1_saved_ww <= s1_ww;
s1_saved_ww1 <= s1_ww1;
end if;
if tail_call = '1' then
core_call <= '1';
core_ww <= tail_ww;
core_ww1 <= tail_ww1;
elsif core_ret = '1' or s1_act = '1' then
s1_act <= '0';
if s1_wait = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_ww <= s1_saved_ww;
core_ww1 <= s1_saved_ww1;
elsif s1_call = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_ww <= s1_ww;
core_ww1 <= s1_ww1;
end if;
end if;
end if;
end process;
s1_ret <= core_ret and s1_act;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.\Prim\.all;
use work.\GCD\.all;
entity mygcd is
port (clk : in std_logic;
s1_call : in std_logic;
s1_ret : out std_logic;
s1_w : in \GHC.Types.Int\;
s1_w1 : in \GHC.Types.Int\;
res : out \GHC.Types.Int\);
end entity;
architecture rtl of mygcd is
signal tail_call : std_logic;
signal tail_w : \GHC.Types.Int\;
signal tail_w1 : \GHC.Types.Int\;
signal core_call : std_logic;
signal core_ret : std_logic;
signal core_w : \GHC.Types.Int\;
signal core_w1 : \GHC.Types.Int\;
signal s1_act : std_logic;
signal s1_wait : std_logic;
signal s1_saved_w : \GHC.Types.Int\;
signal s1_saved_w1 : \GHC.Types.Int\;
begin
process (core_call, core_w, core_w1)
variable w2 : \GHC.Types.Int\;
variable ww : \Int#\;
variable w3 : \GHC.Types.Int\;
variable ww1 : \Int#\;
variable ww2 : \Int#\;
variable w : \GHC.Types.Int\;
variable w1 : \GHC.Types.Int\;
begin
w := core_w;
w1 := core_w1;
w2 := w;
if \is_GHC.Types.I#\(w2) then
\expand_GHC.Types.I#\(w2, ww);
w3 := w1;
if \is_GHC.Types.I#\(w3) then
\expand_GHC.Types.I#\(w3, ww1);
ww2 := \$wmygcd\(ww, ww1);
res <= \GHC.Types.I#\(ww2);
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
core_call <= '0';
if s1_call = '1' then
s1_wait <= '1';
s1_saved_w <= s1_w;
s1_saved_w1 <= s1_w1;
end if;
if tail_call = '1' then
core_call <= '1';
core_w <= tail_w;
core_w1 <= tail_w1;
elsif core_ret = '1' or s1_act = '1' then
s1_act <= '0';
if s1_wait = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_w <= s1_saved_w;
core_w1 <= s1_saved_w1;
elsif s1_call = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_w <= s1_w;
core_w1 <= s1_w1;
end if;
end if;
end if;
end process;
s1_ret <= core_ret and s1_act;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc289.vhd | 4 | 1713 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc289.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p13n01i00289ent IS
END c03s01b03x00p13n01i00289ent;
ARCHITECTURE c03s01b03x00p13n01i00289arch OF c03s01b03x00p13n01i00289ent IS
type T is
range 1 to 100
units
I ;
J = 2 I;
K = 2 J;
L = 10 K;
end units;
signal S1 : T;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= 10 * L;
assert FALSE
report "***FAILED TEST: c03s01b03x00p13n01i00289 - Value doesn't belong to the physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p13n01i00289arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_11.vhd | 4 | 2837 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_11.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity RAM16x1 is
port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
\d\, \we\ : in std_ulogic;
\o\ : out std_ulogic );
end entity RAM16x1;
architecture a of RAM16x1 is
begin
end architecture a;
entity fg_a_11 is
end entity fg_a_11;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_11 is
-- code from book
component RAM16x1 is
port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
\d\, \we\ : in std_ulogic;
\o\ : out std_ulogic );
end component RAM16x1;
-- . . .
-- end code from book
signal address : std_ulogic_vector(3 downto 0);
signal raminp, ramout : std_ulogic_vector(15 downto 0);
signal write_enable : std_ulogic;
begin
-- code from book
g1 : for i in 0 to 15 generate
rama : component RAM16x1
port map ( \a<0>\ => address(0),
\a<1>\ => address(1),
\a<2>\ => address(2),
\a<3>\ => address(3),
\d\ => raminp ( i ),
\we\ => write_enable,
\o\ => ramout ( i ) );
end generate g1;
-- end code from book
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1067.vhd | 4 | 1818 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1067.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n04i01067ent IS
END c06s04b00x00p03n04i01067ent;
ARCHITECTURE c06s04b00x00p03n04i01067arch OF c06s04b00x00p03n04i01067ent IS
type arrtype is array (positive range 1 to 10) of real;
BEGIN
TESTING: PROCESS
variable k : arrtype;
BEGIN
k(1+2) := 1.2;
assert NOT( K(3)=1.2 )
report "***PASSED TEST: c06s04b00x00p03n04i01067"
severity NOTE;
assert ( K(3)=1.2 )
report "***FAILED TEST: c06s04b00x00p03n04i01067 - The index value belongs to the range of the corresponding index range of the array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n04i01067arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket70/bug.vhdl | 3 | 579 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
procedure proc(constant value : unsigned) is
variable a : integer := value'length;
variable b : integer := (value'length - 1)/2;
begin
report "x = " & integer'image(a);
report "(x-1)/2 = " & integer'image(b);
assert a = 0 and b = 0 severity failure;
end procedure;
variable value : unsigned(0 downto 1);
begin
proc(unsigned'(""));
proc(value);
wait;
end process;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2161.vhd | 4 | 1996 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2161.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02161ent IS
END c07s02b04x00p22n01i02161ent;
ARCHITECTURE c07s02b04x00p22n01i02161arch OF c07s02b04x00p22n01i02161ent IS
TYPE bit_v is array (integer range <>) of bit;
SUBTYPE bit_2 is bit_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : bit_2;
variable l_operand : bit := '1';
variable r_operand : bit := '0';
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = ('1','0')) and (result(1) = '1'))
report "***PASSED TEST: c07s02b04x00p22n01i02161"
severity NOTE;
assert ((result = ('1','0')) and (result(1) = '1'))
report "***FAILED TEST: c07s02b04x00p22n01i02161 - Concatenation of element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02161arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc447.vhd | 4 | 3227 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc447.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00447ent IS
END c03s02b01x01p19n01i00447ent;
ARCHITECTURE c03s02b01x01p19n01i00447arch OF c03s02b01x01p19n01i00447ent IS
type natural_vector is array (natural range <>) of natural;
subtype natural_vector_st is natural_vector(0 to 15);
constant C1 : natural := 4;
constant C70 : natural_vector_st :=(others => C1);
function complex_scalar(s : natural_vector_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return natural_vector_st is
begin
return C70;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : natural_vector_st;
signal S2 : natural_vector_st;
signal S3 : natural_vector_st := C70;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C70) and (S2 = C70))
report "***PASSED TEST: c03s02b01x01p19n01i00447"
severity NOTE;
assert ((S1 = C70) and (S2 = C70))
report "***FAILED TEST: c03s02b01x01p19n01i00447 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00447arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc828.vhd | 4 | 1657 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc828.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00828ent IS
END c01s02b02x00p02n01i00828ent;
ARCHITECTURE c01s02b02x00p02n01i00828arch OF c01s02b02x00p02n01i00828ent IS
BEGIN
wait 3 ns; -- illegal location for wait statement
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00828 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00828arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc851.vhd | 4 | 10055 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc851.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00851pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00851pkg_b;
package body c01s03b01x00p12n01i00851pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00851pkg_b;
use work.c01s03b01x00p12n01i00851pkg_b.all;
package c01s03b01x00p12n01i00851pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00851pkg_a;
use work.c01s03b01x00p12n01i00851pkg_a.all;
use work.c01s03b01x00p12n01i00851pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00851pkg_a.all;
use work.c01s03b01x00p12n01i00851pkg_b.all;
ENTITY c01s03b01x00p12n01i00851ent IS
END c01s03b01x00p12n01i00851ent;
ARCHITECTURE c01s03b01x00p12n01i00851arch OF c01s03b01x00p12n01i00851ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00851"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00851 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00851arch;
configuration c01s03b01x00p12n01i00851cfg of c01s03b01x00p12n01i00851ent is
for c01s03b01x00p12n01i00851arch
for K
for T5:test use configuration work.testbench;
end for;
for G(three downto zero)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1240.vhd | 4 | 1669 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1240.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p03n01i01240ent IS
END c08s02b00x00p03n01i01240ent;
ARCHITECTURE c08s02b00x00p03n01i01240arch OF c08s02b00x00p03n01i01240ent IS
BEGIN
TESTING: PROCESS
type BYTE_T is array (1 to 8) of BIT;
variable k : BYTE_T;
BEGIN
assert k;
assert FALSE
report "***FAILED TEST: c08s02b00x00p03n01i01240 - The condition in the assert statement is not of type boolean"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p03n01i01240arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd | 4 | 1557 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
architecture test of inline_05 is
-- code from book
component nand3 is
port ( a, b, c : in bit := '1'; y : out bit );
end component nand3;
-- end code from book
signal s1, s2, s3 : bit;
begin
-- code from book
gate1 : component nand3
port map ( a => s1, b => s2, c => open, y => s3 );
-- end code from book
end architecture test;
-- code from book
entity nand2 is
port ( a, b : in bit := '1'; y : out bit );
end entity nand2;
-- end code from book
configuration inline_05_test of inline_05 is
for test
-- code from book
for gate1 : nand3
use entity work.nand2(basic);
end for;
-- end code from book
end for;
end configuration inline_05_test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc346.vhd | 4 | 1988 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc346.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p10n05i00346ent IS
END c03s02b01x00p10n05i00346ent;
ARCHITECTURE c03s02b01x00p10n05i00346arch OF c03s02b01x00p10n05i00346ent IS
type MEM is array(INTEGER range <>) of BIT;
BEGIN
TESTING: PROCESS
variable S1 : MEM(1 to 5);
variable S2 : MEM(28 downto 7);
BEGIN
S1(1 to 5) := "11111";
S2(28 downto 21) := "00001111";
assert NOT(S1(1 to 5) = "11111" and S2(28 downto 21)= "00001111")
report "***PASSED TEST: c03s02b01x00p10n05i00346"
severity NOTE;
assert (S1(1 to 5) = "11111" and S2(28 downto 21)= "00001111")
report "***FAILED TEST: c03s02b01x00p10n05i00346 - Different objects of the same unconstrained array type can have different bounds and direction."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p10n05i00346arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/test_alu.vhd | 4 | 2536 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
package alu_types is
-- code from book (in text)
use ieee.numeric_bit.all;
subtype ALU_func is unsigned(3 downto 0);
subtype data_word is unsigned(15 downto 0);
-- . . .
-- end code from book (in text)
end package alu_types;
use work.alu_types.all;
-- code from book (in text)
entity ALU is
port ( a, b : in data_word; func : in ALU_func;
result : out data_word; carry : out bit );
end entity ALU;
-- end code from book (in text)
architecture structural of ALU is
begin
end architecture structural;
entity test_ALU is
end entity test_ALU;
library ieee;
use work.alu_types.all;
-- code from book
architecture random_test of test_ALU is
use ieee.numeric_bit.all;
use ieee.math_real.uniform;
signal a, b, result : data_word;
signal func : ALU_func;
signal carry : bit;
begin
dut : entity work.ALU(structural)
port map ( a, b, func, result, carry );
stimulus : process is
variable seed1, seed2 : positive := 1;
variable a_real, b_real, func_real : real;
begin
wait for 100 ns;
uniform ( seed1, seed2, a_real );
uniform ( seed1, seed2, b_real );
uniform ( seed1, seed2, func_real );
a <= to_unsigned( natural(a_real * real(2**integer'(data_word'length)) - 0.5),
data_word'length );
b <= to_unsigned( natural(b_real * real(2**integer'(data_word'length)) - 0.5),
data_word'length );
func <= to_unsigned( natural(func_real
* real(2**integer'(ALU_func'length)) - 0.5),
ALU_func'length );
end process stimulus;
-- . . . --verification process to check result and carry
end architecture random_test;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl | 4 | 664 | entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : integer := 0;
begin -- only
assign: process
begin -- process p
sig <= 1;
wait;
end process assign;
check1: process
begin -- process check1
wait for 1 fs;
assert sig = 1 report "TEST FAILED" severity FAILURE;
wait;
end process check1;
check2: process
begin -- process check1
wait for 1 fs;
assert sig = 1 report "TEST FAILED" severity FAILURE;
wait;
end process check2;
check3: process
begin -- process check1
wait for 2 fs;
report "TEST PASSED" severity NOTE;
wait;
end process check3;
end only;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue238/var3.vhdl | 2 | 193 | entity var3 is
end;
use work.pkg.all;
architecture behav of var3 is
begin
process
variable v1 : rec_4;
variable v2 : rec_4bis;
begin
v2 := v1;
wait;
end process;
end behav;
| gpl-2.0 |
gmsanchez/OrgComp | TP_01/TB_GenParidad.vhd | 1 | 2520 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:02:19 09/10/2014
-- Design Name:
-- Module Name: /home/gsanchez/Apps/TP_01/TB_GenParidad.vhd
-- Project Name: TP_01
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: GenParidad
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_GenParidad IS
END TB_GenParidad;
ARCHITECTURE behavior OF TB_GenParidad IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT GenParidad
PORT(
E : IN std_logic_vector(3 downto 0);
P : IN std_logic;
S : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
--Inputs
signal E : std_logic_vector(3 downto 0) := (others => '0');
signal P : std_logic := '0';
--Outputs
signal S : std_logic_vector(4 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: GenParidad PORT MAP (
E => E,
P => P,
S => S
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
for Paridad in 0 to 1 loop
P <= std_logic(to_unsigned(Paridad,1)(0));
for Ent in 0 to 15 loop
E <= std_logic_vector(to_unsigned(Ent,4));
wait for 10 ns;
end loop;
end loop;
wait for 100 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/p_jinfo_comps_info_quant_tbl_no.vhd | 2 | 1515 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_quant_tbl_no is
port (
wa0_data : in std_logic_vector(1 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(1 downto 0);
wa0_en : in std_logic
);
end p_jinfo_comps_info_quant_tbl_no;
architecture augh of p_jinfo_comps_info_quant_tbl_no is
-- Embedded RAM
type ram_type is array (0 to 2) of std_logic_vector(1 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-');
end architecture;
| gpl-2.0 |
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