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emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1693.vhd | 4 | 1882 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1693.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01693ent IS
port (B:BIT; C:out BIT) ;
END c09s02b00x00p03n01i01693ent;
ARCHITECTURE c09s02b00x00p03n01i01693arch OF c09s02b00x00p03n01i01693ent IS
BEGIN
process
begin
architecture B6 of E1 is -- Failure_here
--SEMANTICS ERROR: body declarations may not be in a process statement.
begin
process
begin
null;
end process;
end B6;
null;
end process;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01693 - Body declarations are not allowed in process statements."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01693arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1864.vhd | 4 | 1890 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1864.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01864ent IS
END c07s01b00x00p08n01i01864ent;
ARCHITECTURE c07s01b00x00p08n01i01864arch OF c07s01b00x00p08n01i01864ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= obus'right(TESTING) after 5 ns; -- process label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01864 - Process labels are not permitted as primaries in an attribute expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01864arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1575.vhd | 4 | 1648 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1575.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p04n01i01575ent IS
END c08s10b00x00p04n01i01575ent;
ARCHITECTURE c08s10b00x00p04n01i01575arch OF c08s10b00x00p04n01i01575ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
next L when 5;
end loop;
assert FALSE
report "***FAILED TEST: c08s10b00x00p04n01i01575 - The condition in a next statement has to be of type boolean"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p04n01i01575arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc131.vhd | 4 | 1768 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc131.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x01p04n01i00131ent IS
generic ( constant c1 : integer := 9090 );
END c04s03b02x01p04n01i00131ent;
ARCHITECTURE c04s03b02x01p04n01i00131arch OF c04s03b02x01p04n01i00131ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c1 = 9090 )
report "***PASSED TEST: c04s03b02x01p04n01i00131"
severity NOTE;
assert ( c1 = 9090 )
report "***FAILED TEST: c04s03b02x01p04n01i00131 - Constant declarations in generic interface list in generic interface list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x01p04n01i00131arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket29/iomapper.vhdl | 3 | 24390 | use WORK.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.debugtools.all;
entity iomapper is
port (Clk : in std_logic;
cpuclock : in std_logic;
pixelclk : in std_logic;
uartclock : in std_logic;
clock50mhz : in std_logic;
phi0 : in std_logic;
reset : in std_logic;
reset_out : out std_logic;
irq : out std_logic;
nmi : out std_logic;
restore_nmi : out std_logic;
cpu_hypervisor_mode : in std_logic;
address : in std_logic_vector(19 downto 0);
r : in std_logic;
w : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
sd_data_o : out std_logic_vector(7 downto 0);
sector_buffer_mapped : out std_logic;
key_scancode : in unsigned(15 downto 0);
key_scancode_toggle : in std_logic;
reg_isr_out : out unsigned(7 downto 0);
imask_ta_out : out std_logic;
led : out std_logic := '0';
motor : out std_logic := '0';
ps2data : in std_logic;
ps2clock : in std_logic;
pixel_stream_in : in unsigned (7 downto 0);
pixel_y : in unsigned (11 downto 0);
pixel_valid : in std_logic;
pixel_newframe : in std_logic;
pixel_newraster : in std_logic;
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio : inout std_logic;
eth_mdc : out std_logic;
eth_reset : out std_logic;
eth_rxd : in unsigned(1 downto 0);
eth_txd : out unsigned(1 downto 0);
eth_txen : out std_logic;
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_interrupt : in std_logic;
----------------------------------------------------------------------
-- Flash RAM for holding config
----------------------------------------------------------------------
QspiSCK : out std_logic;
QspiDB : inout std_logic_vector(3 downto 0);
QspiCSn : out std_logic;
-------------------------------------------------------------------------
-- Lines for the SDcard interface itself
-------------------------------------------------------------------------
cs_bo : out std_logic;
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
---------------------------------------------------------------------------
-- Lines for other devices that we handle here
---------------------------------------------------------------------------
aclMISO : in std_logic;
aclMOSI : out std_logic;
aclSS : out std_logic;
aclSCK : out std_logic;
aclInt1 : in std_logic;
aclInt2 : in std_logic;
micData : in std_logic;
micClk : out std_logic;
micLRSel : out std_logic;
ampPWM : out std_logic;
ampSD : out std_logic;
tmpSDA : out std_logic;
tmpSCL : out std_logic;
tmpInt : in std_logic;
tmpCT : in std_logic;
sw : in std_logic_vector(15 downto 0);
btn : in std_logic_vector(4 downto 0);
seg_led : out unsigned(31 downto 0);
viciii_iomode : in std_logic_vector(1 downto 0);
colourram_at_dc00 : in std_logic;
---------------------------------------------------------------------------
-- IO port to far call stack
---------------------------------------------------------------------------
farcallstack_we : in std_logic;
farcallstack_addr : in std_logic_vector(8 downto 0);
farcallstack_din : in std_logic_vector(63 downto 0);
farcallstack_dout : out std_logic_vector(63 downto 0)
);
end iomapper;
architecture behavioral of iomapper is
component kickstart is
port (
Clk : in std_logic;
address : in std_logic_vector(13 downto 0);
we : in std_logic;
cs : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0));
end component;
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in unsigned(4 downto 0); -- address lines
di : in unsigned(7 downto 0); -- data in (to chip)
do : out unsigned(7 downto 0); -- data out (from chip)
pot_x : in unsigned(7 downto 0); -- paddle input-X
pot_y : in unsigned(7 downto 0); -- paddle input-Y
audio_data : out unsigned(17 downto 0)
);
end component;
component ethernet is
port (
clock : in std_logic;
clock50mhz : in std_logic;
reset : in std_logic;
irq : out std_logic := 'Z';
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio : inout std_logic;
eth_mdc : out std_logic;
eth_reset : out std_logic;
eth_rxd : in unsigned(1 downto 0);
eth_txd : out unsigned(1 downto 0);
eth_txen : out std_logic;
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_interrupt : in std_logic;
-- Signals from the VIC-IV frame packer to supply the compressed video feed
buffer_moby_toggle : in std_logic := '0';
buffer_address : out unsigned(11 downto 0);
buffer_rdata : in unsigned(7 downto 0);
---------------------------------------------------------------------------
-- keyboard event capture via ethernet
---------------------------------------------------------------------------
eth_keycode_toggle : out std_logic;
eth_keycode : out unsigned(15 downto 0);
fastio_addr : in unsigned(19 downto 0);
fastio_write : in std_logic;
fastio_read : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0)
);
end component;
component sdcardio is
port (
clock : in std_logic;
pixelclk : in std_logic;
reset : in std_logic;
---------------------------------------------------------------------------
-- fast IO port (clocked at core clock). 1MB address space
---------------------------------------------------------------------------
fastio_addr : in unsigned(19 downto 0);
fastio_read : in std_logic;
fastio_write : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0);
-- If colour RAM is mapped at $DC00-$DFFF, then don't map sector buffer
colourram_at_dc00 : in std_logic;
viciii_iomode : in std_logic_vector(1 downto 0);
sectorbuffermapped : out std_logic;
sectorbuffermapped2 : out std_logic;
sectorbuffercs : in std_logic;
led : out std_logic := '0';
motor : out std_logic := '0';
-------------------------------------------------------------------------
-- Lines for the SDcard interface itself
-------------------------------------------------------------------------
cs_bo : out std_logic;
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
---------------------------------------------------------------------------
-- Lines for other devices that we handle here
---------------------------------------------------------------------------
-- Accelerometer
aclMISO : in std_logic;
aclMOSI : out std_logic;
aclSS : out std_logic;
aclSCK : out std_logic;
aclInt1 : in std_logic;
aclInt2 : in std_logic;
-- Microphone
micData : in std_logic;
micClk : out std_logic;
micLRSel : out std_logic;
-- Audio in from digital SIDs
leftsid_audio : in unsigned(17 downto 0);
rightsid_audio : in unsigned(17 downto 0);
-- Audio output
ampPWM : out std_logic;
ampSD : out std_logic;
-- Temperature sensor
tmpSDA : out std_logic;
tmpSCL : out std_logic;
tmpInt : in std_logic;
tmpCT : in std_logic;
----------------------------------------------------------------------
-- Flash RAM for holding config
----------------------------------------------------------------------
QspiSCK : out std_logic;
QspiDB : inout std_logic_vector(3 downto 0);
QspiCSn : out std_logic;
last_scan_code : in std_logic_vector(12 downto 0);
-------------------------------------------------------------------------
-- And general switch inputs on the FPGA board (good as place as any here)
-------------------------------------------------------------------------
sw : in std_logic_vector(15 downto 0);
btn : in std_logic_vector(4 downto 0)
);
end component;
component cia6526 is
port (
cpuclock : in std_logic;
phi0 : in std_logic;
todclock : in std_logic;
reset : in std_logic;
irq : out std_logic := '1';
reg_isr_out : out unsigned(7 downto 0);
imask_ta_out : out std_logic;
---------------------------------------------------------------------------
-- fast IO port (clocked at core clock). 1MB address space
---------------------------------------------------------------------------
cs : in std_logic;
fastio_address : in unsigned(7 downto 0);
fastio_write : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0);
portaout : out std_logic_vector(7 downto 0);
portain : in std_logic_vector(7 downto 0);
portbout : out std_logic_vector(7 downto 0);
portbin : in std_logic_vector(7 downto 0);
flagin : in std_logic;
pcout : out std_logic;
spout : out std_logic;
spin : in std_logic;
countout : out std_logic;
countin : in std_logic);
end component;
component keymapper is
port (
pixelclk : in std_logic;
last_scan_code : out std_logic_vector(12 downto 0);
nmi : out std_logic := 'Z';
reset : out std_logic := 'Z';
-- PS2 keyboard interface
ps2clock : in std_logic;
ps2data : in std_logic;
-- CIA ports
porta_in : in std_logic_vector(7 downto 0);
portb_in : in std_logic_vector(7 downto 0);
porta_out : out std_logic_vector(7 downto 0);
portb_out : out std_logic_vector(7 downto 0);
---------------------------------------------------------------------------
-- keyboard event capture via ethernet
---------------------------------------------------------------------------
eth_keycode_toggle : in std_logic;
eth_keycode : in unsigned(15 downto 0)
);
end component;
component framepacker is
port (
pixelclock : in std_logic;
ioclock : in std_logic;
hypervisor_mode : in std_logic;
pixel_stream_in : in unsigned (7 downto 0);
pixel_y : in unsigned (11 downto 0);
pixel_valid : in std_logic;
pixel_newframe : in std_logic;
pixel_newraster : in std_logic;
-- Signals for ethernet controller
buffer_moby_toggle : out std_logic := '0';
buffer_address : in unsigned(11 downto 0);
buffer_rdata : out unsigned(7 downto 0);
---------------------------------------------------------------------------
-- fast IO port (clocked at CPU clock).
---------------------------------------------------------------------------
fastio_addr : in unsigned(19 downto 0);
fastio_write : in std_logic;
fastio_read : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0)
);
end component;
component farcallstack IS
PORT (
-- CPU fastio port
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- CPU parallel push/pop port
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
end component;
signal kickstartcs : std_logic;
signal reset_high : std_logic;
signal clock50hz : std_logic := '1';
constant divisor50hz : integer := 640000; -- 64MHz/50Hz/2;
signal counter50hz : integer := 0;
signal cia1cs : std_logic;
signal cia2cs : std_logic;
signal sectorbuffercs : std_logic;
signal sector_buffer_mapped_read : std_logic;
signal farcallstackcs : std_logic;
signal farcallstack_w : std_logic;
signal farcallstack_wdata : std_logic_vector(63 downto 0);
signal farcallstack_rdata : std_logic_vector(63 downto 0);
signal last_scan_code : std_logic_vector(12 downto 0);
signal cia1porta_out : std_logic_vector(7 downto 0);
signal cia1porta_in : std_logic_vector(7 downto 0);
signal cia1portb_out : std_logic_vector(7 downto 0);
signal cia1portb_in : std_logic_vector(7 downto 0);
signal leftsid_cs : std_logic;
signal leftsid_audio : unsigned(17 downto 0);
signal rightsid_cs : std_logic;
signal rightsid_audio : unsigned(17 downto 0);
signal spare_bits : unsigned(4 downto 0);
signal buffer_moby_toggle : std_logic;
signal buffer_address : unsigned(11 downto 0);
signal buffer_rdata : unsigned(7 downto 0);
signal eth_keycode_toggle : std_logic;
signal eth_keycode : unsigned(15 downto 0);
begin
kickstartrom : kickstart port map (
clk => clk,
address => address(13 downto 0),
we => w,
cs => kickstartcs,
data_i => data_i,
data_o => data_o);
framepacker0: framepacker port map (
ioclock => clk,
pixelclock => pixelclk,
hypervisor_mode => cpu_hypervisor_mode,
pixel_stream_in => pixel_stream_in,
pixel_y => pixel_y,
pixel_valid => pixel_valid,
pixel_newframe => pixel_newframe,
pixel_newraster => pixel_newraster,
buffer_moby_toggle => buffer_moby_toggle,
buffer_address => buffer_address,
buffer_rdata => buffer_rdata,
fastio_addr => unsigned(address(19 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_read => r,
fastio_wdata => unsigned(data_i)
);
cia1: cia6526 port map (
cpuclock => clk,
phi0 => phi0,
todclock => clock50hz,
reset => reset,
irq => irq,
reg_isr_out => reg_isr_out,
imask_ta_out => imask_ta_out,
cs => cia1cs,
fastio_address => unsigned(address(7 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_wdata => unsigned(data_i),
portaout => cia1porta_out,
portbout => cia1portb_out,
portain => cia1porta_in,
portbin => cia1portb_in,
flagin => '1',
spin => '1',
countin => '1'
);
cia2two: cia6526 port map (
cpuclock => clk,
phi0 => phi0,
todclock => clock50hz,
reset => reset,
irq => nmi,
cs => cia2cs,
fastio_address => unsigned(address(7 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_wdata => unsigned(data_i),
-- CIA ports not connected by default
portbin => x"ff",
portain => x"ff",
flagin => '1',
spin => '1',
countin => '1'
);
keymapper0 : keymapper port map (
pixelclk => clk,
nmi => restore_nmi,
reset => reset_out,
ps2clock => ps2clock,
ps2data => ps2data,
last_scan_code => last_scan_code,
-- key_status => seg_led(1 downto 0),
porta_in => cia1porta_out,
portb_in => cia1portb_out,
porta_out => cia1porta_in,
portb_out => cia1portb_in,
-- remote keyboard input via ethernet
-- eth_keycode_toggle => eth_keycode_toggle,
-- eth_keycode => eth_keycode
-- remote
eth_keycode_toggle => key_scancode_toggle,
eth_keycode => key_scancode
);
leftsid: sid6581 port map (
clk_1MHz => phi0,
clk32 => clk,
reset => reset_high,
cs => leftsid_cs,
we => w,
addr => unsigned(address(4 downto 0)),
di => unsigned(data_i),
std_logic_vector(do) => data_o,
pot_x => x"01",
pot_y => x"02",
audio_data => leftsid_audio);
rightsid: sid6581 port map (
clk_1MHz => phi0,
clk32 => clk,
reset => reset_high,
cs => rightsid_cs,
we => w,
addr => unsigned(address(4 downto 0)),
di => unsigned(data_i),
std_logic_vector(do) => data_o,
pot_x => x"03",
pot_y => x"04",
audio_data => rightsid_audio);
ethernet0 : ethernet port map (
clock50mhz => clock50mhz,
clock => clk,
reset => reset,
irq => irq,
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio => eth_mdio,
eth_mdc => eth_mdc,
eth_reset => eth_reset,
eth_rxd => eth_rxd,
eth_txd => eth_txd,
eth_txen => eth_txen,
eth_rxdv => eth_rxdv,
eth_rxer => eth_rxer,
eth_interrupt => eth_interrupt,
buffer_moby_toggle => buffer_moby_toggle,
buffer_address => buffer_address,
buffer_rdata => buffer_rdata,
eth_keycode_toggle => eth_keycode_toggle,
eth_keycode => eth_keycode,
fastio_addr => unsigned(address),
fastio_write => w,
fastio_read => r,
fastio_wdata => unsigned(data_i),
std_logic_vector(fastio_rdata) => data_o
);
sdcard0 : sdcardio port map (
pixelclk => pixelclk,
clock => clk,
reset => reset,
fastio_addr => unsigned(address),
fastio_write => w,
fastio_read => r,
fastio_wdata => unsigned(data_i),
std_logic_vector(fastio_rdata) => data_o,
colourram_at_dc00 => colourram_at_dc00,
viciii_iomode => viciii_iomode,
sectorbuffermapped => sector_buffer_mapped,
sectorbuffermapped2 => sector_buffer_mapped_read,
sectorbuffercs => sectorbuffercs,
led => led,
motor => motor,
sw => sw,
btn => btn,
cs_bo => cs_bo,
sclk_o => sclk_o,
mosi_o => mosi_o,
miso_i => miso_i,
aclMISO => aclMISO,
aclMOSI => aclMOSI,
aclSS => aclSS,
aclSCK => aclSCK,
aclInt1 => aclInt1,
aclInt2 => aclInt2,
micData => micData,
micClk => micClk,
micLRSel => micLRSel,
leftsid_audio => leftsid_audio,
rightsid_audio => rightsid_audio,
ampSD => ampSD,
ampPWM => ampPWM,
tmpSDA => tmpSDA,
tmpSCL => tmpSCL,
tmpInt => tmpInt,
tmpCT => tmpCT,
QspiSCK => QspiSCK,
QspiDB => QspiDB,
QspiCSn => QspiCSn,
last_scan_code => last_scan_code
);
farcallstack0: farcallstack port map (
clka => clk,
ena => farcallstackcs,
wea(0) => w,
addra => address(11 downto 0),
dina => data_i,
douta => data_o,
clkb => cpuclock,
web(0) => farcallstack_w,
addrb => farcallstack_addr,
dinb => farcallstack_wdata,
doutb => farcallstack_rdata
);
process(reset)
begin
reset_high <= not reset;
end process;
process(clk)
begin
if rising_edge(clk) then
-- Generate 50Hz signal for TOD clock
-- (Note that we are a bit conflicted here, as our video mode is PALx4,
-- but at 60Hz. We will make our CIAs take 50Hz like in most PAL countries
-- so that we don't confuse things too much. We will probably add a 50Hz
-- raster interrupt filter to help music and games play at the right rate.)
if counter50hz<divisor50hz then
counter50hz <= counter50hz + 1;
else
clock50hz <= not clock50hz;
counter50hz <= 0;
end if;
seg_led(12) <= eth_keycode_toggle;
seg_led(11) <= last_scan_code(12);
seg_led(10 downto 0) <= unsigned(last_scan_code(10 downto 0));
end if;
end process;
process (r,w,address,cia1portb_in,cia1porta_out,colourram_at_dc00,
sector_buffer_mapped_read)
begin -- process
if (r or w) = '1' then
-- @IO:GS $FFF8000-$FFFBFFF 16KB Kickstart/hypervisor ROM
-- @IO:GS $FFF8000 Hypervisor entry point when $D67F is written
if address(19 downto 14)&"00" = x"F8" then
kickstartcs <= cpu_hypervisor_mode;
else
kickstartcs <='0';
end if;
-- @IO:GS $FFF0000-$FFF0FFF - CPU far call stack (512x8 byte entries)
if address(19 downto 12) = x"F0" then
farcallstackcs <= '1';
else
farcallstackcs <= '0';
end if;
-- sdcard sector buffer: only mapped if no colour ram @ $DC00, and if
-- the sectorbuffer mapping flag is set
sectorbuffercs <= '0';
report "fastio address = $" & to_hstring(address) severity note;
if address(19 downto 16) = x"D"
and address(15 downto 14) = "00"
and address(11 downto 9)&'0' = x"E"
and sector_buffer_mapped_read = '1' and colourram_at_dc00 = '0' then
sectorbuffercs <= '1';
report "selecting SD card sector buffer" severity note;
end if;
-- Also map SD card sector buffer at $FFD6000 - $FFD61FF regardless of
-- VIC-IV IO mode and mapping of colour RAM
if address(19 downto 8) = x"D60" or address(19 downto 8) = x"D61" then
sectorbuffercs <= '1';
end if;
-- Now map the SIDs
-- @IO:C64 $D440-$D47F = left SID
-- @IO:C64 $D400-$D43F = right SID
-- @IO:C64 $D480-$D4FF = repeated images of SIDs
-- Presumably repeated through to $D5FF. But we will repeat to $D4FF only
-- so that we can use $D500-$D5FF for other stuff.
case address(19 downto 8) is
when x"D04" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D14" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D24" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D34" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when others => leftsid_cs <= '0'; rightsid_cs <= '0';
end case;
-- $D500 - $D5FF is not currently used. Probably use some for FPU.
-- $D600 - $D60F is reserved for 6551 serial UART emulation for C65
-- compatibility (6551 actually only has 4 registers).
-- 6551 is not currently implemented, so this is just unmapped for now,
-- except for any read values required to allow the C65 ROM to function.
-- Hypervisor control (only visible from hypervisor mode) $D640 - $D67F
-- The hypervisor is a CPU provided function.
-- SD controller and miscellaneous hardware (microphone, accelerometer etc)
-- uses $D680 - $D6FF
-- CPU uses $FFD{0,1,2,3}700 for DMAgic and other CPU-hosted IO registers.
-- Now map the CIAs.
-- These are a bit fun, because they only get mapped if colour RAM isn't
-- being mapped in $DC00-$DFFF using the C65 2K colour ram register
cia1cs <='0';
cia2cs <='0';
if colourram_at_dc00='0' and sector_buffer_mapped_read='0' then
case address(19 downto 8) is
when x"D0C" => cia1cs <='1';
when x"D1C" => cia1cs <='1';
when x"D2C" => cia1cs <='1';
when x"D3C" => cia1cs <='1';
when x"D0D" => cia2cs <='1';
when x"D1D" => cia2cs <='1';
when x"D2D" => cia2cs <='1';
when x"D3D" => cia2cs <='1';
when others => null;
end case;
end if;
else
cia1cs <= '0';
cia2cs <= '0';
kickstartcs <= '0';
sectorbuffercs <= '0';
leftsid_cs <= '0';
rightsid_cs <= '0';
farcallstackcs <= '0';
end if;
end process;
end behavioral;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last_value-attribute.vhdl | 4 | 424 | entity test is
end test;
architecture only of test is
signal s : bit;
begin
s <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
p: process
variable v: bit;
begin
wait for 1 ns;
wait for 25 ns;
v:=s'last_value;
assert v = '1' report "TEST FAILED - s previous value incorrect!" severity failure;
report "TEST PASSED v = 1" ;
wait;
end process;
end architecture only;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_05.vhd | 4 | 2034 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_17_05 is
end entity fg_17_05;
----------------------------------------------------------------
architecture test of fg_17_05 is
signal s : bit_vector(0 to 3);
begin
process is
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list, current_cell : value_ptr;
begin
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
-- code from book:
current_cell := value_list;
while current_cell /= null loop
s <= current_cell.value;
wait for 10 ns;
current_cell := current_cell.next_cell;
end loop;
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/sub_496.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_496 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_496;
architecture augh of sub_496 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1489.vhd | 4 | 1792 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1489.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p05n01i01489ent IS
END c08s08b00x00p05n01i01489ent;
ARCHITECTURE c08s08b00x00p05n01i01489arch OF c08s08b00x00p05n01i01489ent IS
BEGIN
TESTING: PROCESS
type x is (Jan,Feb,Mar);
variable y:x;
BEGIN
case y is
when Jan => NULL;
when Feb => NULL;
when Mar => NULL;
when Jan => NULL;
when others => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p05n01i01489 - Each choice in a case statement may only be represented once"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p05n01i01489arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_2in_switch.vhd | 4 | 2189 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_2in_switch is
end tb_2in_switch;
architecture TB_2in_switch of tb_2in_switch is
-- Component declarations
-- Signal declarations
terminal p_in1, p_in2, p_out : electrical;
signal ctl_ulogic : std_ulogic;
signal ctl_logic : std_logic;
begin
-- Signal assignments
ctl_ulogic <= To_X01(ctl_logic); -- Convert X01Z to X01
-- Component instances
vdc1 : entity work.v_constant(ideal)
generic map(
level => 1.0
)
port map(
pos => p_in1,
neg => ELECTRICAL_REF
);
vdc2 : entity work.v_constant(ideal)
generic map(
level => 3.0
)
port map(
pos => p_in2,
neg => ELECTRICAL_REF
);
Clk1 : entity work.clock(ideal)
generic map(
period => 10.0ms
)
port map(
clk_out => ctl_logic
);
R1 : entity work.resistor(ideal)
generic map(
res => 100.0
)
port map(
p1 => p_out,
p2 => electrical_ref
);
swtch : entity work.switch_dig_2in(ideal)
port map(
p_in1 => p_in1,
p_in2 => p_in2,
p_out => p_out,
sw_state => ctl_ulogic
);
end TB_2in_switch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2119.vhd | 4 | 2119 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2119.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02119ent IS
END c07s02b04x00p20n01i02119ent;
ARCHITECTURE c07s02b04x00p20n01i02119arch OF c07s02b04x00p20n01i02119ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_4 is integer_v (1 to 4);
SUBTYPE integer_null is integer_v (1 to 0);
BEGIN
TESTING : PROCESS
variable result : integer_4;
variable l_operand : integer_null;
variable r_operand : integer_4 := (123,789,123,789);
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = (123,789,123,789)) and (result(1) = 123))
report "***PASSED TEST: c07s02b04x00p20n01i02119"
severity NOTE;
assert ((result = (123,789,123,789)) and (result(1) = 123))
report "***FAILED TEST: c07s02b04x00p20n01i02119 - Concatenation of null and INTEGER arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02119arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd | 4 | 1593 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
signal y : bit := '0';
signal or_a_b : bit := '0';
signal clk : bit := '0';
begin
process_3_a : process is
begin
-- code from book:
y <= not or_a_b after 5 ns;
-- end of code from book
wait on or_a_b;
end process process_3_a;
stimulus_3_a : process is
begin
or_a_b <= '1' after 20 ns,
'0' after 40 ns;
wait;
end process stimulus_3_a;
process_3_b : process is
constant T_pw : delay_length := 10 ns;
begin
-- code from book:
clk <= '1' after T_pw, '0' after 2*T_pw;
-- end of code from book
wait for 2*T_pw;
end process process_3_b;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2387.vhd | 4 | 2033 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2387.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n01i02387ent IS
END c07s03b02x00p07n01i02387ent;
ARCHITECTURE c07s03b02x00p07n01i02387arch OF c07s03b02x00p07n01i02387ent IS
type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
type RECORD_TYPE is record
E1,E2 : BOOLEAN;
end record;
signal S2 : RECORD_TYPE;
BEGIN
TESTING: PROCESS
BEGIN
S2 <= ( FALSE, E2 => TRUE);
-- positional and named associations are legal.
wait for 1 ns;
assert NOT(S2.E1=FALSE and S2.E2=TRUE)
report "***PASSED TEST: c07s03b02x00p07n01i02387"
severity NOTE;
assert (S2.E1=FALSE and S2.E2=TRUE)
report "***FAILED TEST: c07s03b02x00p07n01i02387 - Both named and positional associations can be used in the same aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n01i02387arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2430.vhd | 4 | 1953 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2430.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n04i02430ent IS
END c07s03b02x01p01n04i02430ent;
ARCHITECTURE c07s03b02x01p01n04i02430arch OF c07s03b02x01p01n04i02430ent IS
type sigrec1 is
record
B1 : bit;
B2 : integer;
B3 : bit;
end record;
signal S1 : sigrec1;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= (('0' and '1'), 2, '1');
wait for 1 ns;
assert NOT(S1.B1='0' and S1.B2=2 and S1.B3='1')
report "***PASSED TEST: c07s03b02x01p01n04i02430"
severity NOTE;
assert (S1.B1='0' and S1.B2=2 and S1.B3='1')
report "***FAILED TEST: c07s03b02x01p01n04i02430 - Expression of an element association must have the same type as the associated record element."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n04i02430arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1873.vhd | 4 | 1929 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1873.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01873ent IS
END c07s01b00x00p08n01i01873ent;
ARCHITECTURE c07s01b00x00p08n01i01873arch OF c07s01b00x00p08n01i01873ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 => tmp := 0;
when others => tmp := 1;
end case;
return TESTING; -- process labels illegal here
end value;
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01873d - Process labels are not permitted as primaries in a function return expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01873arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2249.vhd | 4 | 1781 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2249.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02249ent IS
END c07s02b06x00p01n01i02249ent;
ARCHITECTURE c07s02b06x00p01n01i02249arch OF c07s02b06x00p01n01i02249ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
type WORDPTR is access WORD;
variable WORDPTRV,
WORDPTR2V: WORDPTR;
variable k : integer;
BEGIN
k := WORDPTRV mod WORDPTR2V;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02249 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02249arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3049.vhd | 4 | 2385 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3049.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03049ent_a IS
port(con : in BIT := '1'; clk : out BIT);
END c12s02b04x00p03n01i03049ent_a;
ARCHITECTURE c12s02b04x00p03n01i03049arch_a OF c12s02b04x00p03n01i03049ent_a IS
BEGIN
process(con)
begin
clk <= con;
end process;
END c12s02b04x00p03n01i03049arch_a;
ENTITY c12s02b04x00p03n01i03049ent IS
END c12s02b04x00p03n01i03049ent;
ARCHITECTURE c12s02b04x00p03n01i03049arch OF c12s02b04x00p03n01i03049ent IS
signal C : bit := '0';
component c12s02b04x00p03n01i03049ent_aa
port ( con : IN bit := '1';
clk : OUT bit );
end component;
for all : c12s02b04x00p03n01i03049ent_aa use entity work.c12s02b04x00p03n01i03049ent_a(c12s02b04x00p03n01i03049arch_a);
BEGIN
T1 : c12s02b04x00p03n01i03049ent_aa port map (open, C);
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( C = '1' )
report "***PASSED TEST: c12s02b04x00p03n01i03049"
severity NOTE;
assert ( C = '1' )
report "***FAILED TEST: c12s02b04x00p03n01i03049 - A port of mode in assumes the value of the default expression when there is no associated signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s02b04x00p03n01i03049arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug08/paren12.vhdl | 3 | 365 | entity paren12 is
end paren12;
architecture behav of paren12
is
begin
proc: process
type string_acc is access string;
variable hel : string_acc := new string'("hello");
impure function a return string_acc is
begin
return hel;
end a;
constant b : natural := 2;
begin
assert proc.a(b) = 'e';
wait;
end process;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1311.vhd | 4 | 1893 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1311.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p07n02i01311ent IS
END c08s04b00x00p07n02i01311ent;
ARCHITECTURE c08s04b00x00p07n02i01311arch OF c08s04b00x00p07n02i01311ent IS
type sigrec is
record
A1 : bit;
A2 : integer;
A3 : character;
A4 : boolean;
end record;
signal S1 : bit;
signal S2 : integer;
signal S3 : character;
signal S4 : boolean;
BEGIN
TESTING: PROCESS
BEGIN
(S1, S2, S3, S4) <= sigrec'('1', 1.2, '1', true);
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p07n02i01311 - Base type of waveform element is not the same as the base type of the signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n02i01311arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3117.vhd | 4 | 3342 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3117.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p03n01i03117ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p03n01i03117ent_a;
ARCHITECTURE c05s02b01x01p03n01i03117arch_a OF c05s02b01x01p03n01i03117ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p03n01i03117arch_a;
ARCHITECTURE c05s02b01x01p03n01i03117arch_b OF c05s02b01x01p03n01i03117ent_a IS
BEGIN
p2 <= p1 after 15 ns;
END c05s02b01x01p03n01i03117arch_b;
configuration c05s02b01x01p03n01i03117cfg_a of c05s02b01x01p03n01i03117ent_a is
for c05s02b01x01p03n01i03117arch_a
end for;
end c05s02b01x01p03n01i03117cfg_a;
configuration c05s02b01x01p03n01i03117cfg_b of c05s02b01x01p03n01i03117ent_a is
for c05s02b01x01p03n01i03117arch_b
end for;
end c05s02b01x01p03n01i03117cfg_b;
--
ENTITY c05s02b01x01p03n01i03117ent IS
END c05s02b01x01p03n01i03117ent;
ARCHITECTURE c05s02b01x01p03n01i03117arch OF c05s02b01x01p03n01i03117ent IS
component ic_socket
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : ic_socket
generic map ( true )
port map (s1, s2);
u2 : ic_socket
generic map ( true )
port map (s2, s3);
u3 : ic_socket
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p03n01i03117"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p03n01i03117 - Entity declaration denoted by the entity name together with an architecture body binding in configuration blocks test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p03n01i03117arch;
configuration c05s02b01x01p03n01i03117cfg of c05s02b01x01p03n01i03117ent is
for c05s02b01x01p03n01i03117arch
for all : ic_socket use entity work.c05s02b01x01p03n01i03117ent_a (c05s02b01x01p03n01i03117arch_a);
end for;
end for;
end c05s02b01x01p03n01i03117cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket92/cover_report2.vhd | 2 | 907 | library ieee;
use ieee.std_logic_1164.all;
library std;
use std.env.all;
entity cover_report2 is
end entity cover_report2;
architecture test of cover_report2 is
signal s_a : std_logic;
signal s_b : std_logic;
signal s_c : std_logic;
signal s_clk : std_logic := '0';
begin
s_clk <= not(s_clk) after 5 ns;
process is
begin
s_a <= '0';
s_b <= '0';
s_c <= '0';
wait until rising_edge(s_clk);
s_a <= '1';
wait until rising_edge(s_clk);
s_a <= '0';
s_b <= '1';
wait until rising_edge(s_clk);
s_b <= '0';
s_c <= '1';
wait until rising_edge(s_clk);
s_c <= '0';
stop(0);
end process;
-- psl default clock is rising_edge(s_clk);
--
-- psl sequence test_p is {s_a; s_b};
--
-- DOES WORK
-- -- psl TEST : cover test_p;
--
-- DOESN'T WORK:
-- psl cover test_p report "Covered";
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd | 4 | 3363 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture std_cell of inline_08 is
attribute cell_name : string;
attribute pin_number : positive;
attribute max_wire_delay : delay_length;
attribute encoding : bit_vector;
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
attribute cell_position : coordinate;
type built_in_type is (bv_incr, std_incr);
attribute built_in : built_in_type;
signal enable, clk : bit;
type state_type is (idle_state, other_state);
type speed_range is (high, other_speed);
type coolant_level is (high, other_level);
attribute representation : string;
function increment ( vector : in bit_vector ) return bit_vector is
begin
end;
function increment ( vector : in std_logic_vector ) return std_logic_vector is
begin
end;
attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
attribute pin_number of enable : signal is 14;
attribute max_wire_delay of clk : signal is 50 ps;
attribute encoding of idle_state : literal is b"0000";
attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
attribute built_in of
increment [ bit_vector return bit_vector ] : function is bv_incr;
attribute built_in of
increment [ std_logic_vector return std_logic_vector ] : function is std_incr;
attribute representation of high [ return speed_range ] : literal is "byte";
attribute representation of high [ return coolant_level ] : literal is "word";
begin
the_fpu : block is
begin
end block the_fpu;
process is
variable v1 : string(1 to 11);
variable v2 : positive;
variable v3 : time;
variable v4 : bit_vector(0 to 3);
variable v5 : coordinate;
variable v6, v7 : built_in_type;
variable v8, v9 : string(1 to 4);
begin
-- code from book included...
v1 := std_cell'cell_name ;
v2 := enable'pin_number ;
v3 := clk'max_wire_delay ;
v4 := idle_state'encoding ;
v5 := the_fpu'cell_position ;
v6 := increment [ bit_vector return bit_vector ] 'built_in ;
v7 := increment [ std_logic_vector return std_logic_vector ] 'built_in ;
v8 := high [ return speed_range ] 'representation ;
v9 := high [ return coolant_level ] 'representation ;
-- end code from book
wait;
end process;
end architecture std_cell;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc714.vhd | 4 | 1552 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc714.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b00x00p02n01i00714ent IS
BEGIN
;
ARCHITECTURE c01s01b00x00p02n01i00714arch OF c01s01b00x00p02n01i00714ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b00x00p02n01i00714 - Missing end in entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b00x00p02n01i00714arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf.vhd | 4 | 1589 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_rf.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.dlx_types.all,
work.reg_file_types.all;
entity reg_file is
generic ( Tac : delay_length );
port ( a1 : in reg_file_addr;
q1 : out dlx_word;
a2 : in reg_file_addr;
q2 : out dlx_word;
a3 : in reg_file_addr;
d3 : in dlx_word;
write_en : in std_logic );
end entity reg_file;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc30.vhd | 4 | 2020 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc30.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b00x00p14n04i00030ent IS
END c04s03b00x00p14n04i00030ent;
ARCHITECTURE c04s03b00x00p14n04i00030arch OF c04s03b00x00p14n04i00030ent IS
signal M1 : BIT_VECTOR(0 to 7) ;
constant M2 : BIT := '1' ;
BEGIN
TESTING: PROCESS
variable V1 : BIT;
BEGIN
M1(3) <= '1' after 10 ns;
--- No_failure_here
--- M1(3) is also a signal; so this signal
--- assignment is possible.
V1 := M2;
wait for 10 ns;
assert NOT( M1(3)='1' and V1='1' )
report "***PASSED TEST: c04s03b00x00p14n04i00030"
severity NOTE;
assert ( M1(3)='1' and V1='1' )
report "***FAILED TEST:c04s03b00x00p14n04i00030 - Each subelement of that object is itself an object of the same class as the given object."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b00x00p14n04i00030arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1135.vhd | 4 | 2104 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1135.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01135ent IS
END c06s05b00x00p04n01i01135ent;
ARCHITECTURE c06s05b00x00p04n01i01135arch OF c06s05b00x00p04n01i01135ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5);
type ENUM2 is (N1, N2, N3, N4, N5);
type FIVE1 is range 1 to 5;
type FIVE2 is range 1 to 5;
variable VE1LOW: ENUM1 := M2;
variable VE2HIGH: ENUM2 := N4;
variable VF1LOW: FIVE1 := 2;
variable VF2HIGH: FIVE2 := 4;
type AE5 is array (M1 to M5) of BOOLEAN;
type AF5 is array (FIVE1) of BOOLEAN;
variable VAE5: AE5 ;
variable VAF5: AF5 ;
BEGIN
VAE5(M2 to M4) := VAE5(VE1LOW to VE2HIGH);
-- SEMANTIC ERROR: BOUNDS OF DISCRETE RANGE MUST BE OF SAME TYPE
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01135 - Bounds of discrete ranges must be of same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01135arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/perf02/cmp_673.vhd | 3 | 378 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_673 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end cmp_673;
architecture augh of cmp_673 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc932.vhd | 4 | 2512 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc932.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s04b00x00p03n03i00932pkg is
subtype register16 is bit_vector(15 downto 0);
function "+" (l,r : bit_vector) return bit_vector;
function "-" (l,r : bit_vector) return bit_vector;
end c10s04b00x00p03n03i00932pkg;
package body c10s04b00x00p03n03i00932pkg is
function "+" (l,r : bit_vector) return bit_vector is
begin
return (B"1111010100101010");
end;
function "-" (l,r : bit_vector) return bit_vector is
begin
return (B"1111010100101010");
end;
end c10s04b00x00p03n03i00932pkg;
use work.c10s04b00x00p03n03i00932pkg.all;
ENTITY c10s04b00x00p03n03i00932ent IS
END c10s04b00x00p03n03i00932ent;
ARCHITECTURE c10s04b00x00p03n03i00932arch OF c10s04b00x00p03n03i00932ent IS
signal i_sig : register16 := B"1010_1110_1010_0011";
BEGIN
TESTING: PROCESS
BEGIN
i_sig <= i_sig - i_sig + B"1111111100000000" after 10 ns;
wait for 20 ns;
assert NOT( i_sig = (B"1111010100101010") )
report "***PASSED TEST: c10s04b00x00p03n03i00932"
severity NOTE;
assert ( i_sig = (B"1111010100101010") )
report "***FAILED TEST: c10s04b00x00p03n03i00932 - All of the declarations of a package are visible within the declarative region if the suffix of a selected name in a use clause is the word 'all'."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s04b00x00p03n03i00932arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd | 4 | 2084 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_07 is
end entity inline_07;
----------------------------------------------------------------
library ieee; use ieee.numeric_bit.all;
architecture test of inline_07 is
begin
process_5_a : process is
-- code from book:
procedure increment ( a : inout integer; n : in integer := 1 ) is -- . . .
-- not in book
begin
a := a + n;
end procedure increment;
-- end not in book;
procedure increment ( a : inout bit_vector; n : in bit_vector := B"1" ) is -- . . .
-- not in book
begin
a := bit_vector(signed(a) + signed(n));
end procedure increment;
-- end not in book;
procedure increment ( a : inout bit_vector; n : in integer := 1 ) is -- . . .
-- not in book
begin
a := bit_vector(signed(a) + to_signed(n, a'length));
end procedure increment;
-- end not in book;
variable count_int : integer := 2;
variable count_bv : bit_vector (15 downto 0) := X"0002";
-- end of code from book
begin
-- code from book:
increment ( count_int, 2 );
increment ( count_int );
increment ( count_bv, X"0002");
increment ( count_bv, 1 );
-- increment ( count_bv );
-- end of code from book
wait;
end process process_5_a;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_09.vhd | 4 | 1780 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_09 is
end entity inline_09;
----------------------------------------------------------------
architecture test of inline_09 is
begin
process is
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list, cell_to_be_deleted : value_ptr;
begin
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
-- code from book:
cell_to_be_deleted := value_list;
value_list := value_list.next_cell;
deallocate(cell_to_be_deleted);
while value_list /= null loop
cell_to_be_deleted := value_list;
value_list := value_list.next_cell;
deallocate(cell_to_be_deleted);
end loop;
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2204.vhd | 4 | 1745 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2204.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02204ent IS
END c07s02b06x00p01n01i02204ent;
ARCHITECTURE c07s02b06x00p01n01i02204arch OF c07s02b06x00p01n01i02204ent IS
BEGIN
TESTING: PROCESS
constant a : integer := 10 / 2;
BEGIN
assert NOT(a = 5)
report "***PASSED TEST: c07s02b06x00p01n01i02204"
severity NOTE;
assert (a = 5)
report "***FAILED TEST: c07s02b06x00p01n01i02204 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02204arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc672.vhd | 4 | 3202 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc672.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:58 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:29 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:38 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00672ent IS
END c03s04b01x00p23n01i00672ent;
ARCHITECTURE c03s04b01x00p23n01i00672arch OF c03s04b01x00p23n01i00672ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ('0', '1', 'X');
type FT is file of SWITCH_LEVEL;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.48";
-- Declare a variable into which we will read.
constant CON : SWITCH_LEVEL := '1';
variable VAR : SWITCH_LEVEL ;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00672"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00672 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00672arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd | 4 | 1602 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
----------------------------------------------------------------
architecture test_behavior of tb_counter is
signal clk, reset : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, reset => reset, count => count );
stimulus : process is
begin
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '1' after 15 ns;
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '0' after 15 ns;
for cycle_count in 1 to 30 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_behavior;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc238.vhd | 4 | 1899 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc238.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00238ent IS
END c03s01b02x00p04n01i00238ent;
ARCHITECTURE c03s01b02x00p04n01i00238arch OF c03s01b02x00p04n01i00238ent IS
type t3 is range (ns/fs) downto (fs/fs);
BEGIN
TESTING: PROCESS
variable k : integer := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p04n01i00238"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p04n01i00238 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00238arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd | 4 | 1833 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_15 is
end entity inline_15;
----------------------------------------------------------------
architecture test of inline_15 is
begin
process_3_c : process is
-- code from book:
subtype name is string(1 to 20);
type display_string is array (integer range 0 to 19) of character;
variable item_name : name;
variable display : display_string;
--
subtype big_endian_upper_halfword is bit_vector(0 to 15);
subtype little_endian_upper_halfword is bit_vector(31 downto 16);
variable big : big_endian_upper_halfword;
variable little : little_endian_upper_halfword;
-- end of code from book
begin
-- error: Incompatible types for assignment
-- display := item_name; -- ilegal
item_name := (others => 'A');
little := x"AAAA";
-- code from book:
display := display_string(item_name);
--
big := little;
little := big;
-- end of code from book
wait;
end process process_3_c;
----------------
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2427.vhd | 4 | 1842 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2427.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n03i02427ent IS
END c07s03b02x01p01n03i02427ent;
ARCHITECTURE c07s03b02x01p01n03i02427arch OF c07s03b02x01p01n03i02427ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
ele_3 : boolean;
end record;
constant p :rec := (ele_1 | ele_2 | ele_3 => 4.5); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n03i02427 - Element association with others choice should be used to represent elements of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n03i02427arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd | 4 | 1577 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
component opamp is
port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
end component opamp;
terminal plus_in, minus_in, output, vdd, vss, gnd : electrical;
begin
voltage_amp : component opamp
port map ( plus_in => plus_in, minus_in => minus_in, output => output,
vdd => vdd, vss => vss, gnd => gnd );
end architecture test;
configuration inline_04a_test of inline_04a is
for test
-- code from book (in text)
for voltage_amp : opamp
use configuration work.opamp_mosfets;
end for;
-- end code from book
end for;
end configuration inline_04a_test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp.vhd | 4 | 1437 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_regmp.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.dlx_types.all;
entity reg_multiple_plus_one_out is
generic ( num_outputs : positive;
Tpd : delay_length );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end entity reg_multiple_plus_one_out;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1752.vhd | 4 | 1879 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1752.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p25n01i01752ent IS
generic (g1: integer := 12);
port (
input1: in bit ;
input2: in bit ;
clk : in boolean;
output: out bit);
END c09s05b00x00p25n01i01752ent;
ARCHITECTURE c09s05b00x00p25n01i01752arch OF c09s05b00x00p25n01i01752ent IS
type a is array (1 to 4) of boolean;
signal i : a;
BEGIN
(i(g1), i(2), i(3), i(4)) <= a'(true, false, false, true);
-- Failure_here : i(g1) is not a locally static name
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b00x00p25n01i01752 - Only locally static signal names may contain here."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b00x00p25n01i01752arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc69.vhd | 4 | 2073 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc69.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p07n05i00069ent IS
END c04s03b01x02p07n05i00069ent;
ARCHITECTURE c04s03b01x02p07n05i00069arch OF c04s03b01x02p07n05i00069ent IS
signal S1 : BIT_VECTOR(0 to 3) := ("0101" and "0101");
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( S1(0) = '0' and
S1(1) = '1' and
S1(2) = '0' and
S1(3) = '1' )
report "***PASSED TEST: c04s03b01x02p07n05i00069"
severity NOTE;
assert ( S1(0) = '0' and
S1(1) = '1' and
S1(2) = '0' and
S1(3) = '1' )
report "***FAILED TEST: c04s03b01x02p07n05i00069 - Each subelement of the value of the composite subtype is the default value of the corresponding subelement of the signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x02p07n05i00069arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket24/psl.vhdl | 2 | 684 | entity psl is
end;
architecture behav of psl is
signal a, b, c : bit;
signal clk : bit;
subtype wf_type is bit_vector (0 to 7);
constant wave_a : wf_type := "10010100";
constant wave_b : wf_type := "01001010";
constant wave_c : wf_type := "00100101";
begin
process
begin
for i in wf_type'range loop
clk <= '0';
wait for 1 ns;
a <= wave_a (i);
b <= wave_b (i);
c <= wave_c (i);
clk <= '1';
wait for 1 ns;
end loop;
wait;
end process;
-- psl default clock is (clk'event and clk = '1');
-- psl a1: assert always a |=> b;
-- psl a2: assert always a -> eventually! c;
-- psl c1: cover {a;b;c};
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1298.vhd | 4 | 1674 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1298.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01298ent IS
END c08s04b00x00p06n01i01298ent;
ARCHITECTURE c08s04b00x00p06n01i01298arch OF c08s04b00x00p06n01i01298ent IS
signal X : integer := 5;
BEGIN
TESTING: PROCESS
subtype q is integer range 1 to 10;
BEGIN
q <= X;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p06n01i01298 - The target of a signal assignment must be a signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01298arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc32.vhd | 4 | 18103 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc32.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p01n01i00032ent IS
END c04s03b01x01p01n01i00032ent;
ARCHITECTURE c04s03b01x01p01n01i00032arch OF c04s03b01x01p01n01i00032ent IS
--
-- Declaration of composite types
--
TYPE U1 IS ARRAY (CHARACTER RANGE <>) OF INTEGER; -- unconstrained array type
TYPE C1 IS ARRAY (5 TO 9) OF BIT; -- constrained array type
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE R1 IS
RECORD
month : month_name;
day : INTEGER RANGE 0 TO 31;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
-- Declaration of composite - composite types
--
TYPE US1 IS ARRAY (INTEGER RANGE <> ) OF STRING ( 1 TO 8 );
TYPE UV1 IS ARRAY (INTEGER RANGE <> ) OF BIT_VECTOR ( 3 DOWNTO 0 );
TYPE UU1 IS ARRAY (INTEGER RANGE <> ) OF U1 ('a' TO 'd');
TYPE UC1 IS ARRAY (INTEGER RANGE <> ) OF C1;
TYPE UR1 IS ARRAY (INTEGER RANGE <> ) OF R1;
TYPE CS1 IS ARRAY (INTEGER RANGE 0 TO 3) OF STRING ( 1 TO 8 );
TYPE CV1 IS ARRAY (INTEGER RANGE 0 TO 3) OF BIT_VECTOR ( 3 DOWNTO 0 );
TYPE CU1 IS ARRAY (INTEGER RANGE 0 TO 3) OF U1 ('a' TO 'd');
TYPE CC1 IS ARRAY (INTEGER RANGE 0 TO 3) OF C1;
TYPE CR1 IS ARRAY (INTEGER RANGE 0 TO 3) OF R1;
TYPE RAR IS RECORD
eS1 : STRING ( 1 TO 8 );
eV1 : BIT_VECTOR ( 3 DOWNTO 0 );
eU1 : U1 ('a' TO 'd');
eC1 : C1 ;
eR1 : R1 ;
END RECORD;
----------------------------------------------------------------------------------------
--
-- CONSTANT declarations - initial aggregate value
-- NOTE: index constraints for the unconstrained types are
-- established by the intial value.
--
CONSTANT US1_con_1 : US1 := (
(NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL),
(BS, HT, LF, VT, FF, CR, SO, SI ),
(DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB),
(CAN, EM, SUB, ESC, FSP, GSP, RSP, USP)
);
CONSTANT UV1_con_1 : UV1 := (
('0', '1', '0', '0'),
('1', '0', '1', '1'),
('1', '0', '0', '0'),
('0', '1', '0', '1')
);
CONSTANT UU1_con_1 : UU1 := (
( 1, 2, 3, 4),
( 5, 6, 7, 8),
( 9, 10, 11, 12),
( 13, 14, 15, 16)
);
CONSTANT UC1_con_1 : UC1 := (
('0', '1', '0', '0', '1'),
('0', '1', '1', '1', '0'),
('0', '0', '0', '1', '0'),
('1', '0', '0', '0', '1')
);
CONSTANT UR1_con_1 : UR1 := ( (Feb,05,1701),
(Apr,10,1802),
(Jun,15,1903),
(Aug,20,2004) );
CONSTANT CS1_con_1 : CS1 := (
(NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL),
(BS, HT, LF, VT, FF, CR, SO, SI ),
(DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB),
(CAN, EM, SUB, ESC, FSP, GSP, RSP, USP)
);
CONSTANT CV1_con_1 : CV1 := (
('0', '1', '0', '0'),
('1', '0', '1', '1'),
('1', '0', '0', '0'),
('0', '1', '0', '1')
);
CONSTANT CU1_con_1 : CU1 := (
( 1, 2, 3, 4),
( 5, 6, 7, 8),
( 9, 10, 11, 12),
( 13, 14, 15, 16)
);
CONSTANT CC1_con_1 : CC1 := (
('0', '1', '0', '0', '1'),
('0', '1', '1', '1', '0'),
('0', '0', '0', '1', '0'),
('1', '0', '0', '0', '1')
);
CONSTANT CR1_con_1 : CR1 := ( (Feb,05,1701),
(Apr,10,1802),
(Jun,15,1903),
(Aug,20,2004) );
CONSTANT RAR_con_1 : RAR := (
(SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS ),
('1', '1', '0', '0'),
( 1, 2, 3, 4),
('0', '1', '0', '0', '1'),
(Feb,29,0108) );
--
-- CONSTANT declarations - aggregate of strings initial value
--
CONSTANT US1_con_2 : US1 := ( "@ABCDEFG", "HIJKLMNO", "PQRSTUVW", "XYZ[\]^_" );
CONSTANT UV1_con_2 : UV1 := ( B"0100", B"1011", B"1000", B"0101" );
CONSTANT UC1_con_2 : UC1 := ( B"01001", B"01110", B"00010", B"10001" );
CONSTANT CS1_con_2 : CS1 := ( "@ABCDEFG", "HIJKLMNO", "PQRSTUVW", "XYZ[\]^_" );
CONSTANT CV1_con_2 : CV1 := ( B"0100", B"1011", B"1000", B"0101" );
CONSTANT CC1_con_2 : CC1 := ( B"01001", B"01110", B"00010", B"10001" );
CONSTANT RAR_con_2 : RAR := ( "@ABCDEFG", B"1100", (1,2,3,4), B"01001", (Feb,29,0108) );
-----------------------------------------------------------------------------------------
BEGIN
TESTING: PROCESS
--
-- Declarationi for generation of BIT test pattern
--
VARIABLE bval : BIT;
VARIABLE index : INTEGER;
VARIABLE ii : INTEGER;
variable k : integer := 0;
PROCEDURE pattern ( index : INOUT INTEGER; bval : OUT BIT ) IS
--
-- if starting index value is 59, the
-- test pattern is 01001011100001010001111 (repeats)
--
BEGIN
IF index > 100
THEN bval := '1';
index := index - 100;
ELSE bval := '0';
END IF;
index := index * 2;
END;
BEGIN
----------------------------------------------------------------------------------------
--
-- Verify initial values
--
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 1 TO 8 LOOP
if (US1_con_1(ii)(J) /= CHARACTER'VAL((I*8)+(J-1))) then
k := 1;
end if;
ASSERT US1_con_1(ii)(J) = CHARACTER'VAL((I*8)+(J-1))
REPORT "ERROR: Bad initial value of US1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 3 DOWNTO 0 LOOP
pattern ( index, bval );
if (UV1_con_1(ii)(J) /= bval) then
k := 1;
end if;
ASSERT UV1_con_1(ii)(J) = bval
REPORT "ERROR: Bad initial value of UV1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 0;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 'a' TO 'd' LOOP
index := index + 1;
if (UU1_con_1(ii)(J) /= index) then
k := 1;
end if;
ASSERT UU1_con_1(ii)(J) = index
REPORT "ERROR: Bad initial value of UU1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (UC1_con_1(ii)(J) /= bval) then
k := 1;
end if;
ASSERT UC1_con_1(ii)(J) = bval
REPORT "ERROR: Bad initial value of UC1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
if (UR1_con_1(ii).month /= month_name'VAL((I*2)+1)) then
k := 1;
end if;
ASSERT UR1_con_1(ii).month = month_name'VAL((I*2)+1)
REPORT "ERROR: Bad initial value of UR1_con_1(ii).month" SEVERITY FAILURE;
if (UR1_con_1(ii).day /= I*5 +5) then
k := 1;
end if;
ASSERT UR1_con_1(ii).day = I*5 + 5
REPORT "ERROR: Bad initial value of UR1_con_1(ii).day" SEVERITY FAILURE;
if (UR1_con_1(ii).year /= 1701 +(I*101)) then
k := 1;
end if;
ASSERT UR1_con_1(ii).year = 1701 + (I*101)
REPORT "ERROR: Bad initial value of UR1_con_1(ii).year" SEVERITY FAILURE;
END LOOP;
--
FOR I IN 0 TO 3 LOOP
FOR J IN 1 TO 8 LOOP
if (CS1_con_1(I)(J) /= CHARACTER'VAL((I*8)+(J-1))) then
k := 1;
end if;
ASSERT CS1_con_1(I)(J) = CHARACTER'VAL((I*8)+(J-1))
REPORT "ERROR: Bad initial value of CS1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP
FOR J IN 3 DOWNTO 0 LOOP
pattern ( index, bval );
if (CV1_con_1(I)(J) /= bval) then
k := 1;
end if;
ASSERT CV1_con_1(I)(J) = bval
REPORT "ERROR: Bad initial value of CV1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 0;
FOR I IN 0 TO 3 LOOP
FOR J IN 'a' TO 'd' LOOP
index := index + 1;
if (CU1_con_1(I)(J) /= index) then
k := 1;
end if;
ASSERT CU1_con_1(I)(J) = index
REPORT "ERROR: Bad initial value of CU1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (CC1_con_1(I)(J) /= bval) then
k := 1;
end if;
ASSERT CC1_con_1(I)(J) = bval
REPORT "ERROR: Bad initial value of CC1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
FOR I IN 0 TO 3 LOOP
if (CR1_con_1(I).month /= month_name'VAL((I*2)+1)) then
k := 1;
end if;
ASSERT CR1_con_1(I).month = month_name'VAL((I*2)+1)
REPORT "ERROR: Bad initial value of CR1_con_1(I).month" SEVERITY FAILURE;
if (CR1_con_1(I).day /= (I+1)*5) then
k := 1;
end if;
ASSERT CR1_con_1(I).day = (I+1)*5
REPORT "ERROR: Bad initial value of CR1_con_1(I).day" SEVERITY FAILURE;
if (CR1_con_1(I).year /= 1701 + (I*101)) then
k := 1;
end if;
ASSERT CR1_con_1(I).year = 1701 + (I*101)
REPORT "ERROR: Bad initial value of CR1_con_1(I).year" SEVERITY FAILURE;
END LOOP;
--
FOR J IN 1 TO 8 LOOP
if (RAR_con_1.eS1(J) /= CHARACTER'VAL(J)) then
k := 1;
end if;
ASSERT RAR_con_1.eS1(J) = CHARACTER'VAL(J)
REPORT "ERROR: Bad initial value of RAR_con_1.eS1" SEVERITY FAILURE;
END LOOP;
FOR J IN 3 DOWNTO 0 LOOP
if (RAR_con_1.eV1(J) /= BIT'VAL(J/2)) then
k := 1;
end if;
ASSERT RAR_con_1.eV1(J) = BIT'VAL(J/2)
REPORT "ERROR: Bad initial value of RAR_con_1.eV1" SEVERITY FAILURE;
END LOOP;
index := 0;
FOR J IN 'a' TO 'd' LOOP
index := index + 1;
if (RAR_con_1.eU1(J) /= index) then
k := 1;
end if;
ASSERT RAR_con_1.eU1(J) = index
REPORT "ERROR: Bad initial value of RAR_con_1.eU1" SEVERITY FAILURE;
END LOOP;
index := 59;
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (RAR_con_1.eC1(J) /= bval) then
k := 1;
end if;
ASSERT RAR_con_1.eC1(J) = bval
REPORT "ERROR: Bad initial value of RAR_con_1.eC1" SEVERITY FAILURE;
END LOOP;
if (RAR_con_1.eR1.month /= FEB) then
k := 1;
end if;
ASSERT RAR_con_1.eR1.month = FEB
REPORT "ERROR: Bad initial value of RAR_con_1.eR1.month" SEVERITY FAILURE;
if (RAR_con_1.eR1.day /= 29) then
k := 1;
end if;
ASSERT RAR_con_1.eR1.day = 29
REPORT "ERROR: Bad initial value of RAR_con_1.eR1.day" SEVERITY FAILURE;
if (RAR_con_1.eR1.year /= 0108) then
k := 1;
end if;
ASSERT RAR_con_1.eR1.year = 0108
REPORT "ERROR: Bad initial value of RAR_con_1.eR1.year" SEVERITY FAILURE;
-- ----------------------------------------------------------------------------------
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 1 TO 8 LOOP
if (US1_con_2(ii)(J) /= CHARACTER'VAL((I*8)+(J-1)+64)) then
k := 1;
end if;
ASSERT US1_con_2(ii)(J) = CHARACTER'VAL((I*8)+(J-1)+64)
REPORT "ERROR: Bad initial value of US1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 3 DOWNTO 0 LOOP
pattern ( index, bval );
if (UV1_con_2(ii)(J) /= bval) then
k := 1;
end if;
ASSERT UV1_con_2(ii)(J) = bval
REPORT "ERROR: Bad initial value of UV1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (UC1_con_2(ii)(J) /= bval) then
k := 1;
end if;
ASSERT UC1_con_2(ii)(J) = bval
REPORT "ERROR: Bad initial value of UC1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
--
FOR I IN 0 TO 3 LOOP
FOR J IN 1 TO 8 LOOP
if (CS1_con_2(I)(J) /= CHARACTER'VAL((I*8)+(J-1)+64)) then
k := 1;
end if;
ASSERT CS1_con_2(I)(J) = CHARACTER'VAL((I*8)+(J-1)+64)
REPORT "ERROR: Bad initial value of CS1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP
FOR J IN 3 DOWNTO 0 LOOP
pattern ( index, bval );
if (CV1_con_2(I)(J) /= bval) then
k := 1;
end if;
ASSERT CV1_con_2(I)(J) = bval
REPORT "ERROR: Bad initial value of CV1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (CC1_con_2(I)(J) /= bval) then
k := 1;
end if;
ASSERT CC1_con_2(I)(J) = bval
REPORT "ERROR: Bad initial value of CC1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
--
FOR J IN 1 TO 8 LOOP
if (RAR_con_2.eS1(J) /= CHARACTER'VAL((J-1)+64)) then
k := 1;
end if;
ASSERT RAR_con_2.eS1(J) = CHARACTER'VAL((J-1)+64)
REPORT "ERROR: Bad initial value of RAR_con_2.eS1" SEVERITY FAILURE;
END LOOP;
FOR J IN 3 DOWNTO 0 LOOP
if (RAR_con_2.eV1(J) /= BIT'VAL(J/2)) then
k := 1;
end if;
ASSERT RAR_con_2.eV1(J) = BIT'VAL(J/2)
REPORT "ERROR: Bad initial value of RAR_con_2.eV1" SEVERITY FAILURE;
END LOOP;
index := 0;
FOR J IN 'a' TO 'd' LOOP
index := index + 1;
if (RAR_con_2.eU1(J) /= index) then
k := 1;
end if;
ASSERT RAR_con_2.eU1(J) = index
REPORT "ERROR: Bad initial value of RAR_con_2.eU1" SEVERITY FAILURE;
END LOOP;
index := 59;
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (RAR_con_2.eC1(J) /= bval) then
k := 1;
end if;
ASSERT RAR_con_2.eC1(J) = bval
REPORT "ERROR: Bad initial value of RAR_con_2.eC1" SEVERITY FAILURE;
END LOOP;
if (RAR_con_2.eR1.month /= FEB) then
k := 1;
end if;
ASSERT RAR_con_2.eR1.month = FEB
REPORT "ERROR: Bad initial value of RAR_con_2.eR1.month" SEVERITY FAILURE;
if (RAR_con_2.eR1.day /=29) then
k := 1;
end if;
ASSERT RAR_con_2.eR1.day = 29
REPORT "ERROR: Bad initial value of RAR_con_2.eR1.day" SEVERITY FAILURE;
if (RAR_con_2.eR1.year /= 0108) then
k := 1;
end if;
ASSERT RAR_con_2.eR1.year = 0108
REPORT "ERROR: Bad initial value of RAR_con_1.eR1.year" SEVERITY
FAILURE;
---------------------------------------------------------------------------------------------
assert NOT( k = 0 )
report "***PASSED TEST: c04s03b01x01p01n01i00032"
severity NOTE;
assert ( k = 0 )
report "***FAILED TEST:c04s03b01x01p01n01i00032 - A constant declares a constant of the specified type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p01n01i00032arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc256.vhd | 4 | 1673 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc256.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00256ent IS
END c03s01b02x00p08n01i00256ent;
ARCHITECTURE c03s01b02x00p08n01i00256arch OF c03s01b02x00p08n01i00256ent IS
-- Failure_here: 1E10 is larger than integer range
type time is range 0 to 1E10
units
fs;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00256 - Integer declared outside bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00256arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/bit_set_mask.vhd | 2 | 2224 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity bit_set_mask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0)
);
end bit_set_mask;
architecture augh of bit_set_mask is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := (
"00000000000000000000000000000001", "00000000000000000000000000000010", "00000000000000000000000000000100",
"00000000000000000000000000001000", "00000000000000000000000000010000", "00000000000000000000000000100000",
"00000000000000000000000001000000", "00000000000000000000000010000000", "00000000000000000000000100000000",
"00000000000000000000001000000000", "00000000000000000000010000000000", "00000000000000000000100000000000",
"00000000000000000001000000000000", "00000000000000000010000000000000", "00000000000000000100000000000000",
"00000000000000001000000000000000", "00000000000000010000000000000000", "00000000000000100000000000000000",
"00000000000001000000000000000000", "00000000000010000000000000000000", "00000000000100000000000000000000",
"00000000001000000000000000000000", "00000000010000000000000000000000", "00000000100000000000000000000000",
"00000001000000000000000000000000", "00000010000000000000000000000000", "00000100000000000000000000000000",
"00001000000000000000000000000000", "00010000000000000000000000000000", "00100000000000000000000000000000",
"01000000000000000000000000000000", "10000000000000000000000000000000"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1383.vhd | 4 | 1712 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1383.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01383ent IS
END c08s05b00x00p03n01i01383ent;
ARCHITECTURE c08s05b00x00p03n01i01383arch OF c08s05b00x00p03n01i01383ent IS
BEGIN
TESTING: PROCESS
variable v1 : integer := 0;
BEGIN
ch0805_p00301_29_arch := v1; -- illegal name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01383 - Target of a variable assignment can not be the name of an architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01383arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket89/repro2.vhdl | 3 | 354 | entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (10 ns);
end process;
process
begin
s <= 3;
wait for 0 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wait;
end process;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2751.vhd | 4 | 1635 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2751.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p03n01i02751ent IS
END c13s07b00x00p03n01i02751ent;
ARCHITECTURE c13s07b00x00p03n01i02751arch OF c13s07b00x00p03n01i02751ent IS
BEGIN
TESTING: PROCESS
variable bit_str : bit_vector (1 to 8) := b"0101_0101_";
BEGIN
assert FALSE
report "***FAILED TEST: c13s07b00x00p03n01i02751 - Trailing underscores are not allowed in bit values."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p03n01i02751arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket30/lib_numeric_tb.vhd | 3 | 564 | use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_primitives.all;
use ieee.vital_timing.all;
entity numeric_tb is
generic (
tperiod_CLK_posedge : VitalDelayType := 0.000 ns);
port (
CLK : in std_ulogic);
attribute VITAL_LEVEL0 of numeric_tb : entity is true;
end numeric_tb;
architecture test of numeric_tb is
begin
process
variable l : line;
begin
write(l, string'("tperiod_CLK_posedge = "));
write(l, tperiod_CLK_posedge);
writeline(output, l);
wait;
end process;
end;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue43/test_tb.vhd | 2 | 1302 | library ieee;
use ieee.std_logic_1164.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.com_context;
entity test_tb is
generic (runner_cfg : runner_cfg_t);
end entity;
architecture beh of test_tb is
signal rx_data : std_logic_vector(159 downto 0);
function to_b(constant s : string) return std_logic is
begin
return '0';
end function;
function to_a(constant s : string) return std_logic is
variable a : std_logic := to_b(s);
begin
return '0';
end function;
procedure to_t( signal sa : out std_logic_vector(31 downto 0)) is
begin
sa <= (others => '1');
assert false report "lol";
end procedure;
begin
asd : for i in 0 to 4 generate
begin
process
constant s : string := "lane" & integer'image(i);
variable self : actor_t := create(s);
begin
--assert false report "Error: " & s;
rx_data(32*(i+1)-1 downto 32*i) <= (others => '0');
wait for 10 ns;
to_t(rx_data(32*(i+1)-1 downto 32*i));
wait;
end process;
end generate;
process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("test1") then
null;
end if;
end loop;
test_runner_cleanup(runner); -- Simulation ends here
end process;
end architecture; | gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1854.vhd | 4 | 1726 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1854.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01854ent IS
END c07s01b00x00p08n01i01854ent;
ARCHITECTURE c07s01b00x00p08n01i01854arch OF c07s01b00x00p08n01i01854ent IS
signal sma_int : integer;
BEGIN
b: block ( sma_int = b ) -- block label illegal here
begin
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01854 - Block labels are not permitted as primaries in a block guard expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01854arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3206.vhd | 4 | 2284 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library std;
use std.textio.all;
ENTITY c14s03b00x00p60n01i03206ent IS
END c14s03b00x00p60n01i03206ent;
ARCHITECTURE c14s03b00x00p60n01i03206arch OF c14s03b00x00p60n01i03206ent IS
BEGIN
TESTING: PROCESS
procedure write1 is
file F: TEXT open write_mode is "iofile.64";
variable L: LINE;
begin
write(L, Integer'(12));
writeline(F, L);
write(L, Integer'(34));
writeline(F, L);
write(L, Integer'(56));
writeline(F, L);
write(L, Integer'(78));
writeline(F, L);
write(L, Integer'(90));
writeline(F, L);
end write1;
procedure read1 is
file F: TEXT open read_mode is "iofile.64";
variable L: LINE;
variable i,v_integer : Integer;
begin
i := 0;
while not ENDFILE(F) loop
readline(F, L);
i := i + 1;
end loop;
Assert i /= 4
report "Line count to ENDFILE is incorrect"
severity ERROR;
assert NOT( i = 5 )
report "***PASSED TEST: c14s03b00x00p60n01i03206"
severity NOTE;
assert ( i = 5 )
report "***FAILED TEST: c14s03b00x00p60n01i03206 - Procedure ENDLINE test failed."
severity ERROR;
end read1;
BEGIN
write1;
wait for 10 ns;
read1;
wait;
END PROCESS TESTING;
END c14s03b00x00p60n01i03206arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2973.vhd | 4 | 2290 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2973.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p03n01i02973ent IS
END c02s03b01x00p03n01i02973ent;
ARCHITECTURE c02s03b01x00p03n01i02973arch OF c02s03b01x00p03n01i02973ent IS
type newt is (one,two,three,four);
function "+" (constant c1,c2 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of left binary + operator"
severity failure;
assert (c2=20)
report "Error in association of right binary + operator"
severity failure;
assert NOT( c1=10 and c2=20 )
report "***PASSED TEST: c02s03b01x00p03n01i02973"
severity NOTE;
assert ( c1=10 and c2=20 )
report "***FAILED TEST: c02s03b01x00p03n01i02973 - Error in + overloading as binary operator."
severity ERROR;
return three;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
n1 := two;
assert (n1=two)
report "Error in initial conditions detected"
severity failure;
n1:= 10 + 20;
assert (n1=three)
report "Error in call to overloaded binary + operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p03n01i02973arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc865.vhd | 4 | 9589 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc865.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00865pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal dumy : bit_vector(0 to 3);
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00865pkg;
use work.c01s03b01x00p12n01i00865pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00865pkg.all;
ENTITY c01s03b01x00p12n01i00865ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
END c01s03b01x00p12n01i00865ent;
ARCHITECTURE c01s03b01x00p12n01i00865arch OF c01s03b01x00p12n01i00865ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00865"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00865 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00865arch;
configuration c01s03b01x00p12n01i00865cfg of c01s03b01x00p12n01i00865ent is
for c01s03b01x00p12n01i00865arch
for K
for T5:test use configuration work.testbench;
end for;
for G(zero to one)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(three downto two)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue99/bug1.vhdl | 2 | 178 | package bug1 is
generic ( gen: natural );
constant test: natural:=gen;
end package;
package mygbug1 is new work.bug1 generic map ( gen => 17 );
package body bug1 is
end ;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/add_with_overflow.vhd | 4 | 1868 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity add_with_overflow is
end entity add_with_overflow;
architecture test of add_with_overflow is
begin
-- code from book
process is
procedure add_with_overflow ( a, b : in integer;
sum : out integer;
overflow : out boolean ) is -- . . .
-- not in book
begin
end;
-- end not in book
procedure add_with_overflow ( a, b : in bit_vector;
sum : out bit_vector;
overflow : out boolean ) is -- . . .
-- not in book
begin
end;
-- end not in book
attribute built_in : string;
attribute built_in of
add_with_overflow [ integer, integer,
integer, boolean ] : procedure is "int_add_overflow";
attribute built_in of
add_with_overflow [ bit_vector, bit_vector,
bit_vector, boolean ] : procedure is "bit_vector_add_overflow";
begin
-- . . .
-- not in book
wait;
-- end not in book
end process;
-- end code from book
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2258.vhd | 4 | 7173 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2258.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p05n01i02258ent IS
END c07s02b06x00p05n01i02258ent;
ARCHITECTURE c07s02b06x00p05n01i02258arch OF c07s02b06x00p05n01i02258ent IS
BEGIN
TESTING: PROCESS
constant mul11 : integer := (1 - 4) * (1 - 4);
constant mul12 : integer := (1 - 4) * (2 - 4);
constant mul13 : integer := (1 - 4) * (3 - 4);
constant mul14 : integer := (1 - 4) * (4 - 4);
constant mul15 : integer := (1 - 4) * (5 - 4);
constant mul16 : integer := (1 - 4) * (6 - 4);
constant mul17 : integer := (1 - 4) * (7 - 4);
constant mul18 : integer := (1 - 4) * (8 - 4);
constant mul19 : integer := (1 - 4) * (9 - 4);
constant mul41 : integer := (4 - 4) * (1 - 4);
constant mul42 : integer := (4 - 4) * (2 - 4);
constant mul43 : integer := (4 - 4) * (3 - 4);
constant mul44 : integer := (4 - 4) * (4 - 4);
constant mul45 : integer := (4 - 4) * (5 - 4);
constant mul46 : integer := (4 - 4) * (6 - 4);
constant mul47 : integer := (4 - 4) * (7 - 4);
constant mul48 : integer := (4 - 4) * (8 - 4);
constant mul49 : integer := (4 - 4) * (9 - 4);
constant mul61 : integer := (6 - 4) * (1 - 4);
constant mul62 : integer := (6 - 4) * (2 - 4);
constant mul63 : integer := (6 - 4) * (3 - 4);
constant mul64 : integer := (6 - 4) * (4 - 4);
constant mul65 : integer := (6 - 4) * (5 - 4);
constant mul66 : integer := (6 - 4) * (6 - 4);
constant mul67 : integer := (6 - 4) * (7 - 4);
constant mul68 : integer := (6 - 4) * (8 - 4);
constant mul69 : integer := (6 - 4) * (9 - 4);
variable four : integer := 4;
BEGIN
assert mul11 = (1 - four) * (1 - four);
assert mul12 = (1 - four) * (2 - four);
assert mul13 = (1 - four) * (3 - four);
assert mul14 = (1 - four) * (4 - four);
assert mul15 = (1 - four) * (5 - four);
assert mul16 = (1 - four) * (6 - four);
assert mul17 = (1 - four) * (7 - four);
assert mul18 = (1 - four) * (8 - four);
assert mul19 = (1 - four) * (9 - four);
assert mul41 = (4 - four) * (1 - four);
assert mul42 = (4 - four) * (2 - four);
assert mul43 = (4 - four) * (3 - four);
assert mul44 = (4 - four) * (4 - four);
assert mul45 = (4 - four) * (5 - four);
assert mul46 = (4 - four) * (6 - four);
assert mul47 = (4 - four) * (7 - four);
assert mul48 = (4 - four) * (8 - four);
assert mul49 = (4 - four) * (9 - four);
assert mul61 = (6 - four) * (1 - four);
assert mul62 = (6 - four) * (2 - four);
assert mul63 = (6 - four) * (3 - four);
assert mul64 = (6 - four) * (4 - four);
assert mul65 = (6 - four) * (5 - four);
assert mul66 = (6 - four) * (6 - four);
assert mul67 = (6 - four) * (7 - four);
assert mul68 = (6 - four) * (8 - four);
assert mul69 = (6 - four) * (9 - four);
assert NOT(( mul11 = (1 - four) * (1 - four)) and
( mul12 = (1 - four) * (2 - four)) and
( mul13 = (1 - four) * (3 - four)) and
( mul14 = (1 - four) * (4 - four)) and
( mul15 = (1 - four) * (5 - four)) and
( mul16 = (1 - four) * (6 - four)) and
( mul17 = (1 - four) * (7 - four)) and
( mul18 = (1 - four) * (8 - four)) and
( mul19 = (1 - four) * (9 - four)) and
( mul41 = (4 - four) * (1 - four)) and
( mul42 = (4 - four) * (2 - four)) and
( mul43 = (4 - four) * (3 - four)) and
( mul44 = (4 - four) * (4 - four)) and
( mul45 = (4 - four) * (5 - four)) and
( mul46 = (4 - four) * (6 - four)) and
( mul47 = (4 - four) * (7 - four)) and
( mul48 = (4 - four) * (8 - four)) and
( mul49 = (4 - four) * (9 - four)) and
( mul61 = (6 - four) * (1 - four)) and
( mul62 = (6 - four) * (2 - four)) and
( mul63 = (6 - four) * (3 - four)) and
( mul64 = (6 - four) * (4 - four)) and
( mul65 = (6 - four) * (5 - four)) and
( mul66 = (6 - four) * (6 - four)) and
( mul67 = (6 - four) * (7 - four)) and
( mul68 = (6 - four) * (8 - four)) and
( mul69 = (6 - four) * (9 - four)) )
report "***PASSED TEST: c07s02b06x00p05n01i02258"
severity NOTE;
assert (( mul11 = (1 - four) * (1 - four)) and
( mul12 = (1 - four) * (2 - four)) and
( mul13 = (1 - four) * (3 - four)) and
( mul14 = (1 - four) * (4 - four)) and
( mul15 = (1 - four) * (5 - four)) and
( mul16 = (1 - four) * (6 - four)) and
( mul17 = (1 - four) * (7 - four)) and
( mul18 = (1 - four) * (8 - four)) and
( mul19 = (1 - four) * (9 - four)) and
( mul41 = (4 - four) * (1 - four)) and
( mul42 = (4 - four) * (2 - four)) and
( mul43 = (4 - four) * (3 - four)) and
( mul44 = (4 - four) * (4 - four)) and
( mul45 = (4 - four) * (5 - four)) and
( mul46 = (4 - four) * (6 - four)) and
( mul47 = (4 - four) * (7 - four)) and
( mul48 = (4 - four) * (8 - four)) and
( mul49 = (4 - four) * (9 - four)) and
( mul61 = (6 - four) * (1 - four)) and
( mul62 = (6 - four) * (2 - four)) and
( mul63 = (6 - four) * (3 - four)) and
( mul64 = (6 - four) * (4 - four)) and
( mul65 = (6 - four) * (5 - four)) and
( mul66 = (6 - four) * (6 - four)) and
( mul67 = (6 - four) * (7 - four)) and
( mul68 = (6 - four) * (8 - four)) and
( mul69 = (6 - four) * (9 - four)) )
report "***FAILED TEST: c07s02b06x00p05n01i02258 - Constant integer type multiplication test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p05n01i02258arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug7751/7751_tests.vhd | 3 | 5259 | entity top is
end top;
architecture sim of top is
-------------- static value ----------------------
-- static value : enumeration
constant boolstr : string := "false";
constant off : boolean := boolean'value("FALSE");
-- static value : integer
constant numstr : string := "5";
-- static value : float
constant fpstr1 : string := "123.4567";
constant fpstr2 : string := "123.4567e-3";
constant fpstr3 : string := "-123.4567e4";
constant fp0 : real := real'value("123.4567");
constant fp1 : real := real'value(fpstr1);
constant fp2 : real := real'value(fpstr2);
constant fp3 : real := real'value(fpstr3);
-- static value : physical
constant t_val_static : time := time'value("123 ns");
-------------- static image ----------------------
-- static image : enumeration
constant bool_img1 : string := boolean'image(False);
constant bool_img2 : string := boolean'image(True);
-- static image : integer
constant int_img : string := integer'image(123);
-- static image : float
constant fpimg0 : string := real'image(fp0);
constant fpimg1 : string := real'image(fp1);
constant fpimg2 : string := real'image(fp2);
constant fpimg3 : string := real'image(fp3);
constant t_img_static : string := time'image(456 ps);
-- physical types always evaluated at runtime...
-------------- runtime value ----------------------
-- runtime integer
signal my_int : integer := 5;
signal my_str1 : string(1 to 1) := "5";
-- runtime boolean
signal my_bool : boolean := true;
-- runtime float
signal my_flt : real := 0.0;
-------------- runtime image ----------------------
-- runtime(signal) physical
signal t : time := time'value("789 US");
function t_img (t : time) return string is
begin
return time'image(t);
end t_img;
begin
-- Value tests : static enumeration expressions.
Assert boolean'value("FALSE") report "Bool Assertion triggered" severity NOTE;
Assert boolean'value(boolstr) report "Bool Assertion triggered" severity NOTE;
-- Value tests : static integer expressions.
Assert 2 + 2 = natural'value("5") report "Integer Assertion triggered" severity NOTE;
Assert 2 + 2 = natural'value(numstr) report "Integer Assertion triggered" severity NOTE;
-- Value tests : static real expressions.
Assert false report "real'value(""123.4567"" = " & real'image(fp0) severity NOTE;
-- Value tests : static physical expressions. Use time and at least one other phys unit.
Assert false report "123 ns is " & time'image(t_val_static) severity note;
-- To check compiler error diagnosis, uncomment these.
-- Assert boolean'value(79) report "Assertion triggered" severity NOTE;
-- Assert boolean'value(False) report "Assertion triggered" severity NOTE;
-- Assert boolean'value("SILLY") report "Assertion triggered" severity NOTE;
-- Image tests : static enumeration expressions.
Assert false report "Boolean can be " & boolean'image(True) & " or " & boolean'image(False) severity Note;
Assert false report "Static Boolean can be " & bool_img1 & " or " & bool_img2 severity Note;
-- Image tests : static integer expressions.
Assert false report "Integer image of 123 is " & int_img severity note;
-- Image tests : static real expressions.
Assert false report "123.4567" & " = " & fpimg0 severity note;
Assert false report "123.4567" & " = " & real'image(fp0) severity note;
Assert false report "124.4567" & " = " & real'image(fp0 + 1.0) severity note;
-- These assert despite nominally equal values.
Assert fp0 = real'value(fpimg0) report "123.4567" & " = " & fpimg0 severity note;
Assert fp1 = real'value(fpimg1) report fpstr1 & " = " & fpimg1 severity note;
Assert fp2 = real'value(fpimg2) report fpstr2 & " = " & fpimg2 severity note;
Assert fp3 = real'value(fpimg3) report fpstr3 & " = " & fpimg3 severity note;
-- So verify that the differences are not actually 0
Assert false report "fp0 - real'value(fpimg0) = " & real'image(fp0 - real'value(fpimg0)) severity note;
Assert false report "fp1 - real'value(fpimg1) = " & real'image(fp1 - real'value(fpimg1)) severity note;
Assert false report "fp2 - real'value(fpimg2) = " & real'image(fp2 - real'value(fpimg2)) severity note;
Assert false report "fp3 - real'value(fpimg3) = " & real'image(fp3 - real'value(fpimg3)) severity note;
-- Image tests : static physical expressions
Assert false report "456 ps is " & t_img_static severity note;
-- Value tests : runtime expressions
Assert boolean'value("FALSE") report "Assertion triggered" severity NOTE;
Assert boolean'value(boolstr) report "Assertion triggered" severity NOTE;
Assert my_bool report "Boolean my_bool = " & boolean'image(my_bool) severity NOTE;
my_str1(1) <= '6' after 1 ns, '4' after 2 ns;
my_flt <= fp0 after 3 ns;
my_bool <= False after 4 ns;
Assert my_flt = 0.0 report "my_flt = " & real'image(my_flt) severity note;
Assert 2 + 2 = natural'value(my_str1) report "RT Assertion 1 triggered" severity NOTE;
Assert 2 + 2 /= natural'value(my_str1) report "RT Assertion 2 triggered" severity NOTE;
Assert my_bool report "Boolean my_bool = " & boolean'image(my_bool) severity NOTE;
-- Image tests : runtime physical expressions.
Assert false report "Time " & t_img(123 us) severity note;
end sim;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2482.vhd | 4 | 1870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2482.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s03b03x00p01n01i02482pkg is
function uno return natural;
constant a_bit : bit_vector (uno to uno) := ( uno => '1' );
end c07s03b03x00p01n01i02482pkg;
package body c07s03b03x00p01n01i02482pkg is
function uno return natural is
begin
return 1;
end uno;
end c07s03b03x00p01n01i02482pkg;
ENTITY c07s03b03x00p01n01i02482ent IS
END c07s03b03x00p01n01i02482ent;
ARCHITECTURE c07s03b03x00p01n01i02482arch OF c07s03b03x00p01n01i02482ent IS
BEGIN
TESTING: PROCESS
BEGIN
uno;
assert FALSE
report "***FAILED TEST: c07s03b03x00p01n01i02482 - Function body is not defined."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p01n01i02482arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1534.vhd | 4 | 1877 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1534.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p09n02i01534ent IS
END c08s09b00x00p09n02i01534ent;
ARCHITECTURE c08s09b00x00p09n02i01534arch OF c08s09b00x00p09n02i01534ent IS
BEGIN
TESTING: PROCESS
variable i1, i2, i3 : integer := 1;
BEGIN
--
-- Initialize two integer variables so their division yeilds a real
--
i2 := 11;
i3 := 3;
--
-- Loop must have discrete parameters
--
L1: for c in real(i2) / i3 to i2 loop -- parameters must be discrete
null;
end loop L1;
assert FALSE
report "***FAILED TEST: c08s09b00x00p09n02i01534 - Loop parameters must be discrete."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p09n02i01534arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd | 4 | 1457 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity and2 is
port ( a, b : in std_ulogic; y : out std_ulogic );
end entity and2;
--------------------------------------------------
architecture detailed_delay of and2 is
signal result : std_ulogic;
begin
gate : process (a, b) is
begin
result <= a and b;
end process gate;
delay : process (result) is
begin
if result = '1' then
y <= reject 400 ps inertial '1' after 1.5 ns;
elsif result = '0' then
y <= reject 300 ps inertial '0' after 1.2 ns;
else
y <= reject 300 ps inertial 'X' after 500 ps;
end if;
end process delay;
end architecture detailed_delay;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc929.vhd | 4 | 1802 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc929.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s04b00x00p01n01i00929pkg is
type p2 is (a, b);
end c10s04b00x00p01n01i00929pkg;
use work.all;
ENTITY c10s04b00x00p01n01i00929ent IS
END c10s04b00x00p01n01i00929ent;
ARCHITECTURE c10s04b00x00p01n01i00929arch OF c10s04b00x00p01n01i00929ent IS
signal s: p2; -- Failure_here
-- should report an error as the type p2 is not visible.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c10s04b00x00p01n01i00929 - Type definition does not exist in scope of declaration region for architecture."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s04b00x00p01n01i00929arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_05.vhd | 4 | 2065 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
begin
process is
-- code from book:
type coordinate is array (1 to 3) of real;
type coordinate_ptr is access coordinate;
variable origin : coordinate_ptr := new coordinate'(0.0, 0.0, 0.0);
type time_array is array (positive range <>) of time;
variable activation_times : time_array(1 to 100);
-- end of code from book
begin
report real'image( origin(1) );
report real'image( origin(2) );
report real'image( origin(3) );
report real'image( origin.all(1) );
wait;
end process;
process is
type time_array is array (positive range <>) of time;
-- code from book:
type time_array_ptr is access time_array;
variable activation_times : time_array_ptr;
-- end of code from book
begin
-- code from book:
activation_times := new time_array'(10 us, 15 us, 40 us);
activation_times := new time_array'( activation_times.all
& time_array'(70 us, 100 us) );
activation_times := new time_array(1 to 10);
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc520.vhd | 4 | 60047 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc520.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c03s03b00x00p03n04i00520pkg IS
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Scalar type for subelements
--
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
SUBTYPE st_scl4 IS REAL RANGE 0.0 TO 1024.0;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Records of scalars
--
TYPE t_scre_1 IS RECORD
left : st_scl1;
second : TIME;
third : st_scl3;
right : st_scl4;
END RECORD;
--
-- Unconstrained arrays of scalars
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
--
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 , -- ( i2, i1 ) of CHAR
st_ind1 );
SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 , -- ( i3, i2, i1) of CHAR
st_ind2 ,
st_ind1 );
SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 , -- ( i4, i3, i2, i1 ) of CHAR
st_ind3 ,
st_ind2 ,
st_ind1 );
--
--
-- constrained arrays of composites
--
TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1; -- ( i1 ) is RECORD of scalar
TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1; -- ( i2 )( i1 ) is CHAR
TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2; -- ( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3; -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1; -- ( i3 )( i2, i1 ) is CHAR
TYPE t_cca2_2 IS ARRAY (st_ind4, -- ( i4, i3 )( i2, i1 ) of CHAR
st_ind3) OF t_csa2_1;
TYPE t_cca3_1 IS ARRAY (st_ind4, -- ( i4, i3, i2 )( i1 ) of CHAR
st_ind3,
st_ind2) OF t_csa1_1;
TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1; -- ( i4 )( i3, i2, i1 ) is CHAR
--
-- Records of composites
--
TYPE t_cmre_1 IS RECORD
left : t_csa1_1; -- .fN(i1) is CHAR
second : t_scre_1; -- .fN.fN
END RECORD;
TYPE t_cmre_2 IS RECORD
left ,
second ,
third ,
right : t_csa1_1; -- .fN(i1) is CHAR
END RECORD;
--
-- Mixed Records/arrays
--
TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2; -- (i3).fN(i1) is CHAR
TYPE t_cmre_3 IS RECORD
left ,
second ,
third ,
right : t_cca1_7; -- .fN(i3).fN(i1) is CHAR
END RECORD;
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
--
-- Declaration of Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
--
-- Resolved SUBTYPE declaration
--
SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
--
-- Functions declarations for multi-dimensional comosite values
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
-- -------------------------------------------------------------------------------------------
-- Data values for Composite Types
-- -------------------------------------------------------------------------------------------
CONSTANT CX_scl1 : st_scl1 := 'X' ;
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C1_scl1 : st_scl1 := 'A' ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT CX_scl2 : TIME := 99 fs ;
CONSTANT C0_scl2 : TIME := TIME'LEFT ;
CONSTANT C1_scl2 : TIME := 0 fs;
CONSTANT C2_scl2 : TIME := 2 ns;
CONSTANT CX_scl3 : st_scl3 := 15 ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C1_scl3 : st_scl3 := 6 ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT CX_scl4 : st_scl4 := 99.9 ;
CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
CONSTANT C1_scl4 : st_scl4 := 1.0 ;
CONSTANT C2_scl4 : st_scl4 := 2.1 ;
CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
OTHERS =>C0_scl2);
CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
OTHERS =>C0_scl4);
--
CONSTANT CX_csa2_1 : t_csa2_1 ;
CONSTANT C0_csa2_1 : t_csa2_1 ;
CONSTANT C1_csa2_1 : t_csa2_1 ;
CONSTANT C2_csa2_1 : t_csa2_1 ;
CONSTANT CX_csa3_1 : t_csa3_1 ;
CONSTANT C0_csa3_1 : t_csa3_1 ;
CONSTANT C1_csa3_1 : t_csa3_1 ;
CONSTANT C2_csa3_1 : t_csa3_1 ;
CONSTANT CX_csa4_1 : t_csa4_1 ;
CONSTANT C0_csa4_1 : t_csa4_1 ;
CONSTANT C1_csa4_1 : t_csa4_1 ;
CONSTANT C2_csa4_1 : t_csa4_1 ;
--
CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 );
CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 );
CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 );
CONSTANT CX_cca2_1 : t_cca2_1 ;
CONSTANT C0_cca2_1 : t_cca2_1 ;
CONSTANT C1_cca2_1 : t_cca2_1 ;
CONSTANT C2_cca2_1 : t_cca2_1 ;
--
CONSTANT CX_cca2_2 : t_cca2_2 ;
CONSTANT C0_cca2_2 : t_cca2_2 ;
CONSTANT C1_cca2_2 : t_cca2_2 ;
CONSTANT C2_cca2_2 : t_cca2_2 ;
CONSTANT CX_cca3_1 : t_cca3_1 ;
CONSTANT C0_cca3_1 : t_cca3_1 ;
CONSTANT C1_cca3_1 : t_cca3_1 ;
CONSTANT C2_cca3_1 : t_cca3_1 ;
--
CONSTANT CX_cca3_2 : t_cca3_2 ;
CONSTANT C0_cca3_2 : t_cca3_2 ;
CONSTANT C1_cca3_2 : t_cca3_2 ;
CONSTANT C2_cca3_2 : t_cca3_2 ;
CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 );
CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
-- --------------------------------------------------------------------------------------------
-- Functions for mapping from integer test values to/from values of the Test types
-- --------------------------------------------------------------------------------------------
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
FUNCTION val_t ( i : INTEGER ) RETURN TIME;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER;
FUNCTION val_i ( i : TIME ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING;
FUNCTION val_s ( i : TIME ) RETURN STRING;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
END;
PACKAGE BODY c03s03b00x00p03n04i00520pkg IS
CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 );
--
-- Functions to provide values for multi-dimensional composites
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
VARIABLE res : t_csa2_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
VARIABLE res : t_csa3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
VARIABLE res : t_csa4_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
FOR l IN res'RANGE(4) LOOP
res(i,j,k,l) := v0;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
RETURN res;
END;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
VARIABLE res : t_cca2_2;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
VARIABLE res : t_cca3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
--
-- Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_scre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa4_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_7;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_3;
ELSE RETURN v(1);
END IF;
END;
--
--
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
BEGIN
IF i = 0 THEN RETURN C0_scl1; END IF;
IF i = 1 THEN RETURN C1_scl1; END IF;
IF i = 2 THEN RETURN C2_scl1; END IF;
RETURN CX_scl1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
BEGIN
IF i = 0 THEN RETURN C0_scl2; END IF;
IF i = 1 THEN RETURN C1_scl2; END IF;
IF i = 2 THEN RETURN C2_scl2; END IF;
RETURN CX_scl2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
BEGIN
IF i = 0 THEN RETURN C0_scl3; END IF;
IF i = 1 THEN RETURN C1_scl3; END IF;
IF i = 2 THEN RETURN C2_scl3; END IF;
RETURN CX_scl3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
BEGIN
IF i = 0 THEN RETURN C0_scl4; END IF;
IF i = 1 THEN RETURN C1_scl4; END IF;
IF i = 2 THEN RETURN C2_scl4; END IF;
RETURN CX_scl4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_scre_1; END IF;
IF i = 1 THEN RETURN C1_scre_1; END IF;
IF i = 2 THEN RETURN C2_scre_1; END IF;
RETURN CX_scre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_1; END IF;
IF i = 1 THEN RETURN C1_csa1_1; END IF;
IF i = 2 THEN RETURN C2_csa1_1; END IF;
RETURN CX_csa1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_2; END IF;
IF i = 1 THEN RETURN C1_csa1_2; END IF;
IF i = 2 THEN RETURN C2_csa1_2; END IF;
RETURN CX_csa1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_3; END IF;
IF i = 1 THEN RETURN C1_csa1_3; END IF;
IF i = 2 THEN RETURN C2_csa1_3; END IF;
RETURN CX_csa1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_4; END IF;
IF i = 1 THEN RETURN C1_csa1_4; END IF;
IF i = 2 THEN RETURN C2_csa1_4; END IF;
RETURN CX_csa1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa2_1; END IF;
IF i = 1 THEN RETURN C1_csa2_1; END IF;
IF i = 2 THEN RETURN C2_csa2_1; END IF;
RETURN CX_csa2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa3_1; END IF;
IF i = 1 THEN RETURN C1_csa3_1; END IF;
IF i = 2 THEN RETURN C2_csa3_1; END IF;
RETURN CX_csa3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa4_1; END IF;
IF i = 1 THEN RETURN C1_csa4_1; END IF;
IF i = 2 THEN RETURN C2_csa4_1; END IF;
RETURN CX_csa4_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_1; END IF;
IF i = 1 THEN RETURN C1_cca1_1; END IF;
IF i = 2 THEN RETURN C2_cca1_1; END IF;
RETURN CX_cca1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_2; END IF;
IF i = 1 THEN RETURN C1_cca1_2; END IF;
IF i = 2 THEN RETURN C2_cca1_2; END IF;
RETURN CX_cca1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_3; END IF;
IF i = 1 THEN RETURN C1_cca1_3; END IF;
IF i = 2 THEN RETURN C2_cca1_3; END IF;
RETURN CX_cca1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_4; END IF;
IF i = 1 THEN RETURN C1_cca1_4; END IF;
IF i = 2 THEN RETURN C2_cca1_4; END IF;
RETURN CX_cca1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_1; END IF;
IF i = 1 THEN RETURN C1_cca2_1; END IF;
IF i = 2 THEN RETURN C2_cca2_1; END IF;
RETURN CX_cca2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_2; END IF;
IF i = 1 THEN RETURN C1_cca2_2; END IF;
IF i = 2 THEN RETURN C2_cca2_2; END IF;
RETURN CX_cca2_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_1; END IF;
IF i = 1 THEN RETURN C1_cca3_1; END IF;
IF i = 2 THEN RETURN C2_cca3_1; END IF;
RETURN CX_cca3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_2; END IF;
IF i = 1 THEN RETURN C1_cca3_2; END IF;
IF i = 2 THEN RETURN C2_cca3_2; END IF;
RETURN CX_cca3_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_1; END IF;
IF i = 1 THEN RETURN C1_cmre_1; END IF;
IF i = 2 THEN RETURN C2_cmre_1; END IF;
RETURN CX_cmre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_2; END IF;
IF i = 1 THEN RETURN C1_cmre_2; END IF;
IF i = 2 THEN RETURN C2_cmre_2; END IF;
RETURN CX_cmre_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_7; END IF;
IF i = 1 THEN RETURN C1_cca1_7; END IF;
IF i = 2 THEN RETURN C2_cca1_7; END IF;
RETURN CX_cca1_7;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_3; END IF;
IF i = 1 THEN RETURN C1_cmre_3; END IF;
IF i = 2 THEN RETURN C2_cmre_3; END IF;
RETURN CX_cmre_3;
END;
--
--
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl1 THEN RETURN 0; END IF;
IF i = C1_scl1 THEN RETURN 1; END IF;
IF i = C2_scl1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
BEGIN
IF i = C0_scl2 THEN RETURN 0; END IF;
IF i = C1_scl2 THEN RETURN 1; END IF;
IF i = C2_scl2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl3 THEN RETURN 0; END IF;
IF i = C1_scl3 THEN RETURN 1; END IF;
IF i = C2_scl3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl4 THEN RETURN 0; END IF;
IF i = C1_scl4 THEN RETURN 1; END IF;
IF i = C2_scl4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scre_1 THEN RETURN 0; END IF;
IF i = C1_scre_1 THEN RETURN 1; END IF;
IF i = C2_scre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_1 THEN RETURN 0; END IF;
IF i = C1_csa1_1 THEN RETURN 1; END IF;
IF i = C2_csa1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_2 THEN RETURN 0; END IF;
IF i = C1_csa1_2 THEN RETURN 1; END IF;
IF i = C2_csa1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_3 THEN RETURN 0; END IF;
IF i = C1_csa1_3 THEN RETURN 1; END IF;
IF i = C2_csa1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_4 THEN RETURN 0; END IF;
IF i = C1_csa1_4 THEN RETURN 1; END IF;
IF i = C2_csa1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa2_1 THEN RETURN 0; END IF;
IF i = C1_csa2_1 THEN RETURN 1; END IF;
IF i = C2_csa2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa3_1 THEN RETURN 0; END IF;
IF i = C1_csa3_1 THEN RETURN 1; END IF;
IF i = C2_csa3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa4_1 THEN RETURN 0; END IF;
IF i = C1_csa4_1 THEN RETURN 1; END IF;
IF i = C2_csa4_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_1 THEN RETURN 0; END IF;
IF i = C1_cca1_1 THEN RETURN 1; END IF;
IF i = C2_cca1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_2 THEN RETURN 0; END IF;
IF i = C1_cca1_2 THEN RETURN 1; END IF;
IF i = C2_cca1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_3 THEN RETURN 0; END IF;
IF i = C1_cca1_3 THEN RETURN 1; END IF;
IF i = C2_cca1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_4 THEN RETURN 0; END IF;
IF i = C1_cca1_4 THEN RETURN 1; END IF;
IF i = C2_cca1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_1 THEN RETURN 0; END IF;
IF i = C1_cca2_1 THEN RETURN 1; END IF;
IF i = C2_cca2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_2 THEN RETURN 0; END IF;
IF i = C1_cca2_2 THEN RETURN 1; END IF;
IF i = C2_cca2_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_1 THEN RETURN 0; END IF;
IF i = C1_cca3_1 THEN RETURN 1; END IF;
IF i = C2_cca3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_2 THEN RETURN 0; END IF;
IF i = C1_cca3_2 THEN RETURN 1; END IF;
IF i = C2_cca3_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_1 THEN RETURN 0; END IF;
IF i = C1_cmre_1 THEN RETURN 1; END IF;
IF i = C2_cmre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_2 THEN RETURN 0; END IF;
IF i = C1_cmre_2 THEN RETURN 1; END IF;
IF i = C2_cmre_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_7 THEN RETURN 0; END IF;
IF i = C1_cca1_7 THEN RETURN 1; END IF;
IF i = C2_cca1_7 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_3 THEN RETURN 0; END IF;
IF i = C1_cmre_3 THEN RETURN 1; END IF;
IF i = C2_cmre_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
BEGIN
IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : TIME ) RETURN STRING IS
BEGIN
IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
BEGIN
IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
BEGIN
IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
BEGIN
IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
RETURN "UNKNOWN";
END;
END c03s03b00x00p03n04i00520pkg;
USE work.c03s03b00x00p03n04i00520pkg.ALL;ENTITY c03s03b00x00p03n04i00520ent IS
END c03s03b00x00p03n04i00520ent;
ARCHITECTURE c03s03b00x00p03n04i00520arch OF c03s03b00x00p03n04i00520ent IS
--
-- Access type declarations
--
TYPE at_usa1_1 IS ACCESS t_usa1_1 ;
TYPE at_usa1_2 IS ACCESS t_usa1_2 ;
TYPE at_usa1_3 IS ACCESS t_usa1_3 ;
TYPE at_usa1_4 IS ACCESS t_usa1_4 ;
TYPE at_csa1_1 IS ACCESS t_csa1_1 ;
TYPE at_csa1_2 IS ACCESS t_csa1_2 ;
TYPE at_csa1_3 IS ACCESS t_csa1_3 ;
TYPE at_csa1_4 IS ACCESS t_csa1_4 ;
--
--
BEGIN
TESTING: PROCESS
--
-- ACCESS VARIABLE declarations
--
VARIABLE AV0_usa1_1 : at_usa1_1 ;
VARIABLE AV2_usa1_1 : at_usa1_1 ;
VARIABLE AV0_usa1_2 : at_usa1_2 ;
VARIABLE AV2_usa1_2 : at_usa1_2 ;
VARIABLE AV0_usa1_3 : at_usa1_3 ;
VARIABLE AV2_usa1_3 : at_usa1_3 ;
VARIABLE AV0_usa1_4 : at_usa1_4 ;
VARIABLE AV2_usa1_4 : at_usa1_4 ;
VARIABLE AV0_csa1_1 : at_csa1_1 ;
VARIABLE AV2_csa1_1 : at_csa1_1 ;
VARIABLE AV0_csa1_2 : at_csa1_2 ;
VARIABLE AV2_csa1_2 : at_csa1_2 ;
VARIABLE AV0_csa1_3 : at_csa1_3 ;
VARIABLE AV2_csa1_3 : at_csa1_3 ;
VARIABLE AV0_csa1_4 : at_csa1_4 ;
VARIABLE AV2_csa1_4 : at_csa1_4 ;
--
--
BEGIN
--
-- Allocation of access values
--
AV0_usa1_1 := NEW t_usa1_1 (st_ind1 ) ;
AV0_usa1_2 := NEW t_usa1_2 (st_ind2 ) ;
AV0_usa1_3 := NEW t_usa1_3 (st_ind3 ) ;
AV0_usa1_4 := NEW t_usa1_4 (st_ind4 ) ;
AV0_csa1_1 := NEW t_csa1_1 ;
AV0_csa1_2 := NEW t_csa1_2 ;
AV0_csa1_3 := NEW t_csa1_3 ;
AV0_csa1_4 := NEW t_csa1_4 ;
---
AV2_usa1_1 := NEW t_usa1_1 ' ( C2_csa1_1 ) ;
AV2_usa1_2 := NEW t_usa1_2 ' ( C2_csa1_2 ) ;
AV2_usa1_3 := NEW t_usa1_3 ' ( C2_csa1_3 ) ;
AV2_usa1_4 := NEW t_usa1_4 ' ( C2_csa1_4 ) ;
AV2_csa1_1 := NEW t_csa1_1 ' ( C2_csa1_1 ) ;
AV2_csa1_2 := NEW t_csa1_2 ' ( C2_csa1_2 ) ;
AV2_csa1_3 := NEW t_csa1_3 ' ( C2_csa1_3 ) ;
AV2_csa1_4 := NEW t_csa1_4 ' ( C2_csa1_4 ) ;
--
--
ASSERT AV0_usa1_1.all = C0_csa1_1
REPORT "Improper initialization of AV0_usa1_1" SEVERITY FAILURE;
ASSERT AV2_usa1_1.all = C2_csa1_1
REPORT "Improper initialization of AV2_usa1_1" SEVERITY FAILURE;
ASSERT AV0_usa1_2.all = C0_csa1_2
REPORT "Improper initialization of AV0_usa1_2" SEVERITY FAILURE;
ASSERT AV2_usa1_2.all = C2_csa1_2
REPORT "Improper initialization of AV2_usa1_2" SEVERITY FAILURE;
ASSERT AV0_usa1_3.all = C0_csa1_3
REPORT "Improper initialization of AV0_usa1_3" SEVERITY FAILURE;
ASSERT AV2_usa1_3.all = C2_csa1_3
REPORT "Improper initialization of AV2_usa1_3" SEVERITY FAILURE;
ASSERT AV0_usa1_4.all = C0_csa1_4
REPORT "Improper initialization of AV0_usa1_4" SEVERITY FAILURE;
ASSERT AV2_usa1_4.all = C2_csa1_4
REPORT "Improper initialization of AV2_usa1_4" SEVERITY FAILURE;
ASSERT AV0_csa1_1.all = C0_csa1_1
REPORT "Improper initialization of AV0_csa1_1" SEVERITY FAILURE;
ASSERT AV2_csa1_1.all = C2_csa1_1
REPORT "Improper initialization of AV2_csa1_1" SEVERITY FAILURE;
ASSERT AV0_csa1_2.all = C0_csa1_2
REPORT "Improper initialization of AV0_csa1_2" SEVERITY FAILURE;
ASSERT AV2_csa1_2.all = C2_csa1_2
REPORT "Improper initialization of AV2_csa1_2" SEVERITY FAILURE;
ASSERT AV0_csa1_3.all = C0_csa1_3
REPORT "Improper initialization of AV0_csa1_3" SEVERITY FAILURE;
ASSERT AV2_csa1_3.all = C2_csa1_3
REPORT "Improper initialization of AV2_csa1_3" SEVERITY FAILURE;
ASSERT AV0_csa1_4.all = C0_csa1_4
REPORT "Improper initialization of AV0_csa1_4" SEVERITY FAILURE;
ASSERT AV2_csa1_4.all = C2_csa1_4
REPORT "Improper initialization of AV2_csa1_4" SEVERITY FAILURE;
--
--
assert NOT( ( AV0_usa1_1.all = C0_csa1_1 )
and ( AV2_usa1_1.all = C2_csa1_1 )
and ( AV0_usa1_2.all = C0_csa1_2 )
and ( AV2_usa1_2.all = C2_csa1_2 )
and ( AV0_usa1_3.all = C0_csa1_3 )
and ( AV2_usa1_3.all = C2_csa1_3 )
and ( AV0_usa1_4.all = C0_csa1_4 )
and ( AV2_usa1_4.all = C2_csa1_4 )
and ( AV0_csa1_1.all = C0_csa1_1 )
and ( AV2_csa1_1.all = C2_csa1_1 )
and ( AV0_csa1_2.all = C0_csa1_2 )
and ( AV2_csa1_2.all = C2_csa1_2 )
and ( AV0_csa1_3.all = C0_csa1_3 )
and ( AV2_csa1_3.all = C2_csa1_3 )
and ( AV0_csa1_4.all = C0_csa1_4 )
and ( AV2_csa1_4.all = C2_csa1_4 ))
report "***PASSED TEST: c03s03b00x00p03n04i00520"
severity NOTE;
assert ( ( AV0_usa1_1.all = C0_csa1_1 )
and ( AV2_usa1_1.all = C2_csa1_1 )
and ( AV0_usa1_2.all = C0_csa1_2 )
and ( AV2_usa1_2.all = C2_csa1_2 )
and ( AV0_usa1_3.all = C0_csa1_3 )
and ( AV2_usa1_3.all = C2_csa1_3 )
and ( AV0_usa1_4.all = C0_csa1_4 )
and ( AV2_usa1_4.all = C2_csa1_4 )
and ( AV0_csa1_1.all = C0_csa1_1 )
and ( AV2_csa1_1.all = C2_csa1_1 )
and ( AV0_csa1_2.all = C0_csa1_2 )
and ( AV2_csa1_2.all = C2_csa1_2 )
and ( AV0_csa1_3.all = C0_csa1_3 )
and ( AV2_csa1_3.all = C2_csa1_3 )
and ( AV0_csa1_4.all = C0_csa1_4 )
and ( AV2_csa1_4.all = C2_csa1_4 ))
report "***FAILED TEST: c03s03b00x00p03n04i00520 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00520arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/sub_262.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_262 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_262;
architecture augh of sub_262 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/mul_565.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_565 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_565;
architecture augh of mul_565 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd | 4 | 2927 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
package stimulus_generators is
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length );
procedure all_possible_values ( signal bv : out std_ulogic_vector;
delay_between_values : in delay_length );
procedure all_possible_values ( signal bv : out std_logic_vector;
delay_between_values : in delay_length );
end package stimulus_generators;
package body stimulus_generators is
type digit_table is array ( natural range 0 to 1 ) of bit;
constant digit : digit_table := ( '0', '1' );
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(0 to length - 1);
begin
for index in result'reverse_range loop
result(index) := digit( temp rem 2 );
temp := temp / 2;
end loop;
return result;
end function natural_to_bv;
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length ) is
begin
bv <= natural_to_bv(0, bv'length);
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= natural_to_bv(value, bv'length);
end loop;
end procedure all_possible_values;
procedure all_possible_values ( signal bv : out std_ulogic_vector;
delay_between_values : in delay_length ) is
begin
bv <= To_StdULogicVector(natural_to_bv(0, bv'length));
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= To_StdULogicVector(natural_to_bv(value, bv'length));
end loop;
end procedure all_possible_values;
procedure all_possible_values ( signal bv : out std_logic_vector;
delay_between_values : in delay_length ) is
begin
bv <= To_StdLogicVector(natural_to_bv(0, bv'length));
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= To_StdLogicVector(natural_to_bv(value, bv'length));
end loop;
end procedure all_possible_values;
end package body stimulus_generators;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2861.vhd | 4 | 1794 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2861.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p03n01i02861ent IS
END c13s10b00x00p03n01i02861ent;
ARCHITECTURE c13s10b00x00p03n01i02861arch OF c13s10b00x00p03n01i02861ent IS
BEGIN
TESTING: PROCESS
variable total_time : real;
BEGIN
total_time := 5:1234.4321:E-10; -- no_failure_here
assert NOT(total_time = 5:1234.4321:E-10)
report "***PASSED TEST: c13s10b00x00p03n01i02861"
severity NOTE;
assert (total_time = 5:1234.4321:E-10)
report "***FAILED TEST: c13s10b00x00p03n01i02861 - Sharp character test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p03n01i02861arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1321.vhd | 4 | 2151 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1321.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p09n03i01321ent IS
END c08s04b00x00p09n03i01321ent;
ARCHITECTURE c08s04b00x00p09n03i01321arch OF c08s04b00x00p09n03i01321ent IS
signal S1 : BIT := '1';
signal S2 : BIT := '1';
signal S : BIT := '1';
BEGIN
S1 <= transport '0' after 5 ns,
'1' after 10 ns;
S2 <= transport S1 after 15 ns;
TEST : PROCESS(S2)
variable k : integer := 0;
BEGIN
if ((S2 = '0') and (NOW = 20 ns)) then
k := 1;
end if;
if ((S2 = '1') and (NOW = 25 ns) and (k = 1)) then
S <= '0' after 10 ns;
end if;
END PROCESS TEST;
TESTING: PROCESS(S)
BEGIN
if (NOW > 1 ns) then
assert NOT(S = '0')
report "***PASSED TEST: c08s04b00x00p09n03i01321"
severity NOTE;
assert (S = '0')
report "***FAILED TEST: c08s04b00x00p09n03i01321 - Any pulse is transmitted, not matter how short its durtion"
severity ERROR;
end if;
END PROCESS TESTING;
END c08s04b00x00p09n03i01321arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/sub_544.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_544 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_544;
architecture augh of sub_544 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc446.vhd | 4 | 3197 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc446.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00446ent IS
END c03s02b01x01p19n01i00446ent;
ARCHITECTURE c03s02b01x01p19n01i00446arch OF c03s02b01x01p19n01i00446ent IS
type time_vector is array (natural range <>) of time;
subtype time_vector_st is time_vector(0 to 15);
constant C1 : time := 4 ns;
constant C70 : time_vector_st :=(others => C1);
function complex_scalar(s : time_vector_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return time_vector_st is
begin
return C70;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : time_vector_st;
signal S2 : time_vector_st;
signal S3 : time_vector_st := C70;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C70) and (S2 = C70))
report "***PASSED TEST: c03s02b01x01p19n01i00446"
severity NOTE;
assert ((S1 = C70) and (S2 = C70))
report "***FAILED TEST: c03s02b01x01p19n01i00446 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00446arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2628.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2628.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02628ent IS
END c13s03b01x00p02n01i02628ent;
ARCHITECTURE c13s03b01x00p02n01i02628arch OF c13s03b01x00p02n01i02628ent IS
BEGIN
TESTING: PROCESS
variable k;k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02628 - Identifier can not contain ';'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02628arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2167.vhd | 4 | 2116 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2167.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02167ent IS
END c07s02b04x00p22n01i02167ent;
ARCHITECTURE c07s02b04x00p22n01i02167arch OF c07s02b04x00p22n01i02167ent IS
TYPE character_v is array (integer range <>) of character;
SUBTYPE character_2 is character_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : character_2;
variable l_operand : character := 'A';
variable r_operand : character := 'z';
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = ('A', 'z')) and (result(1)='A'))
report "***PASSED TEST: c07s02b04x00p22n01i02167"
severity NOTE;
assert ((result = ('A', 'z')) and (result(1)='A'))
report "***FAILED TEST: c07s02b04x00p22n01i02167 - Concatenation of CHARACTER element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02167arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu.vhd | 4 | 1485 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity cpu is
end entity cpu;
-- end not in book
architecture behavioral of cpu is
begin
interpreter : process is
variable instr_reg : work.cpu_types.word;
variable instr_opcode : work.cpu_types.opcode;
begin
-- . . . -- initialize
loop
-- . . . -- fetch instruction
instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
case instr_opcode is
when work.cpu_types.op_nop => null;
when work.cpu_types.op_breq => -- . . .
-- . . .
-- not in book
when others => null;
-- end not in book
end case;
end loop;
end process interpreter;
end architecture behavioral;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1053.vhd | 4 | 1878 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1053.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01053ent IS
END c06s04b00x00p03n02i01053ent;
ARCHITECTURE c06s04b00x00p03n02i01053arch OF c06s04b00x00p03n02i01053ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A11 is array (THREE) of BOOLEAN;
variable V1: BOOLEAN;
variable V11: A11 ;
BEGIN
V1 := V11(1, 2); -- ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01053 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01053arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug037/sim_types.vhdl | 2 | 4991 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
-- use PoC.utils.all;
-- use PoC.strings.all;
use PoC.vectors.all;
-- use PoC.physical.all;
package sim_types is
-- Simulation Task and Status Management
-- ===========================================================================
subtype T_SIM_PROCESS_ID is NATURAL range 0 to 1023;
subtype T_SIM_PROCESS_NAME is STRING(1 to 64);
subtype T_SIM_PROCESS_INSTNAME is STRING(1 to 256);
type T_SIM_PROCESS_STATUS is (
SIM_PROCESS_STATUS_ACTIVE,
SIM_PROCESS_STATUS_ENDED
);
type T_SIM_PROCESS is record
ID : T_SIM_PROCESS_ID;
Name : T_SIM_PROCESS_NAME;
InstanceName : T_SIM_PROCESS_INSTNAME;
Status : T_SIM_PROCESS_STATUS;
end record;
type T_SIM_PROCESS_VECTOR is array(NATURAL range <>) of T_SIM_PROCESS;
subtype T_SIM_TEST_ID is NATURAL range 0 to 1023;
subtype T_SIM_TEST_NAME is STRING(1 to 256);
type T_SIM_TEST_STATUS is (
SIM_TEST_STATUS_ACTIVE,
SIM_TEST_STATUS_ENDED
);
type T_SIM_TEST is record
ID : T_SIM_TEST_ID;
Name : T_SIM_TEST_NAME;
Status : T_SIM_TEST_STATUS;
end record;
type T_SIM_TEST_VECTOR is array(NATURAL range <>) of T_SIM_TEST;
-- clock generation
-- ===========================================================================
-- type T_PERCENT is INTEGER'range units
type T_PERCENT is range INTEGER'low to INTEGER'high units
ppb;
ppm = 1000 ppb;
permil = 1000 ppm;
percent = 10 permil;
one = 100 percent;
end units;
subtype T_WANDER is T_PERCENT range -1 one to 1 one;
subtype T_DUTYCYCLE is T_PERCENT range 0 ppb to 1 one;
type T_DEGREE is range INTEGER'low to INTEGER'high units
second;
minute = 60 second;
deg = 60 minute;
end units;
subtype T_PHASE is T_DEGREE range -360 deg to 360 deg;
function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE;
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
end package;
package body sim_types is
function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
end package body;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_25.vhd | 4 | 2096 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity nand3 is
generic ( Tpd : delay_length );
port ( a, b, c : in bit; y : out bit );
end entity nand3;
architecture basic of nand3 is
begin
y <= not (a and b and c) after Tpd;
end architecture basic;
library project_lib;
library stimulus;
use stimulus.stimulus_generators.all;
entity misc_logic is
end entity misc_logic;
-- code from book
architecture gate_level of misc_logic is
component nand3 is
generic ( Tpd : delay_length );
port ( a, b, c : in bit; y : out bit );
end component nand3;
for all : nand3
use entity project_lib.nand3(basic);
-- . . .
-- not in book
signal sig1, sig2, sig3, out_sig : bit;
signal test_vector : bit_vector(1 to 3);
-- end not in book
begin
gate1 : component nand3
generic map ( Tpd => 2 ns )
port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
-- . . .
-- not in book
all_possible_values(test_vector, 10 ns);
(sig1, sig2, sig3) <= test_vector;
-- end not in book
end architecture gate_level;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc692.vhd | 4 | 3120 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc692.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:04 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:38 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:43 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00692ent IS
END c03s04b01x00p23n01i00692ent;
ARCHITECTURE c03s04b01x00p23n01i00692arch OF c03s04b01x00p23n01i00692ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of BIT;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.08";
-- Declare a variable into which we will read.
constant CON : BIT := '1';
variable VAR : BIT;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00692"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00692 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00692arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2957.vhd | 4 | 2005 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2957.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p02n01i02957ent IS
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
begin
assert (I1 /= '1')
report "No failure on test" ;
assert (I3 /= 5)
report "No failure on test" ;
; --Failure here
END c02s02b00x00p02n01i02957ent;
ARCHITECTURE c02s02b00x00p02n01i02957arch OF c02s02b00x00p02n01i02957ent IS
signal S1 : Bit := '1';
signal S2 : Integer := 5;
signal S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
PX(S1,S3,S2);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c02s02b00x00p02n01i02957 - Missing keyword end."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p02n01i02957arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2074.vhd | 4 | 2502 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2074.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02074ent IS
END c07s02b04x00p01n02i02074ent;
ARCHITECTURE c07s02b04x00p01n02i02074arch OF c07s02b04x00p01n02i02074ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- Local declarations.
variable DISTV : DISTANCE := 1 A;
variable POSRV : POSITIVE_R := 0.0;
BEGIN
DISTV := DISTV + POSRV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02074 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02074arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_03.vhd | 4 | 1604 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_03 is
end entity ch_18_03;
----------------------------------------------------------------
architecture test of ch_18_03 is
begin
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
procedure write ( file f : file_type; value : in element_type );
-- end of code from book
procedure write ( file f : file_type; value : in element_type ) is
begin
end;
begin
wait;
end process;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc414.vhd | 4 | 2997 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc414.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00414ent IS
END c03s02b01x01p19n01i00414ent;
ARCHITECTURE c03s02b01x01p19n01i00414arch OF c03s02b01x01p19n01i00414ent IS
constant C1 : positive := 1;
function complex_scalar(s : positive) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return positive is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : positive;
signal S2 : positive;
signal S3 : positive := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00414"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00414 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00414arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2441.vhd | 4 | 1756 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2441.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02441ent IS
type a_index is range 0 to 15;
type a_bus is array (a_index range <>) of bit;
END c07s03b02x02p01n01i02441ent;
ARCHITECTURE c07s03b02x02p01n01i02441arch OF c07s03b02x02p01n01i02441ent IS
signal a_sig : a_bus(a_index range 0 to 3) := (4 => '1', others => '0');
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02441 - Each choice must specify values of the index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02441arch;
| gpl-2.0 |
emogenet/ghdl | libraries/vital95/vital_primitives_body.vhdl | 6 | 235006 | -------------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : VITAL
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #204 - glitch detection prior to OutputMap
-- ----------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
PACKAGE BODY VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Default values for Primitives
-- ------------------------------------------------------------------------
-- default values for delay parameters
CONSTANT VitalDefDelay01 : VitalDelayType01 := VitalZeroDelay01;
CONSTANT VitalDefDelay01Z : VitalDelayType01Z := VitalZeroDelay01Z;
TYPE VitalTimeArray IS ARRAY (NATURAL RANGE <>) OF TIME;
-- default primitive model operation parameters
-- Glitch detection/reporting
TYPE VitalGlitchModeType IS ( MessagePlusX, MessageOnly, XOnly, NoGlitch);
CONSTANT PrimGlitchMode : VitalGlitchModeType := XOnly;
-- ------------------------------------------------------------------------
-- Local Type and Subtype Declarations
-- ------------------------------------------------------------------------
---------------------------------------------------------------------------
-- enumeration value representing the transition or level of the signal.
-- See function 'GetEdge'
---------------------------------------------------------------------------
TYPE EdgeType IS ( 'U', -- Uninitialized level
'X', -- Unknown level
'0', -- low level
'1', -- high level
'\', -- 1 to 0 falling edge
'/', -- 0 to 1 rising edge
'F', -- * to 0 falling edge
'R', -- * to 1 rising edge
'f', -- rising to X edge
'r', -- falling to X edge
'x', -- Unknown edge (ie U->X)
'V' -- Timing violation edge
);
TYPE EdgeArray IS ARRAY ( NATURAL RANGE <> ) OF EdgeType;
TYPE EdgeX1Table IS ARRAY ( EdgeType ) OF EdgeType;
TYPE EdgeX2Table IS ARRAY ( EdgeType, EdgeType ) OF EdgeType;
TYPE EdgeX3Table IS ARRAY ( EdgeType, EdgeType, EdgeType ) OF EdgeType;
TYPE EdgeX4Table IS ARRAY (EdgeType,EdgeType,EdgeType,EdgeType) OF EdgeType;
TYPE LogicToEdgeT IS ARRAY(std_ulogic, std_ulogic) OF EdgeType;
TYPE LogicToLevelT IS ARRAY(std_ulogic ) OF EdgeType;
TYPE GlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
CurrentValue : std_ulogic;
END RECORD;
TYPE GlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF GlitchDataType;
-- Enumerated type used in selection of output path delays
TYPE SchedType IS
RECORD
inp0 : TIME; -- time (abs) of output change due to input change to 0
inp1 : TIME; -- time (abs) of output change due to input change to 1
InpX : TIME; -- time (abs) of output change due to input change to X
Glch0 : TIME; -- time (abs) of output glitch due to input change to 0
Glch1 : TIME; -- time (abs) of output glitch due to input change to 0
END RECORD;
TYPE SchedArray IS ARRAY ( NATURAL RANGE <> ) OF SchedType;
CONSTANT DefSchedType : SchedType := (TIME'HIGH, TIME'HIGH, 0 ns,0 ns,0 ns);
CONSTANT DefSchedAnd : SchedType := (TIME'HIGH, 0 ns,0 ns, TIME'HIGH,0 ns);
-- Constrained array declarations (common sizes used by primitives)
SUBTYPE SchedArray2 IS SchedArray(1 DOWNTO 0);
SUBTYPE SchedArray3 IS SchedArray(2 DOWNTO 0);
SUBTYPE SchedArray4 IS SchedArray(3 DOWNTO 0);
SUBTYPE SchedArray8 IS SchedArray(7 DOWNTO 0);
SUBTYPE TimeArray2 IS VitalTimeArray(1 DOWNTO 0);
SUBTYPE TimeArray3 IS VitalTimeArray(2 DOWNTO 0);
SUBTYPE TimeArray4 IS VitalTimeArray(3 DOWNTO 0);
SUBTYPE TimeArray8 IS VitalTimeArray(7 DOWNTO 0);
SUBTYPE GlitchArray2 IS GlitchDataArrayType(1 DOWNTO 0);
SUBTYPE GlitchArray3 IS GlitchDataArrayType(2 DOWNTO 0);
SUBTYPE GlitchArray4 IS GlitchDataArrayType(3 DOWNTO 0);
SUBTYPE GlitchArray8 IS GlitchDataArrayType(7 DOWNTO 0);
SUBTYPE EdgeArray2 IS EdgeArray(1 DOWNTO 0);
SUBTYPE EdgeArray3 IS EdgeArray(2 DOWNTO 0);
SUBTYPE EdgeArray4 IS EdgeArray(3 DOWNTO 0);
SUBTYPE EdgeArray8 IS EdgeArray(7 DOWNTO 0);
CONSTANT DefSchedArray2 : SchedArray2 :=
(OTHERS=> (0 ns, 0 ns, 0 ns, 0 ns, 0 ns));
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT InitialEdge : LogicToLevelT := (
'1'|'H' => 'R',
'0'|'L' => 'F',
OTHERS => 'x'
);
CONSTANT LogicToEdge : LogicToEdgeT := ( -- previous, current
-- old \ new: U X 0 1 Z W L H -
'U' => ( 'U', 'x', 'F', 'R', 'x', 'x', 'F', 'R', 'x' ),
'X' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ),
'0' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ),
'1' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ),
'Z' => ( 'x', 'X', 'F', 'R', 'X', 'x', 'F', 'R', 'x' ),
'W' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ),
'L' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ),
'H' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ),
'-' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' )
);
CONSTANT LogicToLevel : LogicToLevelT := (
'1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X'
);
-- -----------------------------------
-- 3-state logic tables
-- -----------------------------------
CONSTANT BufIf0_Table : stdlogic_table :=
-- enable data value
( '1'|'H' => ( OTHERS => 'Z' ),
'0'|'L' => ( '1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT BufIf1_Table : stdlogic_table :=
-- enable data value
( '0'|'L' => ( OTHERS => 'Z' ),
'1'|'H' => ( '1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT InvIf0_Table : stdlogic_table :=
-- enable data value
( '1'|'H' => ( OTHERS => 'Z' ),
'0'|'L' => ( '1'|'H' => '0',
'0'|'L' => '1',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT InvIf1_Table : stdlogic_table :=
-- enable data value
( '0'|'L' => ( OTHERS => 'Z' ),
'1'|'H' => ( '1'|'H' => '0',
'0'|'L' => '1',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
TYPE To_StateCharType IS ARRAY (VitalStateSymbolType) OF CHARACTER;
CONSTANT To_StateChar : To_StateCharType :=
( '/', '\', 'P', 'N', 'r', 'f', 'p', 'n', 'R', 'F', '^', 'v',
'E', 'A', 'D', '*', 'X', '0', '1', '-', 'B', 'Z', 'S' );
TYPE To_TruthCharType IS ARRAY (VitalTruthSymbolType) OF CHARACTER;
CONSTANT To_TruthChar : To_TruthCharType :=
( 'X', '0', '1', '-', 'B', 'Z' );
TYPE TruthTableOutMapType IS ARRAY (VitalTruthSymbolType) OF std_ulogic;
CONSTANT TruthTableOutMap : TruthTableOutMapType :=
-- 'X', '0', '1', '-', 'B', 'Z'
( 'X', '0', '1', 'X', '-', 'Z' );
TYPE StateTableOutMapType IS ARRAY (VitalStateSymbolType) OF std_ulogic;
-- does conversion to X01Z or '-' if invalid
CONSTANT StateTableOutMap : StateTableOutMapType :=
-- '/' '\' 'P' 'N' 'r' 'f' 'p' 'n' 'R' 'F' '^' 'v'
-- 'E' 'A' 'D' '*' 'X' '0' '1' '-' 'B' 'Z' 'S'
( '-','-','-','-','-','-','-','-','-','-','-','-',
'-','-','-','-','X','0','1','X','-','Z','W');
-- ------------------------------------------------------------------------
TYPE ValidTruthTableInputType IS ARRAY (VitalTruthSymbolType) OF BOOLEAN;
-- checks if a symbol IS valid for the stimulus portion of a truth table
CONSTANT ValidTruthTableInput : ValidTruthTableInputType :=
-- 'X' '0' '1' '-' 'B' 'Z'
( TRUE, TRUE, TRUE, TRUE, TRUE, FALSE );
TYPE TruthTableMatchType IS ARRAY (X01, VitalTruthSymbolType) OF BOOLEAN;
-- checks if an input matches th corresponding truth table symbol
-- use: TruthTableMatch(input_converted_to_X01, truth_table_stimulus_symbol)
CONSTANT TruthTableMatch : TruthTableMatchType := (
-- X, 0, 1, - B Z
( TRUE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- X
( FALSE, TRUE, FALSE, TRUE, TRUE, FALSE ), -- 0
( FALSE, FALSE, TRUE, TRUE, TRUE, FALSE ) -- 1
);
-- ------------------------------------------------------------------------
TYPE ValidStateTableInputType IS ARRAY (VitalStateSymbolType) OF BOOLEAN;
CONSTANT ValidStateTableInput : ValidStateTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'p', 'n', 'R', 'F', '^', 'v',
TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'E', 'A', 'D', '*',
TRUE, TRUE, TRUE, TRUE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S'
TRUE );
CONSTANT ValidStateTableState : ValidStateTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'p', 'n', 'R', 'F', '^', 'v',
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'E', 'A', 'D', '*',
FALSE, FALSE, FALSE, FALSE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S'
FALSE );
TYPE StateTableMatchType IS ARRAY (X01,X01,VitalStateSymbolType) OF BOOLEAN;
-- last value, present value, table symbol
CONSTANT StateTableMatch : StateTableMatchType := (
( -- X (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,FALSE,FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,TRUE, TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE),
(FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, FALSE,TRUE, FALSE,
TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE)
),
(-- 0 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,TRUE, FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,TRUE ),
(TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE)
),
(-- 1 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,FALSE,TRUE ,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE),
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,TRUE )
)
);
TYPE Logic_UX01Z_Table IS ARRAY (std_ulogic) OF UX01Z;
----------------------------------------------------------
-- table name : cvt_to_x01z
-- parameters : std_ulogic -- some logic value
-- returns : UX01Z -- state value of logic value
-- purpose : to convert state-strength to state only
----------------------------------------------------------
CONSTANT cvt_to_ux01z : Logic_UX01Z_Table :=
('U','X','0','1','Z','X','0','1','X' );
TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER;
CONSTANT LogicCvtTable : LogicCvtTableType
:= ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
--------------------------------------------------------------------
-- LOCAL Utilities
--------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- FUNCTION NAME : MINIMUM
--
-- PARAMETERS : in1, in2 - integer, time
--
-- DESCRIPTION : return smaller of in1 and in2
-- ------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT in1, in2 : INTEGER
) RETURN INTEGER IS
BEGIN
IF (in1 < in2) THEN
RETURN in1;
END IF;
RETURN in2;
END;
-- ------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT t1,t2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( t1 < t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Minimum;
-- ------------------------------------------------------------------------
-- FUNCTION NAME : MAXIMUM
--
-- PARAMETERS : in1, in2 - integer, time
--
-- DESCRIPTION : return larger of in1 and in2
-- ------------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT in1, in2 : INTEGER
) RETURN INTEGER IS
BEGIN
IF (in1 > in2) THEN
RETURN in1;
END IF;
RETURN in2;
END;
-----------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT t1,t2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( t1 > t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Maximum;
-----------------------------------------------------------------------
FUNCTION GlitchMinTime (
CONSTANT Time1, Time2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( Time1 >= NOW ) THEN
IF ( Time2 >= NOW ) THEN
RETURN Minimum ( Time1, Time2);
ELSE
RETURN Time1;
END IF;
ELSE
IF ( Time2 >= NOW ) THEN
RETURN Time2;
ELSE
RETURN 0 ns;
END IF;
END IF;
END;
--------------------------------------------------------------------
-- Error Message Types and Tables
--------------------------------------------------------------------
TYPE VitalErrorType IS (
ErrNegDel,
ErrInpSym,
ErrOutSym,
ErrStaSym,
ErrVctLng,
ErrTabWidSml,
ErrTabWidLrg,
ErrTabResSml,
ErrTabResLrg
);
TYPE VitalErrorSeverityType IS ARRAY (VitalErrorType) OF SEVERITY_LEVEL;
CONSTANT VitalErrorSeverity : VitalErrorSeverityType := (
ErrNegDel => WARNING,
ErrInpSym => ERROR,
ErrOutSym => ERROR,
ErrStaSym => ERROR,
ErrVctLng => ERROR,
ErrTabWidSml => ERROR,
ErrTabWidLrg => WARNING,
ErrTabResSml => WARNING,
ErrTabResLrg => WARNING
);
CONSTANT MsgNegDel : STRING :=
"Negative delay. New output value not scheduled. Output signal is: ";
CONSTANT MsgInpSym : STRING :=
"Illegal symbol in the input portion of a Truth/State table.";
CONSTANT MsgOutSym : STRING :=
"Illegal symbol in the output portion of a Truth/State table.";
CONSTANT MsgStaSym : STRING :=
"Illegal symbol in the state portion of a State table.";
CONSTANT MsgVctLng : STRING :=
"Vector (array) lengths not equal. ";
CONSTANT MsgTabWidSml : STRING :=
"Width of the Truth/State table is too small.";
CONSTANT MsgTabWidLrg : STRING :=
"Width of Truth/State table is too large. Extra elements are ignored.";
CONSTANT MsgTabResSml : STRING :=
"Result of Truth/State table has too many elements.";
CONSTANT MsgTabResLrg : STRING :=
"Result of Truth/State table has too few elements.";
CONSTANT MsgUnknown : STRING :=
"Unknown error message.";
--------------------------------------------------------------------
-- LOCAL Utilities
--------------------------------------------------------------------
FUNCTION VitalMessage (
CONSTANT ErrorId : IN VitalErrorType
) RETURN STRING IS
BEGIN
CASE ErrorId IS
WHEN ErrNegDel => RETURN MsgNegDel;
WHEN ErrInpSym => RETURN MsgInpSym;
WHEN ErrOutSym => RETURN MsgOutSym;
WHEN ErrStaSym => RETURN MsgStaSym;
WHEN ErrVctLng => RETURN MsgVctLng;
WHEN ErrTabWidSml => RETURN MsgTabWidSml;
WHEN ErrTabWidLrg => RETURN MsgTabWidLrg;
WHEN ErrTabResSml => RETURN MsgTabResSml;
WHEN ErrTabResLrg => RETURN MsgTabResLrg;
WHEN OTHERS => RETURN MsgUnknown;
END CASE;
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId)
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN STRING
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN CHARACTER
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
---------------------------------------------------------------------------
PROCEDURE ReportGlitch (
CONSTANT GlitchRoutine : IN STRING;
CONSTANT OutSignalName : IN STRING;
CONSTANT PreemptedTime : IN TIME;
CONSTANT PreemptedValue : IN std_ulogic;
CONSTANT NewTime : IN TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT Index : IN INTEGER := 0;
CONSTANT IsArraySignal : IN BOOLEAN := FALSE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE StrPtr1, StrPtr2, StrPtr3, StrPtr4, StrPtr5 : LINE;
BEGIN
Write (StrPtr1, PreemptedTime );
Write (StrPtr2, NewTime);
Write (StrPtr3, LogicCvtTable(PreemptedValue));
Write (StrPtr4, LogicCvtTable(NewValue));
IF IsArraySignal THEN
Write (StrPtr5, STRING'( "(" ) );
Write (StrPtr5, Index);
Write (StrPtr5, STRING'( ")" ) );
ELSE
Write (StrPtr5, STRING'( " " ) );
END IF;
-- Issue Report only if Preemted value has not been
-- removed from event queue
ASSERT PreemptedTime > NewTime
REPORT GlitchRoutine & ": GLITCH Detected on port " &
OutSignalName & StrPtr5.ALL &
"; Preempted Future Value := " & StrPtr3.ALL &
" @ " & StrPtr1.ALL &
"; Newly Scheduled Value := " & StrPtr4.ALL &
" @ " & StrPtr2.ALL &
";"
SEVERITY MsgSeverity;
DEALLOCATE(StrPtr1);
DEALLOCATE(StrPtr2);
DEALLOCATE(StrPtr3);
DEALLOCATE(StrPtr4);
DEALLOCATE(StrPtr5);
RETURN;
END ReportGlitch;
---------------------------------------------------------------------------
-- Procedure : VitalGlitchOnEvent
-- :
-- Parameters : OutSignal ........ signal being driven
-- : OutSignalName..... name of the driven signal
-- : GlitchData........ internal data required by the procedure
-- : NewValue.......... new value being assigned
-- : NewDelay.......... Delay accompanying the assignment
-- : (Note: for vectors, this is an array)
-- : GlitchMode........ Glitch generation mode
-- : MessagePlusX, MessageOnly,
-- : XOnly, NoGlitch )
-- : GlitchDelay....... if <= 0 ns , then there will be no Glitch
-- : if > NewDelay, then there is no Glitch,
-- : otherwise, this is the time when a FORCED
-- : generation of a glitch will occur.
----------------------------------------------------------------------------
PROCEDURE VitalGlitchOnEvent (
SIGNAL OutSignal : OUT std_logic;
CONSTANT OutSignalName : IN STRING;
VARIABLE GlitchData : INOUT GlitchDataType;
CONSTANT NewValue : IN std_logic;
CONSTANT NewDelay : IN TIME := 0 ns;
CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX;
CONSTANT GlitchDelay : IN TIME := 0 ns;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
-- ------------------------------------------------------------------------
VARIABLE NoGlitchDet : BOOLEAN := FALSE;
VARIABLE OldGlitch : BOOLEAN := FALSE;
VARIABLE Dly : TIME := NewDelay;
BEGIN
-- If nothing to schedule, just return
IF NewDelay < 0 ns THEN
IF (NewValue /= GlitchData.SchedValue) THEN
VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName );
END IF;
ELSE
-- If nothing currently scheduled
IF GlitchData.SchedTime <= NOW THEN
GlitchData.CurrentValue := GlitchData.SchedValue;
IF (GlitchDelay <= 0 ns) THEN
IF (NewValue = GlitchData.SchedValue) THEN RETURN; END IF;
NoGlitchDet := TRUE;
END IF;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlitchData.GlitchTime <= NOW THEN
GlitchData.CurrentValue := 'X';
OldGlitch := TRUE;
IF (GlitchData.SchedValue = NewValue) THEN
dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
-- Transaction currently scheduled (no glitch if same value)
ELSIF (GlitchData.SchedValue = NewValue) AND
(GlitchData.SchedTime = GlitchData.GlitchTime) AND
(GlitchDelay <= 0 ns) THEN
NoGlitchDet := TRUE;
Dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
GlitchData.SchedTime := NOW+Dly;
IF OldGlitch THEN
OutSignal <= NewValue AFTER Dly;
ELSIF NoGlitchDet THEN
GlitchData.GlitchTime := NOW+Dly;
OutSignal <= NewValue AFTER Dly;
ELSE -- new glitch
GlitchData.GlitchTime := GlitchMinTime ( GlitchData.GlitchTime,
NOW+GlitchDelay );
IF (GlitchMode = MessagePlusX) OR
(GlitchMode = MessageOnly) THEN
ReportGlitch ( "VitalGlitchOnEvent", OutSignalName,
GlitchData.GlitchTime, GlitchData.SchedValue,
(Dly + NOW), NewValue,
MsgSeverity=>MsgSeverity );
END IF;
IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN
OutSignal <= 'X' AFTER GlitchData.GlitchTime-NOW;
OutSignal <= TRANSPORT NewValue AFTER Dly;
ELSE
OutSignal <= NewValue AFTER Dly;
END IF;
END IF;
GlitchData.SchedValue := NewValue;
END IF;
RETURN;
END;
----------------------------------------------------------------------------
PROCEDURE VitalGlitchOnEvent (
SIGNAL OutSignal : OUT std_logic_vector;
CONSTANT OutSignalName : IN STRING;
VARIABLE GlitchData : INOUT GlitchDataArrayType;
CONSTANT NewValue : IN std_logic_vector;
CONSTANT NewDelay : IN VitalTimeArray;
CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX;
CONSTANT GlitchDelay : IN VitalTimeArray;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
ALIAS GlDataAlias : GlitchDataArrayType(1 TO GlitchData'LENGTH)
IS GlitchData;
ALIAS NewValAlias : std_logic_vector(1 TO NewValue'LENGTH) IS NewValue;
ALIAS GlDelayAlias : VitalTimeArray(1 TO GlitchDelay'LENGTH)
IS GlitchDelay;
ALIAS NewDelAlias : VitalTimeArray(1 TO NewDelay'LENGTH) IS NewDelay;
VARIABLE Index : INTEGER := OutSignal'LEFT;
VARIABLE Direction : INTEGER;
VARIABLE NoGlitchDet : BOOLEAN;
VARIABLE OldGlitch : BOOLEAN;
VARIABLE Dly, GlDly : TIME;
BEGIN
IF (OutSignal'LEFT > OutSignal'RIGHT) THEN
Direction := -1;
ELSE
Direction := 1;
END IF;
IF ( (OutSignal'LENGTH /= GlitchData'LENGTH) OR
(OutSignal'LENGTH /= NewValue'LENGTH) OR
(OutSignal'LENGTH /= NewDelay'LENGTH) OR
(OutSignal'LENGTH /= GlitchDelay'LENGTH) ) THEN
VitalError ( "VitalGlitchOnEvent", ErrVctLng, OutSignalName );
RETURN;
END IF;
-- a call to the scalar function cannot be made since the actual
-- name associated with a signal parameter must be locally static
FOR n IN 1 TO OutSignal'LENGTH LOOP
NoGlitchDet := FALSE;
OldGlitch := FALSE;
Dly := NewDelAlias(n);
-- If nothing to schedule, just skip to next loop iteration
IF NewDelAlias(n) < 0 ns THEN
IF (NewValAlias(n) /= GlDataAlias(n).SchedValue) THEN
VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName );
END IF;
ELSE
-- If nothing currently scheduled (i.e. last scheduled
-- transaction already occurred)
IF GlDataAlias(n).SchedTime <= NOW THEN
GlDataAlias(n).CurrentValue := GlDataAlias(n).SchedValue;
IF (GlDelayAlias(n) <= 0 ns) THEN
-- Next iteration if no change in value
IF (NewValAlias(n) = GlDataAlias(n).SchedValue) THEN
Index := Index + Direction;
NEXT;
END IF;
-- since last transaction already occurred there is no glitch
NoGlitchDet := TRUE;
END IF;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlDataAlias(n).GlitchTime <= NOW THEN
GlDataAlias(n).CurrentValue := 'X';
OldGlitch := TRUE;
IF (GlDataAlias(n).SchedValue = NewValAlias(n)) THEN
dly := Minimum( GlDataAlias(n).SchedTime-NOW,
NewDelAlias(n) );
END IF;
-- Transaction currently scheduled
ELSIF (GlDataAlias(n).SchedValue = NewValAlias(n)) AND
(GlDataAlias(n).SchedTime = GlDataAlias(n).GlitchTime) AND
(GlDelayAlias(n) <= 0 ns) THEN
NoGlitchDet := TRUE;
Dly := Minimum( GlDataAlias(n).SchedTime-NOW,
NewDelAlias(n) );
END IF;
-- update last scheduled transaction
GlDataAlias(n).SchedTime := NOW+Dly;
IF OldGlitch THEN
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
ELSIF NoGlitchDet THEN
-- if no glitch then update last glitch time
-- and OutSignal(actual_index)
GlDataAlias(n).GlitchTime := NOW+Dly;
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
ELSE -- new glitch
GlDataAlias(n).GlitchTime := GlitchMinTime (
GlDataAlias(n).GlitchTime,
NOW+GlDelayAlias(n) );
IF (GlitchMode = MessagePlusX) OR
(GlitchMode = MessageOnly) THEN
ReportGlitch ( "VitalGlitchOnEvent", OutSignalName,
GlDataAlias(n).GlitchTime,
GlDataAlias(n).SchedValue,
(Dly + NOW), NewValAlias(n),
Index, TRUE, MsgSeverity );
END IF;
IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN
GlDly := GlDataAlias(n).GlitchTime - NOW;
OutSignal(Index) <= 'X' AFTER GlDly;
OutSignal(Index) <= TRANSPORT NewValAlias(n) AFTER Dly;
ELSE
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
END IF;
END IF; -- glitch / no-glitch
GlDataAlias(n).SchedValue := NewValAlias(n);
END IF; -- NewDelAlias(n) < 0 ns
Index := Index + Direction;
END LOOP;
RETURN;
END;
---------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- PROCEDURE NAME : TruthOutputX01Z
--
-- PARAMETERS : table_out - output of table
-- X01Zout - output converted to X01Z
-- err - true if illegal character is encountered
--
--
-- DESCRIPTION : converts the output of a truth table to a valid
-- std_ulogic
-- ------------------------------------------------------------------------
PROCEDURE TruthOutputX01Z (
CONSTANT TableOut : IN VitalTruthSymbolType;
VARIABLE X01Zout : OUT std_ulogic;
VARIABLE Err : OUT BOOLEAN
) IS
VARIABLE TempOut : std_ulogic;
BEGIN
Err := FALSE;
TempOut := TruthTableOutMap(TableOut);
IF (TempOut = '-') THEN
Err := TRUE;
TempOut := 'X';
VitalError ( "VitalTruthTable", ErrOutSym, To_TruthChar(TableOut));
END IF;
X01Zout := TempOut;
END;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME : StateOutputX01Z
--
-- PARAMETERS : table_out - output of table
-- prev_out - previous output value
-- X01Zout - output cojnverted to X01Z
-- err - true if illegal character is encountered
--
-- DESCRIPTION : converts the output of a state table to a
-- valid std_ulogic
-- ------------------------------------------------------------------------
PROCEDURE StateOutputX01Z (
CONSTANT TableOut : IN VitalStateSymbolType;
CONSTANT PrevOut : IN std_ulogic;
VARIABLE X01Zout : OUT std_ulogic;
VARIABLE Err : OUT BOOLEAN
) IS
VARIABLE TempOut : std_ulogic;
BEGIN
Err := FALSE;
TempOut := StateTableOutMap(TableOut);
IF (TempOut = '-') THEN
Err := TRUE;
TempOut := 'X';
VitalError ( "VitalStateTable", ErrOutSym, To_StateChar(TableOut));
ELSIF (TempOut = 'W') THEN
TempOut := To_X01Z(PrevOut);
END IF;
X01Zout := TempOut;
END;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME: StateMatch
--
-- PARAMETERS : symbol - symbol from state table
-- in2 - input from VitalStateTble procedure
-- to state table
-- in2LastValue - previous value of input
-- state - false if the symbol is from the input
-- portion of the table,
-- true if the symbol is from the state
-- portion of the table
-- Err - true if symbol is not a valid input symbol
-- ReturnValue - true if match occurred
--
-- DESCRIPTION : This procedure sets ReturnValue to true if in2 matches
-- symbol (from the state table). If symbol is an edge
-- value edge is set to true and in2 and in2LastValue are
-- checked against symbol. Err is set to true if symbol
-- is an invalid value for the input portion of the state
-- table.
--
-- ------------------------------------------------------------------------
PROCEDURE StateMatch (
CONSTANT Symbol : IN VitalStateSymbolType;
CONSTANT in2 : IN std_ulogic;
CONSTANT in2LastValue : IN std_ulogic;
CONSTANT State : IN BOOLEAN;
VARIABLE Err : OUT BOOLEAN;
VARIABLE ReturnValue : OUT BOOLEAN
) IS
BEGIN
IF (State) THEN
IF (NOT ValidStateTableState(Symbol)) THEN
VitalError ( "VitalStateTable", ErrStaSym, To_StateChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
Err := FALSE;
ReturnValue := StateTableMatch(in2LastValue, in2, Symbol);
END IF;
ELSE
IF (NOT ValidStateTableInput(Symbol) ) THEN
VitalError ( "VitalStateTable", ErrInpSym, To_StateChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
ReturnValue := StateTableMatch(in2LastValue, in2, Symbol);
Err := FALSE;
END IF;
END IF;
END;
-- -----------------------------------------------------------------------
-- FUNCTION NAME: StateTableLookUp
--
-- PARAMETERS : StateTable - state table
-- PresentDataIn - current inputs
-- PreviousDataIn - previous inputs and states
-- NumStates - number of state variables
-- PresentOutputs - current state and current outputs
--
-- DESCRIPTION : This function is used to find the output of the
-- StateTable corresponding to a given set of inputs.
--
-- ------------------------------------------------------------------------
FUNCTION StateTableLookUp (
CONSTANT StateTable : VitalStateTableType;
CONSTANT PresentDataIn : std_logic_vector;
CONSTANT PreviousDataIn : std_logic_vector;
CONSTANT NumStates : NATURAL;
CONSTANT PresentOutputs : std_logic_vector
) RETURN std_logic_vector IS
CONSTANT InputSize : INTEGER := PresentDataIn'LENGTH;
CONSTANT NumInputs : INTEGER := InputSize + NumStates - 1;
CONSTANT TableEntries : INTEGER := StateTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := StateTable'LENGTH(2);
CONSTANT OutSize : INTEGER := TableWidth - InputSize - NumStates;
VARIABLE Inputs : std_logic_vector(0 TO NumInputs);
VARIABLE PrevInputs : std_logic_vector(0 TO NumInputs)
:= (OTHERS => 'X');
VARIABLE ReturnValue : std_logic_vector(0 TO (OutSize-1))
:= (OTHERS => 'X');
VARIABLE Temp : std_ulogic;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
-- This needs to be done since the TableLookup arrays must be
-- ascending starting with 0
VARIABLE TableAlias : VitalStateTableType(0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= StateTable;
BEGIN
Inputs(0 TO InputSize-1) := PresentDataIn;
Inputs(InputSize TO NumInputs) := PresentOutputs(0 TO NumStates - 1);
PrevInputs(0 TO InputSize - 1) := PreviousDataIn(0 TO InputSize - 1);
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the entry
FOR j IN 0 TO InputSize + NumStates LOOP
IF (j = InputSize + NumStates) THEN -- a match occurred
FOR k IN 0 TO Minimum(OutSize, PresentOutputs'LENGTH)-1 LOOP
StateOutputX01Z (
TableAlias(i, TableWidth - k - 1),
PresentOutputs(PresentOutputs'LENGTH - k - 1),
Temp, Err);
ReturnValue(OutSize - k - 1) := Temp;
IF (Err) THEN
ReturnValue := (OTHERS => 'X');
RETURN ReturnValue;
END IF;
END LOOP;
RETURN ReturnValue;
END IF;
StateMatch ( TableAlias(i,j),
Inputs(j), PrevInputs(j),
j >= InputSize, Err, Match);
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
ReturnValue := (OTHERS => 'X');
RETURN ReturnValue;
END;
--------------------------------------------------------------------
-- to_ux01z
-------------------------------------------------------------------
FUNCTION To_UX01Z ( s : std_ulogic
) RETURN UX01Z IS
BEGIN
RETURN cvt_to_ux01z (s);
END;
---------------------------------------------------------------------------
-- Function : GetEdge
-- Purpose : Converts transitions on a given input signal into a
-- enumeration value representing the transition or level
-- of the signal.
--
-- previous "value" current "value" := "edge"
-- ---------------------------------------------------------
-- '1' | 'H' '1' | 'H' '1' level, no edge
-- '0' | 'L' '1' | 'H' '/' rising edge
-- others '1' | 'H' 'R' rising from X
--
-- '1' | 'H' '0' | 'L' '\' falling egde
-- '0' | 'L' '0' | 'L' '0' level, no edge
-- others '0' | 'L' 'F' falling from X
--
-- 'X' | 'W' | '-' 'X' | 'W' | '-' 'X' unknown (X) level
-- 'Z' 'Z' 'X' unknown (X) level
-- 'U' 'U' 'U' 'U' level
--
-- '1' | 'H' others 'f' falling to X
-- '0' | 'L' others 'r' rising to X
-- 'X' | 'W' | '-' 'U' | 'Z' 'x' unknown (X) edge
-- 'Z' 'X' | 'W' | '-' | 'U' 'x' unknown (X) edge
-- 'U' 'X' | 'W' | '-' | 'Z' 'x' unknown (X) edge
--
---------------------------------------------------------------------------
FUNCTION GetEdge (
SIGNAL s : IN std_logic
) RETURN EdgeType IS
BEGIN
IF (s'EVENT)
THEN RETURN LogicToEdge ( s'LAST_VALUE, s );
ELSE RETURN LogicToLevel ( s );
END IF;
END;
---------------------------------------------------------------------------
PROCEDURE GetEdge (
SIGNAL s : IN std_logic_vector;
VARIABLE LastS : INOUT std_logic_vector;
VARIABLE Edge : OUT EdgeArray ) IS
ALIAS sAlias : std_logic_vector ( 1 TO s'LENGTH ) IS s;
ALIAS LastSAlias : std_logic_vector ( 1 TO LastS'LENGTH ) IS LastS;
ALIAS EdgeAlias : EdgeArray ( 1 TO Edge'LENGTH ) IS Edge;
BEGIN
IF s'LENGTH /= LastS'LENGTH OR
s'LENGTH /= Edge'LENGTH THEN
VitalError ( "GetEdge", ErrVctLng, "s, LastS, Edge" );
END IF;
FOR n IN 1 TO s'LENGTH LOOP
EdgeAlias(n) := LogicToEdge( LastSAlias(n), sAlias(n) );
LastSAlias(n) := sAlias(n);
END LOOP;
END;
---------------------------------------------------------------------------
FUNCTION ToEdge ( Value : IN std_logic
) RETURN EdgeType IS
BEGIN
RETURN LogicToLevel( Value );
END;
-- Note: This function will likely be replaced by S'DRIVING_VALUE in VHDL'92
----------------------------------------------------------------------------
FUNCTION CurValue (
CONSTANT GlitchData : IN GlitchDataType
) RETURN std_logic IS
BEGIN
IF NOW >= GlitchData.SchedTime THEN
RETURN GlitchData.SchedValue;
ELSIF NOW >= GlitchData.GlitchTime THEN
RETURN 'X';
ELSE
RETURN GlitchData.CurrentValue;
END IF;
END;
---------------------------------------------------------------------------
FUNCTION CurValue (
CONSTANT GlitchData : IN GlitchDataArrayType
) RETURN std_logic_vector IS
VARIABLE Result : std_logic_vector(GlitchData'RANGE);
BEGIN
FOR n IN GlitchData'RANGE LOOP
IF NOW >= GlitchData(n).SchedTime THEN
Result(n) := GlitchData(n).SchedValue;
ELSIF NOW >= GlitchData(n).GlitchTime THEN
Result(n) := 'X';
ELSE
Result(n) := GlitchData(n).CurrentValue;
END IF;
END LOOP;
RETURN Result;
END;
---------------------------------------------------------------------------
-- function calculation utilities
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Function : VitalSame
-- Returns : VitalSame compares the state (UX01) of two logic value. A
-- value of 'X' is returned if the values are different. The
-- common value is returned if the values are equal.
-- Purpose : When the result of a logic model may be either of two
-- separate input values (eg. when the select on a MUX is 'X'),
-- VitalSame may be used to determine if the result needs to
-- be 'X'.
-- Arguments : See the declarations below...
---------------------------------------------------------------------------
FUNCTION VitalSame (
CONSTANT a, b : IN std_ulogic
) RETURN std_ulogic IS
BEGIN
IF To_UX01(a) = To_UX01(b)
THEN RETURN To_UX01(a);
ELSE RETURN 'X';
END IF;
END;
---------------------------------------------------------------------------
-- delay selection utilities
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure : BufPath, InvPath
--
-- Purpose : BufPath and InvPath compute output change times, based on
-- a change on an input port. The computed output change times
-- returned in the composite parameter 'schd'.
--
-- BufPath and InpPath are used together with the delay path
-- selection functions (GetSchedDelay, VitalAND, VitalOR... )
-- The 'schd' value from each of the input ports of a model are
-- combined by the delay selection functions (VitalAND,
-- VitalOR, ...). The GetSchedDelay procedure converts the
-- combined output changes times to the single delay (delta
-- time) value for scheduling the output change (passed to
-- VitalGlitchOnEvent).
--
-- The values in 'schd' are: (absolute times)
-- inp0 : time of output change due to input change to 0
-- inp1 : time of output change due to input change to 1
-- inpX : time of output change due to input change to X
-- glch0 : time of output glitch due to input change to 0
-- glch1 : time of output glitch due to input change to 1
--
-- The output times are computed from the model INPUT value
-- and not the final value. For this reason, 'BufPath' should
-- be used to compute the output times for a non-inverting
-- delay paths and 'InvPath' should be used to compute the
-- ouput times for inverting delay paths. Delay paths which
-- include both non-inverting and paths require usage of both
-- 'BufPath' and 'InvPath'. (IE this is needed for the
-- select->output path of a MUX -- See the VitalMUX model).
--
--
-- Parameters : schd....... Computed output result times. (INOUT parameter
-- modified only on input edges)
-- Iedg....... Input port edge/level value.
-- tpd....... Propagation delays from this input
--
---------------------------------------------------------------------------
PROCEDURE BufPath (
VARIABLE Schd : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := NOW + tpd(tr01); Schd.Glch1 := Schd.inp1;
Schd.InpX := Schd.inp1;
WHEN '\'|'F' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := NOW + tpd(tr10); Schd.Glch0 := Schd.inp0;
Schd.InpX := Schd.inp0;
WHEN 'r' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr01);
WHEN 'f' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr10);
WHEN 'x' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
-- update for X->X change
Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE BufPath (
VARIABLE Schd : INOUT SchedArray;
CONSTANT Iedg : IN EdgeArray;
CONSTANT tpd : IN VitalDelayArrayType01
) IS
BEGIN
FOR n IN Schd'RANGE LOOP
CASE Iedg(n) IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := NOW + tpd(n)(tr01);
Schd(n).Glch1 := Schd(n).inp1;
Schd(n).InpX := Schd(n).inp1;
WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := NOW + tpd(n)(tr10);
Schd(n).Glch0 := Schd(n).inp0;
Schd(n).InpX := Schd(n).inp0;
WHEN 'r' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr01);
WHEN 'f' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr10);
WHEN 'x' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
-- update for X->X change
Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10),
tpd(n)(tr01) );
WHEN OTHERS => NULL; -- no timing change
END CASE;
END LOOP;
END;
PROCEDURE InvPath (
VARIABLE Schd : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := NOW + tpd(tr10); Schd.Glch1 := Schd.inp1;
Schd.InpX := Schd.inp1;
WHEN '\'|'F' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := NOW + tpd(tr01); Schd.Glch0 := Schd.inp0;
Schd.InpX := Schd.inp0;
WHEN 'r' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr10);
WHEN 'f' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr01);
WHEN 'x' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
-- update for X->X change
Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE InvPath (
VARIABLE Schd : INOUT SchedArray;
CONSTANT Iedg : IN EdgeArray;
CONSTANT tpd : IN VitalDelayArrayType01
) IS
BEGIN
FOR n IN Schd'RANGE LOOP
CASE Iedg(n) IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := NOW + tpd(n)(tr10);
Schd(n).Glch1 := Schd(n).inp1;
Schd(n).InpX := Schd(n).inp1;
WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := NOW + tpd(n)(tr01);
Schd(n).Glch0 := Schd(n).inp0;
Schd(n).InpX := Schd(n).inp0;
WHEN 'r' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr10);
WHEN 'f' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr01);
WHEN 'x' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
-- update for X->X change
Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10),
tpd(n)(tr01) );
WHEN OTHERS => NULL; -- no timing change
END CASE;
END LOOP;
END;
---------------------------------------------------------------------------
-- Procedure : BufEnab, InvEnab
--
-- Purpose : BufEnab and InvEnab compute output change times, from a
-- change on an input enable port for a 3-state driver. The
-- computed output change times are returned in the composite
-- parameters 'schd1', 'schd0'.
--
-- BufEnab and InpEnab are used together with the delay path
-- selection functions (GetSchedDelay, VitalAND, VitalOR... )
-- The 'schd' value from each of the non-enable input ports of
-- a model (See BufPath, InvPath) are combined using the delay
-- selection functions (VitalAND, VitalOR, ...). The
-- GetSchedDelay procedure combines the output times on the
-- enable path with the output times from the data path(s) and
-- computes the single delay (delta time) value for scheduling
-- the output change (passed to VitalGlitchOnEvent)
--
-- The values in 'schd*' are: (absolute times)
-- inp0 : time of output change due to input change to 0
-- inp1 : time of output change due to input change to 1
-- inpX : time of output change due to input change to X
-- glch0 : time of output glitch due to input change to 0
-- glch1 : time of output glitch due to input change to 1
--
-- 'schd1' contains output times for 1->Z, Z->1 transitions.
-- 'schd0' contains output times for 0->Z, Z->0 transitions.
--
-- 'BufEnab' is used for computing the output times for an
-- high asserted enable (output 'Z' for enable='0').
-- 'InvEnab' is used for computing the output times for an
-- low asserted enable (output 'Z' for enable='1').
--
-- Note: separate 'schd1', 'schd0' parameters are generated
-- so that the combination of the delay paths from
-- multiple enable signals may be combined using the
-- same functions/operators used in combining separate
-- data paths. (See exampe 2 below)
--
--
-- Parameters : schd1...... Computed output result times for 1->Z, Z->1
-- transitions. This parameter is modified only on
-- input edge values (events).
-- schd0...... Computed output result times for 0->Z, 0->1
-- transitions. This parameter is modified only on
-- input edge values (events).
-- Iedg....... Input port edge/level value.
-- tpd....... Propagation delays for the enable -> output path.
--
---------------------------------------------------------------------------
PROCEDURE BufEnab (
VARIABLE Schd1 : INOUT SchedType;
VARIABLE Schd0 : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01Z
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := NOW + tpd(trz1);
Schd1.Glch1 := Schd1.inp1;
Schd1.InpX := Schd1.inp1;
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := NOW + tpd(trz0);
Schd0.Glch1 := Schd0.inp1;
Schd0.InpX := Schd0.inp1;
WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := NOW + tpd(tr1z);
Schd1.Glch0 := Schd1.inp0;
Schd1.InpX := Schd1.inp0;
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := NOW + tpd(tr0z);
Schd0.Glch0 := Schd0.inp0;
Schd0.InpX := Schd0.inp0;
WHEN 'r' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := TIME'HIGH;
Schd1.InpX := NOW + tpd(trz1);
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := TIME'HIGH;
Schd0.InpX := NOW + tpd(trz0);
WHEN 'f' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + tpd(tr1z);
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + tpd(tr0z);
WHEN 'x' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE InvEnab (
VARIABLE Schd1 : INOUT SchedType;
VARIABLE Schd0 : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01Z
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := NOW + tpd(tr1z);
Schd1.Glch1 := Schd1.inp1;
Schd1.InpX := Schd1.inp1;
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := NOW + tpd(tr0z);
Schd0.Glch1 := Schd0.inp1;
Schd0.InpX := Schd0.inp1;
WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := NOW + tpd(trz1);
Schd1.Glch0 := Schd1.inp0;
Schd1.InpX := Schd1.inp0;
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := NOW + tpd(trz0);
Schd0.Glch0 := Schd0.inp0;
Schd0.InpX := Schd0.inp0;
WHEN 'r' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := TIME'HIGH;
Schd1.InpX := NOW + tpd(tr1z);
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := TIME'HIGH;
Schd0.InpX := NOW + tpd(tr0z);
WHEN 'f' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + tpd(trz1);
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + tpd(trz0);
WHEN 'x' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
---------------------------------------------------------------------------
-- Procedure : GetSchedDelay
--
-- Purpose : GetSchedDelay computes the final delay (incremental) for
-- for scheduling an output signal. The delay is computed
-- from the absolute output times in the 'NewSched' parameter.
-- (See BufPath, InvPath).
--
-- Computation of the output delay for non-3_state outputs
-- consists of selection the appropriate output time based
-- on the new output value 'NewValue' and subtracting 'NOW'
-- to convert to an incremental delay value.
--
-- The Computation of the output delay for 3_state output
-- also includes combination of the enable path delay with
-- the date path delay.
--
-- Parameters : NewDelay... Returned output delay value.
-- GlchDelay.. Returned output delay for the start of a glitch.
-- NewValue... New output value.
-- CurValue... Current value of the output.
-- NewSched... Composite containing the combined absolute
-- output times from the data inputs.
-- EnSched1... Composite containing the combined absolute
-- output times from the enable input(s).
-- (for a 3_state output transitions 1->Z, Z->1)
-- EnSched0... Composite containing the combined absolute
-- output times from the enable input(s).
-- (for a 3_state output transitions 0->Z, Z->0)
--
---------------------------------------------------------------------------
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT TIME;
VARIABLE GlchDelay : OUT TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT CurValue : IN std_ulogic;
CONSTANT NewSched : IN SchedType
) IS
VARIABLE Tim, Glch : TIME;
BEGIN
CASE To_UX01(NewValue) IS
WHEN '0' => Tim := NewSched.inp0;
Glch := NewSched.Glch1;
WHEN '1' => Tim := NewSched.inp1;
Glch := NewSched.Glch0;
WHEN OTHERS => Tim := NewSched.InpX;
Glch := -1 ns;
END CASE;
IF (CurValue /= NewValue)
THEN Glch := -1 ns;
END IF;
NewDelay := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelay := Glch;
ELSE GlchDelay := Glch - NOW;
END IF; -- glch < 0 ns
END;
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT VitalTimeArray;
VARIABLE GlchDelay : OUT VitalTimeArray;
CONSTANT NewValue : IN std_logic_vector;
CONSTANT CurValue : IN std_logic_vector;
CONSTANT NewSched : IN SchedArray
) IS
VARIABLE Tim, Glch : TIME;
ALIAS NewDelayAlias : VitalTimeArray( NewDelay'LENGTH DOWNTO 1)
IS NewDelay;
ALIAS GlchDelayAlias : VitalTimeArray(GlchDelay'LENGTH DOWNTO 1)
IS GlchDelay;
ALIAS NewSchedAlias : SchedArray( NewSched'LENGTH DOWNTO 1)
IS NewSched;
ALIAS NewValueAlias : std_logic_vector ( NewValue'LENGTH DOWNTO 1 )
IS NewValue;
ALIAS CurValueAlias : std_logic_vector ( CurValue'LENGTH DOWNTO 1 )
IS CurValue;
BEGIN
FOR n IN NewDelay'LENGTH DOWNTO 1 LOOP
CASE To_UX01(NewValueAlias(n)) IS
WHEN '0' => Tim := NewSchedAlias(n).inp0;
Glch := NewSchedAlias(n).Glch1;
WHEN '1' => Tim := NewSchedAlias(n).inp1;
Glch := NewSchedAlias(n).Glch0;
WHEN OTHERS => Tim := NewSchedAlias(n).InpX;
Glch := -1 ns;
END CASE;
IF (CurValueAlias(n) /= NewValueAlias(n))
THEN Glch := -1 ns;
END IF;
NewDelayAlias(n) := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelayAlias(n) := Glch;
ELSE GlchDelayAlias(n) := Glch - NOW;
END IF; -- glch < 0 ns
END LOOP;
RETURN;
END;
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT TIME;
VARIABLE GlchDelay : OUT TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT CurValue : IN std_ulogic;
CONSTANT NewSched : IN SchedType;
CONSTANT EnSched1 : IN SchedType;
CONSTANT EnSched0 : IN SchedType
) IS
SUBTYPE v2 IS std_logic_vector(0 TO 1);
VARIABLE Tim, Glch : TIME;
BEGIN
CASE v2'(To_X01Z(CurValue) & To_X01Z(NewValue)) IS
WHEN "00" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := GlitchMinTime(NewSched.Glch1,EnSched0.Glch0);
WHEN "01" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := EnSched1.Glch0;
WHEN "0Z" => Tim := EnSched0.inp0;
Glch := NewSched.Glch1;
WHEN "0X" => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
WHEN "10" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := EnSched0.Glch0;
WHEN "11" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := GlitchMinTime(NewSched.Glch0,EnSched1.Glch0);
WHEN "1Z" => Tim := EnSched1.inp0;
Glch := NewSched.Glch0;
WHEN "1X" => Tim := Maximum (NewSched.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN "Z0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
IF NewSched.Glch0 > NOW
THEN Glch := Maximum(NewSched.Glch1,EnSched1.inp1);
ELSE Glch := 0 ns;
END IF;
WHEN "Z1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
IF NewSched.Glch1 > NOW
THEN Glch := Maximum(NewSched.Glch0,EnSched0.inp1);
ELSE Glch := 0 ns;
END IF;
WHEN "ZX" => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
WHEN "ZZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN "X0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := 0 ns;
WHEN "X1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := 0 ns;
WHEN "XZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN OTHERS => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
END CASE;
NewDelay := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelay := Glch;
ELSE GlchDelay := Glch - NOW;
END IF; -- glch < 0 ns
END;
---------------------------------------------------------------------------
-- Operators and Functions for combination (selection) of path delays
-- > These functions support selection of the "appripriate" path delay
-- dependent on the logic function.
-- > These functions only "select" from the possable output times. No
-- calculation (addition) of delays is performed.
-- > See description of 'BufPath', 'InvPath' and 'GetSchedDelay'
-- > See primitive PROCEDURE models for examples.
---------------------------------------------------------------------------
FUNCTION "not" (
CONSTANT a : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := a.inp0 ;
z.inp0 := a.inp1 ;
z.InpX := a.InpX ;
z.Glch1 := a.Glch0;
z.Glch0 := a.Glch1;
RETURN (z);
END;
FUNCTION "and" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := Maximum ( a.inp1 , b.inp1 );
z.inp0 := Minimum ( a.inp0 , b.inp0 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch1 := Maximum ( a.Glch1, b.Glch1 );
z.Glch0 := GlitchMinTime ( a.Glch0, b.Glch0 );
RETURN (z);
END;
FUNCTION "or" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp0 := Maximum ( a.inp0 , b.inp0 );
z.inp1 := Minimum ( a.inp1 , b.inp1 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch0 := Maximum ( a.Glch0, b.Glch0 );
z.Glch1 := GlitchMinTime ( a.Glch1, b.Glch1 );
RETURN (z);
END;
FUNCTION "nand" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp0 := Maximum ( a.inp1 , b.inp1 );
z.inp1 := Minimum ( a.inp0 , b.inp0 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch0 := Maximum ( a.Glch1, b.Glch1 );
z.Glch1 := GlitchMinTime ( a.Glch0, b.Glch0 );
RETURN (z);
END;
FUNCTION "nor" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := Maximum ( a.inp0 , b.inp0 );
z.inp0 := Minimum ( a.inp1 , b.inp1 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch1 := Maximum ( a.Glch0, b.Glch0 );
z.Glch0 := GlitchMinTime ( a.Glch1, b.Glch1 );
RETURN (z);
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 2-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalXOR2 (
CONSTANT ab,ai, bb,bi : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
-- z = (a AND b) NOR (a NOR b)
z.inp1 := Maximum ( Minimum (ai.inp0 , bi.inp0 ),
Minimum (ab.inp1 , bb.inp1 ) );
z.inp0 := Minimum ( Maximum (ai.inp1 , bi.inp1 ),
Maximum (ab.inp0 , bb.inp0 ) );
z.InpX := Maximum ( Maximum (ai.InpX , bi.InpX ),
Maximum (ab.InpX , bb.InpX ) );
z.Glch1 := Maximum (GlitchMinTime (ai.Glch0, bi.Glch0),
GlitchMinTime (ab.Glch1, bb.Glch1) );
z.Glch0 := GlitchMinTime ( Maximum (ai.Glch1, bi.Glch1),
Maximum (ab.Glch0, bb.Glch0) );
RETURN (z);
END;
FUNCTION VitalXNOR2 (
CONSTANT ab,ai, bb,bi : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
-- z = (a AND b) OR (a NOR b)
z.inp0 := Maximum ( Minimum (ab.inp0 , bb.inp0 ),
Minimum (ai.inp1 , bi.inp1 ) );
z.inp1 := Minimum ( Maximum (ab.inp1 , bb.inp1 ),
Maximum (ai.inp0 , bi.inp0 ) );
z.InpX := Maximum ( Maximum (ab.InpX , bb.InpX ),
Maximum (ai.InpX , bi.InpX ) );
z.Glch0 := Maximum (GlitchMinTime (ab.Glch0, bb.Glch0),
GlitchMinTime (ai.Glch1, bi.Glch1) );
z.Glch1 := GlitchMinTime ( Maximum (ab.Glch1, bb.Glch1),
Maximum (ai.Glch0, bi.Glch0) );
RETURN (z);
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 3-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalXOR3 (
CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXOR2 ( VitalXOR2 (ab,ai, bb,bi),
VitalXOR2 (ai,ab, bi,bb),
cb, ci );
END;
FUNCTION VitalXNOR3 (
CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
cb, ci );
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 4-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalXOR4 (
CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
VitalXOR2 ( cb,ci, db,di ),
VitalXOR2 ( ci,cb, di,db ) );
END;
FUNCTION VitalXNOR4 (
CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
VitalXOR2 ( cb,ci, db,di ),
VitalXOR2 ( ci,cb, di,db ) );
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for N-bit Logical gates.
-- ------------------------------------------------------------------------
-- Note: index range on datab,datai assumed to be 1 TO length.
-- This is enforced by internal only usage of this Function
FUNCTION VitalXOR (
CONSTANT DataB, DataI : IN SchedArray
) RETURN SchedType IS
CONSTANT Leng : INTEGER := DataB'LENGTH;
BEGIN
IF Leng = 2 THEN
RETURN VitalXOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) );
ELSE
RETURN VitalXOR2 ( VitalXOR ( DataB(1 TO Leng-1),
DataI(1 TO Leng-1) ),
VitalXOR ( DataI(1 TO Leng-1),
DataB(1 TO Leng-1) ),
DataB(Leng),DataI(Leng) );
END IF;
END;
-- Note: index range on datab,datai assumed to be 1 TO length.
-- This is enforced by internal only usage of this Function
FUNCTION VitalXNOR (
CONSTANT DataB, DataI : IN SchedArray
) RETURN SchedType IS
CONSTANT Leng : INTEGER := DataB'LENGTH;
BEGIN
IF Leng = 2 THEN
RETURN VitalXNOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) );
ELSE
RETURN VitalXNOR2 ( VitalXOR ( DataB(1 TO Leng-1),
DataI(1 TO Leng-1) ),
VitalXOR ( DataI(1 TO Leng-1),
DataB(1 TO Leng-1) ),
DataB(Leng),DataI(Leng) );
END IF;
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
FUNCTION VitalMUX2 (
CONSTANT d1, d0 : IN SchedType;
CONSTANT sb, SI : IN SchedType
) RETURN SchedType IS
BEGIN
RETURN (d1 AND sb) OR (d0 AND (NOT SI) );
END;
--
FUNCTION VitalMUX4 (
CONSTANT Data : IN SchedArray4;
CONSTANT sb : IN SchedArray2;
CONSTANT SI : IN SchedArray2
) RETURN SchedType IS
BEGIN
RETURN ( sb(1) AND VitalMUX2(Data(3),Data(2), sb(0), SI(0)) )
OR ( (NOT SI(1)) AND VitalMUX2(Data(1),Data(0), sb(0), SI(0)) );
END;
FUNCTION VitalMUX8 (
CONSTANT Data : IN SchedArray8;
CONSTANT sb : IN SchedArray3;
CONSTANT SI : IN SchedArray3
) RETURN SchedType IS
BEGIN
RETURN ( ( sb(2)) AND VitalMUX4 (Data(7 DOWNTO 4),
sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) )
OR ( (NOT SI(2)) AND VitalMUX4 (Data(3 DOWNTO 0),
sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) );
END;
--
FUNCTION VInterMux (
CONSTANT Data : IN SchedArray;
CONSTANT sb : IN SchedArray;
CONSTANT SI : IN SchedArray
) RETURN SchedType IS
CONSTANT sMsb : INTEGER := sb'LENGTH;
CONSTANT dMsbHigh : INTEGER := Data'LENGTH;
CONSTANT dMsbLow : INTEGER := Data'LENGTH/2;
BEGIN
IF sb'LENGTH = 1 THEN
RETURN VitalMUX2( Data(2), Data(1), sb(1), SI(1) );
ELSIF sb'LENGTH = 2 THEN
RETURN VitalMUX4( Data, sb, SI );
ELSIF sb'LENGTH = 3 THEN
RETURN VitalMUX8( Data, sb, SI );
ELSIF sb'LENGTH > 3 THEN
RETURN (( sb(sMsb)) AND VInterMux( Data(dMsbLow DOWNTO 1),
sb(sMsb-1 DOWNTO 1),
SI(sMsb-1 DOWNTO 1) ))
OR ((NOT SI(sMsb)) AND VInterMux( Data(dMsbHigh DOWNTO dMsbLow+1),
sb(sMsb-1 DOWNTO 1),
SI(sMsb-1 DOWNTO 1) ));
ELSE
RETURN (0 ns, 0 ns, 0 ns, 0 ns, 0 ns); -- dselect'LENGTH < 1
END IF;
END;
--
FUNCTION VitalMUX (
CONSTANT Data : IN SchedArray;
CONSTANT sb : IN SchedArray;
CONSTANT SI : IN SchedArray
) RETURN SchedType IS
CONSTANT msb : INTEGER := 2**sb'LENGTH;
VARIABLE lDat : SchedArray(msb DOWNTO 1);
ALIAS DataAlias : SchedArray ( Data'LENGTH DOWNTO 1 ) IS Data;
ALIAS sbAlias : SchedArray ( sb'LENGTH DOWNTO 1 ) IS sb;
ALIAS siAlias : SchedArray ( SI'LENGTH DOWNTO 1 ) IS SI;
BEGIN
IF Data'LENGTH <= msb THEN
FOR i IN Data'LENGTH DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
FOR i IN msb DOWNTO Data'LENGTH+1 LOOP
lDat(i) := DefSchedAnd;
END LOOP;
ELSE
FOR i IN msb DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
END IF;
RETURN VInterMux( lDat, sbAlias, siAlias );
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- ------------------------------------------------------------------------
FUNCTION VitalDECODER2 (
CONSTANT DataB : IN SchedType;
CONSTANT DataI : IN SchedType;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray2;
BEGIN
Result(1) := Enable AND ( DataB);
Result(0) := Enable AND (NOT DataI);
RETURN Result;
END;
FUNCTION VitalDECODER4 (
CONSTANT DataB : IN SchedArray2;
CONSTANT DataI : IN SchedArray2;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray4;
BEGIN
Result(3) := Enable AND ( DataB(1)) AND ( DataB(0));
Result(2) := Enable AND ( DataB(1)) AND (NOT DataI(0));
Result(1) := Enable AND (NOT DataI(1)) AND ( DataB(0));
Result(0) := Enable AND (NOT DataI(1)) AND (NOT DataI(0));
RETURN Result;
END;
FUNCTION VitalDECODER8 (
CONSTANT DataB : IN SchedArray3;
CONSTANT DataI : IN SchedArray3;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray8;
BEGIN
Result(7):= Enable AND ( DataB(2))AND( DataB(1))AND( DataB(0));
Result(6):= Enable AND ( DataB(2))AND( DataB(1))AND(NOT DataI(0));
Result(5):= Enable AND ( DataB(2))AND(NOT DataI(1))AND( DataB(0));
Result(4):= Enable AND ( DataB(2))AND(NOT DataI(1))AND(NOT DataI(0));
Result(3):= Enable AND (NOT DataI(2))AND( DataB(1))AND( DataB(0));
Result(2):= Enable AND (NOT DataI(2))AND( DataB(1))AND(NOT DataI(0));
Result(1):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND( DataB(0));
Result(0):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND(NOT DataI(0));
RETURN Result;
END;
FUNCTION VitalDECODER (
CONSTANT DataB : IN SchedArray;
CONSTANT DataI : IN SchedArray;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
CONSTANT DMsb : INTEGER := DataB'LENGTH - 1;
ALIAS DataBAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataB;
ALIAS DataIAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataI;
BEGIN
IF DataB'LENGTH = 1 THEN
RETURN VitalDECODER2 ( DataBAlias( 0 ),
DataIAlias( 0 ), Enable );
ELSIF DataB'LENGTH = 2 THEN
RETURN VitalDECODER4 ( DataBAlias(1 DOWNTO 0),
DataIAlias(1 DOWNTO 0), Enable );
ELSIF DataB'LENGTH = 3 THEN
RETURN VitalDECODER8 ( DataBAlias(2 DOWNTO 0),
DataIAlias(2 DOWNTO 0), Enable );
ELSIF DataB'LENGTH > 3 THEN
RETURN VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0),
DataIAlias(DMsb-1 DOWNTO 0),
Enable AND ( DataBAlias(DMsb)) )
& VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0),
DataIAlias(DMsb-1 DOWNTO 0),
Enable AND (NOT DataIAlias(DMsb)) );
ELSE
RETURN DefSchedArray2;
END IF;
END;
-------------------------------------------------------------------------------
-- PRIMITIVES
-------------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- N-bit wide Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '1';
FOR i IN Data'RANGE LOOP
Result := Result AND Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result OR Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result XOR Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '1';
FOR i IN Data'RANGE LOOP
Result := Result AND Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
--
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result OR Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
--
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result XOR Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
-- ------------------------------------------------------------------------
-- Commonly used 2-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b);
END;
--
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b);
END;
--
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b);
END;
--
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a NAND b);
END;
--
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a NOR b);
END;
--
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b));
END;
--
-- ------------------------------------------------------------------------
-- Commonly used 3-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b AND c);
END;
--
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b OR c);
END;
--
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b XOR c);
END;
--
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a AND b AND c));
END;
--
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a OR b OR c));
END;
--
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b XOR c));
END;
-- ---------------------------------------------------------------------------
-- Commonly used 4-bit Logical gates.
-- ---------------------------------------------------------------------------
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b AND c AND d);
END;
--
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b OR c OR d);
END;
--
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b XOR c XOR d);
END;
--
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a AND b AND c AND d));
END;
--
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a OR b OR c OR d));
END;
--
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b XOR c XOR d));
END;
-- ------------------------------------------------------------------------
-- Buffers
-- BUF ....... standard non-inverting buffer
-- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0')
-- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(To_UX01(Data));
END;
--
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(BufIf0_Table(Enable,Data));
END;
--
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(BufIf1_Table(Enable,Data));
END;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(To_UX01Z(Data));
END;
-- ------------------------------------------------------------------------
-- Invertors
-- INV ......... standard inverting buffer
-- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0')
-- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT Data);
END;
--
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(InvIf0_Table(Enable,Data));
END;
--
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(InvIf1_Table(Enable,Data));
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
CASE To_X01(dSelect) IS
WHEN '0' => Result := To_UX01(Data0);
WHEN '1' => Result := To_UX01(Data1);
WHEN OTHERS => Result := VitalSame( Data1, Data0 );
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Slct : std_logic_vector2;
VARIABLE Result : UX01;
BEGIN
Slct := To_X01(dSelect);
CASE Slct IS
WHEN "00" => Result := To_UX01(Data(0));
WHEN "01" => Result := To_UX01(Data(1));
WHEN "10" => Result := To_UX01(Data(2));
WHEN "11" => Result := To_UX01(Data(3));
WHEN "0X" => Result := VitalSame( Data(1), Data(0) );
WHEN "1X" => Result := VitalSame( Data(2), Data(3) );
WHEN "X0" => Result := VitalSame( Data(2), Data(0) );
WHEN "X1" => Result := VitalSame( Data(3), Data(1) );
WHEN OTHERS => Result := VitalSame( VitalSame(Data(3),Data(2)),
VitalSame(Data(1),Data(0)));
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
CASE To_X01(dSelect(2)) IS
WHEN '0' => Result := VitalMUX4( Data(3 DOWNTO 0),
dSelect(1 DOWNTO 0));
WHEN '1' => Result := VitalMUX4( Data(7 DOWNTO 4),
dSelect(1 DOWNTO 0));
WHEN OTHERS => Result := VitalSame( VitalMUX4( Data(3 DOWNTO 0),
dSelect(1 DOWNTO 0)),
VitalMUX4( Data(7 DOWNTO 4),
dSelect(1 DOWNTO 0)));
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VInterMux (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector
) RETURN std_ulogic IS
CONSTANT sMsb : INTEGER := dSelect'LENGTH;
CONSTANT dMsbHigh : INTEGER := Data'LENGTH;
CONSTANT dMsbLow : INTEGER := Data'LENGTH/2;
ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data;
ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect;
VARIABLE Result : UX01;
BEGIN
IF dSelect'LENGTH = 1 THEN
Result := VitalMUX2( DataAlias(2), DataAlias(1), dSelAlias(1) );
ELSIF dSelect'LENGTH = 2 THEN
Result := VitalMUX4( DataAlias, dSelAlias );
ELSIF dSelect'LENGTH > 2 THEN
CASE To_X01(dSelect(sMsb)) IS
WHEN '0' =>
Result := VInterMux( DataAlias(dMsbLow DOWNTO 1),
dSelAlias(sMsb-1 DOWNTO 1) );
WHEN '1' =>
Result := VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1),
dSelAlias(sMsb-1 DOWNTO 1) );
WHEN OTHERS =>
Result := VitalSame(
VInterMux( DataAlias(dMsbLow DOWNTO 1),
dSelAlias(sMsb-1 DOWNTO 1) ),
VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1),
dSelAlias(sMsb-1 DOWNTO 1) )
);
END CASE;
ELSE
Result := 'X'; -- dselect'LENGTH < 1
END IF;
RETURN Result;
END;
--
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
CONSTANT msb : INTEGER := 2**dSelect'LENGTH;
ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data;
ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect;
VARIABLE lDat : std_logic_vector(msb DOWNTO 1) := (OTHERS=>'X');
VARIABLE Result : UX01;
BEGIN
IF Data'LENGTH <= msb THEN
FOR i IN Data'LENGTH DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
ELSE
FOR i IN msb DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
END IF;
Result := VInterMux( lDat, dSelAlias );
RETURN ResultMap(Result);
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- ------------------------------------------------------------------------
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2 IS
VARIABLE Result : std_logic_vector2;
BEGIN
Result(1) := ResultMap(Enable AND ( Data));
Result(0) := ResultMap(Enable AND (NOT Data));
RETURN Result;
END;
--
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4 IS
VARIABLE Result : std_logic_vector4;
BEGIN
Result(3) := ResultMap(Enable AND ( Data(1)) AND ( Data(0)));
Result(2) := ResultMap(Enable AND ( Data(1)) AND (NOT Data(0)));
Result(1) := ResultMap(Enable AND (NOT Data(1)) AND ( Data(0)));
Result(0) := ResultMap(Enable AND (NOT Data(1)) AND (NOT Data(0)));
RETURN Result;
END;
--
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8 IS
VARIABLE Result : std_logic_vector8;
BEGIN
Result(7) := ( Data(2)) AND ( Data(1)) AND ( Data(0));
Result(6) := ( Data(2)) AND ( Data(1)) AND (NOT Data(0));
Result(5) := ( Data(2)) AND (NOT Data(1)) AND ( Data(0));
Result(4) := ( Data(2)) AND (NOT Data(1)) AND (NOT Data(0));
Result(3) := (NOT Data(2)) AND ( Data(1)) AND ( Data(0));
Result(2) := (NOT Data(2)) AND ( Data(1)) AND (NOT Data(0));
Result(1) := (NOT Data(2)) AND (NOT Data(1)) AND ( Data(0));
Result(0) := (NOT Data(2)) AND (NOT Data(1)) AND (NOT Data(0));
Result(0) := ResultMap ( Enable AND Result(0) );
Result(1) := ResultMap ( Enable AND Result(1) );
Result(2) := ResultMap ( Enable AND Result(2) );
Result(3) := ResultMap ( Enable AND Result(3) );
Result(4) := ResultMap ( Enable AND Result(4) );
Result(5) := ResultMap ( Enable AND Result(5) );
Result(6) := ResultMap ( Enable AND Result(6) );
Result(7) := ResultMap ( Enable AND Result(7) );
RETURN Result;
END;
--
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector IS
CONSTANT DMsb : INTEGER := Data'LENGTH - 1;
ALIAS DataAlias : std_logic_vector ( DMsb DOWNTO 0 ) IS Data;
BEGIN
IF Data'LENGTH = 1 THEN
RETURN VitalDECODER2 (DataAlias( 0 ), Enable, ResultMap );
ELSIF Data'LENGTH = 2 THEN
RETURN VitalDECODER4 (DataAlias(1 DOWNTO 0), Enable, ResultMap );
ELSIF Data'LENGTH = 3 THEN
RETURN VitalDECODER8 (DataAlias(2 DOWNTO 0), Enable, ResultMap );
ELSIF Data'LENGTH > 3 THEN
RETURN VitalDECODER (DataAlias(DMsb-1 DOWNTO 0),
Enable AND ( DataAlias(DMsb)), ResultMap )
& VitalDECODER (DataAlias(DMsb-1 DOWNTO 0),
Enable AND (NOT DataAlias(DMsb)), ResultMap );
ELSE RETURN "X";
END IF;
END;
-- ------------------------------------------------------------------------
-- N-bit wide Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalAND(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '1';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue AND Data(i);
new_schd := new_schd AND Data_Schd(i);
END LOOP;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '0';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue OR Data(i);
new_schd := new_schd OR Data_Schd(i);
END LOOP;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd;
ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalXOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( DataB_Schd, Data_Edge, Atpd_data_q );
InvPath ( DataI_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalXOR ( Data );
new_schd := VitalXOR ( DataB_Schd, DataI_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalNAND(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
InvPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '1';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue AND Data(i);
new_schd := new_schd AND Data_Schd(i);
END LOOP;
NewValue := NOT NewValue;
new_schd := NOT new_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalNOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
InvPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '0';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue OR Data(i);
new_schd := new_schd OR Data_Schd(i);
END LOOP;
NewValue := NOT NewValue;
new_schd := NOT new_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd;
ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalXNOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( DataB_Schd, Data_Edge, Atpd_data_q );
InvPath ( DataI_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalXNOR ( Data );
new_schd := VitalXNOR ( DataB_Schd, DataI_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
-- ------------------------------------------------------------------------
-- Commonly used 2-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b;
new_schd := a_schd AND b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b;
new_schd := a_schd OR b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a NAND b;
new_schd := a_schd NAND b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a NOR b;
new_schd := a_schd NOR b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd : SchedType;
VARIABLE ai_schd, bi_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b;
new_schd := VitalXOR2 ( ab_schd,ai_schd, bb_schd,bi_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd : SchedType;
VARIABLE ai_schd, bi_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b);
new_schd := VitalXNOR2 ( ab_schd,ai_schd, bb_schd,bi_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Commonly used 3-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
--
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b AND c;
new_schd := a_schd AND b_schd AND c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b OR c;
new_schd := a_schd OR b_schd OR c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a AND b) NAND c;
new_schd := (a_schd AND b_schd) NAND c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a OR b) NOR c;
new_schd := (a_schd OR b_schd) NOR c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b XOR c;
new_schd := VitalXOR3 ( ab_schd,ai_schd,
bb_schd,bi_schd,
cb_schd,ci_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b XOR c);
new_schd := VitalXNOR3 ( ab_schd, ai_schd,
bb_schd, bi_schd,
cb_schd, ci_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Commonly used 4-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
BufPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
BufPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b AND c AND d;
new_schd := a_schd AND b_schd AND c_schd AND d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
BufPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
BufPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b OR c OR d;
new_schd := a_schd OR b_schd OR c_schd OR d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
InvPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
InvPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a AND b) NAND (c AND d);
new_schd := (a_schd AND b_schd) NAND (c_schd AND d_Schd);
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
InvPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
InvPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a OR b) NOR (c OR d);
new_schd := (a_schd OR b_schd) NOR (c_schd OR d_Schd);
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
BufPath ( DB_Schd, InitialEdge(d), tpd_d_q );
InvPath ( di_schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
BufPath ( DB_Schd, GetEdge(d), tpd_d_q );
InvPath ( di_schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b XOR c XOR d;
new_schd := VitalXOR4 ( ab_schd,ai_schd, bb_schd,bi_schd,
cb_schd,ci_schd, DB_Schd,di_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
BufPath ( DB_Schd, InitialEdge(d), tpd_d_q );
InvPath ( di_schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
BufPath ( DB_Schd, GetEdge(d), tpd_d_q );
InvPath ( di_schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b XOR c XOR d);
new_schd := VitalXNOR4 ( ab_schd,ai_schd, bb_schd,bi_schd,
cb_schd,ci_schd, DB_Schd,di_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Buffers
-- BUF ....... standard non-inverting buffer
-- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0')
-- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_a_q = VitalZeroDelay01) THEN
LOOP
q <= ResultMap(To_UX01(a));
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := To_UX01(a); -- convert to forcing strengths
CASE EdgeType'(GetEdge(a)) IS
WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr01);
WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr10);
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
--
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalBUFIF1( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d_Schd, InitialEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d_Schd, GetEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalBUFIF1( Data, Enable );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
d_Schd, e1_Schd, e0_Schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE ne1_schd, ne0_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalBUFIF0( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d_Schd, InitialEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d_Schd, GetEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalBUFIF0( Data, Enable );
ne1_schd := NOT e1_Schd;
ne0_schd := NOT e0_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
d_Schd, ne1_schd, ne0_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
SUBTYPE v2 IS std_logic_vector(0 TO 1);
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_a_q = VitalZeroDelay01Z) THEN
LOOP
q <= ResultMap(To_UX01Z(a));
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
CASE v2'(To_X01Z(NewValue) & To_X01Z(a)) IS
WHEN "00" => Dly := tpd_a_q(tr10);
WHEN "01" => Dly := tpd_a_q(tr01);
WHEN "0Z" => Dly := tpd_a_q(tr0z);
WHEN "0X" => Dly := tpd_a_q(tr01);
WHEN "10" => Dly := tpd_a_q(tr10);
WHEN "11" => Dly := tpd_a_q(tr01);
WHEN "1Z" => Dly := tpd_a_q(tr1z);
WHEN "1X" => Dly := tpd_a_q(tr10);
WHEN "Z0" => Dly := tpd_a_q(trz0);
WHEN "Z1" => Dly := tpd_a_q(trz1);
WHEN "ZZ" => Dly := 0 ns;
WHEN "ZX" => Dly := Minimum (tpd_a_q(trz1), tpd_a_q(trz0));
WHEN "X0" => Dly := tpd_a_q(tr10);
WHEN "X1" => Dly := tpd_a_q(tr01);
WHEN "XZ" => Dly := Minimum (tpd_a_q(tr0z), tpd_a_q(tr1z));
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
NewValue := To_UX01Z(a);
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Invertors
-- INV ......... standard inverting buffer
-- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0')
-- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
IF (tpd_a_q = VitalZeroDelay01) THEN
LOOP
q <= ResultMap(NOT a);
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT a;
CASE EdgeType'(GetEdge(a)) IS
WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr10);
WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr01);
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
--
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE new_schd : SchedType;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalINVIF1( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( d_Schd, InitialEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( d_Schd, GetEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalINVIF1( Data, Enable );
new_schd := NOT d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
new_schd, e1_Schd, e0_Schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE new_schd : SchedType;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE ne1_schd, ne0_schd : SchedType := DefSchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalINVIF0( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( d_Schd, InitialEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( d_Schd, GetEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalINVIF0( Data, Enable );
ne1_schd := NOT e1_Schd;
ne0_schd := NOT e0_Schd;
new_schd := NOT d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
new_schd, ne1_schd, ne0_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE d1_Schd, d0_Schd : SchedType;
VARIABLE dSel_bSchd, dSel_iSchd : SchedType;
VARIABLE d1_Edge, d0_Edge, dSel_Edge : EdgeType;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_d1_q = VitalZeroDelay01)
AND (tpd_d0_q = VitalZeroDelay01)
AND (tpd_dsel_q = VitalZeroDelay01) ) THEN
LOOP
q <= VitalMUX2 ( d1, d0, dSel, ResultMap );
WAIT ON d1, d0, dSel;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d1_Schd, InitialEdge(d1), tpd_d1_q );
BufPath ( d0_Schd, InitialEdge(d0), tpd_d0_q );
BufPath ( dSel_bSchd, InitialEdge(dSel), tpd_dsel_q );
InvPath ( dSel_iSchd, InitialEdge(dSel), tpd_dsel_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d1_Schd, GetEdge(d1), tpd_d1_q );
BufPath ( d0_Schd, GetEdge(d0), tpd_d0_q );
BufPath ( dSel_bSchd, GetEdge(dSel), tpd_dsel_q );
InvPath ( dSel_iSchd, GetEdge(dSel), tpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX2 ( d1, d0, dSel );
new_schd := VitalMUX2 ( d1_Schd, d0_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON d1, d0, dSel;
END LOOP;
END IF;
END;
--
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray4;
VARIABLE Data_Edge : EdgeArray4;
VARIABLE dSel_Edge : EdgeArray2;
VARIABLE dSel_bSchd : SchedArray2;
VARIABLE dSel_iSchd : SchedArray2;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX4 ( Data, dSel );
new_schd := VitalMUX4 ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF; --SN
END;
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray8;
VARIABLE Data_Edge : EdgeArray8;
VARIABLE dSel_Edge : EdgeArray3;
VARIABLE dSel_bSchd : SchedArray3;
VARIABLE dSel_iSchd : SchedArray3;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX8 ( Data, dSel );
new_schd := VitalMUX8 ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF;
END;
--
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE dSel_Edge : EdgeArray(dSel'RANGE);
VARIABLE dSel_bSchd : SchedArray(dSel'RANGE);
VARIABLE dSel_iSchd : SchedArray(dSel'RANGE);
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX ( Data, dSel );
new_schd := VitalMUX ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF; --SN
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- Caution: If 'ResultMap' defines other than strength mapping, the
-- delay selection is not defined.
-- ------------------------------------------------------------------------
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : std_logic_vector2;
VARIABLE Glitch_Data : GlitchArray2;
VARIABLE new_schd : SchedArray2;
VARIABLE Dly, Glch : TimeArray2;
VARIABLE Enable_Schd : SchedType := DefSchedType;
VARIABLE Data_BSchd, Data_ISchd : SchedType;
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q = VitalZeroDelay01) AND (tpd_data_q = VitalZeroDelay01) THEN
LOOP
q <= VitalDECODER2(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( Data_BSchd, InitialEdge(Data), tpd_data_q );
InvPath ( Data_ISchd, InitialEdge(Data), tpd_data_q );
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( Data_BSchd, GetEdge(Data), tpd_data_q );
InvPath ( Data_ISchd, GetEdge(Data), tpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER2 ( Data, Enable, ResultMap );
new_schd := VitalDECODER2 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF; -- SN
END;
--
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector4;
VARIABLE Glitch_Data : GlitchArray4;
VARIABLE new_schd : SchedArray4;
VARIABLE Dly, Glch : TimeArray4;
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray2;
VARIABLE Data_BSchd, Data_ISchd : SchedArray2;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER4(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER4 ( Data, Enable, ResultMap );
new_schd := VitalDECODER4 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector8;
VARIABLE Glitch_Data : GlitchArray8;
VARIABLE new_schd : SchedArray8;
VARIABLE Dly, Glch : TimeArray8;
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray3;
VARIABLE Data_BSchd, Data_ISchd : SchedArray3;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER8 ( Data, Enable, ResultMap );
new_schd := VitalDECODER8 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector(q'RANGE);
VARIABLE Glitch_Data : GlitchDataArrayType(q'RANGE);
VARIABLE new_schd : SchedArray(q'RANGE);
VARIABLE Dly, Glch : VitalTimeArray(q'RANGE);
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_BSchd, Data_ISchd : SchedArray(Data'RANGE);
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE;
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER ( Data, Enable, ResultMap );
new_schd := VitalDECODER ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize;
VARIABLE ReturnValue : std_logic_vector(OutSize - 1 DOWNTO 0)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO InputSize - 1)
:= To_X01(DataIn);
VARIABLE Index : INTEGER;
VARIABLE Err : BOOLEAN := FALSE;
-- This needs to be done since the TableLookup arrays must be
-- ascending starting with 0
VARIABLE TableAlias : VitalTruthTableType(0 TO (TruthTable'LENGTH(1)-1),
0 TO (TruthTable'LENGTH(2)-1))
:= TruthTable;
BEGIN
-- search through each row of the truth table
IF OutSize > 0 THEN
ColLoop:
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each input element of the entry
FOR j IN 0 TO InputSize LOOP
IF (j = InputSize) THEN -- This entry matches
-- Return the Result
Index := 0;
FOR k IN TruthTable'LENGTH(2) - 1 DOWNTO InputSize LOOP
TruthOutputX01Z ( TableAlias(i,k),
ReturnValue(Index), Err);
EXIT WHEN Err;
Index := Index + 1;
END LOOP;
IF Err THEN
ReturnValue := (OTHERS => 'X');
END IF;
RETURN ReturnValue;
END IF;
IF NOT ValidTruthTableInput(TableAlias(i,j)) THEN
VitalError ( "VitalTruthTable", ErrInpSym,
To_TruthChar(TableAlias(i,j)) );
EXIT ColLoop;
END IF;
EXIT RowLoop WHEN NOT ( TruthTableMatch( DataInAlias(j),
TableAlias(i, j)));
END LOOP RowLoop;
END LOOP ColLoop;
ELSE
VitalError ( "VitalTruthTable", ErrTabWidSml );
END IF;
RETURN ReturnValue;
END VitalTruthTable;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize;
VARIABLE TempResult : std_logic_vector(OutSize - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
IF (OutSize > 0) THEN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF ( 1 > OutSize) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF ( 1 < OutSize) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
RETURN (TempResult(0));
ELSE
VitalError ( "VitalTruthTable", ErrTabWidSml );
RETURN 'X';
END IF;
END VitalTruthTable;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) IS
CONSTANT ResLeng : INTEGER := Result'LENGTH;
CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH;
CONSTANT FinalResLen : INTEGER := Minimum(ActResLen, ResLeng);
VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF (ResLeng > ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF (ResLeng < ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
TempResult(FinalResLen-1 DOWNTO 0) := TempResult(FinalResLen-1 DOWNTO 0);
Result <= TempResult;
END VitalTruthTable;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) IS
CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH;
VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF ( 1 > ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF ( 1 < ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
IF (ActResLen > 0) THEN
Result <= TempResult(0);
END IF;
END VitalTruthTable;
-- ------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER
:= StateTable'LENGTH(2) - InputSize - NumStates;
CONSTANT ResLeng : INTEGER := Result'LENGTH;
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1)
:= To_X01(DataIn);
VARIABLE PrevDataAlias : std_logic_vector(0 TO PreviousDataIn'LENGTH-1)
:= To_X01(PreviousDataIn);
VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1)
:= To_X01(Result);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (PreviousDataIn'LENGTH < DataIn'LENGTH) THEN
VitalError ( "VitalStateTable", ErrVctLng, "PreviousDataIn<DataIn");
ResultAlias := (OTHERS => 'X');
Result := ResultAlias;
ELSIF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
ResultAlias := (OTHERS => 'X');
Result := ResultAlias;
ELSE
IF (ResLeng > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF (ResLeng < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevDataAlias, NumStates,
ResultAlias);
ResultAlias := (OTHERS => 'X');
ResultAlias ( Maximum(0, ResLeng - OutSize) TO ResLeng - 1)
:= ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1);
Result := ResultAlias;
PrevDataAlias(0 TO InputSize - 1) := DataInAlias;
PreviousDataIn := PrevDataAlias;
END IF;
END VitalStateTable;
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic; -- states
VARIABLE PreviousDataIn : INOUT std_logic_vector; -- previous inputs and states
CONSTANT StateTable : IN VitalStateTableType; -- User's StateTable data
CONSTANT DataIn : IN std_logic_vector -- Inputs
) IS
VARIABLE ResultAlias : std_logic_vector(0 TO 0);
BEGIN
ResultAlias(0) := Result;
VitalStateTable ( StateTable => StateTable,
DataIn => DataIn,
NumStates => 1,
Result => ResultAlias,
PreviousDataIn => PreviousDataIn
);
Result := ResultAlias(0);
END VitalStateTable;
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER
:= StateTable'LENGTH(2) - InputSize - NumStates;
CONSTANT ResLeng : INTEGER := Result'LENGTH;
VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1);
VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
ResultAlias := (OTHERS => 'X');
Result <= ResultAlias;
ELSE
IF (ResLeng > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF (ResLeng < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
LOOP
DataInAlias := To_X01(DataIn);
ResultAlias := To_X01(Result);
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevData, NumStates,
ResultAlias);
ResultAlias := (OTHERS => 'X');
ResultAlias(Maximum(0, ResLeng - OutSize) TO ResLeng-1)
:= ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1);
Result <= ResultAlias;
PrevData := DataInAlias;
WAIT ON DataIn;
END LOOP;
END IF;
END VitalStateTable;
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := StateTable'LENGTH(2) - InputSize-1;
VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1);
VARIABLE ResultAlias : std_logic_vector(0 TO 0);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
Result <= 'X';
ELSE
IF ( 1 > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF ( 1 < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
LOOP
ResultAlias(0) := To_X01(Result);
DataInAlias := To_X01(DataIn);
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevData, 1, ResultAlias);
Result <= ExpResult(OutSize-1);
PrevData := DataInAlias;
WAIT ON DataIn;
END LOOP;
END IF;
END VitalStateTable;
-- ------------------------------------------------------------------------
-- std_logic resolution primitive
-- ------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
CONSTANT Data : IN std_logic_vector
) IS
VARIABLE uData : std_ulogic_vector(Data'RANGE);
BEGIN
FOR i IN Data'RANGE LOOP
uData(i) := Data(i);
END LOOP;
q <= resolved(uData);
END;
END VITAL_Primitives;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2165.vhd | 4 | 2047 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2165.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02165ent IS
END c07s02b04x00p22n01i02165ent;
ARCHITECTURE c07s02b04x00p22n01i02165arch OF c07s02b04x00p22n01i02165ent IS
TYPE time_v is array (integer range <>) of time;
SUBTYPE time_2 is time_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : time_2;
variable l_operand : time := 78 ns ;
variable r_operand : time := 23 ns ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result = ( 78 ns, 23 ns ))
report "***PASSED TEST: c07s02b04x00p22n01i02165"
severity NOTE;
assert (result = ( 78 ns, 23 ns ))
report "***FAILED TEST: c07s02b04x00p22n01i02165 - Concatenation of element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02165arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/mul_561.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_561 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_561;
architecture augh of mul_561 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1272.vhd | 4 | 1627 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1272.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p02n01i01272ent IS
END c08s04b00x00p02n01i01272ent;
ARCHITECTURE c08s04b00x00p02n01i01272arch OF c08s04b00x00p02n01i01272ent IS
signal T1 : integer;
BEGIN
TESTING: PROCESS
BEGIN
T1 <= 1 after 10 ns transport;
assert FALSE
report "***FAILED TEST: c08s04b00x00p02n01i01272 - Reserved word 'transport' is out of place"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p02n01i01272arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc366.vhd | 4 | 2021 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc366.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n01i00366ent IS
END c03s02b01x01p03n01i00366ent;
ARCHITECTURE c03s02b01x01p03n01i00366arch OF c03s02b01x01p03n01i00366ent IS
type MVL is ('0', '1', 'Z') ;
type tribit is array (natural range <>) of MVL;
subtype word is tribit (0 to 16); -- Success_here
BEGIN
TESTING: PROCESS
variable k : word;
BEGIN
k(0) := '0';
k(16) := 'Z';
assert NOT (k(0)='0' and k(16)='Z')
report "***PASSED TEST: c03s02b01x01p03n01i00366"
severity NOTE;
assert (k(0)='0' and k(16)='Z')
report "***FAILED TEST: c03s02b01x01p03n01i00366 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n01i00366arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket65/bug1.vhdl | 3 | 476 | entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Error
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2592.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2592.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02592ent IS
END c13s03b01x00p02n01i02592ent;
ARCHITECTURE c13s03b01x00p02n01i02592arch OF c13s03b01x00p02n01i02592ent IS
BEGIN
TESTING: PROCESS
variable k= : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02592 - Identifier can not end with '='."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02592arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc1148.vhd | 4 | 1823 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1148.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p07n01i01148ent IS
END c06s05b00x00p07n01i01148ent;
ARCHITECTURE c06s05b00x00p07n01i01148arch OF c06s05b00x00p07n01i01148ent IS
type A is array (10 downto 1) of integer;
BEGIN
TESTING: PROCESS
variable var : A := (66,66,others=>66);
BEGIN
wait for 5 ns;
assert NOT( var(1 downto 1) = 66 )
report "***PASSED TEST: c06s05b00x00p07n01i01148"
severity NOTE;
assert ( var(1 downto 1) = 66 )
report "***FAILED TEST: c06s05b00x00p07n01i01148 - A(N downto N) should be a slice that contains one element."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p07n01i01148arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst.vhd | 4 | 1076 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtst.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity dlx_test is
end entity dlx_test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd | 4 | 1391 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity full_adder is
port ( a, b, c_in : bit; s, c_out : out bit );
end entity full_adder;
architecture truth_table of full_adder is
begin
with bit_vector'(a, b, c_in) select
(c_out, s) <= bit_vector'("00") when "000",
bit_vector'("01") when "001",
bit_vector'("01") when "010",
bit_vector'("10") when "011",
bit_vector'("01") when "100",
bit_vector'("10") when "101",
bit_vector'("10") when "110",
bit_vector'("11") when "111";
end architecture truth_table;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_12.vhd | 4 | 2085 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity DRAM_4M_by_4 is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM_4M_by_4;
architecture chip_function of DRAM_4M_by_4 is
begin
d <= (others => 'Z');
end architecture chip_function;
-- code from book
library chip_lib; use chip_lib.all;
configuration down_to_chips of memory_board is
for chip_level
for bank_array
for nibble_array
for a_DRAM : DRAM
use entity DRAM_4M_by_4(chip_function);
end for;
end for;
end for;
-- . . . -- configurations of other component instances
end for;
end configuration down_to_chips;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_05.vhd | 4 | 1567 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_05.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity cos is
port ( theta : in real; result : out real );
end entity cos;
architecture series of cos is
begin
summation : process (theta) is
variable sum, term : real;
variable n : natural;
begin
sum := 1.0;
term := 1.0;
n := 0;
while abs term > abs (sum / 1.0E6) loop
n := n + 2;
term := (-term) * theta**2 / real(((n-1) * n));
sum := sum + term;
end loop;
result <= sum;
end process summation;
end architecture series;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd | 4 | 1437 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.resolve.all;
-- code from book (in text)
entity tri_state_reg is
port ( d : in resolved_byte;
q : out resolved_byte bus;
clock, out_enable : in bit );
end entity tri_state_reg;
-- end code from book
-- code from book
architecture behavioral of tri_state_reg is
begin
reg_behavior : process (d, clock, out_enable) is
variable stored_byte : byte;
begin
if clock'event and clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
end process reg_behavior;
end architecture behavioral;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2511.vhd | 4 | 1888 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2511.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n03i02511ent IS
END c07s03b04x00p03n03i02511ent;
ARCHITECTURE c07s03b04x00p03n03i02511arch OF c07s03b04x00p03n03i02511ent IS
BEGIN
TESTING: PROCESS
function f1 return integer is
begin
return 2;
end;
variable k : integer := 0;
BEGIN
k := integer'(f1/f1);
assert NOT( k=1 )
report "***PASSED TEST: c07s03b04x00p03n03i02511"
severity NOTE;
assert ( k=1 )
report "***FAILED TEST: c07s03b04x00p03n03i02511 - The evaluation of a qualified expression evaluates the operand and checks that its value belongs to the subtype denoted by the type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n03i02511arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2187.vhd | 4 | 3954 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2187.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02187ent IS
END c07s02b05x00p01n01i02187ent;
ARCHITECTURE c07s02b05x00p01n01i02187arch OF c07s02b05x00p01n01i02187ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable INTV1 : INTEGER := 0;
variable INTV2 : INTEGER := 0;
variable TIMEV1 : TIME := 1 ns;
variable TIMEV2 : TIME := 1 ns;
variable REALV1 : REAL := 0.0;
variable REALV2 : REAL := 0.0;
BEGIN
-- Test negation of simple integers.
INTV1 := 14;
assert (-INTV1 = -14)
report "Negation of simple integers does not work.";
INTV2 := INTEGER'HIGH;
assert (-INTV2 = -INTEGER'HIGH)
report "Negation of simple integers does not work.";
-- Test identity of simple integers.
assert (+14 = 14)
report "Identity of simple integers does not work.";
-- Test negation of "TIME".
TIMEV1 := 1 ns;
assert (-TIMEV1 = -1 ns)
report "Negation of TIME values does not work.";
TIMEV2 := TIME'HIGH;
assert (-TIMEV2 = -TIME'HIGH)
report "Negation of TIME values does not work.";
-- Test identify of "TIME".
assert (+14 ps = 14 ps)
report "Identity of TIME values does not work.";
-- Test negation of simple floating point numbers.
REALV1 := 14.0;
assert (-REALV1 = -14.0)
report "Negation of simple integers does not work.";
REALV2 := REAL'HIGH;
assert (-REALV2 = -REAL'HIGH)
report "Negation of simple integers does not work.";
-- Test identity of simple floating point numbers.
assert (+14.0 = 14.0)
report "Identity of simple integers does not work.";
wait for 5 fs;
assert NOT( (-INTV1 = -14) and
(-INTV2 = -INTEGER'HIGH) and
(+14 = 14) and
(-TIMEV1 = -1 ns) and
(-TIMEV2 = -TIME'HIGH) and
(+14 ps = 14 ps) and
(-REALV1 = -14.0) and
(-REALV2 = -REAL'HIGH) and
(+14.0 = 14.0) )
report "***PASSED TEST: c07s02b05x00p01n01i02187"
severity NOTE;
assert ( (-INTV1 = -14) and
(-INTV2 = -INTEGER'HIGH) and
(+14 = 14) and
(-TIMEV1 = -1 ns) and
(-TIMEV2 = -TIME'HIGH) and
(+14 ps = 14 ps) and
(-REALV1 = -14.0) and
(-REALV2 = -REAL'HIGH) and
(+14.0 = 14.0) )
report "***FAILED TEST: c07s02b05x00p01n01i02187 - Identity and nefation function did not work correctly for all numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02187arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue209/util.vhdl | 2 | 91 | package Util is
type integer_list_t is array (natural range <>) of integer;
end package;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2706.vhd | 4 | 1657 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2706.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p06n02i02706ent IS
END c13s04b01x00p06n02i02706ent;
ARCHITECTURE c13s04b01x00p06n02i02706arch OF c13s04b01x00p06n02i02706ent IS
BEGIN
TESTING: PROCESS
variable total_time : integer;
BEGIN
total_time := 123234e-3; -- failure_here
assert FALSE
report "***FAILED TEST: c13s04b01x00p06n02i02706 - An integer literal may not have a negative exponent."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p06n02i02706arch;
| gpl-2.0 |
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