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db-electronics/NESMappers | MMC1/src/MMC1.vhd | 1 | 10556 |
--Signal types are listed in parenthesis:
--
--(r) this line goes to the ROM only.
--(s) this line is Shared between the ROM, MMC/chip, and Nintendo
--(n) this line connects to the NES cart edge only, and not the ROM
--(w) this line connects to the WRAM only and nowhere else
--
--
--MMC1 Chip: (24 pin shrink-DIP)
------------
--Comes in several varieties: 'MMC1', 'MMC1A', and 'MMC1B2'
--
-- .---\/---.
-- PRG A14 (r) - |01 24| - +5V
-- PRG A15 (r) - |02 23| - M2
-- PRG A16 (r) - |03 22| - PRG A13 (s)
-- PRG A17 (r) - |04 21| - PRG A14 (n)
-- PRG /CE (r) - |05 20| - PRG /CE (n)
-- WRAM CE (w) - |06 19| - PRG D7 (s)
-- CHR A12 (r) - |07 18| - PRG D0 (s)
-- CHR A13 (r) - |08 17| - PRG R/W
-- CHR A14 (r) - |09 16| - CIRAM A10 (n)
-- CHR A15 (r) - |10 15| - CHR A12 (n)
-- CHR A16 (r) or WRAM /CE (w) - |11 14| - CHR A11 (s)
-- GND - |12 13| - CHR A10 (s)
-- `--------'
--
-- MMC1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library altera;
use altera.altera_primitives_components.all;
entity MMC1 is
port (
--reset generator (if required)
--note there are ports specified here which are not required
--for MMC1, this is because the PCB will support other mappers as
--well
nRST_p : in std_logic;
--input from NES
CPUDATA_p : in std_logic_vector(7 downto 0);
CPURnW_p : in std_logic;
nROMSEL_p : in std_logic;
CPUA14_p : in std_logic;
CPUA13_p : in std_logic;
CPUA0_p : in std_logic;
nPPUA13_p : in std_logic;
PPUA13_p : in std_logic;
PPUA12_p : in std_logic;
PPUA11_p : in std_logic;
PPUA10_p : in std_logic;
nPPURD_p : in std_logic;
nPPUWR_p : in std_logic;
M2_p : in std_logic;
CLK_p : in std_logic;
--output to Program ROM / WRAM
PRGA18_p : out std_logic;
PRGA17_p : out std_logic;
PRGA16_p : out std_logic;
PRGA15_p : out std_logic;
PRGA14_p : out std_logic;
PRGA13_p : out std_logic;
nPRGCE_p : out std_logic;
nWRAMCE_p : out std_logic;
--output to Character ROM
CHRA17_p : out std_logic;
CHRA16_p : out std_logic;
CHRA15_p : out std_logic;
CHRA14_p : out std_logic;
CHRA13_p : out std_logic;
CHRA12_p : out std_logic;
CHRA11_p : out std_logic;
CHRA10_p : out std_logic;
--output to NES
nIRQ_p : out std_logic;
nCIRAMCE_p : out std_logic;
CIRAMA10_p : out std_logic
);
end entity;
architecture MMC1_a of MMC1 is
signal RomAddr17to14_s : std_logic_vector(3 downto 0);
signal ChrAddr16to12_s : std_logic_vector(4 downto 0);
signal cpuA15_s : std_logic;
signal MMCReg0_s : std_logic_vector(4 downto 0);
signal MMCReg1_s : std_logic_vector(4 downto 0);
signal MMCReg2_s : std_logic_vector(4 downto 0);
signal MMCReg3_s : std_logic_vector(4 downto 0);
signal TempReg_s : std_logic_vector(4 downto 0);
signal CHRMirr_s : std_logic_vector(1 downto 0);
--state machine for serial writes to registers
signal resetState : std_logic;
type state_type is (s0,s1,s2,s3,s4);
signal current_s,next_s : state_type;
signal cpuAddr15to13_s : std_logic_vector(2 downto 0);
begin
--no IRQ in MMC1
nIRQ_p <= 'Z';
--CIRAM always enabled
nCIRAMCE_p <= nPPUA13_p;
--determine A15
cpuA15_s <= '0' when (M2_p = '1' and nROMSEL_p = '0') else '1';
--group higher addresses for easier reading
cpuAddr15to13_s <= cpuA15_s & CPUA14_p & CPUA13_p;
--**************************************************************
--WRAM
--CPU $6000-$7FFF: 8 KB PRG RAM bank, fixed on all boards but SOROM and SXROM
--M2 is high when address is valid
--0b0110 -> 0b0111
nWRAMCE_p <= '0' when (M2_p = '1' and cpuAddr15to13_s = "011" and MMCReg3_s(4) = '0') else '1';
--**************************************************************
--Mirroring
--To configure a cartridge board for horizontal mirroring, connect PPU A11 to CIRAM A10
--To configure a cartridge board for vertical mirroring, connect PPU A10 to CIRAM A10
--00b - 1-screen mirroring (nametable 0)
--01b - 1-screen mirroring (nametable 1)
--10b - Vert. mirroring
--11b - Horiz. mirroring
CHRMirr_s <= MMCReg0_s(1 downto 0);
CIRAMA10_p <= '0' when CHRMirr_s = "00" else
'1' when CHRMirr_s = "01" else
PPUA10_p when CHRMirr_s = "10" else
PPUA11_p when CHRMirr_s = "11" else
'0';
--**************************************************************
--CHR ROM banking
CHRA10_p <= PPUA10_p;
CHRA11_p <= PPUA11_p;
CHRA12_p <= ChrAddr16to12_s(0);
CHRA13_p <= ChrAddr16to12_s(1);
CHRA14_p <= ChrAddr16to12_s(2);
CHRA15_p <= ChrAddr16to12_s(3);
CHRA16_p <= ChrAddr16to12_s(4);
CHRA17_p <= '0';
CHRBanking : process (PPUA13_p, PPUA12_p)
begin
--check bank size
if (MMCReg0_s(4) = '0') then
--0 - Single 8K bank in CHR space.
--8K bank mode, this selects a full 8K bank at 0000h on the PPU space.
ChrAddr16to12_s <= MMCReg1_s(4 downto 1) & PPUA12_p;
else
--1 - Two 4K banks in CHR space.
--4K bank mode, this selects a 4K bank at 0000h on the PPU space.
if (PPUA12_p = '0') then
ChrAddr16to12_s <= MMCReg1_s(4 downto 0);
else
ChrAddr16to12_s <= MMCReg2_s(4 downto 0);
end if;
end if;
end process;
--**************************************************************
--PRG ROM banking
nPRGCE_p <= nROMSEL_p;
PRGA13_p <= CPUA13_p;
PRGA14_p <= RomAddr17to14_s(0);
PRGA15_p <= RomAddr17to14_s(1);
PRGA16_p <= RomAddr17to14_s(2);
PRGA17_p <= RomAddr17to14_s(3);
PRGA18_p <= '0';
PRGBanking : process (nROMSEL_p, CPUA14_p)
begin
--check bank size
if (MMCReg0_s(3) = '1') then
--16K mode, this selects a 16K bank in either 8000-BFFFh
--or C000-FFFFh depending on the state of the "H" bit in register 0.
--check which bank is swappable
if (MMCReg0_s(2) = '1') then
--1 - Bank C000-FFFFh is fixed, while 8000-FFFFh is swappable. (power-on default)
--fix last bank at $C000 and switch 16 KB bank at $8000
if (CPUA14_p = '0') then --first bank
RomAddr17to14_s <= MMCReg3_s(3 downto 0);
else --last bank
RomAddr17to14_s <= "1111";
end if;
else
--0 - Bank 8000-BFFFh is fixed, while C000-FFFFh is swappable
--fix first bank at $8000 and switch 16 KB bank at $C000;
if (CPUA14_p = '1') then --last bank
RomAddr17to14_s <= MMCReg3_s(3 downto 0);
else --first bank
RomAddr17to14_s <= "0000";
end if;
end if;
else
--32K mode, this selects a full 32K bank in the PRG space.
--Only the upper 3 bits are used then.
RomAddr17to14_s(3 downto 0) <= MMCReg3_s(3 downto 1) & CPUA14_p;
end if;
end process;
--write to mapper registers state machine
--use A14 and A13 to determine the register being written to
--The first bit in is the LSB, while the last bit in is the MSB.
process (nROMSEL_p, CPURnW_p)
begin
if (falling_edge(CPURnW_p)) then
if (nROMSEL_p = '0') then
current_s <= next_s; --state change.
end if;
end if;
end process;
process (current_s, CPUDATA_p, nROMSEL_p)
begin
if (rising_edge(nROMSEL_p)) then
if (CPURnW_p = '0') then
case current_s is
when s0 =>
if (CPUDATA_p(7) = '1') then
next_s <= s0;
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s <= "01100";
when "01" =>
MMCReg1_s <= "00000";
when "10" =>
MMCReg2_s <= "00000";
when "11" =>
MMCReg3_s <= "00000";
end case;
else
tempReg_s(3 downto 0) <= tempReg_s(4 downto 1);
tempReg_s(4) <= CPUDATA_p(0);
next_s <= s1;
end if;
when s1 =>
if (CPUDATA_p(7) = '1') then
next_s <= s0;
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s <= "01100";
when "01" =>
MMCReg1_s <= "00000";
when "10" =>
MMCReg2_s <= "00000";
when "11" =>
MMCReg3_s <= "00000";
end case;
else
tempReg_s(3 downto 0) <= tempReg_s(4 downto 1);
tempReg_s(4) <= CPUDATA_p(0);
next_s <= s2;
end if;
when s2 =>
if (CPUDATA_p(7) = '1') then
next_s <= s0;
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s <= "01100";
when "01" =>
MMCReg1_s <= "00000";
when "10" =>
MMCReg2_s <= "00000";
when "11" =>
MMCReg3_s <= "00000";
end case;
else
tempReg_s(3 downto 0) <= tempReg_s(4 downto 1);
tempReg_s(4) <= CPUDATA_p(0);
next_s <= s3;
end if;
when s3 =>
if (CPUDATA_p(7) = '1') then
next_s <= s0;
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s <= "01100";
when "01" =>
MMCReg1_s <= "00000";
when "10" =>
MMCReg2_s <= "00000";
when "11" =>
MMCReg3_s <= "00000";
end case;
else
tempReg_s(3 downto 0) <= tempReg_s(4 downto 1);
tempReg_s(4) <= CPUDATA_p(0);
next_s <= s4;
end if;
when s4 =>
if (CPUDATA_p(7) = '1') then
next_s <= s0;
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s <= "01100";
when "01" =>
MMCReg1_s <= "00000";
when "10" =>
MMCReg2_s <= "00000";
when "11" =>
MMCReg3_s <= "00000";
end case;
else
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s(3 downto 0) <= tempReg_s(4 downto 1);
MMCReg0_s(4) <= CPUDATA_p(0);
when "01" =>
MMCReg1_s(3 downto 0) <= tempReg_s(4 downto 1);
MMCReg1_s(4) <= CPUDATA_p(0);
when "10" =>
MMCReg2_s(3 downto 0) <= tempReg_s(4 downto 1);
MMCReg2_s(4) <= CPUDATA_p(0);
when "11" =>
MMCReg3_s(3 downto 0) <= tempReg_s(4 downto 1);
MMCReg3_s(4) <= CPUDATA_p(0);
end case;
next_s <= s0;
end if;
when others =>
next_s <= s0;
end case;
end if;
end if;
end process;
end MMC1_a; | gpl-2.0 |
m-novikov/ctags | Units/review-needed.r/test.vhd.t/input.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
artic92/sistemi-embedded-task2 | src/integration_task/tb_integrazione_task.vhd | 1 | 9687 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Scognamiglio, Riccio, Sorrentino
--
-- Create Date: 17.07.2017 16:56:47
-- Design Name:
-- Module Name: tb_integrazione_task - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_integrazione_task is
end tb_integrazione_task;
architecture Behavioral of tb_integrazione_task is
component integrazione_task is
Generic ( campione : natural := 20460;
doppler : natural := 11;
satellite : natural := 10);
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
poff_pinc : in STD_LOGIC_VECTOR (47 downto 0);
dds_out : out STD_LOGIC_VECTOR (31 downto 0); --DA TOGLIERE
dds_done : out STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC;
fft1_in : in STD_LOGIC_VECTOR(31 downto 0);
fft1_ready_out : out STD_LOGIC;
fft1_valid_in : in STD_LOGIC;
ifft_out : out STD_LOGIC_VECTOR (31 downto 0); --DA TOGLIERE
fft1_out : out STD_LOGIC_VECTOR (31 downto 0); --DA TOGLIERE
fft2_out : out STD_LOGIC_VECTOR (31 downto 0); --DA TOGLIERE
pos_campione : out STD_LOGIC_VECTOR (natural(ceil(log2(real(campione))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR (natural(ceil(log2(real(doppler))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR (natural(ceil(log2(real(satellite))))-1 downto 0);
sample_max : out STD_LOGIC_VECTOR (31 downto 0);
max : out STD_LOGIC_VECTOR (31 downto 0));
end component integrazione_task;
--!Constants
constant campione : natural:= 8;
constant doppler : natural:= 11;
constant satellite : natural:= 10;
constant clock_period : time := 100 ns;
--!Signal
signal clock : std_logic := '0';
signal reset_n : std_logic := '0';
signal valid_in : std_logic := '0';
signal valid_out : std_logic := '0';
signal ready_in : std_logic := '0';
signal ready_out : std_logic := '0';
signal dds_done : std_logic := '0';
signal fft1_ready_out : std_logic := '0';
signal fft1_valid_in : std_logic := '0';
signal fft1_in : std_logic_vector(31 downto 0) := (others => '0');
signal ifft_out : std_logic_vector(31 downto 0) := (others => '0');
signal poff_pinc : std_logic_vector(47 downto 0) := (others => '0');
signal dds_out : std_logic_vector(31 downto 0) := (others => '0');
signal fft1_out : std_logic_vector(31 downto 0) := (others => '0');
signal fft2_out : std_logic_vector(31 downto 0) := (others => '0');
signal sample_max : std_logic_vector(31 downto 0) := (others => '0');
signal max : std_logic_vector(31 downto 0) := (others => '0');
signal pos_campione : std_logic_vector(natural(ceil(log2(real(campione))))-1 downto 0) := (others => '0');
signal pos_doppler : std_logic_vector(natural(ceil(log2(real(doppler))))-1 downto 0) := (others => '0');
signal pos_satellite : std_logic_vector(natural(ceil(log2(real(satellite))))-1 downto 0) := (others => '0');
--SEGNALI PER LA SCRITTURA SUL FILE
signal file_sig1_out : bit_vector(31 downto 0);
signal file_sig2_out : bit_vector(31 downto 0);
signal file_ifft_out : bit_vector(31 downto 0);
signal linenumber : integer:= 1;
signal endoffile : bit := '0';
signal fft1_out_sig : std_logic_vector(31 downto 0) := (others => '0');
signal fft2_out_sig : std_logic_vector(31 downto 0) := (others => '0');
signal ifft_out_sig : std_logic_vector(31 downto 0) := (others => '0');
begin
ifft_out <= ifft_out_sig;
fft1_out <= fft1_out_sig;
fft2_out <= fft2_out_sig;
uut: integrazione_task
Generic map ( campione => campione,
doppler => doppler,
satellite => satellite )
Port map ( clock => clock,
reset_n => reset_n,
poff_pinc => poff_pinc,
valid_in => valid_in,
ready_in => ready_in,
valid_out => valid_out,
ready_out => ready_out,
fft1_in => fft1_in,
fft1_ready_out => fft1_ready_out,
fft1_valid_in => fft1_valid_in,
dds_out => dds_out,
dds_done => dds_done,
fft1_out => fft1_out_sig,
fft2_out => fft2_out_sig,
ifft_out => ifft_out_sig,
pos_campione => pos_campione,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
sample_max => sample_max,
max => max);
clock_process: process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
fft1_input_process: process(clock,fft1_ready_out)
begin
if(rising_edge(clock))then
if(fft1_ready_out = '1')then
fft1_in <= fft1_in + 1;
fft1_valid_in <= '1';
else
fft1_valid_in <= '0';
end if;
end if;
end process;
stimoli: process
begin
wait for clock_period*10;
reset_n <= '1';
ready_in <= '0';
for i in 0 to satellite-1 loop
--!PRIMA DOPPLER
valid_in <= '1';
poff_pinc <= x"A00000FFF597";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!SECONDA DOPPLER
valid_in <= '1';
poff_pinc <= x"500000FFF797";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!TERZA DOPPLER
valid_in <= '1';
poff_pinc <= x"000000FFF998";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!QUARTA DOPPLER
valid_in <= '1';
poff_pinc <= x"B00000FFFB98";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!QUINTA DOPPLER
valid_in <= '1';
poff_pinc <= x"600000FFFD99";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!SESTA DOPPLER
valid_in <= '1';
poff_pinc <= x"100000FFFF99";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!SETTIMA DOPPLER
valid_in <= '1';
poff_pinc <= x"C0000000019A";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!OTTAVA DOPPLER
valid_in <= '1';
poff_pinc <= x"70000000039B";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!NONA DOPPLER
valid_in <= '1';
poff_pinc <= x"20000000059B";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!DECIMA DOPPLER
valid_in <= '1';
poff_pinc <= x"D0000000079C";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!UNDICESIMA DOPPLER
valid_in <= '1';
poff_pinc <= x"80000000099C";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
end loop;
wait;
end process;
--SCRITTURA SUL FILE
file_sig1_out <= to_bitvector(fft1_out_sig);
file_sig2_out <= to_bitvector(fft2_out_sig);
file_ifft_out <= to_bitvector(ifft_out_sig);
--write process
writing : process
file outfilesig1 : text is out "fft1_out.txt";
file outfilesig2 : text is out "fft2_out.txt";
file outfileifft : text is out "ifft_out.txt";
variable outlinesig1 : line;
variable outlinesig2 : line;
variable outlineifft : line;
begin
wait until falling_edge(clock);
if(endoffile='0') then --if the file end is not reached.
--write(linenumber,value(real type),justified(side),field(width),digits(natural));
write(outlinesig1,file_sig1_out,right,32);
writeline(outfilesig1, outlinesig1);
write(outlinesig2,file_sig2_out,right,32);
writeline(outfilesig2, outlinesig2);
write(outlineifft,file_ifft_out,right,32);
writeline(outfileifft, outlineifft);
linenumber <= linenumber + 1;
end if;
end process writing;
end Behavioral;
| gpl-2.0 |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/d_edge_triggered.vhd | 1 | 1342 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:16:54 11/06/2015
-- Design Name:
-- Module Name: d_edge_triggered - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity d_edge_triggered is
generic (delay : time := 0 ns);
Port (data_in : in STD_LOGIC;
reset_n : in STD_LOGIC;
clock : in STD_LOGIC;
data_out : out STD_LOGIC);
end d_edge_triggered;
architecture Behavioral of d_edge_triggered is
begin
process(clock, reset_n, data_in)
begin
-- Reset asincrono
if (reset_n = '0') then
data_out <= '0' after delay;
--elsif (clk = '1' and clock'event) then
elsif (rising_edge(clock)) then
data_out <= data_in after delay;
end if;
end process;
end Behavioral;
| gpl-2.0 |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/tb_wrapper_complex_abs_esaustivo.vhd | 1 | 5476 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.07.2017 17:24:32
-- Design Name:
-- Module Name: tb_wrapper_complex_abs_esaustivo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.math_real.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_wrapper_complex_abs_esaustivo is
end tb_wrapper_complex_abs_esaustivo;
architecture Behavioral of tb_wrapper_complex_abs_esaustivo is
component wrapper_complex_abs is
Generic ( complex_width : natural := 32 );
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
complex_value : in STD_LOGIC_VECTOR (complex_width-1 downto 0);
complex_value_out :out STD_LOGIC_VECTOR(complex_width-1 downto 0);
abs_value : out STD_LOGIC_VECTOR (complex_width-1 downto 0);
valid_out : out STD_LOGIC;
valid_in : in STD_LOGIC;
ready_out : out STD_LOGIC;
ready_in : in STD_LOGIC);
end component wrapper_complex_abs;
--Constants
constant clock_period : time := 10 ns;
constant complex_width : natural := 32;
constant num_cicli : natural := 2 ** (complex_width-1)-1;
--constant num_cicli : natural := 10;
--Inputs
signal clock : std_logic := '0';
signal reset_n : std_logic := '1';
signal complex_value : std_logic_vector(complex_width-1 downto 0) := (others => '0');
signal valid_in : std_logic := '0';
signal ready_in : std_logic := '0';
--Outputs
signal abs_value : std_logic_vector(complex_width-1 downto 0);
signal valid_out: std_logic := '0';
signal ready_out : std_logic := '0';
signal complex_value_out : STD_LOGIC_VECTOR(complex_width-1 downto 0);
begin
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
uut : wrapper_complex_abs
port map(
clock => clock,
reset_n => reset_n,
complex_value => complex_value,
complex_value_out => complex_value_out,
abs_value => abs_value,
valid_out => valid_out,
valid_in => valid_in,
ready_out => ready_out,
ready_in => ready_in);
--Questo test incrementa ad ogni colpo di clock il valore in ingresso di 1 da 1 a 2^31 (non 2^32 perche in vivado non si puo rappresentare
-- come intero un numero piu grande di 2^31).
-- le due variabili rappresentano la parte real e quella immaginaria del segnale in ingresso in particolare
-- devo considerare che i valori ammissibili per entrambi siano compresi tra (-32768,32767) cioe
-- -2^complex_width-1 e 2^(complex_width-1)-1
stim_proc: process
variable modulo : std_logic_vector(complex_width-1 downto 0) := (others=> '0');
variable complex_value_variable_real, complex_value_variable_img : integer := 0;
begin
-- TEST partenza da 0
reset_n <= '0';
complex_value <= x"00000000";
complex_value_variable_real := 0;
complex_value_variable_img := 0;
--TEST PARTENZA DAL PRIMO NEGATIVO
-- complex_value <=x"7fff7fff";
-- complex_value_variable_real := 32767;
-- complex_value_variable_img := 32767;
wait for 100 ns;
reset_n <= '1';
ready_in <= '1';
--Gli if sono messi per evitare che l'assert dia problemi durante la simulazione
--I trattini indicano dei don't care.
for i in 0 to num_cicli loop
complex_value <= complex_value + 1;
complex_value_variable_real := complex_value_variable_real + 1;
--Se ho esaminato tutti i negativi della parte reale cioe il segnale in ingresso valeva al ciclo precedente
-- ----FFFF e ora quindi mi trovo che la parte reale è 0 e devo incrementare quella immaginaria
if(complex_value_variable_real = 0) then
complex_value_variable_img := complex_value_variable_img + 1;
--Se ho esaminato tutti i numeri positivi della parte reale cioè il segnale in ingresso valeva al ciclo
--precedente ----7FFF e ora quindi mi trovo che la parte reale deve essere portata al numero negativo piu grande
elsif(complex_value_variable_real = 32768)then
complex_value_variable_real := -2**((complex_width/2)-1);
end if;
--stessa considerazione del commento precendete solo applicata alla parte immaginaria
if(complex_value_variable_img = 32768)then
complex_value_variable_img := -2**((complex_width/2)-1);
end if;
valid_in <= '1';
wait for clock_period * 2;
valid_in <= '0';
wait until valid_out<= '1';
modulo := std_logic_vector(to_signed(complex_value_variable_real * complex_value_variable_real + complex_value_variable_img * complex_value_variable_img , 32));
assert(abs_value = modulo)report "Modulo calcolato sbagliato!";
wait until ready_out <= '1';
end loop;
wait;
end process;
end Behavioral;
| gpl-2.0 |
xhacker/geany | tests/ctags/bug2374109.vhd | 98 | 196 | function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
| gpl-2.0 |
artic92/sistemi-embedded-task2 | src/ip_core2/tb_complex_max.vhd | 1 | 17517 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.07.2017 14:40:20
-- Design Name:
-- Module Name: tb_complex_max - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_complex_max is
end tb_complex_max;
architecture Behavioral of tb_complex_max is
component complex_max is
Generic ( sample_width : natural := 32;
s : natural := 5;
d : natural := 4;
c : natural := 5 );
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
sample : in STD_LOGIC_VECTOR(sample_width-1 downto 0);
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0);
ready_out : out STD_LOGIC;
valid_out : out STD_LOGIC);
end component;
--Constants
constant clock_period : time := 10 ns;
constant sample_width : natural := 32;
constant s : natural := 5;
constant d : natural := 4;
constant c : natural := 5;
--Inputs
signal clock : std_logic := '0';
signal reset_n : std_logic := '1';
signal sample : std_logic_vector(sample_width-1 downto 0) := (others => '0');
signal valid_in : std_logic := '0';
signal ready_in : std_logic := '0';
-- Outputs
signal sample_max : std_logic_vector(sample_width-1 downto 0) := (others => '0');
signal max : std_logic_vector(sample_width-1 downto 0) := (others => '0');
signal pos_campione : STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0);
signal pos_doppler : STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0);
signal pos_satellite : STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0);
signal ready_out : std_logic := '0';
signal valid_out : std_logic := '0';
begin
uut: complex_max
Generic map ( sample_width => sample_width,
s => s,
d => d,
c => c )
Port map ( clock => clock,
reset_n => reset_n,
ready_in => ready_in,
valid_in => valid_in,
sample => sample,
sample_max => sample_max,
max => max,
pos_campione => pos_campione,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
ready_out => ready_out,
valid_out => valid_out);
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stim_proc: process
begin
reset_n <= '0';
wait for 100 ns;
reset_n <= '1';
ready_in <= '0';
--TEST Primo assoluto
-- sample <= x"000a000a";
sample <= x"00010001";
--TEST dato iniziale non pronto
--wait for clock_period * 20;
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00090009";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00090009";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
--TEST attesa simultanea dei blocchi
-- sample <= x"000b000b";
-- wait for clock_period * 50;
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
--TEST Ultimo campione del secondo satellite
-- sample <= x"000a000a";
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
--TEST Primo campione del terzo satellite
--sample <= x"000a000a";
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
--TEST in mezzo al terzo satellite
-- sample <= x"000a000a";
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
--TEST Ultimo in assoluto
-- sample <= x"000a000a";
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
valid_in <= '1';
sample <=x"000c000c";
wait for clock_period * 20;
ready_in <= '0';
wait;
end process;
end Behavioral;
| gpl-2.0 |
JoseHawk/Voltmeter | Voltímetro_01/codificador7Segmentos.vhd | 4 | 894 | -- CODIFICADOR 7 SEGMENTOS
-- Librerias necesarias
library ieee;
use ieee.std_logic_1164.all;
ENTITY codificador7Segmentos IS
PORT (
entrada : IN INTEGER RANGE 0 TO 9;
salida : OUT STD_lOGIC_VECTOR (6 DOWNTO 0)
);
END codificador7Segmentos;
ARCHITECTURE arquitecturaCodificador7Segmentos OF codificador7Segmentos IS
BEGIN
codificacion : PROCESS (entrada)
BEGIN
CASE entrada IS
WHEN 0 => salida <= "0000001";
WHEN 1 => salida <= "1001111";
WHEN 2 => salida <= "0010010";
WHEN 3 => salida <= "0000110";
WHEN 4 => salida <= "1001100";
WHEN 5 => salida <= "0100100";
WHEN 6 => salida <= "1100000";
WHEN 7 => salida <= "0001111";
WHEN 8 => salida <= "0000000";
WHEN 9 => salida <= "0001100";
END CASE;
END PROCESS codificacion;
END arquitecturaCodificador7Segmentos; | gpl-2.0 |
praveendath92/securePUF | ipcore_dir/blk_mem_gen_paramReg_ste/example_design/bmg_wrapper.vhd | 1 | 10478 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 255
-- C_READ_DEPTH_A : 255
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 255
-- C_READ_DEPTH_B : 255
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 1
-- C_DISABLE_WARN_BHV_RANGE : 1
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT blk_mem_gen_paramReg_top IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_paramReg_top
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| gpl-2.0 |
praveendath92/securePUF | ipcore_dir/RMEM/simulation/random.vhd | 101 | 4108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
praveendath92/securePUF | ipcore_dir/blk_mem_gen_inputMem_ste/example_design/blk_mem_gen_inputMem_top.vhd | 1 | 5013 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_inputMem_top IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END blk_mem_gen_inputMem_top;
ARCHITECTURE xilinx OF blk_mem_gen_inputMem_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_inputMem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : blk_mem_gen_inputMem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| gpl-2.0 |
glenoverby/hackrf | firmware/cpld/sgpio_if/top.vhd | 12 | 5535 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7F" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i;
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i and decimate_en;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
praveendath92/securePUF | ipcore_dir/RMEM/simulation/bmg_tb_pkg.vhd | 101 | 6006 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
| gpl-2.0 |
praveendath92/securePUF | ipcore_dir/blk_mem_gen_inputMem_ste/example_design/bmg_wrapper.vhd | 1 | 10225 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 131072
-- C_READ_DEPTH_A : 131072
-- C_ADDRA_WIDTH : 17
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 131072
-- C_READ_DEPTH_B : 131072
-- C_ADDRB_WIDTH : 17
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 1
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 1
-- C_DISABLE_WARN_BHV_RANGE : 1
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT blk_mem_gen_inputMem_top IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_inputMem_top
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| gpl-2.0 |
juniper-project/fpgas-caicos | dynamic_board_designs/common/wrapper_hdl/wrapper.vhd | 2 | 19233 | library ieee ;
use ieee.std_logic_1164.all;
entity hls_toplevel is
port(
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
m_axi_mem_AWVALID : OUT STD_LOGIC;
m_axi_mem_AWREADY : IN STD_LOGIC;
m_axi_mem_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mem_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_AWREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_WVALID : OUT STD_LOGIC;
m_axi_mem_WREADY : IN STD_LOGIC;
m_axi_mem_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_WLAST : OUT STD_LOGIC;
m_axi_mem_WID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_ARVALID : OUT STD_LOGIC;
m_axi_mem_ARREADY : IN STD_LOGIC;
m_axi_mem_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mem_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mem_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_ARREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mem_RVALID : IN STD_LOGIC;
m_axi_mem_RREADY : OUT STD_LOGIC;
m_axi_mem_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mem_RLAST : IN STD_LOGIC;
m_axi_mem_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_mem_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_BVALID : IN STD_LOGIC;
m_axi_mem_BREADY : OUT STD_LOGIC;
m_axi_mem_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mem_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
interrupt : OUT STD_LOGIC;
jamaica_syscall : OUT STD_LOGIC;
hold_outputs : IN STD_LOGIC
);
end entity hls_toplevel;
architecture rtl of hls_toplevel is
COMPONENT hls
PORT (
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
m_axi_MAXI_AWVALID : OUT STD_LOGIC;
m_axi_MAXI_AWREADY : IN STD_LOGIC;
m_axi_MAXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_MAXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_AWREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_AWUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_WVALID : OUT STD_LOGIC;
m_axi_MAXI_WREADY : IN STD_LOGIC;
m_axi_MAXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_WLAST : OUT STD_LOGIC;
m_axi_MAXI_WID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_ARVALID : OUT STD_LOGIC;
m_axi_MAXI_ARREADY : IN STD_LOGIC;
m_axi_MAXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_MAXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_MAXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_ARREGION : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_MAXI_ARUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_RVALID : IN STD_LOGIC;
m_axi_MAXI_RREADY : OUT STD_LOGIC;
m_axi_MAXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_MAXI_RLAST : IN STD_LOGIC;
m_axi_MAXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_BVALID : IN STD_LOGIC;
m_axi_MAXI_BREADY : OUT STD_LOGIC;
m_axi_MAXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_MAXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_MAXI_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
interrupt : OUT STD_LOGIC;
syscall_interrupt_i : IN STD_LOGIC;
syscall_interrupt_o : OUT STD_LOGIC
);
END COMPONENT;
-- Insert a pipeline stage on hold_outputs
signal reg_hold_outputs : std_logic := '0';
signal sig_s_axi_AXILiteS_AWVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_AWREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_AWADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_s_axi_AXILiteS_WVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_WREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_WDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_s_axi_AXILiteS_WSTRB : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_s_axi_AXILiteS_ARVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_ARREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_ARADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_s_axi_AXILiteS_RVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_RREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_RDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_s_axi_AXILiteS_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_s_axi_AXILiteS_BVALID : STD_LOGIC;
signal sig_s_axi_AXILiteS_BREADY : STD_LOGIC;
signal sig_s_axi_AXILiteS_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_ap_clk : STD_LOGIC;
signal sig_ap_rst_n : STD_LOGIC;
signal sig_m_axi_mem_AWVALID : STD_LOGIC;
signal sig_m_axi_mem_AWREADY : STD_LOGIC;
signal sig_m_axi_mem_AWADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_AWID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_AWLEN : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_m_axi_mem_AWSIZE : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_AWBURST : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_AWLOCK : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_AWCACHE : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_AWPROT : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_AWQOS : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_AWREGION : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_AWUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_WVALID : STD_LOGIC;
signal sig_m_axi_mem_WREADY : STD_LOGIC;
signal sig_m_axi_mem_WDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_WSTRB : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_WLAST : STD_LOGIC;
signal sig_m_axi_mem_WID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_WUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_ARVALID : STD_LOGIC;
signal sig_m_axi_mem_ARREADY : STD_LOGIC;
signal sig_m_axi_mem_ARADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_ARID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_ARLEN : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sig_m_axi_mem_ARSIZE : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_ARBURST : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_ARLOCK : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_ARCACHE : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_ARPROT : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal sig_m_axi_mem_ARQOS : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_ARREGION : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sig_m_axi_mem_ARUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_RVALID : STD_LOGIC;
signal sig_m_axi_mem_RREADY : STD_LOGIC;
signal sig_m_axi_mem_RDATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sig_m_axi_mem_RLAST : STD_LOGIC;
signal sig_m_axi_mem_RID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_RUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_BVALID : STD_LOGIC;
signal sig_m_axi_mem_BREADY : STD_LOGIC;
signal sig_m_axi_mem_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal sig_m_axi_mem_BID : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_m_axi_mem_BUSER : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal sig_interrupt : STD_LOGIC;
signal sig_dummy_user : STD_LOGIC_VECTOR(0 downto 0);
signal sig_syscall_interrupt_o : STD_LOGIC;
attribute S : string;
attribute S of sig_dummy_user : signal is "TRUE";
begin
update_output_hold: process(sig_ap_clk,sig_ap_rst_n)
begin
if (sig_ap_rst_n = '0') then
reg_hold_outputs <= '0';
elsif (sig_ap_clk = '1' and sig_ap_clk'event) then
reg_hold_outputs <= hold_outputs;
end if;
end process;
brg : hls
PORT MAP (
s_axi_AXILiteS_AWVALID => sig_s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY => sig_s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR => sig_s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID => sig_s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY => sig_s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA => sig_s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB => sig_s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID => sig_s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY => sig_s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR => sig_s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID => sig_s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY => sig_s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA => sig_s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP => sig_s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID => sig_s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY => sig_s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP => sig_s_axi_AXILiteS_BRESP,
ap_clk => sig_ap_clk,
ap_rst_n => sig_ap_rst_n,
m_axi_MAXI_AWVALID => sig_m_axi_mem_AWVALID,
m_axi_MAXI_AWREADY => sig_m_axi_mem_AWREADY,
m_axi_MAXI_AWADDR => sig_m_axi_mem_AWADDR,
m_axi_MAXI_AWID => sig_m_axi_mem_AWID,
m_axi_MAXI_AWLEN => sig_m_axi_mem_AWLEN,
m_axi_MAXI_AWSIZE => sig_m_axi_mem_AWSIZE,
m_axi_MAXI_AWBURST => sig_m_axi_mem_AWBURST,
m_axi_MAXI_AWLOCK => sig_m_axi_mem_AWLOCK,
m_axi_MAXI_AWCACHE => sig_m_axi_mem_AWCACHE,
m_axi_MAXI_AWPROT => sig_m_axi_mem_AWPROT,
m_axi_MAXI_AWQOS => sig_m_axi_mem_AWQOS,
m_axi_MAXI_AWREGION => sig_m_axi_mem_AWREGION,
m_axi_MAXI_AWUSER => sig_m_axi_mem_AWUSER,
m_axi_MAXI_WVALID => sig_m_axi_mem_WVALID,
m_axi_MAXI_WREADY => sig_m_axi_mem_WREADY,
m_axi_MAXI_WDATA => sig_m_axi_mem_WDATA,
m_axi_MAXI_WSTRB => sig_m_axi_mem_WSTRB,
m_axi_MAXI_WLAST => sig_m_axi_mem_WLAST,
m_axi_MAXI_WID => sig_m_axi_mem_WID,
m_axi_MAXI_WUSER => sig_m_axi_mem_WUSER,
m_axi_MAXI_ARVALID => sig_m_axi_mem_ARVALID,
m_axi_MAXI_ARREADY => sig_m_axi_mem_ARREADY,
m_axi_MAXI_ARADDR => sig_m_axi_mem_ARADDR,
m_axi_MAXI_ARID => sig_m_axi_mem_ARID,
m_axi_MAXI_ARLEN => sig_m_axi_mem_ARLEN,
m_axi_MAXI_ARSIZE => sig_m_axi_mem_ARSIZE,
m_axi_MAXI_ARBURST => sig_m_axi_mem_ARBURST,
m_axi_MAXI_ARLOCK => sig_m_axi_mem_ARLOCK,
m_axi_MAXI_ARCACHE => sig_m_axi_mem_ARCACHE,
m_axi_MAXI_ARPROT => sig_m_axi_mem_ARPROT,
m_axi_MAXI_ARQOS => sig_m_axi_mem_ARQOS,
m_axi_MAXI_ARREGION => sig_m_axi_mem_ARREGION,
m_axi_MAXI_ARUSER => sig_m_axi_mem_ARUSER,
m_axi_MAXI_RVALID => sig_m_axi_mem_RVALID,
m_axi_MAXI_RREADY => sig_m_axi_mem_RREADY,
m_axi_MAXI_RDATA => sig_m_axi_mem_RDATA,
m_axi_MAXI_RLAST => sig_m_axi_mem_RLAST,
m_axi_MAXI_RID => sig_m_axi_mem_RID,
m_axi_MAXI_RUSER => sig_dummy_user,
m_axi_MAXI_RRESP => sig_m_axi_mem_RRESP,
m_axi_MAXI_BVALID => sig_m_axi_mem_BVALID,
m_axi_MAXI_BREADY => sig_m_axi_mem_BREADY,
m_axi_MAXI_BRESP => sig_m_axi_mem_BRESP,
m_axi_MAXI_BID => sig_m_axi_mem_BID,
m_axi_MAXI_BUSER => "0",
interrupt => sig_interrupt,
syscall_interrupt_o => sig_syscall_interrupt_o,
syscall_interrupt_i => '0'
);
s_axi_AXILiteS_AWREADY <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_AWREADY;
s_axi_AXILiteS_WREADY <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_WREADY ;
s_axi_AXILiteS_ARREADY <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_ARREADY;
s_axi_AXILiteS_RVALID <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_RVALID ;
s_axi_AXILiteS_RDATA <= (not (31 downto 0 => reg_hold_outputs)) and sig_s_axi_AXILiteS_RDATA;
s_axi_AXILiteS_RRESP <= (not (1 downto 0 => reg_hold_outputs)) and sig_s_axi_AXILiteS_RRESP;
s_axi_AXILiteS_BVALID <= (not reg_hold_outputs) and sig_s_axi_AXILiteS_BVALID ;
s_axi_AXILiteS_BRESP <= (not (1 downto 0 => reg_hold_outputs)) and sig_s_axi_AXILiteS_BRESP;
m_axi_mem_AWVALID <= (not reg_hold_outputs) and sig_m_axi_mem_AWVALID ;
m_axi_mem_AWADDR <= (not (31 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWADDR ;
m_axi_mem_AWID <= (not (0 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWID ;
m_axi_mem_AWLEN <= (not (7 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWLEN ;
m_axi_mem_AWSIZE <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWSIZE ;
m_axi_mem_AWBURST <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWBURST ;
m_axi_mem_AWLOCK <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWLOCK ;
m_axi_mem_AWCACHE <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWCACHE ;
m_axi_mem_AWPROT <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWPROT ;
m_axi_mem_AWQOS <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWQOS ;
m_axi_mem_AWREGION <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_AWREGION;
m_axi_mem_WVALID <= (not reg_hold_outputs) and sig_m_axi_mem_WVALID ;
m_axi_mem_WDATA <= (not (31 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_WDATA;
m_axi_mem_WSTRB <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_WSTRB;
m_axi_mem_WLAST <= (not reg_hold_outputs) and sig_m_axi_mem_WLAST ;
m_axi_mem_WID <= (not (0 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_WID;
m_axi_mem_ARVALID <= (not reg_hold_outputs) and sig_m_axi_mem_ARVALID ;
m_axi_mem_ARADDR <= (not (31 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARADDR ;
m_axi_mem_ARID <= (not (0 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARID ;
m_axi_mem_ARLEN <= (not (7 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARLEN ;
m_axi_mem_ARSIZE <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARSIZE ;
m_axi_mem_ARBURST <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARBURST ;
m_axi_mem_ARLOCK <= (not (1 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARLOCK ;
m_axi_mem_ARCACHE <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARCACHE ;
m_axi_mem_ARPROT <= (not (2 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARPROT ;
m_axi_mem_ARQOS <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARQOS ;
m_axi_mem_ARREGION <= (not (3 downto 0 => reg_hold_outputs)) and sig_m_axi_mem_ARREGION;
m_axi_mem_RREADY <= (not reg_hold_outputs) and sig_m_axi_mem_RREADY ;
m_axi_mem_BREADY <= (not reg_hold_outputs) and sig_m_axi_mem_BREADY ;
interrupt <= (not reg_hold_outputs) and sig_interrupt ;
sig_s_axi_AXILiteS_AWVALID <= s_axi_AXILiteS_AWVALID;
sig_s_axi_AXILiteS_AWADDR <= s_axi_AXILiteS_AWADDR ;
sig_s_axi_AXILiteS_WVALID <= s_axi_AXILiteS_WVALID ;
sig_s_axi_AXILiteS_WDATA <= s_axi_AXILiteS_WDATA ;
sig_s_axi_AXILiteS_WSTRB <= s_axi_AXILiteS_WSTRB ;
sig_s_axi_AXILiteS_ARVALID <= s_axi_AXILiteS_ARVALID;
sig_s_axi_AXILiteS_ARADDR <= s_axi_AXILiteS_ARADDR ;
sig_s_axi_AXILiteS_RREADY <= s_axi_AXILiteS_RREADY ;
sig_s_axi_AXILiteS_BREADY <= s_axi_AXILiteS_BREADY ;
sig_ap_clk <= ap_clk ;
sig_ap_rst_n <= (not reg_hold_outputs) and ap_rst_n; -- Also hold reset when isolated...
sig_m_axi_mem_AWREADY <= m_axi_mem_AWREADY ;
sig_m_axi_mem_WREADY <= m_axi_mem_WREADY ;
sig_m_axi_mem_ARREADY <= m_axi_mem_ARREADY ;
sig_m_axi_mem_RVALID <= m_axi_mem_RVALID ;
sig_m_axi_mem_RDATA <= m_axi_mem_RDATA ;
sig_m_axi_mem_RLAST <= m_axi_mem_RLAST ;
sig_m_axi_mem_RID <= m_axi_mem_RID ;
sig_m_axi_mem_RRESP <= m_axi_mem_RRESP ;
sig_m_axi_mem_BVALID <= m_axi_mem_BVALID ;
sig_m_axi_mem_BRESP <= m_axi_mem_BRESP ;
sig_m_axi_mem_BID <= m_axi_mem_BID ;
sig_dummy_user <= sig_m_axi_mem_AWUSER or sig_m_axi_mem_WUSER or sig_m_axi_mem_ARUSER;
jamaica_syscall <= (not reg_hold_outputs) and sig_syscall_interrupt_o;
end architecture rtl;
| gpl-2.0 |
praveendath92/securePUF | ipcore_dir/RMEM/simulation/RMEM_synth.vhd | 1 | 7855 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RMEM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY RMEM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE RMEM_synth_ARCH OF RMEM_synth IS
COMPONENT RMEM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: RMEM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-2.0 |
freecores/minimips | miniMIPS/bench/rom.vhd | 1 | 6850 | ------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.pack_mips.all;
entity rom is
generic (mem_size : natural := 256; -- Size of the memory in words
start : natural := 32768;
latency : time := 0 ns);
port(
adr : in bus32;
donnee : out bus32;
ack : out std_logic;
load : in std_logic;
fname : in string
);
end;
architecture bench of rom is
type storage_array is array(natural range start to start+4*mem_size - 1) of bus8;
signal storage : storage_array := (others => (others => '0')); -- The memory
signal adresse : bus16;
signal taille : bus16;
begin
process (load)
-- Variables for loading the memory
-- The reading is done by blocks
type bin is file of integer; -- Binary type file
file load_file : bin;
variable c : integer ; -- Integer (32 bits) read in the file
variable index : integer range storage'range; -- Index for loading
variable word : bus32; -- Word read in the file
variable taille_bloc : integer; -- Current size of the block to load
variable tmp : bus16;
variable status : file_open_status;
variable s : line;
variable big_endian : boolean := true; -- Define if the processor (on which we work) is little or big endian
begin
if load='1' then
-- Reading of the file de fill the memory at the defined address
file_open(status, load_file, fname, read_mode);
if status=open_ok then
while not endfile(load_file) loop
-- Read the header of the block
read(load_file, c); -- Read a 32 bit long word
word := bus32(to_unsigned(c, 32)); -- Conversion to a bit vector
if big_endian then
tmp := word(7 downto 0) & word(15 downto 8);
else
tmp := word(31 downto 16);
end if;
index := to_integer(unsigned(tmp));
adresse <= tmp;
if big_endian then
tmp := word(23 downto 16) & word(31 downto 24);
else
tmp := word(15 downto 0);
end if;
taille_bloc := to_integer(unsigned(tmp)) / 4;
taille <= tmp;
-- Load the block in the ROM
for n in 1 to taille_bloc loop
-- The header file is not correct (block too small, ROM to small ...)
-- The simulation is stopped
assert (not endfile(load_file) and (index<=storage'high))
report "L'image n'a pas le bon format ou ne rentre pas dans la rom."
severity error;
if not endfile(load_file) and (index<=storage'high) then
read(load_file, c);
word := bus32(to_unsigned(c, 32));
if (c < 0) then
word := not(word);
word := std_logic_vector(unsigned(word)+1);
end if;
for i in 0 to 3 loop
if big_endian then
storage(index+i) <= word(8*(i+1)-1 downto 8*i);
else
storage(index+(3-i)) <= word(8*(i+1)-1 downto 8*i);
end if;
end loop;
index := index + 4;
end if;
end loop;
end loop;
file_close(load_file);
else
assert false
report "Impossible d'ouvrir le fichier specifie."
severity error;
end if;
end if;
end process;
process(adr) -- Request for reading the ROM
variable inadr : integer;
variable i : natural;
begin
inadr := to_integer(unsigned(adr));
if (inadr>=storage'low) and (inadr<=storage'high) then
for i in 0 to 3 loop
donnee(8*(i+1)-1 downto 8*i) <= storage(inadr+3-i) after latency;
end loop;
ack <= '0', '1' after latency;
else
donnee <= (others => 'Z');
ack <= 'L';
end if;
end process;
end bench;
| gpl-2.0 |
jvshahid/ctags-exuberant | Test/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
techwoes/sump | logic_analyzer/clockman.vhd | 3 | 2890 | ----------------------------------------------------------------------------------
-- clockman.vhd
--
-- Author: Michael "Mr. Sump" Poppitz
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- This is only a wrapper for Xilinx' DCM component so it doesn't
-- have to go in the main code and can be replaced more easily.
--
-- Creates clk0 with 100MHz.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clockman is
Port (
clkin : in STD_LOGIC; -- clock input
clk0 : out std_logic -- double clock rate output
);
end clockman;
architecture Behavioral of clockman is
signal clkfb, clkfbbuf, realclk0 : std_logic;
begin
-- DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E
-- Xilinx HDL Language Template version 8.1i
DCM_baseClock : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKIN => clkin, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0', -- DCM asynchronous reset input
CLK2X => realclk0,
CLK0 => clkfb,
CLKFB => clkfbbuf
);
-- clkfb is run through a BUFG only to shut up ISE 8.1
BUFG_clkfb : BUFG
port map (
O => clkfbbuf, -- Clock buffer output
I => clkfb -- Clock buffer input
);
clk0 <= realclk0;
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic_analyzer/sram_bram.vhd | 4 | 2555 | ----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Simple BlockRAM interface.
--
-- This module should be used instead of sram.vhd if no external SRAM is present.
-- Instead, it will use internal BlockRAM (16 Blocks).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_bram is
GENERIC
(
ADDRESS_WIDTH : integer := 13
);
Port (
clock : in STD_LOGIC;
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic
);
end sram_bram;
architecture Behavioral of sram_bram is
signal address : std_logic_vector (ADDRESS_WIDTH - 1 downto 0);
signal bramIn, bramOut : std_logic_vector (31 downto 0);
COMPONENT BRAM8k32bit--SampleRAM
PORT(
WE : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
ADDR : IN std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
DOUT : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
begin
-- assign signals
output <= bramOut;
-- memory io interface state controller
bramIn <= input;
-- memory address controller
process(clock)
begin
if rising_edge(clock) then
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
-- sample block ram
Inst_SampleRAM: BRAM8k32bit PORT MAP(
ADDR => address,
DIN => bramIn,
WE => write,
CLK => clock,
DOUT => bramOut
);
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic_analyzer2/sram_bram.vhd | 4 | 2555 | ----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Simple BlockRAM interface.
--
-- This module should be used instead of sram.vhd if no external SRAM is present.
-- Instead, it will use internal BlockRAM (16 Blocks).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_bram is
GENERIC
(
ADDRESS_WIDTH : integer := 13
);
Port (
clock : in STD_LOGIC;
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic
);
end sram_bram;
architecture Behavioral of sram_bram is
signal address : std_logic_vector (ADDRESS_WIDTH - 1 downto 0);
signal bramIn, bramOut : std_logic_vector (31 downto 0);
COMPONENT BRAM8k32bit--SampleRAM
PORT(
WE : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
ADDR : IN std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
DOUT : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
begin
-- assign signals
output <= bramOut;
-- memory io interface state controller
bramIn <= input;
-- memory address controller
process(clock)
begin
if rising_edge(clock) then
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
-- sample block ram
Inst_SampleRAM: BRAM8k32bit PORT MAP(
ADDR => address,
DIN => bramIn,
WE => write,
CLK => clock,
DOUT => bramOut
);
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic-analyzer-orig/fpga/BRAM8k32bit.vhd | 4 | 2519 | ----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM8k32bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (31 downto 0);
DIN : in STD_LOGIC_VECTOR (31 downto 0));
end BRAM8k32bit;
architecture Behavioral of BRAM8k32bit is
begin
BlockRAMS: for i in 0 to 15 generate
RAMB16_S2_inst : RAMB16_S2
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
ADDR => ADDR, -- 13-bit Address Input
CLK => CLK, -- Clock
DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WE -- Write Enable Input
);
end generate;
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic-analyzer-orig/fpga/rle_enc.vhd | 4 | 3391 | ----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Run Length Encoder
--
-- If enabled, encode the incoming data with the following scheme:
-- The MSB (bit 31) is used as a flag for the encoding.
-- If the MSB is clear, the datum represents "regular" data
-- if set, the datum represents the number of repetitions of the previous data
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rle_enc is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (31 downto 0);
validIn : in STD_LOGIC;
enable : in STD_LOGIC;
dataOut : out STD_LOGIC_VECTOR (31 downto 0);
validOut : out STD_LOGIC);
end rle_enc;
architecture Behavioral of rle_enc is
signal old: std_logic_vector(30 downto 0);
signal dout: std_logic_vector(31 downto 0);
signal ctr: std_logic_vector(30 downto 0);
signal valid, valout: std_logic;
begin
dataOut <= dataIn when (enable = '0') else dout;
validOut <= validIn when (enable = '0') else valout;
-- shift register
process(clock, reset)
begin
if (reset = '1') then
valid <= '0';
elsif rising_edge(clock) then
if (validIn = '1') then
old <= dataIn(30 downto 0);
valid <= '1';
end if;
end if;
end process;
-- RLE encoder
process(clock, reset)
begin
if (reset = '1') then
ctr <= (others => '0');
elsif rising_edge(clock) then
valout <= '0'; --default
if (enable = '0') then
ctr <= (others => '0');
elsif (valid = '1') AND (validIn = '1') then
if (old = dataIn(30 downto 0)) then
if (ctr = 0) then -- write first datum of series
dout <= '0' & dataIn(30 downto 0); -- discard MSB, which is used for encoding a count
valout <= '1';
elsif (ctr = "111111111111111111111111111111") then -- ctr overflow
dout <= '1' & ctr; -- write count
valout <= '1';
ctr <= (others => '0'); -- reset count, so "series" starts again.
end if;
ctr <= ctr + 1;
else -- series complete, write count (or data, if series was 0 or 1 long)
valout <= '1';
ctr <= (others => '0');
if (ctr > 1) then -- TODO: try if /=0 AND /=1 is faster than >1
dout <= '1' & ctr;
else
dout <= '0' & old;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
freecores/minimips | miniMIPS/src/pps_di.vhd | 1 | 25818 | ------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- Processor miniMIPS : Instruction decoding stage --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
entity pps_di is
port (
clock : in std_logic;
reset : in std_logic;
stop_all : in std_logic; -- Unconditionnal locking of the outputs
clear : in std_logic; -- Clear the pipeline stage (nop in the outputs)
-- Asynchronous connexion with the register management and data bypass unit
adr_reg1 : out adr_reg_type; -- Address of the first register operand
adr_reg2 : out adr_reg_type; -- Address of the second register operand
use1 : out std_logic; -- Effective use of operand 1
use2 : out std_logic; -- Effective use of operand 2
stop_di : in std_logic; -- Unresolved detected : send nop in the pipeline
data1 : in bus32; -- Operand register 1
data2 : in bus32; -- Operand register 2
-- Datas from EI stage
EI_adr : in bus32; -- Address of the instruction
EI_instr : in bus32; -- The instruction to decode
EI_it_ok : in std_logic; -- Allow hardware interruptions
-- Synchronous output to EX stage
DI_bra : out std_logic; -- Branch decoded
DI_link : out std_logic; -- A link for that instruction
DI_op1 : out bus32; -- operand 1 for alu
DI_op2 : out bus32; -- operand 2 for alu
DI_code_ual : out alu_ctrl_type; -- Alu operation
DI_offset : out bus32; -- Offset for the address calculation
DI_adr_reg_dest : out adr_reg_type; -- Address of the destination register of the result
DI_ecr_reg : out std_logic; -- Effective writing of the result
DI_mode : out std_logic; -- Address mode (relative to pc or indexed to a register)
DI_op_mem : out std_logic; -- Memory operation request
DI_r_w : out std_logic; -- Type of memory operation (reading or writing)
DI_adr : out bus32; -- Address of the decoded instruction
DI_exc_cause : out bus32; -- Potential exception detected
DI_level : out level_type; -- Availability of the result for the data bypass
DI_it_ok : out std_logic -- Allow hardware interruptions
);
end entity;
architecture rtl of pps_di is
-- Enumeration type used for the micro-code of the instruction
type op_mode_type is (OP_NORMAL, OP_SPECIAL, OP_REGIMM, OP_COP0); -- selection du mode de l'instruction
type off_sel_type is (OFS_PCRL, OFS_NULL, OFS_SESH, OFS_SEXT); -- selection de la valeur de l'offset
type rdest_type is ( D_RT, D_RD, D_31, D_00); -- selection du registre destination
-- Record type containg the micro-code of an instruction
type micro_instr_type is
record
op_mode : op_mode_type; -- Instruction codop mode
op_code : bus6; -- Instruction codop
bra : std_logic; -- Branch instruction
link : std_logic; -- Branch with link : the return address is saved in a register
code_ual : alu_ctrl_type; -- Operation code for the alu
op_mem : std_logic; -- Memory operation needed
r_w : std_logic; -- Read/Write selection in memory
mode : std_logic; -- Address calculation from the current pc ('1') or the alu operand 1 ('0')
off_sel : off_sel_type; -- Offset source : PC(31..28) & Adresse & 00 || 0 || sgn_ext(Imm) & 00 || sgn_ext(Imm)
exc_cause : bus32; -- Unconditionnal exception cause to generate
cop_org1 : std_logic; -- Source register 1 : general register if 0, coprocessor register if 1
cop_org2 : std_logic; -- Source register 2 : general register if 0, coprocessor register if 1
cs_imm1 : std_logic; -- Use of immediat operand 1 instead of register bank
cs_imm2 : std_logic; -- Use of immediat operand 2 instead of register bank
imm1_sel : std_logic; -- Origine of immediat operand 1
imm2_sel : std_logic; -- Origine of immediat operand 2
level : level_type; -- Data availability stage for the bypass
ecr_reg : std_logic; -- Writing the result in a register
bank_des : std_logic; -- Register bank selection : GPR if 0, coprocessor system if 1
des_sel : rdest_type ; -- Destination register address : Rt, Rd, $31, $0
end record;
type micro_code_type is array (natural range <>) of micro_instr_type;
constant micro_code : micro_code_type :=
( -- Instruction decoding in micro-instructions table
(OP_SPECIAL, "100000", '0', '0', OP_ADD , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- ADD
(OP_NORMAL , "001000", '0', '0', OP_ADD , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '1', LVL_EX , '1', '0', D_RT), -- ADDI
(OP_NORMAL , "001001", '0', '0', OP_ADDU , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_RT), -- ADDIU
(OP_SPECIAL, "100001", '0', '0', OP_ADDU , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- ADDU
(OP_SPECIAL, "100100", '0', '0', OP_AND , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- AND
(OP_NORMAL , "001100", '0', '0', OP_AND , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_RT), -- ANDI
(OP_NORMAL , "000100", '1', '0', OP_EQU , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_DI , '0', '0', D_RT), -- BEQ
(OP_REGIMM , "000001", '1', '0', OP_LPOS , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- BGEZ
(OP_REGIMM , "010001", '1', '1', OP_LPOS , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_31), -- BGEZAL
(OP_NORMAL , "000111", '1', '0', OP_SPOS , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- BGTZ
(OP_NORMAL , "000110", '1', '0', OP_LNEG , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- BLEZ
(OP_REGIMM , "000000", '1', '0', OP_SNEG , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- BLTZ
(OP_REGIMM , "010000", '1', '1', OP_SNEG , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_31), -- BLTZAL
(OP_NORMAL , "000101", '1', '0', OP_NEQU , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_DI , '0', '0', D_RT), -- BNE
(OP_SPECIAL, "001101", '0', '0', OP_OUI , '0', '0', '0', OFS_PCRL, IT_BREAK, '0', '0', '1', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- BREAK
(OP_COP0 , "000001", '0', '0', OP_OP2 , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_DI , '1', '1', D_00), -- COP0
(OP_NORMAL , "000010", '1', '0', OP_OUI , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- J
(OP_NORMAL , "000011", '1', '1', OP_OUI , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_EX , '1', '0', D_31), -- JAL
(OP_SPECIAL, "001001", '1', '1', OP_OUI , '0', '0', '0', OFS_NULL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_RD), -- JALR
(OP_SPECIAL, "001000", '1', '0', OP_OUI , '0', '0', '0', OFS_NULL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- JR
(OP_NORMAL , "001111", '0', '0', OP_LUI , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_EX , '1', '0', D_RT), -- LUI
(OP_NORMAL , "100011", '0', '0', OP_OUI , '1', '0', '0', OFS_SEXT, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_MEM, '1', '0', D_RT), -- LW
(OP_NORMAL , "110000", '0', '0', OP_OUI , '1', '0', '0', OFS_SEXT, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_MEM, '1', '1', D_RT), -- LWC0
(OP_COP0 , "000000", '0', '0', OP_OP2 , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '1', '1', '0', '0', '0', LVL_DI , '1', '0', D_RD), -- MFC0
(OP_SPECIAL, "010000", '0', '0', OP_MFHI , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_EX , '1', '0', D_RD), -- MFHI
(OP_SPECIAL, "010010", '0', '0', OP_MFLO , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_EX , '1', '0', D_RD), -- MFLO
(OP_COP0 , "000100", '0', '0', OP_OP2 , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '0', '0', '0', LVL_DI , '1', '1', D_RD), -- MTC0
(OP_SPECIAL, "010001", '0', '0', OP_MTHI , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- MTHI
(OP_SPECIAL, "010011", '0', '0', OP_MTLO , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- MTLO
(OP_SPECIAL, "011000", '0', '0', OP_MULT , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '0', '0', D_RT), -- MULT
(OP_SPECIAL, "011001", '0', '0', OP_MULTU, '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '0', '0', D_RT), -- MULT
(OP_SPECIAL, "100111", '0', '0', OP_NOR , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- NOR
(OP_SPECIAL, "100101", '0', '0', OP_OR , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- OR
(OP_NORMAL , "001101", '0', '0', OP_OR , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_RT), -- ORI
(OP_SPECIAL, "000000", '0', '0', OP_SLL , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '0', '1', '0', LVL_EX , '1', '0', D_RD), -- SLL
(OP_SPECIAL, "000100", '0', '0', OP_SLL , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SLLV
(OP_SPECIAL, "101010", '0', '0', OP_SLT , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SLT
(OP_NORMAL , "001010", '0', '0', OP_SLT , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '1', LVL_EX , '1', '0', D_RT), -- SLTI
(OP_NORMAL , "001011", '0', '0', OP_SLTU , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '1', LVL_EX , '1', '0', D_RT), -- SLTIU
(OP_SPECIAL, "101011", '0', '0', OP_SLTU , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SLTU
(OP_SPECIAL, "000011", '0', '0', OP_SRA , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '0', '1', '0', LVL_EX , '1', '0', D_RD), -- SRA
(OP_SPECIAL, "000111", '0', '0', OP_SRA , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SRAV
(OP_SPECIAL, "000010", '0', '0', OP_SRL , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '0', '1', '0', LVL_EX , '1', '0', D_RD), -- SRL
(OP_SPECIAL, "000110", '0', '0', OP_SRL , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SRLV
(OP_SPECIAL, "100010", '0', '0', OP_SUB , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SUB
(OP_SPECIAL, "100011", '0', '0', OP_SUBU , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SUBU
(OP_NORMAL , "101011", '0', '0', OP_OP2 , '1', '1', '0', OFS_SEXT, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_DI , '0', '0', D_RT), -- SW
(OP_NORMAL , "111000", '0', '0', OP_OP2 , '1', '1', '0', OFS_SEXT, IT_NOEXC, '0', '1', '0', '0', '0', '0', LVL_DI , '0', '0', D_RT), -- SWC0
(OP_SPECIAL, "001100", '0', '0', OP_OUI , '0', '0', '0', OFS_PCRL, IT_SCALL, '0', '0', '1', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- SYSC
(OP_SPECIAL, "100110", '0', '0', OP_XOR , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- XOR
(OP_NORMAL , "001110", '0', '0', OP_XOR , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_RT) -- XORI
);
-- Preparation of the synchronous outputs
signal PRE_bra : std_logic; -- Branch operation
signal PRE_link : std_logic; -- Branch with link
signal PRE_op1 : bus32; -- operand 1 of the ual
signal PRE_op2 : bus32; -- operand 2 of the ual
signal PRE_code_ual : alu_ctrl_type; -- Alu operation
signal PRE_offset : bus32; -- Address offset for calculation
signal PRE_adr_reg_dest : adr_reg_type; -- Destination register adress for result
signal PRE_ecr_reg : std_logic; -- Writing of result in the bank register
signal PRE_mode : std_logic; -- Address calculation with current pc
signal PRE_op_mem : std_logic; -- Memory access operation instruction
signal PRE_r_w : std_logic; -- Read/write selection in memory
signal PRE_exc_cause : bus32; -- Potential exception cause
signal PRE_level : level_type; -- Result availability stage for bypass
begin
-- Instruction decoding
process (EI_instr, EI_adr, data1, data2)
variable op_code : bus6; -- Effective codop of the instruction
variable op_mode : op_mode_type; -- Instruction mode
variable flag : boolean; -- Is true if valid instruction
variable instr : integer; -- Current micro-instruction adress
-- Instruction fields
variable rs : bus5;
variable rt : bus5;
variable rd : bus5;
variable shamt : bus5;
variable imm : bus16;
variable address : bus26;
begin
-- Selection of the instruction codop and its mode
case EI_instr(31 downto 26) is
when "000000" => -- special mode
op_mode := OP_SPECIAL;
op_code := EI_instr(5 downto 0);
when "000001" => -- regimm mode
op_mode := OP_REGIMM;
op_code := '0' & EI_instr(20 downto 16);
when "010000" => -- cop0 mode
op_mode := OP_COP0;
op_code := '0' & EI_instr(25 downto 21);
when others => -- normal mode
op_mode := OP_NORMAL;
op_code := EI_instr(31 downto 26);
end case;
-- Search the current instruction in the micro-code table
flag := false;
instr := 0;
for i in micro_code'range loop
if micro_code(i).op_mode=op_mode and micro_code(i).op_code=op_code then
flag := true; -- The instruction exists
instr := i; -- Index memorisation
end if;
end loop;
-- Read the instruction field
rs := EI_instr(25 downto 21);
rt := EI_instr(20 downto 16);
rd := EI_instr(15 downto 11);
shamt := EI_instr(10 downto 6);
imm := EI_instr(15 downto 0);
address := EI_instr(25 downto 0);
if not flag then -- Unknown instruction
-- Synchronous output preparation
PRE_bra <= '0'; -- Branch operation
PRE_link <= '0'; -- Branch with link
PRE_op1 <= (others => '0'); -- operand 1 of the ual
PRE_op2 <= (others => '0'); -- operand 2 of the ual
PRE_code_ual <= OP_OUI; -- Alu operation
PRE_offset <= (others => '0'); -- Address offset for calculation
PRE_adr_reg_dest <= (others => '0'); -- Destination register adress for result
PRE_ecr_reg <= '0'; -- Writing of result in the bank register
PRE_mode <= '0'; -- Address calculation with current pc
PRE_op_mem <= '0'; -- Memory access operation instruction
PRE_r_w <= '0'; -- Read/write selection in memory
PRE_exc_cause <= IT_ERINS; -- Potential exception cause
PRE_level <= LVL_DI; -- Result availability stage for bypass
-- Set asynchronous outputs
adr_reg1 <= (others => '0'); -- First operand register
adr_reg2 <= (others => '0'); -- Second operand register
use1 <= '0'; -- Effective use of operand 1
use2 <= '0'; -- Effective use of operand 2
else -- Valid instruction
-- Offset signal preparation
case micro_code(instr).off_sel is
when OFS_PCRL => -- PC(31..28) & Adresse & 00
PRE_offset <= EI_adr(31 downto 28) & address & "00";
when OFS_NULL => -- 0
PRE_offset <= (others => '0');
when OFS_SESH => -- sgn_ext(Imm) & 00
if imm(15)='1' then
PRE_offset <= "11111111111111" & imm & "00";
else
PRE_offset <= "00000000000000" & imm & "00";
end if;
when OFS_SEXT => -- sgn_ext(Imm)
if imm(15)='1' then
PRE_offset <= "1111111111111111" & imm;
else
PRE_offset <= "0000000000000000" & imm;
end if;
end case;
-- Alu operand preparation
if micro_code(instr).cs_imm1='0' then
-- Datas from register banks
PRE_op1 <= data1;
else
-- Immediate datas
if micro_code(instr).imm1_sel='0' then
PRE_op1 <= (others => '0'); -- Immediate operand = 0
else
PRE_op1 <= X"000000" & "000" & shamt; -- Immediate operand = shamt
end if;
end if;
if micro_code(instr).cs_imm2='0' then
-- Datas from register banks
PRE_op2 <= data2;
else
-- Immediate datas
if micro_code(instr).imm2_sel='0' then
PRE_op2 <= X"0000" & imm; -- Immediate operand = imm
else
if imm(15)='1' then -- Immediate operand = sgn_ext(imm)
PRE_op2 <= X"FFFF" & imm;
else
PRE_op2 <= X"0000" & imm;
end if;
end if;
end if;
-- Selection of destination register address
case micro_code(instr).des_sel is
when D_RT => PRE_adr_reg_dest <= micro_code(instr).bank_des & rt;
when D_RD => PRE_adr_reg_dest <= micro_code(instr).bank_des & rd;
when D_31 => PRE_adr_reg_dest <= micro_code(instr).bank_des & "11111";
when D_00 => PRE_adr_reg_dest <= micro_code(instr).bank_des & "00000";
end case;
-- Command signal affectation
PRE_bra <= micro_code(instr).bra; -- Branch operation
PRE_link <= micro_code(instr).link; -- Branch with link
PRE_code_ual <= micro_code(instr).code_ual; -- Alu operation
PRE_ecr_reg <= micro_code(instr).ecr_reg; -- Writing the result in a bank register
PRE_mode <= micro_code(instr).mode; -- Type of calculation for the address with current pc
PRE_op_mem <= micro_code(instr).op_mem; -- Memory operation needed
PRE_r_w <= micro_code(instr).r_w; -- Read/Write in memory selection
PRE_exc_cause <= micro_code(instr).exc_cause; -- Potential cause exception
PRE_level <= micro_code(instr).level;
-- Set asynchronous outputs
adr_reg1 <= micro_code(instr).cop_org1 & rs; -- First operand register address
adr_reg2 <= micro_code(instr).cop_org2 & rt; -- Second operand register address
use1 <= not micro_code(instr).cs_imm1; -- Effective use of operande 1
use2 <= not micro_code(instr).cs_imm2; -- Effective use of operande 2
end if;
end process;
-- Set the synchronous outputs
process (clock)
begin
if clock='1' and clock'event then
if reset='1' then
DI_bra <= '0';
DI_link <= '0';
DI_op1 <= (others => '0');
DI_op2 <= (others => '0');
DI_code_ual <= OP_OUI;
DI_offset <= (others => '0');
DI_adr_reg_dest <= (others => '0');
DI_ecr_reg <= '0';
DI_mode <= '0';
DI_op_mem <= '0';
DI_r_w <= '0';
DI_adr <= (others => '0');
DI_exc_cause <= IT_NOEXC;
DI_level <= LVL_DI;
DI_it_ok <= '0';
elsif stop_all='0' then
if clear='1' or stop_di='1' then
-- Nop instruction
DI_bra <= '0';
DI_link <= '0';
DI_op1 <= (others => '0');
DI_op2 <= (others => '0');
DI_code_ual <= OP_OUI;
DI_offset <= (others => '0');
DI_adr_reg_dest <= (others => '0');
DI_ecr_reg <= '0';
DI_mode <= '0';
DI_op_mem <= '0';
DI_r_w <= '0';
DI_adr <= EI_adr;
DI_exc_cause <= IT_NOEXC;
DI_level <= LVL_DI;
if clear='1' then
DI_it_ok <= '0';
else
DI_it_ok <= EI_it_ok;
end if;
else -- Noraml step
DI_bra <= PRE_bra;
DI_link <= PRE_link;
DI_op1 <= PRE_op1;
DI_op2 <= PRE_op2;
DI_code_ual <= PRE_code_ual;
DI_offset <= PRE_offset;
DI_adr_reg_dest <= PRE_adr_reg_dest;
DI_ecr_reg <= PRE_ecr_reg;
DI_mode <= PRE_mode;
DI_op_mem <= PRE_op_mem;
DI_r_w <= PRE_r_w;
DI_adr <= EI_adr;
DI_exc_cause <= PRE_exc_cause;
DI_level <= PRE_level;
DI_it_ok <= EI_it_ok;
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
techwoes/sump | logic_analyzer/prescaler.vhd | 3 | 2076 | ----------------------------------------------------------------------------------
-- prescaler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Shared prescaler for transmitter and receiver timings.
-- Used to control the transfer speed.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prescaler is
generic (
SCALE : integer
);
Port ( clock : in STD_LOGIC;
reset : in std_logic;
div : in std_logic_vector(1 downto 0);
scaled : out std_logic
);
end prescaler;
architecture Behavioral of prescaler is
signal counter : integer range 0 to (6 * SCALE) - 1;
begin
process(clock, reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clock) then
if
(counter = SCALE - 1 and div = "00") -- 115200
or (counter = 2 * SCALE - 1 and div = "01") -- 57600
or (counter = 3 * SCALE - 1 and div = "10") -- 38400
or (counter = 6 * SCALE - 1 and div = "11") -- 19200
then
counter <= 0;
scaled <= '1';
else
counter <= counter + 1;
scaled <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
jvshahid/ctags-exuberant | Test/bug2374109.vhd | 98 | 196 | function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
| gpl-2.0 |
techwoes/sump | logic-analyzer-orig/fpga/transmitter.vhd | 3 | 4675 | ----------------------------------------------------------------------------------
-- transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the serial port.
-- End of transmission is signalled by taking back the busy flag.
-- Supports xon/xoff flow control.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
generic (
FREQ : integer;
RATE : integer
);
Port (
data : in STD_LOGIC_VECTOR (31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : in std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in std_logic;
tx : out STD_LOGIC;
busy: out std_logic
-- pause: out std_logic
);
end transmitter;
architecture Behavioral of transmitter is
type TX_STATES is (IDLE, SEND, POLL);
constant BITLENGTH : integer := FREQ / RATE;
signal dataBuffer : STD_LOGIC_VECTOR (31 downto 0);
signal disabledBuffer : std_logic_vector (3 downto 0);
signal txBuffer : std_logic_vector (9 downto 0) := "1000000000";
signal byte : std_logic_vector (7 downto 0);
signal counter : integer range 0 to BITLENGTH;
signal bits : integer range 0 to 10;
signal bytes : integer range 0 to 4;
signal state : TX_STATES;
signal paused, writeByte, byteDone, disabled : std_logic;
begin
-- pause <= paused;
tx <= txBuffer(0);
-- sends one byte
process(clock)
begin
if rising_edge(clock) then
if writeByte = '1' then
counter <= 0;
bits <= 0;
byteDone <= disabled;
txBuffer <= '1' & byte & "0";
elsif counter = BITLENGTH then
counter <= 0;
txBuffer <= '1' & txBuffer(9 downto 1);
if bits = 10 then
byteDone <= '1';
else
bits <= bits + 1;
end if;
elsif trxClock = '1' then
counter <= counter + 1;
end if;
end if;
end process;
-- control mechanism for sending a 32 bit word
process(clock, reset)
begin
if reset = '1' then
writeByte <= '0';
state <= IDLE;
dataBuffer <= (others => '0');
disabledBuffer <= (others => '0');
elsif rising_edge(clock) then
if (state /= IDLE) or (write = '1') or (paused = '1') then
busy <= '1';
else
busy <= '0';
end if;
case state is
-- when write is '1', data will be available with next cycle
when IDLE =>
if write = '1' then
dataBuffer <= data;
disabledBuffer <= disabledGroups;
state <= SEND;
bytes <= 0;
elsif id = '1' then
dataBuffer <= x"534c4131";
disabledBuffer <= "0000";
state <= SEND;
bytes <= 0;
end if;
when SEND =>
if bytes = 4 then
state <= IDLE;
else
bytes <= bytes + 1;
case bytes is
when 0 =>
byte <= dataBuffer(7 downto 0);
disabled <= disabledBuffer(0);
when 1 =>
byte <= dataBuffer(15 downto 8);
disabled <= disabledBuffer(1);
when 2 =>
byte <= dataBuffer(23 downto 16);
disabled <= disabledBuffer(2);
when others =>
byte <= dataBuffer(31 downto 24);
disabled <= disabledBuffer(3);
end case;
writeByte <= '1';
state <= POLL;
end if;
when POLL =>
writeByte <= '0';
if byteDone = '1' and writeByte = '0' and paused = '0' then
state <= SEND;
end if;
end case;
end if;
end process;
-- set paused mode according to xon/xoff commands
process(clock, reset)
begin
if reset = '1' then
paused <= '0';
elsif rising_edge(clock) then
if xon = '1' then
paused <= '0';
elsif xoff = '1' then
paused <= '1';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
freecores/minimips | miniMIPS/src/pack_mips.vhd | 1 | 15609 | ------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- Processor miniMIPS : Enumerations and components declarations --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package pack_mips is
-- Type signal on n bits
subtype bus64 is std_logic_vector(63 downto 0);
subtype bus33 is std_logic_vector(32 downto 0);
subtype bus32 is std_logic_vector(31 downto 0);
subtype bus31 is std_logic_vector(30 downto 0);
subtype bus26 is std_logic_vector(25 downto 0);
subtype bus24 is std_logic_vector(23 downto 0);
subtype bus16 is std_logic_vector(15 downto 0);
subtype bus8 is std_logic_vector(7 downto 0);
subtype bus6 is std_logic_vector(5 downto 0);
subtype bus5 is std_logic_vector(4 downto 0);
subtype bus4 is std_logic_vector(3 downto 0);
subtype bus2 is std_logic_vector(1 downto 0);
subtype bus1 is std_logic;
-- Address of a register type
subtype adr_reg_type is std_logic_vector(5 downto 0);
-- Coding of the level of data availability for UR
subtype level_type is std_logic_vector(1 downto 0);
constant LVL_DI : level_type := "11"; -- Data available from the op2 of DI stage
constant LVL_EX : level_type := "10"; -- Data available from the data_ual register of EX stage
constant LVL_MEM : level_type := "01"; -- Data available from the data_ecr register of MEM stage
constant LVL_REG : level_type := "00"; -- Data available only in the register bank
-- Different values of cause exceptions
constant IT_NOEXC : bus32 := X"00000000";
constant IT_ITMAT : bus32 := X"00000001";
constant IT_OVERF : bus32 := X"00000002";
constant IT_ERINS : bus32 := X"00000004";
constant IT_BREAK : bus32 := X"00000008";
constant IT_SCALL : bus32 := X"00000010";
-- Operation type of the coprocessor system (only the low 16 bits are valid)
constant SYS_NOP : bus32 := X"0000_0000";
constant SYS_MASK : bus32 := X"0000_0001";
constant SYS_UNMASK : bus32 := X"0000_0002";
constant SYS_ITRET : bus32 := X"0000_0004";
-- Type for the alu control
subtype alu_ctrl_type is std_logic_vector(27 downto 0);
-- Arithmetical operations
constant OP_ADD : alu_ctrl_type := "1000000000000000000000000000"; -- op1 + op2 sign
constant OP_ADDU : alu_ctrl_type := "0100000000000000000000000000"; -- op1 + op2 non sign
constant OP_SUB : alu_ctrl_type := "0010000000000000000000000000"; -- op1 - op2 sign
constant OP_SUBU : alu_ctrl_type := "0001000000000000000000000000"; -- op1 - op2 non signe
-- Logical operations
constant OP_AND : alu_ctrl_type := "0000100000000000000000000000"; -- et logique
constant OP_OR : alu_ctrl_type := "0000010000000000000000000000"; -- ou logique
constant OP_XOR : alu_ctrl_type := "0000001000000000000000000000"; -- ou exclusif logique
constant OP_NOR : alu_ctrl_type := "0000000100000000000000000000"; -- non ou logique
-- Tests : result to one if ok
constant OP_SLT : alu_ctrl_type := "0000000010000000000000000000"; -- op1 < op2 (sign)
constant OP_SLTU : alu_ctrl_type := "0000000001000000000000000000"; -- op1 < op2 (non sign)
constant OP_EQU : alu_ctrl_type := "0000000000100000000000000000"; -- op1 = op2
constant OP_NEQU : alu_ctrl_type := "0000000000010000000000000000"; -- op1 /= op2
constant OP_SNEG : alu_ctrl_type := "0000000000001000000000000000"; -- op1 < 0
constant OP_SPOS : alu_ctrl_type := "0000000000000100000000000000"; -- op1 > 0
constant OP_LNEG : alu_ctrl_type := "0000000000000010000000000000"; -- op1 <= 0
constant OP_LPOS : alu_ctrl_type := "0000000000000001000000000000"; -- op1 >= 0
-- Multiplications
constant OP_MULT : alu_ctrl_type := "0000000000000000100000000000"; -- op1 * op2 sign (chargement des poids faibles)
constant OP_MULTU : alu_ctrl_type := "0000000000000000010000000000"; -- op1 * op2 non sign (chargement des poids faibles)
-- Shifts
constant OP_SLL : alu_ctrl_type := "0000000000000000001000000000"; -- decallage logique a gauche
constant OP_SRL : alu_ctrl_type := "0000000000000000000100000000"; -- decallage logique a droite
constant OP_SRA : alu_ctrl_type := "0000000000000000000010000000"; -- decallage arithmetique a droite
constant OP_LUI : alu_ctrl_type := "0000000000000000000001000000"; -- met en poids fort la valeur immediate
-- Access to internal registers
constant OP_MFHI : alu_ctrl_type := "0000000000000000000000100000"; -- lecture des poids forts
constant OP_MFLO : alu_ctrl_type := "0000000000000000000000010000"; -- lecture des poids faibles
constant OP_MTHI : alu_ctrl_type := "0000000000000000000000001000"; -- ecriture des poids forts
constant OP_MTLO : alu_ctrl_type := "0000000000000000000000000100"; -- ecriture des poids faibles
-- Operations which do nothing but are useful
constant OP_OUI : alu_ctrl_type := "0000000000000000000000000010"; -- met a 1 le bit de poids faible en sortie
constant OP_OP2 : alu_ctrl_type := "0000000000000000000000000001"; -- recopie l'operande 2 en sortie
-- Starting boot address (after reset)
constant ADR_INIT : bus32 := X"00000000";
constant INS_NOP : bus32 := X"00000000";
-- Internal component of the pipeline stage
component alu
port (
clock : in bus1;
reset : in bus1;
op1 : in bus32;
op2 : in bus32;
ctrl : in alu_ctrl_type;
res : out bus32;
overflow : out bus1
);
end component;
-- Pipeline stage components
component pps_pf
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
bra_cmd : in bus1;
bra_cmd_pr : in bus1;
bra_adr : in bus32;
exch_cmd : in bus1;
exch_adr : in bus32;
stop_pf : in bus1;
PF_pc : out bus32
);
end component;
component pps_ei
port (
clock : in bus1;
reset : in bus1;
clear : in bus1;
stop_all : in bus1;
stop_ei : in bus1;
CTE_instr : in bus32;
ETC_adr : out bus32;
PF_pc : in bus32;
EI_instr : out bus32;
EI_adr : out bus32;
EI_it_ok : out bus1
);
end component;
component pps_di
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
adr_reg1 : out adr_reg_type;
adr_reg2 : out adr_reg_type;
use1 : out bus1;
use2 : out bus1;
stop_di : in bus1;
data1 : in bus32;
data2 : in bus32;
EI_adr : in bus32;
EI_instr : in bus32;
EI_it_ok : in bus1;
DI_bra : out bus1;
DI_link : out bus1;
DI_op1 : out bus32;
DI_op2 : out bus32;
DI_code_ual : out alu_ctrl_type;
DI_offset : out bus32;
DI_adr_reg_dest : out adr_reg_type;
DI_ecr_reg : out bus1;
DI_mode : out bus1;
DI_op_mem : out bus1;
DI_r_w : out bus1;
DI_adr : out bus32;
DI_exc_cause : out bus32;
DI_level : out level_type;
DI_it_ok : out bus1
);
end component;
component pps_ex
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
DI_bra : in bus1;
DI_link : in bus1;
DI_op1 : in bus32;
DI_op2 : in bus32;
DI_code_ual : in alu_ctrl_type;
DI_offset : in bus32;
DI_adr_reg_dest : in adr_reg_type;
DI_ecr_reg : in bus1;
DI_mode : in bus1;
DI_op_mem : in bus1;
DI_r_w : in bus1;
DI_adr : in bus32;
DI_exc_cause : in bus32;
DI_level : in level_type;
DI_it_ok : in bus1;
EX_adr : out bus32;
EX_bra_confirm : out bus1;
EX_data_ual : out bus32;
EX_adresse : out bus32;
EX_adr_reg_dest : out adr_reg_type;
EX_ecr_reg : out bus1;
EX_op_mem : out bus1;
EX_r_w : out bus1;
EX_exc_cause : out bus32;
EX_level : out level_type;
EX_it_ok : out bus1
);
end component;
component pps_mem
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
MTC_data : out bus32;
MTC_adr : out bus32;
MTC_r_w : out bus1;
MTC_req : out bus1;
CTM_data : in bus32;
EX_adr : in bus32;
EX_data_ual : in bus32;
EX_adresse : in bus32;
EX_adr_reg_dest : in adr_reg_type;
EX_ecr_reg : in bus1;
EX_op_mem : in bus1;
EX_r_w : in bus1;
EX_exc_cause : in bus32;
EX_level : in level_type;
EX_it_ok : in bus1;
MEM_adr : out bus32;
MEM_adr_reg_dest : out adr_reg_type;
MEM_ecr_reg : out bus1;
MEM_data_ecr : out bus32;
MEM_exc_cause : out bus32;
MEM_level : out level_type;
MEM_it_ok : out bus1
);
end component;
component renvoi
port (
adr1 : in adr_reg_type;
adr2 : in adr_reg_type;
use1 : in bus1;
use2 : in bus1;
data1 : out bus32;
data2 : out bus32;
alea : out bus1;
DI_level : in level_type;
DI_adr : in adr_reg_type;
DI_ecr : in bus1;
DI_data : in bus32;
EX_level : in level_type;
EX_adr : in adr_reg_type;
EX_ecr : in bus1;
EX_data : in bus32;
MEM_level : in level_type;
MEM_adr : in adr_reg_type;
MEM_ecr : in bus1;
MEM_data : in bus32;
interrupt : in bus1;
write_data : out bus32;
write_adr : out bus5;
write_GPR : out bus1;
write_SCP : out bus1;
read_adr1 : out bus5;
read_adr2 : out bus5;
read_data1_GPR : in bus32;
read_data1_SCP : in bus32;
read_data2_GPR : in bus32;
read_data2_SCP : in bus32
);
end component;
component banc
port (
clock : in bus1;
reset : bus1;
reg_src1 : in bus5;
reg_src2 : in bus5;
reg_dest : in bus5;
donnee : in bus32;
cmd_ecr : in bus1;
data_src1 : out bus32;
data_src2 : out bus32
);
end component;
component bus_ctrl
port
(
clock : bus1;
reset : bus1;
interrupt : in std_logic;
adr_from_ei : in bus32;
instr_to_ei : out bus32;
req_from_mem : in bus1;
r_w_from_mem : in bus1;
adr_from_mem : in bus32;
data_from_mem : in bus32;
data_to_mem : out bus32;
req_to_ram : out std_logic;
adr_to_ram : out bus32;
r_w_to_ram : out bus1;
ack_from_ram : in bus1;
data_inout_ram : inout bus32;
stop_all : out bus1
);
end component;
component syscop
port
(
clock : in bus1;
reset : in bus1;
MEM_adr : in bus32;
MEM_exc_cause : in bus32;
MEM_it_ok : in bus1;
it_mat : in bus1;
interrupt : out bus1;
vecteur_it : out bus32;
write_data : in bus32;
write_adr : in bus5;
write_SCP : in bus1;
read_adr1 : in bus5;
read_adr2 : in bus5;
read_data1 : out bus32;
read_data2 : out bus32
);
end component;
component predict
generic (
nb_record : integer := 3
);
port (
clock : in std_logic;
reset : in std_logic;
PF_pc : in std_logic_vector(31 downto 0);
DI_bra : in std_logic;
DI_adr : in std_logic_vector(31 downto 0);
EX_bra_confirm : in std_logic;
EX_adr : in std_logic_vector(31 downto 0);
EX_adresse : in std_logic_vector(31 downto 0);
EX_uncleared : in std_logic;
PR_bra_cmd : out std_logic;
PR_bra_bad : out std_logic;
PR_bra_adr : out std_logic_vector(31 downto 0);
PR_clear : out std_logic
);
end component;
component minimips
port (
clock : in bus1;
reset : in bus1;
ram_req : out bus1;
ram_adr : out bus32;
ram_r_w : out bus1;
ram_data : inout bus32;
ram_ack : in bus1;
it_mat : in bus1
);
end component;
end pack_mips;
| gpl-2.0 |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_i2c_arb/wb_i2c_arbiter.vhd | 1 | 11159 | -------------------------------------------------------------------------------
-- Title : WB I2C Bus Arbiter
-- Project : White Rabbit Project
-------------------------------------------------------------------------------
-- File : wb_i2c_arbiter.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2015-08-06
-- Last update: 2015-08-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This component allows to share a single I2C bus for many masters in a simple
-- way.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2015 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.i2c_arb_wbgen2_pkg.all;
use work.i2c_arb_pkg.all;
use work.wishbone_pkg.all;
entity wb_i2c_arbiter is
generic (
g_num_inputs : natural range 2 to 32 := 2;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_enable_bypass_mode : boolean := true;
g_enable_oen : boolean := false
);
port (
-- Clock & Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C input buses
input_sda_i : in std_logic_vector(g_num_inputs-1 downto 0);
input_sda_o : out std_logic_vector(g_num_inputs-1 downto 0);
input_sda_oen : in std_logic_vector(g_num_inputs-1 downto 0);
input_scl_i : in std_logic_vector(g_num_inputs-1 downto 0);
input_scl_o : out std_logic_vector(g_num_inputs-1 downto 0);
input_scl_oen : in std_logic_vector(g_num_inputs-1 downto 0);
-- I2C output bus
output_sda_i : in std_logic;
output_sda_o : out std_logic;
output_sda_oen : out std_logic;
output_scl_i : in std_logic;
output_scl_o : out std_logic;
output_scl_oen : out std_logic;
-- WB Slave bus
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic
);
end wb_i2c_arbiter;
architecture struct of wb_i2c_arbiter is
-- WB signals
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal regs_out : t_i2c_arb_out_registers := c_i2c_arb_out_registers_init_value;
-- Signals for the Start Condition Detectors
signal start_cond_detect : std_logic_vector(g_num_inputs-1 downto 0);
--signal start_acks : std_logic_vector(g_num_inputs-1 downto 0);
signal start_ack : std_logic;
-- Signals for the Stop Condition Detectors
signal stop_cond_detect : std_logic_vector(g_num_inputs-1 downto 0);
--signal stop_acks : std_logic_vector(g_num_inputs-1 downto 0);
signal stop_ack : std_logic;
-- Signal for the Main process
signal active_input : integer range g_num_inputs-1 downto 0 := 0;
signal active_input_hotone : integer range g_num_inputs-1 downto 0 := 0;
type arb_state is (ARB_IDLE, ARB_WAIT, ARB_BLOCKED, ARB_RELEASED, ARB_BYPASS);
signal arb_st : arb_state := ARB_IDLE;
signal hotone_enable_input : std_logic;
signal redirector_enable_input : std_logic;
-- Debug stuff
-- attribute MARK_DEBUG : string;
-- attribute MARK_DEBUG of wb_in : signal is "TRUE";
-- attribute MARK_DEBUG of wb_out : signal is "TRUE";
-- attribute MARK_DEBUG of regs_out : signal is "TRUE";
-- attribute MARK_DEBUG of start_cond_detect : signal is "TRUE";
-- attribute MARK_DEBUG of start_ack : signal is "TRUE";
-- attribute MARK_DEBUG of stop_cond_detect : signal is "TRUE";
-- attribute MARK_DEBUG of stop_ack : signal is "TRUE";
-- attribute MARK_DEBUG of active_input : signal is "TRUE";
-- attribute MARK_DEBUG of active_input_hotone : signal is "TRUE";
-- attribute MARK_DEBUG of arb_st : signal is "TRUE";
-- attribute MARK_DEBUG of hotone_enable_input : signal is "TRUE";
-- attribute MARK_DEBUG of redirector_enable_input : signal is "TRUE";
begin
-- WB Adapter & Regs
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => wb_adr_i,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
U_WB_SLAVE : wb_i2c_arb_slave
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
regs_o => regs_out
);
-- Start & Stop detectors
ss_detectors : for I in 0 to g_num_inputs-1 generate
ss: i2c_arbiter_ss_detector
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
input_sda_i => input_sda_i(I),
input_scl_i => input_scl_i(I),
start_ack_i => start_ack,
stop_ack_i => stop_ack,
start_state_o => start_cond_detect(I),
stop_state_o => stop_cond_detect(I)
);
end generate ss_detectors;
-- I2C Redirector
I2C_REDIRECTOR: i2c_arbiter_redirector
generic map (
g_num_inputs => g_num_inputs,
g_enable_oen => g_enable_oen
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
enable_i => '1',
input_sda_i => input_sda_i,
input_sda_o => input_sda_o,
input_sda_oen => input_sda_oen,
input_scl_i => input_scl_i,
input_scl_o => input_scl_o,
input_scl_oen => input_scl_oen,
output_sda_i => output_sda_i,
output_sda_o => output_sda_o,
output_sda_oen => output_sda_oen,
output_scl_i => output_scl_i,
output_scl_o => output_scl_o,
output_scl_oen => output_scl_oen,
input_enabled_i => redirector_enable_input,
input_idx_enabled_i => active_input
);
-- I2C Hotone decoder
I2C_HOTONE_DEC: i2c_arbiter_hotone_dec
generic map (
g_num_inputs => g_num_inputs
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
enable_i => '1',
start_state_i => start_cond_detect,
input_enabled_o => hotone_enable_input,
input_idx_enabled_o => active_input_hotone
);
-- Mux for the I2C Redirector
redirector_enable_input <= '1' when g_enable_bypass_mode and regs_out.cr_bypass_mode_o = '1' else hotone_enable_input;
-- Active_input Reg
active_input_idx_process: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
active_input <= 0;
elsif arb_st = ARB_WAIT then
if g_enable_bypass_mode and regs_out.cr_bypass_mode_o = '1' then
active_input <= to_integer(signed(regs_out.cr_bypass_src_o));
elsif hotone_enable_input = '1' then
active_input <= active_input_hotone;
end if;
end if;
end if;
end process active_input_idx_process;
-- Start/Stop Ack process
start_stop_ack_process : process(arb_st,stop_cond_detect,active_input)
begin
case arb_st is
when ARB_IDLE =>
stop_ack <= '0';
start_ack <= '0';
when ARB_WAIT =>
stop_ack <= '0';
start_ack <= '0';
when ARB_BLOCKED =>
if stop_cond_detect(active_input) = '1' then
stop_ack <= '1';
start_ack <= '1';
else
stop_ack <= '0';
start_ack <= '0';
end if;
when ARB_RELEASED =>
stop_ack <= '0';
start_ack <= '0';
when ARB_BYPASS =>
stop_ack <= '1';
start_ack <= '1';
when others =>
stop_ack <= '0';
start_ack <= '0';
end case;
end process start_stop_ack_process;
-- FSM process
main_state : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
arb_st <= ARB_IDLE;
else
case arb_st is
when ARB_IDLE =>
arb_st <= ARB_WAIT;
when ARB_WAIT =>
if g_enable_bypass_mode and regs_out.cr_bypass_mode_o = '1' then
arb_st <= ARB_BYPASS;
elsif hotone_enable_input = '1' then
arb_st <= ARB_BLOCKED;
end if;
when ARB_BLOCKED =>
if stop_cond_detect(active_input) = '1' then
arb_st <= ARB_RELEASED;
end if;
when ARB_RELEASED =>
arb_st <= ARB_IDLE;
when ARB_BYPASS =>
if g_enable_bypass_mode and regs_out.cr_bypass_mode_o = '0' then
arb_st <= ARB_RELEASED;
end if;
when others =>
arb_st <= ARB_IDLE;
end case;
end if;
end if;
end process main_state;
end struct;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/rcs.ei.tum.de/Syma_Ctrl_core_v1_2/5d78a94c/hdl/Syma_Ctrl_core_v1_1.vhd | 2 | 14242 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Syma_Ctrl_core_v1_1 is
generic (
-- Users to add parameters here
-- Determe´ins weather Debug Ports are available
DEBUG : integer := 1;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4;
-- Parameters of Axi Slave Bus Interface S01_AXI
C_S01_AXI_DATA_WIDTH : integer := 32;
C_S01_AXI_ADDR_WIDTH : integer := 5;
-- Parameters of Axi Master Bus Interface M01_AXI
C_M01_AXI_START_DATA_VALUE : std_logic_vector := x"AA000000";
C_M01_AXI_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
C_M01_AXI_ADDR_WIDTH : integer := 32;
C_M01_AXI_DATA_WIDTH : integer := 32;
C_M01_AXI_TRANSACTIONS_NUM : integer := 4
);
port (
-- Users to add ports here
--SPI Init Signal
l_ss_init : out std_logic;
ppm_signal_in : in std_logic;
sample_clk : in std_logic;
ppm_irq_single: out std_logic;
ppm_irq_complete: out std_logic;
-- Debug Ports
d_axi_done : out std_logic;
d_axi_start : out std_logic;
d_axi_data : out std_logic_vector(7 downto 0);
d_axi_addr : out std_logic_vector(7 downto 0);
d_slave_cr : out std_logic_vector(7 downto 0);
d_slave_sr : out std_logic_vector(7 downto 0);
d_slave_flight : out std_logic_vector(31 downto 0);
-- d_ppm_sample : inout std_logic_vector (1 downto 0) := "00";
-- d_counter : inout unsigned (31 downto 0) := x"00_00_00_00";
-- d_reg_nr : inout unsigned (3 downto 0) := "0000";
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic;
-- Ports of Axi Slave Bus Interface S01_AXI
s01_axi_aclk : in std_logic;
s01_axi_aresetn : in std_logic;
s01_axi_awaddr : in std_logic_vector(C_S01_AXI_ADDR_WIDTH-1 downto 0);
s01_axi_awprot : in std_logic_vector(2 downto 0);
s01_axi_awvalid : in std_logic;
s01_axi_awready : out std_logic;
s01_axi_wdata : in std_logic_vector(C_S01_AXI_DATA_WIDTH-1 downto 0);
s01_axi_wstrb : in std_logic_vector((C_S01_AXI_DATA_WIDTH/8)-1 downto 0);
s01_axi_wvalid : in std_logic;
s01_axi_wready : out std_logic;
s01_axi_bresp : out std_logic_vector(1 downto 0);
s01_axi_bvalid : out std_logic;
s01_axi_bready : in std_logic;
s01_axi_araddr : in std_logic_vector(C_S01_AXI_ADDR_WIDTH-1 downto 0);
s01_axi_arprot : in std_logic_vector(2 downto 0);
s01_axi_arvalid : in std_logic;
s01_axi_arready : out std_logic;
s01_axi_rdata : out std_logic_vector(C_S01_AXI_DATA_WIDTH-1 downto 0);
s01_axi_rresp : out std_logic_vector(1 downto 0);
s01_axi_rvalid : out std_logic;
s01_axi_rready : in std_logic;
-- Ports of Axi Master Bus Interface M01_AXI
-- m01_axi_init_axi_txn : in std_logic;
-- m01_axi_error : out std_logic;
-- m01_axi_txn_done : out std_logic;
m01_axi_aclk : in std_logic;
m01_axi_aresetn : in std_logic;
m01_axi_awaddr : out std_logic_vector(C_M01_AXI_ADDR_WIDTH-1 downto 0);
m01_axi_awprot : out std_logic_vector(2 downto 0);
m01_axi_awvalid : out std_logic;
m01_axi_awready : in std_logic;
m01_axi_wdata : out std_logic_vector(C_M01_AXI_DATA_WIDTH-1 downto 0);
m01_axi_wstrb : out std_logic_vector(C_M01_AXI_DATA_WIDTH/8-1 downto 0);
m01_axi_wvalid : out std_logic;
m01_axi_wready : in std_logic;
m01_axi_bresp : in std_logic_vector(1 downto 0);
m01_axi_bvalid : in std_logic;
m01_axi_bready : out std_logic;
m01_axi_araddr : out std_logic_vector(C_M01_AXI_ADDR_WIDTH-1 downto 0);
m01_axi_arprot : out std_logic_vector(2 downto 0);
m01_axi_arvalid : out std_logic;
m01_axi_arready : in std_logic;
m01_axi_rdata : in std_logic_vector(C_M01_AXI_DATA_WIDTH-1 downto 0);
m01_axi_rresp : in std_logic_vector(1 downto 0);
m01_axi_rvalid : in std_logic;
m01_axi_rready : out std_logic
);
end Syma_Ctrl_core_v1_1;
architecture arch_imp of Syma_Ctrl_core_v1_1 is
signal m01_axi_init_axi_txn : std_logic;
signal m01_axi_txn_done : std_logic;
signal m01_axi_spi_data : std_logic_vector(7 downto 0);
signal m01_axi_spi_addr : std_logic_vector(7 downto 0);
signal m01_axi_error : std_logic;
signal s00_axi_cr : std_logic_vector(7 downto 0);
signal s00_axi_sr : std_logic_vector(7 downto 0);
signal s00_axi_flight : std_logic_vector(31 downto 0);
-- component declaration
component Syma_Ctrl_core_v1_1_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
S_AXI_CR : out std_logic_vector(7 downto 0);
S_AXI_SR : in std_logic_vector(7 downto 0);
S_AXI_FLIGHT : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component Syma_Ctrl_core_v1_1_S00_AXI;
component Syma_Ctrl_core_v1_1_S01_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
PPM_INPUT : in std_logic;
SAMPLE_CLOCK : in std_logic;
INTR_SINGLE : out std_logic;
INTR_COMPLETE: out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component Syma_Ctrl_core_v1_1_S01_AXI;
component Syma_Ctrl_core_v1_1_M01_AXI is
generic (
C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
C_M_AXI_ADDR_WIDTH : integer := 32;
C_M_AXI_DATA_WIDTH : integer := 32;
C_M_TRANSACTIONS_NUM : integer := 4
);
port (
INIT_AXI_TXN : in std_logic;
ERROR : out std_logic;
TXN_DONE : out std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
M_AXI_SPI_DATA : in std_logic_vector(7 downto 0);
M_AXI_SPI_ADDR : in std_logic_vector(7 downto 0)
);
end component Syma_Ctrl_core_v1_1_M01_AXI;
component spi_timer is
Port (
clk : in std_logic;
axi_done : std_logic;
axi_start : out std_logic;
axi_data : out std_logic_vector (7 downto 0);
axi_addr : out std_logic_vector (7 downto 0);
slave_cr : in std_logic_vector (7 downto 0);
slave_sr : out std_logic_vector (7 downto 0);
slave_flight : in std_logic_vector (31 downto 0);
ss_init : out std_logic := '0'); -- ss init signal needed by transmitter module, logical or with ss in board design
end component;
begin
-- Instantiation of Axi Bus Interface S00_AXI
Syma_Ctrl_core_v1_1_S00_AXI_inst : Syma_Ctrl_core_v1_1_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
S_AXI_CR => s00_axi_cr,
S_AXI_SR => s00_axi_sr,
S_AXI_FLIGHT => s00_axi_flight,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Instantiation of Axi Bus Interface S01_AXI
Syma_Ctrl_core_v1_1_S01_AXI_inst : Syma_Ctrl_core_v1_1_S01_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S01_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S01_AXI_ADDR_WIDTH
)
port map (
PPM_INPUT => ppm_signal_in,
SAMPLE_CLOCK => sample_clk,
INTR_SINGLE => ppm_irq_single,
INTR_COMPLETE => ppm_irq_complete,
S_AXI_ACLK => s01_axi_aclk,
S_AXI_ARESETN => s01_axi_aresetn,
S_AXI_AWADDR => s01_axi_awaddr,
S_AXI_AWPROT => s01_axi_awprot,
S_AXI_AWVALID => s01_axi_awvalid,
S_AXI_AWREADY => s01_axi_awready,
S_AXI_WDATA => s01_axi_wdata,
S_AXI_WSTRB => s01_axi_wstrb,
S_AXI_WVALID => s01_axi_wvalid,
S_AXI_WREADY => s01_axi_wready,
S_AXI_BRESP => s01_axi_bresp,
S_AXI_BVALID => s01_axi_bvalid,
S_AXI_BREADY => s01_axi_bready,
S_AXI_ARADDR => s01_axi_araddr,
S_AXI_ARPROT => s01_axi_arprot,
S_AXI_ARVALID => s01_axi_arvalid,
S_AXI_ARREADY => s01_axi_arready,
S_AXI_RDATA => s01_axi_rdata,
S_AXI_RRESP => s01_axi_rresp,
S_AXI_RVALID => s01_axi_rvalid,
S_AXI_RREADY => s01_axi_rready
);
-- Instantiation of Axi Bus Interface M01_AXI
Syma_Ctrl_core_v1_1_M01_AXI_inst : Syma_Ctrl_core_v1_1_M01_AXI
generic map (
C_M_START_DATA_VALUE => C_M01_AXI_START_DATA_VALUE,
C_M_TARGET_SLAVE_BASE_ADDR => C_M01_AXI_TARGET_SLAVE_BASE_ADDR,
C_M_AXI_ADDR_WIDTH => C_M01_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M01_AXI_DATA_WIDTH,
C_M_TRANSACTIONS_NUM => C_M01_AXI_TRANSACTIONS_NUM
)
port map (
M_AXI_SPI_DATA => m01_axi_spi_data,
M_AXI_SPI_ADDR => m01_axi_spi_addr,
INIT_AXI_TXN => m01_axi_init_axi_txn,
ERROR => m01_axi_error,
TXN_DONE => m01_axi_txn_done,
M_AXI_ACLK => m01_axi_aclk,
M_AXI_ARESETN => m01_axi_aresetn,
M_AXI_AWADDR => m01_axi_awaddr,
M_AXI_AWPROT => m01_axi_awprot,
M_AXI_AWVALID => m01_axi_awvalid,
M_AXI_AWREADY => m01_axi_awready,
M_AXI_WDATA => m01_axi_wdata,
M_AXI_WSTRB => m01_axi_wstrb,
M_AXI_WVALID => m01_axi_wvalid,
M_AXI_WREADY => m01_axi_wready,
M_AXI_BRESP => m01_axi_bresp,
M_AXI_BVALID => m01_axi_bvalid,
M_AXI_BREADY => m01_axi_bready,
M_AXI_ARADDR => m01_axi_araddr,
M_AXI_ARPROT => m01_axi_arprot,
M_AXI_ARVALID => m01_axi_arvalid,
M_AXI_ARREADY => m01_axi_arready,
M_AXI_RDATA => m01_axi_rdata,
M_AXI_RRESP => m01_axi_rresp,
M_AXI_RVALID => m01_axi_rvalid,
M_AXI_RREADY => m01_axi_rready
);
-- Add user logic here
spi_timer_0 : spi_timer
port map (
clk => m01_axi_aclk,
axi_done => m01_axi_txn_done,
axi_start => m01_axi_init_axi_txn,
axi_data => m01_axi_spi_data,
axi_addr => m01_axi_spi_addr,
slave_cr => s00_axi_cr,
slave_sr => s00_axi_sr,
slave_flight => s00_axi_flight,
ss_init => l_ss_init
);
d_axi_done <= m01_axi_txn_done;
d_axi_start <= m01_axi_init_axi_txn;
d_axi_data <= m01_axi_spi_data;
d_axi_addr <= m01_axi_spi_addr;
d_slave_cr <= s00_axi_cr;
d_slave_sr <= s00_axi_sr;
d_slave_flight <= s00_axi_flight;
-- User logic ends
end arch_imp;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/daf00b91/hdl/src/vhdl/ipif_pkg.vhd | 24 | 55293 | -- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
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-- ** covered by a separate agreement. **
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-- ** any rights you may require for your implementation. **
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-- ** but not limited to any warranties or representations that this **
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-- ** code and therefore cannot answer specific questions related **
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-- ** code IP shall only address issues and questions related **
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-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function log2(x : natural) return integer;
function clog2(x : positive) return natural;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
| gpl-2.0 |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_i2c_arb/i2c_arbiter_hotone_dec.vhd | 1 | 2879 | -------------------------------------------------------------------------------
-- Title : I2C Bus Arbiter Hotone Decoder
-- Project : White Rabbit Project
-------------------------------------------------------------------------------
-- File : i2c_arbiter_hotone_dec.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2015-08-06
-- Last update: 2015-08-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This component allows to share a single I2C bus for many masters in a simple
-- way.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2015 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity i2c_arbiter_hotone_dec is
generic (
g_num_inputs : natural range 2 to 32 := 2
);
port (
-- Clock & Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
enable_i : in std_logic;
start_state_i : in std_logic_vector(g_num_inputs-1 downto 0);
input_enabled_o : out std_logic;
input_idx_enabled_o : out integer range 0 to g_num_inputs-1
);
end i2c_arbiter_hotone_dec;
architecture struct of i2c_arbiter_hotone_dec is
begin
main: process(clk_i)
variable idx : integer := -1;
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
input_enabled_o <= '0';
input_idx_enabled_o <= 0;
else
if enable_i = '1' then
idx := -1;
for I in g_num_inputs-1 downto 0 loop
if start_state_i(I) = '1' then
idx := I;
end if;
end loop;
if idx = -1 then
input_enabled_o <= '0';
input_idx_enabled_o <= 0;
else
input_enabled_o <= '1';
input_idx_enabled_o <= idx;
end if;
end if;
end if;
end if;
end process main;
end struct;
| gpl-2.0 |
INTI-CMNB/Lattuino_IP_Core | Work/pm_pkg.vhdl | 1 | 8052 | ------------------------------------------------------------------------------
---- ----
---- Lattuino program memories and peripherals package ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This is a package with the PMs used for Lattuino. ----
---- It also includes the Lattuino peripherals. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL v2 or newer license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: PrgMems (Package) ----
---- File name: pm_pkg.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: lattuino ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: iCE40HX4K-TQ144 ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Lattice iCECube2 2016.02.27810 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package PrgMems is
component lattuino_1_blPM_8 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end component lattuino_1_blPM_8;
component lattuino_1_blPM_4 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end component lattuino_1_blPM_4;
component lattuino_1_blPM_2 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end component lattuino_1_blPM_2;
component lattuino_1_blPM_2S is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end component lattuino_1_blPM_2S;
component TMCounter is
generic(
CNT_PRESC : natural:=24;
ENA_TMR : std_logic:='1');
port(
-- WISHBONE signals
wb_clk_i : in std_logic; -- Clock
wb_rst_i : in std_logic; -- Reset input
wb_adr_i : in std_logic_vector(2 downto 0); -- Adress bus
wb_dat_o : out std_logic_vector(7 downto 0); -- DataOut Bus
wb_dat_i : in std_logic_vector(7 downto 0); -- DataIn Bus
wb_we_i : in std_logic; -- Write Enable
wb_stb_i : in std_logic; -- Strobe
wb_ack_o : out std_logic; -- Acknowledge
pwm_o : out std_logic_vector(5 downto 0); -- 6 PWMs
pwm_e_o : out std_logic_vector(5 downto 0)); -- Pin enable for the PWMs
end component TMCounter;
component TM16bits is
generic(
CNT_PRESC : natural:=24;
ENA_TMR : std_logic:='1');
port(
-- WISHBONE signals
wb_clk_i : in std_logic; -- Clock
wb_rst_i : in std_logic; -- Reset input
wb_adr_i : in std_logic_vector(0 downto 0); -- Adress bus
wb_dat_o : out std_logic_vector(7 downto 0); -- DataOut Bus
wb_dat_i : in std_logic_vector(7 downto 0); -- DataIn Bus
wb_we_i : in std_logic; -- Write Enable
wb_stb_i : in std_logic; -- Strobe
wb_ack_o : out std_logic; -- Acknowledge
-- Interface
irq_req_o : out std_logic;
irq_ack_i : in std_logic);
end component TM16bits;
component AD_Conv is
generic(
DIVIDER : positive:=12;
INTERNAL_CLK : std_logic:='1'; -- not boolean for Verilog compat
ENABLE : std_logic:='1'); -- not boolean for Verilog compat
port(
-- WISHBONE signals
wb_clk_i : in std_logic; -- Clock
wb_rst_i : in std_logic; -- Reset input
wb_adr_i : in std_logic_vector(0 downto 0); -- Adress bus
wb_dat_o : out std_logic_vector(7 downto 0); -- DataOut Bus
wb_dat_i : in std_logic_vector(7 downto 0); -- DataIn Bus
wb_we_i : in std_logic; -- Write Enable
wb_stb_i : in std_logic; -- Strobe
wb_ack_o : out std_logic; -- Acknowledge
-- SPI rate (2x)
-- Note: with 2 MHz spi_ena_i we get 1 MHz SPI clock => 55,6 ks/s
spi_ena_i: in std_logic; -- 2xSPI clock
-- A/D interface
ad_ncs_o : out std_logic; -- SPI /CS
ad_clk_o : out std_logic; -- SPI clock
ad_din_o : out std_logic; -- SPI A/D Din (MOSI)
ad_dout_i: in std_logic); -- SPI A/D Dout (MISO)
end component AD_Conv;
end package PrgMems;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_mode_0_module.vhd | 1 | 92630 | --
---- SPI Module - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_0_module.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg;
use lib_pkg_v1_0.lib_pkg.log2;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------:
-- C_SCK_RATIO -- 2, 4, 16, 32, , , , 1024, 2048 SPI
-- clock ratio (16*N), where N=1,2,3...
-- C_SPI_NUM_BITS_REG -- Width of SPI Control register
-- in this module
-- C_NUM_SS_BITS -- Total number of SS-bits
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- OTHER INTERFACE
-- Slave_MODF_strobe -- Slave mode fault strobe
-- MODF_strobe -- Mode fault strobe
-- SR_3_MODF -- Mode fault error flag
-- SR_5_Tx_Empty -- Transmit Empty
-- Control_Reg -- Control Register
-- Slave_Select_Reg -- Slave Select Register
-- Transmit_Data -- Data Transmit Register Interface
-- Receive_Data -- Data Receive Register Interface
-- SPIXfer_done -- SPI transfer done flag
-- DTR_underrun -- DTR underrun generation signal
-- SPI INTERFACE
-- SCK_I -- SPI Bus Clock Input
-- SCK_O_reg -- SPI Bus Clock Output
-- SCK_T -- SPI Bus Clock 3-state Enable
-- (3-state when high)
-- MISO_I -- Master out,Slave in Input
-- MISO_O -- Master out,Slave in Output
-- MISO_T -- Master out,Slave in 3-state Enable
-- MOSI_I -- Master in,Slave out Input
-- MOSI_O -- Master in,Slave out Output
-- MOSI_T -- Master in,Slave out 3-state Enable
-- SPISEL -- Local SPI slave select active low input
-- has to be initialzed to VCC
-- SS_I -- Input of slave select vector
-- of length N input where there are
-- N SPI devices,but not connected
-- SS_O -- One-hot encoded,active low slave select
-- vector of length N ouput
-- SS_T -- Single 3-state control signal for
-- slave select vector of length N
-- (3-state when high)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_mode_0_module is
generic
(
--C_SPI_MODE : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_USE_STARTUP : integer;
C_SPICR_REG_WIDTH : integer;
C_SUB_FAMILY : string;
C_FIFO_EXIST : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
----------------------
-- Control Reg is 10-bit wide
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
Slave_MODF_strobe : out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
DTR_underrun : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
MISO_I : in std_logic;
MISO_O : out std_logic;
MISO_T : out std_logic;
MOSI_I : in std_logic;
MOSI_O : out std_logic;
MOSI_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
control_bit_7_8 : in std_logic_vector(0 to 1);
Mst_N_Slv_mode : out std_logic;
Rx_FIFO_Full : in std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic;
DRR_Overrun_reg : out std_logic;
tx_cntr_xfer_done : out std_logic
);
end qspi_mode_0_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_mode_0_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function Declarations
---------------------------------------------------------------------
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
-- coverage off
return 2;
-- coverage on
end if;
end spcl_log2;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector
(COUNT_WIDTH downto 0)
:= (others => '0');
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal Serial_Dout : std_logic;
signal Serial_Din : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_Slave_MODF_Strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal Loading_SR_Reg_int : std_logic;
signal sck_i_d1 : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal rising_edge_sck_i : std_logic;
signal falling_edge_sck_i : std_logic;
signal edge_sck_i : std_logic;
signal MODF_strobe_int : std_logic;
signal master_tri_state_en_control: std_logic;
signal slave_tri_state_en_control: std_logic;
-- following signals are added for use in variouos clock ratio modes.
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
-- added synchronization signals for SPISEL and SCK_I
signal SPISEL_sync : std_logic;
signal SCK_I_sync : std_logic;
-- following register are declared for making data path clear in different modes
signal rx_shft_reg_s : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0110 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal sck_fe1 : std_logic;
signal sck_d21 : std_logic:='0';
signal sck_d11 : std_logic:='0';
signal SCK_O_1 : std_logic:='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal serial_dout_int : std_logic;
--
attribute IOB : string;
--attribute IOB of SPI_TRISTATE_CONTROL_II : label is "true";
attribute IOB of SPI_TRISTATE_CONTROL_III : label is "false";
--attribute IOB of SPI_TRISTATE_CONTROL_IV : label is "true";
attribute IOB of SPI_TRISTATE_CONTROL_V : label is "false";
--attribute IOB of OTHER_RATIO_GENERATE : label is "true";
--attribute IOB of SCK_I_REG : label is "true";
--attribute IOB of SPISEL_REG : label is "true";
signal Mst_Trans_inhibit_d1, Mst_Trans_inhibit_pulse : std_logic;
signal no_slave_selected : std_logic;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
TRANSFER_OKAY,
TEMP_TRANSFER_OKAY
);
signal spi_cntrl_ps: STATE_TYPE;
signal spi_cntrl_ns: STATE_TYPE;
signal stop_clock_reg : std_logic;
signal stop_clock : std_logic;
signal Rx_FIFO_Full_reg, DRR_Overrun_reg_int : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal SR_5_Tx_Empty_d1 : std_logic;
signal SR_5_Tx_Empty_pulse: std_logic;
signal SR_5_Tx_comeplete_Empty : std_logic;
signal falling_edge_sck_i_d1, rising_edge_sck_i_d1 : std_logic;
signal spisel_d2 : std_logic;
signal xfer_done_fifo_0 : std_logic;
signal rst_xfer_done_fifo_0 : std_logic;
-------------------------------------------------------------------------------
-- Architecture Starts
-------------------------------------------------------------------------------
begin
--------------------------------------------------
LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----------------------------------------
TX_EMPTY_MODE_0_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) or
(transfer_start_pulse = '1') or
(rst_xfer_done_fifo_0 = '1')then
xfer_done_fifo_0 <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
xfer_done_fifo_0 <= '1';
end if;
end if;
end process TX_EMPTY_MODE_0_P;
------------------------------
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
-----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv,
stop_clock_reg,
spi_cntrl_ps,
no_slave_selected,
SR_5_Tx_Empty,
SPIXfer_done_int_pulse,
transfer_start_pulse,
xfer_done_fifo_0
)
begin
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
stop_clock <= '0';
spi_cntrl_ns <= TRANSFER_OKAY;
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
if(no_slave_selected = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
stop_clock <= xfer_done_fifo_0;
if (no_slave_selected = '1')then
spi_cntrl_ns <= IDLE;
--code coverage -- elsif(SPIXfer_done_int_pulse='1')then
--code coverage -- stop_clock <= SR_5_Tx_Empty;
--code coverage -- spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
-----------------------------------------------
end generate LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN;
-------------------------------------------------------------------------------
LOCAL_TX_EMPTY_FIFO_12_GEN: if C_FIFO_EXIST /= 0 generate
-----
begin
-----
xfer_done_fifo_0 <= '0';
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Rx_FIFO_Full_reg <= '0';
elsif(reset_RcFIFO_ptr_to_spi = '1') or (DRR_Overrun_reg_int = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(SPIXfer_done_int_pulse = '1')and (Rx_FIFO_Full = '1') then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv ,
stop_clock_reg ,
spi_cntrl_ps ,
no_slave_selected ,
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse ,
transfer_start_pulse ,
SPIXfer_done_int_pulse_d2,
SR_5_Tx_comeplete_Empty,
Loop_mode
)is
-----
begin
-----
stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
spi_cntrl_ns <= TRANSFER_OKAY;
stop_clock <= '0';
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
--if(no_slave_selected = '1')then
if(SR_5_Tx_comeplete_Empty = '1' and
SPIXfer_done_int_pulse_d2 = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if(SR_5_Tx_comeplete_Empty='1')then
-- stop_clock <= xfer_done_fifo_0;
if (Loop_mode = '1' and
SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
elsif(no_slave_selected = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
--stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
----------------------------------------
----------------------------------------
end generate LOCAL_TX_EMPTY_FIFO_12_GEN;
-----------------------------------------
SR_5_TX_EMPTY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SR_5_Tx_Empty_d1 <= '0';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
end if;
end if;
end process SR_5_TX_EMPTY_PROCESS;
----------------------------------
SR_5_Tx_Empty_pulse <= SR_5_Tx_Empty_d1 and not (SR_5_Tx_Empty);
----------------------------------
-------------------------------------------------------------------------------
-- Combinatorial operations
-------------------------------------------------------------------------------
-----------------------------------------------------------
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
Mst_N_Slv_mode <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
-----------------------------------------------------------
MOSI_O <= Serial_Dout;
MISO_O <= Serial_Dout;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0') and --no mode fault
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_II : Tri-state register for SCK_T, ideal state-deactive
SPI_TRISTATE_CONTROL_II: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_III: tri-state register for MOSI, ideal state-deactive
SPI_TRISTATE_CONTROL_III: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MOSI_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_IV: tri-state register for SS,ideal state-deactive
SPI_TRISTATE_CONTROL_IV: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--* -------------------------------------------------------------------------------
--* -- SLAVE_TRIST_EN_PROCESS : If slave mode, then make tristate enabled
--* ---------------------------
slave_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='0') and -- decides master/slave
(control_bit_7_8(1)='1') and -- decide the spi_en
(SPISEL_sync = '0') and
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_V: tri-state register for MISO, ideal state-deactive
SPI_TRISTATE_CONTROL_V: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MISO_T,
C => Bus2IP_Clk,
D => slave_tri_state_en_control
);
-------------------------------------------------------------------------------
DTR_COMPLETE_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if(SR_5_Tx_Empty = '1' and SPIXfer_done_int_pulse = '1')then
SR_5_Tx_comeplete_Empty <= '1';
elsif(SR_5_Tx_Empty = '0')then
SR_5_Tx_comeplete_Empty <= '0';
end if;
end if;
end process DTR_COMPLETE_EMPTY_P;
---------------------------------
DTR_UNDERRUN_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
--if(SPIXfer_done_int_pulse_d2 = '1') then
DTR_underrun <= '1';
--end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_0_GEN;
DTR_UNDERRUN_FIFO_EXIST_GEN: if C_FIFO_EXIST /= 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
if(SPIXfer_done_int_pulse = '1') then
DTR_underrun <= '1';
end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_EXIST_GEN;
-------------------------------------------------------------------------------
-- SPISEL_SYNC: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
SPISEL_REG: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
---- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-------------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
spisel_d2 <= '1';
else
spisel_d1 <= SPISEL_sync;
spisel_d2 <= spisel_d1;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
--SPISEL_DELAY_1CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d1,
-- C => Bus2IP_Clk,
-- D => SPISEL_sync
-- );
--SPISEL_DELAY_2CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d2,
-- C => Bus2IP_Clk,
-- D => spisel_d1
-- );
---- spisel pulse generating logic
---- this one clock cycle pulse will be available for data loading into
---- shift register
--spisel_pulse <= (not SPISEL_sync) and spisel_d1;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not spisel_d1) and spisel_d2;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- ----------------|___-- spisel_d2
-- _____________|--|__ -- SPISEL_pulse_op
SPISEL_pulse_op <= spisel_pulse;
SPISEL_d1_reg <= spisel_d2;
-------------------------------------------------------------------------------
--SCK_I_SYNC: first synchronize incomming signal
-------------
SCK_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => SCK_I_sync,
C => Bus2IP_Clk,
D => SCK_I
);
------------------------------------------------------------------
-- SCK_I_DELAY_1CLK_PROCESS : Detect active SCK edge in slave mode on +ve edge
SCK_I_DELAY_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
sck_i_d1 <= '0';
else
sck_i_d1 <= SCK_I_sync;
end if;
end if;
end process SCK_I_DELAY_1CLK_PROCESS;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_4_GEN: to synchronise the incoming clock signal in
-- slave mode in SCK ratio = 4
RISING_EDGE_CLK_RATIO_4_GEN : if C_SCK_RATIO = 4 generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I and (not(SCK_I_sync)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I) and SCK_I_sync) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_4_GEN;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_OTHERS_GEN: Due to timing crunch, in SCK> 4 mode,
-- the incoming clock signal cant be synchro
-- -nized with internal AXI clock.
-- slave mode operation on SCK_RATIO=2 isn't
-- supported in the core.
RISING_EDGE_CLK_RATIO_OTHERS_GEN: if ((C_SCK_RATIO /= 2) and (C_SCK_RATIO /= 4))
generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I_sync and (not(sck_i_d1)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I_sync) and sck_i_d1) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_OTHERS_GEN;
-------------------------------------------------------------------------------
-- combine rising edge as well as falling edge as a single signal
edge_sck_i <= rising_edge_sck_i or falling_edge_sck_i;
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
Mst_N_Slv = '1' and -- If Master Mode
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1'
)
) or
(
Mst_N_Slv = '0' and -- If Slave Mode
(
SPI_En = '0' -- enable not asserted or
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
--if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1') or
-- (SPIXfer_done_int_pulse_d2='1')) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
---------------------------------------------------------------------------------
---- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
----------------------------
--TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- --elsif (transfer_start_pulse = '1') then
-- -- SPIXfer_done_int <= '0';
-- elsif(and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) = '1') then --(Count(COUNT_WIDTH) = '1') then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
--end process TRANSFER_DONE_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
begin
-----
TRANSFER_DONE_8: if C_NUM_TRANSFER_BITS = 8 generate
TRANSFER_DONE_PROCESS_8: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_8;
end generate TRANSFER_DONE_8;
TRANSFER_DONE_16: if C_NUM_TRANSFER_BITS = 16 generate
TRANSFER_DONE_PROCESS_16: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_16;
end generate TRANSFER_DONE_16;
TRANSFER_DONE_32: if C_NUM_TRANSFER_BITS = 32 generate
TRANSFER_DONE_PROCESS_32: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '1' and
Count(COUNT_WIDTH-6) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_32;
end generate TRANSFER_DONE_32;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
rx_shft_reg <= rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= Shift_Reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= Shift_Reg;
end if;
end if;
else
if(SPIXfer_done_int_pulse_d2 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-- Done strobe delayed to match receive data
SPIXfer_done <= SPIXfer_done_int_pulse_d3;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d3; -- SPIXfer_done_int_pulse_d1;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d3;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-- RX_DATA_GEN_OTHER_RATIOS: This logic is for other SCK ratios than
---------------------------- C_SCK_RATIO =2
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
begin
FIFO_PRESENT_GEN: if C_FIFO_EXIST = 1 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '1') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
then
SPIXfer_done_int <= '1';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '0') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or
-- transfer_start_pulse = '1' or
-- SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- elsif(Mst_N_Slv = '1') and
-- --and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
-- and
-- Count_trigger = '1'
-- then
-- SPIXfer_done_int <= '1';
-- elsif--(Mst_N_Slv = '0') and
-- and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
-- if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
-- end if;
-- end process TRANSFER_DONE_PROCESS;
end generate FIFO_PRESENT_GEN;
--------------------------------------------------------------
FIFO_ABSENT_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and
((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
end generate FIFO_ABSENT_GEN;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
-- the below mux is applicable only for Master mode of SPI.
rx_shft_reg <=
rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else
rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (Mst_N_Slv = '1') then -- in master mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
elsif(Mst_N_Slv = '0') then -- in slave mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg_s
(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg_s;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or
SPIXfer_done_int_pulse_d2 or
spisel_pulse;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
--attribute IOB : string;
--attribute IOB of MOSI_I_REG : label is "true";
begin
-----
-------------------------------------------------------------------------------
-- OTHER_RATIO_MISO_I_REG_IOB_GEN: Push the IO1_I register in IOB
-- --------------
-- Only when the targeted family is 7-series or spartan 6
-- ir-respective of C_USE_STARTUP parameter
-- OTHER_RATIO_MISO_I_REG_IOB_GEN: if(C_SUB_FAMILY = "virtex7"
-- or
-- C_SUB_FAMILY = "kintex7"
-- or
-- C_SUB_FAMILY = "artix7"
-- --or
-- --C_SUB_FAMILY = "spartan6"
-- )
-- -- or
-- -- (
-- -- C_USE_STARTUP = 0
-- -- and
-- -- C_SUB_FAMILY = "virtex6"
-- -- )
-- generate
-- -- attribute IOB : string;
-- --attribute IOB of MISO_I_REG : label is "true";
-- -----
-- begin
-----
-- MISO_I_REG: component FD
-- generic map
-- (
-- INIT => '0'
-- )
-- port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => MISO_I
-- );
miso_i_sync <= MISO_I;
--end generate OTHER_RATIO_MISO_I_REG_IOB_GEN;
-----------------------------------------------------------------
-- OTHER_RATIO_MISO_I_REG_NO_IOB_GEN: If C_USE_STARTUP is used and family is virtex6, then
-- IO1_I is registered only, but it is not pushed in IOB.
-- this is due to STARTUP block in V6 is having DINSPI interface available for IO1_I.
-- OTHER_RATIO_MISO_I_REG_NO_IOB_GEN: if(C_USE_STARTUP = 1
-- and
-- C_SUB_FAMILY = "virtex6"
-- ) generate
-------
--begin
-------
--MISO_I_REG: component FD
--generic map
-- (
-- INIT => '0'
-- )
--port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => MISO_I
-- );
--end generate OTHER_RATIO_MISO_I_REG_NO_IOB_GEN;
-----------------------------------------------------------------
-- MOSI_I_REG: component FD
-- generic map
-- (
-- INIT => '0'
-- )
-- port map
-- (
-- Q => mosi_i_sync,
-- C => Bus2IP_Clk,
-- D => MOSI_I
-- );
mosi_i_sync <= MOSI_I;
------------------------------
LOOP_BACK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '0' or Soft_Reset_op = RESET_ACTIVE) then
serial_dout_int <= '0';
elsif(Loop_mode = '1') then
serial_dout_int <= Serial_Dout;
end if;
end if;
end process LOOP_BACK_PROCESS;
------------------------------
-- EXTERNAL_INPUT_OR_LOOP_PROCESS: The logic below provides MUXed input to
-- serial_din input.
EXTERNAL_INPUT_OR_LOOP_PROCESS: process(Loop_mode,
Mst_N_Slv,
mosi_i_sync,
miso_i_sync,
serial_dout_int
)is
-----
begin
-----
if(Mst_N_Slv = '1' )then
if(Loop_mode = '1')then
Serial_Din <= serial_dout_int;
else
Serial_Din <= miso_i_sync;
end if;
else
Serial_Din <= mosi_i_sync;
end if;
end process EXTERNAL_INPUT_OR_LOOP_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Count <= (others => '0');
elsif (Mst_N_Slv = '1') then
if (SPIXfer_done_int = '1')or
(transfer_start = '0') or
(xfer_done_fifo_0 = '1') then
Count <= (others => '0');
elsif((Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0')) then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
elsif (Mst_N_Slv = '0') then
if ((transfer_start = '0') or (SPISEL_sync = '1')or
(spixfer_done_int = '1')) then
Count <= (others => '0');
elsif (edge_sck_i = '1') then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1') or
(Mst_N_Slv='0')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process SCK_SET_RESET_PROCESS;
------------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
DELAY_CLK: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and (transfer_start='1')) then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
--
sck_fe1 <= (not sck_d1) and sck_d2;
-- CAPT_RX_FE_MODE_01_10 : The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 01 and 10.
CAPT_RX_FE_MODE_01_10 : process(Bus2IP_Clk)
begin
--if rising_edge(Bus2IP_Clk) then
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0110 <= (others => '0');
elsif ((sck_fe1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif((Mst_N_Slv = '1')) then -- and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
-- Capture Data on even Count
elsif(--(transfer_start = '1') and
(Count(0) = '0') ) then
Serial_Dout <= Shift_Reg(0);
-- Shift Data on odd Count
elsif(--(transfer_start = '1') and
(Count(0) = '1') and
(Count_trigger_pulse = '1')) then
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & Serial_Din;
end if;
-- below mode is slave mode logic for SPI
elsif(Mst_N_Slv = '0') then
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
--if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(SR_5_Tx_Empty_pulse = '1' or SPIXfer_done_int = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif (transfer_start = '1') then
if((CPOL = '0' and CPHA = '0') or
(CPOL = '1' and CPHA = '1')) then
if(rising_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(falling_edge_sck_i = '1') then
--elsif(rising_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
elsif((CPOL = '0' and CPHA = '1') or
(CPOL = '1' and CPHA = '0')) then
--Serial_Dout <= Shift_Reg(0);
if(falling_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(rising_edge_sck_i = '1') then
--elsif(falling_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
end if;
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate OTHER_RATIO_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(transfer_start = '0') or
(SPIXfer_done_int = '1') or
(Mst_N_Slv = '0')) then
Count <= (others => '0');
--elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
elsif(Count(COUNT_WIDTH) = '0')then
if(CPHA = '0')then
if(CPOL = '0' and transfer_start_d1 = '1')then -- cpol = cpha = 00
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then -- cpol = cpha = 10
Count <= Count + 1;
end if;
else
if(CPOL = '1' and transfer_start_d1 = '1')then -- cpol = cpha = 11
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then-- cpol = cpha = 10
Count <= Count + 1;
end if;
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);-- xor Count(COUNT_WIDTH);
end if;
end if;
end process SCK_SET_RESET_PROCESS;
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
-- CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '0') then
-- sck_d1 <= sck_o_int;
-- sck_d2 <= sck_d1;
-- -- if (sck_rising_edge = '1') then
-- if (sck_d1 = '1') then
-- rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
-- (1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
-- end if;
-- end if;
-- end process CAPT_RX_FE_MODE_00_11;
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
-- sck_d3 <= sck_d2;
-- if (sck_rising_edge = '1') then
if (sck_d2 = '0') then
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
-- Falling egde pulse
sck_rising_edge <= sck_d2 and not sck_d1;
--
-- CAPT_RX_FE_MODE_01_10: the below logic captures data in SPI 01 or 10 mode.
---------------------------
CAPT_RX_FE_MODE_01_10: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d11 <= sck_o_in;
sck_d21 <= sck_d11;
if(CPOL = '1' and CPHA = '0') then
if ((sck_d1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
elsif((CPOL = '0') and (CPHA = '1')) then
if ((sck_fe1 = '0') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
sck_fe1 <= (not sck_d11) and sck_d21;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif(Mst_N_Slv = '1') then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif(--(transfer_start = '1') and
(Count(0) = '0') -- and
--(Count(COUNT_WIDTH) = '0')
) then -- Shift Data on even
Serial_Dout <= Shift_Reg(0);
elsif(--(transfer_start = '1') and
(Count(0) = '1')-- and
--(Count(COUNT_WIDTH) = '0')
) then -- Capture Data on odd
if(Loop_mode = '1') then -- Loop mode
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Dout;
else
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & MISO_I;
end if;
end if;
elsif(Mst_N_Slv = '0') then
-- Added to have consistent default value after reset
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
if(spisel_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= (others => '0');
Serial_Dout <= '0';
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate RATIO_OF_2_GENERATE;
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,CPHA,transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse
)
begin
-- if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)
begin
--if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv,
sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
-----
begin
-----
if((Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
-------------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,Mst_N_Slv,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF,
transfer_start_pulse)is
begin
if(Soft_Reset_op = RESET_ACTIVE) then
Loading_SR_Reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
((Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
) or
((Mst_N_Slv = '0') and --Slave configuration
((transfer_start_pulse = '1'))
)
)
)then
Loading_SR_Reg_int <= '1'; --Set flag
else
Loading_SR_Reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') or (xfer_done_fifo_0 = '1') then -- Tranfer not in progress
if(Manual_SS_mode = '0') then -- Auto SS assert
SS_O <= (others => '1');
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
end if;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and (Allow_MODF_Strobe = '1')) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
-------------------------------------------------------------------------------
-- SLAVE_MODF_STROBE_PROCESS : Strobe MODF signal when slave is addressed
-- but not enabled.
------------------------------
SLAVE_MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
Slave_MODF_strobe <= '0';
Allow_Slave_MODF_Strobe<= '1';
elsif((Mst_N_Slv = '0') and --In Slave mode
(SPI_En = '0') and --but not enabled
(SPISEL_sync = '0') and
(Allow_Slave_MODF_Strobe = '1')
) then
Slave_MODF_strobe <= '1';
Allow_Slave_MODF_Strobe <= '0';
else
Slave_MODF_strobe <= '0';
end if;
end if;
end process SLAVE_MODF_STROBE_PROCESS;
---------------------xxx------------------------------------------------------
end imp;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_cntrl_reg.vhd | 1 | 18470 | -------------------------------------------------------------------------------
-- qspi_cntrl_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_cntrl_reg.vhd
-- Version: v3.0
-- Description: control register module for axi quad spi. This module decides the
-- behavior of the core in master/slave, CPOL/CPHA etc modes.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- Width of the slave data bus
-- C_SPI_NUM_BITS_REG -- Width of SPI registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Wr_ce_reduce_ack_gen -- common write ack generation logic input
-- Bus2IP_SPICR_data -- Data written from the PLB bus
-- Bus2IP_SPICR_WrCE -- Write CE for control register
-- Bus2IP_SPICR_RdCE -- Read CE for control register
-- IP2Bus_SPICR_Data -- Data to be send on the bus
-- SPI MODULE INTERFACE
-- Control_Register_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_cntrl_reg is
generic
(
----------------------------
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
----------------------------
-- Number of bits in register, 10 for control reg - to match old version
C_SPI_NUM_BITS_REG : integer;
----------------------------
C_SPICR_REG_WIDTH : integer;
----------------------------
C_SPI_MODE : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Wr_ce_reduce_ack_gen : in std_logic;
Bus2IP_SPICR_WrCE : in std_logic;
Bus2IP_SPICR_RdCE : in std_logic;
Bus2IP_SPICR_data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- SPI module ports
SPICR_0_LOOP : out std_logic;
SPICR_1_SPE : out std_logic;
SPICR_2_MASTER_N_SLV : out std_logic;
SPICR_3_CPOL : out std_logic;
SPICR_4_CPHA : out std_logic;
SPICR_5_TXFIFO_RST : out std_logic;
SPICR_6_RXFIFO_RST : out std_logic;
SPICR_7_SS : out std_logic;
SPICR_8_TR_INHIBIT : out std_logic;
SPICR_9_LSB : out std_logic;
--------------------------
-- to Status Register
SPISR_1_LOOP_Back_Error : out std_logic;
SPISR_2_MSB_Error : out std_logic;
SPISR_3_Slave_Mode_Error : out std_logic;
-- SPISR_4_XIP_Mode_On : out std_logic;
SPISR_4_CPOL_CPHA_Error : out std_logic;
IP2Bus_SPICR_Data : out std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
Control_bit_7_8 : out std_logic_vector(0 to 1) --(7 to 8)
);
end qspi_cntrl_reg;
-------------------------------------------------------------------------------
-- Architecture
--------------------------------------
architecture imp of qspi_cntrl_reg is
-------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal SPICR_data_int : std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal SPICR_3_4_Reset : std_logic;
signal Control_bit_7_8_int : std_logic_vector(7 to 8);
signal temp_wr_ce : std_logic;
-----
begin
-----
----------------------------
-- Combinatorial operations
----------------------------
-- Control_Register_Data <= SPICR_data_int;
-------------------------------------------------------
SPICR_0_LOOP <= SPICR_data_int(C_SPICR_REG_WIDTH-1); -- as per the SPICR Fig 3 in DS this bit is @ 0th position
SPICR_1_SPE <= SPICR_data_int(C_SPICR_REG_WIDTH-2); -- as per the SPICR Fig 3 in DS this bit is @ 1st position
SPICR_2_MASTER_N_SLV <= SPICR_data_int(C_SPICR_REG_WIDTH-3); -- as per the SPICR Fig 3 in DS this bit is @ 2nd position
SPICR_3_CPOL <= SPICR_data_int(C_SPICR_REG_WIDTH-4); -- as per the SPICR Fig 3 in DS this bit is @ 3rd position
SPICR_4_CPHA <= SPICR_data_int(C_SPICR_REG_WIDTH-5); -- as per the SPICR Fig 3 in DS this bit is @ 4th position
SPICR_5_TXFIFO_RST <= SPICR_data_int(C_SPICR_REG_WIDTH-6); -- as per the SPICR Fig 3 in DS this bit is @ 5th position
SPICR_6_RXFIFO_RST <= SPICR_data_int(C_SPICR_REG_WIDTH-7); -- as per the SPICR Fig 3 in DS this bit is @ 6th position
SPICR_7_SS <= SPICR_data_int(C_SPICR_REG_WIDTH-8); -- as per the SPICR Fig 3 in DS this bit is @ 7th position
SPICR_8_TR_INHIBIT <= SPICR_data_int(C_SPICR_REG_WIDTH-9); -- as per the SPICR Fig 3 in DS this bit is @ 8th position
SPICR_9_LSB <= SPICR_data_int(C_SPICR_REG_WIDTH-10);-- as per the SPICR Fig 3 in DS this bit is @ 9th position
-------------------------------------------------------
SPISR_DUAL_MODE_STATUS_GEN : if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
----------------------------
--signal ored_SPICR_7_12 : std_logic;
begin
-----
--ored_SPICR_7_12 <= or_reduce(SPICR_data_int(7 to 12));
-- C_SPICR_REG_WIDTH is of 10 bit wide
SPISR_1_LOOP_Back_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-1);-- 9th bit in present SPICR
SPISR_2_MSB_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-C_SPICR_REG_WIDTH); -- 0th LSB bit in present SPICR
SPISR_3_Slave_Mode_Error <= not SPICR_data_int(C_SPICR_REG_WIDTH-3); -- Mst_n_Slv 7th bit in control register - default is slave mode of operation
SPISR_4_CPOL_CPHA_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-5) xor -- bit 5-CPHA and 6-CPOL in present SPICR
SPICR_data_int(C_SPICR_REG_WIDTH-4);-- CPOL-CPHA = 01 or 10 in control register
end generate SPISR_DUAL_MODE_STATUS_GEN;
----------------------------------------
SPISR_NO_DUAL_MODE_STATUS_GEN : if C_SPI_MODE = 0 generate
-------------------------------
begin
-----
SPISR_1_LOOP_Back_Error <= '0';
SPISR_2_MSB_Error <= '0';
SPISR_3_Slave_Mode_Error <= '0';
SPISR_4_CPOL_CPHA_Error <= '0';
end generate SPISR_NO_DUAL_MODE_STATUS_GEN;
-------------------------------------------
SPICR_REG_RD_GENERATE: for i in 0 to C_SPICR_REG_WIDTH-1 generate
-----
begin
-----
IP2Bus_SPICR_Data(i) <= SPICR_data_int(i) and Bus2IP_SPICR_RdCE;
end generate SPICR_REG_RD_GENERATE;
-----------------------------------
---------------------------------------------------------------
-- Bus2IP Data bit mapping - 0 to 21 - NA
-- 22 23 24 25 26 27 28 29 30 31
--
-- Control Register - 0 to 22 bit mapping
-- 0 1 2 3 4 5 6 7 8 9
-- LSB TRAN MANUAL RX FIFO TX FIFO CPHA CPOL MASTER SPE LOOP
-- INHI SLAVE RST RST
-- '0' '1' '1' '0' '0' '0' '0' '0' '0' '0'
-----------------------------------------------------
-- AXI Data 31 downto 0 |
-- valid bits in AXI start from LSB i.e. 0 |
-- Bus2IP_Data 0 to 31 |
-- **** IMP Starts **** |
-- This is 1 is to 1 mapping with reverse bit order.|
-- **** IMP Ends **** |
-- Bus2IP_Data 0 1 2 3 4 5 6 7 21 22--->31 |
-- Control Bits<-------NA--------> 0---->9 |
-----------------------------------------------------
--SPICR_NO_DUAL_MODE_WR_GEN: if C_SPI_MODE = 0 generate
---------------------------------
--begin
-----
-- SPICR_data_int(0 to 12) <= (others => '0');
--end generate SPICR_NO_DUAL_MODE_WR_GEN;
----------------------------------------------
temp_wr_ce <= wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE;
-- -- SPICR_REG_0_PROCESS : Control Register Write Operation for bit 0 - LSB
-- -----------------------------
-- Behavioral Code **
SPICR_REG_0_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(0) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(0) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH);-- after 100 ps;
end if;
end if;
end process SPICR_REG_0_PROCESS;
--------------------------------
CONTROL_REG_1_2_GENERATE: for i in 1 to 2 generate
------------------------
begin
-----
-- SPICR_REG_1_2_PROCESS : Control Register Write Operation for bit 1_2 - TRAN_INHI and MANUAL_SLAVE
-----------------------------
SPICR_REG_1_2_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(i) <= '1';
elsif((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_1_2_PROCESS;
----------------------------------
end generate CONTROL_REG_1_2_GENERATE;
--------------------------------------
-- the below reset signal is needed to de-assert the Tx/Rx FIFO reset signals.
SPICR_3_4_Reset <= (not Bus2IP_SPICR_WrCE) or Soft_Reset_op;
-- CONTROL_REG_3_4_GENERATE : Control Register Write Operation for bit 3_4 - Receive FIFO Reset and Transmit FIFO Reset
-----------------------------
CONTROL_REG_3_4_GENERATE: for i in 3 to 4 generate
-----
begin
-----
SPICR_REG_3_4_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (SPICR_3_4_Reset = RESET_ACTIVE) then
SPICR_data_int(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_3_4_PROCESS;
----------------------------------
end generate CONTROL_REG_3_4_GENERATE;
--------------------------------------
-- CONTROL_REG_5_9_GENERATE : Control Register Write Operation for bit 5:9 - CPHA, CPOL, MASTER, SPE, LOOP
-----------------------------
CONTROL_REG_5_9_GENERATE: for i in 5 to C_SPICR_REG_WIDTH-1 generate
-----
begin
-----
SPICR_REG_5_9_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_5_9_PROCESS;
----------------------------------
end generate CONTROL_REG_5_9_GENERATE;
--------------------------------------
--
-- SPICR_REG_78_GENERATE: This logic is newly added to register _T signals
-- ------------------------ in IOB. This logic simplifies the register method
-- for _T in IOB, without affecting functionality.
SPICR_REG_78_GENERATE: for i in 7 to 8 generate
-----
begin
-----
SPI_TRISTATE_CONTROL_I: component FDRE
port map
(
Q => Control_bit_7_8_int(i) ,-- out:
C => Bus2IP_Clk ,--: in
CE => Bus2IP_SPICR_WrCE ,--: in
R => Soft_Reset_op ,-- : in
D => Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i) --: in
);
end generate SPICR_REG_78_GENERATE;
-----------------------------------
Control_bit_7_8 <= Control_bit_7_8_int;
---------------------------------------
end imp;
--------------------------------------------------------------------------------
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/daf00b91/hdl/src/vhdl/slave_attachment.vhd | 10 | 23547 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/mul_592.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_592 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_592;
architecture augh of mul_592 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/vector.d/add_170.vhd | 2 | 796 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_170 is
port (
result : out std_logic_vector(8 downto 0);
in_a : in std_logic_vector(8 downto 0);
in_b : in std_logic_vector(8 downto 0)
);
end add_170;
architecture augh of add_170 is
signal carry_inA : std_logic_vector(10 downto 0);
signal carry_inB : std_logic_vector(10 downto 0);
signal carry_res : std_logic_vector(10 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(9 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2846.vhd | 4 | 1614 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2846.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity VARIABLE is
end VARIABLE;
ENTITY c13s09b00x00p99n01i02846ent IS
END c13s09b00x00p99n01i02846ent;
ARCHITECTURE c13s09b00x00p99n01i02846arch OF c13s09b00x00p99n01i02846ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02846 - Reserved word VARIABLE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02846arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc498.vhd | 4 | 2104 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc498.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p02n01i00498ent IS
END c03s02b02x00p02n01i00498ent;
ARCHITECTURE c03s02b02x00p02n01i00498arch OF c03s02b02x00p02n01i00498ent IS
type Month_name is (jan, dec);
type Date is
record
Day : integer range 1 to 31;
Month : Month_name;
Year : integer range 0 to 4000;
end record;
BEGIN
TESTING: PROCESS
variable k : Date;
BEGIN
k.Day := 16;
k.Month := jan;
k.Year := 1993;
assert NOT(k.Day=16 and k.Month=jan and k.Year =1993)
report "***PASSED TEST: c03s02b02x00p02n01i00498"
severity NOTE;
assert (k.Day=16 and k.Month=jan and k.Year =1993)
report "***FAILED TEST: c03s02b02x00p02n01i00498 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p02n01i00498arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2250.vhd | 4 | 1789 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2250.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02250ent IS
END c07s02b06x00p01n01i02250ent;
ARCHITECTURE c07s02b06x00p01n01i02250arch OF c07s02b06x00p01n01i02250ent IS
BEGIN
TESTING: PROCESS
-- array types.
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV: ADDRESS;
variable k : integer;
BEGIN
k := ADDRESSV rem NULL;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02250 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02250arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1552.vhd | 4 | 5227 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1552.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n03i01552ent IS
END c08s09b00x00p10n03i01552ent;
ARCHITECTURE c08s09b00x00p10n03i01552arch OF c08s09b00x00p10n03i01552ent IS
BEGIN
TESTING: PROCESS
-- enumerated type.
type COLORS is (RED, GREEN, BLUE, ORANGE, PINK, GRAY, YELLOW);
-- local variables
variable EXECUTED_ONCE : BOOLEAN;
variable LAST_INT : INTEGER;
variable LAST_COLOR : COLORS;
variable k : integer := 0;
BEGIN
-- 1. Test ascending and descending integer discrete ranges.
EXECUTED_ONCE := FALSE;
LAST_INT := INTEGER'LOW + 1;
for I in (INTEGER'LOW+1) to (INTEGER'LOW + 10) loop
-- Verify that the first value is correct.
if (not(EXECUTED_ONCE)) then
if (I /= (integer'low + 1)) then
k := 1;
end if;
assert (I = (INTEGER'LOW+1))
report "First value is bad.";
EXECUTED_ONCE := TRUE;
-- Otherwise, test that this value is to the right of the previous one.
else
if (integer'succ(last_int) /= I) then
k := 1;
end if;
assert (INTEGER'SUCC( LAST_INT ) = I)
report "Subsequent values are bad.";
LAST_INT := I;
end if;
end loop;
EXECUTED_ONCE := FALSE;
LAST_INT := INTEGER'HIGH - 1;
for I in (INTEGER'HIGH-1) downto (INTEGER'HIGH - 10) loop
-- Verify that the first value is correct.
if (not(EXECUTED_ONCE)) then
if (I /= integer'high-1) then
k := 1;
end if;
assert (I = (INTEGER'HIGH-1))
report "First value, second loop, is bad.";
EXECUTED_ONCE := TRUE;
-- Otherwise, test that this value is to the right of the previous one.
else
if (integer'pred(last_int) /= I) then
k := 1;
end if;
assert (INTEGER'PRED( LAST_INT ) = I)
report "Subsequent values, second loop, are bad.";
LAST_INT := I;
end if;
end loop;
-- 2. Test ascending and descending enumerated type ranges.
EXECUTED_ONCE := FALSE;
LAST_COLOR := COLORS'SUCC( COLORS'LOW );
for I in (COLORS'SUCC( COLORS'LOW )) to (COLORS'HIGH) loop
-- Verify that the first value is correct.
if (not(EXECUTED_ONCE)) then
if (I /= colors'succ(colors'low)) then
k := 1;
end if;
assert (I = (COLORS'SUCC( COLORS'LOW )))
report "First value, third loop, is bad.";
EXECUTED_ONCE := TRUE;
-- Otherwise, test that this value is to the right of the previous one.
else
if (colors'succ(last_color) /= I) then
k := 1;
end if;
assert (COLORS'SUCC( LAST_COLOR ) = I)
report "Subsequent values, third loop, are bad.";
LAST_COLOR := I;
end if;
end loop;
EXECUTED_ONCE := FALSE;
LAST_COLOR := COLORS'PRED( COLORS'HIGH );
for I in (COLORS'PRED( COLORS'HIGH )) downto (COLORS'LOW) loop
-- Verify that the first value is correct.
if (not(EXECUTED_ONCE)) then
if (I /= colors'pred(colors'high)) then
k := 1;
end if;
assert (I = (COLORS'PRED( COLORS'HIGH )))
report "First value, fourth loop, is bad.";
EXECUTED_ONCE := TRUE;
-- Otherwise, test that this value is to the right of the previous one.
else
if (colors'pred(last_color) /= I) then
k := 1;
end if;
assert (COLORS'PRED( LAST_COLOR ) = I)
report "Subsequent values, fourth loop, are bad.";
LAST_COLOR := I;
end if;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p10n03i01552"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p10n03i01552 - Each iteration of a loop statement with a for iteration scheme, the corresponding value of the discrete range is assigned to the loop parameter, these values are assigned in left to rigth order"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n03i01552arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_03.vhd | 4 | 2710 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 32;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
end package cpu_types;
package bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
end package bit_vector_unsigned_arithmetic;
package body bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
end package body bit_vector_unsigned_arithmetic;
-- code from book
package DMA_controller_types_and_utilities is
alias word is work.cpu_types.word;
alias address is work.cpu_types.address;
alias status_value is work.cpu_types.status_value;
alias "+" is work.bit_vector_unsigned_arithmetic."+"
[ bit_vector, bit_vector return bit_vector ];
-- . . .
end package DMA_controller_types_and_utilities;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3158.vhd | 4 | 2890 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3158.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p16n01i03158ent IS
END c05s03b00x00p16n01i03158ent;
ARCHITECTURE c05s03b00x00p16n01i03158arch OF c05s03b00x00p16n01i03158ent IS
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Use the implicit disconnect specification here.
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '1' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '0' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
assert NOT( SIG = '0' and ShouldBeTime = NOW )
report "***PASSED TEST: c05s03b00x00p16n01i03158"
severity NOTE;
assert ( SIG = '0' and ShouldBeTime = NOW )
report "***FAILED TEST: c05s03b00x00p16n01i03158 - Default disconnect specification test failed."
severity ERROR;
-- Define a second driver for SIG, just for kicks.
-- Should never get invoked. Not have an effect on the value.
SIG <= '0' after 10 ns;
wait;
END PROCESS TESTING;
END c05s03b00x00p16n01i03158arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2999.vhd | 4 | 1969 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2999.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p02n01i02999pkg is
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
end c02s06b00x00p02n01i02999pkg;
package body is --Failure here
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
begin
assert (I1 /= '1')
report "No failure on test" ;
assert (I3 /= 5)
report "No failure on test" ;
end PX;
end;
ENTITY c02s06b00x00p02n01i02999ent IS
END c02s06b00x00p02n01i02999ent;
ARCHITECTURE c02s06b00x00p02n01i02999arch OF c02s06b00x00p02n01i02999ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p02n01i02999 - Missing pcakage simple name."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p02n01i02999arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc547.vhd | 4 | 1730 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc547.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n03i00547ent IS
END c03s04b00x00p03n03i00547ent;
ARCHITECTURE c03s04b00x00p03n03i00547arch OF c03s04b00x00p03n03i00547ent IS
type TM is
file of integer;
type FT is -- file decl
file of TM; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s04b00x00p03n03i00547 - Subtype denoted by a filetype cannot have a base type of a file or access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n03i00547arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd | 4 | 2378 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
use std.textio.all;
architecture test of inline_06 is
subtype encoding_type is bit_vector(1 downto 0);
attribute encoding : encoding_type;
begin
process1 : process is
-- code from book:
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle [ return controller_state ] : literal is b"00";
attribute encoding of active [ return controller_state ] : literal is b"01";
attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
-- end of code from book
variable L : line;
begin
write(L, string'("process1"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, active [ return controller_state ] ' encoding);
writeline(output, L);
write(L, fail_safe [ return controller_state ] ' encoding);
writeline(output, L);
wait;
end process process1;
process2 : process is
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle : literal is b"11";
variable L : line;
begin
write(L, string'("process2"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, idle [ return load_level ] ' encoding);
writeline(output, L);
wait;
end process process2;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1982.vhd | 4 | 1816 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1982.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p01n03i01982ent IS
END c07s02b02x00p01n03i01982ent;
ARCHITECTURE c07s02b02x00p01n03i01982arch OF c07s02b02x00p01n03i01982ent IS
BEGIN
TESTING: PROCESS
variable i, j, k, l, m, n, o, p : integer := 1;
BEGIN
if (m=n) then -- No_failure_here
k := 5;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p01n03i01982"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p01n03i01982 - The result type of each relational operator is the predefined type BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p01n03i01982arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket59/bug.vhdl | 3 | 846 | package pkg is
type rec0_t is record
field0 : boolean;
end record;
type rec1_t is record
field1 : boolean;
end record;
function fun(val : boolean) return rec0_t;
function fun(val : boolean) return rec1_t;
function fun(val : boolean) return boolean;
procedure proc;
end package;
package body pkg is
function fun(val : boolean) return rec0_t is
begin
return (field0 => val);
end function;
function fun(val : boolean) return rec1_t is
begin
return (field1 => val);
end function;
function fun(val : boolean) return boolean is
begin
return val;
end function;
procedure proc is
begin
assert fun(true).field0;
assert fun(true).field1;
assert fun(true);
end procedure;
end package body;
entity ent is
end;
architecture behav of ent is
begin
work.pkg.proc;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3170.vhd | 4 | 1819 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3170.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03170ent IS
END c14s01b00x00p17n01i03170ent;
ARCHITECTURE c14s01b00x00p17n01i03170arch OF c14s01b00x00p17n01i03170ent IS
constant L : REAL := -10.0;
constant R : REAL := 10.0;
type RT1 is range L to R;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( RT1'right = RT1(R) )
report "***PASSED TEST: c14s01b00x00p17n01i03170"
severity NOTE;
assert ( RT1'right = RT1(R) )
report "***FAILED TEST: c14s01b00x00p17n01i03170 - Predefined attribute RIGHT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03170arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1823.vhd | 4 | 1812 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1823.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01823ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01823ent;
ARCHITECTURE c07s01b00x00p08n01i01823arch OF c07s01b00x00p08n01i01823ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus(0) <= small_int(small_int) after 5 ns; -- type name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01823 - Type names are not permitted as primaries in a type conversion expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01823arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd | 4 | 2036 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity motor_system is
port ( terminal vp, vm : electrical;
terminal px : electrical_vector(1 to 3) );
end entity motor_system;
----------------------------------------------------------------
architecture state_space of motor_system is
quantity v_in across vp to vm;
quantity x across i_x through px to electrical_ref;
constant Tfb : real := 0.001;
constant Kfb : real := 1.0;
constant Te : real := 0.001;
constant Ke : real := 1.0;
constant Tm : real := 0.1;
constant Km : real := 1.0;
type real_matrix is array (1 to 3, 1 to 3) of real;
constant c : real_matrix := ( ( -1.0/Tfb, 0.0, Kfb/Tfb ),
( -Ke/Te, -1.0/Te, 0.0 ),
( 0.0, Km/Tm, -1.0/Tm ) );
begin
state_eqn : procedural is
variable sum : real_vector(1 to 3) := (0.0, 0.0, 0.0);
begin
for i in 1 to 3 loop
for j in 1 to 3 loop
sum(i) := sum(i) + c(i, j) * x(j);
end loop;
end loop;
x(1)'dot := sum(1);
x(2)'dot := sum(2) + (Ke/Te)*v_in;
x(3)'dot := sum(3);
end procedural state_eqn;
end architecture state_space;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2807.vhd | 4 | 1726 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2807.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity IS is
end IS;
ENTITY c13s09b00x00p99n01i02807ent IS
END c13s09b00x00p99n01i02807ent;
ARCHITECTURE c13s09b00x00p99n01i02807arch OF c13s09b00x00p99n01i02807ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02807 - Reserved word IS can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02807arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_04.vhd | 4 | 2115 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_04.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_04 is
end entity ch_04_04;
----------------------------------------------------------------
architecture test of ch_04_04 is
begin
process_04_1_i : process is
-- code from book:
type A is array (1 to 4, 31 downto 0) of boolean;
-- end of code from book
variable free_map : bit_vector(1 to 10) := "0011010110";
variable count : natural;
begin
-- code from book (just the conditions):
assert A'left(1) = 1; assert A'low(1) = 1;
assert A'right(2) = 0 ; assert A'high(2) = 31;
assert A'length(1) = 4; assert A'length(2) = 32;
assert A'ascending(1) = true; assert A'ascending(2) = false;
assert A'low = 1; assert A'length = 4;
--
count := 0;
for index in free_map'range loop
if free_map(index) = '1' then
count := count + 1;
end if;
end loop;
-- end of code from book
wait;
end process process_04_1_i;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1170.vhd | 4 | 1957 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1170.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p06n01i01170ent IS
END c06s06b00x00p06n01i01170ent;
ARCHITECTURE c06s06b00x00p06n01i01170arch OF c06s06b00x00p06n01i01170ent IS
BEGIN
TESTING: PROCESS
type II is range 1 to 1000;
type RR is range 0.0001 to 10000.01;
function F1 (A:II;B:RR) return BOOLEAN is
variable G1 : II;
variable G2 : RR;
begin
if (A'LEFT(0) /= 0) then -- ERROR: attribute does not have a
-- generic expression assoc. with it.
return FALSE;
end if;
end F1;
BEGIN
assert FALSE
report "***FAILED TEST: c06s06b00x00p06n01i01170 - Arrtribute does not have generic expression associated with it."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p06n01i01170arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug019/PoC/src/common/fileio.vhdl | 4 | 3036 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: File I/O-related Functions.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- Exploring the options for providing a more convenient API than std.textio.
-- Not yet recommended for adoption as it depends on the VHDL generation and
-- still is under discussion.
--
-- Open problems:
-- - verify that std.textio.write(text, string) is, indeed, specified and
-- that it does *not* print a trailing \newline
-- -> would help to eliminate line buffering in shared variables
-- - move C_LINEBREAK to my_config to keep platform dependency out?
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library PoC;
use PoC.my_project.all;
package FileIO is
-- Constant declarations
constant C_LINEBREAK : STRING;
-- =============================================================================
procedure stdout_write (str : STRING);
procedure stdout_writeline(str : STRING := "");
end package;
package body FileIO is
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
-- =============================================================================
constant C_LINEBREAK : STRING := ite(str_equal(MY_OPERATING_SYSTEM, "WINDOWS"), (CR & LF), (1 => LF));
-- =============================================================================
shared variable stdout_line : line;
shared variable stderr_line : line;
procedure stdout_write(str : STRING) is
begin
write(stdout_line, str);
end procedure;
procedure stdout_writeline(str : STRING := "") is
begin
write(stdout_line, str);
writeline(output, stdout_line);
end procedure;
end package body;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2396.vhd | 4 | 2921 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2396.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n01i02396ent IS
END c07s03b02x00p07n01i02396ent;
ARCHITECTURE c07s03b02x00p07n01i02396arch OF c07s03b02x00p07n01i02396ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
-- Declare array variables of these types.
variable BYTEV : BYTE;
BEGIN
BYTEV := BYTE'( 7 => '0', 6 => '1', 4 => '1',
2 => '1', 0 => '1', 5 => '0',
3 => '0', 1 => '0' );
assert( BYTEV( 1 ) = '0' );
assert( BYTEV( 3 ) = '0' );
assert( BYTEV( 5 ) = '0' );
assert( BYTEV( 7 ) = '0' );
assert( BYTEV( 0 ) = '1' );
assert( BYTEV( 2 ) = '1' );
assert( BYTEV( 4 ) = '1' );
assert( BYTEV( 6 ) = '1' );
wait for 1 ns;
assert NOT( ( BYTEV( 1 ) = '0' ) and
( BYTEV( 3 ) = '0' ) and
( BYTEV( 5 ) = '0' ) and
( BYTEV( 7 ) = '0' ) and
( BYTEV( 0 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 6 ) = '1' ))
report "***PASSED TEST: c07s03b02x00p07n01i02396"
severity NOTE;
assert ( ( BYTEV( 1 ) = '0' ) and
( BYTEV( 3 ) = '0' ) and
( BYTEV( 5 ) = '0' ) and
( BYTEV( 7 ) = '0' ) and
( BYTEV( 0 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 6 ) = '1' ))
report "***FAILED TEST: c07s03b02x00p07n01i02396 - Named association should be able to appear in any order."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n01i02396arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue163/qualified_expr.vhdl | 2 | 548 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity qualified_expr is
port (
X : in std_logic_vector(7 downto 0);
CIn : in std_logic;
Y : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of qualified_expr is
begin
-- analyze error with GHDL
Y <= std_logic_vector(unsigned(X) + unsigned'((0 to 0 => CIn)));
-- analyses with GHDL but not with other tools
--Y <= std_logic_vector(unsigned(X) + unsigned'(0 to 0 => CIn));
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1209.vhd | 4 | 4688 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1209.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s01b00x00p24n01i01209pkg is
-- Type declarations.
type SWITCH_LEVEL is ( '0', '1', 'X' );
type S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
-- Define the bus resolution function.
function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
-- Further type declarations.
subtype SWITCH_T is switchF SWITCH_LEVEL;
type WORD is array(0 to 31) of SWITCH_T;
end c08s01b00x00p24n01i01209pkg;
package body c08s01b00x00p24n01i01209pkg is
-- A dumb resolution function.
function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
begin
return( S(1) );
end switchf;
end c08s01b00x00p24n01i01209pkg;
use work.c08s01b00x00p24n01i01209pkg.all;
ENTITY c08s01b00x00p24n01i01209ent IS
END c08s01b00x00p24n01i01209ent;
ARCHITECTURE c08s01b00x00p24n01i01209arch OF c08s01b00x00p24n01i01209ent IS
-- Local types
type WORD2 is array(0 to 31) of SWITCH_LEVEL;
type REC is RECORD
R1 : SWITCH_T;
R2 : SWITCH_T;
end RECORD;
-- Local signals.
signal A : WORD;
signal UnResolved : WORD2;
signal RecSig : REC;
BEGIN
TESTING: PROCESS
-- Constant declarations.
constant One : INTEGER := 1;
constant Two : INTEGER := 2;
-- Local variables.
variable ShouldBeTime : TIME;
variable I : INTEGER;
variable k : integer := 0;
BEGIN
--1. Test waiting on an array of scalar resolved elements.
for I in 0 to 31 loop
ShouldBeTime := NOW + 1 ns;
A( I ) <= 'X' after 1 ns;
wait on A;
if (A(I) /= 'X' and ShouldBeTime /= Now) then
k := 1;
end if;
-- Verify that we waited the right amount of time.
assert (ShouldBeTime = NOW);
assert (A( I ) = 'X');
end loop;
-- 2. Test waiting on an array of scalar unresolved elements.
ShouldBeTime := NOW + 1 ns;
UnResolved <= ( '1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1' ) after 1 ns;
wait on UnResolved;
if (UnResolved /= ( '1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1' ) and ShouldBeTime /= Now) then
k := 1;
end if;
-- Verify that we waited allright.
assert (ShouldBeTime = NOW);
for I in 0 to 31 loop
assert ( UnResolved( I ) = '1');
end loop;
-- 3. Test waiting on a record.
RECSIG.R1 <= 'X' after 1 ns;
RECSIG.R2 <= 'X' after 2 ns;
ShouldBeTime := NOW + 1 ns;
wait on RECSIG;
if (RECSIG.R1 /= 'X' and ShouldBeTime /= Now) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (RECSIG.R1 = 'X');
ShouldBeTime := NOW + 1 ns;
wait on RECSIG;
if (RECSIG.R2 /= 'X' and ShouldBeTime /= Now) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (RECSIG.R2 = 'X');
assert NOT( k=0 )
report "***PASSED TEST: c08s01b00x00p24n01i01209"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s01b00x00p24n01i01209 - The effect of a signal name denotes a signal of a composite type is as if name of each scalar subelement of that signal appears in the list."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p24n01i01209arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc83.vhd | 4 | 1900 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc83.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x03p02n01i00083ent IS
END c04s03b01x03p02n01i00083ent;
ARCHITECTURE c04s03b01x03p02n01i00083arch OF c04s03b01x03p02n01i00083ent IS
type x is (a, b, c, d);
BEGIN
TESTING: PROCESS
variable x1 : x := a; -- No_failure_here
variable x : character := 'a'; -- No_failure_here
variable x2 : character := 'a'; -- No_failure_here
BEGIN
assert NOT( x1 = a and x = 'a' and x2 = 'a' )
report "***PASSED TEST:c04s03b01x03p02n01i00083"
severity NOTE;
assert ( x1 = a and x = 'a' and x2 = 'a' )
report "***FAILED TEST: c04s03b01x03p02n01i00083- Variable assignment test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x03p02n01i00083arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc291.vhd | 4 | 1957 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc291.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p14n01i00291ent IS
END c03s01b03x00p14n01i00291ent;
ARCHITECTURE c03s01b03x00p14n01i00291arch OF c03s01b03x00p14n01i00291ent IS
type T is
range -2147483647 to 2147483647 -- No_failure_here
units
I ;
J = 2 I;
K = 2 J;
L = 10 K;
M = 1000 L;
end units;
BEGIN
TESTING: PROCESS
variable kk : T := 1 L;
BEGIN
assert NOT( kk = 20 J )
report "***PASSED TEST: c03s01b03x00p14n01i00291"
severity NOTE;
assert ( kk = 20 J )
report "***FAILED TEST: c03s01b03x00p14n01i00291 - The declaration of any physical type whose range is wholly contained within the bounds -2147483647 and +2147483647, inclusive."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p14n01i00291arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1313.vhd | 4 | 1790 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1313.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p07n03i01313ent IS
END c08s04b00x00p07n03i01313ent;
ARCHITECTURE c08s04b00x00p07n03i01313arch OF c08s04b00x00p07n03i01313ent IS
subtype BV2 is BIT_VECTOR(0 to 1);
signal S : BV2;
signal T : BV2;
BEGIN
TESTING: PROCESS
variable BITV : BV2 := B"11";
variable I : integer := 1;
BEGIN
(S(I), T(I)) <= BITV after 5 ns;
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p07n03i01313 - The expression in the element association is not locally static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n03i01313arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2989.vhd | 4 | 2430 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2989.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p06n01i02989pkg is
constant c1 : INTEGER;
function f return INTEGER;
procedure p(x : inout INTEGER);
end c02s05b00x00p06n01i02989pkg;
package body c02s05b00x00p06n01i02989pkg is
constant c1 : INTEGER := 10;
constant c2 : INTEGER := 20;
function f return INTEGER is
begin
return c1 + c2;
end;
procedure p( x: inout INTEGER) is
begin
x := c1 + c2;
end;
end c02s05b00x00p06n01i02989pkg;
ENTITY c02s05b00x00p06n01i02989ent IS
END c02s05b00x00p06n01i02989ent;
ARCHITECTURE c02s05b00x00p06n01i02989arch OF c02s05b00x00p06n01i02989ent IS
signal s1 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
signal s2 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
BEGIN
TESTING: PROCESS
variable temp : INTEGER;
BEGIN
s1 <= WORK.c02s05b00x00p06n01i02989pkg.F;
WORK.c02s05b00x00p06n01i02989pkg.P(temp);
s2 <= temp;
wait for 5 ns;
assert NOT( s1 = 30 and s2 = 30 )
report "***PASSED TEST: c02s05b00x00p06n01i02989"
severity NOTE;
assert ( s1 = 30 and s2 = 30 )
report "***FAILED TEST: c02s05b00x00p06n01i02989 - Package declaration visibility test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p06n01i02989arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc628.vhd | 4 | 2023 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc628.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:46 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00628ent IS
END c03s04b01x00p01n01i00628ent;
ARCHITECTURE c03s04b01x00p01n01i00628arch OF c03s04b01x00p01n01i00628ent IS
type byte is array(0 to 7) of bit;
type byte_file is file of byte;
constant C38 : byte := (others => '1');
BEGIN
TESTING: PROCESS
file filein : byte_file open write_mode is "iofile.40";
BEGIN
for i in 1 to 100 loop
write(filein, C38);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00628 - The output file will be verified by test s010282.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00628arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2406.vhd | 4 | 1776 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2406.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n05i02406ent IS
END c07s03b02x00p08n05i02406ent;
ARCHITECTURE c07s03b02x00p08n05i02406arch OF c07s03b02x00p08n05i02406ent IS
type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
signal S1 : ARRAY_TYPE(1 to 2) ;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= (others=>TRUE,TRUE); -- Failure_here
-- SEMANTIC ERROR: association cannot follow "others" association.
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n05i02406 - Nothing may follow an others association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n05i02406arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd | 4 | 1667 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_09 is
end entity inline_09;
----------------------------------------------------------------
architecture test of inline_09 is
begin
process_2_d : process is
-- code from book:
variable N : integer := 1;
--
constant C : integer := 1;
-- end of code from book
constant expression : integer := 7;
begin
-- code from book:
-- error: Case choice must be a locally static expression
-- case expression is -- example of an illegal case statement
-- when N | N+1 => -- . . .
-- when N+2 to N+5 => -- . . .
-- when others => -- . . .
-- end case;
--
case expression is
when C | C+1 => -- . . .
when C+2 to C+5 => -- . . .
when others => -- . . .
end case;
-- end of code from book
wait;
end process process_2_d;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue312/test.vhdl | 2 | 231 | package pkg is
generic (
type T
);
end package;
use work.pkg.all;
entity test is
end entity;
architecture tb of test is
package p is new package pkg
generic map (
T => integer
);
begin
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc230.vhd | 4 | 1818 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc230.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p02n01i00230ent IS
END c03s01b02x00p02n01i00230ent;
ARCHITECTURE c03s01b02x00p02n01i00230arch OF c03s01b02x00p02n01i00230ent IS
type a is range (((((10-1)-1)-1)-1)-1) to (((((10+1)+1)+1)+1)+1);
BEGIN
TESTING: PROCESS
variable k : a := 11;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p02n01i00230"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p02n01i00230 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p02n01i00230arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1681.vhd | 4 | 1599 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1681.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p09n01i01681ent IS
END c09s01b00x00p09n01i01681ent;
ARCHITECTURE c09s01b00x00p09n01i01681arch OF c09s01b00x00p09n01i01681ent IS
BEGIN
lab : block
begin
end block lab; -- labels match
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s01b00x00p09n01i01681"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s01b00x00p09n01i01681arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2071.vhd | 4 | 1936 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2071.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02071ent IS
END c07s02b04x00p01n02i02071ent;
ARCHITECTURE c07s02b04x00p01n02i02071arch OF c07s02b04x00p01n02i02071ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable POSRV : POSITIVE_R := 0.0;
BEGIN
POSV := POSV + POSRV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02071 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02071arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2309.vhd | 4 | 1847 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2309.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02309ent IS
END c07s02b07x00p01n01i02309ent;
ARCHITECTURE c07s02b07x00p01n01i02309arch OF c07s02b07x00p01n01i02309ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
constant b : phys := abs (10 p2);
BEGIN
assert NOT(b = 100 p1)
report "***PASSED TEST: c07s02b07x00p01n01i02309"
severity NOTE;
assert (b = 100 p1)
report "***FAILED TEST: c07s02b07x00p01n01i02309 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02309arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/top.vhd | 2 | 261165 | library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_ack : in std_logic;
stdout_data : out std_logic_vector(7 downto 0);
stdin_data : in std_logic_vector(7 downto 0);
stdin_rdy : out std_logic
);
end top;
architecture augh of top is
-- Declaration of components
component cmp_869 is
port (
eq : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in0 : in std_logic_vector(7 downto 0)
);
end component;
component cmp_978 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_979 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_847 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_855 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_852 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component mul_213 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_216 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_214 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component cmp_846 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_848 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_849 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component p_jinfo_comps_info_id is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_h_samp_factor is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_quant_tbl_no is
port (
wa0_data : in std_logic_vector(1 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(1 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_dc_tbl_no is
port (
wa0_data : in std_logic;
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic;
wa0_en : in std_logic
);
end component;
component p_jinfo_quant_tbl_quantval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(7 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(7 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_mincode is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_valptr is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_mincode is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_valptr is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_vpos is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_hpos is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(14 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(14 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component izigzag_index is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(5 downto 0)
);
end component;
component jpegfilebuf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(12 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(12 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component huffbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(7 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(7 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component idctbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(8 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(8 downto 0);
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component quantbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(5 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component extend_mask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(20 downto 0)
);
end component;
component bit_set_mask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0)
);
end component;
component lmask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0)
);
end component;
component huff_make_dhuff_tb_ac_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_ac_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_dc_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_dc_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component rgb_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component zigzag_index is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(5 downto 0)
);
end component;
component shr_212 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end component;
component mul_209 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_210 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component shl_211 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end component;
component sub_206 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_207 is
port (
ge : out std_logic;
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_208 is
port (
ge : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_205 is
port (
gt : out std_logic;
ge : out std_logic;
lt : out std_logic;
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component add_202 is
port (
output : out std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component add_203 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component add_204 is
port (
output : out std_logic_vector(24 downto 0);
in_b : in std_logic_vector(24 downto 0);
in_a : in std_logic_vector(24 downto 0)
);
end component;
component add_201 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component add_200 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component cmp_775 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_779 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_780 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_787 is
port (
eq : out std_logic;
in1 : in std_logic;
in0 : in std_logic
);
end component;
component cmp_788 is
port (
eq : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_790 is
port (
ne : out std_logic;
in1 : in std_logic_vector(3 downto 0);
in0 : in std_logic_vector(3 downto 0)
);
end component;
component cmp_792 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_793 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_794 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_791 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_804 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_800 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_799 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_865 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_882 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_885 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_887 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component mul_215 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component cmp_850 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_851 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_861 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_871 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_873 is
port (
eq : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in0 : in std_logic_vector(7 downto 0)
);
end component;
component cmp_879 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_880 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component sub_217 is
port (
ge : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component cmp_863 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_868 is
port (
eq : out std_logic;
in1 : in std_logic_vector(23 downto 0);
in0 : in std_logic_vector(23 downto 0)
);
end component;
component cmp_877 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_878 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component sub_218 is
port (
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_220 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_221 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component mul_222 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component sub_219 is
port (
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component cmp_962 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_975 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component fsm_224 is
port (
clock : in std_logic;
reset : in std_logic;
out40 : out std_logic;
in2 : in std_logic;
in11 : in std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out152 : out std_logic;
in12 : in std_logic;
out153 : out std_logic;
out154 : out std_logic;
in13 : in std_logic;
out156 : out std_logic;
out157 : out std_logic;
out160 : out std_logic;
out162 : out std_logic;
out165 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out175 : out std_logic;
out177 : out std_logic;
out180 : out std_logic;
out184 : out std_logic;
in14 : in std_logic;
out186 : out std_logic;
out189 : out std_logic;
out191 : out std_logic;
out192 : out std_logic;
out193 : out std_logic;
out197 : out std_logic;
out199 : out std_logic;
out201 : out std_logic;
out202 : out std_logic;
out205 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
in15 : in std_logic;
out221 : out std_logic;
out222 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out231 : out std_logic;
out99 : out std_logic;
in6 : in std_logic;
out92 : out std_logic;
out232 : out std_logic;
in16 : in std_logic;
out234 : out std_logic;
out236 : out std_logic;
out239 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out245 : out std_logic;
out246 : out std_logic;
out247 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
in17 : in std_logic;
out263 : out std_logic;
out264 : out std_logic;
out266 : out std_logic;
in18 : in std_logic;
out267 : out std_logic;
out268 : out std_logic;
out270 : out std_logic;
out273 : out std_logic;
out275 : out std_logic;
out276 : out std_logic;
in19 : in std_logic;
out279 : out std_logic;
in20 : in std_logic;
out281 : out std_logic;
out282 : out std_logic;
in21 : in std_logic;
out283 : out std_logic;
out286 : out std_logic;
out289 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out299 : out std_logic;
out300 : out std_logic;
out304 : out std_logic;
out305 : out std_logic;
in22 : in std_logic;
out306 : out std_logic;
out310 : out std_logic;
out311 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
in23 : in std_logic;
out316 : out std_logic;
out317 : out std_logic;
out320 : out std_logic;
out322 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out328 : out std_logic;
out332 : out std_logic;
out333 : out std_logic;
out334 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out339 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out93 : out std_logic;
out98 : out std_logic;
out85 : out std_logic;
out87 : out std_logic;
out88 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out83 : out std_logic;
out84 : out std_logic;
in5 : in std_logic;
out77 : out std_logic;
out78 : out std_logic;
out71 : out std_logic;
out72 : out std_logic;
in4 : in std_logic;
out65 : out std_logic;
out67 : out std_logic;
out60 : out std_logic;
out64 : out std_logic;
in3 : in std_logic;
out59 : out std_logic;
out53 : out std_logic;
out55 : out std_logic;
out49 : out std_logic;
out44 : out std_logic;
out104 : out std_logic;
out107 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
in7 : in std_logic;
out117 : out std_logic;
out119 : out std_logic;
out122 : out std_logic;
in8 : in std_logic;
out128 : out std_logic;
in9 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
in10 : in std_logic;
out139 : out std_logic;
out143 : out std_logic;
out144 : out std_logic;
out32 : out std_logic;
out35 : out std_logic;
out27 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
in1 : in std_logic;
out15 : out std_logic;
out16 : out std_logic;
out11 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out7 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
out3 : out std_logic;
out4 : out std_logic;
in0 : in std_logic;
in24 : in std_logic;
out346 : out std_logic;
out347 : out std_logic;
out348 : out std_logic;
out349 : out std_logic;
in25 : in std_logic;
out350 : out std_logic;
out351 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out365 : out std_logic;
out366 : out std_logic;
out370 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out375 : out std_logic;
in26 : in std_logic;
out376 : out std_logic;
out378 : out std_logic;
out379 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
in27 : in std_logic;
out384 : out std_logic;
in28 : in std_logic;
out391 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out405 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
in29 : in std_logic;
out412 : out std_logic;
out414 : out std_logic;
out415 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out422 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
in30 : in std_logic;
out428 : out std_logic;
out429 : out std_logic;
out432 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out437 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
in31 : in std_logic;
out443 : out std_logic;
in32 : in std_logic;
out445 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
in33 : in std_logic;
out453 : out std_logic;
out455 : out std_logic;
out458 : out std_logic;
in34 : in std_logic;
out462 : out std_logic;
out464 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out472 : out std_logic;
in35 : in std_logic;
out478 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
in36 : in std_logic;
out491 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out500 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
in37 : in std_logic;
out506 : out std_logic;
out508 : out std_logic;
in38 : in std_logic;
out510 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out515 : out std_logic;
out517 : out std_logic;
out519 : out std_logic;
in39 : in std_logic;
out523 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out530 : out std_logic;
out531 : out std_logic;
out533 : out std_logic;
out534 : out std_logic;
out537 : out std_logic;
out538 : out std_logic;
out549 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out561 : out std_logic;
in40 : in std_logic;
out566 : out std_logic;
out567 : out std_logic;
out568 : out std_logic;
out569 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out574 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
in41 : in std_logic;
out578 : out std_logic;
out581 : out std_logic;
out589 : out std_logic;
out590 : out std_logic;
out595 : out std_logic;
out597 : out std_logic;
out599 : out std_logic;
out601 : out std_logic;
out602 : out std_logic;
out607 : out std_logic;
out610 : out std_logic;
out612 : out std_logic;
in42 : in std_logic;
out614 : out std_logic;
out621 : out std_logic;
out628 : out std_logic;
out635 : out std_logic;
out636 : out std_logic;
out638 : out std_logic;
out640 : out std_logic;
out643 : out std_logic;
out646 : out std_logic;
out649 : out std_logic;
out651 : out std_logic;
out656 : out std_logic;
in43 : in std_logic;
out658 : out std_logic;
out659 : out std_logic;
out661 : out std_logic;
out663 : out std_logic;
out664 : out std_logic;
in44 : in std_logic;
out667 : out std_logic;
out668 : out std_logic;
out670 : out std_logic;
out672 : out std_logic;
out674 : out std_logic;
in45 : in std_logic;
out679 : out std_logic;
out681 : out std_logic;
out683 : out std_logic;
out686 : out std_logic;
out688 : out std_logic;
out690 : out std_logic;
out692 : out std_logic;
out694 : out std_logic;
out696 : out std_logic;
out697 : out std_logic;
out698 : out std_logic;
out699 : out std_logic;
out700 : out std_logic;
out703 : out std_logic;
out704 : out std_logic;
out706 : out std_logic;
out708 : out std_logic;
out710 : out std_logic;
out712 : out std_logic;
out715 : out std_logic;
out718 : out std_logic;
in46 : in std_logic;
out722 : out std_logic;
out724 : out std_logic;
out726 : out std_logic;
out728 : out std_logic;
out731 : out std_logic;
out733 : out std_logic;
out734 : out std_logic;
out737 : out std_logic;
out739 : out std_logic;
out740 : out std_logic;
out743 : out std_logic;
out745 : out std_logic;
out746 : out std_logic;
in47 : in std_logic;
out749 : out std_logic;
out753 : out std_logic;
out755 : out std_logic;
out759 : out std_logic;
in48 : in std_logic;
out762 : out std_logic;
out764 : out std_logic;
out765 : out std_logic;
out767 : out std_logic;
out768 : out std_logic;
in49 : in std_logic;
out772 : out std_logic;
in50 : in std_logic;
out775 : out std_logic;
out776 : out std_logic;
out778 : out std_logic;
out783 : out std_logic;
out784 : out std_logic;
out787 : out std_logic;
out791 : out std_logic;
in51 : in std_logic;
out794 : out std_logic;
out795 : out std_logic;
in52 : in std_logic;
out799 : out std_logic;
out802 : out std_logic;
out806 : out std_logic;
out809 : out std_logic;
out812 : out std_logic;
out815 : out std_logic;
out826 : out std_logic;
out828 : out std_logic;
in53 : in std_logic;
in54 : in std_logic;
out843 : out std_logic;
out848 : out std_logic;
out852 : out std_logic;
in55 : in std_logic;
out855 : out std_logic;
out858 : out std_logic;
in56 : in std_logic;
out860 : out std_logic;
out861 : out std_logic;
out863 : out std_logic;
out866 : out std_logic;
out872 : out std_logic;
in57 : in std_logic;
out874 : out std_logic;
out876 : out std_logic;
out879 : out std_logic;
out882 : out std_logic;
out886 : out std_logic;
out887 : out std_logic;
in58 : in std_logic;
out888 : out std_logic;
out892 : out std_logic;
out894 : out std_logic;
out895 : out std_logic;
out896 : out std_logic;
out901 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out905 : out std_logic;
out907 : out std_logic;
out918 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out923 : out std_logic;
out925 : out std_logic;
out928 : out std_logic;
out929 : out std_logic;
out931 : out std_logic;
out933 : out std_logic;
out936 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out939 : out std_logic;
out942 : out std_logic;
out943 : out std_logic;
out944 : out std_logic;
out947 : out std_logic;
out948 : out std_logic;
out949 : out std_logic;
out951 : out std_logic;
in59 : in std_logic;
out952 : out std_logic;
out953 : out std_logic;
out955 : out std_logic;
out956 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
in60 : in std_logic;
in61 : in std_logic;
out962 : out std_logic;
out963 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
in62 : in std_logic;
out978 : out std_logic;
out979 : out std_logic;
out981 : out std_logic;
out982 : out std_logic;
out985 : out std_logic;
out986 : out std_logic;
out989 : out std_logic;
in63 : in std_logic;
in64 : in std_logic;
in65 : in std_logic;
in66 : in std_logic;
in67 : in std_logic;
in68 : in std_logic;
in69 : in std_logic;
in70 : in std_logic;
in71 : in std_logic;
in72 : in std_logic;
in73 : in std_logic;
in74 : in std_logic;
in75 : in std_logic;
in76 : in std_logic;
in77 : in std_logic;
in78 : in std_logic;
out990 : out std_logic;
out991 : out std_logic;
out993 : out std_logic;
out994 : out std_logic;
out996 : out std_logic;
out997 : out std_logic;
out998 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1005 : out std_logic;
out1006 : out std_logic;
out1007 : out std_logic;
out1009 : out std_logic;
out1011 : out std_logic;
out1012 : out std_logic;
out1013 : out std_logic;
out1014 : out std_logic;
out1015 : out std_logic;
out1016 : out std_logic;
out1018 : out std_logic;
out1019 : out std_logic;
out1021 : out std_logic;
out1022 : out std_logic;
out1024 : out std_logic;
out1026 : out std_logic;
out1027 : out std_logic;
out1029 : out std_logic;
out1030 : out std_logic;
out1032 : out std_logic;
out1033 : out std_logic;
out1035 : out std_logic;
out1036 : out std_logic;
out1037 : out std_logic;
out1057 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1070 : out std_logic;
out1072 : out std_logic;
out1073 : out std_logic;
out1075 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1082 : out std_logic;
out1083 : out std_logic;
out1084 : out std_logic;
out1085 : out std_logic;
out1088 : out std_logic;
out1089 : out std_logic;
out1091 : out std_logic;
out1092 : out std_logic;
out1094 : out std_logic;
out1096 : out std_logic;
out1098 : out std_logic;
out1101 : out std_logic;
out1104 : out std_logic;
out1107 : out std_logic;
out1109 : out std_logic;
out1111 : out std_logic;
out1114 : out std_logic;
out1119 : out std_logic;
out1121 : out std_logic;
out1125 : out std_logic;
out1126 : out std_logic;
out1128 : out std_logic;
out1131 : out std_logic;
out1134 : out std_logic;
out1137 : out std_logic;
out1139 : out std_logic;
out1141 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1155 : out std_logic;
out1158 : out std_logic;
out1160 : out std_logic;
out1164 : out std_logic;
out1166 : out std_logic;
out1169 : out std_logic;
out1171 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1190 : out std_logic;
out1213 : out std_logic;
out1215 : out std_logic;
out1217 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out1223 : out std_logic;
out1228 : out std_logic;
out1229 : out std_logic;
out1231 : out std_logic;
out1235 : out std_logic;
out1236 : out std_logic;
out1240 : out std_logic;
out1243 : out std_logic;
out1250 : out std_logic;
out1252 : out std_logic;
out1253 : out std_logic;
out1258 : out std_logic;
out1262 : out std_logic;
out1266 : out std_logic;
out1269 : out std_logic;
out1275 : out std_logic;
out1278 : out std_logic;
out1279 : out std_logic;
out1284 : out std_logic;
out1286 : out std_logic;
out1287 : out std_logic;
out1289 : out std_logic;
out1290 : out std_logic;
out1292 : out std_logic;
out1293 : out std_logic;
out1295 : out std_logic;
out1298 : out std_logic;
out1301 : out std_logic;
out1302 : out std_logic;
out1303 : out std_logic;
out1308 : out std_logic;
out1309 : out std_logic;
out1311 : out std_logic;
out1318 : out std_logic;
out1319 : out std_logic;
out1320 : out std_logic;
out1323 : out std_logic;
out1324 : out std_logic;
out1326 : out std_logic;
out1327 : out std_logic;
out1329 : out std_logic;
out1337 : out std_logic;
out1339 : out std_logic;
out1340 : out std_logic;
out1341 : out std_logic;
out1344 : out std_logic;
out1346 : out std_logic;
out1349 : out std_logic;
out1353 : out std_logic;
out1356 : out std_logic;
out1362 : out std_logic;
out1363 : out std_logic;
out1364 : out std_logic;
out1365 : out std_logic;
out1366 : out std_logic;
out1368 : out std_logic;
out1370 : out std_logic;
out1375 : out std_logic;
out1378 : out std_logic;
out1381 : out std_logic;
out1383 : out std_logic;
out1387 : out std_logic
);
end component;
component muxb_784 is
port (
in_sel : in std_logic;
out_data : out std_logic_vector(31 downto 0);
in_data0 : in std_logic_vector(31 downto 0);
in_data1 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_964 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_972 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_973 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_974 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_985 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_971 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_977 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
-- Declaration of signals
signal sig_clock : std_logic;
signal sig_reset : std_logic;
signal augh_test_159 : std_logic;
signal augh_test_6 : std_logic;
signal augh_test_9 : std_logic;
signal augh_test_10 : std_logic;
signal augh_test_26 : std_logic;
signal augh_test_49 : std_logic;
signal augh_test_52 : std_logic;
signal augh_test_53 : std_logic;
signal augh_test_62 : std_logic;
signal augh_test_67 : std_logic;
signal augh_test_72 : std_logic;
signal augh_test_77 : std_logic;
signal augh_test_83 : std_logic;
signal augh_test_89 : std_logic;
signal augh_test_90 : std_logic;
signal augh_test_94 : std_logic;
signal augh_test_99 : std_logic;
signal augh_test_100 : std_logic;
signal augh_test_101 : std_logic;
signal augh_test_102 : std_logic;
signal augh_test_103 : std_logic;
signal augh_test_104 : std_logic;
signal augh_test_105 : std_logic;
signal augh_test_106 : std_logic;
signal augh_test_107 : std_logic;
signal augh_test_108 : std_logic;
signal augh_test_109 : std_logic;
signal augh_test_111 : std_logic;
signal augh_test_113 : std_logic;
signal augh_test_114 : std_logic;
signal augh_test_115 : std_logic;
signal augh_test_118 : std_logic;
signal augh_test_119 : std_logic;
signal augh_test_120 : std_logic;
signal augh_test_122 : std_logic;
signal augh_test_123 : std_logic;
signal augh_test_124 : std_logic;
signal augh_test_125 : std_logic;
signal augh_test_126 : std_logic;
signal augh_test_127 : std_logic;
signal augh_test_128 : std_logic;
signal augh_test_130 : std_logic;
signal augh_test_131 : std_logic;
signal augh_test_132 : std_logic;
signal augh_test_133 : std_logic;
signal augh_test_134 : std_logic;
signal augh_test_136 : std_logic;
signal augh_test_138 : std_logic;
signal augh_test_142 : std_logic;
signal augh_test_144 : std_logic;
signal augh_test_148 : std_logic;
signal augh_test_150 : std_logic;
signal augh_test_151 : std_logic;
signal augh_test_152 : std_logic;
signal augh_test_154 : std_logic;
signal augh_test_155 : std_logic;
signal augh_test_157 : std_logic;
signal augh_test_158 : std_logic;
signal augh_test_165 : std_logic;
signal augh_test_166 : std_logic;
signal augh_test_167 : std_logic;
signal augh_test_168 : std_logic;
signal sig_start : std_logic;
signal augh_test_171 : std_logic;
signal augh_test_178 : std_logic;
signal augh_test_179 : std_logic;
signal augh_test_180 : std_logic;
signal augh_test_182 : std_logic;
signal augh_test_183 : std_logic;
signal augh_test_184 : std_logic;
signal augh_test_186 : std_logic;
signal augh_test_187 : std_logic;
signal augh_test_188 : std_logic;
signal augh_test_189 : std_logic;
signal augh_test_194 : std_logic;
signal augh_test_196 : std_logic;
signal augh_test_197 : std_logic;
signal sig_990 : std_logic;
signal sig_991 : std_logic;
signal sig_992 : std_logic_vector(31 downto 0);
signal sig_993 : std_logic;
signal sig_994 : std_logic;
signal sig_995 : std_logic;
signal sig_996 : std_logic;
signal sig_997 : std_logic;
signal sig_998 : std_logic;
signal sig_999 : std_logic;
signal sig_1000 : std_logic;
signal sig_1001 : std_logic;
signal sig_1002 : std_logic;
signal sig_1003 : std_logic;
signal sig_1004 : std_logic;
signal sig_1005 : std_logic;
signal sig_1006 : std_logic;
signal sig_1007 : std_logic;
signal sig_1008 : std_logic;
signal sig_1009 : std_logic;
signal sig_1010 : std_logic;
signal sig_1011 : std_logic;
signal sig_1012 : std_logic;
signal sig_1013 : std_logic;
signal sig_1014 : std_logic;
signal sig_1015 : std_logic;
signal sig_1016 : std_logic;
signal sig_1017 : std_logic;
signal sig_1018 : std_logic;
signal sig_1019 : std_logic;
signal sig_1020 : std_logic;
signal sig_1021 : std_logic;
signal sig_1022 : std_logic;
signal sig_1023 : std_logic;
signal sig_1024 : std_logic;
signal sig_1025 : std_logic;
signal sig_1026 : std_logic;
signal sig_1027 : std_logic;
signal sig_1028 : std_logic;
signal sig_1029 : std_logic;
signal sig_1030 : std_logic;
signal sig_1031 : std_logic;
signal sig_1032 : std_logic;
signal sig_1033 : std_logic;
signal sig_1034 : std_logic;
signal sig_1035 : std_logic;
signal sig_1036 : std_logic;
signal sig_1037 : std_logic;
signal sig_1038 : std_logic;
signal sig_1039 : std_logic;
signal sig_1040 : std_logic;
signal sig_1041 : std_logic;
signal sig_1042 : std_logic;
signal sig_1043 : std_logic;
signal sig_1044 : std_logic;
signal sig_1045 : std_logic;
signal sig_1046 : std_logic;
signal sig_1047 : std_logic;
signal sig_1048 : std_logic;
signal sig_1049 : std_logic;
signal sig_1050 : std_logic;
signal sig_1051 : std_logic;
signal sig_1052 : std_logic;
signal sig_1053 : std_logic;
signal sig_1054 : std_logic;
signal sig_1055 : std_logic;
signal sig_1056 : std_logic;
signal sig_1057 : std_logic;
signal sig_1058 : std_logic;
signal sig_1059 : std_logic;
signal sig_1060 : std_logic;
signal sig_1061 : std_logic;
signal sig_1062 : std_logic;
signal sig_1063 : std_logic;
signal sig_1064 : std_logic;
signal sig_1065 : std_logic;
signal sig_1066 : std_logic;
signal sig_1067 : std_logic;
signal sig_1068 : std_logic;
signal sig_1069 : std_logic;
signal sig_1070 : std_logic;
signal sig_1071 : std_logic;
signal sig_1072 : std_logic;
signal sig_1073 : std_logic;
signal sig_1074 : std_logic;
signal sig_1075 : std_logic;
signal sig_1076 : std_logic;
signal sig_1077 : std_logic;
signal sig_1078 : std_logic;
signal sig_1079 : std_logic;
signal sig_1080 : std_logic;
signal sig_1081 : std_logic;
signal sig_1082 : std_logic;
signal sig_1083 : std_logic;
signal sig_1084 : std_logic;
signal sig_1085 : std_logic;
signal sig_1086 : std_logic;
signal sig_1087 : std_logic;
signal sig_1088 : std_logic;
signal sig_1089 : std_logic;
signal sig_1090 : std_logic;
signal sig_1091 : std_logic;
signal sig_1092 : std_logic;
signal sig_1093 : std_logic;
signal sig_1094 : std_logic;
signal sig_1095 : std_logic;
signal sig_1096 : std_logic;
signal sig_1097 : std_logic;
signal sig_1098 : std_logic;
signal sig_1099 : std_logic;
signal sig_1100 : std_logic;
signal sig_1101 : std_logic;
signal sig_1102 : std_logic;
signal sig_1103 : std_logic;
signal sig_1104 : std_logic;
signal sig_1105 : std_logic;
signal sig_1106 : std_logic;
signal sig_1107 : std_logic;
signal sig_1108 : std_logic;
signal sig_1109 : std_logic;
signal sig_1110 : std_logic;
signal sig_1111 : std_logic;
signal sig_1112 : std_logic;
signal sig_1113 : std_logic;
signal sig_1114 : std_logic;
signal sig_1115 : std_logic;
signal sig_1116 : std_logic;
signal sig_1117 : std_logic;
signal sig_1118 : std_logic;
signal sig_1119 : std_logic;
signal sig_1120 : std_logic;
signal sig_1121 : std_logic;
signal sig_1122 : std_logic;
signal sig_1123 : std_logic;
signal sig_1124 : std_logic;
signal sig_1125 : std_logic;
signal sig_1126 : std_logic;
signal sig_1127 : std_logic;
signal sig_1128 : std_logic;
signal sig_1129 : std_logic;
signal sig_1130 : std_logic;
signal sig_1131 : std_logic;
signal sig_1132 : std_logic;
signal sig_1133 : std_logic;
signal sig_1134 : std_logic;
signal sig_1135 : std_logic;
signal sig_1136 : std_logic;
signal sig_1137 : std_logic;
signal sig_1138 : std_logic;
signal sig_1139 : std_logic;
signal sig_1140 : std_logic;
signal sig_1141 : std_logic;
signal sig_1142 : std_logic;
signal sig_1143 : std_logic;
signal sig_1144 : std_logic;
signal sig_1145 : std_logic;
signal sig_1146 : std_logic;
signal sig_1147 : std_logic;
signal sig_1148 : std_logic;
signal sig_1149 : std_logic;
signal sig_1150 : std_logic;
signal sig_1151 : std_logic;
signal sig_1152 : std_logic;
signal sig_1153 : std_logic;
signal sig_1154 : std_logic;
signal sig_1155 : std_logic;
signal sig_1156 : std_logic;
signal sig_1157 : std_logic;
signal sig_1158 : std_logic;
signal sig_1159 : std_logic;
signal sig_1160 : std_logic;
signal sig_1161 : std_logic;
signal sig_1162 : std_logic;
signal sig_1163 : std_logic;
signal sig_1164 : std_logic;
signal sig_1165 : std_logic;
signal sig_1166 : std_logic;
signal sig_1167 : std_logic;
signal sig_1168 : std_logic;
signal sig_1169 : std_logic;
signal sig_1170 : std_logic;
signal sig_1171 : std_logic;
signal sig_1172 : std_logic;
signal sig_1173 : std_logic;
signal sig_1174 : std_logic;
signal sig_1175 : std_logic;
signal sig_1176 : std_logic;
signal sig_1177 : std_logic;
signal sig_1178 : std_logic;
signal sig_1179 : std_logic;
signal sig_1180 : std_logic;
signal sig_1181 : std_logic;
signal sig_1182 : std_logic;
signal sig_1183 : std_logic;
signal sig_1184 : std_logic;
signal sig_1185 : std_logic;
signal sig_1186 : std_logic;
signal sig_1187 : std_logic;
signal sig_1188 : std_logic;
signal sig_1189 : std_logic;
signal sig_1190 : std_logic;
signal sig_1191 : std_logic;
signal sig_1192 : std_logic;
signal sig_1193 : std_logic;
signal sig_1194 : std_logic;
signal sig_1195 : std_logic;
signal sig_1196 : std_logic;
signal sig_1197 : std_logic;
signal sig_1198 : std_logic;
signal sig_1199 : std_logic;
signal sig_1200 : std_logic;
signal sig_1201 : std_logic;
signal sig_1202 : std_logic;
signal sig_1203 : std_logic;
signal sig_1204 : std_logic;
signal sig_1205 : std_logic;
signal sig_1206 : std_logic;
signal sig_1207 : std_logic;
signal sig_1208 : std_logic;
signal sig_1209 : std_logic;
signal sig_1210 : std_logic;
signal sig_1211 : std_logic;
signal sig_1212 : std_logic;
signal sig_1213 : std_logic;
signal sig_1214 : std_logic;
signal sig_1215 : std_logic;
signal sig_1216 : std_logic;
signal sig_1217 : std_logic;
signal sig_1218 : std_logic;
signal sig_1219 : std_logic;
signal sig_1220 : std_logic;
signal sig_1221 : std_logic;
signal sig_1222 : std_logic;
signal sig_1223 : std_logic;
signal sig_1224 : std_logic;
signal sig_1225 : std_logic;
signal sig_1226 : std_logic;
signal sig_1227 : std_logic;
signal sig_1228 : std_logic;
signal sig_1229 : std_logic;
signal sig_1230 : std_logic;
signal sig_1231 : std_logic;
signal sig_1232 : std_logic;
signal sig_1233 : std_logic;
signal sig_1234 : std_logic;
signal sig_1235 : std_logic;
signal sig_1236 : std_logic;
signal sig_1237 : std_logic;
signal sig_1238 : std_logic;
signal sig_1239 : std_logic;
signal sig_1240 : std_logic;
signal sig_1241 : std_logic;
signal sig_1242 : std_logic;
signal sig_1243 : std_logic;
signal sig_1244 : std_logic;
signal sig_1245 : std_logic;
signal sig_1246 : std_logic;
signal sig_1247 : std_logic;
signal sig_1248 : std_logic;
signal sig_1249 : std_logic;
signal sig_1250 : std_logic;
signal sig_1251 : std_logic;
signal sig_1252 : std_logic;
signal sig_1253 : std_logic;
signal sig_1254 : std_logic;
signal sig_1255 : std_logic;
signal sig_1256 : std_logic;
signal sig_1257 : std_logic;
signal sig_1258 : std_logic;
signal sig_1259 : std_logic;
signal sig_1260 : std_logic;
signal sig_1261 : std_logic;
signal sig_1262 : std_logic;
signal sig_1263 : std_logic;
signal sig_1264 : std_logic;
signal sig_1265 : std_logic;
signal sig_1266 : std_logic;
signal sig_1267 : std_logic;
signal sig_1268 : std_logic;
signal sig_1269 : std_logic;
signal sig_1270 : std_logic;
signal sig_1271 : std_logic;
signal sig_1272 : std_logic;
signal sig_1273 : std_logic;
signal sig_1274 : std_logic;
signal sig_1275 : std_logic;
signal sig_1276 : std_logic;
signal sig_1277 : std_logic;
signal sig_1278 : std_logic;
signal sig_1279 : std_logic;
signal sig_1280 : std_logic;
signal sig_1281 : std_logic;
signal sig_1282 : std_logic;
signal sig_1283 : std_logic;
signal sig_1284 : std_logic;
signal sig_1285 : std_logic;
signal sig_1286 : std_logic;
signal sig_1287 : std_logic;
signal sig_1288 : std_logic;
signal sig_1289 : std_logic;
signal sig_1290 : std_logic;
signal sig_1291 : std_logic;
signal sig_1292 : std_logic;
signal sig_1293 : std_logic;
signal sig_1294 : std_logic;
signal sig_1295 : std_logic;
signal sig_1296 : std_logic;
signal sig_1297 : std_logic;
signal sig_1298 : std_logic;
signal sig_1299 : std_logic;
signal sig_1300 : std_logic;
signal sig_1301 : std_logic;
signal sig_1302 : std_logic;
signal sig_1303 : std_logic;
signal sig_1304 : std_logic;
signal sig_1305 : std_logic;
signal sig_1306 : std_logic;
signal sig_1307 : std_logic;
signal sig_1308 : std_logic;
signal sig_1309 : std_logic;
signal sig_1310 : std_logic;
signal sig_1311 : std_logic;
signal sig_1312 : std_logic;
signal sig_1313 : std_logic;
signal sig_1314 : std_logic;
signal sig_1315 : std_logic;
signal sig_1316 : std_logic;
signal sig_1317 : std_logic;
signal sig_1318 : std_logic;
signal sig_1319 : std_logic;
signal sig_1320 : std_logic;
signal sig_1321 : std_logic;
signal sig_1322 : std_logic;
signal sig_1323 : std_logic;
signal sig_1324 : std_logic;
signal sig_1325 : std_logic;
signal sig_1326 : std_logic;
signal sig_1327 : std_logic;
signal sig_1328 : std_logic;
signal sig_1329 : std_logic;
signal sig_1330 : std_logic;
signal sig_1331 : std_logic;
signal sig_1332 : std_logic;
signal sig_1333 : std_logic;
signal sig_1334 : std_logic;
signal sig_1335 : std_logic;
signal sig_1336 : std_logic;
signal sig_1337 : std_logic;
signal sig_1338 : std_logic;
signal sig_1339 : std_logic;
signal sig_1340 : std_logic;
signal sig_1341 : std_logic;
signal sig_1342 : std_logic;
signal sig_1343 : std_logic;
signal sig_1344 : std_logic;
signal sig_1345 : std_logic;
signal sig_1346 : std_logic;
signal sig_1347 : std_logic;
signal sig_1348 : std_logic;
signal sig_1349 : std_logic;
signal sig_1350 : std_logic;
signal sig_1351 : std_logic;
signal sig_1352 : std_logic;
signal sig_1353 : std_logic;
signal sig_1354 : std_logic;
signal sig_1355 : std_logic;
signal sig_1356 : std_logic;
signal sig_1357 : std_logic;
signal sig_1358 : std_logic;
signal sig_1359 : std_logic;
signal sig_1360 : std_logic;
signal sig_1361 : std_logic;
signal sig_1362 : std_logic;
signal sig_1363 : std_logic;
signal sig_1364 : std_logic;
signal sig_1365 : std_logic;
signal sig_1366 : std_logic;
signal sig_1367 : std_logic;
signal sig_1368 : std_logic;
signal sig_1369 : std_logic;
signal sig_1370 : std_logic;
signal sig_1371 : std_logic;
signal sig_1372 : std_logic;
signal sig_1373 : std_logic;
signal sig_1374 : std_logic;
signal sig_1375 : std_logic;
signal sig_1376 : std_logic;
signal sig_1377 : std_logic;
signal sig_1378 : std_logic;
signal sig_1379 : std_logic;
signal sig_1380 : std_logic;
signal sig_1381 : std_logic;
signal sig_1382 : std_logic;
signal sig_1383 : std_logic;
signal sig_1384 : std_logic;
signal sig_1385 : std_logic;
signal sig_1386 : std_logic;
signal sig_1387 : std_logic;
signal sig_1388 : std_logic;
signal sig_1389 : std_logic;
signal sig_1390 : std_logic;
signal sig_1391 : std_logic;
signal sig_1392 : std_logic;
signal sig_1393 : std_logic;
signal sig_1394 : std_logic;
signal sig_1395 : std_logic;
signal sig_1396 : std_logic;
signal sig_1397 : std_logic;
signal sig_1398 : std_logic;
signal sig_1399 : std_logic;
signal sig_1400 : std_logic;
signal sig_1401 : std_logic;
signal sig_1402 : std_logic;
signal sig_1403 : std_logic;
signal sig_1404 : std_logic;
signal sig_1405 : std_logic;
signal sig_1406 : std_logic;
signal sig_1407 : std_logic;
signal sig_1408 : std_logic;
signal sig_1409 : std_logic;
signal sig_1410 : std_logic;
signal sig_1411 : std_logic;
signal sig_1412 : std_logic;
signal sig_1413 : std_logic;
signal sig_1414 : std_logic;
signal sig_1415 : std_logic;
signal sig_1416 : std_logic;
signal sig_1417 : std_logic;
signal sig_1418 : std_logic;
signal sig_1419 : std_logic;
signal sig_1420 : std_logic;
signal sig_1421 : std_logic;
signal sig_1422 : std_logic;
signal sig_1423 : std_logic;
signal sig_1424 : std_logic;
signal sig_1425 : std_logic;
signal sig_1426 : std_logic;
signal sig_1427 : std_logic;
signal sig_1428 : std_logic;
signal sig_1429 : std_logic;
signal sig_1430 : std_logic;
signal sig_1431 : std_logic;
signal sig_1432 : std_logic;
signal sig_1433 : std_logic;
signal sig_1434 : std_logic;
signal sig_1435 : std_logic;
signal sig_1436 : std_logic;
signal sig_1437 : std_logic;
signal sig_1438 : std_logic;
signal sig_1439 : std_logic;
signal sig_1440 : std_logic;
signal sig_1441 : std_logic;
signal sig_1442 : std_logic;
signal sig_1443 : std_logic;
signal sig_1444 : std_logic;
signal sig_1445 : std_logic;
signal sig_1446 : std_logic;
signal sig_1447 : std_logic;
signal sig_1448 : std_logic;
signal sig_1449 : std_logic;
signal sig_1450 : std_logic;
signal sig_1451 : std_logic;
signal sig_1452 : std_logic;
signal sig_1453 : std_logic;
signal sig_1454 : std_logic;
signal sig_1455 : std_logic;
signal sig_1456 : std_logic;
signal sig_1457 : std_logic;
signal sig_1458 : std_logic;
signal sig_1459 : std_logic;
signal sig_1460 : std_logic;
signal sig_1461 : std_logic;
signal sig_1462 : std_logic;
signal sig_1463 : std_logic;
signal sig_1464 : std_logic;
signal sig_1465 : std_logic;
signal sig_1466 : std_logic;
signal sig_1467 : std_logic;
signal sig_1468 : std_logic;
signal sig_1469 : std_logic;
signal sig_1470 : std_logic;
signal sig_1471 : std_logic;
signal sig_1472 : std_logic;
signal sig_1473 : std_logic;
signal sig_1474 : std_logic;
signal sig_1475 : std_logic;
signal sig_1476 : std_logic;
signal sig_1477 : std_logic;
signal sig_1478 : std_logic;
signal sig_1479 : std_logic;
signal sig_1480 : std_logic;
signal sig_1481 : std_logic;
signal sig_1482 : std_logic;
signal sig_1483 : std_logic;
signal sig_1484 : std_logic;
signal sig_1485 : std_logic;
signal sig_1486 : std_logic;
signal sig_1487 : std_logic;
signal sig_1488 : std_logic;
signal sig_1489 : std_logic;
signal sig_1490 : std_logic;
signal sig_1491 : std_logic;
signal sig_1492 : std_logic;
signal sig_1493 : std_logic;
signal sig_1494 : std_logic;
signal sig_1495 : std_logic;
signal sig_1496 : std_logic;
signal sig_1497 : std_logic;
signal sig_1498 : std_logic;
signal sig_1499 : std_logic;
signal sig_1500 : std_logic;
signal sig_1501 : std_logic;
signal sig_1502 : std_logic;
signal sig_1503 : std_logic;
signal sig_1504 : std_logic;
signal sig_1505 : std_logic;
signal sig_1506 : std_logic;
signal sig_1507 : std_logic;
signal sig_1508 : std_logic;
signal sig_1509 : std_logic;
signal sig_1510 : std_logic;
signal sig_1511 : std_logic;
signal sig_1512 : std_logic;
signal sig_1513 : std_logic;
signal sig_1514 : std_logic;
signal sig_1515 : std_logic;
signal sig_1516 : std_logic;
signal sig_1517 : std_logic;
signal sig_1518 : std_logic;
signal sig_1519 : std_logic;
signal sig_1520 : std_logic;
signal sig_1521 : std_logic;
signal sig_1522 : std_logic;
signal sig_1523 : std_logic;
signal sig_1524 : std_logic;
signal sig_1525 : std_logic;
signal sig_1526 : std_logic;
signal sig_1527 : std_logic;
signal sig_1528 : std_logic;
signal sig_1529 : std_logic;
signal sig_1530 : std_logic;
signal sig_1531 : std_logic;
signal sig_1532 : std_logic;
signal sig_1533 : std_logic;
signal sig_1534 : std_logic;
signal sig_1535 : std_logic;
signal sig_1536 : std_logic;
signal sig_1537 : std_logic;
signal sig_1538 : std_logic;
signal sig_1539 : std_logic;
signal sig_1540 : std_logic;
signal sig_1541 : std_logic;
signal sig_1542 : std_logic;
signal sig_1543 : std_logic;
signal sig_1544 : std_logic;
signal sig_1545 : std_logic;
signal sig_1546 : std_logic;
signal sig_1547 : std_logic;
signal sig_1548 : std_logic;
signal sig_1549 : std_logic;
signal sig_1550 : std_logic;
signal sig_1551 : std_logic;
signal sig_1552 : std_logic;
signal sig_1553 : std_logic;
signal sig_1554 : std_logic;
signal sig_1555 : std_logic;
signal sig_1556 : std_logic;
signal sig_1557 : std_logic;
signal sig_1558 : std_logic;
signal sig_1559 : std_logic;
signal sig_1560 : std_logic;
signal sig_1561 : std_logic;
signal sig_1562 : std_logic;
signal sig_1563 : std_logic;
signal sig_1564 : std_logic;
signal sig_1565 : std_logic;
signal sig_1566 : std_logic;
signal sig_1567 : std_logic;
signal sig_1568 : std_logic;
signal sig_1569 : std_logic;
signal sig_1570 : std_logic;
signal sig_1571 : std_logic;
signal sig_1572 : std_logic;
signal sig_1573 : std_logic;
signal sig_1574 : std_logic;
signal sig_1575 : std_logic;
signal sig_1576 : std_logic;
signal sig_1577 : std_logic;
signal sig_1578 : std_logic;
signal sig_1579 : std_logic;
signal sig_1580 : std_logic;
signal sig_1581 : std_logic;
signal sig_1582 : std_logic;
signal sig_1583 : std_logic;
signal sig_1584 : std_logic;
signal sig_1585 : std_logic_vector(40 downto 0);
signal sig_1586 : std_logic;
signal sig_1587 : std_logic_vector(40 downto 0);
signal sig_1588 : std_logic_vector(40 downto 0);
signal sig_1589 : std_logic;
signal sig_1590 : std_logic_vector(40 downto 0);
signal sig_1591 : std_logic;
signal sig_1592 : std_logic_vector(40 downto 0);
signal sig_1593 : std_logic;
signal sig_1594 : std_logic;
signal sig_1595 : std_logic;
signal sig_1596 : std_logic_vector(40 downto 0);
signal sig_1597 : std_logic;
signal sig_1598 : std_logic;
signal sig_1599 : std_logic;
signal sig_1600 : std_logic_vector(40 downto 0);
signal sig_1601 : std_logic;
signal sig_1602 : std_logic;
signal sig_1603 : std_logic;
signal sig_1604 : std_logic;
signal sig_1605 : std_logic;
signal sig_1606 : std_logic;
signal sig_1607 : std_logic;
signal sig_1608 : std_logic;
signal sig_1609 : std_logic_vector(38 downto 0);
signal sig_1610 : std_logic_vector(38 downto 0);
signal sig_1611 : std_logic_vector(24 downto 0);
signal sig_1612 : std_logic_vector(38 downto 0);
signal sig_1613 : std_logic_vector(31 downto 0);
signal sig_1614 : std_logic_vector(40 downto 0);
signal sig_1615 : std_logic;
signal sig_1616 : std_logic;
signal sig_1617 : std_logic;
signal sig_1618 : std_logic;
signal sig_1619 : std_logic_vector(40 downto 0);
signal sig_1620 : std_logic;
signal sig_1621 : std_logic_vector(40 downto 0);
signal sig_1622 : std_logic;
signal sig_1623 : std_logic;
signal sig_1624 : std_logic_vector(40 downto 0);
signal sig_1625 : std_logic;
signal sig_1626 : std_logic_vector(31 downto 0);
signal sig_1627 : std_logic_vector(40 downto 0);
signal sig_1628 : std_logic_vector(40 downto 0);
signal sig_1629 : std_logic_vector(31 downto 0);
signal sig_1630 : std_logic_vector(5 downto 0);
signal sig_1631 : std_logic_vector(7 downto 0);
signal sig_1632 : std_logic_vector(31 downto 0);
signal sig_1633 : std_logic_vector(31 downto 0);
signal sig_1634 : std_logic_vector(31 downto 0);
signal sig_1635 : std_logic_vector(31 downto 0);
signal sig_1636 : std_logic_vector(31 downto 0);
signal sig_1637 : std_logic_vector(31 downto 0);
signal sig_1638 : std_logic_vector(20 downto 0);
signal sig_1639 : std_logic_vector(31 downto 0);
signal sig_1640 : std_logic_vector(31 downto 0);
signal sig_1641 : std_logic_vector(31 downto 0);
signal sig_1642 : std_logic_vector(31 downto 0);
signal sig_1643 : std_logic_vector(31 downto 0);
signal sig_1644 : std_logic_vector(7 downto 0);
signal sig_1645 : std_logic_vector(5 downto 0);
signal sig_1646 : std_logic_vector(7 downto 0);
signal sig_1647 : std_logic_vector(31 downto 0);
signal sig_1648 : std_logic_vector(31 downto 0);
signal sig_1649 : std_logic_vector(8 downto 0);
signal sig_1650 : std_logic_vector(8 downto 0);
signal sig_1651 : std_logic_vector(31 downto 0);
signal sig_1652 : std_logic_vector(31 downto 0);
signal sig_1653 : std_logic_vector(8 downto 0);
signal sig_1654 : std_logic_vector(8 downto 0);
signal sig_1655 : std_logic_vector(31 downto 0);
signal sig_1656 : std_logic_vector(31 downto 0);
signal sig_1657 : std_logic_vector(31 downto 0);
signal sig_1658 : std_logic_vector(31 downto 0);
signal sig_1659 : std_logic_vector(31 downto 0);
signal sig_1660 : std_logic_vector(31 downto 0);
signal sig_1661 : std_logic_vector(31 downto 0);
signal sig_1662 : std_logic;
signal sig_1663 : std_logic_vector(1 downto 0);
signal sig_1664 : std_logic_vector(7 downto 0);
signal sig_1665 : std_logic_vector(7 downto 0);
signal sig_1666 : std_logic_vector(40 downto 0);
signal sig_1667 : std_logic_vector(40 downto 0);
signal sig_1668 : std_logic_vector(40 downto 0);
signal sig_1669 : std_logic;
signal sig_1670 : std_logic;
signal sig_1671 : std_logic_vector(31 downto 0);
signal sig_1672 : std_logic_vector(31 downto 0);
signal sig_1673 : std_logic_vector(40 downto 0);
signal sig_1674 : std_logic_vector(40 downto 0);
signal sig_1675 : std_logic_vector(40 downto 0);
signal sig_1676 : std_logic_vector(40 downto 0);
signal sig_1677 : std_logic_vector(31 downto 0);
signal sig_1678 : std_logic_vector(31 downto 0);
signal sig_1679 : std_logic_vector(40 downto 0);
signal sig_1680 : std_logic_vector(31 downto 0);
signal sig_1681 : std_logic_vector(31 downto 0);
signal sig_1682 : std_logic_vector(31 downto 0);
signal sig_1683 : std_logic_vector(31 downto 0);
signal sig_1684 : std_logic_vector(31 downto 0);
signal sig_1685 : std_logic_vector(31 downto 0);
signal sig_1686 : std_logic_vector(31 downto 0);
signal sig_1687 : std_logic_vector(31 downto 0);
signal sig_1688 : std_logic_vector(24 downto 0);
signal sig_1689 : std_logic_vector(40 downto 0);
signal sig_1690 : std_logic_vector(31 downto 0);
signal sig_1691 : std_logic_vector(9 downto 0);
signal sig_1692 : std_logic_vector(8 downto 0);
signal sig_1693 : std_logic_vector(14 downto 0);
signal sig_1694 : std_logic_vector(14 downto 0);
signal sig_1695 : std_logic_vector(6 downto 0);
signal sig_1696 : std_logic_vector(6 downto 0);
signal sig_1697 : std_logic_vector(6 downto 0);
signal sig_1698 : std_logic_vector(6 downto 0);
signal sig_1699 : std_logic_vector(6 downto 0);
signal sig_1700 : std_logic_vector(6 downto 0);
signal sig_1701 : std_logic_vector(6 downto 0);
signal sig_1702 : std_logic_vector(6 downto 0);
signal sig_1703 : std_logic_vector(9 downto 0);
signal sig_1704 : std_logic_vector(6 downto 0);
signal sig_1705 : std_logic_vector(9 downto 0);
signal sig_1706 : std_logic_vector(6 downto 0);
signal sig_1707 : std_logic_vector(7 downto 0);
signal sig_1708 : std_logic_vector(31 downto 0);
signal sig_1709 : std_logic_vector(31 downto 0);
signal sig_1710 : std_logic_vector(31 downto 0);
signal sig_1711 : std_logic_vector(31 downto 0);
signal sig_1712 : std_logic_vector(31 downto 0);
signal sig_1713 : std_logic_vector(31 downto 0);
signal sig_1714 : std_logic_vector(31 downto 0);
signal sig_1715 : std_logic_vector(31 downto 0);
signal sig_1716 : std_logic_vector(31 downto 0);
-- Other inlined components
signal mux_967 : std_logic_vector(31 downto 0);
signal and_976 : std_logic;
signal and_982 : std_logic_vector(31 downto 0);
signal and_983 : std_logic_vector(27 downto 0);
signal and_984 : std_logic_vector(31 downto 0);
signal mux_689 : std_logic_vector(31 downto 0);
signal mux_690 : std_logic_vector(6 downto 0);
signal mux_691 : std_logic_vector(6 downto 0);
signal and_853 : std_logic_vector(31 downto 0);
signal izigzagmatrix_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_233 : std_logic_vector(31 downto 0);
signal izigzagmatrix_out_idx : std_logic_vector(31 downto 0) := (others => '0');
signal iquantize_qidx : std_logic_vector(1 downto 0) := (others => '0');
signal write8_u8 : std_logic_vector(7 downto 0) := (others => '0');
signal p_jinfo_image_height : std_logic_vector(15 downto 0) := (others => '0');
signal p_jinfo_image_width : std_logic_vector(15 downto 0) := (others => '0');
signal mux_671 : std_logic_vector(31 downto 0);
signal p_jinfo_num_components : std_logic_vector(7 downto 0) := (others => '0');
signal p_jinfo_smp_fact : std_logic_vector(1 downto 0) := (others => '0');
signal mux_665 : std_logic_vector(1 downto 0);
signal mux_663 : std_logic_vector(31 downto 0);
signal mux_664 : std_logic_vector(1 downto 0);
signal mux_659 : std_logic_vector(31 downto 0);
signal mux_660 : std_logic_vector(1 downto 0);
signal mux_661 : std_logic_vector(1 downto 0);
signal mux_652 : std_logic_vector(12 downto 0);
signal mux_648 : std_logic_vector(31 downto 0);
signal mux_633 : std_logic_vector(31 downto 0);
signal mux_622 : std_logic_vector(31 downto 0);
signal mux_614 : std_logic_vector(31 downto 0);
signal mux_616 : std_logic_vector(31 downto 0);
signal p_jinfo_mcuwidth : std_logic_vector(31 downto 0) := (others => '0');
signal mux_602 : std_logic_vector(31 downto 0);
signal p_jinfo_mcuheight : std_logic_vector(31 downto 0) := (others => '0');
signal mux_600 : std_logic_vector(31 downto 0);
signal p_jinfo_nummcu : std_logic_vector(31 downto 0) := (others => '0');
signal i_jinfo_jpeg_data : std_logic_vector(31 downto 0) := (others => '0');
signal mux_593 : std_logic_vector(31 downto 0);
signal curhuffreadbuf_idx : std_logic_vector(31 downto 0) := (others => '0');
signal mux_587 : std_logic_vector(31 downto 0);
signal outdata_image_width : std_logic_vector(7 downto 0) := (others => '0');
signal mux_585 : std_logic_vector(15 downto 0);
signal outdata_image_height : std_logic_vector(7 downto 0) := (others => '0');
signal mux_580 : std_logic_vector(7 downto 0);
signal mux_569 : std_logic_vector(7 downto 0);
signal mux_567 : std_logic_vector(31 downto 0);
signal mux_568 : std_logic_vector(7 downto 0);
signal mux_563 : std_logic_vector(8 downto 0);
signal mux_565 : std_logic_vector(8 downto 0);
signal mux_561 : std_logic_vector(31 downto 0);
signal mux_562 : std_logic_vector(8 downto 0);
signal mux_557 : std_logic_vector(31 downto 0);
signal mux_558 : std_logic_vector(5 downto 0);
signal mux_559 : std_logic_vector(5 downto 0);
signal mux_555 : std_logic_vector(31 downto 0);
signal mux_551 : std_logic_vector(31 downto 0);
signal mux_553 : std_logic_vector(31 downto 0);
signal mux_549 : std_logic_vector(31 downto 0);
signal mux_545 : std_logic_vector(31 downto 0);
signal mux_547 : std_logic_vector(31 downto 0);
signal mux_543 : std_logic_vector(31 downto 0);
signal mux_731 : std_logic_vector(7 downto 0);
signal mux_727 : std_logic_vector(6 downto 0);
signal mux_723 : std_logic_vector(9 downto 0);
signal mux_719 : std_logic_vector(6 downto 0);
signal mux_539 : std_logic_vector(31 downto 0);
signal mux_541 : std_logic_vector(31 downto 0);
signal mux_537 : std_logic_vector(31 downto 0);
signal mux_533 : std_logic_vector(31 downto 0);
signal mux_535 : std_logic_vector(31 downto 0);
signal mux_715 : std_logic_vector(9 downto 0);
signal mux_711 : std_logic;
signal mux_705 : std_logic_vector(31 downto 0);
signal mux_706 : std_logic_vector(6 downto 0);
signal mux_707 : std_logic_vector(6 downto 0);
signal mux_531 : std_logic_vector(31 downto 0);
signal mux_529 : std_logic_vector(31 downto 0);
signal mux_695 : std_logic;
signal mux_524 : std_logic_vector(4 downto 0);
signal mux_521 : std_logic_vector(31 downto 0);
signal readbuf_idx : std_logic_vector(31 downto 0) := (others => '0');
signal read_byte : std_logic_vector(7 downto 0) := (others => '0');
signal read_word : std_logic_vector(15 downto 0) := (others => '0');
signal read_word_c : std_logic_vector(7 downto 0) := (others => '0');
signal mux_519 : std_logic_vector(31 downto 0);
signal mux_517 : std_logic_vector(7 downto 0);
signal next_marker : std_logic_vector(7 downto 0) := (others => '0');
signal next_marker_c : std_logic_vector(7 downto 0) := (others => '0');
signal get_sof_ci : std_logic_vector(31 downto 0) := (others => '0');
signal mux_507 : std_logic_vector(31 downto 0);
signal mux_505 : std_logic_vector(31 downto 0);
signal get_sof_i_comp_info_id : std_logic_vector(1 downto 0) := (others => '0');
signal mux_501 : std_logic_vector(31 downto 0);
signal get_sof_i_comp_info_h_samp_factor : std_logic_vector(1 downto 0) := (others => '0');
signal get_sof_i_comp_info_quant_tbl_no : std_logic_vector(1 downto 0) := (others => '0');
signal mux_492 : std_logic_vector(31 downto 0);
signal mux_488 : std_logic_vector(31 downto 0);
signal mux_490 : std_logic_vector(31 downto 0);
signal get_sos_num_comp : std_logic_vector(7 downto 0) := (others => '0');
signal mux_486 : std_logic_vector(31 downto 0);
signal get_sos_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_482 : std_logic_vector(31 downto 0);
signal mux_484 : std_logic_vector(31 downto 0);
signal get_sos_c : std_logic := '0';
signal mux_480 : std_logic_vector(31 downto 0);
signal get_sos_cc : std_logic_vector(7 downto 0) := (others => '0');
signal mux_476 : std_logic_vector(31 downto 0);
signal mux_478 : std_logic_vector(8 downto 0);
signal get_sos_ci : std_logic_vector(31 downto 0) := (others => '0');
signal get_sos_j : std_logic_vector(31 downto 0) := (others => '0');
signal get_sos_i_comp_info_dc_tbl_no : std_logic_vector(1 downto 0) := (others => '0');
signal get_dht_length : std_logic_vector(31 downto 0) := (others => '0');
signal get_dht_index : std_logic := '0';
signal mux_459 : std_logic_vector(31 downto 0);
signal get_dht_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_455 : std_logic_vector(31 downto 0);
signal mux_457 : std_logic_vector(31 downto 0);
signal get_dht_count : std_logic_vector(31 downto 0) := (others => '0');
signal mux_453 : std_logic_vector(31 downto 0);
signal mux_449 : std_logic_vector(31 downto 0);
signal mux_451 : std_logic_vector(31 downto 0);
signal get_dht_is_ac : std_logic := '0';
signal get_dqt_length : std_logic_vector(31 downto 0) := (others => '0');
signal mux_447 : std_logic_vector(31 downto 0);
signal get_dqt_prec : std_logic_vector(3 downto 0) := (others => '0');
signal mux_443 : std_logic_vector(31 downto 0);
signal mux_445 : std_logic_vector(8 downto 0);
signal get_dqt_num : std_logic_vector(1 downto 0) := (others => '0');
signal get_dqt_i : std_logic_vector(31 downto 0) := (others => '0');
signal get_dqt_tmp : std_logic_vector(15 downto 0) := (others => '0');
signal read_markers_unread_marker : std_logic_vector(7 downto 0) := (others => '0');
signal read_markers_sow_soi : std_logic := '0';
signal mux_430 : std_logic_vector(31 downto 0);
signal mux_422 : std_logic_vector(31 downto 0);
signal mux_424 : std_logic_vector(31 downto 0);
signal chenidct_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_416 : std_logic_vector(31 downto 0);
signal chenidct_aidx : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_a0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_410 : std_logic_vector(31 downto 0);
signal chenidct_a1 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_408 : std_logic_vector(31 downto 0);
signal chenidct_a2 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_a3 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_b0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_398 : std_logic_vector(31 downto 0);
signal mux_400 : std_logic_vector(31 downto 0);
signal chenidct_b1 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_b2 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_392 : std_logic_vector(31 downto 0);
signal mux_394 : std_logic_vector(31 downto 0);
signal chenidct_b3 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c1 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c2 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c3 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_378 : std_logic_vector(7 downto 0);
signal mux_379 : std_logic_vector(9 downto 0);
signal mux_375 : std_logic_vector(1 downto 0);
signal mux_373 : std_logic_vector(1 downto 0);
signal current_read_byte : std_logic_vector(31 downto 0) := (others => '0');
signal mux_365 : std_logic_vector(31 downto 0);
signal mux_367 : std_logic_vector(31 downto 0);
signal read_position : std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
signal pgetc : std_logic_vector(7 downto 0) := (others => '0');
signal pgetc_temp : std_logic_vector(7 downto 0) := (others => '0');
signal buf_getb : std_logic := '0';
signal buf_getv : std_logic_vector(31 downto 0) := (others => '0');
signal buf_getv_n : std_logic_vector(31 downto 0) := (others => '0');
signal mux_363 : std_logic_vector(31 downto 0);
signal buf_getv_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_359 : std_logic_vector(31 downto 0);
signal mux_361 : std_logic_vector(31 downto 0);
signal buf_getv_rv : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_tbl_no : std_logic := '0';
signal huff_make_dhuff_tb_ac_p_dhtbl_ml : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_i_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_j : std_logic_vector(31 downto 0) := (others => '0');
signal mux_347 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_ac_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_345 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_ac_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_341 : std_logic_vector(2 downto 0);
signal mux_343 : std_logic_vector(1 downto 0);
signal huff_make_dhuff_tb_ac_size : std_logic_vector(31 downto 0) := (others => '0');
signal mux_339 : std_logic_vector(2 downto 0);
signal huff_make_dhuff_tb_ac_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_335 : std_logic_vector(31 downto 0);
signal mux_337 : std_logic_vector(2 downto 0);
signal mux_333 : std_logic_vector(31 downto 0);
signal mux_331 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_dc_tbl_no : std_logic := '0';
signal huff_make_dhuff_tb_dc_p_dhtbl_ml : std_logic_vector(31 downto 0) := (others => '0');
signal mux_323 : std_logic_vector(5 downto 0);
signal huff_make_dhuff_tb_dc_i_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_320 : std_logic_vector(31 downto 0);
signal mux_322 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc_j : std_logic_vector(31 downto 0) := (others => '0');
signal mux_317 : std_logic_vector(1 downto 0);
signal huff_make_dhuff_tb_dc_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_314 : std_logic_vector(31 downto 0);
signal mux_315 : std_logic_vector(31 downto 0);
signal mux_316 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_313 : std_logic_vector(8 downto 0);
signal huff_make_dhuff_tb_dc_size : std_logic_vector(31 downto 0) := (others => '0');
signal mux_308 : std_logic_vector(2 downto 0);
signal huff_make_dhuff_tb_dc_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_306 : std_logic_vector(40 downto 0);
signal mux_307 : std_logic_vector(40 downto 0);
signal mux_302 : std_logic_vector(40 downto 0);
signal mux_303 : std_logic_vector(40 downto 0);
signal decodehuffman_ac : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_ac_tbl_no : std_logic := '0';
signal mux_294 : std_logic_vector(1 downto 0);
signal decodehuffman_ac_dhuff_ml : std_logic_vector(5 downto 0) := (others => '0');
signal mux_290 : std_logic_vector(40 downto 0);
signal mux_291 : std_logic_vector(40 downto 0);
signal mux_292 : std_logic_vector(31 downto 0);
signal decodehuffman_ac_code : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_ac_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_286 : std_logic_vector(31 downto 0);
signal decodehuffman_ac_p : std_logic_vector(8 downto 0) := (others => '0');
signal decodehuffman_dc : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_dc_tbl_no : std_logic := '0';
signal decodehuffman_dc_dhuff_ml : std_logic_vector(5 downto 0) := (others => '0');
signal mux_275 : std_logic_vector(31 downto 0);
signal decodehuffman_dc_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_272 : std_logic_vector(38 downto 0);
signal mux_274 : std_logic_vector(31 downto 0);
signal decodehuffman_dc_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_271 : std_logic_vector(38 downto 0);
signal decodehuffman_dc_p : std_logic_vector(8 downto 0) := (others => '0');
signal decodehuffmcu_bufdim1 : std_logic_vector(1 downto 0) := (others => '0');
signal mux_266 : std_logic_vector(38 downto 0);
signal mux_265 : std_logic_vector(38 downto 0);
signal decodehuffmcu_s : std_logic_vector(31 downto 0) := (others => '0');
signal mux_260 : std_logic_vector(38 downto 0);
signal mux_261 : std_logic_vector(38 downto 0);
signal mux_262 : std_logic_vector(31 downto 0);
signal decodehuffmcu_diff : std_logic_vector(31 downto 0) := (others => '0');
signal mux_257 : std_logic_vector(31 downto 0);
signal decodehuffmcu_tbl_no : std_logic := '0';
signal decodehuffmcu_i : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffmcu_k : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffmcu_n : std_logic_vector(27 downto 0) := (others => '0');
signal writeoneblock_outidx : std_logic_vector(1 downto 0) := (others => '0');
signal writeoneblock_indim1 : std_logic_vector(1 downto 0) := (others => '0');
signal writeoneblock_width : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_height : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_voffs : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_hoffs : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_i : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_e : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_inidx : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_diff : std_logic_vector(12 downto 0) := (others => '0');
signal writeblock_i : std_logic_vector(1 downto 0) := (others => '0');
signal write4blocks_i : std_logic_vector(1 downto 0) := (others => '0');
signal write4blocks_voffs : std_logic_vector(31 downto 0) := (others => '0');
signal write4blocks_hoffs : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_p : std_logic_vector(1 downto 0) := (others => '0');
signal yuvtorgb_yidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_uidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_vidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_r : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_g : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_b : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_y : std_logic_vector(23 downto 0) := (others => '0');
signal yuvtorgb_u : std_logic_vector(30 downto 0) := (others => '0');
signal yuvtorgb_v : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_i : std_logic_vector(31 downto 0) := (others => '0');
signal decode_block_comp_no : std_logic_vector(1 downto 0) := (others => '0');
signal decode_block_out_buf_idx : std_logic_vector(2 downto 0) := (others => '0');
signal decode_block_in_buf_idx : std_logic_vector(1 downto 0) := (others => '0');
signal decode_start_i : std_logic_vector(31 downto 0) := (others => '0');
signal decode_start_currentmcu : std_logic_vector(31 downto 0) := (others => '0');
signal nand_786 : std_logic;
signal or_845 : std_logic_vector(31 downto 0);
signal or_854 : std_logic_vector(31 downto 0);
signal or_866 : std_logic_vector(31 downto 0);
signal jpeg2bmp_main_i : std_logic_vector(31 downto 0) := (others => '0');
signal jpeg2bmp_main_j : std_logic_vector(31 downto 0) := (others => '0');
signal read8_ret0_195 : std_logic_vector(7 downto 0) := (others => '0');
signal and_785 : std_logic;
signal and_801 : std_logic_vector(31 downto 0);
signal mux_761 : std_logic_vector(8 downto 0);
signal mux_782 : std_logic_vector(31 downto 0);
signal or_802 : std_logic_vector(23 downto 0);
signal and_803 : std_logic_vector(31 downto 0);
signal mux_822 : std_logic_vector(31 downto 0);
signal mux_823 : std_logic_vector(31 downto 0);
signal mux_776 : std_logic_vector(31 downto 0);
signal mux_820 : std_logic_vector(31 downto 0);
signal mux_824 : std_logic_vector(31 downto 0);
signal mux_825 : std_logic_vector(31 downto 0);
signal mux_760 : std_logic_vector(31 downto 0);
signal and_789 : std_logic;
signal mux_759 : std_logic_vector(5 downto 0);
signal mux_768 : std_logic_vector(31 downto 0);
signal mux_757 : std_logic_vector(7 downto 0);
signal mux_773 : std_logic_vector(7 downto 0);
signal mux_762 : std_logic_vector(31 downto 0);
signal mux_766 : std_logic_vector(31 downto 0);
signal mux_781 : std_logic_vector(31 downto 0);
signal mux_797 : std_logic_vector(31 downto 0);
signal mux_821 : std_logic_vector(31 downto 0);
signal mux_826 : std_logic_vector(31 downto 0);
signal mux_778 : std_logic_vector(31 downto 0);
signal mux_827 : std_logic_vector(31 downto 0);
signal mux_815 : std_logic_vector(31 downto 0);
signal mux_798 : std_logic_vector(31 downto 0);
signal mux_816 : std_logic_vector(31 downto 0);
signal mux_817 : std_logic_vector(31 downto 0);
signal mux_777 : std_logic_vector(31 downto 0);
signal mux_819 : std_logic_vector(31 downto 0);
signal mux_783 : std_logic_vector(31 downto 0);
signal mux_795 : std_logic_vector(31 downto 0);
signal mux_796 : std_logic_vector(31 downto 0);
signal mux_805 : std_logic_vector(31 downto 0);
signal mux_806 : std_logic_vector(31 downto 0);
signal mux_807 : std_logic_vector(31 downto 0);
signal mux_808 : std_logic_vector(31 downto 0);
signal mux_809 : std_logic_vector(31 downto 0);
signal mux_810 : std_logic_vector(31 downto 0);
signal mux_811 : std_logic_vector(31 downto 0);
signal mux_812 : std_logic_vector(31 downto 0);
signal mux_813 : std_logic_vector(31 downto 0);
signal mux_814 : std_logic_vector(31 downto 0);
signal mux_818 : std_logic_vector(31 downto 0);
signal mux_828 : std_logic_vector(31 downto 0);
signal mux_829 : std_logic_vector(31 downto 0);
signal mux_830 : std_logic_vector(31 downto 0);
signal mux_831 : std_logic_vector(31 downto 0);
signal mux_832 : std_logic_vector(31 downto 0);
signal mux_836 : std_logic_vector(31 downto 0);
signal mux_837 : std_logic_vector(31 downto 0);
signal mux_839 : std_logic_vector(31 downto 0);
signal mux_840 : std_logic_vector(31 downto 0);
signal mux_841 : std_logic_vector(31 downto 0);
signal mux_842 : std_logic_vector(31 downto 0);
signal mux_843 : std_logic_vector(31 downto 0);
signal mux_856 : std_logic_vector(31 downto 0);
signal and_864 : std_logic;
signal mux_870 : std_logic_vector(31 downto 0);
signal mux_872 : std_logic_vector(1 downto 0);
signal mux_875 : std_logic_vector(31 downto 0);
signal mux_891 : std_logic_vector(31 downto 0);
signal mux_892 : std_logic_vector(31 downto 0);
signal mux_893 : std_logic_vector(31 downto 0);
signal mux_894 : std_logic_vector(31 downto 0);
signal mux_895 : std_logic_vector(31 downto 0);
signal mux_896 : std_logic_vector(31 downto 0);
signal mux_897 : std_logic_vector(31 downto 0);
signal mux_898 : std_logic_vector(31 downto 0);
signal mux_899 : std_logic_vector(31 downto 0);
signal mux_900 : std_logic_vector(31 downto 0);
signal mux_901 : std_logic_vector(31 downto 0);
signal mux_902 : std_logic_vector(31 downto 0);
signal mux_903 : std_logic_vector(31 downto 0);
signal mux_904 : std_logic_vector(31 downto 0);
signal mux_905 : std_logic_vector(31 downto 0);
signal mux_906 : std_logic_vector(31 downto 0);
signal mux_907 : std_logic_vector(31 downto 0);
signal mux_908 : std_logic_vector(31 downto 0);
signal mux_917 : std_logic_vector(31 downto 0);
signal mux_918 : std_logic_vector(31 downto 0);
signal mux_924 : std_logic_vector(31 downto 0);
signal mux_925 : std_logic_vector(31 downto 0);
signal mux_928 : std_logic_vector(31 downto 0);
signal mux_929 : std_logic_vector(31 downto 0);
signal mux_931 : std_logic_vector(31 downto 0);
signal mux_932 : std_logic_vector(31 downto 0);
signal mux_934 : std_logic_vector(31 downto 0);
signal mux_935 : std_logic_vector(31 downto 0);
signal mux_936 : std_logic_vector(31 downto 0);
signal mux_937 : std_logic_vector(31 downto 0);
signal mux_938 : std_logic_vector(31 downto 0);
signal mux_939 : std_logic_vector(31 downto 0);
signal mux_941 : std_logic_vector(31 downto 0);
signal mux_944 : std_logic_vector(31 downto 0);
signal mux_945 : std_logic_vector(31 downto 0);
signal mux_946 : std_logic_vector(31 downto 0);
signal mux_833 : std_logic_vector(31 downto 0);
signal mux_834 : std_logic_vector(31 downto 0);
signal mux_835 : std_logic_vector(31 downto 0);
signal mux_838 : std_logic_vector(31 downto 0);
signal mux_844 : std_logic_vector(31 downto 0);
signal mux_857 : std_logic_vector(31 downto 0);
signal mux_858 : std_logic_vector(31 downto 0);
signal mux_859 : std_logic_vector(31 downto 0);
signal mux_874 : std_logic_vector(31 downto 0);
signal mux_888 : std_logic_vector(31 downto 0);
signal mux_889 : std_logic_vector(31 downto 0);
signal mux_913 : std_logic_vector(31 downto 0);
signal mux_914 : std_logic_vector(31 downto 0);
signal mux_915 : std_logic_vector(31 downto 0);
signal mux_916 : std_logic_vector(31 downto 0);
signal mux_933 : std_logic_vector(31 downto 0);
signal mux_940 : std_logic_vector(31 downto 0);
signal mux_942 : std_logic_vector(31 downto 0);
signal and_867 : std_logic;
signal mux_909 : std_logic_vector(31 downto 0);
signal mux_910 : std_logic_vector(31 downto 0);
signal mux_911 : std_logic_vector(31 downto 0);
signal mux_920 : std_logic_vector(31 downto 0);
signal mux_921 : std_logic_vector(31 downto 0);
signal mux_926 : std_logic_vector(31 downto 0);
signal mux_927 : std_logic_vector(31 downto 0);
signal mux_943 : std_logic_vector(31 downto 0);
signal mux_886 : std_logic;
signal mux_922 : std_logic_vector(31 downto 0);
signal mux_923 : std_logic_vector(31 downto 0);
signal mux_930 : std_logic_vector(31 downto 0);
signal mux_987 : std_logic_vector(31 downto 0);
signal and_860 : std_logic_vector(31 downto 0);
signal and_881 : std_logic_vector(31 downto 0);
signal and_884 : std_logic_vector(31 downto 0);
signal mux_890 : std_logic_vector(31 downto 0);
signal mux_912 : std_logic_vector(31 downto 0);
signal mux_919 : std_logic_vector(31 downto 0);
signal mux_948 : std_logic_vector(31 downto 0);
signal mux_949 : std_logic_vector(31 downto 0);
signal mux_950 : std_logic_vector(31 downto 0);
signal and_862 : std_logic;
signal mux_953 : std_logic_vector(31 downto 0);
signal mux_954 : std_logic_vector(31 downto 0);
signal mux_955 : std_logic_vector(31 downto 0);
signal mux_951 : std_logic_vector(31 downto 0);
signal mux_952 : std_logic_vector(31 downto 0);
signal mux_959 : std_logic_vector(31 downto 0);
signal mux_960 : std_logic_vector(31 downto 0);
signal mux_961 : std_logic_vector(31 downto 0);
signal mux_965 : std_logic_vector(31 downto 0);
signal mux_966 : std_logic_vector(31 downto 0);
signal and_876 : std_logic_vector(7 downto 0);
signal mux_956 : std_logic_vector(31 downto 0);
signal mux_957 : std_logic_vector(31 downto 0);
signal mux_947 : std_logic_vector(31 downto 0);
signal mux_968 : std_logic_vector(31 downto 0);
signal mux_969 : std_logic_vector(31 downto 0);
signal mux_970 : std_logic_vector(31 downto 0);
signal mux_980 : std_logic_vector(31 downto 0);
signal mux_981 : std_logic_vector(31 downto 0);
signal mux_958 : std_logic_vector(31 downto 0);
signal and_963 : std_logic;
signal mux_986 : std_logic_vector(31 downto 0);
signal mux_988 : std_logic_vector(31 downto 0);
signal mux_989 : std_logic_vector(31 downto 0);
-- This utility function is used for inlining MUX behaviour
-- Little utility function to ease concatenation of an std_logic
-- and explicitely return an std_logic_vector
function repeat(N: natural; B: std_logic) return std_logic_vector is
variable result: std_logic_vector(N-1 downto 0);
begin
result := (others => B);
return result;
end;
begin
-- Instantiation of components
cmp_869_i : cmp_869 port map (
eq => sig_1670,
in1 => sig_1665,
in0 => get_sos_cc
);
cmp_978_i : cmp_978 port map (
ne => augh_test_132,
in1 => sig_1633,
in0 => huff_make_dhuff_tb_dc_size
);
cmp_979_i : cmp_979 port map (
ne => augh_test_124,
in1 => sig_1635,
in0 => huff_make_dhuff_tb_ac_size
);
cmp_847_i : cmp_847 port map (
eq => augh_test_100,
in1 => sig_1716,
in0 => "00000000000000000000000011000000"
);
cmp_855_i : cmp_855 port map (
ne => sig_1669,
in1 => sig_1715,
in0 => "00000000000000000000000000000000"
);
cmp_852_i : cmp_852 port map (
eq => augh_test_94,
in1 => sig_1714,
in0 => "00000000000000000000000000000000"
);
mul_213_i : mul_213 port map (
output => sig_1668,
in_b => "00000000000000000000000000110001",
in_a => chenidct_b3
);
mul_216_i : mul_216 port map (
output => sig_1667,
in_b => sig_1713,
in_a => mux_762
);
mul_214_i : mul_214 port map (
output => sig_1666,
in_b => sig_1712,
in_a => mux_760
);
cmp_846_i : cmp_846 port map (
eq => augh_test_99,
in1 => sig_1711,
in0 => "00000000000000000000000011011000"
);
cmp_848_i : cmp_848 port map (
eq => augh_test_101,
in1 => sig_1710,
in0 => "00000000000000000000000011011010"
);
cmp_849_i : cmp_849 port map (
eq => augh_test_102,
in1 => sig_1709,
in0 => "00000000000000000000000011000100"
);
p_jinfo_comps_info_id_i : p_jinfo_comps_info_id port map (
wa0_data => read_byte,
wa0_addr => get_sof_i_comp_info_id,
clk => sig_clock,
ra0_addr => get_sos_ci(1 downto 0),
ra0_data => sig_1665,
wa0_en => sig_1213
);
p_jinfo_comps_info_h_samp_factor_i : p_jinfo_comps_info_h_samp_factor port map (
wa0_data => and_876,
wa0_addr => get_sof_i_comp_info_h_samp_factor,
clk => sig_clock,
ra0_addr => "00",
ra0_data => sig_1664,
wa0_en => sig_1214
);
p_jinfo_comps_info_quant_tbl_no_i : p_jinfo_comps_info_quant_tbl_no port map (
wa0_data => read_byte(1 downto 0),
wa0_addr => get_sof_i_comp_info_quant_tbl_no,
clk => sig_clock,
ra0_addr => decode_block_comp_no,
ra0_data => sig_1663,
wa0_en => sig_1212
);
p_jinfo_comps_info_dc_tbl_no_i : p_jinfo_comps_info_dc_tbl_no port map (
wa0_data => get_sos_c,
wa0_addr => get_sos_i_comp_info_dc_tbl_no,
clk => sig_clock,
ra0_addr => decode_block_comp_no,
ra0_data => sig_1662,
wa0_en => sig_1252
);
p_jinfo_quant_tbl_quantval_i : p_jinfo_quant_tbl_quantval port map (
wa0_data => sig_1708,
wa0_addr => sig_1707,
clk => sig_clock,
ra0_addr => mux_731,
ra0_data => sig_1661,
wa0_en => sig_1334
);
p_jinfo_dc_xhuff_tbl_bits_i : p_jinfo_dc_xhuff_tbl_bits port map (
wa0_data => mux_782,
wa0_addr => sig_1706,
clk => sig_clock,
ra0_addr => mux_727,
ra0_data => sig_1660,
wa0_en => sig_1457
);
p_jinfo_dc_xhuff_tbl_huffval_i : p_jinfo_dc_xhuff_tbl_huffval port map (
wa0_data => mux_778,
wa0_addr => sig_1705,
clk => sig_clock,
ra0_addr => mux_723,
ra0_data => sig_1659,
wa0_en => sig_1540
);
p_jinfo_ac_xhuff_tbl_bits_i : p_jinfo_ac_xhuff_tbl_bits port map (
wa0_data => mux_783,
wa0_addr => sig_1704,
clk => sig_clock,
ra0_addr => mux_719,
ra0_data => sig_1658,
wa0_en => sig_1457
);
p_jinfo_ac_xhuff_tbl_huffval_i : p_jinfo_ac_xhuff_tbl_huffval port map (
wa0_data => mux_781,
wa0_addr => sig_1703,
clk => sig_clock,
ra0_addr => mux_715,
ra0_data => sig_1657,
wa0_en => sig_1540
);
p_jinfo_dc_dhuff_tbl_ml_i : p_jinfo_dc_dhuff_tbl_ml port map (
wa0_data => huff_make_dhuff_tb_dc,
wa0_addr => sig_1188,
clk => sig_clock,
ra0_addr => mux_711,
ra0_data => sig_1656,
wa0_en => sig_1190
);
p_jinfo_dc_dhuff_tbl_maxcode_i : p_jinfo_dc_dhuff_tbl_maxcode port map (
wa0_data => mux_705,
wa0_addr => mux_706,
clk => sig_clock,
ra0_addr => mux_707,
ra0_data => sig_1655,
wa0_en => sig_1560
);
p_jinfo_dc_dhuff_tbl_mincode_i : p_jinfo_dc_dhuff_tbl_mincode port map (
wa0_data => sig_1632(8 downto 0),
wa0_addr => sig_1702,
clk => sig_clock,
ra0_addr => sig_1701,
ra0_data => sig_1654,
wa0_en => sig_1039
);
p_jinfo_dc_dhuff_tbl_valptr_i : p_jinfo_dc_dhuff_tbl_valptr port map (
wa0_data => huff_make_dhuff_tb_dc_p(8 downto 0),
wa0_addr => sig_1700,
clk => sig_clock,
ra0_addr => sig_1699,
ra0_data => sig_1653,
wa0_en => sig_1039
);
p_jinfo_ac_dhuff_tbl_ml_i : p_jinfo_ac_dhuff_tbl_ml port map (
wa0_data => huff_make_dhuff_tb_ac,
wa0_addr => sig_1183,
clk => sig_clock,
ra0_addr => mux_695,
ra0_data => sig_1652,
wa0_en => sig_1185
);
p_jinfo_ac_dhuff_tbl_maxcode_i : p_jinfo_ac_dhuff_tbl_maxcode port map (
wa0_data => mux_689,
wa0_addr => mux_690,
clk => sig_clock,
ra0_addr => mux_691,
ra0_data => sig_1651,
wa0_en => sig_1522
);
p_jinfo_ac_dhuff_tbl_mincode_i : p_jinfo_ac_dhuff_tbl_mincode port map (
wa0_data => sig_1634(8 downto 0),
wa0_addr => sig_1698,
clk => sig_clock,
ra0_addr => sig_1697,
ra0_data => sig_1650,
wa0_en => sig_1549
);
p_jinfo_ac_dhuff_tbl_valptr_i : p_jinfo_ac_dhuff_tbl_valptr port map (
wa0_data => huff_make_dhuff_tb_ac_p(8 downto 0),
wa0_addr => sig_1696,
clk => sig_clock,
ra0_addr => sig_1695,
ra0_data => sig_1649,
wa0_en => sig_1549
);
outdata_comp_vpos_i : outdata_comp_vpos port map (
wa0_data => mux_663,
wa0_addr => mux_664,
clk => sig_clock,
ra0_addr => mux_665,
ra0_data => sig_1648,
wa0_en => sig_1295
);
outdata_comp_hpos_i : outdata_comp_hpos port map (
wa0_data => mux_659,
wa0_addr => mux_660,
clk => sig_clock,
ra0_addr => mux_661,
ra0_data => sig_1647,
wa0_en => sig_1295
);
outdata_comp_buf_i : outdata_comp_buf port map (
wa0_data => sig_1631,
wa0_addr => sig_1694,
clk => sig_clock,
ra0_addr => sig_1693,
ra0_data => sig_1646,
wa0_en => sig_1013
);
izigzag_index_i : izigzag_index port map (
clk => sig_clock,
ra0_addr => get_dqt_i(5 downto 0),
ra0_data => sig_1645
);
jpegfilebuf_i : jpegfilebuf port map (
wa0_data => read8_ret0_195,
wa0_addr => jpeg2bmp_main_i(12 downto 0),
clk => sig_clock,
ra0_addr => mux_652,
ra0_data => sig_1644,
wa0_en => sig_1041
);
huffbuff_i : huffbuff port map (
wa0_data => mux_567,
wa0_addr => mux_568,
clk => sig_clock,
ra0_addr => mux_569,
ra0_data => sig_1643,
wa0_en => sig_1428
);
idctbuff_i : idctbuff port map (
wa0_data => mux_561,
wa0_addr => mux_562,
clk => sig_clock,
ra2_data => sig_1642,
ra2_addr => mux_563,
ra1_data => sig_1641,
ra1_addr => sig_1692,
ra0_addr => mux_565,
ra0_data => sig_1640,
wa0_en => sig_1474
);
quantbuff_i : quantbuff port map (
wa0_data => mux_557,
wa0_addr => mux_558,
clk => sig_clock,
ra0_addr => mux_559,
ra0_data => sig_1639,
wa0_en => sig_1431
);
extend_mask_i : extend_mask port map (
clk => sig_clock,
ra0_addr => decodehuffmcu_s(4 downto 0),
ra0_data => sig_1638
);
bit_set_mask_i : bit_set_mask port map (
clk => sig_clock,
ra0_addr => mux_524,
ra0_data => sig_1637
);
lmask_i : lmask port map (
clk => sig_clock,
ra0_addr => buf_getv_n(4 downto 0),
ra0_data => sig_1636
);
huff_make_dhuff_tb_ac_huffsize_i : huff_make_dhuff_tb_ac_huffsize port map (
wa0_data => mux_476,
wa0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
clk => sig_clock,
ra0_addr => mux_478,
ra0_data => sig_1635,
wa0_en => sig_1501
);
huff_make_dhuff_tb_ac_huffcode_i : huff_make_dhuff_tb_ac_huffcode port map (
wa0_data => huff_make_dhuff_tb_ac_code,
wa0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
clk => sig_clock,
ra0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
ra0_data => sig_1634,
wa0_en => sig_1024
);
huff_make_dhuff_tb_dc_huffsize_i : huff_make_dhuff_tb_dc_huffsize port map (
wa0_data => mux_443,
wa0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
clk => sig_clock,
ra0_addr => mux_445,
ra0_data => sig_1633,
wa0_en => sig_1530
);
huff_make_dhuff_tb_dc_huffcode_i : huff_make_dhuff_tb_dc_huffcode port map (
wa0_data => huff_make_dhuff_tb_dc_code,
wa0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
clk => sig_clock,
ra0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
ra0_data => sig_1632,
wa0_en => sig_1036
);
rgb_buf_i : rgb_buf port map (
wa0_data => mux_378,
wa0_addr => mux_379,
clk => sig_clock,
ra0_addr => sig_1691,
ra0_data => sig_1631,
wa0_en => sig_1236
);
zigzag_index_i : zigzag_index port map (
clk => sig_clock,
ra0_addr => izigzagmatrix_i(5 downto 0),
ra0_data => sig_1630
);
shr_212_i : shr_212 port map (
output => sig_1629,
input => mux_322,
shift => mux_323,
padding => '0'
);
mul_209_i : mul_209 port map (
output => sig_1628,
in_b => mux_315,
in_a => mux_316
);
mul_210_i : mul_210 port map (
output => sig_1627,
in_b => sig_1690,
in_a => mux_314
);
shl_211_i : shl_211 port map (
output => sig_1626,
input => current_read_byte,
shift => buf_getv_p(5 downto 0),
padding => '0'
);
sub_206_i : sub_206 port map (
gt => sig_1625,
output => sig_1624,
sign => '1',
in_b => mux_306,
in_a => mux_307
);
sub_207_i : sub_207 port map (
ge => sig_1623,
le => sig_1622,
output => sig_1621,
sign => '1',
in_b => mux_302,
in_a => mux_303
);
sub_208_i : sub_208 port map (
ge => sig_1620,
output => sig_1619,
sign => '1',
in_b => "00000000000000000000000000000000000000000",
in_a => sig_1689
);
sub_205_i : sub_205 port map (
gt => sig_1618,
ge => sig_1617,
lt => sig_1616,
le => sig_1615,
output => sig_1614,
sign => '1',
in_b => mux_290,
in_a => mux_291
);
add_202_i : add_202 port map (
output => sig_1613,
in_b => mux_274,
in_a => mux_275
);
add_203_i : add_203 port map (
output => sig_1612,
in_b => mux_271,
in_a => mux_272
);
add_204_i : add_204 port map (
output => sig_1611,
in_b => "0000000000000000000000001",
in_a => sig_1688
);
add_201_i : add_201 port map (
output => sig_1610,
in_b => mux_265,
in_a => mux_266
);
add_200_i : add_200 port map (
output => sig_1609,
in_b => mux_260,
in_a => mux_261
);
cmp_775_i : cmp_775 port map (
eq => augh_test_158,
in1 => sig_1687,
in0 => "00000000000000000000000000001111"
);
cmp_779_i : cmp_779 port map (
eq => sig_1608,
in1 => sig_1686,
in0 => "00000000000000000000000000000000"
);
cmp_780_i : cmp_780 port map (
ne => sig_1607,
in1 => sig_1685,
in0 => "00000000000000000000000000000000"
);
cmp_787_i : cmp_787 port map (
eq => sig_1606,
in1 => '0',
in0 => sig_1610(0)
);
cmp_788_i : cmp_788 port map (
eq => sig_1605,
in1 => "000",
in0 => sig_1642(2 downto 0)
);
cmp_790_i : cmp_790 port map (
ne => sig_1604,
in1 => sig_1624(3 downto 0),
in0 => "0000"
);
cmp_792_i : cmp_792 port map (
eq => augh_test_134,
in1 => sig_1660,
in0 => "00000000000000000000000000000000"
);
cmp_793_i : cmp_793 port map (
eq => augh_test_131,
in1 => sig_1633,
in0 => "00000000000000000000000000000000"
);
cmp_794_i : cmp_794 port map (
eq => augh_test_126,
in1 => sig_1658,
in0 => "00000000000000000000000000000000"
);
cmp_791_i : cmp_791 port map (
ne => augh_test_148,
in1 => decodehuffman_dc,
in0 => "00000000000000000000000000000000"
);
cmp_804_i : cmp_804 port map (
ne => augh_test_113,
in1 => and_803,
in0 => "00000000000000000000000000000000"
);
cmp_800_i : cmp_800 port map (
eq => augh_test_118,
in1 => buf_getv_p,
in0 => "00000000000000000000000000000000"
);
cmp_799_i : cmp_799 port map (
eq => augh_test_123,
in1 => sig_1635,
in0 => "00000000000000000000000000000000"
);
cmp_865_i : cmp_865 port map (
ne => sig_1603,
in1 => sig_1624(2 downto 0),
in0 => "000"
);
cmp_882_i : cmp_882 port map (
eq => augh_test_157,
in1 => and_881,
in0 => "00000000000000000000000000000000"
);
cmp_885_i : cmp_885 port map (
ne => sig_1602,
in1 => and_884,
in0 => "00000000000000000000000000000000"
);
cmp_887_i : cmp_887 port map (
eq => sig_1601,
in1 => and_884,
in0 => "00000000000000000000000000000000"
);
mul_215_i : mul_215 port map (
output => sig_1600,
in_b => "00000000000000000000000111011001",
in_a => chenidct_b2
);
cmp_850_i : cmp_850 port map (
eq => augh_test_103,
in1 => sig_1684,
in0 => "00000000000000000000000011011011"
);
cmp_851_i : cmp_851 port map (
eq => augh_test_104,
in1 => sig_1683,
in0 => "00000000000000000000000011011001"
);
cmp_861_i : cmp_861 port map (
eq => augh_test_150,
in1 => and_860,
in0 => "00000000000000000000000000000000"
);
cmp_871_i : cmp_871 port map (
eq => sig_1599,
in1 => sig_1682,
in0 => "00000000000000000000000000000000"
);
cmp_873_i : cmp_873 port map (
eq => sig_1598,
in1 => sig_1664,
in0 => "00000010"
);
cmp_879_i : cmp_879 port map (
ne => augh_test_6,
in1 => sig_1681,
in0 => "00000000000000000000000011111111"
);
cmp_880_i : cmp_880 port map (
eq => augh_test_9,
in1 => sig_1680,
in0 => "00000000000000000000000011111111"
);
sub_217_i : sub_217 port map (
ge => sig_1597,
output => sig_1596,
sign => '1',
in_b => "00000000000000000000000000000000000000000",
in_a => sig_1679
);
cmp_863_i : cmp_863 port map (
ne => sig_1595,
in1 => sig_1614(2 downto 0),
in0 => "000"
);
cmp_868_i : cmp_868 port map (
eq => sig_1594,
in1 => "000000000000000000000000",
in0 => "000000000000000000000000"
);
cmp_877_i : cmp_877 port map (
ne => augh_test_109,
in1 => sig_1678,
in0 => "00000000000000000000000000000000"
);
cmp_878_i : cmp_878 port map (
ne => augh_test_10,
in1 => sig_1677,
in0 => "00000000000000000000000000000000"
);
sub_218_i : sub_218 port map (
le => sig_1593,
output => sig_1592,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1676
);
sub_220_i : sub_220 port map (
gt => sig_1591,
output => sig_1590,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1675
);
sub_221_i : sub_221 port map (
gt => sig_1589,
output => sig_1588,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1674
);
mul_222_i : mul_222 port map (
output => sig_1587,
in_b => "00000000000000000000000010110101",
in_a => mux_233
);
sub_219_i : sub_219 port map (
le => sig_1586,
output => sig_1585,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1673
);
cmp_962_i : cmp_962 port map (
ne => augh_test_62,
in1 => get_sos_j,
in0 => "11111111111111111111111111111111"
);
cmp_975_i : cmp_975 port map (
ne => augh_test_154,
in1 => decodehuffmcu_s,
in0 => "00000000000000000000000000000000"
);
fsm_224_i : fsm_224 port map (
clock => sig_clock,
reset => sig_reset,
out40 => sig_1584,
in2 => augh_test_152,
in11 => augh_test_131,
out146 => sig_1583,
out148 => sig_1582,
out150 => sig_1581,
out152 => sig_1580,
in12 => augh_test_128,
out153 => sig_1579,
out154 => sig_1578,
in13 => augh_test_127,
out156 => sig_1577,
out157 => sig_1576,
out160 => sig_1575,
out162 => sig_1574,
out165 => sig_1573,
out170 => sig_1572,
out171 => sig_1571,
out173 => sig_1570,
out175 => sig_1569,
out177 => sig_1568,
out180 => sig_1567,
out184 => sig_1566,
in14 => augh_test_126,
out186 => sig_1565,
out189 => sig_1564,
out191 => sig_1563,
out192 => sig_1562,
out193 => sig_1561,
out197 => sig_1560,
out199 => sig_1559,
out201 => sig_1558,
out202 => sig_1557,
out205 => sig_1556,
out207 => sig_1555,
out208 => sig_1554,
out209 => sig_1553,
out210 => sig_1552,
out212 => sig_1551,
out213 => sig_1550,
in15 => augh_test_125,
out221 => sig_1549,
out222 => sig_1548,
out224 => sig_1547,
out225 => sig_1546,
out228 => sig_1545,
out229 => sig_1544,
out230 => sig_1543,
out231 => sig_1542,
out99 => sig_1541,
in6 => augh_test_142,
out92 => sig_1540,
out232 => sig_1539,
in16 => augh_test_123,
out234 => sig_1538,
out236 => sig_1537,
out239 => sig_1536,
out240 => sig_1535,
out241 => sig_1534,
out245 => sig_1533,
out246 => sig_1532,
out247 => sig_1531,
out251 => sig_1530,
out252 => sig_1529,
out253 => sig_1528,
out255 => sig_1527,
out256 => sig_1526,
out258 => sig_1525,
out259 => sig_1524,
in17 => augh_test_120,
out263 => sig_1523,
out264 => sig_1522,
out266 => sig_1521,
in18 => augh_test_119,
out267 => sig_1520,
out268 => sig_1519,
out270 => sig_1518,
out273 => sig_1517,
out275 => sig_1516,
out276 => sig_1515,
in19 => augh_test_118,
out279 => sig_1514,
in20 => augh_test_115,
out281 => sig_1513,
out282 => sig_1512,
in21 => augh_test_114,
out283 => sig_1511,
out286 => sig_1510,
out289 => sig_1509,
out296 => sig_1508,
out297 => sig_1507,
out299 => sig_1506,
out300 => sig_1505,
out304 => sig_1504,
out305 => sig_1503,
in22 => augh_test_113,
out306 => sig_1502,
out310 => sig_1501,
out311 => sig_1500,
out313 => sig_1499,
out314 => sig_1498,
in23 => augh_test_111,
out316 => sig_1497,
out317 => sig_1496,
out320 => sig_1495,
out322 => sig_1494,
out324 => sig_1493,
out325 => sig_1492,
out326 => sig_1491,
out328 => sig_1490,
out332 => sig_1489,
out333 => sig_1488,
out334 => sig_1487,
out335 => sig_1486,
out338 => sig_1485,
out339 => sig_1484,
out341 => sig_1483,
out342 => sig_1482,
out344 => sig_1481,
out93 => sig_1480,
out98 => sig_1479,
out85 => sig_1478,
out87 => sig_1477,
out88 => sig_1476,
out80 => sig_1475,
out82 => sig_1474,
out83 => sig_1473,
out84 => sig_1472,
in5 => augh_test_144,
out77 => sig_1471,
out78 => sig_1470,
out71 => sig_1469,
out72 => sig_1468,
in4 => augh_test_148,
out65 => sig_1467,
out67 => sig_1466,
out60 => sig_1465,
out64 => sig_1464,
in3 => augh_test_151,
out59 => sig_1463,
out53 => sig_1462,
out55 => sig_1461,
out49 => sig_1460,
out44 => sig_1459,
out104 => sig_1458,
out107 => sig_1457,
out111 => sig_1456,
out112 => sig_1455,
out114 => sig_1454,
in7 => augh_test_138,
out117 => sig_1453,
out119 => sig_1452,
out122 => sig_1451,
in8 => augh_test_136,
out128 => sig_1450,
in9 => augh_test_134,
out129 => sig_1449,
out130 => sig_1448,
out133 => sig_1447,
out134 => sig_1446,
out136 => sig_1445,
out137 => sig_1444,
in10 => augh_test_133,
out139 => sig_1443,
out143 => sig_1442,
out144 => sig_1441,
out32 => sig_1440,
out35 => sig_1439,
out27 => sig_1438,
out25 => sig_1437,
out26 => sig_1436,
in1 => augh_test_158,
out15 => sig_1435,
out16 => sig_1434,
out11 => sig_1433,
out13 => sig_1432,
out14 => sig_1431,
out7 => sig_1430,
out1 => sig_1429,
out2 => sig_1428,
out3 => sig_1427,
out4 => sig_1426,
in0 => augh_test_159,
in24 => augh_test_107,
out346 => sig_1425,
out347 => sig_1424,
out348 => sig_1423,
out349 => sig_1422,
in25 => augh_test_106,
out350 => sig_1421,
out351 => sig_1420,
out355 => sig_1419,
out356 => sig_1418,
out357 => sig_1417,
out358 => sig_1416,
out360 => sig_1415,
out362 => sig_1414,
out363 => sig_1413,
out364 => sig_1412,
out365 => sig_1411,
out366 => sig_1410,
out370 => sig_1409,
out371 => sig_1408,
out372 => sig_1407,
out373 => sig_1406,
out375 => sig_1405,
in26 => augh_test_105,
out376 => sig_1404,
out378 => sig_1403,
out379 => sig_1402,
out381 => sig_1401,
out382 => sig_1400,
in27 => augh_test_99,
out384 => sig_1399,
in28 => augh_test_100,
out391 => sig_1398,
out395 => sig_1397,
out396 => sig_1396,
out401 => sig_1395,
out402 => sig_1394,
out403 => sig_1393,
out404 => sig_1392,
out405 => sig_1391,
out407 => sig_1390,
out408 => sig_1389,
out409 => sig_1388,
out410 => sig_1387,
in29 => augh_test_101,
out412 => sig_1386,
out414 => sig_1385,
out415 => sig_1384,
out417 => sig_1383,
out418 => sig_1382,
out419 => sig_1381,
out420 => sig_1380,
out422 => sig_1379,
out424 => sig_1378,
out425 => sig_1377,
out426 => sig_1376,
in30 => augh_test_102,
out428 => sig_1375,
out429 => sig_1374,
out432 => sig_1373,
out433 => sig_1372,
out434 => sig_1371,
out437 => sig_1370,
out440 => sig_1369,
out441 => sig_1368,
in31 => augh_test_103,
out443 => sig_1367,
in32 => augh_test_104,
out445 => sig_1366,
out447 => sig_1365,
out448 => sig_1364,
out450 => sig_1363,
in33 => augh_test_94,
out453 => sig_1362,
out455 => sig_1361,
out458 => sig_1360,
in34 => augh_test_90,
out462 => sig_1359,
out464 => sig_1358,
out467 => sig_1357,
out468 => sig_1356,
out472 => sig_1355,
in35 => augh_test_89,
out478 => sig_1354,
out479 => sig_1353,
out480 => sig_1352,
out487 => sig_1351,
out488 => sig_1350,
in36 => augh_test_83,
out491 => sig_1349,
out496 => sig_1348,
out497 => sig_1347,
out498 => sig_1346,
out500 => sig_1345,
out504 => sig_1344,
out505 => sig_1343,
in37 => augh_test_150,
out506 => sig_1342,
out508 => sig_1341,
in38 => augh_test_77,
out510 => sig_1340,
out513 => sig_1339,
out514 => sig_1338,
out515 => sig_1337,
out517 => sig_1336,
out519 => sig_1335,
in39 => augh_test_72,
out523 => sig_1334,
out526 => sig_1333,
out527 => sig_1332,
out528 => sig_1331,
out530 => sig_1330,
out531 => sig_1329,
out533 => sig_1328,
out534 => sig_1327,
out537 => sig_1326,
out538 => sig_1325,
out549 => sig_1324,
out558 => sig_1323,
out559 => sig_1322,
out561 => sig_1321,
in40 => augh_test_67,
out566 => sig_1320,
out567 => sig_1319,
out568 => sig_1318,
out569 => sig_1317,
out570 => sig_1316,
out572 => sig_1315,
out574 => sig_1314,
out575 => sig_1313,
out577 => sig_1312,
in41 => augh_test_52,
out578 => sig_1311,
out581 => sig_1310,
out589 => sig_1309,
out590 => sig_1308,
out595 => sig_1307,
out597 => sig_1306,
out599 => sig_1305,
out601 => sig_1304,
out602 => sig_1303,
out607 => sig_1302,
out610 => sig_1301,
out612 => sig_1300,
in42 => augh_test_53,
out614 => sig_1299,
out621 => sig_1298,
out628 => sig_1297,
out635 => sig_1296,
out636 => sig_1295,
out638 => sig_1294,
out640 => sig_1293,
out643 => sig_1292,
out646 => sig_1291,
out649 => sig_1290,
out651 => sig_1289,
out656 => sig_1288,
in43 => augh_test_49,
out658 => sig_1287,
out659 => sig_1286,
out661 => sig_1285,
out663 => sig_1284,
out664 => sig_1283,
in44 => augh_test_109,
out667 => sig_1282,
out668 => sig_1281,
out670 => sig_1280,
out672 => sig_1279,
out674 => sig_1278,
in45 => augh_test_26,
out679 => sig_1277,
out681 => sig_1276,
out683 => sig_1275,
out686 => sig_1274,
out688 => sig_1273,
out690 => sig_1272,
out692 => sig_1271,
out694 => sig_1270,
out696 => sig_1269,
out697 => sig_1268,
out698 => sig_1267,
out699 => sig_1266,
out700 => sig_1265,
out703 => sig_1264,
out704 => sig_1263,
out706 => sig_1262,
out708 => sig_1261,
out710 => sig_1260,
out712 => sig_1259,
out715 => sig_1258,
out718 => sig_1257,
in46 => augh_test_10,
out722 => sig_1256,
out724 => sig_1255,
out726 => sig_1254,
out728 => sig_1253,
out731 => sig_1252,
out733 => sig_1251,
out734 => sig_1250,
out737 => sig_1249,
out739 => sig_1248,
out740 => sig_1247,
out743 => sig_1246,
out745 => sig_1245,
out746 => sig_1244,
in47 => augh_test_6,
out749 => sig_1243,
out753 => sig_1242,
out755 => sig_1241,
out759 => sig_1240,
in48 => augh_test_9,
out762 => sig_1239,
out764 => sig_1238,
out765 => sig_1237,
out767 => sig_1236,
out768 => sig_1235,
in49 => augh_test_157,
out772 => sig_1234,
in50 => stdout_ack,
out775 => sig_1233,
out776 => sig_1232,
out778 => sig_1231,
out783 => sig_1230,
out784 => sig_1229,
out787 => sig_1228,
out791 => sig_1227,
in51 => stdin_ack,
out794 => sig_1226,
out795 => sig_1225,
in52 => augh_test_62,
out799 => sig_1224,
out802 => sig_1223,
out806 => sig_1222,
out809 => sig_1221,
out812 => sig_1220,
out815 => sig_1219,
out826 => sig_1218,
out828 => sig_1217,
in53 => augh_test_122,
in54 => augh_test_197,
out843 => sig_1216,
out848 => sig_1215,
out852 => sig_1214,
in55 => augh_test_196,
out855 => sig_1213,
out858 => sig_1212,
in56 => augh_test_189,
out860 => sig_1211,
out861 => sig_1210,
out863 => sig_1209,
out866 => sig_1208,
out872 => sig_1207,
in57 => augh_test_188,
out874 => sig_1206,
out876 => sig_1205,
out879 => sig_1204,
out882 => sig_1203,
out886 => sig_1202,
out887 => sig_1201,
in58 => augh_test_187,
out888 => sig_1200,
out892 => sig_1199,
out894 => sig_1198,
out895 => sig_1197,
out896 => sig_1196,
out901 => sig_1195,
out902 => sig_1194,
out903 => sig_1193,
out905 => sig_1192,
out907 => sig_1191,
out918 => sig_1190,
out920 => sig_1189,
out921 => sig_1188,
out923 => sig_1187,
out925 => sig_1186,
out928 => sig_1185,
out929 => sig_1184,
out931 => sig_1183,
out933 => sig_1182,
out936 => stdout_rdy,
out937 => sig_1181,
out938 => sig_1180,
out939 => sig_1179,
out942 => sig_1178,
out943 => sig_1177,
out944 => sig_1176,
out947 => sig_1175,
out948 => sig_1174,
out949 => sig_1173,
out951 => sig_1172,
in59 => augh_test_186,
out952 => sig_1171,
out953 => sig_1170,
out955 => sig_1169,
out956 => sig_1168,
out957 => sig_1167,
out958 => sig_1166,
in60 => augh_test_184,
in61 => augh_test_183,
out962 => sig_1165,
out963 => sig_1164,
out972 => sig_1163,
out973 => sig_1162,
out974 => sig_1161,
in62 => augh_test_182,
out978 => sig_1160,
out979 => sig_1159,
out981 => sig_1158,
out982 => sig_1157,
out985 => sig_1156,
out986 => sig_1155,
out989 => sig_1154,
in63 => augh_test_180,
in64 => augh_test_179,
in65 => augh_test_178,
in66 => augh_test_194,
in67 => augh_test_154,
in68 => augh_test_130,
in69 => augh_test_132,
in70 => augh_test_124,
in71 => augh_test_171,
in72 => augh_test_168,
in73 => augh_test_167,
in74 => augh_test_166,
in75 => augh_test_165,
in76 => augh_test_108,
in77 => sig_start,
in78 => augh_test_155,
out990 => sig_1153,
out991 => sig_1152,
out993 => sig_1151,
out994 => sig_1150,
out996 => sig_1149,
out997 => sig_1148,
out998 => sig_1147,
out999 => sig_1146,
out1000 => sig_1145,
out1002 => sig_1144,
out1003 => sig_1143,
out1005 => sig_1142,
out1006 => sig_1141,
out1007 => sig_1140,
out1009 => sig_1139,
out1011 => sig_1138,
out1012 => sig_1137,
out1013 => sig_1136,
out1014 => sig_1135,
out1015 => sig_1134,
out1016 => sig_1133,
out1018 => sig_1132,
out1019 => sig_1131,
out1021 => sig_1130,
out1022 => sig_1129,
out1024 => sig_1128,
out1026 => sig_1127,
out1027 => sig_1126,
out1029 => sig_1125,
out1030 => sig_1124,
out1032 => sig_1123,
out1033 => sig_1122,
out1035 => sig_1121,
out1036 => sig_1120,
out1037 => sig_1119,
out1057 => sig_1118,
out1068 => sig_1117,
out1069 => sig_1116,
out1070 => sig_1115,
out1072 => sig_1114,
out1073 => sig_1113,
out1075 => sig_1112,
out1078 => sig_1111,
out1080 => sig_1110,
out1082 => sig_1109,
out1083 => sig_1108,
out1084 => sig_1107,
out1085 => sig_1106,
out1088 => sig_1105,
out1089 => sig_1104,
out1091 => sig_1103,
out1092 => sig_1102,
out1094 => sig_1101,
out1096 => sig_1100,
out1098 => sig_1099,
out1101 => sig_1098,
out1104 => sig_1097,
out1107 => sig_1096,
out1109 => sig_1095,
out1111 => sig_1094,
out1114 => sig_1093,
out1119 => sig_1092,
out1121 => sig_1091,
out1125 => sig_1090,
out1126 => sig_1089,
out1128 => sig_1088,
out1131 => sig_1087,
out1134 => sig_1086,
out1137 => sig_1085,
out1139 => sig_1084,
out1141 => sig_1083,
out1145 => sig_1082,
out1146 => sig_1081,
out1147 => sig_1080,
out1150 => sig_1079,
out1151 => sig_1078,
out1152 => sig_1077,
out1155 => sig_1076,
out1158 => sig_1075,
out1160 => sig_1074,
out1164 => sig_1073,
out1166 => sig_1072,
out1169 => sig_1071,
out1171 => sig_1070,
out1174 => sig_1069,
out1175 => sig_1068,
out1176 => sig_1067,
out1180 => sig_1066,
out1181 => sig_1065,
out1182 => sig_1064,
out1185 => sig_1063,
out1186 => sig_1062,
out1187 => sig_1061,
out1190 => sig_1060,
out1213 => sig_1059,
out1215 => sig_1058,
out1217 => sig_1057,
out1220 => sig_1056,
out1221 => sig_1055,
out1223 => sig_1054,
out1228 => sig_1053,
out1229 => sig_1052,
out1231 => sig_1051,
out1235 => sig_1050,
out1236 => sig_1049,
out1240 => sig_1048,
out1243 => sig_1047,
out1250 => sig_1046,
out1252 => sig_1045,
out1253 => sig_1044,
out1258 => sig_1043,
out1262 => sig_1042,
out1266 => sig_1041,
out1269 => sig_1040,
out1275 => sig_1039,
out1278 => sig_1038,
out1279 => sig_1037,
out1284 => sig_1036,
out1286 => sig_1035,
out1287 => sig_1034,
out1289 => sig_1033,
out1290 => sig_1032,
out1292 => sig_1031,
out1293 => sig_1030,
out1295 => sig_1029,
out1298 => sig_1028,
out1301 => sig_1027,
out1302 => sig_1026,
out1303 => sig_1025,
out1308 => sig_1024,
out1309 => sig_1023,
out1311 => sig_1022,
out1318 => sig_1021,
out1319 => sig_1020,
out1320 => sig_1019,
out1323 => sig_1018,
out1324 => sig_1017,
out1326 => sig_1016,
out1327 => sig_1015,
out1329 => sig_1014,
out1337 => sig_1013,
out1339 => sig_1012,
out1340 => sig_1011,
out1341 => sig_1010,
out1344 => sig_1009,
out1346 => sig_1008,
out1349 => sig_1007,
out1353 => sig_1006,
out1356 => sig_1005,
out1362 => sig_1004,
out1363 => sig_1003,
out1364 => sig_1002,
out1365 => sig_1001,
out1366 => sig_1000,
out1368 => sig_999,
out1370 => sig_998,
out1375 => sig_997,
out1378 => sig_996,
out1381 => sig_995,
out1383 => sig_994,
out1387 => sig_993
);
muxb_784_i : muxb_784 port map (
in_sel => sig_1616,
out_data => sig_992,
in_data0 => sig_1609(31 downto 0),
in_data1 => sig_1613
);
cmp_964_i : cmp_964 port map (
eq => sig_991,
in1 => sig_1635,
in0 => huff_make_dhuff_tb_ac_size
);
cmp_972_i : cmp_972 port map (
ne => augh_test_196,
in1 => jpeg2bmp_main_i,
in0 => "00000000000000000000000000000010"
);
cmp_973_i : cmp_973 port map (
eq => augh_test_180,
in1 => sig_1672,
in0 => "00000000000000000000000000000000"
);
cmp_974_i : cmp_974 port map (
ne => augh_test_194,
in1 => jpeg2bmp_main_i,
in0 => "00000000000000000001010001010110"
);
cmp_985_i : cmp_985 port map (
eq => augh_test_108,
in1 => sig_1671,
in0 => "00000000000000000000000011111111"
);
cmp_971_i : cmp_971 port map (
ne => augh_test_197,
in1 => jpeg2bmp_main_j,
in0 => "00000000000000000001010010111101"
);
cmp_977_i : cmp_977 port map (
eq => sig_990,
in1 => sig_1633,
in0 => huff_make_dhuff_tb_dc_size
);
-- Behaviour of component 'mux_967' model 'mux'
mux_967 <=
(repeat(32, sig_1620) and mux_968);
-- Behaviour of component 'and_976' model 'and'
and_976 <=
sig_1615 and
sig_990;
-- Behaviour of component 'and_982' model 'and'
and_982 <=
"00000000000000000000000000001111" and
decodehuffman_ac;
-- Behaviour of component 'and_983' model 'and'
and_983 <=
"0000000000000000000000001111" and
decodehuffman_ac(31 downto 4);
-- Behaviour of component 'and_984' model 'and'
and_984 <=
sig_1636 and
buf_getv_rv;
-- Behaviour of component 'mux_689' model 'mux'
mux_689 <=
(repeat(32, sig_1034) and sig_1634) or
(repeat(32, sig_1520) and "11111111111111111111111111111111") or
(repeat(32, sig_1523) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_690' model 'mux'
mux_690 <=
(repeat(7, sig_1519) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0)) or
(repeat(7, sig_1523) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_p_dhtbl_ml(5 downto 0));
-- Behaviour of component 'mux_691' model 'mux'
mux_691 <=
(repeat(7, sig_1523) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_p_dhtbl_ml(5 downto 0)) or
(repeat(7, sig_1568) and decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0)) or
(repeat(7, sig_1570) and decodehuffman_ac_tbl_no & decodehuffman_ac_dhuff_ml);
-- Behaviour of component 'and_853' model 'and'
and_853 <=
sig_1636 and
sig_1629;
-- Behaviour of component 'mux_233' model 'mux'
mux_233 <=
(repeat(32, sig_1118) and sig_1609(31 downto 0)) or
(repeat(32, sig_1324) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_671' model 'mux'
mux_671 <=
(repeat(32, sig_1183) and i_jinfo_jpeg_data) or
(repeat(32, sig_1441) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_665' model 'mux'
mux_665 <=
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_663' model 'mux'
mux_663 <=
(repeat(32, sig_1163) and sig_1609(30 downto 0) & sig_1648(0)) or
(repeat(32, sig_1161) and mux_896) or
(repeat(32, sig_1215) and mux_874) or
(repeat(32, sig_1297) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_664' model 'mux'
mux_664 <=
(repeat(2, sig_1043) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_659' model 'mux'
mux_659 <=
(repeat(32, sig_1163) and sig_1610(30 downto 0) & sig_1647(0)) or
(repeat(32, sig_1161) and mux_897) or
(repeat(32, sig_1215) and mux_875) or
(repeat(32, sig_1297) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_660' model 'mux'
mux_660 <=
(repeat(2, sig_1043) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_661' model 'mux'
mux_661 <=
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_652' model 'mux'
mux_652 <=
(repeat(13, sig_1247) and readbuf_idx(12 downto 0)) or
(repeat(13, sig_1441) and curhuffreadbuf_idx(12 downto 0));
-- Behaviour of component 'mux_648' model 'mux'
mux_648 <=
(repeat(32, sig_1247) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_633' model 'mux'
mux_633 <=
(repeat(32, sig_1211) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_622' model 'mux'
mux_622 <=
(repeat(32, sig_1251) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_614' model 'mux'
mux_614 <=
(repeat(32, sig_1269) and "00000000000000000000000000000011") or
(repeat(32, sig_1287) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_616' model 'mux'
mux_616 <=
(repeat(32, sig_1254) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_602' model 'mux'
mux_602 <=
(repeat(32, sig_1198) and "00000000000000000000000000000001") or
(repeat(32, sig_1479) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_600' model 'mux'
mux_600 <=
(repeat(32, sig_1458) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_593' model 'mux'
mux_593 <=
(repeat(32, sig_1240) and mux_870) or
(repeat(32, sig_1317) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_587' model 'mux'
mux_587 <=
(repeat(32, sig_1335) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_585' model 'mux'
mux_585 <=
(repeat(16, sig_1337) and read_word) or
(repeat(16, sig_1339) and "00000000" & read_byte);
-- Behaviour of component 'mux_580' model 'mux'
mux_580 <=
(repeat(8, sig_1346) and read_byte) or
(repeat(8, sig_1348) and next_marker);
-- Behaviour of component 'mux_569' model 'mux'
mux_569 <=
(repeat(8, sig_1027) and decodehuffmcu_bufdim1 & "000000") or
(repeat(8, sig_1268) and decodehuffmcu_bufdim1 & decodehuffmcu_k(5 downto 0)) or
(repeat(8, sig_1436) and decode_block_in_buf_idx & sig_1630);
-- Behaviour of component 'mux_567' model 'mux'
mux_567 <=
(repeat(32, sig_1257) and sig_1610(31 downto 0)) or
(repeat(32, sig_1000) and decodehuffmcu_diff) or
(repeat(32, sig_1202) and buf_getv) or
(repeat(32, sig_1267) and or_866);
-- Behaviour of component 'mux_568' model 'mux'
mux_568 <=
(repeat(8, sig_1266) and decodehuffmcu_bufdim1 & decodehuffmcu_k(5 downto 0)) or
(repeat(8, sig_1000) and decodehuffmcu_bufdim1 & "000000") or
(repeat(8, sig_1443) and decodehuffmcu_bufdim1 & decodehuffmcu_i(5 downto 0)) or
(repeat(8, sig_1429) and decode_start_i(1 downto 0) & "000000");
-- Behaviour of component 'mux_563' model 'mux'
mux_563 <=
(repeat(9, sig_1555) and decode_block_out_buf_idx & "011000") or
(repeat(9, sig_1408) and decode_block_out_buf_idx & "001010") or
(repeat(9, sig_1407) and decode_block_out_buf_idx & "101010") or
(repeat(9, sig_1405) and decode_block_out_buf_idx & "010100") or
(repeat(9, sig_1403) and decode_block_out_buf_idx & "110101") or
(repeat(9, sig_1401) and decode_block_out_buf_idx & "111000") or
(repeat(9, sig_1510) and decode_block_out_buf_idx & "101000") or
(repeat(9, sig_1389) and decode_block_out_buf_idx & "011001") or
(repeat(9, sig_1388) and decode_block_out_buf_idx & "100110") or
(repeat(9, sig_1384) and decode_block_out_buf_idx & "111010") or
(repeat(9, sig_1382) and decode_block_out_buf_idx & "111011") or
(repeat(9, sig_1381) and decode_block_out_buf_idx & "111100") or
(repeat(9, sig_1377) and decode_block_out_buf_idx & "000100") or
(repeat(9, sig_1375) and decode_block_out_buf_idx & "100100") or
(repeat(9, sig_1372) and decode_block_out_buf_idx & "010010") or
(repeat(9, sig_1512) and decode_block_out_buf_idx & "000001") or
(repeat(9, sig_1515) and decode_block_out_buf_idx & "011110") or
(repeat(9, sig_1517) and decode_block_out_buf_idx & "011100") or
(repeat(9, sig_1418) and decode_block_out_buf_idx & "111101") or
(repeat(9, sig_1417) and decode_block_out_buf_idx & "100010") or
(repeat(9, sig_1415) and decode_block_out_buf_idx & "010111") or
(repeat(9, sig_1414) and decode_block_out_buf_idx & chenidct_aidx(5 downto 0)) or
(repeat(9, sig_1451) and decode_block_out_buf_idx & chenidct_i(5 downto 0)) or
(repeat(9, sig_1469) and decode_block_out_buf_idx & "010000") or
(repeat(9, sig_1370) and decode_block_out_buf_idx & "000111") or
(repeat(9, sig_1368) and decode_block_out_buf_idx & "001100") or
(repeat(9, sig_1366) and decode_block_out_buf_idx & "111111") or
(repeat(9, sig_1365) and decode_block_out_buf_idx & "101100") or
(repeat(9, sig_1362) and decode_block_out_buf_idx & "110010") or
(repeat(9, sig_1331) and decode_block_out_buf_idx & "000101") or
(repeat(9, sig_1330) and decode_block_out_buf_idx & "010001") or
(repeat(9, sig_1328) and decode_block_out_buf_idx & "001111") or
(repeat(9, sig_1326) and decode_block_out_buf_idx & "100111") or
(repeat(9, sig_1299) and yuvtorgb_yidx & yuvtorgb_i(5 downto 0)) or
(repeat(9, sig_1281) and decode_block_out_buf_idx & "011101") or
(repeat(9, sig_1279) and decode_block_out_buf_idx & "101110") or
(repeat(9, sig_1278) and decode_block_out_buf_idx & "110110") or
(repeat(9, sig_1265) and decode_block_out_buf_idx & "001110") or
(repeat(9, sig_1261) and decode_block_out_buf_idx & "001001") or
(repeat(9, sig_1238) and decode_block_out_buf_idx & "010110") or
(repeat(9, sig_1232) and decode_block_out_buf_idx & "001011") or
(repeat(9, sig_1177) and decode_block_out_buf_idx & "111110") or
(repeat(9, sig_1174) and decode_block_out_buf_idx & "100001") or
(repeat(9, sig_1171) and decode_block_out_buf_idx & "011111") or
(repeat(9, sig_1159) and decode_block_out_buf_idx & "000000") or
(repeat(9, sig_1157) and decode_block_out_buf_idx & "100000") or
(repeat(9, sig_1153) and decode_block_out_buf_idx & "000010") or
(repeat(9, sig_1151) and decode_block_out_buf_idx & "010101") or
(repeat(9, sig_1146) and decode_block_out_buf_idx & "101001") or
(repeat(9, sig_1144) and decode_block_out_buf_idx & "110111") or
(repeat(9, sig_1141) and decode_block_out_buf_idx & "001000") or
(repeat(9, sig_1137) and decode_block_out_buf_idx & "101011") or
(repeat(9, sig_1134) and decode_block_out_buf_idx & "111001") or
(repeat(9, sig_1132) and decode_block_out_buf_idx & "000110") or
(repeat(9, sig_1130) and decode_block_out_buf_idx & "011010") or
(repeat(9, sig_1126) and decode_block_out_buf_idx & "100101") or
(repeat(9, sig_1124) and decode_block_out_buf_idx & "011011") or
(repeat(9, sig_1122) and decode_block_out_buf_idx & "000011") or
(repeat(9, sig_1120) and decode_block_out_buf_idx & "100011") or
(repeat(9, sig_1116) and decode_block_out_buf_idx & "001101") or
(repeat(9, sig_1114) and decode_block_out_buf_idx & "101101") or
(repeat(9, sig_1108) and decode_block_out_buf_idx & "110011") or
(repeat(9, sig_1107) and decode_block_out_buf_idx & "010011") or
(repeat(9, sig_1104) and decode_block_out_buf_idx & "110100") or
(repeat(9, sig_1102) and decode_block_out_buf_idx & "110000") or
(repeat(9, sig_1096) and decode_block_out_buf_idx & "101111") or
(repeat(9, sig_1095) and decode_block_out_buf_idx & "110001") or
(repeat(9, sig_1088) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "000");
-- Behaviour of component 'mux_565' model 'mux'
mux_565 <=
(repeat(9, sig_1088) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "001") or
(repeat(9, sig_1299) and yuvtorgb_vidx & yuvtorgb_i(5 downto 0));
-- Behaviour of component 'mux_561' model 'mux'
mux_561 <=
(repeat(32, sig_1556) and sig_1610(24 downto 0) & sig_1642(6 downto 0)) or
(repeat(32, sig_1400) and mux_817) or
(repeat(32, sig_1399) and mux_819) or
(repeat(32, sig_1395) and sig_1609(31 downto 0)) or
(repeat(32, sig_1392) and sig_1614(31 downto 0)) or
(repeat(32, sig_1390) and mux_821) or
(repeat(32, sig_1416) and mux_807) or
(repeat(32, sig_1387) and mux_823) or
(repeat(32, sig_1386) and mux_825) or
(repeat(32, sig_1385) and mux_827) or
(repeat(32, sig_1383) and mux_829) or
(repeat(32, sig_1380) and mux_831) or
(repeat(32, sig_1379) and mux_833) or
(repeat(32, sig_1378) and mux_835) or
(repeat(32, sig_1374) and mux_837) or
(repeat(32, sig_1419) and mux_805) or
(repeat(32, sig_1513) and mux_797) or
(repeat(32, sig_1516) and mux_795) or
(repeat(32, sig_1409) and mux_809) or
(repeat(32, sig_1406) and mux_811) or
(repeat(32, sig_1404) and mux_813) or
(repeat(32, sig_1402) and mux_815) or
(repeat(32, sig_1451) and sig_992) or
(repeat(32, sig_1475) and mux_776) or
(repeat(32, sig_1373) and mux_839) or
(repeat(32, sig_1369) and mux_841) or
(repeat(32, sig_1364) and mux_843) or
(repeat(32, sig_1329) and mux_856) or
(repeat(32, sig_1327) and mux_858) or
(repeat(32, sig_1263) and sig_1610(31 downto 0)) or
(repeat(32, sig_1176) and mux_888) or
(repeat(32, sig_1175) and mux_890) or
(repeat(32, sig_1173) and mux_892) or
(repeat(32, sig_1172) and mux_894) or
(repeat(32, sig_1160) and mux_898) or
(repeat(32, sig_1158) and mux_900) or
(repeat(32, sig_1154) and mux_902) or
(repeat(32, sig_1152) and mux_904) or
(repeat(32, sig_1150) and mux_906) or
(repeat(32, sig_1149) and mux_908) or
(repeat(32, sig_1148) and mux_910) or
(repeat(32, sig_1147) and mux_912) or
(repeat(32, sig_1145) and mux_914) or
(repeat(32, sig_1143) and mux_916) or
(repeat(32, sig_1142) and mux_918) or
(repeat(32, sig_1140) and mux_920) or
(repeat(32, sig_1139) and mux_922) or
(repeat(32, sig_1138) and mux_924) or
(repeat(32, sig_1136) and mux_926) or
(repeat(32, sig_1135) and mux_928) or
(repeat(32, sig_1133) and mux_930) or
(repeat(32, sig_1131) and mux_932) or
(repeat(32, sig_1129) and mux_934) or
(repeat(32, sig_1128) and mux_936) or
(repeat(32, sig_1127) and mux_938) or
(repeat(32, sig_1125) and mux_940) or
(repeat(32, sig_1123) and mux_942) or
(repeat(32, sig_1121) and mux_944) or
(repeat(32, sig_1119) and mux_946) or
(repeat(32, sig_1117) and mux_948) or
(repeat(32, sig_1115) and mux_950) or
(repeat(32, sig_1113) and mux_952) or
(repeat(32, sig_1109) and mux_954) or
(repeat(32, sig_1106) and mux_956) or
(repeat(32, sig_1105) and mux_958) or
(repeat(32, sig_1103) and mux_960) or
(repeat(32, sig_1031) and mux_980) or
(repeat(32, sig_1003) and mux_986) or
(repeat(32, sig_1002) and mux_988);
-- Behaviour of component 'mux_562' model 'mux'
mux_562 <=
(repeat(9, sig_1555) and decode_block_out_buf_idx & "011000") or
(repeat(9, sig_1407) and decode_block_out_buf_idx & "101010") or
(repeat(9, sig_1405) and decode_block_out_buf_idx & "010100") or
(repeat(9, sig_1403) and decode_block_out_buf_idx & "110101") or
(repeat(9, sig_1401) and decode_block_out_buf_idx & "111000") or
(repeat(9, sig_1391) and decode_block_out_buf_idx & chenidct_aidx(5 downto 0)) or
(repeat(9, sig_1510) and decode_block_out_buf_idx & "101000") or
(repeat(9, sig_1389) and decode_block_out_buf_idx & "011001") or
(repeat(9, sig_1388) and decode_block_out_buf_idx & "100110") or
(repeat(9, sig_1384) and decode_block_out_buf_idx & "111010") or
(repeat(9, sig_1382) and decode_block_out_buf_idx & "111011") or
(repeat(9, sig_1381) and decode_block_out_buf_idx & "111100") or
(repeat(9, sig_1377) and decode_block_out_buf_idx & "000100") or
(repeat(9, sig_1375) and decode_block_out_buf_idx & "100100") or
(repeat(9, sig_1372) and decode_block_out_buf_idx & "010010") or
(repeat(9, sig_1512) and decode_block_out_buf_idx & "000001") or
(repeat(9, sig_1515) and decode_block_out_buf_idx & "011110") or
(repeat(9, sig_1517) and decode_block_out_buf_idx & "011100") or
(repeat(9, sig_1418) and decode_block_out_buf_idx & "111101") or
(repeat(9, sig_1417) and decode_block_out_buf_idx & "100010") or
(repeat(9, sig_1415) and decode_block_out_buf_idx & "010111") or
(repeat(9, sig_1408) and decode_block_out_buf_idx & "001010") or
(repeat(9, sig_1450) and decode_block_out_buf_idx & chenidct_i(5 downto 0)) or
(repeat(9, sig_1469) and decode_block_out_buf_idx & "010000") or
(repeat(9, sig_1370) and decode_block_out_buf_idx & "000111") or
(repeat(9, sig_1368) and decode_block_out_buf_idx & "001100") or
(repeat(9, sig_1366) and decode_block_out_buf_idx & "111111") or
(repeat(9, sig_1365) and decode_block_out_buf_idx & "101100") or
(repeat(9, sig_1362) and decode_block_out_buf_idx & "110010") or
(repeat(9, sig_1331) and decode_block_out_buf_idx & "000101") or
(repeat(9, sig_1330) and decode_block_out_buf_idx & "010001") or
(repeat(9, sig_1328) and decode_block_out_buf_idx & "001111") or
(repeat(9, sig_1326) and decode_block_out_buf_idx & "100111") or
(repeat(9, sig_1281) and decode_block_out_buf_idx & "011101") or
(repeat(9, sig_1279) and decode_block_out_buf_idx & "101110") or
(repeat(9, sig_1278) and decode_block_out_buf_idx & "110110") or
(repeat(9, sig_1265) and decode_block_out_buf_idx & "001110") or
(repeat(9, sig_1261) and decode_block_out_buf_idx & "001001") or
(repeat(9, sig_1238) and decode_block_out_buf_idx & "010110") or
(repeat(9, sig_1232) and decode_block_out_buf_idx & "001011") or
(repeat(9, sig_1177) and decode_block_out_buf_idx & "111110") or
(repeat(9, sig_1174) and decode_block_out_buf_idx & "100001") or
(repeat(9, sig_1171) and decode_block_out_buf_idx & "011111") or
(repeat(9, sig_1159) and decode_block_out_buf_idx & "000000") or
(repeat(9, sig_1157) and decode_block_out_buf_idx & "100000") or
(repeat(9, sig_1153) and decode_block_out_buf_idx & "000010") or
(repeat(9, sig_1151) and decode_block_out_buf_idx & "010101") or
(repeat(9, sig_1146) and decode_block_out_buf_idx & "101001") or
(repeat(9, sig_1144) and decode_block_out_buf_idx & "110111") or
(repeat(9, sig_1141) and decode_block_out_buf_idx & "001000") or
(repeat(9, sig_1137) and decode_block_out_buf_idx & "101011") or
(repeat(9, sig_1134) and decode_block_out_buf_idx & "111001") or
(repeat(9, sig_1132) and decode_block_out_buf_idx & "000110") or
(repeat(9, sig_1130) and decode_block_out_buf_idx & "011010") or
(repeat(9, sig_1126) and decode_block_out_buf_idx & "100101") or
(repeat(9, sig_1124) and decode_block_out_buf_idx & "011011") or
(repeat(9, sig_1122) and decode_block_out_buf_idx & "000011") or
(repeat(9, sig_1120) and decode_block_out_buf_idx & "100011") or
(repeat(9, sig_1116) and decode_block_out_buf_idx & "001101") or
(repeat(9, sig_1114) and decode_block_out_buf_idx & "101101") or
(repeat(9, sig_1108) and decode_block_out_buf_idx & "110011") or
(repeat(9, sig_1107) and decode_block_out_buf_idx & "010011") or
(repeat(9, sig_1104) and decode_block_out_buf_idx & "110100") or
(repeat(9, sig_1102) and decode_block_out_buf_idx & "110000") or
(repeat(9, sig_1096) and decode_block_out_buf_idx & "101111") or
(repeat(9, sig_1095) and decode_block_out_buf_idx & "110001") or
(repeat(9, sig_1087) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "000") or
(repeat(9, sig_1083) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "001");
-- Behaviour of component 'mux_557' model 'mux'
mux_557 <=
(repeat(32, sig_1436) and sig_1643) or
(repeat(32, sig_1433) and sig_1628(31 downto 0));
-- Behaviour of component 'mux_558' model 'mux'
mux_558 <=
(repeat(6, sig_1564) and "000101") or
(repeat(6, sig_1321) and "110001") or
(repeat(6, sig_1320) and "000110") or
(repeat(6, sig_1315) and "010101") or
(repeat(6, sig_1311) and "011111") or
(repeat(6, sig_1301) and "100101") or
(repeat(6, sig_1367) and "111010") or
(repeat(6, sig_1293) and "100111") or
(repeat(6, sig_1277) and "000010") or
(repeat(6, sig_1276) and "111001") or
(repeat(6, sig_1275) and "010001") or
(repeat(6, sig_1270) and "110000") or
(repeat(6, sig_1260) and "101001") or
(repeat(6, sig_1259) and "111100") or
(repeat(6, sig_1258) and "011000") or
(repeat(6, sig_1371) and "110111") or
(repeat(6, sig_1410) and "011001") or
(repeat(6, sig_1508) and "001101") or
(repeat(6, sig_1361) and "101100") or
(repeat(6, sig_1359) and "001000") or
(repeat(6, sig_1358) and "101011") or
(repeat(6, sig_1436) and izigzagmatrix_out_idx(5 downto 0)) or
(repeat(6, sig_1432) and "010010") or
(repeat(6, sig_1256) and "010110") or
(repeat(6, sig_1255) and "000011") or
(repeat(6, sig_1246) and "100011") or
(repeat(6, sig_1239) and "100001") or
(repeat(6, sig_1235) and "100100") or
(repeat(6, sig_1231) and "100110") or
(repeat(6, sig_1230) and "100000") or
(repeat(6, sig_1228) and "110101") or
(repeat(6, sig_1227) and "101101") or
(repeat(6, sig_1226) and "011110") or
(repeat(6, sig_1225) and "000100") or
(repeat(6, sig_1223) and "000111") or
(repeat(6, sig_1222) and "110110") or
(repeat(6, sig_1221) and "011101") or
(repeat(6, sig_1220) and "101110") or
(repeat(6, sig_1166) and "001110") or
(repeat(6, sig_1164) and "110100") or
(repeat(6, sig_1156) and "010100") or
(repeat(6, sig_1155) and "101010") or
(repeat(6, sig_1099) and "011010") or
(repeat(6, sig_1098) and "101111") or
(repeat(6, sig_1097) and "010011") or
(repeat(6, sig_1094) and "010111") or
(repeat(6, sig_1093) and "111000") or
(repeat(6, sig_1092) and "011100") or
(repeat(6, sig_1091) and "000001") or
(repeat(6, sig_1090) and "001001") or
(repeat(6, sig_1086) and "001011") or
(repeat(6, sig_1085) and "110010") or
(repeat(6, sig_1084) and "010000") or
(repeat(6, sig_1079) and "001111") or
(repeat(6, sig_1076) and "001010") or
(repeat(6, sig_1075) and "110011") or
(repeat(6, sig_1074) and "111111") or
(repeat(6, sig_1071) and "011011") or
(repeat(6, sig_1063) and "001100") or
(repeat(6, sig_1054) and "101000") or
(repeat(6, sig_1050) and "100010") or
(repeat(6, sig_1028) and "111101") or
(repeat(6, sig_1022) and "111110") or
(repeat(6, sig_1007) and "111011");
-- Behaviour of component 'mux_559' model 'mux'
mux_559 <=
(repeat(6, sig_1581) and chenidct_i(5 downto 0)) or
(repeat(6, sig_1358) and "101011") or
(repeat(6, sig_1321) and "110001") or
(repeat(6, sig_1320) and "000110") or
(repeat(6, sig_1315) and "010101") or
(repeat(6, sig_1311) and "011111") or
(repeat(6, sig_1371) and "110111") or
(repeat(6, sig_1301) and "100101") or
(repeat(6, sig_1293) and "100111") or
(repeat(6, sig_1277) and "000010") or
(repeat(6, sig_1276) and "111001") or
(repeat(6, sig_1275) and "010001") or
(repeat(6, sig_1270) and "110000") or
(repeat(6, sig_1260) and "101001") or
(repeat(6, sig_1259) and "111100") or
(repeat(6, sig_1410) and "011001") or
(repeat(6, sig_1508) and "001101") or
(repeat(6, sig_1564) and "000101") or
(repeat(6, sig_1367) and "111010") or
(repeat(6, sig_1361) and "101100") or
(repeat(6, sig_1359) and "001000") or
(repeat(6, sig_1473) and chenidct_aidx(5 downto 0)) or
(repeat(6, sig_1432) and "010010") or
(repeat(6, sig_1258) and "011000") or
(repeat(6, sig_1256) and "010110") or
(repeat(6, sig_1255) and "000011") or
(repeat(6, sig_1246) and "100011") or
(repeat(6, sig_1239) and "100001") or
(repeat(6, sig_1235) and "100100") or
(repeat(6, sig_1231) and "100110") or
(repeat(6, sig_1230) and "100000") or
(repeat(6, sig_1228) and "110101") or
(repeat(6, sig_1227) and "101101") or
(repeat(6, sig_1226) and "011110") or
(repeat(6, sig_1225) and "000100") or
(repeat(6, sig_1223) and "000111") or
(repeat(6, sig_1222) and "110110") or
(repeat(6, sig_1221) and "011101") or
(repeat(6, sig_1220) and "101110") or
(repeat(6, sig_1166) and "001110") or
(repeat(6, sig_1164) and "110100") or
(repeat(6, sig_1156) and "010100") or
(repeat(6, sig_1155) and "101010") or
(repeat(6, sig_1099) and "011010") or
(repeat(6, sig_1098) and "101111") or
(repeat(6, sig_1097) and "010011") or
(repeat(6, sig_1094) and "010111") or
(repeat(6, sig_1093) and "111000") or
(repeat(6, sig_1092) and "011100") or
(repeat(6, sig_1091) and "000001") or
(repeat(6, sig_1090) and "001001") or
(repeat(6, sig_1086) and "001011") or
(repeat(6, sig_1085) and "110010") or
(repeat(6, sig_1084) and "010000") or
(repeat(6, sig_1079) and "001111") or
(repeat(6, sig_1076) and "001010") or
(repeat(6, sig_1075) and "110011") or
(repeat(6, sig_1074) and "111111") or
(repeat(6, sig_1071) and "011011") or
(repeat(6, sig_1063) and "001100") or
(repeat(6, sig_1054) and "101000") or
(repeat(6, sig_1050) and "100010") or
(repeat(6, sig_1028) and "111101") or
(repeat(6, sig_1022) and "111110") or
(repeat(6, sig_1007) and "111011");
-- Behaviour of component 'mux_555' model 'mux'
mux_555 <=
(repeat(32, sig_1396) and sig_1613) or
(repeat(32, sig_1449) and sig_1612(31 downto 0));
-- Behaviour of component 'mux_551' model 'mux'
mux_551 <=
(repeat(32, sig_1118) and sig_1587(39 downto 8)) or
(repeat(32, sig_1088) and sig_1640) or
(repeat(32, sig_1332) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_553' model 'mux'
mux_553 <=
(repeat(32, sig_1411) and sig_1610(31 downto 0)) or
(repeat(32, sig_1111) and sig_1609(28 downto 0) & chenidct_aidx(2 downto 0)) or
(repeat(32, sig_1262) and sig_1609(31 downto 0)) or
(repeat(32, sig_1582) and sig_1610(28 downto 0) & chenidct_i(2 downto 0)) or
(repeat(32, sig_1477) and sig_1610(28 downto 0) & chenidct_aidx(2 downto 0));
-- Behaviour of component 'mux_549' model 'mux'
mux_549 <=
(repeat(32, sig_1323) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1274) and sig_1642) or
(repeat(32, sig_1324) and sig_1587(39 downto 8)) or
(repeat(32, sig_1463) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_545' model 'mux'
mux_545 <=
(repeat(32, sig_1118) and sig_1612(38 downto 7)) or
(repeat(32, sig_1040) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1351) and sig_1642) or
(repeat(32, sig_1463) and sig_1613);
-- Behaviour of component 'mux_547' model 'mux'
mux_547 <=
(repeat(32, sig_1349) and sig_1614(40 downto 9)) or
(repeat(32, sig_1001) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1413) and sig_1642) or
(repeat(32, sig_1463) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_543' model 'mux'
mux_543 <=
(repeat(32, sig_1088) and sig_1642) or
(repeat(32, sig_1581) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_731' model 'mux'
mux_731 <=
(repeat(8, sig_1508) and iquantize_qidx & "001101") or
(repeat(8, sig_1320) and iquantize_qidx & "000110") or
(repeat(8, sig_1315) and iquantize_qidx & "010101") or
(repeat(8, sig_1311) and iquantize_qidx & "011111") or
(repeat(8, sig_1301) and iquantize_qidx & "100101") or
(repeat(8, sig_1293) and iquantize_qidx & "100111") or
(repeat(8, sig_1361) and iquantize_qidx & "101100") or
(repeat(8, sig_1277) and iquantize_qidx & "000010") or
(repeat(8, sig_1276) and iquantize_qidx & "111001") or
(repeat(8, sig_1275) and iquantize_qidx & "010001") or
(repeat(8, sig_1270) and iquantize_qidx & "110000") or
(repeat(8, sig_1260) and iquantize_qidx & "101001") or
(repeat(8, sig_1259) and iquantize_qidx & "111100") or
(repeat(8, sig_1258) and iquantize_qidx & "011000") or
(repeat(8, sig_1256) and iquantize_qidx & "010110") or
(repeat(8, sig_1367) and iquantize_qidx & "111010") or
(repeat(8, sig_1371) and iquantize_qidx & "110111") or
(repeat(8, sig_1410) and iquantize_qidx & "011001") or
(repeat(8, sig_1360) and iquantize_qidx & "000000") or
(repeat(8, sig_1359) and iquantize_qidx & "001000") or
(repeat(8, sig_1358) and iquantize_qidx & "101011") or
(repeat(8, sig_1321) and iquantize_qidx & "110001") or
(repeat(8, sig_1564) and iquantize_qidx & "000101") or
(repeat(8, sig_1432) and iquantize_qidx & "010010") or
(repeat(8, sig_1255) and iquantize_qidx & "000011") or
(repeat(8, sig_1246) and iquantize_qidx & "100011") or
(repeat(8, sig_1239) and iquantize_qidx & "100001") or
(repeat(8, sig_1235) and iquantize_qidx & "100100") or
(repeat(8, sig_1231) and iquantize_qidx & "100110") or
(repeat(8, sig_1230) and iquantize_qidx & "100000") or
(repeat(8, sig_1228) and iquantize_qidx & "110101") or
(repeat(8, sig_1227) and iquantize_qidx & "101101") or
(repeat(8, sig_1226) and iquantize_qidx & "011110") or
(repeat(8, sig_1225) and iquantize_qidx & "000100") or
(repeat(8, sig_1223) and iquantize_qidx & "000111") or
(repeat(8, sig_1222) and iquantize_qidx & "110110") or
(repeat(8, sig_1221) and iquantize_qidx & "011101") or
(repeat(8, sig_1220) and iquantize_qidx & "101110") or
(repeat(8, sig_1166) and iquantize_qidx & "001110") or
(repeat(8, sig_1164) and iquantize_qidx & "110100") or
(repeat(8, sig_1156) and iquantize_qidx & "010100") or
(repeat(8, sig_1155) and iquantize_qidx & "101010") or
(repeat(8, sig_1099) and iquantize_qidx & "011010") or
(repeat(8, sig_1098) and iquantize_qidx & "101111") or
(repeat(8, sig_1097) and iquantize_qidx & "010011") or
(repeat(8, sig_1094) and iquantize_qidx & "010111") or
(repeat(8, sig_1093) and iquantize_qidx & "111000") or
(repeat(8, sig_1092) and iquantize_qidx & "011100") or
(repeat(8, sig_1091) and iquantize_qidx & "000001") or
(repeat(8, sig_1090) and iquantize_qidx & "001001") or
(repeat(8, sig_1086) and iquantize_qidx & "001011") or
(repeat(8, sig_1085) and iquantize_qidx & "110010") or
(repeat(8, sig_1084) and iquantize_qidx & "010000") or
(repeat(8, sig_1079) and iquantize_qidx & "001111") or
(repeat(8, sig_1076) and iquantize_qidx & "001010") or
(repeat(8, sig_1075) and iquantize_qidx & "110011") or
(repeat(8, sig_1074) and iquantize_qidx & "111111") or
(repeat(8, sig_1071) and iquantize_qidx & "011011") or
(repeat(8, sig_1063) and iquantize_qidx & "001100") or
(repeat(8, sig_1054) and iquantize_qidx & "101000") or
(repeat(8, sig_1050) and iquantize_qidx & "100010") or
(repeat(8, sig_1028) and iquantize_qidx & "111101") or
(repeat(8, sig_1022) and iquantize_qidx & "111110") or
(repeat(8, sig_1007) and iquantize_qidx & "111011");
-- Behaviour of component 'mux_727' model 'mux'
mux_727 <=
(repeat(7, sig_1534) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_i_c0(5 downto 0)) or
(repeat(7, sig_1552) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0)) or
(repeat(7, sig_1458) and get_dht_index & get_dht_i(5 downto 0));
-- Behaviour of component 'mux_723' model 'mux'
mux_723 <=
(repeat(10, sig_1304) and decodehuffman_dc_tbl_no & decodehuffman_dc_p) or
(repeat(10, sig_1480) and get_dht_index & get_dht_i(8 downto 0));
-- Behaviour of component 'mux_719' model 'mux'
mux_719 <=
(repeat(7, sig_1505) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_i_c0(5 downto 0)) or
(repeat(7, sig_1547) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0)) or
(repeat(7, sig_1458) and get_dht_index & get_dht_i(5 downto 0));
-- Behaviour of component 'mux_539' model 'mux'
mux_539 <=
(repeat(32, sig_1118) and sig_1624(31 downto 0)) or
(repeat(32, sig_1354) and sig_1642) or
(repeat(32, sig_1472) and sig_1639(29 downto 0) & "00");
-- Behaviour of component 'mux_541' model 'mux'
mux_541 <=
(repeat(32, sig_999) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1118) and sig_1613) or
(repeat(32, sig_1357) and sig_1642);
-- Behaviour of component 'mux_537' model 'mux'
mux_537 <=
(repeat(32, sig_1285) and sig_1642) or
(repeat(32, sig_1325) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1621(31 downto 0));
-- Behaviour of component 'mux_533' model 'mux'
mux_533 <=
(repeat(32, sig_1324) and sig_1614(40 downto 9)) or
(repeat(32, sig_1395) and sig_1627(39 downto 8));
-- Behaviour of component 'mux_535' model 'mux'
mux_535 <=
(repeat(32, sig_1118) and sig_1614(40 downto 9)) or
(repeat(32, sig_1463) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_715' model 'mux'
mux_715 <=
(repeat(10, sig_1284) and decodehuffman_ac_tbl_no & decodehuffman_ac_p) or
(repeat(10, sig_1480) and get_dht_index & get_dht_i(8 downto 0));
-- Behaviour of component 'mux_711' model 'mux'
mux_711 <=
(sig_1170 and decodehuffmcu_tbl_no) or
(sig_1189 and '1');
-- Behaviour of component 'mux_705' model 'mux'
mux_705 <=
(repeat(32, sig_1271) and sig_1632) or
(repeat(32, sig_1554) and "11111111111111111111111111111111") or
(repeat(32, sig_1561) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_706' model 'mux'
mux_706 <=
(repeat(7, sig_1553) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0)) or
(repeat(7, sig_1561) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_p_dhtbl_ml(5 downto 0));
-- Behaviour of component 'mux_707' model 'mux'
mux_707 <=
(repeat(7, sig_1561) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_p_dhtbl_ml(5 downto 0)) or
(repeat(7, sig_1575) and decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0)) or
(repeat(7, sig_1577) and decodehuffman_dc_tbl_no & decodehuffman_dc_dhuff_ml);
-- Behaviour of component 'mux_531' model 'mux'
mux_531 <=
(repeat(32, sig_1324) and sig_1609(38 downto 7)) or
(repeat(32, sig_1395) and sig_1628(39 downto 8));
-- Behaviour of component 'mux_529' model 'mux'
mux_529 <=
(repeat(32, sig_1118) and sig_1610(38 downto 7)) or
(repeat(32, sig_1463) and sig_1613);
-- Behaviour of component 'mux_695' model 'mux'
mux_695 <=
(sig_1184 and '1') or
(sig_1453 and decodehuffmcu_tbl_no);
-- Behaviour of component 'mux_524' model 'mux'
mux_524 <=
(repeat(5, sig_1310) and decodehuffmcu_s(4 downto 0)) or
(repeat(5, sig_1482) and read_position(4 downto 0));
-- Behaviour of component 'mux_521' model 'mux'
mux_521 <=
(repeat(32, sig_1422) and "000000000000000000000000" & pgetc) or
(repeat(32, sig_1493) and or_802 & pgetc);
-- Behaviour of component 'mux_519' model 'mux'
mux_519 <=
(repeat(32, sig_1484) and sig_1614(31 downto 0)) or
(repeat(32, sig_1355) and sig_1624(31 downto 0)) or
(repeat(32, sig_1421) and "00000000000000000000000000000111") or
(repeat(32, sig_1493) and sig_1610(28 downto 0) & read_position(2 downto 0)) or
(repeat(32, sig_1497) and "11111111111111111111111111111111");
-- Behaviour of component 'mux_517' model 'mux'
mux_517 <=
(repeat(8, sig_1423) and "11111111") or
(repeat(8, sig_1425) and pgetc_temp);
-- Behaviour of component 'mux_507' model 'mux'
mux_507 <=
(repeat(32, sig_1008) and and_984) or
(repeat(32, sig_1345) and and_853) or
(repeat(32, sig_1497) and and_801);
-- Behaviour of component 'mux_505' model 'mux'
mux_505 <=
(repeat(32, sig_1167) and sig_1614(31 downto 0)) or
(repeat(32, sig_1197) and decodehuffmcu_s) or
(repeat(32, sig_1201) and decodehuffman_dc);
-- Behaviour of component 'mux_501' model 'mux'
mux_501 <=
(repeat(32, sig_1355) and or_845) or
(repeat(32, sig_1489) and sig_1626);
-- Behaviour of component 'mux_492' model 'mux'
mux_492 <=
(repeat(32, sig_1186) and sig_1652) or
(repeat(32, sig_1514) and "00000000000000000000000000000001") or
(repeat(32, sig_1544) and huff_make_dhuff_tb_ac_l);
-- Behaviour of component 'mux_488' model 'mux'
mux_488 <=
(repeat(32, sig_1499) and sig_1609(31 downto 0)) or
(repeat(32, sig_1504) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_490' model 'mux'
mux_490 <=
(repeat(32, sig_1498) and "00000000000000000000000000000001") or
(repeat(32, sig_1507) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_486' model 'mux'
mux_486 <=
(repeat(32, sig_1500) and sig_1610(31 downto 0)) or
(repeat(32, sig_1544) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_482' model 'mux'
mux_482 <=
(repeat(32, sig_1283) and sig_1610(31 downto 0)) or
(repeat(32, sig_1558) and sig_1635);
-- Behaviour of component 'mux_484' model 'mux'
mux_484 <=
(repeat(32, sig_1023) and sig_1609(31 downto 0)) or
(repeat(32, sig_1283) and huff_make_dhuff_tb_ac_code(30 downto 0) & '0');
-- Behaviour of component 'mux_480' model 'mux'
mux_480 <=
(repeat(32, sig_1514) and "00000000000000000000000000000001") or
(repeat(32, sig_1525) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_476' model 'mux'
mux_476 <=
(repeat(32, sig_1499) and huff_make_dhuff_tb_ac_i_c0);
-- Behaviour of component 'mux_478' model 'mux'
mux_478 <=
(repeat(9, sig_1511) and huff_make_dhuff_tb_ac_p(8 downto 0));
-- Behaviour of component 'mux_459' model 'mux'
mux_459 <=
(repeat(32, sig_1038) and huff_make_dhuff_tb_dc_l) or
(repeat(32, sig_1305) and sig_1656) or
(repeat(32, sig_1542) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_455' model 'mux'
mux_455 <=
(repeat(32, sig_1527) and sig_1609(31 downto 0)) or
(repeat(32, sig_1533) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_457' model 'mux'
mux_457 <=
(repeat(32, sig_1526) and "00000000000000000000000000000001") or
(repeat(32, sig_1536) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_453' model 'mux'
mux_453 <=
(repeat(32, sig_1038) and sig_1609(31 downto 0)) or
(repeat(32, sig_1528) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_449' model 'mux'
mux_449 <=
(repeat(32, sig_1033) and sig_1633) or
(repeat(32, sig_1068) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_451' model 'mux'
mux_451 <=
(repeat(32, sig_1035) and sig_1609(31 downto 0)) or
(repeat(32, sig_1068) and huff_make_dhuff_tb_dc_code(30 downto 0) & '0');
-- Behaviour of component 'mux_447' model 'mux'
mux_447 <=
(repeat(32, sig_1542) and "00000000000000000000000000000001") or
(repeat(32, sig_1563) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_443' model 'mux'
mux_443 <=
(repeat(32, sig_1527) and huff_make_dhuff_tb_dc_i_c0);
-- Behaviour of component 'mux_445' model 'mux'
mux_445 <=
(repeat(9, sig_1537) and huff_make_dhuff_tb_dc_p(8 downto 0));
-- Behaviour of component 'mux_430' model 'mux'
mux_430 <=
(repeat(32, sig_1284) and sig_1657);
-- Behaviour of component 'mux_422' model 'mux'
mux_422 <=
(repeat(32, sig_1565) and "00000000000000000000000000000001") or
(repeat(32, sig_1567) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_424' model 'mux'
mux_424 <=
(repeat(32, sig_1565) and "0000000000000000000000000000000" & buf_getb) or
(repeat(32, sig_1567) and sig_1610(30 downto 0) & buf_getb);
-- Behaviour of component 'mux_416' model 'mux'
mux_416 <=
(repeat(32, sig_1304) and sig_1659);
-- Behaviour of component 'mux_410' model 'mux'
mux_410 <=
(repeat(32, sig_1571) and "0000000000000000000000000000000" & buf_getb) or
(repeat(32, sig_1574) and sig_1610(30 downto 0) & buf_getb);
-- Behaviour of component 'mux_408' model 'mux'
mux_408 <=
(repeat(32, sig_1571) and "00000000000000000000000000000001") or
(repeat(32, sig_1574) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_398' model 'mux'
mux_398 <=
(repeat(32, sig_1026) and sig_1610(31 downto 0)) or
(repeat(32, sig_1341) and buf_getv) or
(repeat(32, sig_1344) and or_854);
-- Behaviour of component 'mux_400' model 'mux'
mux_400 <=
(repeat(32, sig_1030) and and_982) or
(repeat(32, sig_1342) and sig_1614(31 downto 0)) or
(repeat(32, sig_1579) and decodehuffman_dc);
-- Behaviour of component 'mux_392' model 'mux'
mux_392 <=
(repeat(32, sig_1454) and "00000000000000000000000000000001") or
(repeat(32, sig_1466) and sig_1610(31 downto 0)) or
(repeat(32, sig_1464) and sig_1610(27 downto 0) & decodehuffmcu_k(3 downto 0));
-- Behaviour of component 'mux_394' model 'mux'
mux_394 <=
(repeat(32, sig_1443) and sig_1610(31 downto 0)) or
(repeat(32, sig_1445) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_378' model 'mux'
mux_378 <=
(repeat(8, sig_1070) and yuvtorgb_r(7 downto 0)) or
(repeat(8, sig_1234) and yuvtorgb_b(7 downto 0)) or
(repeat(8, sig_1237) and yuvtorgb_g(7 downto 0));
-- Behaviour of component 'mux_379' model 'mux'
mux_379 <=
(repeat(10, sig_1070) and yuvtorgb_p & "00" & yuvtorgb_i(5 downto 0)) or
(repeat(10, sig_1234) and yuvtorgb_p & "10" & yuvtorgb_i(5 downto 0)) or
(repeat(10, sig_1237) and yuvtorgb_p & "01" & yuvtorgb_i(5 downto 0));
-- Behaviour of component 'mux_375' model 'mux'
mux_375 <=
(repeat(2, sig_1020) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_373' model 'mux'
mux_373 <=
(repeat(2, sig_1005) and "10") or
(repeat(2, sig_1004) and "11") or
(repeat(2, sig_1019) and "01");
-- Behaviour of component 'mux_365' model 'mux'
mux_365 <=
(repeat(32, sig_1005) and sig_1614(31 downto 0)) or
(repeat(32, sig_1021) and sig_1610(28 downto 0) & write4blocks_hoffs(2 downto 0)) or
(repeat(32, sig_1196) and sig_1647(28 downto 0) & "000");
-- Behaviour of component 'mux_367' model 'mux'
mux_367 <=
(repeat(32, sig_1005) and sig_1610(28 downto 0) & write4blocks_voffs(2 downto 0)) or
(repeat(32, sig_1021) and write4blocks_voffs) or
(repeat(32, sig_1196) and sig_1648(28 downto 0) & "000");
-- Behaviour of component 'mux_363' model 'mux'
mux_363 <=
(repeat(32, sig_1018) and sig_1610(31 downto 0)) or
(repeat(32, sig_1065) and writeoneblock_voffs);
-- Behaviour of component 'mux_359' model 'mux'
mux_359 <=
(repeat(32, sig_1012) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_361' model 'mux'
mux_361 <=
(repeat(32, sig_1017) and sig_1610(31 downto 0)) or
(repeat(32, sig_1081) and writeoneblock_hoffs);
-- Behaviour of component 'mux_347' model 'mux'
mux_347 <=
(repeat(32, sig_1005) and sig_1610(28 downto 0) & write4blocks_voffs(2 downto 0)) or
(repeat(32, sig_1194) and sig_1648(28 downto 0) & "000");
-- Behaviour of component 'mux_345' model 'mux'
mux_345 <=
(repeat(32, sig_1005) and sig_1614(31 downto 0)) or
(repeat(32, sig_1021) and sig_1610(28 downto 0) & write4blocks_hoffs(2 downto 0)) or
(repeat(32, sig_1194) and sig_1647(28 downto 0) & "000");
-- Behaviour of component 'mux_341' model 'mux'
mux_341 <=
(repeat(3, sig_993) and decode_start_i(2 downto 0));
-- Behaviour of component 'mux_343' model 'mux'
mux_343 <=
(repeat(2, sig_993) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_339' model 'mux'
mux_339 <=
(repeat(3, sig_993) and "100") or
(repeat(3, sig_997) and "001");
-- Behaviour of component 'mux_335' model 'mux'
mux_335 <=
(repeat(32, sig_1060) and mux_965) or
(repeat(32, sig_1217) and sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24 downto 1));
-- Behaviour of component 'mux_337' model 'mux'
mux_337 <=
(repeat(3, sig_993) and "101") or
(repeat(3, sig_997) and "010");
-- Behaviour of component 'mux_333' model 'mux'
mux_333 <=
(repeat(32, sig_1060) and mux_969) or
(repeat(32, sig_1217) and sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24 downto 1));
-- Behaviour of component 'mux_331' model 'mux'
mux_331 <=
(repeat(32, sig_1060) and mux_967) or
(repeat(32, sig_1217) and sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24 downto 1));
-- Behaviour of component 'mux_323' model 'mux'
mux_323 <=
(repeat(6, sig_1345) and buf_getv_p(5 downto 0)) or
(repeat(6, sig_1355) and sig_1614(5 downto 0));
-- Behaviour of component 'mux_320' model 'mux'
mux_320 <=
(repeat(32, sig_1234) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_322' model 'mux'
mux_322 <=
(repeat(32, sig_1345) and current_read_byte) or
(repeat(32, sig_1355) and "000000000000000000000000" & pgetc);
-- Behaviour of component 'mux_317' model 'mux'
mux_317 <=
(repeat(2, sig_995) and "01") or
(repeat(2, sig_994) and "10") or
(repeat(2, sig_1045) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_314' model 'mux'
mux_314 <=
(repeat(32, sig_1324) and chenidct_a2) or
(repeat(32, sig_1118) and chenidct_a3) or
(repeat(32, sig_1217) and yuvtorgb_v(30) & yuvtorgb_v(30 downto 0)) or
(repeat(32, sig_1349) and chenidct_b3) or
(repeat(32, sig_1395) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_315' model 'mux'
mux_315 <=
(repeat(32, sig_1349) and "00000000000000000000000000110001") or
(repeat(32, sig_1101) and p_jinfo_mcuwidth) or
(repeat(32, sig_1118) and "00000000000000000000000000011001") or
(repeat(32, sig_1217) and "00000000000000000000000000001011") or
(repeat(32, sig_1324) and "00000000000000000000000011010101") or
(repeat(32, sig_1081) and writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12 downto 0)) or
(repeat(32, sig_1395) and "00000000000000000000000010110101") or
(repeat(32, sig_1433) and sig_1661);
-- Behaviour of component 'mux_316' model 'mux'
mux_316 <=
(repeat(32, sig_1349) and chenidct_b2) or
(repeat(32, sig_1101) and p_jinfo_mcuheight) or
(repeat(32, sig_1118) and chenidct_a0) or
(repeat(32, sig_1217) and yuvtorgb_u(28) & yuvtorgb_u(28) & yuvtorgb_u(28) & yuvtorgb_u(28 downto 0)) or
(repeat(32, sig_1324) and chenidct_a1) or
(repeat(32, sig_1081) and writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12 downto 0)) or
(repeat(32, sig_1395) and sig_1610(31 downto 0)) or
(repeat(32, sig_1433) and sig_1639);
-- Behaviour of component 'mux_313' model 'mux'
mux_313 <=
(repeat(9, sig_1324) and "001000111") or
(repeat(9, sig_1118) and "011111011") or
(repeat(9, sig_1217) and "001011011") or
(repeat(9, sig_1349) and "111011001") or
(repeat(9, sig_1395) and "010110101");
-- Behaviour of component 'mux_308' model 'mux'
mux_308 <=
(repeat(3, sig_994) and "101") or
(repeat(3, sig_995) and "100") or
(repeat(3, sig_1046) and decode_start_i(2 downto 0));
-- Behaviour of component 'mux_306' model 'mux'
mux_306 <=
(repeat(41, sig_1451) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1299) and "00000000000000000000000000000000010000000") or
(repeat(41, sig_1308) and "00000000000000000000000000000000000000001") or
(repeat(41, sig_1324) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(41, sig_1355) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1217) and sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30 downto 0) & '0') or
(repeat(41, sig_1161) and "00000000000000000000000000000000000000010") or
(repeat(41, sig_1118) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(41, sig_1470) and "00000000000000000000000000000000011111111") or
(repeat(41, sig_1463) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2);
-- Behaviour of component 'mux_307' model 'mux'
mux_307 <=
(repeat(41, sig_1355) and "00000000000000000000000000000000000000111") or
(repeat(41, sig_1217) and sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31 downto 0)) or
(repeat(41, sig_1299) and sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30 downto 0)) or
(repeat(41, sig_1309) and p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width) or
(repeat(41, sig_1324) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(41, sig_1216) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648) or
(repeat(41, sig_1118) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1468) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1463) and chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3);
-- Behaviour of component 'mux_302' model 'mux'
mux_302 <=
(repeat(41, sig_1216) and p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth) or
(repeat(41, sig_1470) and "00000000000000000000000000000000011111111") or
(repeat(41, sig_1463) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3);
-- Behaviour of component 'mux_303' model 'mux'
mux_303 <=
(repeat(41, sig_1216) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1471) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1463) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0);
-- Behaviour of component 'mux_294' model 'mux'
mux_294 <=
(repeat(2, sig_995) and "01") or
(repeat(2, sig_994) and "10") or
(repeat(2, sig_1045) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_290' model 'mux'
mux_290 <=
(repeat(41, sig_1395) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(41, sig_1376) and "00000000000000000000000000000000000000111") or
(repeat(41, sig_1363) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2) or
(repeat(41, sig_1355) and buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5 downto 0)) or
(repeat(41, sig_1349) and sig_1627) or
(repeat(41, sig_1534) and sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660) or
(repeat(41, sig_1324) and sig_1667(38 downto 0) & "00") or
(repeat(41, sig_1318) and "00000000000000000000000000000000000000010") or
(repeat(41, sig_1313) and get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count) or
(repeat(41, sig_1300) and "00000000000000000000000000000000000010001") or
(repeat(41, sig_1299) and "00000000000000000000000000000000010000000") or
(repeat(41, sig_1292) and sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654) or
(repeat(41, sig_1289) and sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650) or
(repeat(41, sig_1280) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(41, sig_1550) and "00000000000000000000000000000000000010000") or
(repeat(41, sig_1569) and sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651) or
(repeat(41, sig_1576) and sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655) or
(repeat(41, sig_1505) and sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658) or
(repeat(41, sig_1491) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1486) and "00000000000000000000000000000000000010111") or
(repeat(41, sig_1485) and "00000000000000000000000000000000000000001") or
(repeat(41, sig_1440) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(41, sig_1434) and "00000000000000000000000000000000000111111") or
(repeat(41, sig_1244) and "000000000000000000000000000000000" & p_jinfo_num_components) or
(repeat(41, sig_1241) and "000000000000000000000000000000000" & get_sos_num_comp) or
(repeat(41, sig_1240) and "00000000000000000000000000000000001000000") or
(repeat(41, sig_1229) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(41, sig_1217) and sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28 downto 0) & "000") or
(repeat(41, sig_1216) and p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth) or
(repeat(41, sig_1165) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1118) and sig_1627(39 downto 0) & '0') or
(repeat(41, sig_1089) and "00000000000000000000000000000000001000001") or
(repeat(41, sig_1077) and "00000000000000000000000000000000100000000") or
(repeat(41, sig_1049) and "00000000000000000000000000000000000000011") or
(repeat(41, sig_1048) and p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu) or
(repeat(41, sig_1032) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position) or
(repeat(41, sig_1015) and writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width) or
(repeat(41, sig_1014) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 0) & writeoneblock_hoffs(2 downto 0)) or
(repeat(41, sig_1010) and writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height) or
(repeat(41, sig_1009) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 0) & writeoneblock_voffs(2 downto 0));
-- Behaviour of component 'mux_291' model 'mux'
mux_291 <=
(repeat(41, sig_1468) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1505) and huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j) or
(repeat(41, sig_1502) and huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0) or
(repeat(41, sig_1492) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1487) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position) or
(repeat(41, sig_1420) and chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i) or
(repeat(41, sig_1569) and decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code) or
(repeat(41, sig_1395) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(41, sig_1393) and chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2) or
(repeat(41, sig_1363) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(41, sig_1355) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1349) and sig_1628(38 downto 0) & "00") or
(repeat(41, sig_1342) and decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s) or
(repeat(41, sig_1336) and get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i) or
(repeat(41, sig_1324) and sig_1666(39 downto 0) & '0') or
(repeat(41, sig_1576) and decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code) or
(repeat(41, sig_1446) and decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i) or
(repeat(41, sig_1455) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k) or
(repeat(41, sig_1551) and huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l) or
(repeat(41, sig_1534) and huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j) or
(repeat(41, sig_1531) and huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0) or
(repeat(41, sig_1518) and huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l) or
(repeat(41, sig_1463) and chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0) or
(repeat(41, sig_1435) and izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i) or
(repeat(41, sig_1322) and get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length) or
(repeat(41, sig_1319) and read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word) or
(repeat(41, sig_1314) and get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length) or
(repeat(41, sig_1309) and p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height) or
(repeat(41, sig_1303) and get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i) or
(repeat(41, sig_1299) and sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640) or
(repeat(41, sig_1291) and sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8 downto 0)) or
(repeat(41, sig_1287) and get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j) or
(repeat(41, sig_1280) and chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3) or
(repeat(41, sig_1245) and get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci) or
(repeat(41, sig_1241) and get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i) or
(repeat(41, sig_1229) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(41, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y & "00000000") or
(repeat(41, sig_1216) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(41, sig_1209) and get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci) or
(repeat(41, sig_1168) and buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n) or
(repeat(41, sig_1118) and sig_1628(37) & sig_1628(37 downto 0) & "00") or
(repeat(41, sig_1078) and huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1051) and decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i) or
(repeat(41, sig_1048) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu) or
(repeat(41, sig_1037) and huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p) or
(repeat(41, sig_1025) and yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i) or
(repeat(41, sig_1016) and writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e) or
(repeat(41, sig_1011) and writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i) or
(repeat(41, sig_1005) and write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs);
-- Behaviour of component 'mux_292' model 'mux'
mux_292 <=
(repeat(32, sig_1294) and sig_1613) or
(repeat(32, sig_1427) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_286' model 'mux'
mux_286 <=
(repeat(32, sig_1047) and sig_1610(31 downto 0)) or
(repeat(32, sig_1052) and sig_1610(29 downto 0) & decode_start_currentmcu(1 downto 0));
-- Behaviour of component 'mux_275' model 'mux'
mux_275 <=
(repeat(32, sig_1396) and chenidct_i) or
(repeat(32, sig_1118) and chenidct_a1) or
(repeat(32, sig_1217) and sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23 downto 0) & sig_1666(6)) or
(repeat(32, sig_1294) and decode_start_i) or
(repeat(32, sig_1309) and sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16 downto 3)) or
(repeat(32, sig_1451) and sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31 downto 4)) or
(repeat(32, sig_1463) and chenidct_c3);
-- Behaviour of component 'mux_272' model 'mux'
mux_272 <=
(repeat(39, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y) or
(repeat(39, sig_1118) and sig_1600(40 downto 2)) or
(repeat(39, sig_1309) and sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16 downto 0)) or
(repeat(39, sig_1449) and chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i);
-- Behaviour of component 'mux_274' model 'mux'
mux_274 <=
(repeat(32, sig_1397) and "00000000000000000000000000000001") or
(repeat(32, sig_1118) and chenidct_a2) or
(repeat(32, sig_1309) and "0000000000000000000000000000000" & and_864) or
(repeat(32, sig_1451) and "0000000000000000000000000000000" & and_789) or
(repeat(32, sig_1463) and chenidct_c2);
-- Behaviour of component 'mux_271' model 'mux'
mux_271 <=
(repeat(39, sig_1118) and sig_1668(38 downto 0)) or
(repeat(39, sig_1217) and sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31 downto 8)) or
(repeat(39, sig_1448) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_266' model 'mux'
mux_266 <=
(repeat(39, sig_1463) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(39, sig_1574) and decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30 downto 0)) or
(repeat(39, sig_1567) and decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30 downto 0)) or
(repeat(39, sig_1563) and huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l) or
(repeat(39, sig_1561) and sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655) or
(repeat(39, sig_1556) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31 downto 7)) or
(repeat(39, sig_1479) and get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i) or
(repeat(39, sig_1548) and huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p) or
(repeat(39, sig_1536) and huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0) or
(repeat(39, sig_1529) and huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p) or
(repeat(39, sig_1525) and huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l) or
(repeat(39, sig_1523) and sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651) or
(repeat(39, sig_1507) and huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0) or
(repeat(39, sig_1493) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31 downto 3)) or
(repeat(39, sig_1412) and "0000000" & chenidct_aidx) or
(repeat(39, sig_1477) and "0000000000" & chenidct_aidx(31 downto 3)) or
(repeat(39, sig_1466) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k) or
(repeat(39, sig_1464) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31 downto 4)) or
(repeat(39, sig_1451) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31 downto 3)) or
(repeat(39, sig_1443) and decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i) or
(repeat(39, sig_1441) and "0000000" & curhuffreadbuf_idx) or
(repeat(39, sig_1582) and "0000000000" & chenidct_i(31 downto 3)) or
(repeat(39, sig_1436) and izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i) or
(repeat(39, sig_1427) and decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i) or
(repeat(39, sig_1395) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(39, sig_1350) and "0000000" & chenidct_i(28 downto 0) & "001") or
(repeat(39, sig_1335) and get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num) or
(repeat(39, sig_1309) and sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16 downto 3)) or
(repeat(39, sig_1297) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(39, sig_1292) and sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653) or
(repeat(39, sig_1289) and sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649) or
(repeat(39, sig_1283) and huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size) or
(repeat(39, sig_1264) and chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2) or
(repeat(39, sig_1257) and sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643) or
(repeat(39, sig_1254) and get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci) or
(repeat(39, sig_1251) and get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i) or
(repeat(39, sig_1247) and "0000000" & readbuf_idx) or
(repeat(39, sig_1234) and yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i) or
(repeat(39, sig_1217) and sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31 downto 7)) or
(repeat(39, sig_1211) and get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci) or
(repeat(39, sig_1163) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31 downto 1)) or
(repeat(39, sig_1118) and sig_1666(39 downto 1)) or
(repeat(39, sig_1112) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(39, sig_1110) and chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3) or
(repeat(39, sig_1073) and "0000000000000000000000000000000000000" & sig_1663) or
(repeat(39, sig_1068) and huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size) or
(repeat(39, sig_1059) and "0000000" & jpeg2bmp_main_j) or
(repeat(39, sig_1056) and "0000000" & jpeg2bmp_main_i) or
(repeat(39, sig_1052) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31 downto 2)) or
(repeat(39, sig_1047) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu) or
(repeat(39, sig_1026) and decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff) or
(repeat(39, sig_1021) and write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31 downto 3)) or
(repeat(39, sig_1018) and writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i) or
(repeat(39, sig_1017) and writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e) or
(repeat(39, sig_1014) and writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31 downto 3)) or
(repeat(39, sig_1012) and writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff) or
(repeat(39, sig_1009) and writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31 downto 3)) or
(repeat(39, sig_1005) and write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31 downto 3));
-- Behaviour of component 'mux_265' model 'mux'
mux_265 <=
(repeat(39, sig_1112) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2) or
(repeat(39, sig_1110) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(39, sig_1027) and sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643) or
(repeat(39, sig_1012) and writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12 downto 0)) or
(repeat(39, sig_1006) and "00000000000" & decodehuffmcu_n) or
(repeat(39, sig_1309) and "00000000000000000000000000000000000000" & and_862) or
(repeat(39, sig_1395) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(39, sig_1546) and "111111111111111111111111111111111111111") or
(repeat(39, sig_1556) and "000000000000000000000000000000000000001") or
(repeat(39, sig_1292) and decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8 downto 0)) or
(repeat(39, sig_1289) and decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8 downto 0)) or
(repeat(39, sig_1264) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(39, sig_1118) and sig_1667(37) & sig_1667(37 downto 0)) or
(repeat(39, sig_1463) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(39, sig_1426) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_260' model 'mux'
mux_260 <=
(repeat(39, sig_1458) and "0000000000000000000000000000000" & read_byte) or
(repeat(39, sig_1324) and sig_1627(38 downto 0)) or
(repeat(39, sig_1395) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(39, sig_1544) and sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658) or
(repeat(39, sig_1451) and "00000000000000000000000000000000000000" & and_785) or
(repeat(39, sig_1217) and sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30 downto 7)) or
(repeat(39, sig_1118) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(39, sig_1038) and sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660) or
(repeat(39, sig_1463) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(39, sig_1438) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_261' model 'mux'
mux_261 <=
(repeat(39, sig_1458) and get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count) or
(repeat(39, sig_1324) and sig_1628(39 downto 1)) or
(repeat(39, sig_1309) and sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16 downto 0)) or
(repeat(39, sig_1297) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648) or
(repeat(39, sig_1262) and "0000000" & chenidct_aidx) or
(repeat(39, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y) or
(repeat(39, sig_1546) and sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31 downto 0)) or
(repeat(39, sig_1163) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31 downto 1)) or
(repeat(39, sig_1111) and "0000000000" & chenidct_aidx(31 downto 3)) or
(repeat(39, sig_1035) and huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code) or
(repeat(39, sig_1023) and huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code) or
(repeat(39, sig_1012) and "0000000" & writeoneblock_inidx) or
(repeat(39, sig_1567) and decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l) or
(repeat(39, sig_1574) and decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l) or
(repeat(39, sig_1451) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 1)) or
(repeat(39, sig_1527) and huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j) or
(repeat(39, sig_1499) and huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j) or
(repeat(39, sig_1398) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(39, sig_1335) and get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i) or
(repeat(39, sig_1463) and chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0) or
(repeat(39, sig_1436) and izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx);
-- Behaviour of component 'mux_262' model 'mux'
mux_262 <=
(repeat(32, sig_1056) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_257' model 'mux'
mux_257 <=
(repeat(32, sig_1059) and sig_1610(31 downto 0));
-- Behaviour of component 'nand_786' model 'nand'
nand_786 <= not (
sig_1605 and
sig_1606
);
-- Behaviour of component 'or_845' model 'or'
or_845 <=
sig_1629 or
buf_getv_rv;
-- Behaviour of component 'or_854' model 'or'
or_854 <=
sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638 or
buf_getv;
-- Behaviour of component 'or_866' model 'or'
or_866 <=
sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638 or
sig_1643;
-- Behaviour of component 'and_785' model 'and'
and_785 <=
nand_786 and
sig_1610(28);
-- Behaviour of component 'and_801' model 'and'
and_801 <=
sig_1636 and
current_read_byte;
-- Behaviour of component 'mux_761' model 'mux'
mux_761 <=
(repeat(9, sig_1118) and "000011001") or
(repeat(9, sig_1217) and "101100111") or
(repeat(9, sig_1324) and "001000111");
-- Behaviour of component 'mux_782' model 'mux'
mux_782 <=
(repeat(32, sig_1607) and sig_1660) or
(repeat(32, sig_1608) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'or_802' model 'or'
or_802 <=
current_read_byte(23 downto 0) or
"000000000000000000000000";
-- Behaviour of component 'and_803' model 'and'
and_803 <=
sig_1637 and
current_read_byte;
-- Behaviour of component 'mux_822' model 'mux'
mux_822 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_823' model 'mux'
mux_823 <=
(repeat(32, sig_1617) and mux_824);
-- Behaviour of component 'mux_776' model 'mux'
mux_776 <=
(repeat(32, sig_1617) and mux_777);
-- Behaviour of component 'mux_820' model 'mux'
mux_820 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_824' model 'mux'
mux_824 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_825' model 'mux'
mux_825 <=
(repeat(32, sig_1617) and mux_826);
-- Behaviour of component 'mux_760' model 'mux'
mux_760 <=
(repeat(32, sig_1118) and chenidct_a0) or
(repeat(32, sig_1217) and yuvtorgb_u(30) & yuvtorgb_u) or
(repeat(32, sig_1324) and chenidct_a2);
-- Behaviour of component 'and_789' model 'and'
and_789 <=
sig_1604 and
sig_1624(31);
-- Behaviour of component 'mux_759' model 'mux'
mux_759 <=
(repeat(6, sig_1118) and "111011") or
(repeat(6, sig_1217) and "100011") or
(repeat(6, sig_1324) and "010101");
-- Behaviour of component 'mux_768' model 'mux'
mux_768 <=
(repeat(32, sig_1436) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_757' model 'mux'
mux_757 <=
(repeat(8, sig_1057) and sig_1646) or
(repeat(8, sig_1062) and outdata_image_height);
-- Behaviour of component 'mux_773' model 'mux'
mux_773 <=
(repeat(8, sig_1179) and outdata_image_height) or
(repeat(8, sig_1180) and outdata_image_width) or
(repeat(8, sig_1181) and write8_u8);
-- Behaviour of component 'mux_762' model 'mux'
mux_762 <=
(repeat(32, sig_1118) and chenidct_a3) or
(repeat(32, sig_1217) and yuvtorgb_v) or
(repeat(32, sig_1324) and chenidct_a1);
-- Behaviour of component 'mux_766' model 'mux'
mux_766 <=
(repeat(32, sig_1436) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_781' model 'mux'
mux_781 <=
(repeat(32, sig_1608) and sig_1657) or
(repeat(32, sig_1607) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_797' model 'mux'
mux_797 <=
(repeat(32, sig_1617) and mux_798);
-- Behaviour of component 'mux_821' model 'mux'
mux_821 <=
(repeat(32, sig_1617) and mux_822);
-- Behaviour of component 'mux_826' model 'mux'
mux_826 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_778' model 'mux'
mux_778 <=
(repeat(32, sig_1607) and sig_1659) or
(repeat(32, sig_1608) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_827' model 'mux'
mux_827 <=
(repeat(32, sig_1617) and mux_828);
-- Behaviour of component 'mux_815' model 'mux'
mux_815 <=
(repeat(32, sig_1617) and mux_816);
-- Behaviour of component 'mux_798' model 'mux'
mux_798 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_816' model 'mux'
mux_816 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_817' model 'mux'
mux_817 <=
(repeat(32, sig_1617) and mux_818);
-- Behaviour of component 'mux_777' model 'mux'
mux_777 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_819' model 'mux'
mux_819 <=
(repeat(32, sig_1617) and mux_820);
-- Behaviour of component 'mux_783' model 'mux'
mux_783 <=
(repeat(32, sig_1608) and sig_1658) or
(repeat(32, sig_1607) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_795' model 'mux'
mux_795 <=
(repeat(32, sig_1617) and mux_796);
-- Behaviour of component 'mux_796' model 'mux'
mux_796 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_805' model 'mux'
mux_805 <=
(repeat(32, sig_1617) and mux_806);
-- Behaviour of component 'mux_806' model 'mux'
mux_806 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_807' model 'mux'
mux_807 <=
(repeat(32, sig_1617) and mux_808);
-- Behaviour of component 'mux_808' model 'mux'
mux_808 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_809' model 'mux'
mux_809 <=
(repeat(32, sig_1617) and mux_810);
-- Behaviour of component 'mux_810' model 'mux'
mux_810 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_811' model 'mux'
mux_811 <=
(repeat(32, sig_1617) and mux_812);
-- Behaviour of component 'mux_812' model 'mux'
mux_812 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_813' model 'mux'
mux_813 <=
(repeat(32, sig_1617) and mux_814);
-- Behaviour of component 'mux_814' model 'mux'
mux_814 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_818' model 'mux'
mux_818 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_828' model 'mux'
mux_828 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_829' model 'mux'
mux_829 <=
(repeat(32, sig_1617) and mux_830);
-- Behaviour of component 'mux_830' model 'mux'
mux_830 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_831' model 'mux'
mux_831 <=
(repeat(32, sig_1617) and mux_832);
-- Behaviour of component 'mux_832' model 'mux'
mux_832 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_836' model 'mux'
mux_836 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_837' model 'mux'
mux_837 <=
(repeat(32, sig_1617) and mux_838);
-- Behaviour of component 'mux_839' model 'mux'
mux_839 <=
(repeat(32, sig_1617) and mux_840);
-- Behaviour of component 'mux_840' model 'mux'
mux_840 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_841' model 'mux'
mux_841 <=
(repeat(32, sig_1617) and mux_842);
-- Behaviour of component 'mux_842' model 'mux'
mux_842 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_843' model 'mux'
mux_843 <=
(repeat(32, sig_1617) and mux_844);
-- Behaviour of component 'mux_856' model 'mux'
mux_856 <=
(repeat(32, sig_1617) and mux_857);
-- Behaviour of component 'and_864' model 'and'
and_864 <=
sig_1603 and
sig_1624(16);
-- Behaviour of component 'mux_870' model 'mux'
mux_870 <=
(repeat(32, sig_1599) and get_dqt_length) or
(repeat(32, sig_1669) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_872' model 'mux'
mux_872 <=
(repeat(2, sig_1598) and "10");
-- Behaviour of component 'mux_875' model 'mux'
mux_875 <=
(repeat(32, sig_1616) and sig_1647);
-- Behaviour of component 'mux_891' model 'mux'
mux_891 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_892' model 'mux'
mux_892 <=
(repeat(32, sig_1617) and mux_893);
-- Behaviour of component 'mux_893' model 'mux'
mux_893 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_894' model 'mux'
mux_894 <=
(repeat(32, sig_1617) and mux_895);
-- Behaviour of component 'mux_895' model 'mux'
mux_895 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_896' model 'mux'
mux_896 <=
(repeat(32, sig_1623) and sig_1648) or
(repeat(32, sig_1616) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_897' model 'mux'
mux_897 <=
(repeat(32, sig_1616) and sig_1647);
-- Behaviour of component 'mux_898' model 'mux'
mux_898 <=
(repeat(32, sig_1617) and mux_899);
-- Behaviour of component 'mux_899' model 'mux'
mux_899 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_900' model 'mux'
mux_900 <=
(repeat(32, sig_1617) and mux_901);
-- Behaviour of component 'mux_901' model 'mux'
mux_901 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_902' model 'mux'
mux_902 <=
(repeat(32, sig_1617) and mux_903);
-- Behaviour of component 'mux_903' model 'mux'
mux_903 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_904' model 'mux'
mux_904 <=
(repeat(32, sig_1617) and mux_905);
-- Behaviour of component 'mux_905' model 'mux'
mux_905 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_906' model 'mux'
mux_906 <=
(repeat(32, sig_1617) and mux_907);
-- Behaviour of component 'mux_907' model 'mux'
mux_907 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_908' model 'mux'
mux_908 <=
(repeat(32, sig_1617) and mux_909);
-- Behaviour of component 'mux_917' model 'mux'
mux_917 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_918' model 'mux'
mux_918 <=
(repeat(32, sig_1617) and mux_919);
-- Behaviour of component 'mux_924' model 'mux'
mux_924 <=
(repeat(32, sig_1617) and mux_925);
-- Behaviour of component 'mux_925' model 'mux'
mux_925 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_928' model 'mux'
mux_928 <=
(repeat(32, sig_1617) and mux_929);
-- Behaviour of component 'mux_929' model 'mux'
mux_929 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_931' model 'mux'
mux_931 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_932' model 'mux'
mux_932 <=
(repeat(32, sig_1617) and mux_933);
-- Behaviour of component 'mux_934' model 'mux'
mux_934 <=
(repeat(32, sig_1617) and mux_935);
-- Behaviour of component 'mux_935' model 'mux'
mux_935 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_936' model 'mux'
mux_936 <=
(repeat(32, sig_1617) and mux_937);
-- Behaviour of component 'mux_937' model 'mux'
mux_937 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_938' model 'mux'
mux_938 <=
(repeat(32, sig_1617) and mux_939);
-- Behaviour of component 'mux_939' model 'mux'
mux_939 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_941' model 'mux'
mux_941 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_944' model 'mux'
mux_944 <=
(repeat(32, sig_1617) and mux_945);
-- Behaviour of component 'mux_945' model 'mux'
mux_945 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_946' model 'mux'
mux_946 <=
(repeat(32, sig_1617) and mux_947);
-- Behaviour of component 'mux_833' model 'mux'
mux_833 <=
(repeat(32, sig_1617) and mux_834);
-- Behaviour of component 'mux_834' model 'mux'
mux_834 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_835' model 'mux'
mux_835 <=
(repeat(32, sig_1617) and mux_836);
-- Behaviour of component 'mux_838' model 'mux'
mux_838 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_844' model 'mux'
mux_844 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_857' model 'mux'
mux_857 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_858' model 'mux'
mux_858 <=
(repeat(32, sig_1617) and mux_859);
-- Behaviour of component 'mux_859' model 'mux'
mux_859 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_874' model 'mux'
mux_874 <=
(repeat(32, sig_1623) and sig_1648) or
(repeat(32, sig_1616) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_888' model 'mux'
mux_888 <=
(repeat(32, sig_1617) and mux_889);
-- Behaviour of component 'mux_889' model 'mux'
mux_889 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_913' model 'mux'
mux_913 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_914' model 'mux'
mux_914 <=
(repeat(32, sig_1617) and mux_915);
-- Behaviour of component 'mux_915' model 'mux'
mux_915 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_916' model 'mux'
mux_916 <=
(repeat(32, sig_1617) and mux_917);
-- Behaviour of component 'mux_933' model 'mux'
mux_933 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_940' model 'mux'
mux_940 <=
(repeat(32, sig_1617) and mux_941);
-- Behaviour of component 'mux_942' model 'mux'
mux_942 <=
(repeat(32, sig_1617) and mux_943);
-- Behaviour of component 'and_867' model 'and'
and_867 <=
sig_1670 and
sig_1594;
-- Behaviour of component 'mux_909' model 'mux'
mux_909 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_910' model 'mux'
mux_910 <=
(repeat(32, sig_1617) and mux_911);
-- Behaviour of component 'mux_911' model 'mux'
mux_911 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_920' model 'mux'
mux_920 <=
(repeat(32, sig_1617) and mux_921);
-- Behaviour of component 'mux_921' model 'mux'
mux_921 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_926' model 'mux'
mux_926 <=
(repeat(32, sig_1617) and mux_927);
-- Behaviour of component 'mux_927' model 'mux'
mux_927 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_943' model 'mux'
mux_943 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_886' model 'mux'
mux_886 <=
(sig_1601 and read_byte(0)) or
(sig_1602 and read_byte(0));
-- Behaviour of component 'mux_922' model 'mux'
mux_922 <=
(repeat(32, sig_1617) and mux_923);
-- Behaviour of component 'mux_923' model 'mux'
mux_923 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_930' model 'mux'
mux_930 <=
(repeat(32, sig_1617) and mux_931);
-- Behaviour of component 'mux_987' model 'mux'
mux_987 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'and_860' model 'and'
and_860 <=
sig_1637 and
buf_getv;
-- Behaviour of component 'and_881' model 'and'
and_881 <=
sig_1637 and
sig_1643;
-- Behaviour of component 'and_884' model 'and'
and_884 <=
"00000000000000000000000000010000" and
"000000000000000000000000" & read_byte;
-- Behaviour of component 'mux_890' model 'mux'
mux_890 <=
(repeat(32, sig_1617) and mux_891);
-- Behaviour of component 'mux_912' model 'mux'
mux_912 <=
(repeat(32, sig_1617) and mux_913);
-- Behaviour of component 'mux_919' model 'mux'
mux_919 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_948' model 'mux'
mux_948 <=
(repeat(32, sig_1617) and mux_949);
-- Behaviour of component 'mux_949' model 'mux'
mux_949 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_950' model 'mux'
mux_950 <=
(repeat(32, sig_1617) and mux_951);
-- Behaviour of component 'and_862' model 'and'
and_862 <=
sig_1595 and
sig_1614(16);
-- Behaviour of component 'mux_953' model 'mux'
mux_953 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_954' model 'mux'
mux_954 <=
(repeat(32, sig_1617) and mux_955);
-- Behaviour of component 'mux_955' model 'mux'
mux_955 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_951' model 'mux'
mux_951 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_952' model 'mux'
mux_952 <=
(repeat(32, sig_1617) and mux_953);
-- Behaviour of component 'mux_959' model 'mux'
mux_959 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_960' model 'mux'
mux_960 <=
(repeat(32, sig_1617) and mux_961);
-- Behaviour of component 'mux_961' model 'mux'
mux_961 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_965' model 'mux'
mux_965 <=
(repeat(32, sig_1617) and mux_966);
-- Behaviour of component 'mux_966' model 'mux'
mux_966 <=
(repeat(32, sig_1622) and yuvtorgb_r) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'and_876' model 'and'
and_876 <=
"00001111" and
"0000" & read_byte(7 downto 4);
-- Behaviour of component 'mux_956' model 'mux'
mux_956 <=
(repeat(32, sig_1617) and mux_957);
-- Behaviour of component 'mux_957' model 'mux'
mux_957 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_947' model 'mux'
mux_947 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_968' model 'mux'
mux_968 <=
(repeat(32, sig_1593) and yuvtorgb_b) or
(repeat(32, sig_1591) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_969' model 'mux'
mux_969 <=
(repeat(32, sig_1597) and mux_970);
-- Behaviour of component 'mux_970' model 'mux'
mux_970 <=
(repeat(32, sig_1586) and yuvtorgb_g) or
(repeat(32, sig_1589) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_980' model 'mux'
mux_980 <=
(repeat(32, sig_1617) and mux_981);
-- Behaviour of component 'mux_981' model 'mux'
mux_981 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_958' model 'mux'
mux_958 <=
(repeat(32, sig_1617) and mux_959);
-- Behaviour of component 'and_963' model 'and'
and_963 <=
sig_1615 and
sig_991;
-- Behaviour of component 'mux_986' model 'mux'
mux_986 <=
(repeat(32, sig_1617) and mux_987);
-- Behaviour of component 'mux_988' model 'mux'
mux_988 <=
(repeat(32, sig_1617) and mux_989);
-- Behaviour of component 'mux_989' model 'mux'
mux_989 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of all components of model 'reg'
-- Registers with clock = sig_clock and no reset
process(sig_clock)
begin
if rising_edge(sig_clock) then
if sig_1437 = '1' then
izigzagmatrix_i <= mux_768;
end if;
if sig_1437 = '1' then
izigzagmatrix_out_idx <= mux_766;
end if;
if sig_1072 = '1' then
iquantize_qidx <= sig_1610(1 downto 0);
end if;
if sig_1061 = '1' then
write8_u8 <= mux_757;
end if;
if sig_1206 = '1' then
p_jinfo_image_height <= read_word;
end if;
if sig_1207 = '1' then
p_jinfo_image_width <= read_word;
end if;
if sig_1204 = '1' then
p_jinfo_num_components <= read_byte;
end if;
if sig_1219 = '1' then
p_jinfo_smp_fact <= mux_872;
end if;
if sig_1307 = '1' then
p_jinfo_mcuwidth <= sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17 downto 0);
end if;
if sig_1307 = '1' then
p_jinfo_mcuheight <= sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17 downto 0);
end if;
if sig_1100 = '1' then
p_jinfo_nummcu <= sig_1628(31 downto 0);
end if;
if sig_1273 = '1' then
i_jinfo_jpeg_data <= readbuf_idx;
end if;
if sig_1583 = '1' then
curhuffreadbuf_idx <= mux_671;
end if;
if sig_1042 = '1' then
outdata_image_width <= p_jinfo_image_width(7 downto 0);
end if;
if sig_1042 = '1' then
outdata_image_height <= p_jinfo_image_height(7 downto 0);
end if;
if sig_1340 = '1' then
readbuf_idx <= mux_648;
end if;
if sig_1053 = '1' then
read_byte <= sig_1644;
end if;
if sig_1249 = '1' then
read_word <= read_word_c & sig_1644;
end if;
if sig_1248 = '1' then
read_word_c <= sig_1644;
end if;
if sig_1205 = '1' then
next_marker <= next_marker_c;
end if;
if sig_1203 = '1' then
next_marker_c <= read_byte;
end if;
if sig_1210 = '1' then
get_sof_ci <= mux_633;
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_id <= get_sof_ci(1 downto 0);
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_h_samp_factor <= get_sof_ci(1 downto 0);
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_quant_tbl_no <= get_sof_ci(1 downto 0);
end if;
if sig_1224 = '1' then
get_sos_num_comp <= read_byte;
end if;
if sig_1250 = '1' then
get_sos_i <= mux_622;
end if;
if sig_1272 = '1' then
get_sos_c <= read_byte(4);
end if;
if sig_1242 = '1' then
get_sos_cc <= read_byte;
end if;
if sig_1253 = '1' then
get_sos_ci <= mux_616;
end if;
if sig_1286 = '1' then
get_sos_j <= mux_614;
end if;
if sig_1243 = '1' then
get_sos_i_comp_info_dc_tbl_no <= get_sos_ci(1 downto 0);
end if;
if sig_1312 = '1' then
get_dht_length <= sig_1614(31 downto 0);
end if;
if sig_1199 = '1' then
get_dht_index <= mux_886;
end if;
if sig_1541 = '1' then
get_dht_i <= mux_602;
end if;
if sig_1456 = '1' then
get_dht_count <= mux_600;
end if;
if sig_1199 = '1' then
get_dht_is_ac <= sig_1602;
end if;
if sig_1316 = '1' then
get_dqt_length <= mux_593;
end if;
if sig_1302 = '1' then
get_dqt_prec <= read_byte(7 downto 4);
end if;
if sig_1302 = '1' then
get_dqt_num <= read_byte(1 downto 0);
end if;
if sig_1333 = '1' then
get_dqt_i <= mux_587;
end if;
if sig_1338 = '1' then
get_dqt_tmp <= mux_585;
end if;
if sig_1347 = '1' then
read_markers_unread_marker <= mux_580;
end if;
if sig_1352 = '1' then
read_markers_sow_soi <= sig_1353;
end if;
if sig_1447 = '1' then
chenidct_i <= mux_555;
end if;
if sig_1476 = '1' then
chenidct_aidx <= mux_553;
end if;
if sig_1462 = '1' then
chenidct_a0 <= mux_551;
end if;
if sig_1439 = '1' then
chenidct_a1 <= mux_549;
end if;
if sig_1584 = '1' then
chenidct_a2 <= mux_547;
end if;
if sig_1465 = '1' then
chenidct_a3 <= mux_545;
end if;
if sig_1459 = '1' then
chenidct_b0 <= mux_543;
end if;
if sig_1356 = '1' then
chenidct_b1 <= mux_541;
end if;
if sig_1478 = '1' then
chenidct_b2 <= mux_539;
end if;
if sig_1460 = '1' then
chenidct_b3 <= mux_537;
end if;
if sig_1461 = '1' then
chenidct_c0 <= mux_535;
end if;
if sig_1394 = '1' then
chenidct_c1 <= mux_533;
end if;
if sig_1394 = '1' then
chenidct_c2 <= mux_531;
end if;
if sig_1461 = '1' then
chenidct_c3 <= mux_529;
end if;
if sig_1494 = '1' then
current_read_byte <= mux_521;
end if;
if sig_1424 = '1' then
pgetc <= mux_517;
end if;
if sig_1442 = '1' then
pgetc_temp <= sig_1644;
end if;
if sig_1483 = '1' then
buf_getb <= sig_1481;
end if;
if sig_1495 = '1' then
buf_getv <= mux_507;
end if;
if sig_1200 = '1' then
buf_getv_n <= mux_505;
end if;
if sig_1490 = '1' then
buf_getv_p <= sig_1614(31 downto 0);
end if;
if sig_1488 = '1' then
buf_getv_rv <= mux_501;
end if;
if sig_1521 = '1' then
huff_make_dhuff_tb_ac <= huff_make_dhuff_tb_ac_p_dhtbl_ml;
end if;
if sig_1187 = '1' then
huff_make_dhuff_tb_ac_tbl_no <= sig_1184;
end if;
if sig_1543 = '1' then
huff_make_dhuff_tb_ac_p_dhtbl_ml <= mux_492;
end if;
if sig_1506 = '1' then
huff_make_dhuff_tb_ac_i_c0 <= mux_490;
end if;
if sig_1503 = '1' then
huff_make_dhuff_tb_ac_j <= mux_488;
end if;
if sig_1545 = '1' then
huff_make_dhuff_tb_ac_p <= mux_486;
end if;
if sig_1282 = '1' then
huff_make_dhuff_tb_ac_code <= mux_484;
end if;
if sig_1557 = '1' then
huff_make_dhuff_tb_ac_size <= mux_482;
end if;
if sig_1524 = '1' then
huff_make_dhuff_tb_ac_l <= mux_480;
end if;
if sig_1559 = '1' then
huff_make_dhuff_tb_dc <= huff_make_dhuff_tb_dc_p_dhtbl_ml;
end if;
if sig_1306 = '1' then
huff_make_dhuff_tb_dc_tbl_no <= sig_1189;
end if;
if sig_1539 = '1' then
huff_make_dhuff_tb_dc_p_dhtbl_ml <= mux_459;
end if;
if sig_1535 = '1' then
huff_make_dhuff_tb_dc_i_c0 <= mux_457;
end if;
if sig_1532 = '1' then
huff_make_dhuff_tb_dc_j <= mux_455;
end if;
if sig_1538 = '1' then
huff_make_dhuff_tb_dc_p <= mux_453;
end if;
if sig_1067 = '1' then
huff_make_dhuff_tb_dc_code <= mux_451;
end if;
if sig_1069 = '1' then
huff_make_dhuff_tb_dc_size <= mux_449;
end if;
if sig_1562 = '1' then
huff_make_dhuff_tb_dc_l <= mux_447;
end if;
if sig_1572 = '1' then
decodehuffman_ac <= mux_430;
end if;
if sig_1452 = '1' then
decodehuffman_ac_tbl_no <= decodehuffmcu_tbl_no;
end if;
if sig_1452 = '1' then
decodehuffman_ac_dhuff_ml <= sig_1652(5 downto 0);
end if;
if sig_1566 = '1' then
decodehuffman_ac_code <= mux_424;
end if;
if sig_1566 = '1' then
decodehuffman_ac_l <= mux_422;
end if;
if sig_1288 = '1' then
decodehuffman_ac_p <= sig_1614(8 downto 0);
end if;
if sig_1580 = '1' then
decodehuffman_dc <= mux_416;
end if;
if sig_1509 = '1' then
decodehuffman_dc_tbl_no <= sig_1662;
end if;
if sig_1169 = '1' then
decodehuffman_dc_dhuff_ml <= sig_1656(5 downto 0);
end if;
if sig_1573 = '1' then
decodehuffman_dc_code <= mux_410;
end if;
if sig_1573 = '1' then
decodehuffman_dc_l <= mux_408;
end if;
if sig_1290 = '1' then
decodehuffman_dc_p <= sig_1614(8 downto 0);
end if;
if sig_1509 = '1' then
decodehuffmcu_bufdim1 <= decode_block_in_buf_idx;
end if;
if sig_1578 = '1' then
decodehuffmcu_s <= mux_400;
end if;
if sig_1343 = '1' then
decodehuffmcu_diff <= mux_398;
end if;
if sig_1509 = '1' then
decodehuffmcu_tbl_no <= sig_1662;
end if;
if sig_1444 = '1' then
decodehuffmcu_i <= mux_394;
end if;
if sig_1467 = '1' then
decodehuffmcu_k <= mux_392;
end if;
if sig_1029 = '1' then
decodehuffmcu_n <= and_983;
end if;
if sig_1195 = '1' then
writeoneblock_outidx <= mux_375;
end if;
if sig_1195 = '1' then
writeoneblock_indim1 <= mux_373;
end if;
if sig_1195 = '1' then
writeoneblock_width <= p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width;
end if;
if sig_1195 = '1' then
writeoneblock_height <= p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height;
end if;
if sig_1195 = '1' then
writeoneblock_voffs <= mux_367;
end if;
if sig_1195 = '1' then
writeoneblock_hoffs <= mux_365;
end if;
if sig_1064 = '1' then
writeoneblock_i <= mux_363;
end if;
if sig_1080 = '1' then
writeoneblock_e <= mux_361;
end if;
if sig_1066 = '1' then
writeoneblock_inidx <= mux_359;
end if;
if sig_1082 = '1' then
writeoneblock_diff <= sig_1628(12 downto 0);
end if;
if sig_996 = '1' then
writeblock_i <= decode_start_i(1 downto 0);
end if;
if sig_1191 = '1' then
write4blocks_i <= decode_start_i(1 downto 0);
end if;
if sig_1193 = '1' then
write4blocks_voffs <= mux_347;
end if;
if sig_1192 = '1' then
write4blocks_hoffs <= mux_345;
end if;
if sig_998 = '1' then
yuvtorgb_p <= mux_343;
end if;
if sig_998 = '1' then
yuvtorgb_yidx <= mux_341;
end if;
if sig_998 = '1' then
yuvtorgb_uidx <= mux_339;
end if;
if sig_998 = '1' then
yuvtorgb_vidx <= mux_337;
end if;
if sig_1218 = '1' then
yuvtorgb_r <= mux_335;
end if;
if sig_1218 = '1' then
yuvtorgb_g <= mux_333;
end if;
if sig_1218 = '1' then
yuvtorgb_b <= mux_331;
end if;
if sig_1298 = '1' then
yuvtorgb_y <= sig_1642(23 downto 0);
end if;
if sig_1298 = '1' then
yuvtorgb_u <= sig_1624(30 downto 0);
end if;
if sig_1298 = '1' then
yuvtorgb_v <= sig_1614(31 downto 0);
end if;
if sig_1233 = '1' then
yuvtorgb_i <= mux_320;
end if;
if sig_1044 = '1' then
decode_block_comp_no <= mux_317;
end if;
if sig_1044 = '1' then
decode_block_out_buf_idx <= mux_308;
end if;
if sig_1044 = '1' then
decode_block_in_buf_idx <= mux_294;
end if;
if sig_1430 = '1' then
decode_start_i <= mux_292;
end if;
if sig_1182 = '1' then
decode_start_currentmcu <= mux_286;
end if;
if sig_1055 = '1' then
jpeg2bmp_main_i <= mux_262;
end if;
if sig_1058 = '1' then
jpeg2bmp_main_j <= mux_257;
end if;
if sig_1178 = '1' then
read8_ret0_195 <= stdin_data;
end if;
end if;
end process;
-- Registers with clock = sig_clock and reset = sig_reset active '1'
process(sig_clock, sig_reset)
begin
if sig_reset = '1' then
read_position <= "11111111111111111111111111111111";
else
if rising_edge(sig_clock) then
if sig_1496 = '1' then
read_position <= mux_519;
end if;
end if;
end if;
end process;
-- Remaining signal assignments
-- Those who are not assigned by component instantiation
sig_clock <= clock;
sig_reset <= reset;
augh_test_159 <= sig_1615;
augh_test_26 <= sig_1616;
augh_test_49 <= sig_1616;
augh_test_52 <= sig_1616;
augh_test_53 <= and_867;
augh_test_67 <= sig_1618;
augh_test_72 <= sig_1615;
augh_test_77 <= sig_1616;
augh_test_83 <= sig_1618;
augh_test_89 <= sig_1615;
augh_test_90 <= sig_1669;
augh_test_105 <= sig_1615;
augh_test_106 <= sig_1615;
augh_test_107 <= sig_1615;
augh_test_111 <= sig_1616;
augh_test_114 <= sig_1618;
augh_test_115 <= sig_1618;
augh_test_119 <= sig_1615;
augh_test_120 <= sig_1615;
augh_test_122 <= and_963;
augh_test_125 <= sig_1615;
augh_test_127 <= sig_1615;
augh_test_128 <= sig_1615;
augh_test_130 <= and_976;
augh_test_133 <= sig_1615;
augh_test_136 <= sig_1618;
augh_test_138 <= sig_1616;
augh_test_142 <= sig_1618;
augh_test_144 <= sig_1616;
augh_test_151 <= sig_1615;
augh_test_152 <= sig_1615;
augh_test_155 <= sig_1618;
augh_test_165 <= sig_1616;
augh_test_166 <= sig_1616;
augh_test_167 <= sig_1616;
augh_test_168 <= sig_1616;
sig_start <= start;
augh_test_171 <= sig_1615;
augh_test_178 <= sig_1615;
augh_test_179 <= sig_1615;
augh_test_182 <= sig_1616;
augh_test_183 <= sig_1615;
augh_test_184 <= sig_1615;
augh_test_186 <= sig_1616;
augh_test_187 <= sig_1615;
augh_test_188 <= sig_1615;
augh_test_189 <= sig_1615;
sig_1671 <= "000000000000000000000000" & pgetc_temp;
sig_1672 <= "000000000000000000000000000000" & p_jinfo_smp_fact;
sig_1673 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1674 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1675 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1676 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1677 <= "000000000000000000000000" & next_marker_c;
sig_1678 <= "000000000000000000000000" & pgetc_temp;
sig_1679 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1680 <= "000000000000000000000000" & read_byte;
sig_1681 <= "000000000000000000000000" & next_marker_c;
sig_1682 <= "0000000000000000000000000000" & get_dqt_prec;
sig_1683 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1684 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1685 <= "0000000000000000000000000000000" & get_dht_is_ac;
sig_1686 <= "0000000000000000000000000000000" & get_dht_is_ac;
sig_1687 <= "0000" & decodehuffmcu_n;
sig_1688 <= sig_1612(23 downto 0) & sig_1667(7);
sig_1689 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1690 <= "00000000000000000000000" & mux_313;
sig_1691 <= writeoneblock_indim1 & writeoneblock_outidx & writeoneblock_inidx(5 downto 0);
sig_1692 <= yuvtorgb_uidx & yuvtorgb_i(5 downto 0);
sig_1693 <= jpeg2bmp_main_i(1 downto 0) & jpeg2bmp_main_j(12 downto 0);
sig_1694 <= writeoneblock_outidx & sig_1610(12 downto 0);
sig_1695 <= decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0);
sig_1696 <= huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0);
sig_1697 <= decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0);
sig_1698 <= huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0);
sig_1699 <= decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0);
sig_1700 <= huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0);
sig_1701 <= decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0);
sig_1702 <= huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0);
sig_1703 <= get_dht_index & get_dht_i(8 downto 0);
sig_1704 <= get_dht_index & get_dht_i(5 downto 0);
sig_1705 <= get_dht_index & get_dht_i(8 downto 0);
sig_1706 <= get_dht_index & get_dht_i(5 downto 0);
sig_1707 <= sig_1610(1 downto 0) & sig_1645;
sig_1708 <= "0000000000000000" & get_dqt_tmp;
sig_1709 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1710 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1711 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1712 <= "00000000000000000000000011" & mux_759;
sig_1713 <= "00000000000000000000000" & mux_761;
sig_1714 <= "0000000000000000000000000000000" & read_markers_sow_soi;
sig_1715 <= "0000000000000000000000000000" & get_dqt_prec;
sig_1716 <= "000000000000000000000000" & read_markers_unread_marker;
-- Remaining top-level ports assignments
-- Those who are not assigned by component instantiation
stdout_data <= mux_773;
stdin_rdy <= sig_1178;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1019.vhd | 4 | 2237 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1019.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01019ent IS
port (p : in bit);
END c06s03b00x00p10n01i01019ent;
ARCHITECTURE c06s03b00x00p10n01i01019arch OF c06s03b00x00p10n01i01019ent IS
BEGIN
B1:Block
type chars is ('a', 'b', 'c', 'd', 'e');
begin
TESTING: PROCESS
variable c : chars;
variable All_done : boolean;
BEGIN
L1 : for LL1 in TRUE downto FALSE loop
NULL;
if L1.LL1 then -- Selected prefix is loop,
-- suffix is identifier that
-- refers to loop iteration id.
All_done := True;
end if;
end loop L1;
assert NOT(All_done=TRUE)
report "***PASSED TEST: c06s03b00x00p10n01i01019"
severity NOTE;
assert (All_done=TRUE)
report "***FAILED TEST: c06s03b00x00p10n01i01019 - Entity declaration does not occur in construct specifed by the prefix."
severity ERROR;
wait;
END PROCESS TESTING;
end block B1;
END c06s03b00x00p10n01i01019arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2974.vhd | 4 | 2035 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2974.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p03n01i02974ent IS
END c02s03b01x00p03n01i02974ent;
ARCHITECTURE c02s03b01x00p03n01i02974arch OF c02s03b01x00p03n01i02974ent IS
type newt is (one,two,three,four);
function "-" (constant c1 : in integer) return newt is
begin
assert (c1=70)
report "Error in association of unary - operator"
severity failure;
assert NOT( c1=70 )
report "***PASSED TEST: c02s03b01x00p03n01i02974"
severity NOTE;
assert ( c1=70 )
report "***FAILED TEST: c02s03b01x00p03n01i02974 - Error in - overloading as unary operator."
severity ERROR;
return four;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
n1:= -70;
assert (n1=four)
report "Error in call to overloaded unary - operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p03n01i02974arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/cmp_964.vhd | 2 | 378 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_964 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_964;
architecture augh of cmp_964 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd | 4 | 1306 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity lowpass is
port ( terminal input : electrical;
terminal output : electrical );
end entity lowpass;
----------------------------------------------------------------
architecture dot of lowpass is
quantity vin across input to electrical_ref;
quantity vout across iout through output to electrical_ref;
constant tp : real := 15.9e-3; -- filter time constant
begin
vin == vout + tp * vout'dot;
end architecture dot;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc43.vhd | 3 | 1827 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc43.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00043ent IS
END c04s03b01x01p02n01i00043ent;
ARCHITECTURE c04s03b01x01p02n01i00043arch OF c04s03b01x01p02n01i00043ent IS
-- constant integer:integer := 1; -- No_failure_here
-- According to scopes and visibility rules, this test is not correct.
constant integer:natural := 1;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(integer = 1)
report "***PASSED TEST: c04s03b01x01p02n01i00043"
severity NOTE;
assert (integer = 1)
report "***FAILED TEST:c04s03b01x01p02n01i00043 - Constant declaration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00043arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc72.vhd | 4 | 1680 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc72.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p09n01i00072ent IS
END c04s03b01x02p09n01i00072ent;
ARCHITECTURE c04s03b01x02p09n01i00072arch OF c04s03b01x02p09n01i00072ent IS
type x is access integer;
signal s1 : x; -- Failure_here
-- error as the signal is an access type.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x02p09n01i00072 - Signal can not be declared to be an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x02p09n01i00072arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/sr2940/Prim.vhd | 3 | 2219 | -- Types and functions for Haskell Primitives
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package \Prim\ is
subtype \Int#\ is signed(31 downto 0);
subtype \GHC.Types.Int\ is signed(31 downto 0);
subtype \GHC.Types.Bool\ is std_logic;
-- Primitive arithmetic operations
function \GHC.Prim.==#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\;
function \GHC.Prim.<#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\;
function \GHC.Prim.-#\ ( a, b : \Int#\ ) return \Int#\;
-- Data Constructor predicates: each takes a object and returns
-- a boolean (i.e., tested with VHDL's if) that indicates whether the
-- object was constructed with the given constructor
function \is_GHC.Types.False\ (a : \GHC.Types.Bool\) return boolean;
function \is_GHC.Types.True\ (a : \GHC.Types.Bool\) return boolean;
function \is_GHC.Types.I#\ (a : \GHC.Types.Int\) return boolean;
-- Data "deconstructor" procedures: split apart an algebraic data type
-- into fields
procedure \expand_GHC.Types.I#\ ( input : in \GHC.Types.Int\;
field1 : out \Int#\);
end \Prim\;
package body \Prim\ is
function \GHC.Prim.==#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\ is
begin
if a = b then
return '1';
else
return '0';
end if;
end \GHC.Prim.==#\;
function \GHC.Prim.<#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\ is
begin
if a < b then
return '1';
else
return '0';
end if;
end \GHC.Prim.<#\;
function \GHC.Prim.-#\ ( a, b : \Int#\ ) return \Int#\ is
begin
return a - b;
end \GHC.Prim.-#\;
function \is_GHC.Types.False\ (a : \GHC.Types.Bool\) return boolean is
begin
return a = '0';
end \is_GHC.Types.False\;
function \is_GHC.Types.True\ (a : \GHC.Types.Bool\) return boolean is
begin
return a = '1';
end \is_GHC.Types.True\;
function \is_GHC.Types.I#\ (a : \GHC.Types.Int\) return boolean is
begin
return true; -- Trivial: there's only one constructor
end \is_GHC.Types.I#\;
procedure \expand_GHC.Types.I#\ (
input : in \GHC.Types.Int\;
field1 : out \Int#\) is
begin
field1 := input;
end \expand_GHC.Types.I#\;
end \Prim\;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1745.vhd | 4 | 1870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1745.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p05n03i01745ent IS
END c09s05b00x00p05n03i01745ent;
ARCHITECTURE c09s05b00x00p05n03i01745arch OF c09s05b00x00p05n03i01745ent IS
signal A : bit := '0';
BEGIN
A <= transport '1' after 10 ns;
TESTING: PROCESS(A)
variable NEWTIME : TIME;
BEGIN
NEWTIME := now;
if ( now > 1 ns ) then
assert NOT( A= '1' and NEWTIME = 10 ns )
report "***PASSED TEST: c09s05b00x00p05n03i01745"
severity NOTE;
assert ( A= '1' and NEWTIME = 10 ns )
report "***FAILED TEST: c09s05b00x00p05n03i01745 - Transport specifies the transport delay."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s05b00x00p05n03i01745arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug019/PoC/src/common/components.vhdl | 3 | 11438 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Common primitives described as a function
--
-- Description:
-- ------------------------------------
-- This packages describes common primitives like flip flops and multiplexers
-- as a function to use them as one-liners.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
PACKAGE components IS
-- FlipFlop functions
function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with reset and enable
function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR; -- D-FlipFlop with reset and enable
function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with set and enable
function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- T-FlipFlop with reset and enable
function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant rst
function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant set
-- adder
function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR;
function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED;
function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED;
function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR;
function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED;
function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED;
-- negate
function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; -- calculate 2's complement
-- counter
function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED;
function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC;
function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED;
function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC;
function downcounter_neg(cnt : SIGNED) return STD_LOGIC;
-- shift/rotate registers
function sr_left(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR;
function sr_right(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR;
function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- compare
function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED;
function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED;
function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC;
function comp_allzero(value : UNSIGNED) return STD_LOGIC;
function comp_allzero(value : SIGNED) return STD_LOGIC;
function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC;
function comp_allone(value : UNSIGNED) return STD_LOGIC;
function comp_allone(value : SIGNED) return STD_LOGIC;
-- multiplexing
function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC;
function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED;
function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED;
end;
package body components is
-- d-flipflop with reset and enable
function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((d and en) or (q and not en)) and not rst;
end function;
function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR is
begin
return ((d and (q'range => en)) or (q and not (q'range => en))) and not (q'range => rst);
end function;
-- d-flipflop with set and enable
function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((d and en) or (q and not en)) or set;
end function;
-- t-flipflop with reset and enable
function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((not q and en) or (q and not en)) and not rst;
end function;
-- rs-flipflop with dominant rst
function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is
begin
return (q or set) and not rst;
end function;
-- rs-flipflop with dominant set
function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is
begin
return (q and not rst) or set;
end function;
-- adder
function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(inc(unsigned(value), increment));
end function;
function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED is
begin
return value + increment;
end function;
function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED is
begin
return value + increment;
end function;
function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(dec(unsigned(value), decrement));
end function;
function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED is
begin
return value + decrement;
end function;
function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED is
begin
return value + decrement;
end function;
-- negate
function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(inc(unsigned(not value))); -- 2's complement
end function;
-- counter
function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED is
begin
if (rst = '1') then
return to_unsigned(init, cnt'length);
elsif (en = '1') then
return cnt + 1;
else
return cnt;
end if;
end function;
function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC is
begin
-- optimized comparison for only up counting values
return to_sl((cnt and to_unsigned(value, cnt'length)) = value);
end function;
function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED is
begin
if (rst = '1') then
return to_signed(init, cnt'length);
elsif (en = '1') then
return cnt - 1;
else
return cnt;
end if;
end function;
function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC is
begin
-- optimized comparison for only down counting values
return to_sl((cnt nor to_signed(value, cnt'length)) /= value);
end function;
function downcounter_neg(cnt : SIGNED) return STD_LOGIC is
begin
return cnt(cnt'high);
end function;
-- shift/rotate registers
function sr_left(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is
begin
return q(q'left - 1 downto q'right) & i;
end function;
function sr_right(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is
begin
return i & q(q'left downto q'right - 1);
end function;
function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return q(q'left - 1 downto q'right) & q(q'left);
end function;
function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return q(q'right) & q(q'left downto q'right - 1);
end function;
-- compare functions
-- return value 1- => value1 < value2 (difference is negative)
-- return value 00 => value1 = value2 (difference is zero)
-- return value -1 => value1 > value2 (difference is positive)
function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
report "Comparing two STD_LOGIC_VECTORs - implicit conversion to UNSIGNED" severity WARNING;
return std_logic_vector(comp(unsigned(value1), unsigned(value2)));
end function;
function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is
begin
if (value1 < value2) then
return "10";
elsif (value1 = value2) then
return "00";
else
return "01";
end if;
end function;
function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED is
begin
if (value1 < value2) then
return "10";
elsif (value1 = value2) then
return "00";
else
return "01";
end if;
end function;
function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return comp_allzero(unsigned(value));
end function;
function comp_allzero(value : UNSIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allzero(value : SIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return comp_allone(unsigned(value));
end function;
function comp_allone(value : UNSIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '1'));
end function;
function comp_allone(value : SIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '1'));
end function;
-- multiplexing
function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC is
begin
return (sl0 and not sel) or (sl1 and sel);
end function;
function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel));
end function;
function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED is
begin
return (us0 and not (us0'range => sel)) or (us1 and (us1'range => sel));
end function;
function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED is
begin
return (s0 and not (s0'range => sel)) or (s1 and (s1'range => sel));
end function;
END PACKAGE BODY; | gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue67/nullacc.vhdl | 2 | 330 | entity nullacc is
end nullacc;
architecture behav of nullacc is
begin
process
type int_acc is access integer;
variable v : int_acc;
begin
v := new integer'(7);
assert v.all = 7 severity failure;
deallocate (v);
assert v.all = 0 severity note; -- access error
wait;
end process;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2566.vhd | 4 | 2411 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2566.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s04b02x00p15n01i02566ent_a IS
GENERIC ( gen_prm : INTEGER );
END c07s04b02x00p15n01i02566ent_a;
ARCHITECTURE c07s04b02x00p15n01i02566arch_a OF c07s04b02x00p15n01i02566ent_a IS
SIGNAL s : BIT;
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF s : SIGNAL IS gen_prm;
--
-- Usage of user-defined attribute as a globally-static expression
--
CONSTANT c0 : INTEGER := s'attr1;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c0 = gen_prm )
report "***PASSED TEST: c07s04b02x00p15n01i02566"
severity NOTE;
assert ( c0 = gen_prm )
report "***FAILED TEST: c07s04b02x00p15n01i02566 - Constant initialization to user-attribute value failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s04b02x00p15n01i02566arch_a;
ENTITY c07s04b02x00p15n01i02566ent IS
END c07s04b02x00p15n01i02566ent;
ARCHITECTURE c07s04b02x00p15n01i02566arch OF c07s04b02x00p15n01i02566ent IS
COMPONENT c07s04b02x00p15n01i02566ent_a
GENERIC ( gen_prm : INTEGER );
END COMPONENT;
for cmp : c07s04b02x00p15n01i02566ent_a use entity work.c07s04b02x00p15n01i02566ent_a(c07s04b02x00p15n01i02566arch_a);
BEGIN
cmp : c07s04b02x00p15n01i02566ent_a generic map (123);
END c07s04b02x00p15n01i02566arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc237.vhd | 4 | 1892 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc237.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00237ent IS
END c03s01b02x00p04n01i00237ent;
ARCHITECTURE c03s01b02x00p04n01i00237arch OF c03s01b02x00p04n01i00237ent IS
type t3 is range (1+1) to (ms/ns);
BEGIN
TESTING: PROCESS
variable k : integer := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p04n01i00237"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p04n01i00237 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00237arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1257.vhd | 4 | 1668 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1257.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01257ent IS
END c08s02b00x00p04n02i01257ent;
ARCHITECTURE c08s02b00x00p04n02i01257arch OF c08s02b00x00p04n02i01257ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "Report this Warning"
severity WARNING;
assert FALSE
report "***PASSED TEST: c08s02b00x00p04n02i01257 - This test needed manual check to see WARNING assertion note appear."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01257arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc751.vhd | 4 | 23127 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc751.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00751ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00751ent;
ARCHITECTURE c01s01b01x01p05n02i00751arch OF c01s01b01x01p05n02i00751ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
BEGIN
TESTING: PROCESS
variable V1 : boolean_vector(zero to fifteen) ;
variable V2 : severity_level_vector(zero to fifteen);
variable V3 : integer_vector(zero to fifteen) ;
variable V4 : real_vector(zero to fifteen) ;
variable V5 : time_vector (zero to fifteen);
variable V6 : natural_vector(zero to fifteen);
variable V7 : positive_vector(zero to fifteen);
variable V8 : boolean_cons_vector;
variable V9 : severity_level_cons_vector ;
variable V10 : integer_cons_vector;
variable V11 : real_cons_vector;
variable V12 : time_cons_vector ;
variable V13 : natural_cons_vector ;
variable V14 : positive_cons_vector ;
variable V15 : boolean_cons_vectorofvector ;
variable V16 : severity_level_cons_vectorofvector;
variable V17 : integer_cons_vectorofvector;
variable V18 : real_cons_vectorofvector;
variable V19 : time_cons_vectorofvector;
variable V20 : natural_cons_vectorofvector;
variable V21 : positive_cons_vectorofvector;
variable V22 : record_std_package;
variable V23 : record_cons_array ;
variable V24 : record_cons_arrayofarray ;
variable V25 : boolean_vector_st ;
variable V26 : severity_level_vector_st ;
variable V27 : integer_vector_st ;
variable V28 : real_vector_st ;
variable V29 : time_vector_st ;
variable V30 : natural_vector_st ;
variable V31 : positive_vector_st ;
variable V32 : record_array_st ;
variable V33 : record_array_st ;
variable V34 : record_array_new ;
variable V35 : record_of_records ;
variable V36 : byte ;
variable V37 : word ;
variable V41 : boolean_vector_range ;
variable V42 : severity_level_vector_range ;
variable V43 : integer_vector_range ;
variable V44 : real_vector_range ;
variable V45 : time_vector_range ;
variable V46 : natural_vector_range ;
variable V47 : positive_vector_range ;
variable V48 : array_rec_std(zero to seven) ;
variable V49 : array_rec_cons(zero to seven) ;
variable V50 : array_rec_rec(zero to seven) ;
variable V51 : record_of_arr_of_record ;
BEGIN
V1 := (zero to fifteen => C1);
V2 := (zero to fifteen => C4);
V3 := (zero to fifteen => C5);
V4 := (zero to fifteen => C6);
V5 := (zero to fifteen => C7);
V6 := (zero to fifteen => C8);
V7 := (zero to fifteen => C9);
V8 := C19;
V9 := C20;
V10 := C21;
V11 := C22;
V12 := C23;
V13 := C24;
V14 := C25;
V15 := C26;
V16 := C27;
V17 := C28;
V18 := C29;
V19 := C30;
V20 := C31;
V21 := C32;
V22 := C50;
V23 := C51;
V24 := C53;
V25 := C70;
V26 := C71;
V27 := C72;
V28 := C73;
V29 := C74;
V30 := C75;
V31 := C76;
V32 := C54a;
V33 := C54a;
V34 := C54b;
V35 := C55;
V36 := C60;
V37 := C61;
V41 := C78;
V42 := C79;
V43 := C80;
V44 := C81;
V45 := C82;
V46 := C83;
V47 := C84;
V48 := C85;
V49 := C86;
V50 := C88;
V51 := C102;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00751"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00751 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00751arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc175.vhd | 4 | 1751 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc175.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00175ent IS
END c04s03b03x01p03n02i00175ent;
ARCHITECTURE c04s03b03x01p03n02i00175arch OF c04s03b03x01p03n02i00175ent IS
signal Addr : bit;
alias SIGN1 : integer is Addr; -- Failure_here
-- error as Addr is of type bit
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c04s03b03x01p03n02i00175 - Alias base type does not match subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00175arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2736.vhd | 4 | 2150 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2736.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p01n01i02736ent IS
END c13s06b00x00p01n01i02736ent;
ARCHITECTURE c13s06b00x00p01n01i02736arch OF c13s06b00x00p01n01i02736ent IS
BEGIN
TESTING: PROCESS
variable S45 : STRING (1 to 44);
variable S50 : STRING (1 to 50);
BEGIN
S45 := "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,";
S50 := "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~";
wait for 5 ns;
assert NOT( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***PASSED TEST: c13s06b00x00p01n01i02736"
severity NOTE;
assert ( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***FAILED TEST: c13s06b00x00p01n01i02736 - String literal lexical test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p01n01i02736arch;
| gpl-2.0 |
gmsanchez/OrgComp | TP_02/TB_SN54LV165A.vhd | 1 | 3793 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:06:18 10/01/2014
-- Design Name:
-- Module Name: E:/2014/Academico/OC/2014/tp2/TB_SN54LV165A.vhd
-- Project Name: tp2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SN54LV165A
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_SN54LV165A IS
END TB_SN54LV165A;
ARCHITECTURE behavior OF TB_SN54LV165A IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SN54LV165A
PORT(
CLK : IN std_logic;
CLKIN : IN std_logic;
NLOAD : IN std_logic;
SER : IN std_logic;
DIN : IN std_logic_vector(7 downto 0);
Q : OUT std_logic;
NQ : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal CLKIN : std_logic := '0';
signal NLOAD : std_logic := '0';
signal SER : std_logic := '0';
signal DIN : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal Q : std_logic;
signal NQ : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SN54LV165A PORT MAP (
CLK => CLK,
CLKIN => CLKIN,
NLOAD => NLOAD,
SER => SER,
DIN => DIN,
Q => Q,
NQ => NQ
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
nload<='1';
-- hold reset state for 20 ns.
wait for 20 ns;
-- insert stimulus here
CLKIN<='1';
SER<='0';
NLOAD<='1';
DIN<="00000000";
wait for 20 ns;
NLOAD<='0';
DIN<="11010101";
wait for 5 ns;
NLOAD<='1';
wait for 20 ns;
CLKIN<='0';
wait;
end process;
corr_proc: process(CLK)
variable theTime : time;
begin
theTime := now;
if theTime=30000 ps then
report time'image(theTime);
assert (q='0' and nq='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=45000 ps then
report time'image(theTime);
assert (q='1' and nq='0')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=90000 ps then
report time'image(theTime);
assert (q='0' and nq='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=100000 ps then
report time'image(theTime);
assert (q='1' and nq='0')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=110000 ps then
report time'image(theTime);
assert (q='0' and nq='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=120000 ps then
report time'image(theTime);
assert (q='1' and nq='0')
report("Salidas erroneas.")
severity ERROR;
end if;
end process;
END;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/generics/entity-generic-defines-port-type.vhdl | 3 | 1012 | entity test_bench is
end test_bench;
entity generic_defines_port_type is
generic( width : natural );
port( input : in bit_vector( width - 1 downto 0 );
finished : in boolean );
end entity;
architecture only of generic_defines_port_type is
begin -- only
p: process( finished )
begin -- process p
if finished = true then
for i in input'range loop
assert input(i) = '1' report "TEST FAILED" severity FAILURE;
end loop; -- i
end if;
end process p;
end only;
architecture only of test_bench is
signal gdpt1_input : bit_vector( 3 downto 0 ) := "0000";
signal gdpt1_finished : boolean := false;
begin -- only
gdpt1: entity work.generic_defines_port_type
generic map ( width => 4 )
port map ( input => gdpt1_input, finished => gdpt1_finished );
doit: process
begin -- process doit
gdpt1_input <= "1111";
wait for 1 fs;
gdpt1_finished <= true;
wait for 1 fs;
report "TEST PASSED";
wait;
end process doit;
end only;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_04.vhd | 4 | 2297 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_04 is
end entity fg_07_04;
architecture test of fg_07_04 is
signal phase1, phase2, reg_file_write_en,
A_reg_out_en, B_reg_out_en, C_reg_load_en : bit := '0';
begin
-- code from book
control_sequencer : process is
procedure control_write_back is
begin
wait until phase1 = '1';
reg_file_write_en <= '1';
wait until phase2 = '0';
reg_file_write_en <= '0';
end procedure control_write_back;
procedure control_arith_op is
begin
wait until phase1 = '1';
A_reg_out_en <= '1';
B_reg_out_en <= '1';
wait until phase1 = '0';
A_reg_out_en <= '0';
B_reg_out_en <= '0';
wait until phase2 = '1';
C_reg_load_en <= '1';
wait until phase2 = '0';
C_reg_load_en <= '0';
control_write_back; -- call procedure
end procedure control_arith_op;
-- . . .
begin
-- . . .
control_arith_op; -- call procedure
-- . . .
-- not in book
wait;
-- end not in book
end process control_sequencer;
-- end code from book
clock_gen : process is
begin
phase1 <= '1' after 10 ns, '0' after 20 ns;
phase2 <= '1' after 30 ns, '0' after 40 ns;
wait for 40 ns;
end process clock_gen;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3099.vhd | 4 | 2902 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3099.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p09n01i03099ent IS
ATTRIBUTE attr1 : INTEGER;
END c05s01b00x00p09n01i03099ent;
ARCHITECTURE c05s01b00x00p09n01i03099arch OF c05s01b00x00p09n01i03099ent IS
SIGNAL s1,s2,s3 : BIT;
SIGNAL s4,s5 : INTEGER;
SIGNAL s6,s7 : STRING(1 TO 3);
ATTRIBUTE attr1 OF s1,s2,s3,s4,s5,s6,s7 : SIGNAL IS 101;
BEGIN
TESTING: PROCESS
BEGIN
ASSERT s1'attr1 = 101 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
ASSERT s2'attr1 = 101 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
ASSERT s3'attr1 = 101 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
ASSERT s4'attr1 = 101 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
ASSERT s5'attr1 = 101 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
ASSERT s6'attr1 = 101 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
ASSERT s7'attr1 = 101 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
assert NOT( s1'attr1 = 101 and
s2'attr1 = 101 and
s3'attr1 = 101 and
s4'attr1 = 101 and
s5'attr1 = 101 and
s6'attr1 = 101 and
s7'attr1 = 101 )
report "***PASSED TEST: c05s01b00x00p09n01i03099"
severity NOTE;
assert ( s1'attr1 = 101 and
s2'attr1 = 101 and
s3'attr1 = 101 and
s4'attr1 = 101 and
s5'attr1 = 101 and
s6'attr1 = 101 and
s7'attr1 = 101 )
report "***FAILED TEST: c05s01b00x00p09n01i03099 - Attribute specification applies to the entity designators list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p09n01i03099arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc918.vhd | 4 | 1763 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc918.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p13n01i00918ent IS
procedure subprogram ( a : integer; b : real ) is
begin
assert ( b = real (a) ) report "not the same" severity FAILURE;
assert NOT( b = real(a) )
report "***PASSED TEST: c10s03b00x00p13n01i00918"
severity NOTE;
assert ( b = real(a) )
report "***FAILED TEST: c10s03b00x00p13n01i00918 - "
severity ERROR;
end subprogram;
END c10s03b00x00p13n01i00918ent;
ARCHITECTURE c10s03b00x00p13n01i00918arch OF c10s03b00x00p13n01i00918ent IS
BEGIN
subprogram ( a => 10 , b => 10.0 );
END c10s03b00x00p13n01i00918arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd | 4 | 1253 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity piston is
port ( terminal motion : translational );
end entity piston;
--------------------------------------------------------------
architecture simple of piston is
constant mass : real := 10.0;
quantity resultant_displacement across applied_force through motion;
begin
applied_force == mass * resultant_displacement'dot'dot;
end architecture simple;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1633.vhd | 4 | 1889 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1633.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n01i01633ent IS
END c08s12b00x00p05n01i01633ent;
ARCHITECTURE c08s12b00x00p05n01i01633arch OF c08s12b00x00p05n01i01633ent IS
BEGIN
TESTING: PROCESS
type AR2 is array (0 to 2) of BIT;
function K return AR2 is
begin
return (1 => '1', others => '0');
end K;
variable kk : AR2;
BEGIN
kk := K;
assert (kk = "010")
report "***FAILED TEST: c08s12b00x00p05n01i01633 - The return type must be the same base tyep declared in the specification of the function."
severity ERROR;
assert NOT(kk = "010")
report "***PASSED TEST: c08s12b00x00p05n01i01633"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01633arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_edge_triggered_register.vhd | 4 | 1584 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_edge_triggered_register is
end entity tb_edge_triggered_register;
----------------------------------------------------------------
architecture test_check_timing of tb_edge_triggered_register is
signal clock : bit := '0';
signal d_in, d_out : real := 0.0;
begin
dut : entity work.edge_triggered_register(check_timing)
port map ( clock => clock, d_in => d_in, d_out => d_out );
stumulus : process is
begin
wait for 20 ns;
d_in <= 1.0; wait for 10 ns;
clock <= '1', '0' after 10 ns; wait for 20 ns;
d_in <= 2.0; wait for 10 ns;
clock <= '1', '0' after 5 ns; wait for 20 ns;
d_in <= 3.0; wait for 10 ns;
clock <= '1', '0' after 4 ns; wait for 20 ns;
wait;
end process stumulus;
end architecture test_check_timing;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2621.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2621.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02621ent IS
END c13s03b01x00p02n01i02621ent;
ARCHITECTURE c13s03b01x00p02n01i02621arch OF c13s03b01x00p02n01i02621ent IS
BEGIN
TESTING: PROCESS
variable k-k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02621 - Identifier can not contain '-'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02621arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc902.vhd | 4 | 1784 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc902.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00902ent IS
type work is (foo,bar); -- No_Failure_here
END c10s03b00x00p05n01i00902ent;
ARCHITECTURE c10s03b00x00p05n01i00902arch OF c10s03b00x00p05n01i00902ent IS
BEGIN
TESTING: PROCESS
variable var : work := foo;
BEGIN
wait for 5 ns;
assert NOT( var = foo )
report "***PASSED TEST: c10s03b00x00p05n01i00902"
severity NOTE;
assert ( var = foo )
report "***FAILED TEST: c10s03b00x00p05n01i00902 - The declaration should be visible in the architecture."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00902arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3087.vhd | 4 | 1908 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3087.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p01n01i03087ent IS
END c05s01b00x00p01n01i03087ent;
ARCHITECTURE c05s01b00x00p01n01i03087arch OF c05s01b00x00p01n01i03087ent IS
-- architecture declaration section
BEGIN
-- architecture statement part
TESTING: PROCESS
BEGIN
-- testcase code
Assert FALSE
Report "***PASSED TEST: c05s01b00x00p01n01i03087"
Severity NOTE;
-- testcase code
Assert FALSE
Report "***FAILED TEST: c05s01b00x00p01n01i03087"
Severity ERROR;
wait; -- forever
END PROCESS TESTING;
END c05s01b00x00p01n01i03087arch;
-- CONFIGURATION c05s01b00x00p01n01i03087cfg OF c05s01b00x00p01n01i03087ent IS
-- FOR c05s01b00x00p01n01i03087arch
-- END FOR;
-- END c05s01b00x00p01n01i03087cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue238/var2.vhdl | 2 | 170 | entity var2 is
end;
use work.pkg.all;
architecture behav of var2 is
begin
process
variable v1, v2 : rec_4;
begin
v2 := v1;
wait;
end process;
end behav;
| gpl-2.0 |
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