repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/cycloneiii_clkgen.vhd | 1 | 7960 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of cyclone3_pll is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY"
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
-- Must use operation_mode other than "ZERO_DELAY_BUFFER" due to
-- tool issues with ZERO_DELAY_BUFFER and non-existent output clock
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 5,
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_cycloneiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_cycloneiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component cyclone3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : cyclone3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_cycloneiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-2.0 |
gareth8118/lepton-eda | gnetlist/examples/vams/vhdl/basic-vhdl/gnd_node.vhdl | 15 | 315 | LIBRARY disciplines,ieee;
--USE disciplines.electromagnetic_system.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
ENTITY ground_node IS
PORT (TERMINAL t1: electrical);
END entity;
ARCHITECTURE beh OF ground_node IS
QUANTITY v ACROSS i THROUGH t1 TO ground;
BEGIN
v == 0.0;
END architecture;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/leon3_zc702_stub_sim.vhd | 2 | 9621 | -------------------------------------------------------------------------------
-- leon3_zc702_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity leon3_zc702_stub is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end leon3_zc702_stub;
architecture STRUCTURE of leon3_zc702_stub is
signal clk : std_logic := '0';
signal clk0 : std_logic := '0';
signal clk1 : std_logic := '0';
signal rst : std_logic := '0';
type memstatetype is (idle, read1, read2, read3, write1, write2, write3);
type blane is array (0 to 2**18-1) of natural;
type memtype is array (0 to 3) of blane;
constant abits : integer := 20;
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**abits)-1)) of BYTE;
type regtype is record
memstate : memstatetype;
addr : integer;
arlen : integer;
mem : memtype;
rcnt : integer;
end record;
signal S_AXI_GP0_rvalid_i : std_logic;
signal r, rin : regtype;
begin
clk0 <= not clk0 after 6.0 ns; -- 83.33 MHz
clk1 <= not clk1 after 2.5 ns; -- 200 MHz
rst <= '1' after 1 us;
S_AXI_GP0_rvalid <= S_AXI_GP0_rvalid_i;
FCLK_CLK0 <= clk0;
clk <= clk0;
FCLK_CLK1 <= clk1;
-- FCLK_CLK2 <= clk2;
-- FCLK_CLK3 <= clk3;
FCLK_RESET0_N <= rst;
mem0 : process(clk)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is "ram.srec";
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable memstate : memstatetype;
variable addr : integer;
-- variable len : integer;
-- variable mem : memtype;
variable rcnt : integer;
begin
if FIRST then
-- if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
recaddr(31 downto abits) := (others => '0');
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
elsif rising_edge(clk) then
case memstate is
when idle =>
S_AXI_GP0_arready <= '0'; S_AXI_GP0_rvalid_i <= '0'; S_AXI_GP0_rlast <= '0';
S_AXI_GP0_awready <= '0'; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '0';
if S_AXI_GP0_arvalid = '1' then
memstate := read1; S_AXI_GP0_arready <= '1';
elsif S_AXI_GP0_awvalid = '1' then
memstate := write1; S_AXI_GP0_awready <= '1';
end if;
when read1 =>
addr:= conv_integer(S_AXI_GP0_araddr(19 downto 0));
len := conv_integer(S_AXI_GP0_arlen);
S_AXI_GP0_arready <= '0'; memstate := read2; rcnt := 23;
when read2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
S_AXI_GP0_rvalid_i <= '1';
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
if (S_AXI_GP0_rready and S_AXI_GP0_rvalid_i) = '1' then
if len = 0 then
S_AXI_GP0_rlast <= '0'; S_AXI_GP0_rvalid_i <= '0';
memstate := idle;
else
addr := addr + 4; len := len - 1;
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
end if;
end if;
for i in 0 to 3 loop
S_AXI_GP0_rdata(i*8+7 downto i*8) <= MEMA(addr+3-i);
end loop;
end if;
when write1 =>
addr:= conv_integer(S_AXI_GP0_awaddr(19 downto 0));
len := conv_integer(S_AXI_GP0_awlen);
S_AXI_GP0_awready <= '0'; memstate := write2; rcnt := 0;
when write2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
memstate := write3;
S_AXI_GP0_wready <= '1';
end if;
when write3 =>
if S_AXI_GP0_wvalid = '1' then
for i in 0 to 3 loop
if S_AXI_GP0_wstrb(i) = '1' then
MEMA(addr+3-i) := S_AXI_GP0_wdata(i*8+7 downto i*8);
end if;
end loop;
if (len = 0) or (S_AXI_GP0_wlast = '1') then
memstate := idle; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '1';
else
addr := addr + 1; len := len - 1;
end if;
end if;
when others =>
end case;
end if;
end process;
S_AXI_GP0_bid <= (others => '0');
S_AXI_GP0_bresp <= (others => '0');
S_AXI_GP0_rresp <= (others => '0');
S_AXI_GP0_rid <= (others => '0');
DDR_addr <= (others => '0');
DDR_ba <= (others => '0');
DDR_cas_n <= '0';
DDR_ck_n <= '0';
DDR_ck_p <= '0';
DDR_cke <= '0';
DDR_cs_n <= '0';
DDR_dm <= (others => '0');
DDR_dq <= (others => '0');
DDR_dqs_n <= (others => '0');
DDR_dqs_p <= (others => '0');
DDR_odt <= '0';
DDR_ras_n <= '0';
DDR_reset_n <= '0';
DDR_we_n <= '0';
FIXED_IO_ddr_vrn <= '0';
FIXED_IO_ddr_vrp <= '0';
FIXED_IO_mio <= (others => '0');
FIXED_IO_ps_clk <= '0';
FIXED_IO_ps_porb <= '0';
FIXED_IO_ps_srstb <= '0';
end architecture STRUCTURE;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3c25/leon3mp.vhd | 1 | 17964 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ssram bus
address : out std_logic_vector(25 downto 1);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
rstoutn : out std_ulogic;
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
-- ssram_adsp_n : out std_ulogic;
-- ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal lclk, lclkout : std_ulogic;
signal dsubre : std_ulogic;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 1,
freq => freq)
port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
rstoutn <= resetn;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram16 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0,
iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP,
bus16 => CFG_SSCTRLP16)
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo);
end generate;
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(25 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- ssram_adv_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adv_n, vcc(0));
-- ssram_adsp_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adsp_n, gnd(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, memi.data(31 downto 0));
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1)
port map (
resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= rxd1; txd1 <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
gpioi.din(i) <= gpio(i);
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP3C25 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc7z020/ahb2axi.vhd | 3 | 9719 | ------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2axi
-- File: ahb2axi.vhd
-- Author: Jiri Gaisler
--
-- AHB/AXI bridge for Zynq S_AXI_GP0 AXI3 slave
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2axi is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
cidsz : integer := 6;
clensz : integer := 4
);
port(
rstn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
m_axi_araddr : out std_logic_vector ( 31 downto 0 );
m_axi_arburst : out std_logic_vector ( 1 downto 0 );
m_axi_arcache : out std_logic_vector ( 3 downto 0 );
m_axi_arid : out std_logic_vector ( cidsz-1 downto 0 );
m_axi_arlen : out std_logic_vector ( clensz-1 downto 0 );
m_axi_arlock : out std_logic_vector (1 downto 0);
m_axi_arprot : out std_logic_vector ( 2 downto 0 );
m_axi_arqos : out std_logic_vector ( 3 downto 0 );
m_axi_arready : in std_logic;
m_axi_arsize : out std_logic_vector ( 2 downto 0 );
m_axi_arvalid : out std_logic;
m_axi_awaddr : out std_logic_vector ( 31 downto 0 );
m_axi_awburst : out std_logic_vector ( 1 downto 0 );
m_axi_awcache : out std_logic_vector ( 3 downto 0 );
m_axi_awid : out std_logic_vector ( cidsz-1 downto 0 );
m_axi_awlen : out std_logic_vector ( clensz-1 downto 0 );
m_axi_awlock : out std_logic_vector (1 downto 0);
m_axi_awprot : out std_logic_vector ( 2 downto 0 );
m_axi_awqos : out std_logic_vector ( 3 downto 0 );
m_axi_awready : in std_logic;
m_axi_awsize : out std_logic_vector ( 2 downto 0 );
m_axi_awvalid : out std_logic;
m_axi_bid : in std_logic_vector ( cidsz-1 downto 0 );
m_axi_bready : out std_logic;
m_axi_bresp : in std_logic_vector ( 1 downto 0 );
m_axi_bvalid : in std_logic;
m_axi_rdata : in std_logic_vector ( 31 downto 0 );
m_axi_rid : in std_logic_vector ( cidsz-1 downto 0 );
m_axi_rlast : in std_logic;
m_axi_rready : out std_logic;
m_axi_rresp : in std_logic_vector ( 1 downto 0 );
m_axi_rvalid : in std_logic;
m_axi_wdata : out std_logic_vector ( 31 downto 0 );
m_axi_wid : out std_logic_vector ( cidsz-1 downto 0 );
m_axi_wlast : out std_logic;
m_axi_wready : in std_logic;
m_axi_wstrb : out std_logic_vector ( 3 downto 0 );
m_axi_wvalid : out std_logic
);
end ;
architecture rtl of ahb2axi is
type bstate_type is (idle, read1, read2, read3, write1, write2, write3);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
m_axi_arlen : std_logic_vector (clensz-1 downto 0 );
m_axi_rdata : std_logic_vector (31 downto 0 );
m_axi_arvalid : std_logic;
m_axi_awvalid : std_logic;
m_axi_rready : std_logic;
m_axi_wstrb : std_logic_vector (3 downto 0 );
m_axi_bready : std_logic;
m_axi_wvalid : std_logic;
m_axi_wlast : std_logic;
m_axi_bresp : std_logic_vector (1 downto 0 );
m_axi_awaddr : std_logic_vector (31 downto 0 );
end record;
signal r, rin : reg_type;
begin
comb: process( rstn, r, ahbsi, m_axi_arready, m_axi_rlast, m_axi_rvalid,
m_axi_awready, m_axi_wready, m_axi_bvalid, m_axi_bresp, m_axi_rdata )
variable v : reg_type;
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector (3 downto 0 );
begin
v := r;
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.haddr := ahbsi.haddr;
if ahbsi.htrans = "10" then
if v.hburst = "000" then v.m_axi_arlen := (others => '0');
else
v.m_axi_arlen := (others => '0');
v.m_axi_arlen(2 downto 0) := not ahbsi.haddr(4 downto 2);
end if;
end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
case r.hsize(1 downto 0) is
when "00" => wstrb := decode(not r.haddr(1 downto 0));
when "01" =>
if r.haddr(1) = '1' then wstrb := "0011"; else wstrb := "1100"; end if;
when others => wstrb := "1111";
end case;
case r.bstate is
when idle =>
if v.hsel = '1' then
if v.hwrite = '1' then v.bstate := write3; v.hready := '1';
else v.bstate := read1; v.m_axi_arvalid := '1';end if;
end if;
when read1 =>
if m_axi_arready = '1' then
v.m_axi_arvalid := '0'; v.bstate := read2; v.m_axi_rready := '1';
end if;
when read2 =>
v.hready := '0';
if m_axi_rvalid = '1' then
v.m_axi_rdata := m_axi_rdata; v.hready := '1';
end if;
if (r.hready = '1') and (ahbsi.htrans /= "11") then
v.bstate := read3;
if v.hsel = '1' then v.hready := '0'; end if;
end if;
if (m_axi_rlast = '1') and (m_axi_rvalid = '1') then
v.bstate := idle; v.m_axi_rready := '0';
end if;
when read3 =>
if (m_axi_rlast = '1') and (m_axi_rvalid = '1') then
v.bstate := idle; v.m_axi_rready := '0';
end if;
when write1 =>
if m_axi_awready = '1' then
v.m_axi_awvalid := '0'; v.bstate := write2; v.m_axi_wvalid := '1';
v.m_axi_wlast := '1';
end if;
when write2 =>
if m_axi_wready = '1' then
v.m_axi_wlast := '0'; v.bstate := idle;
v.m_axi_wvalid := '0'; v.m_axi_wlast := '0';
end if;
when write3 =>
v.m_axi_awvalid := '1';
v.m_axi_awaddr := "0001" & r.haddr(27 downto 2) & "00";
v.m_axi_wstrb := wstrb; v.hwdata := ahbsi.hwdata;
v.bstate := write1;
end case;
if (m_axi_bvalid = '1') and (r.m_axi_bresp = "00") then v.m_axi_bresp := m_axi_bresp; end if;
readdata := (others => '0');
readdata(1 downto 0) := r.m_axi_bresp;
if rstn = '0' then
v.bstate := idle; v.hready := '1';
v.m_axi_arvalid := '0'; v.m_axi_rready := '0';
v.m_axi_rready := '0'; v.m_axi_wstrb := (others => '0');
v.m_axi_bready := '0'; v.m_axi_wvalid := '0'; v.m_axi_wlast := '0';
v.m_axi_bresp := "00"; v.m_axi_awvalid := '0';
end if;
rin <= v;
apbo.prdata <= readdata;
end process;
m_axi_araddr <= "0001" & r.haddr(27 downto 2) & "00";
m_axi_arburst <= "01";
m_axi_arcache <= "0011";
m_axi_arid <= (others => '0');
m_axi_arlen <= r.m_axi_arlen;
m_axi_arlock <= (others => '0');
m_axi_arprot <= "001";
m_axi_arsize <= "010";
m_axi_arvalid <= r.m_axi_arvalid;
m_axi_rready <= r.m_axi_rready;
m_axi_arqos <= (others => '0');
m_axi_awaddr <= r.m_axi_awaddr;
m_axi_awburst <= "01";
m_axi_awcache <= "0011";
m_axi_awid <= (others => '0');
m_axi_awlen <= (others => '0');
m_axi_awlock <= (others => '0');
m_axi_awprot <= "001";
m_axi_awsize <= "010";
m_axi_awvalid <= r.m_axi_awvalid;
m_axi_awqos <= (others => '0');
m_axi_rready <= r.m_axi_rready;
m_axi_wstrb <= r.m_axi_wstrb;
m_axi_bready <= '1';
m_axi_wvalid <= r.m_axi_wvalid;
m_axi_wlast <= r.m_axi_wlast;
m_axi_wdata <= r.hwdata;
m_axi_wid <= (others => '0');
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.m_axi_rdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/unisim/buffer_unisim.vhd | 1 | 2796 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkbuf_xilinx
-- File: clkbuf_xilinx.vhd
-- Author: Marko Isomaki, Jiri GAisler - Gaisler Research
-- Description: Clock buffer generator for Xilinx devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
use unisim.BUFG;
-- pragma translate_on
entity clkbuf_xilinx is
generic(
buftype : integer range 0 to 3 := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkbuf_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal gnd : std_ulogic;
signal x : std_ulogic;
attribute syn_noclockbuf : boolean;
attribute syn_noclockbuf of x : signal is true;
begin
gnd <= '0';
buf0 : if (buftype = 0) or (buftype > 2) generate
x <= i; o <= x;
end generate;
buf1 : if buftype = 1 generate
buf : bufgmux port map(S => gnd, I0 => i, I1 => gnd, O => o);
end generate;
buf2 : if (buftype = 2) generate
buf : bufg port map(I => i, O => o);
end generate;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_xilinx is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml605/testbench.vhd | 1 | 12388 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
use work.ml605.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal ddr3_dm : std_logic_vector(DM_WIDTH-1 downto 0);
signal ddr3_addr : std_logic_vector(ROW_WIDTH-1 downto 0);
signal ddr3_ba : std_logic_vector(BANK_WIDTH-1 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_cs_n : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_odt : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_cke : std_logic_vector(CKE_WIDTH-1 downto 0);
signal ddr3_dqs_p : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_dqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_tdqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_ck_p : std_logic_vector(CK_WIDTH-1 downto 0);
signal ddr3_ck_n : std_logic_vector(CK_WIDTH-1 downto 0);
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
signal emdint : std_logic;
signal egtx_clk : std_logic;
signal gmiiclk_p : std_logic := '1';
signal gmiiclk_n : std_logic := '0';
-- Output signals for LEDs
signal led : std_logic_vector(6 downto 0);
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_dvi, iic_sda_dvi : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal clk_33 : std_ulogic := '0';
signal brdyn : std_ulogic;
---------------------pcie----------------------------------------------
signal cor_sys_reset_n : std_logic := '1';
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
signal rp_sys_clk : std_logic;
signal cor_pci_exp_txn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_txp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_rxn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_rxp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
---------------------pcie end---------------------------------------------
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
gmiiclk_p <= not gmiiclk_p after 4 ns;
gmiiclk_n <= not gmiiclk_n after 4 ns;
clk_33 <= not clk_33 after 15 ns;
rst <= '1', '0' after 200 us;
rstn1 <= not rst;
dsubre <= '0';
urxd <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, disas, dbguart, pclow,
SIM_BYPASS_INIT_CAL)
port map (
reset => rst,
errorn => error,
clk_ref_p => clk200p,
clk_ref_n => clk200n,
-- PROM
address => address(24 downto 1),
data => data(15 downto 0),
romsn => romsn,
oen => oen,
writen => writen,
-- DDR3
ddr3_dq => ddr3_dq,
ddr3_dm => ddr3_dm,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
ddr3_cke => ddr3_cke,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
gmiiclk_p => gmiiclk_p,
gmiiclk_n => gmiiclk_n,
egtx_clk => egtx_clk,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(7 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
emdint => emdint,
etxd => etxdt(7 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- Output signals for LEDs
iic_scl_main => iic_scl_main,
iic_sda_main => iic_sda_main,
dvi_iic_scl => iic_scl_dvi,
dvi_iic_sda => iic_sda_dvi,
tft_lcd_data => tft_lcd_data,
tft_lcd_clk_p => tft_lcd_clk_p,
tft_lcd_clk_n => tft_lcd_clk_n,
tft_lcd_hsync => tft_lcd_hsync,
tft_lcd_vsync => tft_lcd_vsync,
tft_lcd_de => tft_lcd_de,
tft_lcd_reset_b => tft_lcd_reset_b,
clk_33 => clk_33,
sysace_mpa => sysace_mpa,
sysace_mpce => sysace_mpce,
sysace_mpirq => sysace_mpirq,
sysace_mpoe => sysace_mpoe,
sysace_mpwe => sysace_mpwe,
sysace_d => sysace_d,
pci_exp_txp=> cor_pci_exp_txp,
pci_exp_txn=> cor_pci_exp_txn,
pci_exp_rxp=> cor_pci_exp_rxp,
pci_exp_rxn=> cor_pci_exp_rxn,
sys_clk_p=> ep_sys_clk_p,
sys_clk_n=> ep_sys_clk_n,
sys_reset_n=> cor_sys_reset_n,
led => led
);
u1 : ddr3ram
generic map (
width => 64,
abits => 13,
colbits => 10,
rowbits => 13,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 32)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
address(0) <= '0';
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 7)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, egtx_clk);
end generate;
-- spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
-- end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-gr-xc3s-1500/vga_clkgen.vhd | 3 | 2020 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity vga_clkgen is
port (
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
clk25 : in std_logic;
clkm : in std_logic;
clk50 : in std_logic;
clkout : out std_logic
);
end;
architecture struct of vga_clkgen is
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal clk65, clksel : std_logic;
begin
-- 65 MHz clock generator
clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
clk_select : process (clk25, clk50, clk65, sel)
begin
case sel is
when "00" => clksel <= clk25;
when "01" => clksel <= clkm;
when "10" => clksel <= clk50;
when "11" => clksel <= clk65;
when others => clksel <= '0';
end case;
end process;
bufg1 : BUFG port map (I => clksel, O => clkout);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/grlib/amba/amba.in.vhd | 4 | 601 | -- AMBA settings
constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
constant CFG_FPNPEN : integer := CONFIG_AHB_FPNPEN;
constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/irqmp/irqmp.vhd | 1 | 13196 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: irqmp
-- File: irqmp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multi-processor APB interrupt controller. Implements a
-- two-level interrupt controller for 15 interrupts.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
entity irqmp is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
irqmap : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end;
architecture rtl of irqmp is
constant REVISION : integer := 3;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_IRQMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
function IMAP_HIGH return integer is
begin
if irqmap = 0 then
return 0;
elsif eirq /= 0 or irqmap = 2 then
return 31;
end if;
return 15;
end function IMAP_HIGH;
constant IMAP_LOW : integer := 0; -- allow remap of irq line 0
function IMAP_LEN return integer is
begin
if irqmap = 0 then
return 1;
elsif eirq /= 0 then
return 5;
end if;
return 4;
end function IMAP_LEN;
type mask_type is array (0 to ncpu-1) of std_logic_vector(15 downto 1);
type mask2_type is array (0 to ncpu-1) of std_logic_vector(15 downto 0);
type irl_type is array (0 to ncpu-1) of std_logic_vector(3 downto 0);
type irl2_type is array (0 to ncpu-1) of std_logic_vector(4 downto 0);
type irqmap_type is array (IMAP_LOW to (IMAP_HIGH)) of std_logic_vector(IMAP_LEN-1 downto 0);
type reg_type is record
imask : mask_type;
ilevel : std_logic_vector(15 downto 1);
ipend : std_logic_vector(15 downto 1);
iforce : mask_type;
ibroadcast : std_logic_vector(15 downto 1);
irl : irl_type;
cpurst : std_logic_vector(ncpu-1 downto 0);
imap : irqmap_type;
end record;
type ereg_type is record
imask : mask2_type;
ipend : std_logic_vector(15 downto 0);
irl : irl2_type;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
imask => (others => (others => '0')), ilevel => (others => '0'),
ipend => (others => '0'), iforce => (others => (others => '0')),
ibroadcast => (others => '0'), irl => (others => (others => '0')),
cpurst => (others => '0'), imap => (others => (others => '0')));
constant ERES : ereg_type := (
imask => (others => (others => '0')), ipend => (others => '0'),
irl => (others => (others => '0')));
function prioritize(b : std_logic_vector(15 downto 0)) return std_logic_vector is
variable a : std_logic_vector(15 downto 0);
variable irl : std_logic_vector(3 downto 0);
variable level : integer range 0 to 15;
begin
irl := "0000"; level := 0; a := b;
for i in 15 downto 0 loop
level := i;
if a(i) = '1' then exit; end if;
end loop;
irl := conv_std_logic_vector(level, 4);
return(irl);
end;
signal r, rin : reg_type;
signal r2, r2in : ereg_type;
begin
comb : process(rst, r, r2, apbi, irqi)
variable v : reg_type;
variable temp : mask_type;
variable prdata : std_logic_vector(31 downto 0);
variable tmpirq : std_logic_vector(15 downto 0);
variable tmpvar : std_logic_vector(15 downto 1);
variable cpurun : std_logic_vector(ncpu-1 downto 0);
variable v2 : ereg_type;
variable irl2 : std_logic_vector(3 downto 0);
variable ipend2 : std_logic_vector(ncpu-1 downto 0);
variable temp2 : mask2_type;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; v.cpurst := (others => '0');
cpurun := (others => '0'); cpurun(0) := '1';
tmpvar := (others => '0'); ipend2 := (others => '0');
v2 := r2;
-- prioritize interrupts
if eirq /= 0 then
for i in 0 to ncpu-1 loop
temp2(i) := r2.ipend and r2.imask(i);
ipend2(i) := orv(temp2(i));
end loop;
end if;
for i in 0 to ncpu-1 loop
temp(i) := ((r.iforce(i) or r.ipend) and r.imask(i));
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and r.ilevel) & '0');
if v.irl(i) = "0000" then
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and not r.ilevel) & '0');
end if;
end loop;
-- register read
prdata := (others => '0');
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => prdata(15 downto 1) := r.ilevel;
when "001" =>
prdata(15 downto 1) := r.ipend;
if eirq /= 0 then prdata(31 downto 16) := r2.ipend; end if;
when "010" => prdata(15 downto 1) := r.iforce(0);
when "011" =>
when "100" | "101" =>
prdata(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
prdata(19 downto 16) := conv_std_logic_vector(eirq, 4);
for i in 0 to ncpu -1 loop prdata(i) := irqi(i).pwd; end loop;
if ncpu > 1 then
prdata(27) := '1';
case apbi.paddr(4 downto 2) is
when "101" =>
prdata := (others => '0');
prdata(15 downto 1) := r.ibroadcast;
when others =>
end case;
end if;
when others =>
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.imask(i);
if eirq /= 0 then prdata(31 downto 16) := r2.imask(i); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.iforce(i);
end if;
end loop;
when "11" =>
if eirq /= 0 then
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(4 downto 0) := r2.irl(i);
end if;
end loop;
end if;
when others =>
end case;
-- register write
if ((apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' and
(irqmap = 0 or apbi.paddr(9) = '0')) then
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => v.ilevel := apbi.pwdata(15 downto 1);
when "001" => v.ipend := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := apbi.pwdata(31 downto 16); end if;
when "010" => v.iforce(0) := apbi.pwdata(15 downto 1);
when "011" => v.ipend := r.ipend and not apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := r2.ipend and not apbi.pwdata(31 downto 16); end if;
when "100" =>
for i in 0 to ncpu -1 loop v.cpurst(i) := apbi.pwdata(i); end loop;
when others =>
if ncpu > 1 then
case apbi.paddr(4 downto 2) is
when "101" =>
v.ibroadcast := apbi.pwdata(15 downto 1);
when others =>
end case;
end if;
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.imask(i) := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.imask(i) := apbi.pwdata(31 downto 16); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.iforce(i) := (r.iforce(i) or apbi.pwdata(15 downto 1)) and
not apbi.pwdata(31 downto 17);
end if;
end loop;
when others =>
end case;
end if;
-- optionally remap interrupts
irq := (others => '0');
if irqmap /= 0 then
if (apbi.psel(pindex) and apbi.penable and andv(apbi.paddr(9 downto 8))) = '1' then
prdata := (others => '0');
for i in r.imap'range loop
if i/4 = conv_integer(apbi.paddr(4 downto 2)) then
prdata(IMAP_LEN-1+(24-(i mod 4)*8) downto (24-(i mod 4)*8)) := r.imap(i);
if apbi.pwrite = '1' then
v.imap(i) := apbi.pwdata(IMAP_LEN-1+(24-(i mod 4)*8) downto (24-(i mod 4)*8));
end if;
end if;
end loop;
end if;
for i in 0 to IMAP_HIGH loop
if i > NAHBIRQ-1 then
exit;
end if;
if apbi.pirq(i) = '1' then
irq(conv_integer(r.imap(i))) := '1';
end if;
end loop;
else
irq := apbi.pirq;
v.imap := RRES.IMAP;
end if;
-- register new interrupts
for i in 1 to 15 loop
if i > NAHBIRQ-1 then
exit;
end if;
if ncpu = 1 then
v.ipend(i) := v.ipend(i) or irq(i);
else
v.ipend(i) := v.ipend(i) or (irq(i) and not r.ibroadcast(i));
for j in 0 to ncpu-1 loop
tmpvar := v.iforce(j);
tmpvar(i) := tmpvar(i) or (irq(i) and r.ibroadcast(i));
v.iforce(j) := tmpvar;
end loop;
end if;
end loop;
if eirq /= 0 then
for i in 16 to 31 loop
if i > NAHBIRQ-1 then exit; end if;
v2.ipend(i-16) := v2.ipend(i-16) or irq(i);
end loop;
end if;
-- interrupt acknowledge
for i in 0 to ncpu-1 loop
if irqi(i).intack = '1' then
tmpirq := decode(irqi(i).irl);
temp(i) := tmpirq(15 downto 1);
v.iforce(i) := v.iforce(i) and not temp(i);
v.ipend := v.ipend and not ((not r.iforce(i)) and temp(i));
if eirq /= 0 then
if eirq = conv_integer(irqi(i).irl) then
v2.irl(i) := orv(temp2(i)) & prioritize(temp2(i));
if v2.irl(i)(4) = '1' then
v2.ipend(conv_integer(v2.irl(i)(3 downto 0))) := '0';
end if;
end if;
end if;
end if;
end loop;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.imask := RRES.imask; v.iforce := RRES.iforce; v.ipend := RRES.ipend;
if ncpu > 1 then
v.ibroadcast := RRES.ibroadcast;
end if;
if irqmap /= 0 then
for i in r.imap'range loop
v.imap(i) := conv_std_logic_vector(i, IMAP_LEN);
end loop;
end if;
v2.ipend := ERES.ipend; v2.imask := ERES.imask; v2.irl := ERES.irl;
end if;
apbo.prdata <= prdata;
for i in 0 to ncpu-1 loop
irqo(i).irl <= r.irl(i); irqo(i).rst <= r.cpurst(i);
irqo(i).run <= cpurun(i);
irqo(i).rstvec <= (others => '0'); -- Alternate reset vector
irqo(i).iact <= '0';
irqo(i).index <= conv_std_logic_vector(i, 4);
irqo(i).hrdrst <= '0';
end loop;
rin <= v; r2in <= v2;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
dor2regs : if eirq /= 0 generate
regs : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= ERES; end if;
end if;
end process;
end generate;
nor2regs : if eirq = 0 generate
-- r2 <= ((others => "0000000000000000"), "0000000000000000", (others => "00000"));
r2.ipend <= (others => '0');
driveregs: for i in 0 to (ncpu-1) generate
r2.imask(i) <= (others => '0');
r2.irl(i) <= (others => '0');
end generate driveregs;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("irqmp" &
": Multi-processor Interrupt Controller rev " & tost(REVISION) &
", #cpu " & tost(NCPU) & ", eirq " & tost(eirq));
-- pragma translate_on
-- pragma translate_off
cproc : process
begin
assert (irqmap = 0) or (apb_membar_size(pmask) >= 1024)
report "IRQMP: irqmap /= 0 requires pmask to give memory area >= 1024 bytes"
severity failure;
wait;
end process;
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/jtag/bscanregsbd.vhd | 1 | 3158 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: bscanregsbd
-- File: bscanregsbd.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: JTAG boundary scan registers, bi-directional IO
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity bscanregsbd is
generic (
tech: integer:= 0;
nsigs: integer := 8;
enable: integer range 0 to 1 := 1;
hzsup: integer range 0 to 1 := 1
);
port (
pado : out std_logic_vector(nsigs-1 downto 0);
padoen : out std_logic_vector(nsigs-1 downto 0);
padi : in std_logic_vector(nsigs-1 downto 0);
coreo : in std_logic_vector(nsigs-1 downto 0);
coreoen : in std_logic_vector(nsigs-1 downto 0);
corei : out std_logic_vector(nsigs-1 downto 0);
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic -- tri-state output
);
end;
architecture rtl of bscanregsbd is
signal ltdi: std_logic_vector(nsigs downto 0);
begin
disgen: if enable = 0 generate
pado <= coreo;
padoen <= coreoen;
corei <= padi;
tdo <= '0';
ltdi <= (others => '0');
end generate;
engen: if enable /= 0 generate
g: for x in 0 to nsigs-1 generate
r: scanregio
generic map (tech,hzsup)
port map (pado(x),padoen(x),padi(x),coreo(x),coreoen(x),corei(x),
tck,tckn,ltdi(x),ltdi(x+1),bsshft,bscapt,bscapt,bscapt,bsupdi,bsupdo,bsdrive,bshighz);
end generate;
ltdi(0) <= tdi;
tdo <= ltdi(nsigs);
end generate;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmulrue.vhd | 1 | 3779 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulrue
-- File: mmulrue.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulrue is
generic (
position : integer;
entries : integer := 8 );
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type );
end mmulrue;
architecture rtl of mmulrue is
constant entries_log : integer := log2(entries);
type lru_rtype is record
pos : std_logic_vector(entries_log-1 downto 0);
movetop : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
signal c,r : lru_rtype;
begin
p0: process (rst, r, lruei)
variable v : lru_rtype;
variable ov : mmulrue_out_type;
begin
v := r; ov := mmulrue_out_none;
-- #init
if (r.movetop) = '1' then
if (lruei.fromleft) = '0' then
v.pos := lruei.left(entries_log-1 downto 0);
v.movetop := '0';
end if;
elsif (lruei.fromright) = '1' then
v.pos := lruei.right(entries_log-1 downto 0);
v.movetop := not lruei.clear;
end if;
if (lruei.touch and not lruei.clear) = '1' then -- touch request
if (v.pos = lruei.pos(entries_log-1 downto 0)) then -- check
v.movetop := '1';
end if;
end if;
if ((not ASYNC_RESET) and (not RESET_ALL) and (rst = '0')) or (lruei.flush = '1') then
v.pos := conv_std_logic_vector(position, entries_log);
v.movetop := '0';
end if;
--# Drive signals
ov.pos(entries_log-1 downto 0) := r.pos;
ov.movetop := r.movetop;
lrueo <= ov;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r.pos <= conv_std_logic_vector(position, entries_log);
r.movetop <= '0';
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r.pos <= conv_std_logic_vector(position, entries_log);
r.movetop <= '0';
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
end rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/alt/adqsout.vhd | 3 | 8705 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic--;
--dfflo : out std_logic;
--dffhi : out std_logic;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component stratixiii_pseudo_diff_out is
generic (
lpm_type : string := "stratixiii_pseudo_diff_out"
);
port (
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : stratixiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "false",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
pseudo_diff0 : stratixiii_pseudo_diff_out
port map(
i => dqs_reg,
o => dqs_buf,
obar => dqsn_buf
);
-- Outout enable and oct for DQS, DQSN ----------------------------------------------
dqs_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
dqs_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg_n <= not dqsn_oe_reg;
dqsn_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Out buffer (DQS, DQSN) -----------------------------------------------------------
dqs_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqs_buf,
oe => dqs_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqs_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqs_pad,
obar => open
);
dqsn_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqsn_buf,
oe => dqsn_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqsn_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqsn_pad,
obar => open
);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/usb/grusbdc.in.vhd | 3 | 2416 | -- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := CONFIG_GRUSBDC_ENABLE;
constant CFG_GRUSBDC_AIFACE : integer := CONFIG_GRUSBDC_AIFACE;
constant CFG_GRUSBDC_UIFACE : integer := CONFIG_GRUSBDC_UIFACE;
constant CFG_GRUSBDC_DW : integer := CONFIG_GRUSBDC_DW;
constant CFG_GRUSBDC_NEPI : integer := CONFIG_GRUSBDC_NEPI;
constant CFG_GRUSBDC_NEPO : integer := CONFIG_GRUSBDC_NEPO;
constant CFG_GRUSBDC_I0 : integer := CONFIG_GRUSBDC_I0;
constant CFG_GRUSBDC_I1 : integer := CONFIG_GRUSBDC_I1;
constant CFG_GRUSBDC_I2 : integer := CONFIG_GRUSBDC_I2;
constant CFG_GRUSBDC_I3 : integer := CONFIG_GRUSBDC_I3;
constant CFG_GRUSBDC_I4 : integer := CONFIG_GRUSBDC_I4;
constant CFG_GRUSBDC_I5 : integer := CONFIG_GRUSBDC_I5;
constant CFG_GRUSBDC_I6 : integer := CONFIG_GRUSBDC_I6;
constant CFG_GRUSBDC_I7 : integer := CONFIG_GRUSBDC_I7;
constant CFG_GRUSBDC_I8 : integer := CONFIG_GRUSBDC_I8;
constant CFG_GRUSBDC_I9 : integer := CONFIG_GRUSBDC_I9;
constant CFG_GRUSBDC_I10 : integer := CONFIG_GRUSBDC_I10;
constant CFG_GRUSBDC_I11 : integer := CONFIG_GRUSBDC_I11;
constant CFG_GRUSBDC_I12 : integer := CONFIG_GRUSBDC_I12;
constant CFG_GRUSBDC_I13 : integer := CONFIG_GRUSBDC_I13;
constant CFG_GRUSBDC_I14 : integer := CONFIG_GRUSBDC_I14;
constant CFG_GRUSBDC_I15 : integer := CONFIG_GRUSBDC_I15;
constant CFG_GRUSBDC_O0 : integer := CONFIG_GRUSBDC_O0;
constant CFG_GRUSBDC_O1 : integer := CONFIG_GRUSBDC_O1;
constant CFG_GRUSBDC_O2 : integer := CONFIG_GRUSBDC_O2;
constant CFG_GRUSBDC_O3 : integer := CONFIG_GRUSBDC_O3;
constant CFG_GRUSBDC_O4 : integer := CONFIG_GRUSBDC_O4;
constant CFG_GRUSBDC_O5 : integer := CONFIG_GRUSBDC_O5;
constant CFG_GRUSBDC_O6 : integer := CONFIG_GRUSBDC_O6;
constant CFG_GRUSBDC_O7 : integer := CONFIG_GRUSBDC_O7;
constant CFG_GRUSBDC_O8 : integer := CONFIG_GRUSBDC_O8;
constant CFG_GRUSBDC_O9 : integer := CONFIG_GRUSBDC_O9;
constant CFG_GRUSBDC_O10 : integer := CONFIG_GRUSBDC_O10;
constant CFG_GRUSBDC_O11 : integer := CONFIG_GRUSBDC_O11;
constant CFG_GRUSBDC_O12 : integer := CONFIG_GRUSBDC_O12;
constant CFG_GRUSBDC_O13 : integer := CONFIG_GRUSBDC_O13;
constant CFG_GRUSBDC_O14 : integer := CONFIG_GRUSBDC_O14;
constant CFG_GRUSBDC_O15 : integer := CONFIG_GRUSBDC_O15;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-gr-pci-xc2v3000/config.vhd | 1 | 7001 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0034#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000006#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00FE#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/uart/dcom_uart.vhd | 1 | 11463 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom_uart
-- File: dcom_uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART with baud-rate detection.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity dcom_uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end;
architecture rtl of dcom_uart is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBUART, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, stopbit);
type txfsmtype is (idle, data);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
frame : std_ulogic; -- framing error
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(9 downto 0);
thold : std_logic_vector(7 downto 0);
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx data filtering buffer
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(17 downto 0);
brate : std_logic_vector(17 downto 0);
tcnt : std_logic_vector(1 downto 0); -- autobaud counter
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
fedge : std_ulogic; -- rx falling edge
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs := (
rxen => '0', dready => '0', rsempty => '1', tsempty => '1', thempty => '1',
break => '0', ovf => '0', frame => '0', rhold => (others => '0'),
rshift => (others => '0'), tshift => (others => '1'), thold => (others => '0'),
txstate => idle, txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), rxtick => '0', tick => '0',
scaler => "111111111111111011", brate => (others => '1'), tcnt => (others => '0'),
rxf => (others => '0'), fedge => '0');
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti, ui )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(17 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable irxd : std_ulogic;
variable v : uartregs;
begin
v := r;
v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0');
v.rxdb(1) := r.rxdb(0);
-- scaler
if r.tcnt = "11" then scaler := r.scaler - 1;
else scaler := r.scaler + 1; end if;
if r.tcnt /= "11" then
if (r.rxdb(1) and not r.rxdb(0)) = '1' then v.fedge := '1'; end if;
if (r.fedge) = '1' then
v.scaler := scaler;
if (v.scaler(17) and not r.scaler(16)) = '1' then
v.scaler := "111111111111111011";
v.fedge := '0'; v.tcnt := "00";
end if;
end if;
if (r.rxdb(1) and r.fedge and not r.rxdb(0)) = '1' then
if (r.brate(17 downto 4)> r.scaler(17 downto 4)) then
v.brate := r.scaler; v.tcnt := "00";
end if;
v.scaler := "111111111111111011";
if (r.brate(17 downto 4) = r.scaler(17 downto 4)) then
v.tcnt := r.tcnt + 1;
if r.tcnt = "10" then
v.brate := "0000" & r.scaler(17 downto 4);
v.scaler := v.brate; v.rxen := '1';
end if;
end if;
end if;
else
if (r.break and r.rxdb(1)) = '1' then
v.scaler := "111111111111111011";
v.brate := (others => '1'); v.tcnt := "00";
v.break := '0'; v.rxen := '0';
end if;
end if;
if r.rxen = '1' then
v.scaler := scaler;
v.tick := scaler(15) and not r.scaler(15);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- read/write registers
if uarti.read = '1' then v.dready := '0'; end if;
case apbi.paddr(3 downto 2) is
when "01" =>
rdata(9 downto 0) := r.tcnt & r.rxdb(0) & r.frame & '0' & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
when "10" =>
rdata(1 downto 0) := (r.tcnt(1) or r.tcnt(0)) & r.rxen;
when others =>
rdata(17 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.tcnt := apbi.pwdata(1) & apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(17 downto 0);
v.scaler := apbi.pwdata(17 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf(1 downto 0) := r.rxf(0) & ui.rxd; -- meta-stability filter
if ((r.tcnt /= "11") and (r.scaler(0 downto 0) = "1")) or
((r.tcnt = "11") and (r.tick = '1'))
then v.rxf(4 downto 2) := r.rxf(3 downto 1); end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
irxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle and stop bit state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if (r.rxen and (not r.thempty) and r.txtick) = '1' then
v.tshift := '0' & r.thold & '0'; v.txstate := data;
v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmit data frame
if r.txtick = '1' then
v.tshift := '1' & r.tshift(9 downto 1);
if r.tshift(9 downto 1) = "111111110" then
v.tshift(0) := '1'; v.txstate := idle;
end if;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if uarti.write = '1' then
v.thold := uarti.data(7 downto 0); v.thempty := '0';
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb(1) and (not irxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if irxd = '0' then
v.rshift := irxd & r.rshift(7 downto 1); v.rxstate := data;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.rshift := irxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
v.rxstate := stopbit;
end if;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if irxd = '1' then
v.rsempty := '0';
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
else
if r.rshift = "00000000" then
v.break := '1'; -- break
else
v.frame := '1'; -- framing error
end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
when others =>
v.rxstate := idle;
end case;
-- reset operation
if not RESET_ALL and rst = '0' then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.ovf := RES.ovf; v.break := RES.break; v.thempty := RES.thempty;
v.tsempty := RES.tsempty; v.dready := RES.dready; v.fedge := RES.fedge;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.scaler := RES.scaler; v.brate := RES.brate;
v.rxen := RES.rxen; v.tcnt := RES.tcnt;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
end if;
-- update registers
rin <= v;
-- drive outputs
uo.txd <= r.tshift(0);
uo.scaler(31 downto 18) <= (others => '0');
uo.scaler(17 downto 0) <= r.brate;
uo.rtsn <= '0';
uo.rxen <= andv(r.tcnt);
uarto.dready <= r.dready;
uarto.tsempty <= r.tsempty;
uarto.thempty <= r.thempty;
uarto.lock <= r.tcnt(1) and r.tcnt(0);
uarto.enable <= r.rxen;
uarto.data <= r.rhold;
uo.txen <= '1'; uo.flow <= '0';
apbo.prdata <= rdata;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.rxf <= rin.rxf;
end if;
end if;
end process;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-xc3sd-1800/ahbrom.vhd | 3 | 8968 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A033";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE03";
when 16#00069# => romdata <= X"8410A250";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"05248820";
when 16#00077# => romdata <= X"8410A3CD";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000080";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/misc/logan.vhd | 1 | 16981 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: logan
-- File: logan.vhd
-- Author: Kristoffer Carlsson, Gaisler Research
-- Description: On-chip logic analyzer IP core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0; -- Use qualifer bit
usediv : integer range 0 to 1 := 1; -- Enable/disable div counter
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic; -- Synchronous reset
clk : in std_logic; -- System clock
tclk : in std_logic; -- Trace clock
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end logan;
architecture rtl of logan is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LOGAN, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant abits: integer := 8 + log2x(depth/256 - 1);
constant az : std_logic_vector(abits-1 downto 0) := (others => '0');
constant dz : std_logic_vector(dbits-1 downto 0) := (others => '0');
type trig_cfg_type is record
pattern : std_logic_vector(dbits-1 downto 0); -- Pattern to trig on
mask : std_logic_vector(dbits-1 downto 0); -- trigger mask
count : std_logic_vector(5 downto 0); -- match counter
eq : std_ulogic; -- Trig on match or no match?
end record;
type trig_cfg_arr is array (0 to trigl-1) of trig_cfg_type;
type reg_type is record
armed : std_ulogic;
trig_demet : std_ulogic;
trigged : std_ulogic;
fin_demet : std_ulogic;
finished : std_ulogic;
qualifier : std_logic_vector(7 downto 0);
qual_val : std_ulogic;
divcount : std_logic_vector(15 downto 0);
counter : std_logic_vector(abits-1 downto 0);
page : std_logic_vector(3 downto 0);
trig_conf : trig_cfg_arr;
end record;
type trace_reg_type is record
armed : std_ulogic;
arm_demet : std_ulogic;
trigged : std_ulogic;
finished : std_ulogic;
sample : std_ulogic;
divcounter : std_logic_vector(15 downto 0);
match_count : std_logic_vector(5 downto 0);
counter : std_logic_vector(abits-1 downto 0);
curr_tl : integer range 0 to trigl-1;
w_addr : std_logic_vector(abits-1 downto 0);
end record;
signal r_addr : std_logic_vector(13 downto 0);
signal bufout : std_logic_vector(255 downto 0);
signal r_en : std_ulogic;
signal r, rin : reg_type;
signal tr, trin : trace_reg_type;
signal sigreg : std_logic_vector(dbits-1 downto 0);
signal sigold : std_logic_vector(dbits-1 downto 0);
begin
bufout(255 downto dbits) <= (others => '0');
-- Combinatorial process for AMBA clock domain
comb1: process(rstn, apbi, r, tr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable tl : integer range 0 to trigl-1;
variable pattern, mask : std_logic_vector(255 downto 0);
begin
v := r;
rdata := (others => '0'); tl := 0;
pattern := (others => '0'); mask := (others => '0');
-- Two stage synch
v.trig_demet := tr.trigged;
v.trigged := r.trig_demet;
v.fin_demet := tr.finished;
v.finished := r.fin_demet;
if r.finished = '1' then
v.armed := '0';
end if;
r_en <= '0';
-- Read/Write --
if apbi.psel(pindex) = '1' then
-- Write
if apbi.pwrite = '1' and apbi.penable = '1' then
-- Only conf area writeable
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => pattern(31 downto 0) := apbi.pwdata;
when "0001" => pattern(63 downto 32) := apbi.pwdata;
when "0010" => pattern(95 downto 64) := apbi.pwdata;
when "0011" => pattern(127 downto 96) := apbi.pwdata;
when "0100" => pattern(159 downto 128) := apbi.pwdata;
when "0101" => pattern(191 downto 160) := apbi.pwdata;
when "0110" => pattern(223 downto 192) := apbi.pwdata;
when "0111" => pattern(255 downto 224) := apbi.pwdata;
when "1000" => mask(31 downto 0) := apbi.pwdata;
when "1001" => mask(63 downto 32) := apbi.pwdata;
when "1010" => mask(95 downto 64) := apbi.pwdata;
when "1011" => mask(127 downto 96) := apbi.pwdata;
when "1100" => mask(159 downto 128) := apbi.pwdata;
when "1101" => mask(191 downto 160) := apbi.pwdata;
when "1110" => mask(223 downto 192) := apbi.pwdata;
when "1111" => mask(255 downto 224) := apbi.pwdata;
when others => null;
end case;
-- write back updated pattern/mask
v.trig_conf(tl).pattern := pattern(dbits-1 downto 0);
v.trig_conf(tl).mask := mask(dbits-1 downto 0);
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
v.trig_conf(tl).count := apbi.pwdata(6 downto 1);
v.trig_conf(tl).eq := apbi.pwdata(0);
-- arm/reset
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
v.armed := apbi.pwdata(0);
-- Page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
v.page := apbi.pwdata(3 downto 0);
-- Trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
v.counter := apbi.pwdata(abits-1 downto 0);
-- div count
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
v.divcount := apbi.pwdata(15 downto 0);
-- qualifier bit
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
v.qualifier := apbi.pwdata(7 downto 0);
v.qual_val := apbi.pwdata(8);
end if;
end if;
-- end write
-- Read
else
-- Read config/status area
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => rdata := pattern(31 downto 0);
when "0001" => rdata := pattern(63 downto 32);
when "0010" => rdata := pattern(95 downto 64);
when "0011" => rdata := pattern(127 downto 96);
when "0100" => rdata := pattern(159 downto 128);
when "0101" => rdata := pattern(191 downto 160);
when "0110" => rdata := pattern(223 downto 192);
when "0111" => rdata := pattern(255 downto 224);
when "1000" => rdata := mask(31 downto 0);
when "1001" => rdata := mask(63 downto 32);
when "1010" => rdata := mask(95 downto 64);
when "1011" => rdata := mask(127 downto 96);
when "1100" => rdata := mask(159 downto 128);
when "1101" => rdata := mask(191 downto 160);
when "1110" => rdata := mask(223 downto 192);
when "1111" => rdata := mask(255 downto 224);
when others => rdata := (others => '0');
end case;
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
rdata(6 downto 1) := v.trig_conf(tl).count;
rdata(0) := v.trig_conf(tl).eq;
-- status
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
rdata := conv_std_logic_vector(usereg,1) & conv_std_logic_vector(usequal,1) &
r.armed & r.trigged &
conv_std_logic_vector(dbits,8)&
conv_std_logic_vector(depth-1,14)&
conv_std_logic_vector(trigl,6);
-- trace buffer index
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00001" then
rdata(abits-1 downto 0) := tr.w_addr(abits-1 downto 0);
-- page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
rdata(3 downto 0) := r.page;
-- trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
rdata(abits-1 downto 0) := r.counter;
-- divcount
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
rdata(15 downto 0) := r.divcount;
-- qualifier
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
rdata(7 downto 0) := r.qualifier;
rdata(8) := r.qual_val;
end if;
-- Read from trace buffer
else
-- address always r.page & apbi.paddr(14 downto 5)
r_en <= '1';
-- Select word from pattern
case apbi.paddr(4 downto 2) is
when "000" => rdata := bufout(31 downto 0);
when "001" => rdata := bufout(63 downto 32);
when "010" => rdata := bufout(95 downto 64);
when "011" => rdata := bufout(127 downto 96);
when "100" => rdata := bufout(159 downto 128);
when "101" => rdata := bufout(191 downto 160);
when "110" => rdata := bufout(223 downto 192);
when "111" => rdata := bufout(255 downto 224);
when others => rdata := (others => '0');
end case;
end if;
end if; -- end read
end if;
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.finished := '0'; v.trig_demet := '0'; v.fin_demet := '0';
v.counter := (others => '0');
v.divcount := X"0001";
v.qualifier := (others => '0');
v.qual_val := '0';
v.page := (others => '0');
end if;
apbo.prdata <= rdata;
rin <= v;
end process;
-- Combinatorial process for trace clock domain
comb2 : process (rstn, tr, r, sigreg)
variable v : trace_reg_type;
begin
v := tr;
v.sample := '0';
if tr.armed = '0' then
v.trigged := '0'; v.counter := (others => '0'); v.curr_tl := 0; v.match_count := (others => '0');
end if;
-- Synch arm signal
v.arm_demet := r.armed;
v.armed := tr.arm_demet;
if tr.finished = '1' then
v.finished := tr.armed;
end if;
-- Trigger --
if tr.armed = '1' and tr.finished = '0' then
if usediv = 1 then
if tr.divcounter = X"0000" then
v.divcounter := r.divcount-1;
if usequal = 0 or sigreg(conv_integer(r.qualifier)) = r.qual_val then
v.sample := '1';
end if;
else
v.divcounter := v.divcounter - 1;
end if;
else
v.sample := '1';
end if;
if tr.sample = '1' then v.w_addr := tr.w_addr + 1; end if;
if tr.trigged = '1' and tr.sample = '1' then
if tr.counter = r.counter then
v.trigged := '0';
v.sample := '0';
v.finished := '1';
v.counter := (others => '0');
else v.counter := tr.counter + 1; end if;
else
-- match?
if ((sigreg xor r.trig_conf(tr.curr_tl).pattern) and r.trig_conf(tr.curr_tl).mask) = dz then
-- trig on equal
if r.trig_conf(tr.curr_tl).eq = '1' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
else -- not a match
-- trig on inequal
if r.trig_conf(tr.curr_tl).eq = '0' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
end if;
end if;
end if;
-- end trigger
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.sample := '0'; v.finished := '0'; v.arm_demet := '0';
v.curr_tl := 0;
v.counter := (others => '0');
v.divcounter := (others => '0');
v.match_count := (others => '0');
v.w_addr := (others => '0');
end if;
trin <= v;
end process;
-- clk traced signals through register to minimize fan out
inreg: if usereg = 1 generate
process (tclk)
begin
if rising_edge(tclk) then
sigold <= sigreg;
sigreg <= signals;
end if;
end process;
end generate;
noinreg: if usereg = 0 generate
sigreg <= signals;
sigold <= signals;
end generate;
-- Update registers
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
treg: process(tclk)
begin
if rising_edge(tclk) then tr <= trin; end if;
end process;
r_addr <= r.page & apbi.paddr(14 downto 5);
trace_buf : syncram_2p
generic map (tech => memtech, abits => abits, dbits => dbits)
port map (clk, r_en, r_addr(abits-1 downto 0), bufout(dbits-1 downto 0), -- read
tclk, tr.sample, tr.w_addr, sigold); -- write
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end architecture;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/ddr_ireg.vhd | 1 | 3234 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ireg
-- File: ddr_ireg.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DDR input reg with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr_ireg is
generic ( tech : integer; arch : integer := 0; scantest: integer := 0);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
testen: in std_ulogic;
testrst: in std_ulogic);
end;
architecture rtl of ddr_ireg is
begin
inf : if not((is_unisim(tech) = 1) or (tech = axcel) or
(tech = axdsp) or (tech = apa3) or (tech = apa3e) or
(tech = apa3l) or (tech = rhumc) or (tech = igloo2)) generate
inf0 : gen_iddr_reg generic map (scantest,0) port map (Q1, Q2, C1, C2, CE, D, R, S, testen, testrst);
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
axc0 : axcel_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
pa3 : if (tech = apa3) generate
pa0 : apa3_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
pa3e : if (tech = apa3e) generate
pa0 : apa3e_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
pa3l : if (tech = apa3l) generate
pa0 : apa3l_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
igl2 : if (tech = igloo2) generate
igl20 : igloo2_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
xil : if is_unisim(tech) = 1 generate
xil0 : unisim_iddr_reg generic map (tech, arch) port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
rhu : if (tech = rhumc) generate
rhu0: rhumc_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
--pragma translate_off
assert (tech /= easic45) and (tech /= easic90)
report "ddr_ireg: Not supported on eASIC. Use DDR pad instead."
severity failure;
--pragma translate_on
end architecture;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/grlib/amba/ahbctrl.vhd | 1 | 41847 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: ahbctrl
-- File: ahbctrl.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified: Edvin Catovic, Gaisler Research
-- Description: AMBA arbiter, decoder and multiplexer with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity ahbctrl is
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersects
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0; --AMBA compliant data muxing (for hsize > word)
index : integer := 0; --Index for trace print-out
ahbtrace : integer := 0; --AHB trace enable
hwdebug : integer := 0; --Hardware debug
fourgslv : integer := 0 --1=Single slave with single 4 GB bar
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1';
testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0')
);
end;
architecture rtl of ahbctrl is
constant nahbmx : integer := 2**log2(nahbm);
type nmstarr is array (1 to 3) of integer range 0 to nahbmx-1;
type nvalarr is array (1 to 3) of boolean;
type reg_type is record
hmaster : integer range 0 to nahbmx -1;
hmasterd : integer range 0 to nahbmx -1;
hslave : integer range 0 to nahbs-1;
hmasterlock : std_ulogic;
hmasterlockd : std_ulogic;
hready : std_ulogic;
defslv : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
haddr : std_logic_vector(15 downto 2);
cfgsel : std_ulogic;
cfga11 : std_ulogic;
hrdatam : std_logic_vector(31 downto 0);
hrdatas : std_logic_vector(31 downto 0);
beat : std_logic_vector(3 downto 0);
defmst : std_ulogic;
ldefmst : std_ulogic;
lsplmst : integer range 0 to nahbmx-1;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES_r : reg_type := (
hmaster => 0, hmasterd => 0, hslave => 0, hmasterlock => '0',
hmasterlockd => '0', hready => '1', defslv => '0',
htrans => HTRANS_IDLE, hsize => (others => '0'),
haddr => (others => '0'), cfgsel => '0', cfga11 => '0',
hrdatam => (others => '0'), hrdatas => (others => '0'),
beat => (others => '0'), defmst => '0', ldefmst => '0',
lsplmst => 0);
constant RES_split : std_logic_vector(0 to nahbmx-1) := (others => '0');
constant primst : std_logic_vector(NAHBMST downto 0) := conv_std_logic_vector(mprio, NAHBMST+1);
type l0_type is array (0 to 15) of std_logic_vector(2 downto 0);
type l1_type is array (0 to 7) of std_logic_vector(3 downto 0);
type l2_type is array (0 to 3) of std_logic_vector(4 downto 0);
type l3_type is array (0 to 1) of std_logic_vector(5 downto 0);
type tztab_type is array (0 to 15) of std_logic_vector(2 downto 0);
--returns the index number of the highest priority request
--signal in the two lsb bits when indexed with a 4-bit
--request vector with the highest priority signal on the
--lsb. the returned msb bit indicates if a request was
--active ('1' = no request active corresponds to "0000")
constant tztab : tztab_type := ("100", "000", "001", "000",
"010", "000", "001", "000",
"011", "000", "001", "000",
"010", "000", "001", "000");
--calculate the number of the highest priority request signal(up to 64
--requests are supported) in vect_in using a divide and conquer
--algorithm. The lower the index in the vector the higher the priority
--of the signal. First 4-bit slices are indexed in tztab and the msb
--indicates whether there is an active request or not. Then the resulting
--3 bit vectors are compared in pairs (the one corresponding to (3:0) with
--(7:4), (11:8) with (15:12) and so on). If the least significant of the two
--contains an active signal a '0' is added to the msb side (the vector
--becomes one bit wider at each level) to the next level to indicate that
--there are active signals in the lower nibble of the two. Otherwise
--the msb is removed from the vector corresponding to the higher nibble
--and "10" is added if it does not contain active requests and "01" if
--does contain active signals. Thus the msb still indicates if the new
--slice contains active signals and a '1' is added if it is the higher
--part. This results in a 6-bit vector containing the index number
--of the highest priority master in 5:0 if bit 6 is '0' otherwise
--no master requested the bus.
function tz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(63 downto 0);
variable l0 : l0_type;
variable l1 : l1_type;
variable l2 : l2_type;
variable l3 : l3_type;
variable l4 : std_logic_vector(6 downto 0);
variable bci_lsb, bci_msb : std_logic_vector(3 downto 0);
variable bco_lsb, bco_msb : std_logic_vector(2 downto 0);
variable sel : std_logic;
begin
vect := (others => '1');
vect(vect_in'length-1 downto 0) := vect_in;
-- level 0
for i in 0 to 7 loop
bci_lsb := vect(8*i+3 downto 8*i);
bci_msb := vect(8*i+7 downto 8*i+4);
--lookup the highest priority request in each nibble
bco_lsb := tztab(conv_integer(bci_lsb));
bco_msb := tztab(conv_integer(bci_msb));
--select which of two nibbles contain the highest priority ACTIVE
--signal, and forward the corresponding vector to the next level
sel := bco_lsb(2);
if sel = '0' then l1(i) := '0' & bco_lsb;
else l1(i) := bco_msb(2) & not bco_msb(2) & bco_msb(1 downto 0); end if;
end loop;
-- level 1
for i in 0 to 3 loop
sel := l1(2*i)(3);
--select which of two 8-bit vectors contain the
--highest priority ACTIVE signal. the msb set at the previous level
--for each 8-bit slice determines this
if sel = '0' then l2(i) := '0' & l1(2*i);
else
l2(i) := l1(2*i+1)(3) & not l1(2*i+1)(3) & l1(2*i+1)(2 downto 0);
end if;
end loop;
-- level 2
for i in 0 to 1 loop
--16-bit vectors, the msb set at the previous level for each 16-bit
--slice determines the higher priority slice
sel := l2(2*i)(4);
if sel = '0' then l3(i) := '0' & l2(2*i);
else
l3(i) := l2(2*i+1)(4) & not l2(2*i+1)(4) & l2(2*i+1)(3 downto 0);
end if;
end loop;
--level 3
--32-bit vectors, the msb set at the previous level for each 32-bit
--slice determines the higher priority slice
if l3(0)(5) = '0' then l4 := '0' & l3(0);
else l4 := l3(1)(5) & not l3(1)(5) & l3(1)(4 downto 0); end if;
return(l4);
end;
--invert the bit order of the hbusreq signals located in vect_in
--since the highest hbusreq has the highest priority but the
--algorithm in tz has the highest priority on lsb
function lz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(vect_in'length-1 downto 0);
variable vect2 : std_logic_vector(vect_in'length-1 downto 0);
begin
vect := vect_in;
for i in vect'right to vect'left loop
vect2(i) := vect(vect'left-i);
end loop;
return(tz(vect2));
end;
-- Find next master:
-- * 2 arbitration policies: fixed priority or round-robin
-- * Fixed priority: priority is fixed, highest index has highest priority
-- * Round-robin: arbiter maintains circular queue of masters
-- * (master 0, master 1, ..., master (nahbmx-1)). First requesting master
-- * in the queue is granted access to the bus and moved to the end of the queue.
-- * splitted masters are not granted
-- * bus is re-arbited when current owner does not request the bus,
-- or when it performs non-burst accesses
-- * fix length burst transfers will not be interrupted
-- * incremental bursts should assert hbusreq until last access
procedure selmast(r : in reg_type;
msto : in ahb_mst_out_vector;
rsplit : in std_logic_vector(0 to nahbmx-1);
mast : out integer range 0 to nahbmx-1;
defmst : out std_ulogic) is
variable nmst : nmstarr;
variable nvalid : nvalarr;
variable rrvec : std_logic_vector(nahbmx*2-1 downto 0);
variable zcnt : std_logic_vector(log2(nahbmx)+1 downto 0);
variable hpvec : std_logic_vector(nahbmx-1 downto 0);
variable zcnt2 : std_logic_vector(log2(nahbmx) downto 0);
begin
nvalid(1 to 3) := (others => false); nmst(1 to 3) := (others => 0);
mast := r.hmaster;
defmst := '0';
if nahbm = 1 then
mast := 0;
elsif rrobin = 0 then
hpvec := (others => '0');
for i in 0 to nahbmx-1 loop
--masters which have received split are not granted
if ((rsplit(i) = '0') or (split = 0)) then
hpvec(i) := msto(i).hbusreq;
end if;
end loop;
--check if any bus requests are active (nvalid(2) set to true)
--and determine the index (zcnt2) of the highest priority master
zcnt2 := lz(hpvec)(log2(nahbmx) downto 0);
if zcnt2(log2(nahbmx)) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(not (zcnt2(log2(nahbmx)-1 downto 0)));
--find the default master number
for i in 0 to nahbmx-1 loop
if not ((nmst(3) = defmast) and nvalid(3)) then
nmst(3) := i; nvalid(3) := true;
end if;
end loop;
else
rrvec := (others => '0');
--mask requests up to and including current master. Concatenate
--an unmasked request vector above the masked vector. Otherwise
--the rules are the same as for fixed priority
for i in 0 to nahbmx-1 loop
if ((rsplit(i) = '0') or (split = 0)) then
if (i <= r.hmaster) then rrvec(i) := '0';
else rrvec(i) := msto(i).hbusreq; end if;
rrvec(nahbmx+i) := msto(i).hbusreq;
end if;
end loop;
--find the next master uzing tz which gives priority to lower
--indexes
zcnt := tz(rrvec)(log2(nahbmx)+1 downto 0);
--was there a master requesting the bus?
if zcnt(log2(nahbmx)+1) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(zcnt(log2(nahbmx)-1 downto 0));
--if no other master is requesting the bus select the current one
nmst(3) := r.hmaster; nvalid(3) := true;
--check if any masters configured with higher priority are requesting
--the bus
if mprio /= 0 then
for i in 0 to nahbm-1 loop
if (((rsplit(i) = '0') or (split = 0)) and (primst(i) = '1')) then
if msto(i).hbusreq = '1' then nmst(1) := i; nvalid(1) := true; end if;
end if;
end loop;
end if;
end if;
--select the next master. If for round robin a high priority master
--(mprio) requested the bus if nvalid(1) is true. Otherwise
--if nvalid(2) is true at least one master was requesting the bus
--and the one with highest priority was selected. If none of these
--were true then the default master is selected (nvalid(3) true)
for i in 1 to 3 loop
if nvalid(i) then mast := nmst(i); exit; end if;
end loop;
--if no master was requesting the bus and split is enabled
--then select builtin dummy master which only does
--idle transfers
if (not (nvalid(1) or nvalid(2))) and (split /= 0) then
defmst := orv(rsplit);
end if;
end;
constant MIMAX : integer := log2x(nahbmx) - 1;
constant SIMAX : integer := log2x(nahbs) - 1;
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(ioaddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(iomask, 12);
constant CFGAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgaddr, 12);
constant CFGMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgmask, 12);
constant FULLPNP : boolean := (fpnpen /= 0);
signal r, rin : reg_type;
signal rsplit, rsplitin : std_logic_vector(0 to nahbmx-1);
-- pragma translate_off
signal lmsti : ahb_mst_in_type;
signal lslvi : ahb_slv_in_type;
-- pragma translate_on
begin
comb : process(rst, msto, slvo, r, rsplit, testen, testrst, scanen, testoen, testsig)
variable v : reg_type;
variable nhmaster: integer range 0 to nahbmx -1;
variable hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
variable hsel : std_logic_vector(0 to 31); -- slave select
variable hmbsel : std_logic_vector(0 to NAHBAMR-1);
variable nslave : natural range 0 to 31;
variable vsplit : std_logic_vector(0 to nahbmx-1);
variable bnslave : std_logic_vector(3 downto 0);
variable area : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable defslv : std_ulogic;
variable cfgsel : std_ulogic;
variable hresp : std_logic_vector(1 downto 0);
variable hrdata : std_logic_vector(AHBDW-1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable arb : std_ulogic;
variable hconfndx : integer range 0 to 7;
variable vslvi : ahb_slv_in_type;
variable defmst : std_ulogic;
variable tmpv : std_logic_vector(0 to nahbmx-1);
begin
v := r; hgrant := (others => '0'); defmst := '0';
haddr := msto(r.hmaster).haddr;
nhmaster := r.hmaster;
--determine if bus should be rearbitrated. This is done if the current
--master is not performing a locked transfer and if not in the middle
--of burst
arb := '0';
if (r.hmasterlock or r.ldefmst) = '0' then
case msto(r.hmaster).htrans is
when HTRANS_IDLE => arb := '1';
when HTRANS_NONSEQ =>
case msto(r.hmaster).hburst is
when HBURST_SINGLE => arb := '1';
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when HTRANS_SEQ =>
case msto(r.hmaster).hburst is
when HBURST_WRAP4 | HBURST_INCR4 => if (fixbrst = 1) and (r.beat(1 downto 0) = "11") then arb := '1'; end if;
when HBURST_WRAP8 | HBURST_INCR8 => if (fixbrst = 1) and (r.beat(2 downto 0) = "111") then arb := '1'; end if;
when HBURST_WRAP16 | HBURST_INCR16 => if (fixbrst = 1) and (r.beat(3 downto 0) = "1111") then arb := '1'; end if;
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when others => arb := '0';
end case;
end if;
if (split /= 0) then
for i in 0 to nahbmx-1 loop
tmpv(i) := (msto(i).htrans(1) or (msto(i).hbusreq)) and not rsplit(i) and not r.ldefmst;
end loop;
if (r.defmst and orv(tmpv)) = '1' then arb := '1'; end if;
end if;
--rearbitrate bus with selmast. If not arbitrated one must
--ensure that the dummy master is selected for locked splits.
if (arb = '1') then
selmast(r, msto, rsplit, nhmaster, defmst);
elsif (split /= 0) then
defmst := r.defmst;
end if;
-- slave decoding
hsel := (others => '0'); hmbsel := (others => '0');
if fourgslv = 0 then
for i in 0 to nahbs-1 loop
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
case area is
when "10" =>
if ((ioen = 0) or ((IOAREA and IOMSK) /= (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(31 downto 20) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when "11" =>
if ((ioen /= 0) and ((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(19 downto 8) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when others =>
end case;
end loop;
end loop;
else
-- There is only one slave on the bus. The slave has only one bar, which
-- maps 4 GB address space.
hsel(0) := '1'; hmbsel(0) := '1';
end if;
if r.defmst = '1' then hsel := (others => '0'); end if;
bnslave(0) := hsel(1) or hsel(3) or hsel(5) or hsel(7) or
hsel(9) or hsel(11) or hsel(13) or hsel(15);
bnslave(1) := hsel(2) or hsel(3) or hsel(6) or hsel(7) or
hsel(10) or hsel(11) or hsel(14) or hsel(15);
bnslave(2) := hsel(4) or hsel(5) or hsel(6) or hsel(7) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
bnslave(3) := hsel(8) or hsel(9) or hsel(10) or hsel(11) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
nslave := conv_integer(bnslave(SIMAX downto 0));
if ((((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK)) and (ioen /= 0))
or ((IOAREA = haddr(31 downto 20)) and (ioen = 0))) and
((CFGAREA and CFGMSK) = (haddr(19 downto 8) and CFGMSK))
and (cfgmask /= 0)
then cfgsel := '1'; hsel := (others => '0');
else cfgsel := '0'; end if;
if (nslave = 0) and (hsel(0) = '0') and (cfgsel = '0') then defslv := '1';
else defslv := '0'; end if;
if r.defmst = '1' then
cfgsel := '0'; defslv := '1';
end if;
-- error response on undecoded area
v.hready := '0';
hready := slvo(r.hslave).hready; hresp := slvo(r.hslave).hresp;
if r.defslv = '1' then
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle error in case of unimplemented slave access
hresp := HRESP_ERROR; hready := r.hready; v.hready := not r.hready;
end if;
end if;
if acdm = 0 then
hrdata := slvo(r.hslave).hrdata;
else
hrdata := ahbselectdata(slvo(r.hslave).hrdata, r.haddr(4 downto 2), r.hsize);
end if;
if cfgmask /= 0 then
-- plug&play information for masters
if FULLPNP then hconfndx := conv_integer(r.haddr(4 downto 2)); else hconfndx := 0; end if;
if (r.haddr(10 downto MIMAX+6) = zero32(10 downto MIMAX+6)) and (FULLPNP or (r.haddr(4 downto 2) = "000"))
then v.hrdatam := msto(conv_integer(r.haddr(MIMAX+5 downto 5))).hconfig(hconfndx);
else v.hrdatam := (others => '0'); end if;
-- plug&play information for slaves
if (r.haddr(10 downto SIMAX+6) = zero32(10 downto SIMAX+6)) and
(FULLPNP or (r.haddr(4 downto 2) = "000") or (r.haddr(4) = '1'))
then v.hrdatas := slvo(conv_integer(r.haddr(SIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
else v.hrdatas := (others => '0'); end if;
-- device ID, library build and potentially debug information
if r.haddr(10 downto 4) = "1111111" then
if hwdebug = 0 or r.haddr(3 downto 2) = "00" then
v.hrdatas(15 downto 0) := conv_std_logic_vector(LIBVHDL_BUILD, 16);
v.hrdatas(31 downto 16) := conv_std_logic_vector(devid, 16);
elsif r.haddr(3 downto 2) = "01" then
for i in 0 to nahbmx-1 loop v.hrdatas(i) := msto(i).hbusreq; end loop;
else
for i in 0 to nahbmx-1 loop v.hrdatas(i) := rsplit(i); end loop;
end if;
end if;
if r.cfgsel = '1' then
hrdata := (others => '0');
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle read/write respons
hresp := HRESP_OKAY; hready := r.hready; v.hready := not r.hready;
end if;
if r.cfga11 = '0' then hrdata := ahbdrivedata(r.hrdatam);
else hrdata := ahbdrivedata(r.hrdatas); end if;
end if;
end if;
--degrant all masters when split occurs for locked access
if (r.hmasterlockd = '1') then
if (hresp = HRESP_RETRY) or ((split /= 0) and (hresp = HRESP_SPLIT)) then
nhmaster := r.hmaster;
end if;
if split /= 0 then
if hresp = HRESP_SPLIT then
v.ldefmst := '1'; defmst := '1';
v.lsplmst := nhmaster;
end if;
end if;
end if;
if split /= 0 and r.ldefmst = '1' then
if rsplit(r.lsplmst) = '0' then
v.ldefmst := '0'; defmst := '0';
end if;
end if;
if (split = 0) or (defmst = '0') then hgrant(nhmaster) := '1'; end if;
-- latch active master and slave
if hready = '1' then
v.hmaster := nhmaster; v.hmasterd := r.hmaster;
v.hsize := msto(r.hmaster).hsize;
v.hslave := nslave; v.defslv := defslv;
v.hmasterlockd := r.hmasterlock;
if (split = 0) or (r.defmst = '0') then v.htrans := msto(r.hmaster).htrans;
else v.htrans := HTRANS_IDLE; end if;
v.cfgsel := cfgsel;
v.cfga11 := msto(r.hmaster).haddr(11);
v.haddr := msto(r.hmaster).haddr(15 downto 2);
if (msto(r.hmaster).htrans = HTRANS_NONSEQ) or (msto(r.hmaster).htrans = HTRANS_IDLE) then
v.beat := "0001";
elsif (msto(r.hmaster).htrans = HTRANS_SEQ) then
if (fixbrst = 1) then v.beat := r.beat + 1; end if;
end if;
if (split /= 0) then v.defmst := defmst; end if;
end if;
--assign new hmasterlock, v.hmaster is used because if hready
--then master can have changed, and when not hready then the
--previous master will still be selected
v.hmasterlock := msto(v.hmaster).hlock or (r.hmasterlock and not hready);
--if the master asserting hlock received a SPLIT/RETRY response
--to the previous access then disregard the current lock request.
--the bus will otherwise be locked when the previous access is
--retried instead of treating hlock as coupled to the next access.
--use hmasterlockd to keep the bus locked for SPLIT/RETRY to locked
--accesses.
if v.hmaster = r.hmasterd and slvo(r.hslave).hresp(1) = '1' then
if r.hmasterlockd = '0' then
v.hmasterlock := '0'; v.hmasterlockd := '0';
end if;
end if;
-- split support
vsplit := (others => '0');
if SPLIT /= 0 then
vsplit := rsplit;
if slvo(r.hslave).hresp = HRESP_SPLIT then vsplit(r.hmasterd) := '1'; end if;
for i in 0 to nahbs-1 loop
for j in 0 to nahbmx-1 loop
vsplit(j) := vsplit(j) and not slvo(i).hsplit(j);
end loop;
end loop;
end if;
-- interrupt merging
hirq := (others => '0');
if disirq = 0 then
for i in 0 to nahbs-1 loop hirq := hirq or slvo(i).hirq; end loop;
for i in 0 to nahbm-1 loop hirq := hirq or msto(i).hirq; end loop;
end if;
if (split = 0) or (r.defmst = '0') then
vslvi.haddr := haddr;
vslvi.htrans := msto(r.hmaster).htrans;
vslvi.hwrite := msto(r.hmaster).hwrite;
vslvi.hsize := msto(r.hmaster).hsize;
vslvi.hburst := msto(r.hmaster).hburst;
vslvi.hready := hready;
vslvi.hprot := msto(r.hmaster).hprot;
-- vslvi.hmastlock := msto(r.hmaster).hlock;
vslvi.hmastlock := r.hmasterlock;
vslvi.hmaster := conv_std_logic_vector(r.hmaster, 4);
vslvi.hsel := hsel(0 to NAHBSLV-1);
vslvi.hmbsel := hmbsel;
vslvi.hirq := hirq;
else
vslvi := ahbs_in_none;
vslvi.hready := hready;
vslvi.hirq := hirq;
end if;
if acdm = 0 then
vslvi.hwdata := msto(r.hmasterd).hwdata;
else
vslvi.hwdata := ahbselectdata(msto(r.hmasterd).hwdata, r.haddr(4 downto 2), r.hsize);
end if;
vslvi.testen := testen;
vslvi.testrst := testrst;
vslvi.scanen := scanen and testen;
vslvi.testoen := testoen;
vslvi.testin := testen & (scanen and testen) & testsig;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.hmaster := RES_r.hmaster; v.hmasterlock := RES_r.hmasterlock;
vsplit := (others => '0');
v.htrans := RES_r.htrans; v.defslv := RES_r.defslv;
v.hslave := RES_r.hslave; v.cfgsel := RES_r.cfgsel;
v.defmst := RES_r.defmst; v.ldefmst := RES_r.ldefmst;
end if;
-- drive master inputs
msti.hgrant <= hgrant;
msti.hready <= hready;
msti.hresp <= hresp;
msti.hrdata <= hrdata;
msti.hirq <= hirq;
msti.testen <= testen;
msti.testrst <= testrst;
msti.scanen <= scanen and testen;
msti.testoen <= testoen;
msti.testin <= testen & (scanen and testen) & testsig;
-- drive slave inputs
slvi <= vslvi;
-- pragma translate_off
--drive internal signals to bus monitor
lslvi <= vslvi;
lmsti.hgrant <= hgrant;
lmsti.hready <= hready;
lmsti.hresp <= hresp;
lmsti.hrdata <= hrdata;
lmsti.hirq <= hirq;
-- pragma translate_on
if split = 0 then v.ldefmst := '0'; v.lsplmst := 0; end if;
rin <= v; rsplitin <= vsplit;
end process;
reg0 : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES_r;
end if;
end if;
if (split = 0) then r.defmst <= '0'; end if;
end process;
splitreg : if SPLIT /= 0 generate
reg1 : process(clk)
begin
if rising_edge(clk) then
rsplit <= rsplitin;
if RESET_ALL and rst = '0' then
rsplit <= RES_split;
end if;
end if;
end process;
end generate;
nosplitreg : if SPLIT = 0 generate
rsplit <= (others => '0');
end generate;
-- pragma translate_off
ahblog : if ahbtrace /= 0 generate
log : process (clk)
variable hwrite : std_logic;
variable hsize : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable hmaster : std_logic_vector(3 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hwdata, hrdata : std_logic_vector(127 downto 0);
variable mbit, bitoffs : integer;
variable t : integer;
begin
if rising_edge(clk) then
if htrans(1)='1' and lmsti.hready='0' and (lmsti.hresp="01") then
if hwrite = '1' then
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " write " & tost(mbit/8) & " bytes [" & tost(lslvi.hwdata(mbit-1+bitoffs downto bitoffs)) & "] - ERROR!");
else
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " read " & tost(mbit/8) & " bytes [" & tost(lmsti.hrdata(mbit-1+bitoffs downto bitoffs)) & "] - ERROR!");
end if;
end if;
if ((htrans(1) and lmsti.hready) = '1') and (lmsti.hresp = "00") then
mbit := 2**conv_integer(hsize)*8;
bitoffs := 0;
if mbit < ahbdw then
bitoffs := mbit * conv_integer(haddr(log2(ahbdw/8)-1 downto conv_integer(hsize)));
bitoffs := lslvi.hwdata'length-mbit-bitoffs;
end if;
t := (now/1 ns);
if hwrite = '1' then
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " write " & tost(mbit/8) & " bytes [" & tost(lslvi.hwdata(mbit-1+bitoffs downto bitoffs)) & "]");
else
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " read " & tost(mbit/8) & " bytes [" & tost(lmsti.hrdata(mbit-1+bitoffs downto bitoffs)) & "]");
end if;
end if;
if lmsti.hready = '1' then
hwrite := lslvi.hwrite;
hsize := lslvi.hsize;
haddr := lslvi.haddr;
htrans := lslvi.htrans;
hmaster := lslvi.hmaster;
end if;
end if;
end process;
end generate;
mon0 : if enbusmon /= 0 generate
mon : ahbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
hmstdisable => hmstdisable,
hslvdisable => hslvdisable,
arbdisable => arbdisable,
nahbm => nahbm,
nahbs => nahbs)
port map(
rst => rst,
clk => clk,
ahbmi => lmsti,
ahbmo => msto,
ahbsi => lslvi,
ahbso => slvo,
err => open);
end generate;
diag : process
type ahbsbank_type is record
start : std_logic_vector(31 downto 8);
stop : std_logic_vector(31 downto 8);
io : std_ulogic;
end record;
type ahbsbanks_type is array (0 to 3) of ahbsbank_type;
type memmap_type is array (0 to nahbs-1) of ahbsbanks_type;
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable area : std_logic_vector( 1 downto 0);
variable vendori : integer;
variable iosize, tmp : integer;
variable iounit : string(1 to 5) := " byte";
variable memtype : string(1 to 9);
variable iostart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable cfgstart : std_logic_vector(11 downto 0) := CFGAREA and CFGMSK;
variable L1 : line := new string'("");
variable S1 : string(1 to 255);
variable memmap : memmap_type;
begin
wait for 2 ns;
if debug = 0 then wait; end if;
if debug > 0 then
k := 0; mask := IOMSK;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
print("ahbctrl: AHB arbiter/multiplexer rev 1");
if ioen /= 0 then
print("ahbctrl: Common I/O area at " & tost(iostart) & "00000, " & tost(2**k) & " Mbyte");
else
print("ahbctrl: Common I/O area disabled");
end if;
print("ahbctrl: AHB masters: " & tost(nahbm) & ", AHB slaves: " & tost(nahbs));
if cfgmask /= 0 then
print("ahbctrl: Configuration area at " & tost(iostart & cfgstart) & "00, 4 kbyte");
else
print("ahbctrl: Configuration area disabled");
end if;
end if;
for i in 0 to nahbm-1 loop
vendor := msto(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := msto(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
print("ahbctrl: mst" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
end if;
for j in 1 to NAHBIR-1 loop
assert (msto(i).hconfig(j) = zx or FULLPNP or ccheck = 0 or cfgmask = 0)
report "AHB master " & tost(i) & " propagates non-zero user defined PnP data, " &
"but AHBCTRL full PnP decoding has not been enabled (check fpnpen VHDL generic)"
severity warning;
end loop;
assert (msto(i).hindex = i) or (icheck = 0)
report "AHB master index error on master " & tost(i) &
". Detected index value " & tost(msto(i).hindex) severity failure;
else
for j in 0 to NAHBCFG-1 loop
assert (msto(i).hconfig(j) = zx or ccheck = 0)
report "AHB master " & tost(i) & " appears to be disabled, " &
"but the master config record is not driven to zero " &
"(check vendor ID or drive unused bus index with appropriate values)."
severity warning;
end loop;
end if;
end loop;
if nahbm < NAHBMST then
for i in nahbm to NAHBMST-1 loop
for j in 0 to NAHBCFG-1 loop
assert (msto(i).hconfig(j) = zx or ccheck = 0)
report "AHB master " & tost(i) & " is outside the range of " &
"decoded master indexes but the master config record is not driven to zero " &
"(check nahbm VHDL generic)."
severity warning;
end loop;
end loop;
end if;
for i in 0 to nahbs-1 loop
vendor := slvo(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := slvo(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "ahbctrl: slv" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
end if;
for j in 1 to NAHBIR-1 loop
assert (slvo(i).hconfig(j) = zx or FULLPNP or ccheck = 0 or cfgmask = 0)
report "AHB slave " & tost(i) & " propagates non-zero user defined PnP data, " &
"but AHBCTRL full PnP decoding has not been enabled (check fpnpen VHDL generic)."
severity warning;
end loop;
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
mask := slvo(i).hconfig(j)(15 downto 4);
memmap(i)(j mod NAHBIR).start := (others => '0');
memmap(i)(j mod NAHBIR).stop := (others => '0');
memmap(i)(j mod NAHBIR).io := slvo(i).hconfig(j)(0);
if (mask /= "000000000000" or fourgslv = 1) then
case area is
when "01" =>
when "10" =>
k := 0;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
if debug > 1 then
std.textio.write(L1, "ahbctrl: memory at " &
tost(slvo(i).hconfig(j)(31 downto 20) and mask) &
"00000, size "& tost(2**k) & " Mbyte");
if slvo(i).hconfig(j)(16) = '1' then
std.textio.write(L1, string'(", cacheable"));
end if;
if slvo(i).hconfig(j)(17) = '1' then
std.textio.write(L1, string'(", prefetch"));
end if;
std.textio.writeline(OUTPUT, L1);
end if;
memmap(i)(j mod NAHBIR).start(31 downto 20) := slvo(i).hconfig(j)(31 downto 20);
memmap(i)(j mod NAHBIR).start(31 downto 20) :=
(slvo(i).hconfig(j)(31 downto 20) and mask);
memmap(i)(j mod NAHBIR).start(19 downto 8) := (others => '0');
memmap(i)(j mod NAHBIR).stop := memmap(i)(j mod NAHBIR).start + 2**(k+12) - 1;
-- Be verbose if an address with bits set outside the area
-- selected by the mask is encountered
assert ((slvo(i).hconfig(j)(31 downto 20) and not mask) = zero32(11 downto 0)) report
"AHB slave " & tost(i) & " may decode an area larger than intended. Bar " &
tost(j mod NAHBIR) & " will have base address " &
tost(slvo(i).hconfig(j)(31 downto 20) and mask) &
"00000, the intended base address may have been " &
tost(slvo(i).hconfig(j)(31 downto 20)) & "00000"
severity warning;
when "11" =>
if ioen /= 0 then
k := 0;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
memmap(i)(j mod NAHBIR).start := iostart & (slvo(i).hconfig(j)(31 downto 20) and
slvo(i).hconfig(j)(15 downto 4));
memmap(i)(j mod NAHBIR).stop := memmap(i)(j mod NAHBIR).start + 2**k - 1;
if debug > 1 then
iosize := 256 * 2**k; iounit(1) := ' ';
if (iosize > 1023) then
iosize := iosize/1024; iounit(1) := 'k';
end if;
print("ahbctrl: I/O port at " & tost(iostart &
((slvo(i).hconfig(j)(31 downto 20)) and slvo(i).hconfig(j)(15 downto 4))) &
"00, size "& tost(iosize) & iounit);
end if;
assert ((slvo(i).hconfig(j)(31 downto 20) and not mask) = zero32(11 downto 0)) report
"AHB slave " & tost(i) & " may decode an I/O area larger than intended. Bar " &
tost(j mod NAHBIR) & " will have base address " &
tost(iostart & (slvo(i).hconfig(j)(31 downto 20) and mask)) &
"00, the intended base address may have been " &
tost(iostart & slvo(i).hconfig(j)(31 downto 20)) & "00"
severity warning;
else
assert false report
"AHB slave " & tost(i) & " maps bar " & tost(j mod NAHBIR) &
" to the IO area, but this AHBCTRL has been configured with VHDL generic ioen = 0"
severity warning;
end if;
when others =>
end case;
end if;
end loop;
assert (slvo(i).hindex = i) or (icheck = 0)
report "AHB slave index error on slave " & tost(i) &
". Detected index value " & tost(slvo(i).hindex) severity failure;
if mcheck /= 0 then
for j in 0 to i loop
for k in memmap(i)'range loop
if memmap(i)(k).stop /= zero32(memmap(i)(k).stop'range) then
for l in memmap(j)'range loop
assert ((memmap(i)(k).start >= memmap(j)(l).stop) or
(memmap(i)(k).stop <= memmap(j)(l).start) or
(mcheck /= 2 and (memmap(i)(k).io xor memmap(j)(l).io) = '1') or
(i = j and k = l))
report "AHB slave " & tost(i) & " bank " & tost(k) &
" intersects with AHB slave " & tost(j) & " bank " & tost(l)
severity failure;
end loop;
end if;
end loop;
end loop;
end if;
else
for j in 0 to NAHBCFG-1 loop
assert (slvo(i).hconfig(j) = zx or ccheck = 0)
report "AHB slave " & tost(i) & " appears to be disabled, " &
"but the slave config record is not driven to zero " &
"(check vendor ID or drive unused bus index with appropriate values)."
severity warning;
end loop;
end if;
end loop;
if nahbs < NAHBSLV then
for i in nahbs to NAHBSLV-1 loop
for j in 0 to NAHBCFG-1 loop
assert (slvo(i).hconfig(j) = zx or ccheck = 0)
report "AHB slave " & tost(i) & " is outside the range of " &
"decoded slave indexes but the slave config record is not driven to zero " &
"(check nahbs VHDL generic)."
severity warning;
end loop;
end loop;
end if;
wait;
end process;
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-jopdesign-ep1c12/config.vhd | 1 | 7407 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 2;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 2;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 0 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 1;
constant CFG_SRCTRL_PROMWS : integer := (3);
constant CFG_SRCTRL_RAMWS : integer := (2);
constant CFG_SRCTRL_IOWS : integer := (0);
constant CFG_SRCTRL_RMW : integer := 1;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := (19);
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ahb2mig_7series_ddr2.vhd | 1 | 25561 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_7series_ddr2_dq16_ad13_ba3
-- File: ahb2mig_7series_ddr2.vhd
-- Author: Pascal Trotta
--
-- This is a AHB-2.0 interface for the Xilinx Virtex-7 MIG. (adapted from
-- ahb2mig_7series to work with 16-bit ddr2 memories)
-- Notes: - works only with 32-bit bus
-- - does not replicate output data
-- - does not support MIG interface model
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.all;
use gaisler.ahb2mig_7series_pkg.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library std;
use std.textio.all;
entity ahb2mig_7series_ddr2_dq16_ad13_ba3 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_reset_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end ;
architecture rtl of ahb2mig_7series_ddr2_dq16_ad13_ba3 is
type bstate_type is (idle, start, read_cmd, read_data, read_wait, read_output, write_cmd, write_burst);
constant maxburst : integer := 8;
constant maxmigcmds : integer := 3;
constant wrsteps : integer := log2(32);
constant wrmask : integer := log2(32/8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd : std_logic_vector(2 downto 0);
cmd_en : std_logic;
wr_en : std_logic;
wr_end : std_logic;
cmd_count : unsigned(31 downto 0);
wr_count : unsigned(31 downto 0);
rd_count : unsigned(31 downto 0);
hready : std_logic;
hwrite : std_logic;
hwdata_burst : std_logic_vector(128*maxmigcmds-1 downto 0);
mask_burst : std_logic_vector(16*maxmigcmds-1 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(31 downto 0);
haddr_start : std_logic_vector(31 downto 0);
haddr_offset : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
int_buffer : unsigned(128*maxmigcmds-1 downto 0);
rd_buffer : unsigned(128*maxmigcmds-1 downto 0);
wdf_data_buffer : std_logic_vector(127 downto 0);
wdf_mask_buffer : std_logic_vector(15 downto 0);
migcommands : integer;
nxt : std_logic;
maxrburst : integer;
end record;
type mig_in_type is record
app_addr : std_logic_vector(26 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
app_wdf_data : std_logic_vector(127 downto 0);
app_wdf_end : std_logic;
app_wdf_mask : std_logic_vector(15 downto 0);
app_wdf_wren : std_logic;
end record;
type mig_out_type is record
app_rd_data : std_logic_vector(127 downto 0);
app_rd_data_end : std_logic;
app_rd_data_valid : std_logic;
app_rdy : std_logic;
app_wdf_rdy : std_logic;
end record;
signal rin, r, rnxt, rnxtin : reg_type;
signal migin : mig_in_type;
signal migout,migoutraw : mig_out_type;
component mig is
port (
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig;
begin
comb: process( rst_n_syn, r, rin, ahbsi, migout )
-- Design temp variables
variable v,vnxt : reg_type;
variable writedata : std_logic_vector(255 downto 0);
variable wmask : std_logic_vector(AHBDW/4-1 downto 0);
variable shift_steps : natural;
variable hrdata_shift_steps : natural;
variable steps_write : unsigned(31 downto 0);
variable shift_steps_write : natural;
variable shift_steps_write_mask : natural;
variable startaddress : unsigned(v.haddr'length-1 downto 0);
variable start_address : std_logic_vector(v.haddr'length-1 downto 0);
variable step_offset : unsigned(steps_write'length-1 downto 0);
variable haddr_offset : unsigned(steps_write'length-1 downto 0);
begin
-- Make all register visible for the statemachine
v := r; vnxt := rnxt;
-- workout the start address in AHB2MIG buffer based upon
startaddress := resize(unsigned(unsigned(ahbsi.haddr(ahbsi.haddr'left-5 downto 4)) & "000"),startaddress'length);
-- Adjust offset in memory buffer
start_address := std_logic_vector(startaddress);
-- Workout local offset to be able to adust for warp-around
haddr_offset := unsigned(r.haddr_start) - unsigned(unsigned(r.haddr_offset(r.haddr_offset'length-1 downto 4))&"0000");
step_offset := resize(unsigned(haddr_offset(5 downto 4)&"00"),step_offset'length);
-- Fetch AMBA Commands
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready and not ahbsi.htrans(0)) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
vnxt.cmd_count:= (others => '0');
vnxt.wr_count := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.hrdata := (others => '0');
-- Clear old pointers and MIG command signals
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
-- Hold info regarding transaction and execute
vnxt.hburst := ahbsi.hburst;
vnxt.hwrite := ahbsi.hwrite;
vnxt.hsize := ahbsi.hsize;
vnxt.hmaster := ahbsi.hmaster;
vnxt.hready := '0';
vnxt.htrans := ahbsi.htrans;
vnxt.bstate := start;
vnxt.haddr := start_address;
vnxt.haddr_start := ahbsi.haddr;
vnxt.haddr_offset := ahbsi.haddr;
vnxt.cmd(2 downto 0) := (others => '0');
vnxt.cmd(0) := not ahbsi.hwrite;
if (r.bstate = idle) then vnxt.nxt := '0'; else vnxt.nxt := '1'; end if;
-- Clear some old stuff
vnxt.int_buffer := (others => '0');
vnxt.rd_buffer := (others => '0');
vnxt.wdf_data_buffer := (others => '0');
vnxt.wdf_mask_buffer := (others => '0');
end if;
case r.bstate is
when idle =>
-- Clear old pointers and MIG command signals
v.cmd := (others => '0');
v.cmd_en := '0';
v.wr_en := '0';
v.wr_end := '0';
v.hready := '1';
v.hwrite := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.rd_count := (others => '0');
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hready := '1';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.wr_count := (others => '0');
vnxt.cmd_count := (others => '0');
-- Check if this is a single or burst transfer (and not a BUSY transfer)
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
-- Hold info regarding transaction and execute
v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.htrans := ahbsi.htrans;
v.bstate := start;
v.haddr := start_address;
v.haddr_start := ahbsi.haddr;
v.haddr_offset := ahbsi.haddr;
v.cmd := (others => '0');
v.cmd(0) := not ahbsi.hwrite;
end if;
when start =>
v.migcommands := nbrmigcmds16(r.hwrite,r.hsize,ahbsi.htrans,step_offset,AHBDW);
-- Check if a write command shall be issued to the DDR3 memory
if r.hwrite = '1' then
wmask := (others => '0');
writedata := (others => '0');
if ((ahbsi.htrans /= HTRANS_SEQ) or ((ahbsi.htrans = HTRANS_SEQ) and (r.rd_count > 0) and (r.rd_count <= maxburst))) then
-- work out how many steps we need to shift the input
steps_write := ahbselectdatanoreplicastep16(r.haddr_start(7 downto 2),r.hsize(2 downto 0)) + step_offset;
shift_steps_write := to_integer(shift_left(steps_write,wrsteps));
shift_steps_write_mask := to_integer(shift_left(steps_write,wrmask));
-- generate mask for complete burst (only need to use addr[3:0])
wmask := ahbselectdatanoreplicamask(r.haddr_start(6 downto 0),r.hsize(2 downto 0));
v.mask_burst := r.mask_burst or std_logic_vector(shift_left(resize(unsigned(wmask), r.mask_burst'length),shift_steps_write_mask));
-- fetch all wdata before write to memory can begin (only supports upto 128bits i.e. addr[4:0]
writedata(AHBDW-1 downto 0) := ahbselectdatanoreplica(ahbsi.hwdata(AHBDW-1 downto 0),r.haddr_start(4 downto 0),r.hsize(2 downto 0));
v.hwdata_burst := r.hwdata_burst or std_logic_vector(shift_left(resize(unsigned(writedata),v.hwdata_burst'length),shift_steps_write));
v.haddr_start := ahbsi.haddr;
end if;
-- Check if this is a cont burst longer than internal buffer
if (ahbsi.htrans = HTRANS_SEQ) then
if (r.rd_count < maxburst-1) then
v.hready := '1';
else
v.hready := '0';
end if;
if (r.rd_count >= maxburst) then
if (r.htrans = HTRANS_SEQ) then
v.bstate := write_cmd;
end if;
v.htrans := ahbsi.htrans;
end if;
else
v.bstate := write_cmd;
v.htrans := ahbsi.htrans;
end if;
-- Else issue a read command when ready
else
if migout.app_rdy = '1' and migout.app_wdf_rdy = '1' then
v.cmd := "001";
v.bstate := read_cmd;
v.htrans := ahbsi.htrans;
v.cmd_count := to_unsigned(0,v.cmd_count'length);
end if;
end if;
when write_cmd =>
-- Check if burst has ended due to max size burst
if (ahbsi.htrans /= HTRANS_SEQ) then
v.htrans := (others => '0');
end if;
-- Stop when addr and write command is accepted by mig
if (r.wr_count >= r.migcommands) and (r.cmd_count >= r.migcommands) then
if (r.htrans /= HTRANS_SEQ) then
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
else
v.bstate := idle;
end if;
else -- Cont burst and work out new offset for next write command
v.bstate := write_burst;
v.hready := '1';
end if;
end if;
when write_burst =>
v.bstate := start;
v.hready := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
end if;
when read_cmd =>
v.hready := '0';
v.rd_count := (others => '0');
-- stop when read command is accepted ny mig.
if (r.cmd_count >= r.migcommands) then
v.bstate := read_data;
--v.int_buffer := (others => '0');
end if;
when read_data =>
-- We are not ready yet so issue a read command to the memory controller
v.hready := '0';
-- If read data is valid store data in buffers
if (migout.app_rd_data_valid = '1') then
v.rd_count := r.rd_count + 1;
-- Viviado seems to misinterpet the following shift construct and
-- therefore changed to a if-else statement
--v.int_buffer := r.int_buffer or shift_left( resize(unsigned(migout.app_rd_data),r.int_buffer'length),
-- to_integer(shift_left(r.rd_count,9)));
if (r.rd_count = 0) then
v.int_buffer(127 downto 0) := unsigned(migout.app_rd_data);
elsif (r.rd_count = 1) then
v.int_buffer(255 downto 128) := unsigned(migout.app_rd_data);
end if;
end if;
if (r.rd_count >= r.migcommands) then
v.rd_buffer := r.int_buffer;
v.bstate := read_output;
v.rd_count := to_unsigned(0,v.rd_count'length);
end if;
when read_output =>
-- Data is fetched from memory and ready to be transfered
v.hready := '1';
-- uses the "wr_count" signal to keep track of number of bytes output'd to AHB
-- Select correct 32bit output
v.hrdata := ahbselectdatanoreplicaoutput16(r.haddr_start(7 downto 0),r.wr_count,r.hsize,r.rd_buffer,r.wr_count,false);
-- Count number of bytes send
v.wr_count := r.wr_count + 1;
-- Set maximum read burst depending on the starting address offset
case r.haddr_start(3 downto 2) is
when "01" => v.maxrburst := 7;
when "10" => v.maxrburst := 6;
when "11" => v.maxrburst := 5;
when others => v.maxrburst := 8;
end case;
-- Check if this was the last transaction
if (r.wr_count >= v.maxrburst-1) then
v.bstate := read_wait;
end if;
-- Check if transfer was interrupted or no burst
if (ahbsi.htrans = HTRANS_IDLE) or ((ahbsi.htrans = HTRANS_NONSEQ) and (r.wr_count < maxburst)) then
v.bstate := read_wait;
v.wr_count := (others => '0');
v.rd_count := (others => '0');
v.cmd_count := (others => '0');
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
end if;
end if;
when read_wait =>
if ((r.wr_count >= v.maxrburst) and (ahbsi.htrans = HTRANS_SEQ)) then
v.hready := '0';
v.bstate := start;
v.haddr_start := ahbsi.haddr;
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
else
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
else
v.bstate := idle;
v.hready := '1';
end if;
end if;
when others =>
v.bstate := idle;
end case;
if ((ahbsi.htrans /= HTRANS_SEQ) and (r.bstate = start)) then
v.hready := '0';
end if;
if rst_n_syn = '0' then
v.bstate := idle; v.hready := '1'; v.cmd_en := '0'; v.wr_en := '0'; v.wr_end := '0'; v.maxrburst := maxburst;
end if;
rin <= v;
rnxtin <= vnxt;
end process;
ahbso.hready <= r.hready;
ahbso.hresp <= "00";
ahbso.hrdata <= ahbdrivedata(r.hrdata);
migin.app_addr <= r.haddr(26 downto 2) & "00";
migin.app_cmd <= r.cmd;
migin.app_en <= r.cmd_en;
migin.app_wdf_data <= r.wdf_data_buffer;
migin.app_wdf_end <= r.wr_end;
migin.app_wdf_mask <= r.wdf_mask_buffer;
migin.app_wdf_wren <= r.wr_en;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
-- Copy variables into registers (Default values)
r <= rin;
rnxt <= rnxtin;
-- add extra pipe-stage for read data
migout <= migoutraw;
-- IDLE Clear
if ((r.bstate = idle) or (r.bstate = read_wait)) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
if (r.bstate = write_burst) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= to_unsigned(1,r.rd_count'length);
end if;
-- Read AHB write data
if (r.bstate = start) and (r.hwrite = '1') then
r.rd_count <= r.rd_count + 1;
end if;
-- Write command repsonse
if r.bstate = write_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
if (r.wr_count < 1 ) then
r.wr_en <= '1';
r.wr_end <= '1';
r.wdf_mask_buffer <= not r.mask_burst(15 downto 0);
r.wdf_data_buffer <= r.hwdata_burst(127 downto 0);
end if;
if (migoutraw.app_wdf_rdy = '1') and (r.wr_en = '1' ) then
if (r.wr_count = 0) then
r.wdf_mask_buffer <= not r.mask_burst(31 downto 16);
r.wdf_data_buffer <= r.hwdata_burst(255 downto 128);
elsif (r.wr_count = 1) then --to support 3 migcmds
r.wdf_mask_buffer <= not r.mask_burst(47 downto 32);
r.wdf_data_buffer <= r.hwdata_burst(383 downto 256);
else
r.wdf_mask_buffer <= not r.mask_burst(31 downto 16);
r.wdf_data_buffer <= r.hwdata_burst(255 downto 128);
end if;
r.wr_count <= r.wr_count + 1;
if (r.wr_count >= r.migcommands - 1) then
r.wr_en <= '0';
r.wr_end <= '0';
end if;
end if;
end if;
-- Burst Write Wait
if r.bstate = write_burst then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
-- Read command repsonse
if r.bstate = read_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
end if;
end if;
end process;
MCB_inst : mig
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
sys_clk_i => sys_clk_i,
clk_ref_i => clk_ref_i,
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/inferred/ddr_phy_inferred.vhd | 1 | 16488 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_ddr_phy
-- File: ddr_phy_inferred.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Modified: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR PHY (simulation only)
------------------------------------------------------------------------------
--###################################################################################
-- Generic DDR1 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb: in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic -- Mobile DDR enable
);
end;
architecture rtl of generic_ddr_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
signal ckl: std_logic_vector(nclk-1 downto 0);
signal ckel: std_logic_vector(ncs-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl, rst)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' or rst='0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
-- For mobile SDRAM, force Cke high during reset and reset-delay,
-- For regular SDRAM, force Cke low
-- also disable outgoing clock until we have achieved PLL lock
mobgen: if mobile > 1 generate
ckel <= cke or (cke'range => not locked);
end generate;
nmobgen: if mobile < 2 generate
ckel <= cke and (cke'range => locked);
end generate;
ckl <= ck and (ck'range => lockl);
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2, ncs => ncs, nclk => nclk,
resync => 2 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => open,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba,
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => ckel,
odt => (others => '0'),
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ckl
);
end;
--###################################################################################
-- Generic DDR2 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
eightbanks: integer := 0; abits: integer := 14;
cben: integer := 0; chkbits: integer := 8;
nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic; -- system clock returned
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0); -- ddr odt
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector (2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of generic_ddr2_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr2 without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2+EIGHTBANKS, ncs => ncs, nclk => nclk,
resync => 0 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => ddr_odt,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba(1+eightbanks downto 0),
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => cke,
odt => odt,
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ck(nclk-1 downto 0)
);
end;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/i2c_master/vhdl/clkdiv-e.vhd | 1 | 1393 | --------------------------------------------------------------------------------
-- Company: vienna university of technology
-- Engineer: mario faschang
-- Create Date: 14:24:06 11/30/2009
-- Module Name: ClkDiv - rtl
-- Project Name: i2c master controller
-- Description: * This module generates the necessary frequency for all the
-- other modules to finally result in an I2C-Bus SCL-frequency
-- of 100 kHz or 400 kHz.
-- * F100_400_n_i: defines either 100 kHz or 400 kHz as final I2C-
-- Bus SCL-frequency. (Which results in an Clk_o frequency of
-- 200 kHz or 800 kHz)
-- * Clk_i is the input-port for the fast oscillation-frequency
-- * Reset_i is an assynchronous reset input
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ClkDiv is
-- Generates 200 / 800 kHz Clk
Generic (DividerWidth_g : integer range 4 to 32);
Port ( F100_400_n_i : in STD_LOGIC;
Divider800_i : in std_logic_vector(DividerWidth_g-1 downto 0);
Clk_i : in STD_LOGIC;
Reset_i : in STD_LOGIC;
Clk_o : out STD_LOGIC);
end ClkDiv;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/core/vhdl/dmem-ams.vhd | 1 | 4921 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
-------------------------------------------------------------------------------
-- Don't use the VHDL component provided in the package memory_components but
-- use a local component definition. For more explanation see at the end of
-- this file.
--
--library work;
--use work.memory_components.all;
entity DMem is
port (
ram_rstn : in std_logic;
ram_clk : in std_logic;
ram_addr : in std_logic_vector( 6 downto 0);
ram_cen : in std_logic;
ram_dout : out std_logic_vector(15 downto 0);
ram_din : in std_logic_vector(15 downto 0);
ram_wen : in std_logic_vector( 1 downto 0)
);
end DMem;
architecture struct of DMem is
component sram128x8
generic (
TimingChecksOn : BOOLEAN := True
);
port (
CS : in std_logic;
EN : in std_logic;
RD : in std_logic;
WR : in std_logic;
NRST : in std_logic;
AD : in std_logic_VECTOR(6 downto 0);
DI : in std_logic_VECTOR(7 downto 0);
DO : out std_logic_VECTOR(7 downto 0)
);
end component;
-- private
signal ram_addr_s : std_logic_vector(6 downto 0);
signal ram_cen_s : std_logic;
signal ram_din_s : std_logic_vector(15 downto 0);
signal ram_wen_s : std_logic_vector(1 downto 0);
signal RD_s : std_logic;
begin
ram_addr_s <= ram_addr;-- after 2 ns;
ram_cen_s <= ram_cen ;-- after 2 ns;
ram_din_s <= ram_din ;-- after 2 ns;
ram_wen_s <= ram_wen ;-- after 2 ns;
-- RD_s must be '0' during writes
RD_s <= (not ram_cen_s) and and_reduce(ram_wen_s);
sram128x8_0: sram128x8
generic map (
TimingChecksON => false
)
port map (
CS => ram_clk,
EN => '0',
RD => RD_s,
WR => "not"(ram_wen_s(0)),
NRST => ram_rstn,
AD => ram_addr_s,
DI => ram_din_s (7 downto 0),
DO => ram_dout(7 downto 0)
);
sram128x8_1: sram128x8
generic map (
TimingChecksON => false
)
port map (
CS => ram_clk,
EN => '0',
RD => RD_s,
WR => "not"(ram_wen_s(1)),
NRST => ram_rstn,
AD => ram_addr_s,
DI => ram_din_s (15 downto 8),
DO => ram_dout(15 downto 8)
);
end struct;
-------------------------------------------------------------------------------
-- The sram128x8 vital_mem architecture in sram128x8.vhd does rigorous timing
-- checks which lead to an enormous amount of simulation messages and the
-- memory doesn't work. Most of these messages deal with hold time violations
-- during functional simulation, because AD, DI, RD and WR change at the very
-- same time as the edges of CS.
--
-- I tried a few ways to get around these problems.
--
-- 1) Delay AD, DI, RD and WR:
-- ---------------------------
-- Therefore I've added the four ram_*_s signals and assigned the inputs with a
-- delay of 2ns. The time was chosen to be most time delays specified in
-- sram128x8.vhd.
--
-- I didn't try yet, but these delayed assignements using "after" are most
-- probably not allowed in synthesis. Therefore I tried another way.
--
-- 2) Set sram128x8 generic TimingChecksON to false via configuration:
-- -------------------------------------------------------------------
-- I found that the RAM model has a generic TimingChecksON which can be used to
-- disable the timing checks. Unfortunately, the component definition in the
-- package memory_components only exposes the ports but no generics. Therefore
-- I used a configuration (see below) to set this generic.
--
-- This was a bit tricky because I didn't find how to use a configuration for
-- an inner module, except when simulating a top-level configuration. Therefore
-- I created Core_tb_amsram_cfg in ./tb/core_tb-amsram-cfg-c.vhd. Unfortunately
-- it was not possibel to "configure into the Core Verilog module", therefore I
-- created another Verilog configuration CoreAMSRAM in
-- ./verilog/core-amsram-c.v. This finaly used DMem_TimingChecksOFF_cfg.
--
-- Then another problem arised: the generic was set, but the port map as
-- specified above in the instantiations was removed, i.e. the instances were
-- not connected.
--
-- 3) Use local VHDL component:
-- ----------------------------
-- The above problem could be solved by adding a port map to
-- DMem_TimingChecksOFF_cfg (more precisely: adding it two times because both
-- instances have slightly different connections). This was too tedious, so I
-- just added a local VHDL component here which includes the generic
-- TimingChecksON. All configurations were removed.
--
-- Now simulations behaves well.
--
--configuration DMem_TimingChecksOFF_cfg of DMem is
-- for struct
-- for all : sram128x8
-- use entity work.sram128x8(vital_mem)
-- generic map (
-- TimingChecksON => false
-- );
-- end for;
-- end for;
--end DMem_TimingChecksOFF_cfg;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/vhdl_packs/config-noclkgate-p.vhd | 1 | 113 | package Config is
constant CfgClkGating : boolean := false;
end Config;
package body Config is
end Config;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682/chll/out/reconflogic-wrapmax6682-instance.vhd | 1 | 1712 | -- Automatically generated: write_netlist -wrapapp -vhdl -instance reconflogic-wrapmax6682-instance.vhd
MyReconfigLogic_0: MyReconfigLogic
port map (
Reset_n_i => Reset_n_s,
Clk_i => Clk_i,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i,
I2C_Busy_i => I2C_Busy,
I2C_DataIn_o => I2C_DataIn,
I2C_DataOut_i => I2C_DataOut,
I2C_Divider800_o => I2C_Divider800,
I2C_ErrAckParam_o => I2C_ErrAckParam,
I2C_Error_i => I2C_Error,
I2C_F100_400_n_o => I2C_F100_400_n,
I2C_FIFOEmpty_i => I2C_FIFOEmpty,
I2C_FIFOFull_i => I2C_FIFOFull,
I2C_FIFOReadNext_o => I2C_FIFOReadNext,
I2C_FIFOWrite_o => I2C_FIFOWrite,
I2C_ReadCount_o => I2C_ReadCount,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n,
I2C_StartProcess_o => I2C_StartProcess,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
ReconfModuleIRQs_o => ReconfModuleIRQs_s,
SPI_CPHA_o => SPI_CPHA,
SPI_CPOL_o => SPI_CPOL,
SPI_DataIn_o => SPI_DataIn,
SPI_DataOut_i => SPI_DataOut,
SPI_FIFOEmpty_i => SPI_FIFOEmpty,
SPI_FIFOFull_i => SPI_FIFOFull,
SPI_LSBFE_o => SPI_LSBFE,
SPI_ReadNext_o => SPI_ReadNext,
SPI_SPPR_SPR_o => SPI_SPPR_SPR,
SPI_Transmission_i => SPI_Transmission,
SPI_Write_o => SPI_Write,
ReconfModuleIn_i => ReconfModuleIn_s,
ReconfModuleOut_o => ReconfModuleOut_s,
I2C_Errors_i => I2C_Errors,
PerAddr_i => Per_Addr_s,
PerDIn_i => Per_DIn_s,
PerWr_i => Per_Wr_s,
PerEn_i => Per_En_s,
CfgIntfDOut_o => CfgIntf_DOut_s,
ParamIntfDOut_o => ParamIntf_DOut_s
);
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/extadc/chll/out/extadc-extract-intersynth-trfsm0-bitstream.vhd | 1 | 937 | constant TRFSM0Length : integer := 820;
constant TRFSM0Cfg : std_logic_vector(TRFSM0Length-1 downto 0) := "0001000101000101001000100000110001000001111110000000000000001111100000000000000011111000000000000000111110000000000000001111100000000000000011111000000000000000111110000000000000001111100000000000000000000000010010000000010000000000000001010000110000100000000010000010100001000101101000011000010010000000010000000010100010010000010001011010001010001000100101000101001011111000000000000000000000001111100000000000000000000000111110000000000000000000000011111000000000000000000000000000110000110000001100010110100001100101010000001000010100000001100101000100001100001000001111100000000000000000000000000000111000100000010000110001011010000011100010000100000100000101111011111000000000000000000000000000001111100000000000000000000000000000111110000000000000000000000000000000000000111110000000000000000000000000000000000000";
| gpl-2.0 |
doxygen/doxygen | examples/mux.vhdl | 37 | 860 | -------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architecture definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682mean/chll/out/max6682mean-fsm-sensorfsm-wrapper.vhd | 2 | 3285 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 10,
NumRows2 => 10,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7310p16s16/tb/adt7310p16s16_tb.vhd | 1 | 12182 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.BusMasters.all;
entity ADT7310P16S16_tb is
end ADT7310P16S16_tb;
architecture behavior of ADT7310P16S16_tb is
component ADT7310P16S16
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
ADT7310CS_n_o : out std_logic;
SPI_Data_i : in std_logic_vector(7 downto 0);
SPI_Write_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Data_o : out std_logic_vector(7 downto 0);
SPI_FIFOFull_i : in std_logic;
SPI_FIFOEmpty_i : in std_logic;
SPI_Transmission_i : in std_logic;
SPICounterPreset_i : in std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
PeriodCounterPreset_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
SPI_CPOL_o : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_LSBFE_o : out std_logic
);
end component;
component adt7310_model
port (
SCLK_i : in std_logic;
DOUT_o : out std_logic;
DIN_i : in std_logic;
CS_n_i : in std_logic;
CT_n_o : out std_logic;
INT_n_o : out std_logic;
Temp_i : in real);
end component;
component ExtNames
port (
SPIFSM_Done : out std_logic
);
end component;
-- component generics
constant DataWidth : integer := 8;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Enable_i : std_logic;
signal CpuIntr_o : std_logic;
signal ADT7310CS_n_o : std_logic;
signal SPI_Data_i : std_logic_vector(7 downto 0);
signal SPI_Write_o : std_logic;
signal SPI_ReadNext_o : std_logic;
signal SPI_Data_o : std_logic_vector(7 downto 0);
signal SPI_FIFOFull_i : std_logic;
signal SPI_FIFOEmpty_i : std_logic;
signal SPI_Transmission_i : std_logic;
signal SPICounterPreset_i : std_logic_vector(15 downto 0);
signal Threshold_i : std_logic_vector(15 downto 0);
signal PeriodCounterPreset_i : std_logic_vector(15 downto 0);
signal SensorValue_o : std_logic_vector(15 downto 0);
signal SensorValue_real : real;
signal SPI_CPOL_o : std_logic;
signal SPI_CPHA_o : std_logic;
signal SPI_LSBFE_o : std_logic;
signal SPI_SPPR_SPR_o : std_logic_vector(7 downto 0);
-- look into the ADT7310P16S16 app
-- alias SPIFSM_Done_i is << signal .adt7310_tb.DUT.SPIFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the SPIFSM_Done_i signal.
signal SPIFSM_Done_i : std_logic; -- directly from inside SPI_FSM
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- SPIFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal SPIFSM_Done_d : std_logic; -- sightly delayed
signal SPIFSM_Done_a : std_logic; -- SPIFSM_Done_i and SPIFSM_Done_d
-- ADT7310 component ports
signal SCLK_s : std_logic := '1';
signal DOUT_s : std_logic;
signal DIN_s : std_logic := '0';
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
-- SPI Master generics
constant SPPRWidth : integer := 4;
constant SPRWidth : integer := 4;
constant SPIFIFOReadWidth : integer := 4;
constant SPIFIFOWriteWidth : integer := 4;
-- SPI Master component ports
signal SPI_ScanEnable_s : std_logic := '0';
signal SPI_ScanClk_s : std_logic := '0';
signal SPI_ScanDataIn_s : std_logic := '0';
signal SPI_ScanDataOut_s : std_logic := '0';
-- The timer has to wait for 240ms. With a 16 bit resolution, the maximumn
-- counting periode is 3.66us. Here we set the clock signal to 10us = 100kHz.
-- The timer is preset to 24000.
constant ClkPeriode : time := 10 us;
begin
DUT: ADT7310P16S16
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Enable_i => Enable_i,
CpuIntr_o => CpuIntr_o,
ADT7310CS_n_o => ADT7310CS_n_o,
SPI_Data_i => SPI_Data_i,
SPI_Write_o => SPI_Write_o,
SPI_ReadNext_o => SPI_ReadNext_o,
SPI_Data_o => SPI_Data_o,
SPI_FIFOFull_i => SPI_FIFOFull_i,
SPI_FIFOEmpty_i => SPI_FIFOEmpty_i,
SPI_Transmission_i => SPI_Transmission_i,
SPICounterPreset_i => SPICounterPreset_i,
Threshold_i => Threshold_i,
PeriodCounterPreset_i => PeriodCounterPreset_i,
SensorValue_o => SensorValue_o,
SPI_CPOL_o => SPI_CPOL_o,
SPI_CPHA_o => SPI_CPHA_o,
SPI_LSBFE_o => SPI_LSBFE_o
);
SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
ExtNames_1: ExtNames
port map (
SPIFSM_Done => SPIFSM_Done_i
);
SPIFSM_Done_d <= SPIFSM_Done_i after 1.0 ns;
SPIFSM_Done_a <= SPIFSM_Done_i and SPIFSM_Done_d;
spi_master_1: spi_master
generic map (
DataWidth => DataWidth,
SPPRWidth => SPPRWidth,
SPRWidth => SPRWidth,
FIFOReadWidth => SPIFIFOReadWidth,
FIFOWriteWidth => SPIFIFOWriteWidth
)
port map (
Reset_n => Reset_n_i,
Clk => Clk_i,
-- IO
SCK_o => SCLK_s,
MOSI_o => DIN_s,
MISO_i => DOUT_s,
-- control signals
CPOL_i => SPI_CPOL_o,
CPHA_i => SPI_CPHA_o,
LSBFE_i => SPI_LSBFE_o,
SPPR_i => SPI_SPPR_SPR_o(7 downto 4),
SPR_i => SPI_SPPR_SPR_o(3 downto 0),
Transmission_o => SPI_Transmission_i,
Write_i => SPI_Write_o,
ReadNext_i => SPI_ReadNext_o,
Data_i => SPI_Data_o,
Data_o => SPI_Data_i,
FIFOFull_o => SPI_FIFOFull_i,
FIFOEmpty_o => SPI_FIFOEmpty_i,
ScanEnable_i => SPI_ScanEnable_s,
ScanClk_i => SPI_ScanClk_s,
ScanDataIn_i => SPI_ScanDataIn_s,
ScanDataOut_o => SPI_ScanDataOut_s
);
adt7310_1: adt7310_model
port map (
SCLK_i => SCLK_s,
DOUT_o => DOUT_s,
DIN_i => DIN_s,
CS_n_i => ADT7310CS_n_o,
CT_n_o => CT_n_s,
INT_n_o => INT_n_s,
Temp_i => Temp_s);
-- constant value for reconfig signal
SPI_SPPR_SPR_o <= "00000000";
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
Enable_i <= '0';
SPICounterPreset_i <= "0101110111000000";
Threshold_i <= "0000000000011110";
PeriodCounterPreset_i <= "0000000000001010";
wait for 2.3*ClkPeriode;
assert SPI_CPOL_o = '1'
report "Dynamic signal SPI_CPOL_o should have constant value '1'" severity failure;
assert SPI_CPHA_o = '1'
report "Dynamic signal SPI_CPHA_o should have constant value '1'" severity failure;
assert SPI_LSBFE_o = '0'
report "Dynamic signal SPI_LSBFE_o should have constant value '0'" severity failure;
-- deassert Reset
Reset_n_i <= '1';
wait for 1.3*ClkPeriode; -- wait until spi_master's SCK_o goes '1' to conform to CPOL_i = '1'
Temp_s <= 23.7; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
Enable_i <= '1';
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- The digital value is 128*Temp_s (plus/minus rounding to nearest
-- modulo 8). The threshold for too large changes is 30 (see
-- sensorfsm.vhd).
-- 23.7°C --> 3032
-- 25.7°C --> 3288 (delta: | 256| > 30)
-- 25.6°C --> 3280 (delta: | -8| < 30)
-- 25.5°C --> 3264 (delta: | -24| < 30)
-- 25.4°C --> 3248 (delta: | -40| >= 30)
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.7;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.6;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after SPIFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.5;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after SPIFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.4;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
wait for 100 ms;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/celllib/trfsm/vhdl/StateRegister-e.vhd | 2 | 421 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity StateRegister is
generic (
StateWidth : integer range 1 to 10
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- states
State_o : out std_logic_vector(StateWidth-1 downto 0);
NextState_i : in std_logic_vector(StateWidth-1 downto 0)
);
end StateRegister;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/celllib/trfsm/vhdl/StateRegister-rtl-a.vhd | 2 | 398 | architecture rtl of StateRegister is
begin -- rtl
StoreState: process (Clk_i, Reset_n_i)
begin -- process StoreState
if Reset_n_i = '0' then -- asynchronous reset (active low)
State_o <= (others => '0');
elsif Clk_i'event and Clk_i = '1' then -- rising clock edge
State_o <= NextState_i;
end if;
end process StoreState;
end rtl; -- of StateRegister
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/reconfmodule/chll/out/reconflogic-instance.inc.vhd | 1 | 1708 | -- Automatically generated: write_netlist -preliminary -vhdl -instance reconflogic-instance.inc.vhd
MyReconfigLogic_0: MyReconfigLogic
port map (
Reset_n_i => Reset_n_s,
Clk_i => Clk_i,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i,
I2C_Busy_i => I2C_Busy,
I2C_DataIn_o => I2C_DataIn,
I2C_DataOut_i => I2C_DataOut,
I2C_Divider800_o => I2C_Divider800,
I2C_ErrAckParam_o => I2C_ErrAckParam,
I2C_Error_i => I2C_Error,
I2C_F100_400_n_o => I2C_F100_400_n,
I2C_FIFOEmpty_i => I2C_FIFOEmpty,
I2C_FIFOFull_i => I2C_FIFOFull,
I2C_FIFOReadNext_o => I2C_FIFOReadNext,
I2C_FIFOWrite_o => I2C_FIFOWrite,
I2C_ReadCount_o => I2C_ReadCount,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n,
I2C_StartProcess_o => I2C_StartProcess,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
ReconfModuleIRQs_o => ReconfModuleIRQs_s,
SPI_CPHA_o => SPI_CPHA,
SPI_CPOL_o => SPI_CPOL,
SPI_DataIn_o => SPI_DataIn,
SPI_DataOut_i => SPI_DataOut,
SPI_FIFOEmpty_i => SPI_FIFOEmpty,
SPI_FIFOFull_i => SPI_FIFOFull,
SPI_LSBFE_o => SPI_LSBFE,
SPI_ReadNext_o => SPI_ReadNext,
SPI_SPPR_SPR_o => SPI_SPPR_SPR,
SPI_Transmission_i => SPI_Transmission,
SPI_Write_o => SPI_Write,
ReconfModuleIn_i => ReconfModuleIn_s,
ReconfModuleOut_o => ReconfModuleOut_s,
I2C_Errors_i => I2C_Errors,
PerAddr_i => Per_Addr_s,
PerDIn_i => Per_DIn_s,
PerWr_i => Per_Wr_s,
PerEn_i => Per_En_s,
CfgIntfDOut_o => CfgIntf_DOut_s,
ParamIntfDOut_o => ParamIntf_DOut_s
);
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/core/tb/uart/errorbit-rtl-a.vhd | 1 | 741 |
architecture RTL of ErrorBit is
signal ErrorBitSet : STD_LOGIC;
begin
ErrorInd: process (Clk_i, Reset_i_n, ErrorReset_i)
begin
if (Reset_i_n ='0') then
ErrorBitSet <= '0';
elsif(rising_edge(Clk_i)) then
if (ErrorReset_i = '1') then
ErrorBitSet <= '0';
else
-- hold status
if(ErrorBitSet ='1') then
ErrorBitSet <= ErrorBitSet;
-- only set error if getting error from input
elsif ((ErrorBitSet ='0')) then
if (ErrorBit_i ='1') then
ErrorBitSet <= '1';
else
ErrorBitSet <= '0';
end if;
end if;
end if;
end if;
end process ErrorInd;
ErrorIndicatorBit_o <= ErrorBitSet;
end RTL;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/core/zedboard/fpga_test/fpga_test.srcs/sources_1/chip-e.vhd | 1 | 941 | -- Manually adapted from ../../../../../reconfmodule/chll/out/chip-e.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity chip is
port (
Reset_i : in std_logic;
Clk_i : in std_logic;
Dbg_En_i : in std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_b : inout std_logic;
P1_b : inout std_logic_vector(7 downto 0);
P2_b : inout std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
MISO_i : in std_logic;
MOSI_o : out std_logic;
SCK_o : out std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_b : out std_logic;
I2CSDA_b : inout std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0)
);
end chip;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682/chll/out/max6682-extract-sensorfsm-bitstream.vhd | 2 | 976 | constant SensorFSMLength : integer := 850;
constant SensorFSMCfg : std_logic_vector(SensorFSMLength-1 downto 0) := "0001100010000001100011111000000000000000111110000000000000001111100000000000000011111000000000000000000000000000001010000000000010000000000000000011000010000000010000001000000001001000010000001000000100000000001010000000000001001111100000000000000000000000000000001000001001010000001000000010000001000000001011000000010000000101000100000000101001000010000000010011111000000000000000000000000000001111100000000000000000000000000000000010000011010000000100001000000010000000100000110100000100000011000000011011111000000000000000000000000000000000111110000000000000000000000000000000001111100000000000000000000000000000000011111000000000000000000000000000000000000000001111100000000000000000000000000000000000000000111110000000000000000000000000000000000000000011111000000000000000000000000000000000000000001111100000000000000000000000000000000000000000";
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/slowadt7410/chll/out/slowadt7410-extract-sensorfsm-wrapper.vhd | 8 | 3283 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 5,
NumRows2 => 5,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/paramintf/vhdl/paramintf.vhd | 1 | 5504 | -------------------------------------------------------------------------------
-- Title : Parameterization Interface
-- Project :
-------------------------------------------------------------------------------
-- File : paramintf.vhd
-- Author : Johann Glaser
-- Company :
-- Created : 2013-10-24
-- Last update: 2013-10-24
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Parameterization Interface of the Reconfigurable Module
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-10-24 1.0 hansi Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ParamIntf is
generic (
WrAddrWidth : integer range 1 to 15 := 4; -- max. 15 bits
RdAddrWidth : integer range 1 to 15 := 4;
BaseAddr : integer := 16#0188#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0); -- in reality this is 14 downto 1
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector( 1 downto 0); -- byte select
PerEn_i : in std_logic;
-- Param Out
ParamWrAddr_o : out std_logic_vector(WrAddrWidth-1 downto 0);
ParamWrData_o : out std_logic_vector(15 downto 0);
ParamWr_o : out std_logic;
-- optional: Present_i : in std_logic_vector(2**WrAddrWidth-1 downto 0);
-- Param In
ParamRdAddr_o : out std_logic_vector(RdAddrWidth-1 downto 0);
ParamRdData_i : in std_logic_vector(15 downto 0)
);
end ParamIntf;
-------------------------------------------------------------------------------
-- Registers:
--
-- 0x00 PCA Param Config and Address
-- 15: Auto-Increment (when '1')
-- 14:0: Address
--
-- 0x02 PDR Param Data Register
-- 15:0: Param Data
--
-------------------------------------------------------------------------------
architecture rtl of ParamIntf is
-- addressing this module
constant AddrWidth : integer := 2; -- number of bits considered for (full) address decoding
constant MaskAddrRegs : std_logic_vector(14 downto 0) := std_logic_vector(to_unsigned(2**AddrWidth-1,15));
constant MaskAddrBase : std_logic_vector(14 downto 0) := std_logic_vector(to_unsigned(2**15-1,15)) and (not MaskAddrRegs);
constant BaseAddrVec : std_logic_vector(14 downto 0) := std_logic_vector(to_unsigned(BaseAddr,15)) and MaskAddrBase;
-- addressing individual registers
constant AddrPCA : integer := 0; -- Param Config and Address
constant AddrPDR : integer := 2; -- Param Data Register
-- ...
-- ...
signal AutoIncrement : std_logic;
signal Addr : unsigned(14 downto 0);
signal PDR : std_logic_vector(15 downto 0);
signal DoIncrRd : std_logic;
begin -- rtl
-- purpose: peripheral read via bus interface
-- type : combinational
-- inputs : PerAddr_i,PerEn_i
-- outputs: PerDOut_o
PerRead: process (PerAddr_i,PerEn_i,PerWr_i,Addr,AutoIncrement,ParamRdData_i)
begin -- process PerRead
DoIncrRd <= '0';
PerDOut_o <= (others => '0');
if PerEn_i = '1' and ((PerAddr_i & '0') and MaskAddrBase) = BaseAddrVec and PerWr_i = "00" then
case to_integer(unsigned(PerAddr_i(AddrWidth-2 downto 0) & '0')) is
when AddrPCA => PerDOut_o <= AutoIncrement & std_logic_vector(Addr);
when AddrPDR =>
PerDOut_o <= ParamRdData_i;
DoIncrRd <= '1';
when others => null;
end case;
end if;
end process PerRead;
-- purpose: Peripheral write, parameter read/write
-- type : sequential
-- inputs : Clk_i, Reset_n_i
-- outputs:
PerWrite: process (Clk_i, Reset_n_i)
variable DoIncrWr : std_logic;
begin -- process PerWrite
if Reset_n_i = '0' then -- asynchronous reset (active low)
AutoIncrement <= '0';
Addr <= (others => '0');
PDR <= (others => '0');
ParamWrAddr_o <= (others => '0');
ParamWrData_o <= (others => '0');
ParamWr_o <= '0';
DoIncrWr := '0';
elsif Clk_i'event and Clk_i = '1' then -- rising clock edge
ParamWr_o <= '0';
DoIncrWr := '0';
-- Peripheral write via bus interface
if PerEn_i = '1' and ((PerAddr_i & '0') and MaskAddrBase) = BaseAddrVec and PerWr_i = "11" then
case to_integer(unsigned(PerAddr_i(AddrWidth-2 downto 0) & '0')) is
when AddrPCA =>
AutoIncrement <= PerDIn_i(15);
Addr <= unsigned(PerDIn_i(14 downto 0));
when AddrPDR =>
ParamWrAddr_o <= std_logic_vector(Addr(WrAddrWidth-1 downto 0));
ParamWrData_o <= PerDIn_i;
ParamWr_o <= '1';
DoIncrWr := '1';
when others => null;
end case;
end if;
-- auto-increment
if (DoIncrRd = '1' or DoIncrWr = '1') and AutoIncrement = '1'then
Addr <= Addr + 1;
end if;
end if;
end process PerWrite;
ParamRdAddr_o <= std_logic_vector(Addr(RdAddrWidth-1 downto 0));
end rtl;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682mean/chll/out/max6682mean-extract-spifsm-wrapper.vhd | 6 | 3488 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPIFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
Out10_o : out std_logic;
Out11_o : out std_logic;
Out12_o : out std_logic;
Out13_o : out std_logic;
Out14_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SPIFSM;
architecture struct of SPIFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(7 downto 0);
signal Output_s : std_logic_vector(14 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 8,
OutputWidth => 15,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 10,
NumRows2 => 10,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
Out10_o <= Output_s(10);
Out11_o <= Output_s(11);
Out12_o <= Output_s(12);
Out13_o <= Output_s(13);
Out14_o <= Output_s(14);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
| gpl-2.0 |
elegabriel/myzju | junior1/CA/mips_pipeline2/ipcore_dir/instrmem/simulation/bmg_tb_pkg.vhd | 30 | 6206 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682/tb/core_max6682_tb.vhd | 2 | 12024 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
-- OneWire_i : in std_logic;
-- OneWire_o : out std_logic;
-- PWMInput_i : in std_logic;
-- SENTInput_i : in std_logic;
-- SPCInput_i : in std_logic;
-- SPCTrigger_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component MAX6682_Model
port (
ChipSelect_n_i : in std_logic;
SCLK_i : in std_logic;
SO_o : out std_logic;
Value_i : in std_logic_vector(10 downto 0)
);
end component;
component ExtNames
port (
SPIFSM_Done : out std_logic;
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0);
Enable : out std_logic
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal LFXT_Clk_i : std_logic;
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic;
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic;
signal Dbg_SDA_Out_o : std_logic;
signal Dbg_SDA_In_i : std_logic;
signal P1_DOut_o : std_logic_vector(7 downto 0);
signal P1_En_o : std_logic_vector(7 downto 0);
signal P1_DIn_i : std_logic_vector(7 downto 0);
signal P2_DOut_o : std_logic_vector(7 downto 0);
signal P2_En_o : std_logic_vector(7 downto 0);
signal P2_DIn_i : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic;
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic;
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_o : std_logic;
signal I2CSDA_i : std_logic;
signal I2CSDA_o : std_logic;
-- signal OneWire_i : std_logic;
-- signal OneWire_o : std_logic;
-- signal PWMInput_i : std_logic;
-- signal SENTInput_i : std_logic;
-- signal SPCInput_i : std_logic;
-- signal SPCTrigger_o : std_logic;
signal AdcConvComplete_i : std_logic;
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0);
-- look into the ADT7310 app
-- alias SPIFSM_Done_i is << signal .adt7310_tb.DUT.SPIFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the SPIFSM_Done_i signal.
signal SPIFSM_Done_e : std_logic; -- directly from inside SPI_FSM
signal CpuIntr_e : std_logic; -- directly from inside SPI_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
signal Enable_e : std_logic; -- directly from inside
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- SPIFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal SPIFSM_Done_d : std_logic; -- sightly delayed
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal Enable_i : std_logic; -- directly from inside
-- MAX6682 component ports
signal MAX6682CS_n_o : std_logic;
constant ClkPeriode : time := 10 ns;
-- MAX6682 simulation
signal MAX6682Value : unsigned(10 downto 0);
begin
DUT: Core
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
LFXT_Clk_i => LFXT_Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_Out_o => Dbg_SDA_Out_o,
Dbg_SDA_In_i => Dbg_SDA_In_i,
P1_DOut_o => P1_DOut_o,
P1_En_o => P1_En_o,
P1_DIn_i => P1_DIn_i,
P2_DOut_o => P2_DOut_o,
P2_En_o => P2_En_o,
P2_DIn_i => P2_DIn_i,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_o => I2CSCL_o,
I2CSDA_i => I2CSDA_i,
I2CSDA_o => I2CSDA_o,
-- OneWire_i => OneWire_i,
-- OneWire_o => OneWire_o,
-- PWMInput_i => PWMInput_i,
-- SENTInput_i => SENTInput_i,
-- SPCInput_i => SPCInput_i,
-- SPCTrigger_o => SPCTrigger_o,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
MAX6682CS_n_o <= Outputs_o(0);
Inputs_i <= (others => '0');
P1_DIn_i <= (others => '0');
P2_DIn_i <= (others => '0');
ExtNames_1: ExtNames
port map (
SPIFSM_Done => SPIFSM_Done_e,
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e,
Enable => Enable_e
);
SPIFSM_Done_d <= SPIFSM_Done_e after 1.0 ns;
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
Enable_i <= Enable_e after 1.0 ns;
SPIMISO_i <= 'H';
MAX6682_1: MAX6682_Model
port map (
ChipSelect_n_i => MAX6682CS_n_o,
SCLK_i => SPISCK_o,
SO_o => SPIMISO_i,
Value_i => std_logic_vector(MAX6682Value));
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
MAX6682Value <= (others => '0');
wait for 2.2*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
wait until Enable_i = '1';
wait for 9*ClkPeriode; -- 9 cycles
assert MAX6682CS_n_o = '1' report "CS_n should be '1'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert MAX6682CS_n_o = '0' report "CS_n should be '0' after 10 cycles" severity error;
wait for 35*ClkPeriode; -- 35 cycles
assert MAX6682CS_n_o = '0' report "CS_n should still be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
-- new sensor value: 38 -> large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(38,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
wait for 1*ClkPeriode; -- 1 more cycle if notification happened
-- new sensor value: 30 -> small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(30,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
-- new sensor value: 28 -> small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(28,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
-- new sensor value: 27 -> large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(27,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(27,16)) report "SensorValue_o should be 27" severity error;
wait for 1*ClkPeriode; -- 1 more cycle if notification happened
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 10*ClkPeriode;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/extadc/chll/out/extadc-extract-intersynth-trfsm1-bitstream.vhd | 1 | 1896 | constant TRFSM1Length : integer := 1778;
constant TRFSM1Cfg : std_logic_vector(TRFSM1Length-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/celllib/trfsm/tb/tb_trfsm-behavior.vhd | 1 | 19459 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.trfsmparts.all;
use work.trfsmpkg.all;
use work.tb_trfsmpkg.all;
use work.tbfuncs.all;
entity tb_trfsm is
end tb_trfsm;
architecture behavior of tb_trfsm is
constant InputWidth : integer range 1 to 256 := 10;
constant OutputWidth : integer range 1 to 256 := 7;
constant StateWidth : integer range 1 to 8 := 5;
constant UseResetRow : integer range 0 to 1 := 1;
constant UseCurrentState : integer range 0 to 1 := 1;
constant NumRows0 : integer := 3;
constant NumRows1 : integer := 2;
constant NumRows2 : integer := 6;
constant NumRows3 : integer := 6;
constant NumRows4 : integer := 9;
constant NumRows5 : integer := 0;
constant NumRows6 : integer := 0;
constant NumRows7 : integer := 0;
constant NumRows8 : integer := 0;
constant NumRows9 : integer := 0;
constant ConfigLength : integer := CalcTRFSMConfigLength(InputWidth,OutputWidth,StateWidth,UseResetRow,UseCurrentState,NumRows0,NumRows1,NumRows2,NumRows3,NumRows4,NumRows5,NumRows6,NumRows7,NumRows8,NumRows9);
-- Attention: don't make symmetric values because otherwise we can't find
-- problems with the order
constant CBS_S0_S1: std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"1010xxxxxx","00000","00001","1100110");
constant CBS_S0_S2 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"1111xxxxxx","00000","00010","0011001");
constant CBS_S0_S3 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"0000xxxxxx","00000","00011","0110011");
constant CBS_S0_S0 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"!1010xxxxxx,1111xxxxxx,0000xxxxxx","00000","00000","1111111");
constant CBS_S1_S6 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"1100xxxxxx","00001","00110","1111111");
constant CBS_S1_S7 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"0011xxxxxx","00001","00111","1011101");
constant CBS_S1_S1 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"!1100xxxxxx,0011xxxxxx","00001","00001","0111110");
constant CBS_S2_S3 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"xxxx1xxxxx","00010","00011","1111000");
constant CBS_S2_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxx0xxxxx","00010","00101","0001111");
constant CBS_S3_S4 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,1,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,1,OutputWidth,
"xxxxxxxxx1","00011","00100","1110001");
constant CBS_S3_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,1,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,1,OutputWidth,
"xxxxxxxxx0","00011","00101","1100011");
constant CBS_S4_S1 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"xx01xxxxxx","00100","00001","0111000");
constant CBS_S4_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"xx10xxxxxx","00100","00101","1000111");
constant CBS_S4_S4 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"!xx01xxxxxx,xx10xxxxxx","00100","00100","1111100");
constant CBS_S5_S6 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxxxxx111","00101","00110","1100010");
constant CBS_S5_S0 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxxxxx000","00101","00000","1100111");
constant CBS_S5_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"!xxxxxxx111,xxxxxxx000","00101","00101","0000000");
constant CBS_S6_S0 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"xxxxxxx110","00110","00000","1010101");
constant CBS_S6_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxxxxx010","00110","00101","0101010");
constant CBS_S6_S6 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"!xxxxxxx110,xxxxxxx010","00110","00110","1101111");
constant CBS_S7_S8 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,0,OutputWidth,
"","00111","01000","1011110");
constant CBS_S8_S9 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,0,OutputWidth,
"","01000","01001","1011111");
constant CBS_S9_S2 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"!","01001","00010","1011100");
-- use an unused state to disable this TR
constant CBS_0_unused : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,0,OutputWidth,
"","11111","00000","1010101");
-- use a used state but set the IPG to "0000" to disable this TR
constant CBS_2_unused_noinput : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"","00001","00000","1010110");
-- use an unused state to disable this TR but set the IPG to "1111"
constant CBS_2_unused_nostate : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"!","11110","00000","1010111");
-- important: the LSBs of this vector are assiciated with the low-input TRs
constant ConfigBitStream : std_logic_vector(ConfigLength-1 downto 0) :=
-- Width = 0
CBS_S7_S8 &
CBS_S8_S9 &
CBS_0_unused &
-- Width = 1
CBS_S3_S4 &
CBS_S3_S5 &
-- Width = 2
CBS_S2_S3 &
CBS_S4_S1 &
CBS_S4_S5 &
CBS_S9_S2 &
CBS_2_unused_noinput &
CBS_2_unused_nostate &
-- Width = 3
CBS_S2_S5 &
CBS_S5_S6 &
CBS_S5_S0 &
CBS_S5_S5 &
CBS_S6_S5 &
CBS_S6_S6 &
-- Width = 4
CBS_S0_S1 &
CBS_S0_S2 &
CBS_S0_S3 &
CBS_S0_S0 &
CBS_S1_S6 &
CBS_S1_S7 &
CBS_S1_S1 &
CBS_S4_S4 &
CBS_S6_S0;
constant CfgClkHalfPeriode : time := 100 ns;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
signal Reset_n_i : std_logic;
signal Clk_i : std_logic;
signal Input_i : std_logic_vector(InputWidth-1 downto 0);
signal Output_o : std_logic_vector(OutputWidth-1 downto 0);
signal CfgMode_i : std_logic;
signal CfgClk_i : std_logic;
signal CfgShift_i : std_logic;
signal CfgDataIn_i : std_logic;
signal CfgDataOut_o : std_logic;
signal ScanEnable_i : std_logic;
signal ScanClk_i : std_logic;
signal ScanDataIn_i : std_logic;
signal ScanDataOut_o : std_logic;
procedure CheckTRFSM (
constant Input : in std_logic_vector(InputWidth-1 downto 0);
constant Output : in std_logic_vector(OutputWidth-1 downto 0);
signal Input_i : out std_logic_vector(InputWidth-1 downto 0);
signal Output_o : in std_logic_vector(OutputWidth-1 downto 0)
) is
variable l : line;
begin
Input_i <= Input;
write(l,string'("Input = "));
write(l,Input);
wait for CheckOutputDelay;
write(l,string'(" => Output = "));
write(l,Output_o);
if Output_o = Output then
write(l,string'(" OK "));
else
write(l,string'(" ERROR: should be "));
write(l,Output);
end if;
writeline(std.textio.output,l);
wait for SetupNextInputDelay;
end CheckTRFSM;
procedure ClkCycle (
signal Clk_i : out std_logic
) is
begin
Clk_i <= '1';
wait for CfgClkHalfPeriode;
Clk_i <= '0';
wait for CfgClkHalfPeriode;
end ClkCycle;
begin -- behavior
TRFSM_1: TRFSM
generic map (
InputWidth => InputWidth,
OutputWidth => OutputWidth,
StateWidth => StateWidth,
UseResetRow => UseResetRow,
NumRows0 => NumRows0,
NumRows1 => NumRows1,
NumRows2 => NumRows2,
NumRows3 => NumRows3,
NumRows4 => NumRows4,
NumRows5 => NumRows5,
NumRows6 => NumRows6,
NumRows7 => NumRows7,
NumRows8 => NumRows8,
NumRows9 => NumRows9)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_i,
Output_o => Output_o,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_i,
ScanClk_i => ScanClk_i,
ScanDataIn_i => ScanDataIn_i,
ScanDataOut_o => ScanDataOut_o);
Check: process
begin -- process Check
-- set all inputs
Clk_i <= '0';
Input_i <= (others => '0');
CfgMode_i <= '0';
CfgClk_i <= '0';
CfgShift_i <= '0';
CfgDataIn_i <= '0';
ScanEnable_i <= '0';
ScanClk_i <= '0';
ScanDataIn_i <= '0';
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
Reset_n_i <= '0';
wait for 1 us;
Reset_n_i <= '1';
wait for 1 ns;
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
-- shift in the config bit stream with LSB first, the ConfigRegister will
-- shift this from right to left (=MSB to LSB), so after everything is
-- shifted, the bits have the same order as setup above and as visible at
-- the screen.
-- assert false report "ConfigBitStream = " & Vector2String(ConfigBitStream) severity note;
CfgMode_i <= '1';
CfgShift_i <= '1';
wait for CfgClkHalfPeriode;
for i in 0 to ConfigLength-1 loop
CfgDataIn_i <= ConfigBitStream(i);
wait for SetupNextInputDelay;
CfgClk_i <= '1';
wait for CfgClkHalfPeriode;
CfgClk_i <= '0';
wait for CfgClkHalfPeriode-SetupNextInputDelay;
end loop; -- i
CfgMode_i <= '0';
CfgShift_i <= '0';
wait for CheckOutputDelay;
assert false report "### Configuration done" severity note;
-- 127129ns
---------------------------------------------------------------------------
-- Action
---------------------------------------------------------------------------
-- State 0, test all transitions
CheckTRFSM("1010000000","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010111111","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010110011","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010010101","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010101010","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1111000000","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111111111","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111001100","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111101010","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111010111","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("0000000000","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000111111","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000101010","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000010101","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000110111","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("1110000000","1111111",Input_i,Output_o); -- stay
CheckTRFSM("1110111011","1111111",Input_i,Output_o); -- stay
CheckTRFSM("0010000000","1111111",Input_i,Output_o); -- stay
CheckTRFSM("0101000000","1111111",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 0 again
CheckTRFSM("1010110111","1100110",Input_i,Output_o); -- to S1
ClkCycle(Clk_i);
-- State 1
CheckTRFSM("1100110111","1111111",Input_i,Output_o); -- to S6
CheckTRFSM("1100111111","1111111",Input_i,Output_o); -- to S6
CheckTRFSM("1100000000","1111111",Input_i,Output_o); -- to S6
CheckTRFSM("0011000000","1011101",Input_i,Output_o); -- to S7
CheckTRFSM("0011111111","1011101",Input_i,Output_o); -- to S7
CheckTRFSM("0011010101","1011101",Input_i,Output_o); -- to S7
CheckTRFSM("1111110111","0111110",Input_i,Output_o); -- stay
CheckTRFSM("0000000000","0111110",Input_i,Output_o); -- stay
CheckTRFSM("0010010101","0111110",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 1 again
CheckTRFSM("1100011001","1111111",Input_i,Output_o); -- to S6
ClkCycle(Clk_i);
-- State 6
CheckTRFSM("0000000110","1010101",Input_i,Output_o); -- to S0
CheckTRFSM("0000000010","0101010",Input_i,Output_o); -- to S5
CheckTRFSM("0000000111","1101111",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 1 again
CheckTRFSM("1111111010","0101010",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("0000000111","1100010",Input_i,Output_o); -- to S6
CheckTRFSM("1010111000","1100111",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("1111110111","0011001",Input_i,Output_o); -- to S2
ClkCycle(Clk_i);
-- State 2
CheckTRFSM("0000100000","1111000",Input_i,Output_o); -- to S3
CheckTRFSM("0001110000","1111000",Input_i,Output_o); -- to S3
CheckTRFSM("1111011111","0001111",Input_i,Output_o); -- to S5
CheckTRFSM("1110001111","0001111",Input_i,Output_o); -- to S5
CheckTRFSM("0001110011","1111000",Input_i,Output_o); -- to S3
ClkCycle(Clk_i);
-- State 3
CheckTRFSM("0000000001","1110001",Input_i,Output_o); -- to S4
CheckTRFSM("1010101011","1110001",Input_i,Output_o); -- to S4
CheckTRFSM("0000000000","1100011",Input_i,Output_o); -- to S5
CheckTRFSM("0101010100","1100011",Input_i,Output_o); -- to S5
CheckTRFSM("0011100111","1110001",Input_i,Output_o); -- to S4
ClkCycle(Clk_i);
-- State 4
CheckTRFSM("0001000000","0111000",Input_i,Output_o); -- to S1
CheckTRFSM("1101111111","0111000",Input_i,Output_o); -- to S1
CheckTRFSM("0010000000","1000111",Input_i,Output_o); -- to S5
CheckTRFSM("1110111111","1000111",Input_i,Output_o); -- to S5
CheckTRFSM("1111111111","1111100",Input_i,Output_o); -- stay
CheckTRFSM("1100111111","1111100",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 1 again
CheckTRFSM("1010101010","1000111",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("1111111111","1100010",Input_i,Output_o); -- to S6
ClkCycle(Clk_i);
-- State 6
CheckTRFSM("0000000110","1010101",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("1111110111","0011001",Input_i,Output_o); -- to S2
ClkCycle(Clk_i);
-- State 2
CheckTRFSM("1110001111","0001111",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("1010111000","1100111",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("0000011010","0110011",Input_i,Output_o); -- to S3
ClkCycle(Clk_i);
-- State 3
CheckTRFSM("1111111110","1100011",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("0010011111","1100010",Input_i,Output_o); -- to S6
CheckTRFSM("0101010000","1100111",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("1010011010","1100110",Input_i,Output_o); -- to S1
ClkCycle(Clk_i);
-- State 1
CheckTRFSM("0011000000","1011101",Input_i,Output_o); -- to S7
ClkCycle(Clk_i);
-- State 7
CheckTRFSM("0000000000","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("1111111111","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("1010101010","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("0101010101","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("1100110011","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("0011001100","1011110",Input_i,Output_o); -- to S8
ClkCycle(Clk_i);
-- State 8
CheckTRFSM("0000000000","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("1111111111","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("1010101010","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("0101010101","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("1100110011","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("0011001100","1011111",Input_i,Output_o); -- to S9
ClkCycle(Clk_i);
-- State 9
CheckTRFSM("0000000000","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("1111111111","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("1010101010","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("0101010101","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("1100110011","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("0011001100","1011100",Input_i,Output_o); -- to S2
ClkCycle(Clk_i);
-- State 2
CheckTRFSM("1110001111","0001111",Input_i,Output_o); -- to S5
---------------------------------------------------------------------------
-- Simulation is finished
---------------------------------------------------------------------------
assert 0 = 1
report " simulation is finished "
severity failure ;
end process Check;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7410/chll/out/adt7410-wrapreconfmodule-lec.vhd | 1 | 7999 | -- Automatically generated: write_netlist -wraprm_lec -vhdl -module adt7410-wrapreconfmodule-lec.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ADT7410 is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
I2C_ReceiveSend_n_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(7 downto 0);
I2C_StartProcess_o : out std_logic;
I2C_Busy_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_Data_o : out std_logic_vector(7 downto 0);
I2C_Data_i : in std_logic_vector(7 downto 0);
I2C_Error_i : in std_logic;
PeriodCounterPreset_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
WaitCounterPreset_i : in std_logic_vector(15 downto 0)
);
attribute intersynth_port : string;
attribute intersynth_conntype : string;
attribute intersynth_param : string;
attribute intersynth_port of Reset_n_i : signal is "Reset_n_i";
attribute intersynth_port of Clk_i : signal is "Clk_i";
attribute intersynth_port of Enable_i : signal is "ReconfModuleIn_s";
attribute intersynth_conntype of Enable_i : signal is "Bit";
attribute intersynth_port of CpuIntr_o : signal is "ReconfModuleIRQs_s";
attribute intersynth_conntype of CpuIntr_o : signal is "Bit";
attribute intersynth_port of I2C_ReceiveSend_n_o : signal is "I2C_ReceiveSend_n";
attribute intersynth_conntype of I2C_ReceiveSend_n_o : signal is "Bit";
attribute intersynth_port of I2C_ReadCount_o : signal is "I2C_ReadCount";
attribute intersynth_conntype of I2C_ReadCount_o : signal is "Byte";
attribute intersynth_port of I2C_StartProcess_o : signal is "I2C_StartProcess";
attribute intersynth_conntype of I2C_StartProcess_o : signal is "Bit";
attribute intersynth_port of I2C_Busy_i : signal is "I2C_Busy";
attribute intersynth_conntype of I2C_Busy_i : signal is "Bit";
attribute intersynth_port of I2C_FIFOReadNext_o : signal is "I2C_FIFOReadNext";
attribute intersynth_conntype of I2C_FIFOReadNext_o : signal is "Bit";
attribute intersynth_port of I2C_FIFOWrite_o : signal is "I2C_FIFOWrite";
attribute intersynth_conntype of I2C_FIFOWrite_o : signal is "Bit";
attribute intersynth_port of I2C_Data_o : signal is "I2C_DataIn";
attribute intersynth_conntype of I2C_Data_o : signal is "Byte";
attribute intersynth_port of I2C_Data_i : signal is "I2C_DataOut";
attribute intersynth_conntype of I2C_Data_i : signal is "Byte";
attribute intersynth_port of I2C_Error_i : signal is "I2C_Error";
attribute intersynth_conntype of I2C_Error_i : signal is "Bit";
attribute intersynth_param of PeriodCounterPreset_i : signal is "PeriodCounterPreset_i";
attribute intersynth_conntype of PeriodCounterPreset_i : signal is "Word";
attribute intersynth_param of SensorValue_o : signal is "SensorValue_o";
attribute intersynth_conntype of SensorValue_o : signal is "Word";
attribute intersynth_param of Threshold_i : signal is "Threshold_i";
attribute intersynth_conntype of Threshold_i : signal is "Word";
attribute intersynth_param of WaitCounterPreset_i : signal is "WaitCounterPreset_i";
attribute intersynth_conntype of WaitCounterPreset_i : signal is "Word";
end ADT7410;
architecture WrapReconfModule of ADT7410 is
component MyReconfigLogic
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0);
I2C_Busy_i : in std_logic;
I2C_DataIn_o : out std_logic_vector(7 downto 0);
I2C_DataOut_i : in std_logic_vector(7 downto 0);
I2C_Divider800_o : out std_logic_vector(15 downto 0);
I2C_ErrAckParam_o : out std_logic;
I2C_Error_i : in std_logic;
I2C_F100_400_n_o : out std_logic;
I2C_FIFOEmpty_i : in std_logic;
I2C_FIFOFull_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(3 downto 0);
I2C_ReceiveSend_n_o : out std_logic;
I2C_StartProcess_o : out std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
ReconfModuleIRQs_o : out std_logic_vector(4 downto 0);
SPI_CPHA_o : out std_logic;
SPI_CPOL_o : out std_logic;
SPI_DataIn_o : out std_logic_vector(7 downto 0);
SPI_DataOut_i : in std_logic_vector(7 downto 0);
SPI_FIFOEmpty_i : in std_logic;
SPI_FIFOFull_i : in std_logic;
SPI_LSBFE_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_SPPR_SPR_o : out std_logic_vector(7 downto 0);
SPI_Transmission_i : in std_logic;
SPI_Write_o : out std_logic;
ReconfModuleIn_i : in std_logic_vector(7 downto 0);
ReconfModuleOut_o : out std_logic_vector(7 downto 0);
I2C_Errors_i : in std_logic_vector(7 downto 0);
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgIntfDOut_o : out std_logic_vector(15 downto 0);
ParamIntfDOut_o : out std_logic_vector(15 downto 0)
);
end component;
signal ReconfModuleIn_s : std_logic_vector(7 downto 0);
signal ReconfModuleIRQs_s : std_logic_vector(4 downto 0);
signal I2C_ReadCount_s : std_logic_vector(3 downto 0);
signal AdcDoConvert_s : std_logic;
signal CfgIntfDOut_s : std_logic_vector(15 downto 0);
signal I2C_Divider800_s : std_logic_vector(15 downto 0);
signal I2C_ErrAckParam_s : std_logic;
signal I2C_F100_400_n_s : std_logic;
signal Outputs_s : std_logic_vector(7 downto 0);
signal ParamIntfDOut_s : std_logic_vector(15 downto 0);
signal ReconfModuleOut_s : std_logic_vector(7 downto 0);
signal SPI_CPHA_s : std_logic;
signal SPI_CPOL_s : std_logic;
signal SPI_DataIn_s : std_logic_vector(7 downto 0);
signal SPI_LSBFE_s : std_logic;
signal SPI_ReadNext_s : std_logic;
signal SPI_SPPR_SPR_s : std_logic_vector(7 downto 0);
signal SPI_Write_s : std_logic;
begin
MyReconfigLogic_0: MyReconfigLogic
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
ReconfModuleIn_i => ReconfModuleIn_s,
ReconfModuleIRQs_o => ReconfModuleIRQs_s,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n_o,
I2C_ReadCount_o => I2C_ReadCount_s,
I2C_StartProcess_o => I2C_StartProcess_o,
I2C_Busy_i => I2C_Busy_i,
I2C_FIFOReadNext_o => I2C_FIFOReadNext_o,
I2C_FIFOWrite_o => I2C_FIFOWrite_o,
I2C_DataIn_o => I2C_Data_o,
I2C_DataOut_i => I2C_Data_i,
I2C_Error_i => I2C_Error_i,
AdcConvComplete_i => '0',
AdcDoConvert_o => AdcDoConvert_s,
AdcValue_i => "0000000000",
CfgIntfDOut_o => CfgIntfDOut_s,
I2C_Divider800_o => I2C_Divider800_s,
I2C_ErrAckParam_o => I2C_ErrAckParam_s,
I2C_Errors_i => "00000000",
I2C_F100_400_n_o => I2C_F100_400_n_s,
I2C_FIFOEmpty_i => '0',
I2C_FIFOFull_i => '0',
Inputs_i => "00000000",
Outputs_o => Outputs_s,
ParamIntfDOut_o => ParamIntfDOut_s,
PerAddr_i => "00000000000000",
PerDIn_i => "0000000000000000",
PerEn_i => '0',
PerWr_i => "00",
ReconfModuleOut_o => ReconfModuleOut_s,
SPI_CPHA_o => SPI_CPHA_s,
SPI_CPOL_o => SPI_CPOL_s,
SPI_DataIn_o => SPI_DataIn_s,
SPI_DataOut_i => "00000000",
SPI_FIFOEmpty_i => '0',
SPI_FIFOFull_i => '0',
SPI_LSBFE_o => SPI_LSBFE_s,
SPI_ReadNext_o => SPI_ReadNext_s,
SPI_SPPR_SPR_o => SPI_SPPR_SPR_s,
SPI_Transmission_i => '0',
SPI_Write_o => SPI_Write_s
);
CpuIntr_o <= ReconfModuleIRQs_s(0);
I2C_ReadCount_o <= "0000" & I2C_ReadCount_s;
ReconfModuleIn_s <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & Enable_i;
end WrapReconfModule;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/i2c_master/tb/tb_i2ccore-e.vhd | 1 | 643 | --------------------------------------------------------------------------------
-- Company: vienna university of technology
-- Engineer: mario faschang
-- Create Date: 11:22:56 11/26/2009
-- Module Name: tb_I2CCore
-- Project Name: i2c master controller
-- Description: * testbench for i2ccore
-- * generates different scenarios of the i2c-bus-communication
-- to verify the behavior of the i2c-core.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_I2CCore IS
END tb_I2CCore;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/celllib/bytemuxdual/tb/bytemuxdual_tb.vhd | 1 | 2048 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.TbFuncs.all;
entity ByteMuxDual_tb is
end ByteMuxDual_tb;
architecture behavior of ByteMuxDual_tb is
component ByteMuxDual
port (
A_i : in std_logic_vector(7 downto 0);
B_i : in std_logic_vector(7 downto 0);
S_i : in std_logic;
Y_o : out std_logic_vector(7 downto 0)
);
end component;
constant TestCases : natural := 100;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
signal A_i : std_logic_vector(7 downto 0);
signal B_i : std_logic_vector(7 downto 0);
signal S_i : std_logic;
signal Y_o : std_logic_vector(7 downto 0);
begin
DUT: ByteMuxDual
port map (
A_i => A_i,
B_i => B_i,
S_i => S_i,
Y_o => Y_o
);
StimulusProc: process
variable S1 : positive;
variable S2 : positive;
variable R : real;
procedure Check (
constant S : in std_logic;
constant Correct : in std_logic_vector(7 downto 0)) is
begin -- Check
S_i <= S;
wait for CheckOutputDelay;
assert Y_o = Correct
report "Wrong Result Y_o = " & Vector2String(Y_o) &
" for A_i = " & Vector2String(A_i) &
", B_i = " & Vector2String(B_i) &
", S_i = " & std_logic'image(S_i) &
", should be " & Vector2String(Correct) severity error;
end Check;
begin
A_i <= "00000000";
B_i <= "00000000";
S_i <= '0';
wait for SetupNextInputDelay;
for i in 1 to TestCases loop
Uniform(S1,S2,R);
A_i <= std_logic_vector(to_unsigned(integer(trunc(R * real(255))),8));
Uniform(S1,S2,R);
B_i <= std_logic_vector(to_unsigned(integer(trunc(R * real(255))),8));
Check('0',A_i);
Check('1',B_i);
wait for SetupNextInputDelay;
end loop;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/extadc/chll/out/extadc-extract-intersynth-trfsm2-bitstream.vhd | 3 | 1138 | constant TRFSM2Length : integer := 1020;
constant TRFSM2Cfg : std_logic_vector(TRFSM2Length-1 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/core/tb/uart/baudgenerator-rtl-a.vhd | 1 | 2506 |
architecture RTL of BaudGenerator is
constant SamplingRateWidth : integer := Oversampling;
constant SamplingRate : std_logic_vector((SamplingRateWidth-1) downto 0) := (others => '1');
-- signals for the fast BaudRate x 4
signal SamplingBaudEnable : std_logic;
signal BaudEnable : std_logic;
-- Divider_i = Divider
-- speed divider 1 not allowed
begin
-- 4x baud rate for Rx oversampling
SamplingDivider : process (Clk_i, Reset_i_n)
variable Counter : std_logic_vector((MaxSpeedDividerWidth-1) downto 0);
begin
--Counter := Divider;
if Reset_i_n ='0' then
SamplingBaudEnable <= '0';
-- sample input on reset
Counter := (others => '0');
-- set oversampling
elsif rising_edge(Clk_i)then
if BGenable_i = '1' then
Counter := std_logic_vector(unsigned(Counter) - 1);
if ( to_integer(unsigned(Counter)) = 0) then
SamplingBaudEnable <= '1';
Counter := std_logic_vector(unsigned(SpeedDivider_i));
else
SamplingBaudEnable <= '0';
end if;
else
-- enable is like a reset
SamplingBaudEnable <= '0';
Counter := std_logic_vector(unsigned(SpeedDivider_i));
end if;
else
null;
end if;
end process SamplingDivider;
NoOversampling: if Oversampling = 0 generate
BaudEnable <= SamplingBaudEnable;
end generate NoOversampling;
UseOversampling: if Oversampling > 0 generate
-- real baud rate
DivideOversampling : process (Clk_i, Reset_i_n)
variable SubCounter : std_logic_vector((SamplingRateWidth-1) downto 0);
begin
if Reset_i_n ='0' then
SubCounter := SamplingRate;
elsif rising_edge(Clk_i) then
if BGenable_i = '1' then
if SamplingBaudEnable = '1' then
SubCounter := std_logic_vector(unsigned(SubCounter) -1 );
if (to_integer(unsigned(SubCounter)) = 0) then
BaudEnable <= '1';
else
BaudEnable <= '0';
end if;
end if;
else
SubCounter := SamplingRate;
BaudEnable <= '0';
end if;
end if;
end process DivideOversampling;
end generate UseOversampling;
-- Blank out first half of the BaudSamplingClk, so that BaudClk is just high for the second half
BaudClk_o <= '1' when((BaudEnable ='1') and (SamplingBaudEnable = '1')) else
'0';
BaudSamplingClk_o <= SamplingBaudEnable;
end RTL;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/slowadt7410/chll/out/slowadt7410-bitdata-bitstream.vhd | 1 | 1403 | constant bitdataLength : integer := 1282;
constant bitdataCfg : std_logic_vector(bitdataLength-1 downto 0) := "0000000000000000001000001001000010010001000000110000001000000000100000000000000000000011000011000000000000000000000000011000000000000011000000000000000000000000000000000010001000100000010110000000000000000000000000000000000011000000000000000000000000001001000000010000001000000000000000000000000000000000000000000001001000001000100011010000100100001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110101011100000000000010000000000000000000000000000000101101010000000001100000000000000000000011000101000000011010110101101011010110101101010000000000000000000000000000010001100100010000000111100100000000000000000000000000000000000000000001100100110000000000000000000000000000000000000000000000000000000000000000000000000110100000000000000011010100000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000010100000000000000000000001000111000100010101100000000001101011000000101100000011110000101110000001011000000000000000000000000000000000000000000000000000000000000000000000011010000000000000000000000000000010010110000000000000011100000000000000000000000000000001001000000101100100010000100000001010000000000000000000000000000000000000010000000000000000000000000000000000000";
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/spi_master/tb/tb_spi-e.vhd | 1 | 548 | ----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 17:41:00 01/18/2010
-- Design Name: SPI
-- Module Name: tb_SPI
-- Description: VHDL Test Bench for module: SPI
--
-- Revision:
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tb_SPI is
end tb_SPI;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/spi_master/tb/tb_spicontrol-behavior-a.vhd | 1 | 65144 |
architecture behavior of tb_SPIControl is
constant DataWidth : integer range 2 to 64 := 8;
-- Component Declaration for the Unit Under Test (UUT)
component SPIControl is
Generic (
DataWidth : integer range 2 to 64 := 8);
Port (
Reset_n : in STD_LOGIC;
Clk : in STD_LOGIC;
-- SPI config param
CPOL_i : in STD_LOGIC;
CPHA_i : in STD_LOGIC;
-- SPI clock output
SCK_o : out STD_LOGIC;
-- SPI control signals
Transmission_o : out STD_LOGIC;
EnFrqDivider_o : out STD_LOGIC;
NextStep_i : in STD_LOGIC;
LdShifter_o : out STD_LOGIC;
EnShift_o : out STD_LOGIC;
EnSample_o : out STD_LOGIC;
WrFIFOEmpty_i : in STD_LOGIC;
RdWriteFIFO_o : out STD_LOGIC;
RdFIFOFull_i : in STD_LOGIC;
LdReadFIFO_o : out STD_LOGIC);
end component;
-- Inputs
signal Reset_n : STD_LOGIC := '0';
signal Clk : STD_LOGIC := '0';
signal CPOL : STD_LOGIC := '0';
signal CPHA : STD_LOGIC := '0';
signal NextStep : STD_LOGIC := '1';
signal WrFIFOEmpty : STD_LOGIC := '1';
signal RdFIFOFull : STD_LOGIC := '0';
-- Outputs
signal SCK : STD_LOGIC;
signal Transmission : STD_LOGIC;
signal EnFrqDivider : STD_LOGIC;
signal LdShifter : STD_LOGIC;
signal EnShift : STD_LOGIC;
signal EnSample : STD_LOGIC;
signal RdWriteFIFO : STD_LOGIC;
signal LdReadFIFO : STD_LOGIC;
-- TB control signals
signal ClkDivby3 : STD_LOGIC := '0';
-- Clock period definitions
constant Clk_period : time := 10 us;
constant Clk_delay : time := Clk_period/10;
begin
-- Instantiate the Unit Under Test (UUT)
uut: SPIControl
Generic Map (
DataWidth => DataWidth)
Port Map (
Reset_n => Reset_n,
Clk => Clk,
CPOL_i => CPOL,
CPHA_i => CPHA,
SCK_o => SCK,
Transmission_o => Transmission,
EnFrqDivider_o => EnFrqDivider,
NextStep_i => NextStep,
LdShifter_o => LdShifter,
EnShift_o => EnShift,
EnSample_o => EnSample,
WrFIFOEmpty_i => WrFIFOEmpty,
RdWriteFIFO_o => RdWriteFIFO,
RdFIFOFull_i => RdFIFOFull,
LdReadFIFO_o => LdReadFIFO);
-- Clock process definitions
Clk_process: process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process Clk_process;
-- Clock Divider by 3
ClockkDividerby3: process
begin
if ClkDivby3 = '0' then
NextStep <= '1';
wait until Clk'event and Clk = '1';
else
NextStep <= '0';
wait until Clk'event and Clk = '1';
NextStep <= '0';
wait until Clk'event and Clk = '1';
NextStep <= '1';
wait until Clk'event and Clk = '1';
end if;
end process ClockkDividerby3;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for Clk_period*5.
wait for Clk_period*5;
Reset_n <= '1';
wait for Clk_period*5;
-- testcase 1: test for initial state
report "testcase 1" severity note;
assert SCK = '0'
report "SCK_o should be '0' after reset"
severity error;
assert Transmission = '0'
report "Transmission_o should be '0' after reset"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0' after reset"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0' after reset"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' after reset"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' after reset"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' after reset"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' after reset"
severity error;
-- end testcase 1;
-- testcase 2: idle - transmission - transmission - idle
-- baudrate = clk / 6
-- testcase 2a: CPOL = 0, CPHA = 0
report "testcase 2a" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '0';
CPHA <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '1';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '0';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at start of testcase 2a"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '0'; -- continue transmission
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at restart of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at restart of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at restart of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at restart of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at restart of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at end of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at end of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at end of transmission"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' at end of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at end of transmission"
severity error;
ClkDivby3 <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 2a;
-- testcase 2b: CPOL = 1, CPHA = 0
report "testcase 2b" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '1';
CPHA <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '1';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '0';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at start of testcase 2b"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '0'; -- continue transmission
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at restart of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at restart of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at restart of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at restart of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at restart of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at end of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at end of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at end of transmission"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' at end of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at end of transmission"
severity error;
ClkDivby3 <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 2b;
-- testcase 2c: CPOL = 0, CPHA = 1
report "testcase 2c" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '0';
CPHA <= '1';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '1';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '0';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at start of testcase 2c"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '0'; -- continue transmission
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at restart of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at restart of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at restart of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at restart of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at restart of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at end of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at end of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at end of transmission"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' at end of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at end of transmission"
severity error;
ClkDivby3 <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 2c;
-- testcase 2d: CPOL = 1, CPHA = 1
report "testcase 2d" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '1';
CPHA <= '1';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '1';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '0';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at start of testcase 2d"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '0'; -- continue transmission
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at restart of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at restart of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at restart of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at restart of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at restart of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at end of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at end of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at end of transmission"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' at end of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at end of transmission"
severity error;
ClkDivby3 <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 2d;
-- end testcase 2;
-- testcase 3: idle - transmission - suspend - suspend -
-- transmission - suspend - idle
-- baudrate = clk / 2
-- testcase 3a: CPOL = 0, CPHA = 0
report "testcase 3a" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '0';
CPHA <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '0';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '1'; -- force suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at start of testcase 3a"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' before entering suspend mode"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0' before entering suspend mode"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0' before entering suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' before entering suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' before entering suspend mode"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' before entering suspend mode"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' before entering suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
RdFIFOFull <= '0'; -- release from suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at recovering from suspend mode"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' at recovering from suspend mode"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' at recovering from suspend mode"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at recovering from suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at recovering from suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at recovering from suspend mode"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at recovering from suspend mode"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at recovering from suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
RdFIFOFull <= '1'; -- force suspend after transmission
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' before entering suspend mode"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0' before entering suspend mode"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0' before entering suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' before entering suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' before entering suspend mode"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' before entering suspend mode"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' before entering suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
RdFIFOFull <= '0'; -- release from suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '0'
report "Transmission_o should be '0'"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 3a;
-- testcase 3b: CPOL = 0, CPHA = 1
report "testcase 3b" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '0';
CPHA <= '1';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '0';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '1'; -- force suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at start of testcase 3b"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' before entering suspend mode"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0' before entering suspend mode"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0' before entering suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' before entering suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' before entering suspend mode"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' before entering suspend mode"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' before entering suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
RdFIFOFull <= '0'; -- release from suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at recovering from suspend mode"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' at recovering from suspend mode"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' at recovering from suspend mode"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at recovering from suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at recovering from suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at recovering from suspend mode"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at recovering from suspend mode"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at recovering from suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
RdFIFOFull <= '1'; -- force suspend after transmission
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' before entering suspend mode"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0' before entering suspend mode"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0' before entering suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' before entering suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' before entering suspend mode"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' before entering suspend mode"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' before entering suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
RdFIFOFull <= '0'; -- release from suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '0'
report "Transmission_o should be '0'"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 3b;
-- end testcase 3;
-- insert some space time
wait for Clk_period*5;
-- end simulation
report "NONE. Simulation finished" severity failure; -- used to stop simulation
end process;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7310/chll/out/adt7310-fsm-spifsm-bitstream.vhd | 1 | 1413 | constant SPIFSMLength : integer := 1295;
constant SPIFSMCfg : std_logic_vector(SPIFSMLength-1 downto 0) := "00001001110000010000000000010000000000000000000000001010101000000000100000000110000110000000000010000011100100000000100000000000000000010001000000000000000100000000000000100100011000000000001000000010000000010100010000000000000001000100000000110010000000000000000010001100000010100001100000000000010000011000000100101001000000000000100010000000000011001010000000100000000100100000000110001000000000000001001010000000100100001000000000100000010100000001010010100000000001000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000";
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/spi_master/vhdl/spifrqdiv-rtl-a.vhd | 1 | 1585 |
architecture RTL of SPIFrqDiv is
signal SPPR : STD_LOGIC_VECTOR(SPPRWidth-1 downto 0);
signal NextSPPR : STD_LOGIC_VECTOR(SPPRWidth-1 downto 0);
signal SPR : STD_LOGIC_VECTOR(2**SPRWidth-2 downto 0);
signal NextSPR : STD_LOGIC_VECTOR(2**SPRWidth-2 downto 0);
type PreloadTable_t is array(2**SPRWidth-1 downto 0) of STD_LOGIC_VECTOR(2**SPRWidth-2 downto 0);
signal PreLoadTable : PreloadTable_t;
begin
-- generate preload value for baudrate selection
PreLoadTable(0) <= (others => '0');
GenPreload: for i in 1 to 2**SPRWidth-1 generate
PreLoadTable(i) <= std_logic_vector(to_unsigned(integer(2**i-1),2**SPRWidth-1));
end generate GenPreload;
-- baudrate preselector
NextSPPR <= (others => '0') when EnFrqDivider_i = '0' else
SPPR_i when SPPR = 0 else
SPPR-1;
BaudratePreSelector: process (Reset_n, Clk)
begin
if Reset_n = '0' then
SPPR <= (others => '0');
elsif Clk'event and Clk = '1' then
SPPR <= NextSPPR;
end if;
end process BaudratePreSelector;
-- baudrate selector
NextSPR <= (others => '0') when EnFrqDivider_i = '0' else
PreLoadTable(to_integer(unsigned(SPR_i))) when SPR = 0 and SPPR = 0 else
SPR-1 when SPPR = 0 else
SPR;
BaudrateSelector: process (Reset_n, Clk)
begin
if Reset_n = '0' then
SPR <= (others => '0');
elsif Clk'event and Clk = '1' then
SPR <= NextSPR;
end if;
end process BaudrateSelector;
-- generate output
NextStep_o <= '1' when SPR = 0 and SPPR = 0 else
'0';
end RTL;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/core/tb/uart/errorbit-e.vhd | 1 | 923 | ----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Armin FALTINGER
--
-- Create Date: 10:21:09 12/25/2009
-- Module Name: ErrorBit - RTL
-- Project Name: Uart
-- Description: Indicate possible errors,
-- clearing the error with a global reset (Reset_i_n)
-- or the dedicated error reset (ErrorReset)
--
-- Dependencies: pure RTL no dependencies
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ErrorBit is
Port ( Clk_i : in STD_LOGIC;
Reset_i_n : in STD_LOGIC;
ErrorReset_i : in STD_LOGIC;
ErrorBit_i : in STD_LOGIC;
ErrorIndicatorBit_o : out STD_LOGIC);
end ErrorBit;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/reconfmodule/chll/out/reconflogic-cmp.vhd | 1 | 2055 | -- Automatically generated: write_netlist -preliminary -vhdl -component reconflogic-cmp.vhd
component MyReconfigLogic
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0);
I2C_Busy_i : in std_logic;
I2C_DataIn_o : out std_logic_vector(7 downto 0);
I2C_DataOut_i : in std_logic_vector(7 downto 0);
I2C_Divider800_o : out std_logic_vector(15 downto 0);
I2C_ErrAckParam_o : out std_logic;
I2C_Error_i : in std_logic;
I2C_F100_400_n_o : out std_logic;
I2C_FIFOEmpty_i : in std_logic;
I2C_FIFOFull_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(3 downto 0);
I2C_ReceiveSend_n_o : out std_logic;
I2C_StartProcess_o : out std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
ReconfModuleIRQs_o : out std_logic_vector(4 downto 0);
SPI_CPHA_o : out std_logic;
SPI_CPOL_o : out std_logic;
SPI_DataIn_o : out std_logic_vector(7 downto 0);
SPI_DataOut_i : in std_logic_vector(7 downto 0);
SPI_FIFOEmpty_i : in std_logic;
SPI_FIFOFull_i : in std_logic;
SPI_LSBFE_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_SPPR_SPR_o : out std_logic_vector(7 downto 0);
SPI_Transmission_i : in std_logic;
SPI_Write_o : out std_logic;
ReconfModuleIn_i : in std_logic_vector(7 downto 0);
ReconfModuleOut_o : out std_logic_vector(7 downto 0);
I2C_Errors_i : in std_logic_vector(7 downto 0);
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgIntfDOut_o : out std_logic_vector(15 downto 0);
ParamIntfDOut_o : out std_logic_vector(15 downto 0)
);
end component;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682mean/chll/out/max6682mean-wrapintersynth.vhd | 1 | 12817 | -- Automatically generated: write_netlist -wrapis -vhdl -module max6682mean-wrapintersynth.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAX6682Mean is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
MAX6682CS_n_o : out std_logic;
SPI_Data_i : in std_logic_vector(7 downto 0);
SPI_Write_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Data_o : out std_logic_vector(7 downto 0);
SPI_FIFOFull_i : in std_logic;
SPI_FIFOEmpty_i : in std_logic;
SPI_Transmission_i : in std_logic;
PauseCounterPreset_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
SPI_CPOL_o : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_LSBFE_o : out std_logic
);
attribute intersynth_port : string;
attribute intersynth_conntype : string;
attribute intersynth_param : string;
attribute intersynth_port of Reset_n_i : signal is "Reset_n_i";
attribute intersynth_port of Clk_i : signal is "Clk_i";
attribute intersynth_port of Enable_i : signal is "ReconfModuleIn_s";
attribute intersynth_conntype of Enable_i : signal is "Bit";
attribute intersynth_port of CpuIntr_o : signal is "ReconfModuleIRQs_s";
attribute intersynth_conntype of CpuIntr_o : signal is "Bit";
attribute intersynth_port of MAX6682CS_n_o : signal is "Outputs_o";
attribute intersynth_conntype of MAX6682CS_n_o : signal is "Bit";
attribute intersynth_port of SPI_Data_i : signal is "SPI_DataOut";
attribute intersynth_conntype of SPI_Data_i : signal is "Byte";
attribute intersynth_port of SPI_Write_o : signal is "SPI_Write";
attribute intersynth_conntype of SPI_Write_o : signal is "Bit";
attribute intersynth_port of SPI_ReadNext_o : signal is "SPI_ReadNext";
attribute intersynth_conntype of SPI_ReadNext_o : signal is "Bit";
attribute intersynth_port of SPI_Data_o : signal is "SPI_DataIn";
attribute intersynth_conntype of SPI_Data_o : signal is "Byte";
attribute intersynth_port of SPI_FIFOFull_i : signal is "SPI_FIFOFull";
attribute intersynth_conntype of SPI_FIFOFull_i : signal is "Bit";
attribute intersynth_port of SPI_FIFOEmpty_i : signal is "SPI_FIFOEmpty";
attribute intersynth_conntype of SPI_FIFOEmpty_i : signal is "Bit";
attribute intersynth_port of SPI_Transmission_i : signal is "SPI_Transmission";
attribute intersynth_conntype of SPI_Transmission_i : signal is "Bit";
attribute intersynth_param of PauseCounterPreset_i : signal is "PauseCounterPreset_i";
attribute intersynth_conntype of PauseCounterPreset_i : signal is "Word";
attribute intersynth_param of PeriodCounterPresetH_i : signal is "PeriodCounterPresetH_i";
attribute intersynth_conntype of PeriodCounterPresetH_i : signal is "Word";
attribute intersynth_param of PeriodCounterPresetL_i : signal is "PeriodCounterPresetL_i";
attribute intersynth_conntype of PeriodCounterPresetL_i : signal is "Word";
attribute intersynth_param of SensorValue_o : signal is "SensorValue_o";
attribute intersynth_conntype of SensorValue_o : signal is "Word";
attribute intersynth_param of Threshold_i : signal is "Threshold_i";
attribute intersynth_conntype of Threshold_i : signal is "Word";
attribute intersynth_port of SPI_CPOL_o : signal is "SPI_CPOL";
attribute intersynth_conntype of SPI_CPOL_o : signal is "Bit";
attribute intersynth_port of SPI_CPHA_o : signal is "SPI_CPHA";
attribute intersynth_conntype of SPI_CPHA_o : signal is "Bit";
attribute intersynth_port of SPI_LSBFE_o : signal is "SPI_LSBFE";
attribute intersynth_conntype of SPI_LSBFE_o : signal is "Bit";
end MAX6682Mean;
architecture WrapInterSynth of MAX6682Mean is
component MyInterSynthModule
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
bitdata : in std_logic_vector(1281 downto 0);
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(15 downto 0);
I2C_Busy_i : in std_logic;
I2C_DataIn_o : out std_logic_vector(7 downto 0);
I2C_DataOut_i : in std_logic_vector(7 downto 0);
I2C_Error_i : in std_logic;
I2C_FIFOEmpty_i : in std_logic;
I2C_FIFOFull_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(7 downto 0);
I2C_ReceiveSend_n_o : out std_logic;
I2C_StartProcess_o : out std_logic;
Inputs_i_0 : in std_logic;
Inputs_i_1 : in std_logic;
Inputs_i_2 : in std_logic;
Inputs_i_3 : in std_logic;
Inputs_i_4 : in std_logic;
Inputs_i_5 : in std_logic;
Inputs_i_6 : in std_logic;
Inputs_i_7 : in std_logic;
Outputs_o_0 : out std_logic;
Outputs_o_1 : out std_logic;
Outputs_o_2 : out std_logic;
Outputs_o_3 : out std_logic;
Outputs_o_4 : out std_logic;
Outputs_o_5 : out std_logic;
Outputs_o_6 : out std_logic;
Outputs_o_7 : out std_logic;
ReconfModuleIRQs_o_0 : out std_logic;
ReconfModuleIRQs_o_1 : out std_logic;
ReconfModuleIRQs_o_2 : out std_logic;
ReconfModuleIRQs_o_3 : out std_logic;
ReconfModuleIRQs_o_4 : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_CPOL_o : out std_logic;
SPI_DataIn_o : out std_logic_vector(7 downto 0);
SPI_DataOut_i : in std_logic_vector(7 downto 0);
SPI_FIFOEmpty_i : in std_logic;
SPI_FIFOFull_i : in std_logic;
SPI_LSBFE_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Transmission_i : in std_logic;
SPI_Write_o : out std_logic;
ReconfModuleIn_i_0 : in std_logic;
ReconfModuleIn_i_1 : in std_logic;
ReconfModuleIn_i_2 : in std_logic;
ReconfModuleIn_i_3 : in std_logic;
ReconfModuleIn_i_4 : in std_logic;
ReconfModuleIn_i_5 : in std_logic;
ReconfModuleIn_i_6 : in std_logic;
ReconfModuleIn_i_7 : in std_logic;
ReconfModuleOut_o_0 : out std_logic;
ReconfModuleOut_o_1 : out std_logic;
ReconfModuleOut_o_2 : out std_logic;
ReconfModuleOut_o_3 : out std_logic;
ReconfModuleOut_o_4 : out std_logic;
ReconfModuleOut_o_5 : out std_logic;
ReconfModuleOut_o_6 : out std_logic;
ReconfModuleOut_o_7 : out std_logic;
ParamIn_Word_i : in std_logic_vector(79 downto 0);
ParamOut_Word_o : out std_logic_vector(31 downto 0);
CfgMode_i : in std_logic;
CfgClk_TRFSM0_i : in std_logic;
CfgClk_TRFSM1_i : in std_logic;
CfgShift_TRFSM0_i : in std_logic;
CfgShift_TRFSM1_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_TRFSM0_o : out std_logic;
CfgDataOut_TRFSM1_o : out std_logic
);
end component;
signal ParamIn_Word_s : std_logic_vector(79 downto 0);
signal ParamOut_Word_s : std_logic_vector(31 downto 0);
signal BitData_s : std_logic_vector(1281 downto 0);
signal CfgDataOut_TRFSM0_s : std_logic;
signal CfgDataOut_TRFSM1_s : std_logic;
signal AdcDoConvert_o_s : std_logic;
signal I2C_DataIn_o_s : std_logic_vector(7 downto 0);
signal I2C_FIFOReadNext_o_s : std_logic;
signal I2C_FIFOWrite_o_s : std_logic;
signal I2C_ReadCount_o_s : std_logic_vector(7 downto 0);
signal I2C_ReceiveSend_n_o_s : std_logic;
signal I2C_StartProcess_o_s : std_logic;
signal Outputs_o_1_s : std_logic;
signal Outputs_o_2_s : std_logic;
signal Outputs_o_3_s : std_logic;
signal Outputs_o_4_s : std_logic;
signal Outputs_o_5_s : std_logic;
signal Outputs_o_6_s : std_logic;
signal Outputs_o_7_s : std_logic;
signal ReconfModuleIRQs_o_1_s : std_logic;
signal ReconfModuleIRQs_o_2_s : std_logic;
signal ReconfModuleIRQs_o_3_s : std_logic;
signal ReconfModuleIRQs_o_4_s : std_logic;
signal ReconfModuleOut_o_0_s : std_logic;
signal ReconfModuleOut_o_1_s : std_logic;
signal ReconfModuleOut_o_2_s : std_logic;
signal ReconfModuleOut_o_3_s : std_logic;
signal ReconfModuleOut_o_4_s : std_logic;
signal ReconfModuleOut_o_5_s : std_logic;
signal ReconfModuleOut_o_6_s : std_logic;
signal ReconfModuleOut_o_7_s : std_logic;
begin
MyInterSynthModule_0: MyInterSynthModule
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
ReconfModuleIn_i_0 => Enable_i,
ReconfModuleIRQs_o_0 => CpuIntr_o,
Outputs_o_0 => MAX6682CS_n_o,
SPI_DataOut_i => SPI_Data_i,
SPI_Write_o => SPI_Write_o,
SPI_ReadNext_o => SPI_ReadNext_o,
SPI_DataIn_o => SPI_Data_o,
SPI_FIFOFull_i => SPI_FIFOFull_i,
SPI_FIFOEmpty_i => SPI_FIFOEmpty_i,
SPI_Transmission_i => SPI_Transmission_i,
ParamIn_Word_i => ParamIn_Word_s,
ParamOut_Word_o => ParamOut_Word_s,
SPI_CPOL_o => SPI_CPOL_o,
SPI_CPHA_o => SPI_CPHA_o,
SPI_LSBFE_o => SPI_LSBFE_o,
bitdata => BitData_s,
CfgMode_i => '0',
CfgClk_TRFSM0_i => '0',
CfgClk_TRFSM1_i => '0',
CfgShift_TRFSM0_i => '0',
CfgShift_TRFSM1_i => '0',
CfgDataIn_i => '0',
CfgDataOut_TRFSM0_o => CfgDataOut_TRFSM0_s,
CfgDataOut_TRFSM1_o => CfgDataOut_TRFSM1_s,
AdcConvComplete_i => '0',
AdcDoConvert_o => AdcDoConvert_o_s,
AdcValue_i => "0000000000000000",
I2C_Busy_i => '0',
I2C_DataIn_o => I2C_DataIn_o_s,
I2C_DataOut_i => "00000000",
I2C_Error_i => '0',
I2C_FIFOEmpty_i => '0',
I2C_FIFOFull_i => '0',
I2C_FIFOReadNext_o => I2C_FIFOReadNext_o_s,
I2C_FIFOWrite_o => I2C_FIFOWrite_o_s,
I2C_ReadCount_o => I2C_ReadCount_o_s,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n_o_s,
I2C_StartProcess_o => I2C_StartProcess_o_s,
Inputs_i_0 => '0',
Inputs_i_1 => '0',
Inputs_i_2 => '0',
Inputs_i_3 => '0',
Inputs_i_4 => '0',
Inputs_i_5 => '0',
Inputs_i_6 => '0',
Inputs_i_7 => '0',
Outputs_o_1 => Outputs_o_1_s,
Outputs_o_2 => Outputs_o_2_s,
Outputs_o_3 => Outputs_o_3_s,
Outputs_o_4 => Outputs_o_4_s,
Outputs_o_5 => Outputs_o_5_s,
Outputs_o_6 => Outputs_o_6_s,
Outputs_o_7 => Outputs_o_7_s,
ReconfModuleIRQs_o_1 => ReconfModuleIRQs_o_1_s,
ReconfModuleIRQs_o_2 => ReconfModuleIRQs_o_2_s,
ReconfModuleIRQs_o_3 => ReconfModuleIRQs_o_3_s,
ReconfModuleIRQs_o_4 => ReconfModuleIRQs_o_4_s,
ReconfModuleIn_i_1 => '0',
ReconfModuleIn_i_2 => '0',
ReconfModuleIn_i_3 => '0',
ReconfModuleIn_i_4 => '0',
ReconfModuleIn_i_5 => '0',
ReconfModuleIn_i_6 => '0',
ReconfModuleIn_i_7 => '0',
ReconfModuleOut_o_0 => ReconfModuleOut_o_0_s,
ReconfModuleOut_o_1 => ReconfModuleOut_o_1_s,
ReconfModuleOut_o_2 => ReconfModuleOut_o_2_s,
ReconfModuleOut_o_3 => ReconfModuleOut_o_3_s,
ReconfModuleOut_o_4 => ReconfModuleOut_o_4_s,
ReconfModuleOut_o_5 => ReconfModuleOut_o_5_s,
ReconfModuleOut_o_6 => ReconfModuleOut_o_6_s,
ReconfModuleOut_o_7 => ReconfModuleOut_o_7_s
);
ParamIn_Word_s(15 downto 0) <= PauseCounterPreset_i;
ParamIn_Word_s(63 downto 48) <= PeriodCounterPresetH_i;
ParamIn_Word_s(47 downto 32) <= PeriodCounterPresetL_i;
SensorValue_o <= ParamOut_Word_s(15 downto 0);
ParamIn_Word_s(31 downto 16) <= Threshold_i;
ParamIn_Word_s(79 downto 64) <= "0000000000000000";
BitData_s <= "0000000000000000000000000000000000000000000000000000000000000000101011010100000000000000100100000000100000000000000000000000000000000001000000000000000000000000000000000010001000001000000000000110010010000110000000000010001011000000000000000000000000000100100000000000000000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001101010110110100000110010000000000000000000000000100110101011100000000000011110100101010001000010001010001001100000000000000000000000000000000000000000100011001000110001100011000110011101011000000100001111011010100011000110001100010000011000010001101000000010001111011010100010000111000001001010001010000000000000000000001000000000011000001110101000000000000010000010100010110100000000000000000000000100000001000100000000011010100010100000010000011100011001101011000000000000001100101000000000001000100000000000000000000000000001000000000000000000000000000000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000000";
end WrapInterSynth;
| gpl-2.0 |
elegabriel/myzju | junior1/CA/mips_pipeline2/ipcore_dir/Data_Mem/simulation/Data_Mem_synth.vhd | 1 | 8170 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Data_Mem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY Data_Mem_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE Data_Mem_synth_ARCH OF Data_Mem_synth IS
COMPONENT Data_Mem_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: Data_Mem_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-2.0 |
elegabriel/myzju | junior1/CA/mips_pipeline2/ipcore_dir/Data_Mem/example_design/Data_Mem_exdes.vhd | 1 | 4774 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Data_Mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Data_Mem_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Data_Mem_exdes;
ARCHITECTURE xilinx OF Data_Mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Data_Mem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Data_Mem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/celllib/addsubcmp/tb/addsubcmp_tb.vhd | 1 | 10203 | -------------------------------------------------------------------------------
-- Title : Testbench for design "AddSubCmp"
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tbfuncs.all;
-------------------------------------------------------------------------------
entity AddSubCmp_tb is
end AddSubCmp_tb;
-------------------------------------------------------------------------------
architecture behavior of AddSubCmp_tb is
component AddSubCmp
generic (
Width : integer
);
port (
AddOrSub_i : in std_logic;
A_i : in std_logic_vector(Width-1 downto 0);
B_i : in std_logic_vector(Width-1 downto 0);
D_o : out std_logic_vector(Width-1 downto 0);
Carry_i : in std_logic;
Carry_o : out std_logic;
Zero_o : out std_logic;
Sign_o : out std_logic;
Overflow_o : out std_logic
);
end component;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
-- component generics
constant Width : integer := 4;
-- component ports
signal AddOrSub_i : std_logic;
signal A_i : std_logic_vector(Width-1 downto 0);
signal B_i : std_logic_vector(Width-1 downto 0);
signal D_o : std_logic_vector(Width-1 downto 0);
signal Carry_i : std_logic;
signal Carry_o : std_logic;
signal Zero_o : std_logic;
signal Sign_o : std_logic;
signal Overflow_o : std_logic;
procedure CheckAddSubCmp (
constant A : in integer;
constant B : in integer;
constant CarryIn : in std_logic;
constant AddOrSub : in std_logic;
constant SignedCalc : in boolean;
signal A_i : out std_logic_vector(Width-1 downto 0);
signal B_i : out std_logic_vector(Width-1 downto 0);
signal Carry_i : out std_logic;
signal AddOrSub_i : out std_logic;
signal D_o : in std_logic_vector(Width-1 downto 0);
signal Carry_o : in std_logic;
signal Zero_o : in std_logic;
signal Sign_o : in std_logic;
signal Overflow_o : in std_logic
) is
variable A_s : std_logic_vector(Width+1 downto 0);
variable B_s : std_logic_vector(Width+1 downto 0);
variable A_v : integer;
variable B_v : integer;
variable D : integer;
variable D_s : std_logic_vector(Width+1 downto 0);
variable Carry : std_logic;
variable Zero : std_logic;
variable Sign : std_logic;
variable Overflow : std_logic;
variable Temp : integer;
begin -- CheckAddSubCmp
if not SignedCalc then
-- unsigned
assert A < 2**Width report "A is too large (" & integer'image(A) & " > " & integer'image(2**Width-1) severity failure;
assert A >= 0 report "A is too small (" & integer'image(A) & " < " & integer'image(0 ) severity failure;
assert B < 2**Width report "B is too large (" & integer'image(A) & " > " & integer'image(2**Width-1) severity failure;
assert B >= 0 report "B is too small (" & integer'image(A) & " < " & integer'image(0 ) severity failure;
else
-- signed
assert A < 2**(Width-1) report "A is too large (" & integer'image(A) & " > " & integer'image( 2**(Width-1)-1) severity failure;
assert A >= -2**(Width-1) report "A is too small (" & integer'image(A) & " < " & integer'image(-2**(Width-1) ) severity failure;
assert B < 2**(Width-1) report "B is too large (" & integer'image(A) & " > " & integer'image( 2**(Width-1)-1) severity failure;
assert B >= -2**(Width-1) report "B is too small (" & integer'image(A) & " < " & integer'image(-2**(Width-1) ) severity failure;
end if;
-- set defaults
Zero := '0';
Carry := '0';
-- Calculation
A_v := A;
B_v := B;
if A_v < 0 then
A_v := A_v + 2**Width;
end if;
if B_v < 0 then
B_v := B_v + 2**Width;
end if;
if CarryIn = '1' then
if AddOrSub = '0' then
-- add
A_v := A_v + 1;
else
-- sub
A_v := A_v - 1;
end if;
end if;
if AddOrSub = '1' then
B_v := 2**Width - B_v;
end if;
D := A_v + B_v;
A_s := std_logic_vector(to_signed(A,Width+2)); -- use Width+2 to avoid warnings on a truncated vector by to_signed
B_s := std_logic_vector(to_signed(B,Width+2));
D_s := std_logic_vector(to_signed(D,Width+2));
if D > 2**Width-1 then
Carry := '1';
end if;
if unsigned(D_s(Width-1 downto 0)) = 0 then
Zero := '1';
end if;
Sign := D_s(Width-1);
if AddOrSub = '0' then
Overflow := ((not A_s(Width-1)) and (not B_s(Width-1)) and D_s(Width-1) ) or
( A_s(Width-1) and B_s(Width-1) and (not D_s(Width-1)));
else
Overflow := ((not A_s(Width-1)) and B_s(Width-1) and D_s(Width-1) ) or
( A_s(Width-1) and (not B_s(Width-1)) and (not D_s(Width-1)));
end if;
-- set inputs
A_i <= A_s(Width-1 downto 0);
B_i <= B_s(Width-1 downto 0);
Carry_i <= CarryIn;
AddOrSub_i <= AddOrSub;
wait for CheckOutputDelay;
-- check outputs
assert D_o = D_s(Width-1 downto 0)
report "Wrong Result " & Vector2String(D_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & Vector2String(D_s) severity error;
assert Carry_o = Carry report "Wrong Carry " & std_logic'image(Carry_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & std_logic'image(Carry) severity error;
assert Zero_o = Zero report "Wrong Zero " & std_logic'image(Zero_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & std_logic'image(Zero) severity error;
assert Sign_o = Sign report "Wrong Sign " & std_logic'image(Sign_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & std_logic'image(Sign) severity error;
assert Overflow_o = Overflow report "Wrong Overflow " & std_logic'image(Overflow_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & std_logic'image(Overflow) severity error;
wait for SetupNextInputDelay;
end CheckAddSubCmp;
begin -- behavior
-- component instantiation
DUT: AddSubCmp
generic map (
Width => Width)
port map (
AddOrSub_i => AddOrSub_i,
A_i => A_i,
B_i => B_i,
D_o => D_o,
Carry_i => Carry_i,
Carry_o => Carry_o,
Zero_o => Zero_o,
Sign_o => Sign_o,
Overflow_o => Overflow_o);
-- Check
CheckProc: process
begin
wait for 10 ns;
-- add, unsigned, CarryIn = '0'
assert false report "Add, unsigned, CarryIn = 0" severity note;
for A in 0 to 2**Width-1 loop
for B in 0 to 2**Width-1 loop
CheckAddSubCmp(A,B,'0','0',false, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- add, unsigned, CarryIn = '1'
assert false report "Add, unsigned, CarryIn = 1" severity note;
for A in 0 to 2**Width-1 loop
for B in 0 to 2**Width-1 loop
CheckAddSubCmp(A,B,'1','0',false, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- add, signed, CarryIn = '0'
assert false report "Add, signed, CarryIn = 0" severity note;
for A in -(2**(Width-1)) to 2**(Width-1)-1 loop
for B in -(2**(Width-1)) to 2**(Width-1)-1 loop
CheckAddSubCmp(A,B,'0','0',true, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- add, signed, CarryIn = '1'
assert false report "Add, signed, CarryIn = 1" severity note;
for A in -(2**(Width-1)) to 2**(Width-1)-1 loop
for B in -(2**(Width-1)) to 2**(Width-1)-1 loop
CheckAddSubCmp(A,B,'1','0',true, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- sub, unsigned, CarryIn = '0'
assert false report "Sub, unsigned, CarryIn = 0" severity note;
for A in 0 to 2**Width-1 loop
for B in 0 to 2**Width-1 loop
CheckAddSubCmp(A,B,'0','1',false, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- sub, unsigned, CarryIn = '1'
assert false report "Sub, unsigned, CarryIn = 1" severity note;
for A in 0 to 2**Width-1 loop
for B in 0 to 2**Width-1 loop
CheckAddSubCmp(A,B,'1','1',false, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- sub, signed, CarryIn = '0'
assert false report "Sub, signed, CarryIn = 0" severity note;
for A in -(2**(Width-1)) to 2**(Width-1)-1 loop
for B in -(2**(Width-1)) to 2**(Width-1)-1 loop
CheckAddSubCmp(A,B,'0','1',true, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- sub, signed, CarryIn = '1'
assert false report "Sub, signed, CarryIn = 1" severity note;
for A in -(2**(Width-1)) to 2**(Width-1)-1 loop
for B in -(2**(Width-1)) to 2**(Width-1)-1 loop
CheckAddSubCmp(A,B,'1','1',true, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
---------------------------------------------------------------------------
-- Simulation is finished
---------------------------------------------------------------------------
assert false
report "### simulation is finished ###"
severity failure ;
end process CheckProc;
end behavior;
configuration AddSubCmp_tb_verilog_cfg of AddSubCmp_tb is
for behavior
for DUT : AddSubCmp
use configuration work.AddSubCmpVerilog;
end for;
end for;
end AddSubCmp_tb_verilog_cfg;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7310/tb/chip_power_tb.vhd | 1 | 26945 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.UartPkg.all;
entity Chip_Power_tb is
generic (
SPISelect : integer := 1; -- 0: CPU, 1: CHLL
ImpulseGen : integer := 0 -- 0: no, 1: connect Inputs_i(7) to a signal with pulses for wakeup from LPM3
);
end Chip_Power_tb;
architecture behavior of Chip_Power_tb is
component Chip
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_b : inout std_logic;
P1_b : inout std_logic_vector(7 downto 0);
P2_b : inout std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_b : out std_logic;
I2CSDA_b : inout std_logic;
-- OneWire_b : inout std_logic;
-- PWM_i : in std_logic;
-- SENT_i : in std_logic;
-- SPC_b : inout std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component adt7310_model
port (
SCLK_i : in std_logic;
DOUT_o : out std_logic;
DIN_i : in std_logic;
CS_n_i : in std_logic;
CT_n_o : out std_logic;
INT_n_o : out std_logic;
Temp_i : in real);
end component;
-- component ExtNames
-- port (
-- SPIFSM_Done : out std_logic;
-- CpuIntr : out std_logic;
-- SensorValue : out std_logic_vector(15 downto 0)
-- );
-- end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic;
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic;
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic;
signal Dbg_SDA_b : std_logic;
signal P1_b : std_logic_vector(7 downto 0);
signal P2_b : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic;
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic;
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_b : std_logic;
signal I2CSDA_b : std_logic;
-- signal OneWire_b : std_logic;
-- signal PWM_i : std_logic;
-- signal SENT_i : std_logic;
-- signal SPC_b : std_logic;
signal AdcConvComplete_i : std_logic;
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0);
-- -- look into the ADT7310 app
-- -- alias SPIFSM_Done_i is << signal .adt7310_tb.DUT.SPIFSM_Done_s : std_logic >>;
-- -- ModelSim complains here, that the references signal is not a VHDL object.
-- -- True, this is a Verilog object. As a workaround the module ExtNames is created
-- -- which uses Verilog hierarchical names to reference the wire and assigns it to
-- -- an output. This module is instantiated (and it seems ModelSim only adds
-- -- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- -- connected with the SPIFSM_Done_i signal.
-- signal SPIFSM_Done_e : std_logic; -- directly from inside SPI_FSM
-- signal CpuIntr_e : std_logic; -- directly from inside SPI_FSM
-- signal SensorValue_e : std_logic_vector(15 downto 0);
-- -- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- -- SPIFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- -- on the ANDed value.
-- signal SPIFSM_Done_d : std_logic; -- sightly delayed
-- signal CpuIntr_o : std_logic; -- sightly delayed
-- signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
-- signal SensorValue_real : real;
signal Clk_s : std_logic := '1';
signal RTC_s : std_logic := '1';
signal ClkEnable_s : std_logic := '0';
signal RTCEnable_s : std_logic := '0';
signal RTC_i : std_logic;
type ImpulseGenState_t is (igsIdle,igsPulse1,igsWait1,igsPulse2,igsWait2);
signal ImpulseGenState : ImpulseGenState_t := igsIdle;
signal ImpulseGen_s : std_logic := '0';
-- default values, the firmware relies on these!
constant MCUStdClkDiv : integer := 24; -- standard frequency of 100/(24+1) = 4MHz for MCU UART for 9600 baud
constant RTCClockDivider : integer := 3051;
-- setup values for testpoint
signal ClkDiv : integer := 99; -- 100MHz/(99+1) = 1MHz
signal ClkDivRTC : integer := 3051; -- 100MHz/(3051+1) = 32.765kHz
signal Threshold : integer := 100;
signal CycleTime : integer := 5;
signal BusDivider : integer := 1;
-- derived values from setup values
signal ClkPeriode : time := 10 ns * (MCUStdClkDiv+1);
signal RTCPeriode : time := 10 ns * (RTCClockDivider+1);
-- simulation control signals: these will be set using "force" by the simulator
signal HaveTestpoint : boolean := true;
-- Trigger to start/stop the power analysis
signal TriggerEnable_s : std_logic := '0';
signal TriggerSPI_s : std_logic := '0';
signal TriggerManual_s : std_logic := '0';
signal Trigger_s : std_logic := '0';
signal Triggered_s : std_logic := '0'; -- stays '1' until ResetTriggered_s is asserted
signal ResetTriggered_s : std_logic := '0';
-- ADT7310 component ports
signal ADT7310CS_n_s : std_logic;
signal ADT7310MISO_s : std_logic;
signal ADT7310MOSI_s : std_logic;
signal ADT7310SCK_s : std_logic;
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
component Uart
generic (
MaxDataWidth : integer range 5 to 9;
MaxSpeedDividerWidth : integer range 2 to 32;
TxFifoAdressWidth : integer range 2 to 10;
RxFifoAdressWidth : integer range 2 to 10;
Oversampling : integer range 2 to 2);
port (
TxData_i : in STD_LOGIC_VECTOR((MaxDataWidth-1) downto 0);
TxWr_i : in STD_LOGIC;
TxEmpty_o : out STD_LOGIC;
TxFull_o : out STD_LOGIC;
RxData_o : out STD_LOGIC_VECTOR((MaxDataWidth-1) downto 0);
RxRd_i : in STD_LOGIC;
RxFull_o : out STD_LOGIC;
RxEmpty_o : out STD_LOGIC;
BitsSelect_i : in BitSelectionType;
ParityOn_i : in STD_LOGIC;
ParityEvenOdd_i : in ParityType;
SpeedDivider_i : in STD_LOGIC_VECTOR((MaxSpeedDividerWidth-1) downto 0);
Clk_i : in STD_LOGIC;
Reset_i_n : in STD_LOGIC;
ErrorReset_i : in STD_LOGIC;
RxParityErrorIndicator_o : out STD_LOGIC;
RxStopBitErrorIndicator_o : out STD_LOGIC;
RxBufferFullErrorIndicator_o : out STD_LOGIC;
TxD_o : out STD_LOGIC;
RxD_i : in STD_LOGIC;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
constant MaxDataWidth : integer range 5 to 9 := 8;
constant MaxSpeedDividerWidth : integer range 2 to 32 := 16;
constant TxFifoAdressWidth : integer range 2 to 10 := 4;
constant RxFifoAdressWidth : integer range 2 to 10 := 4;
constant Oversampling : integer range 2 to 2 := 2;
-- clock_freq/(2**Oversampling * Baudrate)
-- 4MHz/(2**2 * 9600) = 104.1666 rounded --> 104
-- baudrate = clock_frequency / (2**Oversampling * SpeedDivider) = 4MHz / (2**2 * 104) = 9615.4
-- error: (9615.4-9600)/9600 = -0.0016
-- 9600 Baud is very slow in simulation, so we use 115200 Baud
-- 4MHz/(2**2 * 115200) = 8.68055 rounded --> 9
-- baudrate = clock_frequency / (2**Oversampling * SpeedDivider) = 4MHz / (2**2 * 9) = 111111.1
-- error: (111111.111111-115200)/115200 = -0.0354938271615
constant SpeedDivider : integer := 9;
signal TxData_i : STD_LOGIC_VECTOR((MaxDataWidth-1) downto 0) := (others => '0');
signal TxWr_i : STD_LOGIC := '0';
signal TxEmpty_o : STD_LOGIC;
signal TxFull_o : STD_LOGIC;
signal RxData_o : STD_LOGIC_VECTOR((MaxDataWidth-1) downto 0);
signal RxRd_i : STD_LOGIC;
signal RxFull_o : STD_LOGIC;
signal RxEmpty_o : STD_LOGIC;
signal BitsSelect_i : BitSelectionType := Sel8Bits;
signal ParityOn_i : STD_LOGIC := '0';
signal ParityEvenOdd_i : ParityType := Even;
signal SpeedDivider_i : STD_LOGIC_VECTOR((MaxSpeedDividerWidth-1) downto 0) := std_logic_vector(to_unsigned(SpeedDivider,MaxSpeedDividerWidth));
signal ErrorReset_i : STD_LOGIC := '0';
signal RxParityErrorIndicator_o : STD_LOGIC;
signal RxStopBitErrorIndicator_o : STD_LOGIC;
signal RxBufferFullErrorIndicator_o : STD_LOGIC;
signal ScanEnable_i : std_logic := '0';
signal ScanClk_i : std_logic := '0';
signal ScanDataIn_i : std_logic := '0';
signal ScanDataOut_o : std_logic;
subtype Byte is std_logic_vector(7 downto 0);
signal UartRx : Byte := (others => '0');
signal UartCh : character := NUL;
constant UartRxFifoAddrWidth : integer := 4;
type UartRxFifo_t is array(0 to (2**UartRxFifoAddrWidth-1)) of character;
signal UartRxFifo : UartRxFifo_t;
signal UartRxFifoWr : integer := 0;
signal UartRxFifoRd : integer := 0;
begin
DUT: Chip
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_b => Dbg_SDA_b,
P1_b => P1_b,
P2_b => P2_b,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_b => I2CSCL_b,
I2CSDA_b => I2CSDA_b,
-- OneWire_b => OneWire_b,
-- PWM_i => PWM_i,
-- SENT_i => SENT_i,
-- SPC_b => SPC_b,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
SPISelectCPU: if SPISelect = 0 generate
ADT7310CS_n_s <= P1_b(0);
MISO_i <= ADT7310MISO_s ;
ADT7310MOSI_s <= MOSI_o;
ADT7310SCK_s <= SCK_o;
SPIMISO_i <= '0';
end generate;
SPISelectCHLL: if SPISelect = 1 generate
ADT7310CS_n_s <= Outputs_o(0);
SPIMISO_i <= ADT7310MISO_s ;
ADT7310MOSI_s <= SPIMOSI_o;
ADT7310SCK_s <= SPISCK_o;
MISO_i <= '0';
end generate;
ImpulseGenNo: if ImpulseGen = 0 generate
Inputs_i <= (others => '0');
end generate;
ImpulseGenYes: if ImpulseGen = 1 generate
ImpulseGenProc: process(TriggerEnable_s, Clk_s)
variable NextEvent : time := 0.0 ns;
begin
if rising_edge(TriggerEnable_s) then
-- start with pulse generation
ImpulseGenState <= igsPulse1; -- trick: MCU is already waiting in the 2ms periode, so we skip the first pulse and directly enter in the waiting periode
ImpulseGen_s <= '0';
NextEvent := now + 5 * (10 ns * (ClkDiv+1)); -- 5 Clk cycles
elsif falling_edge(TriggerEnable_s) then
-- stop with pulse generation
ImpulseGenState <= igsIdle;
ImpulseGen_s <= '0';
end if;
if now >= NextEvent then
-- ok, we have something to do
case ImpulseGenState is
when igsIdle => null;
when igsPulse1 =>
-- end of first pulse
ImpulseGen_s <= '0';
NextEvent := now + 1.85 ms;
ImpulseGenState <= igsWait1;
when igsWait1 =>
-- begin second pulse
ImpulseGen_s <= '1';
NextEvent := now + 5 * (10 ns * (ClkDiv+1)); -- 5 Clk cycles
ImpulseGenState <= igsPulse2;
when igsPulse2 =>
-- end of second pulse
ImpulseGen_s <= '0';
NextEvent := now + (real(CycleTime)-1.85) * 1 ms;
ImpulseGenState <= igsWait2;
when igsWait2 =>
-- begin of first pulse
ImpulseGen_s <= '1';
NextEvent := now + 5 * (10 ns * (ClkDiv+1)); -- 5 Clk cycles
ImpulseGenState <= igsPulse1;
when others =>
report "Invalid ImpulseGenState" severity failure;
end case;
end if;
end process ImpulseGenProc;
Inputs_i <= (7 => ImpulseGen_s, others => '0');
end generate;
Cpu_En_i <= '1';
Dbg_En_i <= '0';
-- Dbg_UART_RxD_i <= '1';
Dbg_SCL_i <= 'H';
Dbg_SDA_b <= 'H';
P1_b <= (others => 'H');
P2_b <= (1 => RTC_i, others => 'H');
I2CSCL_b <= 'H';
I2CSDA_b <= 'H';
-- OneWire_b <= 'H';
-- PWM_i <= 'H';
-- SENT_i <= 'H';
-- SPC_b <= 'H';
AdcConvComplete_i <= '0';
AdcValue_i <= (others => '0');
-- ExtNames_1: ExtNames
-- port map (
-- SPIFSM_Done => SPIFSM_Done_e,
-- CpuIntr => CpuIntr_e,
-- SensorValue => SensorValue_e
-- );
-- SPIFSM_Done_d <= SPIFSM_Done_e after 1.0 ns;
-- CpuIntr_o <= CpuIntr_e after 1.0 ns;
-- SensorValue_o <= SensorValue_e after 1.0 ns;
--
-- SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
adt7310_1: adt7310_model
port map (
SCLK_i => ADT7310SCK_s,
DOUT_o => ADT7310MISO_s,
DIN_i => ADT7310MOSI_s,
CS_n_i => ADT7310CS_n_s,
CT_n_o => CT_n_s,
INT_n_o => INT_n_s,
Temp_i => Temp_s);
Uart_1: Uart
generic map (
MaxDataWidth => MaxDataWidth,
MaxSpeedDividerWidth => MaxSpeedDividerWidth,
TxFifoAdressWidth => TxFifoAdressWidth,
RxFifoAdressWidth => RxFifoAdressWidth,
Oversampling => Oversampling
)
port map (
TxData_i => TxData_i,
TxWr_i => TxWr_i,
TxEmpty_o => TxEmpty_o,
TxFull_o => TxFull_o,
RxData_o => RxData_o,
RxRd_i => RxRd_i,
RxFull_o => RxFull_o,
RxEmpty_o => RxEmpty_o,
BitsSelect_i => BitsSelect_i,
ParityOn_i => ParityOn_i,
ParityEvenOdd_i => ParityEvenOdd_i,
SpeedDivider_i => SpeedDivider_i,
Clk_i => Clk_i,
Reset_i_n => Reset_n_i,
ErrorReset_i => ErrorReset_i,
RxParityErrorIndicator_o => RxParityErrorIndicator_o,
RxStopBitErrorIndicator_o => RxStopBitErrorIndicator_o,
RxBufferFullErrorIndicator_o => RxBufferFullErrorIndicator_o,
TxD_o => UartRxD_i,
RxD_i => UartTxD_o,
ScanEnable_i => ScanEnable_i,
ScanClk_i => ScanClk_i,
ScanDataIn_i => ScanDataIn_i,
ScanDataOut_o => ScanDataOut_o
);
-- Generate clock signal
Clk_s <= not Clk_s after ClkPeriode*0.5;
RTC_s <= not RTC_s after RTCPeriode*0.5;
Clk_i <= Clk_s and ClkEnable_s; -- TODO: currently there is no glitch avoidance
RTC_i <= RTC_s and RTCEnable_s;
StimulusProc: process
procedure PutChar (
constant Ch : in character) is
begin -- PutChar
TxWr_i <= '1';
TxData_i <= std_logic_vector(to_unsigned(character'pos(Ch),8));
wait for ClkPeriode;
TxWr_i <= '0';
end PutChar;
-- get received value in the global signal
procedure Recv(
constant Timeout : in time;
variable Ch : out character
) is
variable EndTime : time;
begin
EndTime := now + Timeout;
while (UartRxFifoWr = UartRxFifoRd) and (now < EndTime) loop
-- wait for 1 bit
wait for (2**Oversampling * SpeedDivider) * ClkPeriode;
end loop;
if UartRxFifoWr = UartRxFifoRd then
report "Recv timeout reached" severity failure;
end if;
-- received at least 1 byte
Ch := UartRxFifo(UartRxFifoRd);
UartRxFifoRd <= (UartRxFifoRd+1) mod (2**UartRxFifoAddrWidth); -- no "and" for integers :-(
end Recv;
procedure AssertMCUInitComplete is
variable Ch : character;
begin
Recv(100.0 ms, Ch);
if Ch /= 'I' then
report "Received crap: '" & Ch & "'" severity failure;
end if;
end AssertMCUInitComplete;
procedure SetThreshold(constant Threshold : integer) is
begin
case Threshold is
when 0 => PutChar('q');
when 1 => PutChar('w');
when 2 => PutChar('e');
when 3 => PutChar('r');
when 4 => PutChar('t');
when 5 => PutChar('z');
when 6 => PutChar('u');
when 7 => PutChar('i');
when 8 => PutChar('o');
when 9 => PutChar('p');
when 100 => PutChar('m');
when others =>
report "Invalid threshold " & integer'image(Threshold) severity failure;
end case;
end SetThreshold;
procedure SetCycleTime(constant CycleTime : integer) is
begin
case CycleTime is
when 0 => PutChar('0'); -- no sleep
when 5 => PutChar('a');
when 10 => PutChar('s');
when 20 => PutChar('d');
when 33 => PutChar('f');
when 40 => PutChar('g');
when 50 => PutChar('h');
when 100 => PutChar('j');
when 200 => PutChar('k');
when 2000 => PutChar('l'); -- sleep
when others =>
report "Invalid cycle time " & integer'image(CycleTime) severity failure;
end case;
end SetCycleTime;
procedure SetBusDivider(constant BusDivider : integer) is
begin
case BusDivider is
when 1 => PutChar('b');
when 2 => PutChar('y');
when 4 => PutChar('x');
when 8 => PutChar('c');
when 16 => PutChar('v');
when others =>
report "Invalid busdivider " & integer'image(BusDivider) severity failure;
end case;
end SetBusDivider;
procedure SetFrequencyCompensation(constant ClkDiv : integer) is
begin
case ClkDiv is
when 3051 => PutChar('A');
when 1999 => PutChar('S');
when 999 => PutChar('D');
when 499 => PutChar('F');
when 332 => PutChar('G');
when 249 => PutChar('H');
when 199 => PutChar('J');
when 124 => PutChar('K');
when 99 => PutChar('Q');
when 49 => PutChar('W');
when 32 => PutChar('E');
when 24 => PutChar('R');
when 19 => PutChar('T');
when 15 => PutChar('Z');
when 12 => PutChar('U');
when 11 => PutChar('I');
when 10 => PutChar('O');
when 9 => PutChar('P');
when 0 => SetCycleTime(2000); -- ClkDiv = 0 means frequency = 0, set MCU to sleep mode
when others =>
report "Invalid clock divider " & integer'image(ClkDiv) severity failure;
end case;
end SetFrequencyCompensation;
procedure AssertMCUReady is
variable Ch : character;
begin
PutChar('C'); -- setup complete - continue execution
Recv(100.0 ms, Ch);
if Ch /= 'R' then
report "MCU not ready for measurement." severity failure;
end if;
end AssertMCUReady;
begin
-- TODO: setup SPI Simulator
while HaveTestpoint loop
HaveTestpoint <= false; -- the simulator will set it back to to true if another loop execution is requested
-- setup standard Clk (4MHz) for setup
ClkPeriode <= 10 ns * (MCUStdClkDiv+1);
RTCPeriode <= 10 ns * (RTCClockDivider+1);
ClkEnable_s <= '1';
RTCEnable_s <= '1';
Temp_s <= 0.0; -- degree C, don't disturb the tests
-- reset MCU (but first ensure a fixed relative position to the last Clk edge to avoid complaints of clock gate cells and SRAMs)
wait until rising_edge(Clk_s);
wait for 0.3*ClkPeriode;
report "MCU reset" severity note;
Reset_n_i <= '0';
wait for 2.3*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
wait for 1.3*ClkPeriode; -- wait until spi_master's SCK_o goes '1' to conform to CPOL_i = '1'
-- wait until MCU has initialized, it will send 'I'
AssertMCUInitComplete;
report "MCU startup complete, performing setup: " &
"ClkDiv = " & integer'image(ClkDiv) & ", " &
"ClkDivRTC = " & integer'image(ClkDivRTC) & ", " &
"Threshold = " & integer'image(Threshold) & ", " &
"CycleTime = " & integer'image(CycleTime) & ", " &
"BusDivider = " & integer'image(BusDivider)
severity note;
-- change bus divider according to test point
SetBusDivider(BusDivider);
-- change cycle time according to test point
SetCycleTime(CycleTime);
-- change threshold according to test point
SetThreshold(Threshold);
-- change frequency compensation according to test point
SetFrequencyCompensation(ClkDiv);
-- wait for MCU ready, send 'R' to CPU, it will reply 'C'
AssertMCUReady;
report "MCU setup complete, now starting sensor measurement cycles" severity note;
-- set final clock frequencies
if ClkDiv /= 0 then
ClkPeriode <= 10 ns * (ClkDiv+1);
else
ClkEnable_s <= '0';
end if;
if ClkDivRTC /= 0 then
RTCPeriode <= 10 ns * (ClkDivRTC+1);
else
RTCEnable_s <= '0';
end if;
-- TODO: set impulse durations
-- enable trigger to start the "measurement"
if (CycleTime > 0) and (CycleTime < 2000) and (ClkDiv /= 0) then
-- use trigger
TriggerEnable_s <= '1';
-- reset latching Triggered_s
ResetTriggered_s <= '1';
wait for 1 ns;
ResetTriggered_s <= '0';
-- wait for trigger at most 100ms plus cycle time
for i in 1 to (100+CycleTime) loop
wait for 1 ms;
if Triggered_s = '1' then
exit;
end if;
end loop;
assert Triggered_s = '1' report "Missing trigger" severity error;
-- reset latching Triggered_s
ResetTriggered_s <= '1';
wait for 1 ns;
ResetTriggered_s <= '0';
-- let it do 5 measurement cycles at most
for i in 1 to 5 loop
wait for CycleTime * 1.05 ms; -- wait a bit longer than 1 cycle
if HaveTestpoint then
-- the simulator already has set HaveTestpoint back to true, so we
-- are done waiting and can continue with the outer loop to
-- simulate the next testpoint
exit;
end if;
end loop;
TriggerEnable_s <= '0';
else
-- start immediately, simulate a 200ms delay
wait for 10 ns*(ClkDiv+1) * 100; -- wait 100 Clk cycles until LPMx is established, can't use ClkPeriode in case ClkDiv = 0
TriggerManual_s <= '1';
wait for 10 ns;
TriggerManual_s <= '0';
wait for (200.0 ms - 10.0 ns);
TriggerManual_s <= '1';
wait for 10 ns;
TriggerManual_s <= '0';
wait for 1 us;
end if;
end loop;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
-- trigger detector
TriggerProc: process(TriggerEnable_s, Clk_s, ResetTriggered_s)
variable LastCS_n : std_logic := 'X';
variable LastEvent : time := 0.0 ns;
begin
if rising_edge(TriggerEnable_s) then
LastEvent := now;
end if;
if rising_edge(Clk_s) then
if LastCS_n = '1' and ADT7310CS_n_s = '0' then
if ((now - LastEvent) > 2.8 ms) and (TriggerEnable_s = '1') then
TriggerSPI_s <= '1';
Triggered_s <= '1';
end if;
LastEvent := now;
elsif LastCS_n = '0' and ADT7310CS_n_s = '1' then
TriggerSPI_s <= '0';
end if;
LastCS_n := ADT7310CS_n_s;
end if;
if rising_edge(ResetTriggered_s) then
Triggered_s <= '0';
end if;
end process TriggerProc;
Trigger_s <= TriggerSPI_s or TriggerManual_s;
-- read Uart_1 FIFO
UartRx_Proc: process
begin
RxRd_i <= '0';
wait for 0.2*ClkPeriode;
while true loop
RxRd_i <= not RxEmpty_o;
if RxEmpty_o = '0' then
-- store to variable, because as soon as RxRd_i is '1', RxData_o gives the next value from the FIFO
UartRx <= RxData_o;
UartCh <= character'val(to_integer(unsigned(RxData_o)));
wait for 1 ns; -- update signals
UartRxFifo(UartRxFifoWr) <= UartCh;
UartRxFifoWr <= (UartRxFifoWr + 1) mod (2**UartRxFifoAddrWidth); -- no "and" for integers :-(
--report "Received '" & character'val(to_integer(unsigned(RxData_o))) & "'" severity note;
end if;
wait for ClkPeriode;
end loop;
end process UartRx_Proc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682mean/chll/out/max6682mean-reconfsignals-bitstream.vhd | 4 | 145 | constant ReconfSignalsLength : integer := 9;
constant ReconfSignalsCfg : std_logic_vector(ReconfSignalsLength-1 downto 0) := "000000000";
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/core/vhdl/reconflogic-testcfgintf-cfg-c.vhd | 1 | 132 | configuration MyReconfigLogicTestCfgIntf_cfg of MyReconfigLogic is
for TestCfgIntf
end for;
end MyReconfigLogicTestCfgIntf_cfg;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682mean/chll/out/max6682mean-wrapreconfmodule-vhdl2008.vhd | 1 | 9335 | -- Automatically generated: write_netlist -wraprm_vhdl2008 -vhdl -module max6682mean-wrapreconfmodule-vhdl2008.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAX6682Mean is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
MAX6682CS_n_o : out std_logic;
SPI_Data_i : in std_logic_vector(7 downto 0);
SPI_Write_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Data_o : out std_logic_vector(7 downto 0);
SPI_FIFOFull_i : in std_logic;
SPI_FIFOEmpty_i : in std_logic;
SPI_Transmission_i : in std_logic;
PauseCounterPreset_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
SPI_CPOL_o : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_LSBFE_o : out std_logic
);
attribute intersynth_port : string;
attribute intersynth_conntype : string;
attribute intersynth_param : string;
attribute intersynth_port of Reset_n_i : signal is "Reset_n_i";
attribute intersynth_port of Clk_i : signal is "Clk_i";
attribute intersynth_port of Enable_i : signal is "ReconfModuleIn_s";
attribute intersynth_conntype of Enable_i : signal is "Bit";
attribute intersynth_port of CpuIntr_o : signal is "ReconfModuleIRQs_s";
attribute intersynth_conntype of CpuIntr_o : signal is "Bit";
attribute intersynth_port of MAX6682CS_n_o : signal is "Outputs_o";
attribute intersynth_conntype of MAX6682CS_n_o : signal is "Bit";
attribute intersynth_port of SPI_Data_i : signal is "SPI_DataOut";
attribute intersynth_conntype of SPI_Data_i : signal is "Byte";
attribute intersynth_port of SPI_Write_o : signal is "SPI_Write";
attribute intersynth_conntype of SPI_Write_o : signal is "Bit";
attribute intersynth_port of SPI_ReadNext_o : signal is "SPI_ReadNext";
attribute intersynth_conntype of SPI_ReadNext_o : signal is "Bit";
attribute intersynth_port of SPI_Data_o : signal is "SPI_DataIn";
attribute intersynth_conntype of SPI_Data_o : signal is "Byte";
attribute intersynth_port of SPI_FIFOFull_i : signal is "SPI_FIFOFull";
attribute intersynth_conntype of SPI_FIFOFull_i : signal is "Bit";
attribute intersynth_port of SPI_FIFOEmpty_i : signal is "SPI_FIFOEmpty";
attribute intersynth_conntype of SPI_FIFOEmpty_i : signal is "Bit";
attribute intersynth_port of SPI_Transmission_i : signal is "SPI_Transmission";
attribute intersynth_conntype of SPI_Transmission_i : signal is "Bit";
attribute intersynth_param of PauseCounterPreset_i : signal is "PauseCounterPreset_i";
attribute intersynth_conntype of PauseCounterPreset_i : signal is "Word";
attribute intersynth_param of PeriodCounterPresetH_i : signal is "PeriodCounterPresetH_i";
attribute intersynth_conntype of PeriodCounterPresetH_i : signal is "Word";
attribute intersynth_param of PeriodCounterPresetL_i : signal is "PeriodCounterPresetL_i";
attribute intersynth_conntype of PeriodCounterPresetL_i : signal is "Word";
attribute intersynth_param of SensorValue_o : signal is "SensorValue_o";
attribute intersynth_conntype of SensorValue_o : signal is "Word";
attribute intersynth_param of Threshold_i : signal is "Threshold_i";
attribute intersynth_conntype of Threshold_i : signal is "Word";
attribute intersynth_port of SPI_CPOL_o : signal is "SPI_CPOL";
attribute intersynth_conntype of SPI_CPOL_o : signal is "Bit";
attribute intersynth_port of SPI_CPHA_o : signal is "SPI_CPHA";
attribute intersynth_conntype of SPI_CPHA_o : signal is "Bit";
attribute intersynth_port of SPI_LSBFE_o : signal is "SPI_LSBFE";
attribute intersynth_conntype of SPI_LSBFE_o : signal is "Bit";
end MAX6682Mean;
architecture WrapReconfModule of MAX6682Mean is
component MyReconfigLogic
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0);
I2C_Busy_i : in std_logic;
I2C_DataIn_o : out std_logic_vector(7 downto 0);
I2C_DataOut_i : in std_logic_vector(7 downto 0);
I2C_Divider800_o : out std_logic_vector(15 downto 0);
I2C_ErrAckParam_o : out std_logic;
I2C_Error_i : in std_logic;
I2C_F100_400_n_o : out std_logic;
I2C_FIFOEmpty_i : in std_logic;
I2C_FIFOFull_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(3 downto 0);
I2C_ReceiveSend_n_o : out std_logic;
I2C_StartProcess_o : out std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
ReconfModuleIRQs_o : out std_logic_vector(4 downto 0);
SPI_CPHA_o : out std_logic;
SPI_CPOL_o : out std_logic;
SPI_DataIn_o : out std_logic_vector(7 downto 0);
SPI_DataOut_i : in std_logic_vector(7 downto 0);
SPI_FIFOEmpty_i : in std_logic;
SPI_FIFOFull_i : in std_logic;
SPI_LSBFE_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_SPPR_SPR_o : out std_logic_vector(7 downto 0);
SPI_Transmission_i : in std_logic;
SPI_Write_o : out std_logic;
ReconfModuleIn_i : in std_logic_vector(7 downto 0);
ReconfModuleOut_o : out std_logic_vector(7 downto 0);
I2C_Errors_i : in std_logic_vector(7 downto 0);
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgIntfDOut_o : out std_logic_vector(15 downto 0);
ParamIntfDOut_o : out std_logic_vector(15 downto 0)
);
end component;
signal ReconfModuleIn_s : std_logic_vector(7 downto 0);
signal ReconfModuleIRQs_s : std_logic_vector(4 downto 0);
signal Outputs_s : std_logic_vector(7 downto 0);
signal AdcDoConvert_s : std_logic;
signal CfgIntfDOut_s : std_logic_vector(15 downto 0);
signal I2C_DataIn_s : std_logic_vector(7 downto 0);
signal I2C_Divider800_s : std_logic_vector(15 downto 0);
signal I2C_ErrAckParam_s : std_logic;
signal I2C_F100_400_n_s : std_logic;
signal I2C_FIFOReadNext_s : std_logic;
signal I2C_FIFOWrite_s : std_logic;
signal I2C_ReadCount_s : std_logic_vector(3 downto 0);
signal I2C_ReceiveSend_n_s : std_logic;
signal I2C_StartProcess_s : std_logic;
signal ParamIntfDOut_s : std_logic_vector(15 downto 0);
signal ReconfModuleOut_s : std_logic_vector(7 downto 0);
signal SPI_SPPR_SPR_s : std_logic_vector(7 downto 0);
begin
MyReconfigLogic_0: MyReconfigLogic
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
ReconfModuleIn_i => ReconfModuleIn_s,
ReconfModuleIRQs_o => ReconfModuleIRQs_s,
Outputs_o => Outputs_s,
SPI_DataOut_i => SPI_Data_i,
SPI_Write_o => SPI_Write_o,
SPI_ReadNext_o => SPI_ReadNext_o,
SPI_DataIn_o => SPI_Data_o,
SPI_FIFOFull_i => SPI_FIFOFull_i,
SPI_FIFOEmpty_i => SPI_FIFOEmpty_i,
SPI_Transmission_i => SPI_Transmission_i,
SPI_CPOL_o => SPI_CPOL_o,
SPI_CPHA_o => SPI_CPHA_o,
SPI_LSBFE_o => SPI_LSBFE_o,
AdcConvComplete_i => '0',
AdcDoConvert_o => AdcDoConvert_s,
AdcValue_i => "0000000000",
CfgIntfDOut_o => CfgIntfDOut_s,
I2C_Busy_i => '0',
I2C_DataIn_o => I2C_DataIn_s,
I2C_DataOut_i => "00000000",
I2C_Divider800_o => I2C_Divider800_s,
I2C_ErrAckParam_o => I2C_ErrAckParam_s,
I2C_Error_i => '0',
I2C_Errors_i => "00000000",
I2C_F100_400_n_o => I2C_F100_400_n_s,
I2C_FIFOEmpty_i => '0',
I2C_FIFOFull_i => '0',
I2C_FIFOReadNext_o => I2C_FIFOReadNext_s,
I2C_FIFOWrite_o => I2C_FIFOWrite_s,
I2C_ReadCount_o => I2C_ReadCount_s,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n_s,
I2C_StartProcess_o => I2C_StartProcess_s,
Inputs_i => "00000000",
ParamIntfDOut_o => ParamIntfDOut_s,
PerAddr_i => "00000000000000",
PerDIn_i => "0000000000000000",
PerEn_i => '0',
PerWr_i => "00",
ReconfModuleOut_o => ReconfModuleOut_s,
SPI_SPPR_SPR_o => SPI_SPPR_SPR_s
);
CpuIntr_o <= ReconfModuleIRQs_s(0);
MAX6682CS_n_o <= Outputs_s(0);
<< signal MyReconfigLogic_0.ParamIn_Word_0_s : std_logic_vector(15 downto 0) >> <= PauseCounterPreset_i;
<< signal MyReconfigLogic_0.ParamIn_Word_3_s : std_logic_vector(15 downto 0) >> <= PeriodCounterPresetH_i;
<< signal MyReconfigLogic_0.ParamIn_Word_2_s : std_logic_vector(15 downto 0) >> <= PeriodCounterPresetL_i;
SensorValue_o <= << signal MyReconfigLogic_0.ParamOut_Word_0_s : std_logic_vector(15 downto 0) >>;
<< signal MyReconfigLogic_0.ParamIn_Word_1_s : std_logic_vector(15 downto 0) >> <= Threshold_i;
<< signal MyReconfigLogic_0.ParamIn_Word_4_s : std_logic_vector(15 downto 0) >> <= "0000000000000000";
<< signal MyReconfigLogic_0.I2C_Divider800_o : std_logic_vector(15 downto 0) >> <= "0000000000000000";
<< signal MyReconfigLogic_0.I2C_ErrAckParam_o : std_logic >> <= '0';
ReconfModuleIn_s <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & Enable_i;
end WrapReconfModule;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7310/tb/core_adt7310_tb.vhd | 9 | 13672 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
-- OneWire_i : in std_logic;
-- OneWire_o : out std_logic;
-- PWMInput_i : in std_logic;
-- SENTInput_i : in std_logic;
-- SPCInput_i : in std_logic;
-- SPCTrigger_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component adt7310_model
port (
SCLK_i : in std_logic;
DOUT_o : out std_logic;
DIN_i : in std_logic;
CS_n_i : in std_logic;
CT_n_o : out std_logic;
INT_n_o : out std_logic;
Temp_i : in real);
end component;
component ExtNames
port (
SPIFSM_Done : out std_logic;
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0)
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal LFXT_Clk_i : std_logic;
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic;
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic;
signal Dbg_SDA_Out_o : std_logic;
signal Dbg_SDA_In_i : std_logic;
signal P1_DOut_o : std_logic_vector(7 downto 0);
signal P1_En_o : std_logic_vector(7 downto 0);
signal P1_DIn_i : std_logic_vector(7 downto 0);
signal P2_DOut_o : std_logic_vector(7 downto 0);
signal P2_En_o : std_logic_vector(7 downto 0);
signal P2_DIn_i : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic;
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic;
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_o : std_logic;
signal I2CSDA_i : std_logic;
signal I2CSDA_o : std_logic;
-- signal OneWire_i : std_logic;
-- signal OneWire_o : std_logic;
-- signal PWMInput_i : std_logic;
-- signal SENTInput_i : std_logic;
-- signal SPCInput_i : std_logic;
-- signal SPCTrigger_o : std_logic;
signal AdcConvComplete_i : std_logic;
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0);
-- look into the ADT7310 app
-- alias SPIFSM_Done_i is << signal .adt7310_tb.DUT.SPIFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the SPIFSM_Done_i signal.
signal SPIFSM_Done_e : std_logic; -- directly from inside SPI_FSM
signal CpuIntr_e : std_logic; -- directly from inside SPI_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- SPIFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal SPIFSM_Done_d : std_logic; -- sightly delayed
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal SensorValue_real : real;
-- ADT7310 component ports
signal ADT7310CS_n_o : std_logic;
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
-- The timer has to wait for 240ms. With a 16 bit resolution, the maximumn
-- counting periode is 3.66us. Here we set the clock signal to 10us = 100kHz.
-- The timer is preset to 24000.
constant ClkPeriode : time := 10 us;
begin
DUT: Core
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
LFXT_Clk_i => LFXT_Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_Out_o => Dbg_SDA_Out_o,
Dbg_SDA_In_i => Dbg_SDA_In_i,
P1_DOut_o => P1_DOut_o,
P1_En_o => P1_En_o,
P1_DIn_i => P1_DIn_i,
P2_DOut_o => P2_DOut_o,
P2_En_o => P2_En_o,
P2_DIn_i => P2_DIn_i,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_o => I2CSCL_o,
I2CSDA_i => I2CSDA_i,
I2CSDA_o => I2CSDA_o,
-- OneWire_i => OneWire_i,
-- OneWire_o => OneWire_o,
-- PWMInput_i => PWMInput_i,
-- SENTInput_i => SENTInput_i,
-- SPCInput_i => SPCInput_i,
-- SPCTrigger_o => SPCTrigger_o,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
ADT7310CS_n_o <= Outputs_o(0);
Inputs_i <= (others => '0');
P1_DIn_i <= (others => '0');
P2_DIn_i <= (others => '0');
ExtNames_1: ExtNames
port map (
SPIFSM_Done => SPIFSM_Done_e,
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e
);
SPIFSM_Done_d <= SPIFSM_Done_e after 1.0 ns;
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
adt7310_1: adt7310_model
port map (
SCLK_i => SPISCK_o,
DOUT_o => SPIMISO_i,
DIN_i => SPIMOSI_o,
CS_n_i => ADT7310CS_n_o,
CT_n_o => CT_n_s,
INT_n_o => INT_n_s,
Temp_i => Temp_s);
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
wait for 2.3*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
wait for 1.3*ClkPeriode; -- wait until spi_master's SCK_o goes '1' to conform to CPOL_i = '1'
Temp_s <= 23.7; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- In WrapADT7310, i.e. in the original ADT7310 Verilog source, SPIFSM_Done
-- is '1' directly after reset (combinational!). When using the
-- ReconfModule with the included TR-FSMs, the signal starts at '0' and is
-- set to '1' as soon as the config bitstream gets activated, i.e. when the
-- configuration is done and CfgMode_i goes to '0'.
--
-- Here we wait for the _second_ rising edge of SPIFSM_Done, because at the
-- first time, the sensor is queried, but the result can only be read back
-- after 240ms, i.e. at the second SPI transmission.
if SPIFSM_Done_d = '0' then
-- SPIFSM_Done starts at '0', so this simulation uses the TR-FSMs
wait until SPIFSM_Done_d = '1';
end if;
wait until SPIFSM_Done_d = '0';
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- The digital value is 128*Temp_s (plus/minus rounding to nearest
-- modulo 8). The threshold for too large changes is 30 (see
-- sensorfsm.vhd).
-- 23.7°C --> 3032
-- 25.7°C --> 3288 (delta: | 256| > 30)
-- 25.6°C --> 3280 (delta: | -8| < 30)
-- 25.5°C --> 3264 (delta: | -24| < 30)
-- 25.4°C --> 3248 (delta: | -40| >= 30)
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.7;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.6;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after SPIFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.5;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after SPIFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.4;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
wait for 100*ClkPeriode;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/simplespi/vhdl/simplespi.vhd | 1 | 7512 | -------------------------------------------------------------------------------
--
-- SPI peripheral for the OpenMSP430
--
-- Author: Johann Glaser
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SimpleSPI is
generic (
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0); -- in reality this is 14 downto 1
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector( 1 downto 0); -- byte select
PerEn_i : in std_logic;
Intr_o : out std_logic;
-- SPI Interface
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic
);
end SimpleSPI;
-------------------------------------------------------------------------------
-- Registers:
--
-- 0x00 CSR Config and Status Register
-- 15 (r) Busy Bit
-- 14:11 reserved
-- 10 (rw) Interrupt Enable
-- 9: 6 (rw) BRDE (baud rate divider exponent)
-- 5: 2 (rw) BRDM (baud rate divider mantissa)
-- 1 (rw) CPHA (clock phase) (0: shift on falling edge of SCK (with CPOL=0))
-- 0 (rw) CPOL (clock polarity) (0: SCK is low when idle)
--
-- 0x02 DAT Data Read/Write
-- 15: 8 reserved
-- 7: 0 (rw) Data
--
-- see http://sigalrm.blogspot.co.at/2011/01/introduction-to-arm-cortex-m3-part-2.html
-- see http://commons.wikimedia.org/wiki/File:SPI_timing_diagram.svg
-------------------------------------------------------------------------------
architecture rtl of SimpleSPI is
-- addressing this module
constant AddrWidth : integer := 2; -- number of bits considered for (full) address decoding
constant MaskAddrRegs : std_logic_vector(14 downto 0) := std_logic_vector(to_unsigned(2**AddrWidth-1,15));
constant MaskAddrBase : std_logic_vector(14 downto 0) := std_logic_vector(to_unsigned(2**15-1,15)) and (not MaskAddrRegs);
constant BaseAddrVec : std_logic_vector(14 downto 0) := std_logic_vector(to_unsigned(BaseAddr,15)) and MaskAddrBase;
-- addressing individual registers
constant AddrCSR : integer := 0; -- Config and Status Register
constant AddrDAT : integer := 2; -- Data Read/Write
-- ...
signal Busy : std_logic;
signal IntEn : std_logic;
signal BRDE : std_logic_vector(3 downto 0);
signal BRDM : std_logic_vector(3 downto 0);
signal CPHA : std_logic;
signal CPOL : std_logic;
signal DataRead : std_logic_vector(7 downto 0);
signal DataWrite : std_logic_vector(7 downto 0);
signal Xfer : unsigned(3 downto 0); -- one bit wider than necessary for 8 bits
signal XferPhase : std_logic;
signal Prescaler : unsigned(15 downto 0);
signal PrescalerPrev : unsigned(15 downto 0);
signal PrescalerEdge : std_logic_vector(15 downto 0);
signal PrescalerSel : std_logic;
signal BaudDivider : unsigned(3 downto 0);
signal SckToggle : std_logic;
signal SCK_s : std_logic;
begin -- rtl
-- purpose: peripheral read via bus interface
-- type : combinational
-- inputs : PerAddr_i,PerEn_i
-- outputs: PerDOut_o
PerRead: process (PerAddr_i,PerEn_i,PerWr_i,Busy,IntEn,BRDE,BRDM,CPHA,CPOL,DataRead)
begin -- process PerRead
PerDOut_o <= (others => '0');
if PerEn_i = '1' and ((PerAddr_i & '0') and MaskAddrBase) = BaseAddrVec and PerWr_i = "00" then
case to_integer(unsigned(PerAddr_i(AddrWidth-2 downto 0) & '0')) is
when AddrCSR => PerDOut_o <= Busy & "0000" & IntEn & BRDE & BRDM & CPHA & CPOL;
when AddrDAT => PerDOut_o <= "00000000" & DataRead;
when others => null;
end case;
end if;
end process PerRead;
-- purpose: Peripheral write, shift config
-- type : sequential
-- inputs : Clk_i, Reset_n_i
-- outputs:
PerWrite: process (Clk_i, Reset_n_i)
begin -- process PerWrite
if Reset_n_i = '0' then -- asynchronous reset (active low)
Intr_o <= '0';
Busy <= '0';
IntEn <= '0';
BRDE <= (others => '0');
BRDM <= (others => '0');
CPHA <= '0';
CPOL <= '0';
DataWrite <= (others => '0');
DataRead <= (others => '0');
Xfer <= (others => '0');
XferPhase <= '0';
Prescaler <= (others => '0');
PrescalerPrev <= (others => '0');
BaudDivider <= (others => '0');
SckToggle <= '0';
SCK_s <= '0';
MOSI_o <= '0';
elsif Clk_i'event and Clk_i = '1' then -- rising clock edge
Intr_o <= '0';
-- Peripheral write via bus interface
if PerEn_i = '1' and ((PerAddr_i & '0') and MaskAddrBase) = BaseAddrVec and PerWr_i = "11" and Busy = '0' then
case to_integer(unsigned(PerAddr_i(AddrWidth-2 downto 0) & '0')) is
when AddrCSR =>
-- 15: don't write Busy
-- 14:11: reserved, ignore
IntEn <= PerDIn_i( 10);
BRDE <= PerDIn_i( 9 downto 6);
BRDM <= PerDIn_i( 5 downto 2);
CPHA <= PerDIn_i( 1);
CPOL <= PerDIn_i( 0);
when AddrDAT =>
DataWrite <= PerDIn_i(7 downto 0);
Busy <= '1';
Xfer <= to_unsigned(9,Xfer'length);
XferPhase <= '0';
when others => null;
end case;
end if;
-- baud rate generator
if Xfer = 0 then
-- reset baud rate generator
Prescaler <= (others => '0');
PrescalerPrev <= (others => '1'); -- set to all '1', so that PrescalerSel is '1' when starting a transmission
BaudDivider <= (others => '0');
SCK_s <= '0';
else
PrescalerPrev <= PreScaler;
Prescaler <= Prescaler+1; -- use integer overflow
if PrescalerSel = '1' then
if BaudDivider = 0 then
BaudDivider <= unsigned(BRDM);
if XferPhase = '0' then
-- set MOSI, shift data
if not (Xfer = 1) then
MOSI_o <= DataWrite(7);
DataWrite <= DataWrite(6 downto 0) & '0';
SCK_s <= CPHA;
else
MOSI_o <= '0';
SCK_s <= '0';
Busy <= '0';
Intr_o <= IntEn;
end if;
XferPhase <= '1';
Xfer <= Xfer - 1;
else
-- sample MISO
DataRead <= DataRead(6 downto 0) & MISO_i; -- attention: this is an unregistered input :-( TODO
XferPhase <= '0';
SCK_s <= not CPHA;
end if;
else
BaudDivider <= BaudDivider-1;
end if;
end if;
end if;
end if;
end process PerWrite;
PrescalerEdge <= std_logic_vector(Prescaler) xor std_logic_vector(PrescalerPrev); -- '1' for all bits which have toggled in the last clock periode
PrescalerSel <= PrescalerEdge(to_integer(unsigned(BRDE))); -- prescaled clock: select toggle indicator
SCK_o <= SCK_s xor CPOL;
end rtl;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/fifo/vhdl/fifosynctop-structure-a.vhd | 1 | 2731 |
architecture structure of FIFOSyncTop is
component FIFODualPortRam
Generic (
DataWidth : integer range 2 to 64 := 8;
AdressWidth : integer range 2 to 10 := 4);
Port (
Reset_n_i : in STD_LOGIC;
ClkA : in STD_LOGIC;
DataA_i : in STD_LOGIC_VECTOR (DataWidth - 1 downto 0);
AdressA_i : in STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
WriteEnableA_i : in STD_LOGIC;
DataB_o : out STD_LOGIC_VECTOR (DataWidth - 1 downto 0);
AdressB_i : in STD_LOGIC_VECTOR (AdressWidth - 1 downto 0));
end component;
component FIFOBinaryCounter
Generic (
AdressWidth : integer range 2 to 10 := 4);
Port (
Reset_n : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkEnable_i : in STD_LOGIC;
Binary_o : out STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
BinaryMSB_o : out STD_LOGIC);
end component;
component FIFOSyncCmp
Generic (
AdressWidth : integer range 2 to 10 := 4);
Port (
PointerA_i : in STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
PointerB_i : in STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
MSBPointerA_i : in STD_LOGIC;
MSBPointerB_i : in STD_LOGIC;
FIFOFull_o : out STD_LOGIC;
FIFOEmpty_o : out STD_LOGIC);
end component;
signal AdressA : STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
signal AdressB : STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
signal MSBAdressA : STD_LOGIC;
signal MSBAdressB : STD_LOGIC;
begin
DualPortRam: FIFODualPortRam
Generic Map (
DataWidth => DataWidth,
AdressWidth => AdressWidth)
Port Map (
Reset_n_i => Reset_n,
ClkA => Clk,
DataA_i => DataA_i,
AdressA_i => AdressA,
WriteEnableA_i => WriteA_i,
DataB_o => DataB_o,
AdressB_i => AdressB);
WriteCounter: FIFOBinaryCounter
Generic Map (
AdressWidth => AdressWidth)
Port Map (
Reset_n => Reset_n,
Clk => Clk,
ClkEnable_i => WriteA_i,
Binary_o => AdressA,
BinaryMSB_o => MSBAdressA);
ReadCounter: FIFOBinaryCounter
Generic Map (
AdressWidth => AdressWidth)
Port Map (
Reset_n => Reset_n,
Clk => Clk,
ClkEnable_i => ReadNextB_i,
Binary_o => AdressB,
BinaryMSB_o => MSBAdressB);
SyncCmp: FIFOSyncCmp
Generic Map (
AdressWidth => AdressWidth)
Port Map (
PointerA_i => AdressA,
PointerB_i => AdressB,
MSBPointerA_i => MSBAdressA,
MSBPointerB_i => MSBAdressB,
FIFOFull_o => FIFOFull_o,
FIFOEmpty_o => FIFOEmpty_o);
end structure;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/extadcsimple/tb/core_extadcsimple_tb.vhd | 1 | 19756 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
-- OneWire_i : in std_logic;
-- OneWire_o : out std_logic;
-- PWMInput_i : in std_logic;
-- SENTInput_i : in std_logic;
-- SPCInput_i : in std_logic;
-- SPCTrigger_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component ExtNames
port (
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0);
Enable : out std_logic
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal LFXT_Clk_i : std_logic;
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic;
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic;
signal Dbg_SDA_Out_o : std_logic;
signal Dbg_SDA_In_i : std_logic;
signal P1_DOut_o : std_logic_vector(7 downto 0);
signal P1_En_o : std_logic_vector(7 downto 0);
signal P1_DIn_i : std_logic_vector(7 downto 0);
signal P2_DOut_o : std_logic_vector(7 downto 0);
signal P2_En_o : std_logic_vector(7 downto 0);
signal P2_DIn_i : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic;
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic;
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_o : std_logic;
signal I2CSDA_i : std_logic;
signal I2CSDA_o : std_logic;
-- signal OneWire_i : std_logic;
-- signal OneWire_o : std_logic;
-- signal PWMInput_i : std_logic;
-- signal SENTInput_i : std_logic;
-- signal SPCInput_i : std_logic;
-- signal SPCTrigger_o : std_logic;
signal AdcConvComplete_i : std_logic;
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0);
-- look into the ExtAdc app
signal CpuIntr_e : std_logic; -- directly from inside SPI_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
signal Enable_e : std_logic; -- directly from inside
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal Enable_i : std_logic; -- directly from inside
-- External Sensor ports
constant AdcValueWidth : integer := 10;
signal SensorPower_o : std_logic;
signal SensorStart_o : std_logic;
signal SensorReady_i : std_logic;
alias AdcStart_o : std_logic is AdcDoConvert_o;
alias AdcDone_i : std_logic is AdcConvComplete_i;
constant ClkPeriode : time := 10 ns;
begin
DUT: Core
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
LFXT_Clk_i => LFXT_Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_Out_o => Dbg_SDA_Out_o,
Dbg_SDA_In_i => Dbg_SDA_In_i,
P1_DOut_o => P1_DOut_o,
P1_En_o => P1_En_o,
P1_DIn_i => P1_DIn_i,
P2_DOut_o => P2_DOut_o,
P2_En_o => P2_En_o,
P2_DIn_i => P2_DIn_i,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_o => I2CSCL_o,
I2CSDA_i => I2CSDA_i,
I2CSDA_o => I2CSDA_o,
-- OneWire_i => OneWire_i,
-- OneWire_o => OneWire_o,
-- PWMInput_i => PWMInput_i,
-- SENTInput_i => SENTInput_i,
-- SPCInput_i => SPCInput_i,
-- SPCTrigger_o => SPCTrigger_o,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
SensorPower_o <= Outputs_o(0);
SensorStart_o <= Outputs_o(1);
Inputs_i(0) <= SensorReady_i;
Inputs_i(Inputs_i'high downto 1) <= (others => '0');
P1_DIn_i <= (others => '0');
P2_DIn_i <= (others => '0');
ExtNames_1: ExtNames
port map (
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e,
Enable => Enable_e
);
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
Enable_i <= Enable_e after 1.0 ns;
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
SensorReady_i <= '0';
AdcDone_i <= '0';
AdcValue_i <= (others => '0');
wait for 2.2*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
-- wait until SensorFSM is enabled
wait until Enable_i = '1';
-- Check constant values of dynamic signals coming out of the application modules
wait for 0.1*ClkPeriode;
-- none to check
wait for 9*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 35*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 0.1*ClkPeriode;
assert AdcStart_o = '1' report "AdcStart_o should be '1'" severity error;
wait for 0.9*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
wait for 35*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 38
report "2nd cycle, new sensor value: 38" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(38,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 30
report "3rd cycle, new sensor value: 30" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(30,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(30,16)) report "SensorValue_o should be 30" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 28
report "4th cycle, new sensor value: 28" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(28,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(30,16)) report "SensorValue_o should be 38" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(28,16)) report "SensorValue_o should be 30" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 27
report "5th cycle, new sensor value: 27" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(27,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(28,16)) report "SensorValue_o should be 38" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(27,16)) report "SensorValue_o should be 30" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
report "done testing" severity note;
wait for 10*ClkPeriode;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7310p16ls16l/tb/wrapreconfmodule-c.vhd | 9 | 998 | ------------------------------------------------------------------------------
-- Special configuration which disconnects the ParamOutReg modules, so that
-- we can drive the values with VHDL'2008 external names in the Reconf.Module
-- wrapper <app>-wrapreconfmodule.vhd.
------------------------------------------------------------------------------
configuration WrapReconfModule_cfg of ADT7310_tb is
for behavior
for DUT : ADT7310
for WrapReconfModule
for MyReconfigLogic_0 : MyReconfigLogic
for struct
for all : ParamOutReg
use entity work.ParamOutReg(rtl)
port map (
Reset_n_i => '0',
Clk_i => '0',
Enable_i => '0',
ParamWrData_i => (others => '0'),
Param_o => open
);
end for;
end for;
end for;
end for;
end for;
end for;
end WrapReconfModule_cfg;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7310p32s16/tb/wrapreconfmodule-c.vhd | 9 | 998 | ------------------------------------------------------------------------------
-- Special configuration which disconnects the ParamOutReg modules, so that
-- we can drive the values with VHDL'2008 external names in the Reconf.Module
-- wrapper <app>-wrapreconfmodule.vhd.
------------------------------------------------------------------------------
configuration WrapReconfModule_cfg of ADT7310_tb is
for behavior
for DUT : ADT7310
for WrapReconfModule
for MyReconfigLogic_0 : MyReconfigLogic
for struct
for all : ParamOutReg
use entity work.ParamOutReg(rtl)
port map (
Reset_n_i => '0',
Clk_i => '0',
Enable_i => '0',
ParamWrData_i => (others => '0'),
Param_o => open
);
end for;
end for;
end for;
end for;
end for;
end for;
end WrapReconfModule_cfg;
| gpl-2.0 |
Nixon-/VHDL_library | IO/debounce.vhd | 1 | 1133 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity debounce is
generic(timeOut: integer:=2000000);
port(
input: in std_logic;
clk: in std_logic;
output: out std_logic;
reset: in std_logic
);
end debounce;
architecture Behavioral of debounce is
signal capture: std_logic;
begin
count: process(input,clk)
variable count: integer range 0 to timeOut*2:=0;
variable inputCapture: std_logic;
begin
if(reset = '1') then
count := 0;
inputCapture <= '0';
output <= '0';
elsif(rising_edge(clk)) then
if(count = 0) then
inputCapture := input;
capture <= '1';
else
capture <= '0';
inputCapture := inputCapture;
end if;
if(capture = '1' AND count = timeOut AND input = inputCapture) then
output <= inputCapture;
count := 0;
capture <= '0';
elsif (capture = '1' and count = timeOut and not(input = inputCapture)) then
count := 0;
capture <= '0';
output <= input;
elsif(capture = '1') then
capture <= capture;
count := count+1;
output <= '0';
else
count := count;
output <= ;
capture <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
Nixon-/VHDL_library | memory/to_test/nbit_shift_Register.vhd | 1 | 973 | Library ieee;
use ieee.std_logic_1164.all;
entity nbit_shift_register is
generic(n:integer:=4);
port(
clk,enable,arsh,alsh,load: in std_logic;
inputVector: in std_logic_vector(n-1 downto 0);
outputVector: out std_logic_vector(n-1 downto 0);
bit_in: in std_logic;
bit_out: out std_logic;
);
end nbit_shift_register;
architecture primary of nbit_shift_register is
begin
process(clk,enable,arsh,alsh,load,bit_in,inputVector)
variable cdata,ndata: std_logic_vector(n-1 downto 0);
begin
if(clk' event and clk = '1') then
if (enable = '1') then
if (load = '1') then
ndata := inputVector;
elsif (ashl = '1') then
for i in 0 to i-2 begin
ndata(i+1) := cdata(i);
end for;
b_out <= cdata(n-1);
elsif (ashr = '1') then
for i in 1 to n-1 begin
ndata(i-1) := cdata(i);
end for;
b_out <= cdata(0);
end if;
end if;
outputVector <= ndata;
cdata <= ndata;
end if;
end process;
end primary;
| gpl-2.0 |
freecores/lzrw1-compressor-core | hw/testbench/HastTb.vhd | 1 | 5253 | --/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/6/17 - LS
--* started file
--*
--* Version 1.0 - 2013/4/5 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Test bench for entity hashTable
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity HashTable_tb is
end HashTable_tb;
-------------------------------------------------------------------------------
architecture tb of HashTable_tb is
component HashTable
generic (
entryBitWidth : integer);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
NewEntryxDI : in std_logic_vector(entryBitWidth-1 downto 0);
EnWrxSI : in std_logic;
Key0xDI : in std_logic_vector(7 downto 0);
Key1xDI : in std_logic_vector(7 downto 0);
Key2xDI : in std_logic_vector(7 downto 0);
OldEntryxDO : out std_logic_vector(entryBitWidth-1 downto 0));
end component;
-- component generics
constant entryBitWidth : integer := 12;
-- component ports
signal ClkxCI : std_logic;
signal RstxRI : std_logic := '1';
signal NewEntryxDI : std_logic_vector(entryBitWidth-1 downto 0) := (others => '0');
signal EnWrxSI : std_logic := '0';
signal Key0xDI : std_logic_vector(7 downto 0) := (others => '0');
signal Key1xDI : std_logic_vector(7 downto 0) := (others => '0');
signal Key2xDI : std_logic_vector(7 downto 0) := (others => '0');
signal OldEntryxDO : std_logic_vector(entryBitWidth-1 downto 0);
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : HashTable
generic map (
entryBitWidth => entryBitWidth)
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
NewEntryxDI => NewEntryxDI,
EnWrxSI => EnWrxSI,
Key0xDI => Key0xDI,
Key1xDI => Key1xDI,
Key2xDI => Key2xDI,
OldEntryxDO => OldEntryxDO);
-- clock generation
Clk <= not Clk after 10 ns;
ClkxCI <= Clk;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until Clk = '1';
Key0xDI <= x"10";
Key1xDI <= x"32";
Key2xDI <= x"54";
NewEntryxDI <= x"210";
EnWrxSI <= '1';
wait until Clk'event and Clk = '1';
Key0xDI <= x"00";
Key1xDI <= x"00";
Key2xDI <= x"00";
NewEntryxDI <= x"000";
EnWrxSI <= '1';
wait until Clk'event and Clk = '1';
Key0xDI <= x"10";
Key1xDI <= x"32";
Key2xDI <= x"54";
NewEntryxDI <= x"fff";
EnWrxSI <= '0';
wait until Clk'event and Clk = '1';
Key0xDI <= x"00";
Key1xDI <= x"00";
Key2xDI <= x"00";
NewEntryxDI <= x"111";
EnWrxSI <= '0';
wait until Clk'event and Clk = '1';
Key0xDI <= x"10";
Key1xDI <= x"32";
Key2xDI <= x"54";
NewEntryxDI <= x"fff";
EnWrxSI <= '1';
wait until Clk'event and Clk = '1';
Key0xDI <= x"10";
Key1xDI <= x"32";
Key2xDI <= x"54";
NewEntryxDI <= x"000";
EnWrxSI <= '0';
wait until Clk'event and Clk = '1';
wait;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
configuration HashTable_tb_tb_cfg of HashTable_tb is
for tb
end for;
end HashTable_tb_tb_cfg;
-------------------------------------------------------------------------------
| gpl-2.0 |
koolatron/hackrf | firmware/cpld/sgpio_if/top.vhd | 1 | 5046 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
q_invert <= HOST_Q_INVERT;
q_invert_mask <= X"80" when q_invert = '1' else X"7f";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor q_invert_mask;
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
dac_data_o <= (data_from_host_i xor X"7f") & "11";
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i;
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i and decimate_en;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
freecores/lzrw1-compressor-core | hw/testbench/CompressorTopTb.vhd | 1 | 11628 | --/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/10/16 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Simple testebench for manual signal inspection of the Wishbone interfaces
--* and the DMA unit of CompressorTop.vhd
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity CompressorTop_tb is
end CompressorTop_tb;
architecture TB of CompressorTop_tb is
component CompressorTop
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
SlCycxSI : in std_logic;
SlStbxSI : in std_logic;
SlWexSI : in std_logic;
SlSelxDI : in std_logic_vector(3 downto 0);
SlAdrxDI : in std_logic_vector(4 downto 2);
SlDatxDI : in std_logic_vector(31 downto 0);
SlDatxDO : out std_logic_vector(31 downto 0);
SlAckxSO : out std_logic;
SlErrxSO : out std_logic;
IntxSO : out std_logic;
MaCycxSO : out std_logic;
MaStbxSO : out std_logic;
MaWexSO : out std_logic;
MaSelxDO : out std_logic_vector(3 downto 0);
MaAdrxDO : out std_logic_vector(31 downto 0);
MaDatxDO : out std_logic_vector(31 downto 0);
MaDatxDI : in std_logic_vector(31 downto 0);
MaAckxSI : in std_logic;
MaErrxSI : in std_logic);
end component;
constant PERIOD : time := 25 ns;
signal ClkxCI : std_logic := '0';
signal RstxRI : std_logic := '1';
signal SlCycxSI : std_logic := '0';
signal SlStbxSI : std_logic := '0';
signal SlWexSI : std_logic := '0';
signal SlSelxDI : std_logic_vector(3 downto 0) := "0000";
signal SlAdrxDI : std_logic_vector(4 downto 2) := (others => '0');
signal SlDatxDI : std_logic_vector(31 downto 0) := (others => '0');
signal SlDatxDO : std_logic_vector(31 downto 0) := (others => '0');
signal SlAckxSO : std_logic;
signal SlErrxSO : std_logic;
signal IntxSO : std_logic;
signal MaCycxSO : std_logic;
signal MaStbxSO : std_logic;
signal MaWexSO : std_logic;
signal MaSelxDO : std_logic_vector(3 downto 0) := (others => '0');
signal MaAdrxDO : std_logic_vector(31 downto 0) := (others => '0');
signal MaDatxDO : std_logic_vector(31 downto 0) := (others => '0');
signal MaDatxDI : std_logic_vector(31 downto 0) := (others => '0');
signal MaAckxSI : std_logic := '0';
signal MaErrxSI : std_logic := '0';
begin
ClkxCI <= not ClkxCI after PERIOD/2;
process
begin
RstxRI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
RstxRI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
-- reset core
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "111";
SlWexSI <= '1';
SlSelxDI <= "1111";
SlDatxDI <= x"00000001";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- set inc dest addr flag and IE for in fifo full and for core done
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "001";
SlWexSI <= '1';
SlDatxDI <= x"00020100";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- read flags
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "001";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
-- setup dma destination
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "100";
SlWexSI <= '1';
SlDatxDI <= x"12345670";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- setup dma length
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "101";
SlWexSI <= '1';
SlDatxDI <= x"00000030";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- read dma destination
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "100";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- setup in fifo thresholds
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "010";
SlWexSI <= '1';
SlDatxDI <= x"000f0004";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"03020100";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"07060504";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"0b0a0908";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"0f0e0d0c";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"05030201";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"0b0a0706";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"1413120c";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"08070605";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
--wait for PERIOD*2*20;
-- enable done interrupt
-- wait until ClkxCI'event and ClkxCI = '1';
-- SlCycxSI <= '1';
-- SlStbxSI <= '1';
-- SlAdrxDI <= "001";
-- SlWexSI <= '1';
-- SlDatxDI <= x"00200102";
-- wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
-- SlCycxSI <= '0';
-- SlStbxSI <= '0';
-- SlAdrxDI <= "000";
-- SlWexSI <= '0';
-- SlDatxDI <= x"00000000";
-- flush core
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "111";
SlWexSI <= '1';
SlDatxDI <= x"00000002";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait for PERIOD*200;
-- read flags
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "001";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
wait;
end process;
MaAckxSI <= MaCycxSO and MaStbxSO;
--MaErrxSI <= MaCycxSO and MaStbxSO;
DUT : CompressorTop
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
SlCycxSI => SlCycxSI,
SlStbxSI => SlStbxSI,
SlWexSI => SlWexSI,
SlSelxDI => SlSelxDI,
SlAdrxDI => SlAdrxDI,
SlDatxDI => SlDatxDI,
SlDatxDO => SlDatxDO,
SlAckxSO => SlAckxSO,
SlErrxSO => SlErrxSO,
IntxSO => IntxSO,
MaCycxSO => MaCycxSO,
MaStbxSO => MaStbxSO,
MaWexSO => MaWexSO,
MaSelxDO => MaSelxDO,
MaAdrxDO => MaAdrxDO,
MaDatxDO => MaDatxDO,
MaDatxDI => MaDatxDI,
MaAckxSI => MaAckxSI,
MaErrxSI => MaErrxSI);
end TB;
| gpl-2.0 |
olibre/doxygen | examples/mux.vhdl | 37 | 860 | -------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architecture definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
| gpl-2.0 |
dimitdim/pineapple | strawberry/fpga/blk_mem_gen_v7_3.vhd | 2 | 5482 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v7_3.vhd when simulating
-- the core, blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v7_3 IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END blk_mem_gen_v7_3;
ARCHITECTURE blk_mem_gen_v7_3_a OF blk_mem_gen_v7_3 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_gen_v7_3
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_gen_v7_3 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 16,
c_addrb_width => 16,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "blk_mem_gen_v7_3.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 43000,
c_read_depth_b => 43000,
c_read_width_a => 10,
c_read_width_b => 10,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 43000,
c_write_depth_b => 43000,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 10,
c_write_width_b => 10,
c_xdevicefamily => "spartan3"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v7_3
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END blk_mem_gen_v7_3_a;
| gpl-2.0 |
jslhs/hackrf | firmware/cpld/sgpio_if/top_tb.vhd | 19 | 3604 | --
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
COMPONENT top
PORT(
HOST_DATA : INOUT std_logic_vector(7 downto 0);
HOST_CAPTURE : OUT std_logic;
HOST_DISABLE : IN std_logic;
HOST_DIRECTION : IN std_logic;
HOST_DECIM_SEL : IN std_logic_vector(2 downto 0);
DA : IN std_logic_vector(7 downto 0);
DD : OUT std_logic_vector(9 downto 0);
CODEC_CLK : IN std_logic;
CODEC_X2_CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal DA : std_logic_vector(7 downto 0) := (others => '0');
signal CODEC_CLK : std_logic := '0';
signal CODEC_X2_CLK : std_logic := '0';
signal HOST_DISABLE : std_logic := '1';
signal HOST_DIRECTION : std_logic := '0';
signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010";
--BiDirs
signal HOST_DATA : std_logic_vector(7 downto 0);
--Outputs
signal DD : std_logic_vector(9 downto 0);
signal HOST_CAPTURE : std_logic;
begin
uut: top PORT MAP (
HOST_DATA => HOST_DATA,
HOST_CAPTURE => HOST_CAPTURE,
HOST_DISABLE => HOST_DISABLE,
HOST_DIRECTION => HOST_DIRECTION,
HOST_DECIM_SEL => HOST_DECIM_SEL,
DA => DA,
DD => DD,
CODEC_CLK => CODEC_CLK,
CODEC_X2_CLK => CODEC_X2_CLK
);
clk_process :process
begin
CODEC_CLK <= '1';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
CODEC_CLK <= '0';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
end process;
adc_proc: process
begin
wait until rising_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000000";
wait until falling_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000001";
end process;
sgpio_proc: process
begin
HOST_DATA <= (others => 'Z');
HOST_DIRECTION <= '0';
HOST_DISABLE <= '1';
wait for 135 ns;
HOST_DISABLE <= '0';
wait for 1000 ns;
HOST_DISABLE <= '1';
wait for 100 ns;
HOST_DIRECTION <= '1';
wait for 100 ns;
HOST_DISABLE <= '0';
for i in 0 to 10 loop
HOST_DATA <= (others => '0');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
HOST_DATA <= (others => '1');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
end loop;
wait;
end process;
end;
| gpl-2.0 |
tmeissner/raspberrypi | raspiFpga/src/RaspiFpgaE.vhd | 1 | 8892 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library machxo2;
use machxo2.components.all;
entity RaspiFpgaE is
port (
--+ SPI slave if
SpiSclk_i : inout std_logic;
SpiSte_i : in std_logic;
SpiMosi_i : inout std_logic;
SpiMiso_o : inout std_logic;
--* interrupt line to raspi
RaspiIrq_o : out std_logic
);
end entity RaspiFpgaE;
architecture rtl of RaspiFpgaE is
--+ Wishbone master component
component WishBoneMasterE is
generic (
G_ADR_WIDTH : positive := 8; --* address bus width
G_DATA_WIDTH : positive := 8 --* data bus width
);
port (
--+ wishbone system if
WbRst_i : in std_logic;
WbClk_i : in std_logic;
--+ wishbone outputs
WbCyc_o : out std_logic;
WbStb_o : out std_logic;
WbWe_o : out std_logic;
WbAdr_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
--+ wishbone inputs
WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
WbAck_i : in std_logic;
WbErr_i : in std_logic;
--+ local register if
LocalWen_i : in std_logic;
LocalRen_i : in std_logic;
LocalAdress_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
LocalAck_o : out std_logic;
LocalError_o : out std_logic
);
end component WishBoneMasterE;
component RaspiFpgaCtrlE is
port (
--+ System if
Rst_n_i : in std_logic;
Clk_i : in std_logic;
--+ local register if
LocalWen_o : out std_logic;
LocalRen_o : out std_logic;
LocalAdress_o : out std_logic_vector(7 downto 0);
LocalData_i : in std_logic_vector(7 downto 0);
LocalData_o : out std_logic_vector(7 downto 0);
LocalAck_i : in std_logic;
LocalError_i : in std_logic;
--+ EFB if
EfbSpiIrq_i : in std_logic;
--+ RNG if
RngStart_o : out std_logic;
RngWait_o : out std_logic_vector(7 downto 0);
RngRun_o : out std_logic_vector(7 downto 0);
RngDataValid_i : in std_logic;
RngData_i : in std_logic_vector(7 downto 0)
);
end component RaspiFpgaCtrlE;
component FiRoCtrlE is
generic (
EXTRACT : boolean := true
);
port (
--+ system if
Clk_i : in std_logic;
Reset_i : in std_logic;
--+ ctrl/status
Start_i : in std_logic;
Wait_i : in std_logic_vector(7 downto 0);
Run_i : in std_logic_vector(7 downto 0);
--+ rnd data
DataValid_o : out std_logic;
Data_o : out std_logic_vector(7 downto 0);
-- firo
Run_o : out std_logic;
Data_i : in std_logic
);
end component FiRoCtrlE;
component FiRoE is
generic (
IMP : string := "HDL",
TOGGLE : boolean := true
);
port (
FiRo_o : out std_logic;
Run_i : in std_logic
);
end component FiRoE;
--+ EFB SPI slave component
component EfbSpiSlave is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_ack_o : out std_logic;
spi_clk : inout std_logic;
spi_miso : inout std_logic;
spi_mosi : inout std_logic;
spi_scsn : in std_logic;
spi_irq : out std_logic
);
end component EfbSpiSlave;
--+ oscillator component
component OSCH is
generic (
NOM_FREQ : string := "26.60"
);
port (
STDBY : in std_logic;
OSC : out std_logic;
SEDSTDBY : out std_logic
);
end component OSCH;
attribute NOM_FREQ : string;
attribute NOM_FREQ of i_OSC : label is "26.60";
--+ system signals
signal s_sys_clk : std_logic;
signal s_sys_rst : std_logic := '1';
signal s_spi_sclk : std_logic;
signal s_spi_miso : std_logic;
signal s_spi_mosi : std_logic;
--+ Wishbone bus signals
signal s_wb_clk : std_logic;
signal s_wb_rst : std_logic;
signal s_wb_cyc : std_logic;
signal s_wb_stb : std_logic;
signal s_wb_we : std_logic;
signal s_wb_adr : std_logic_vector(7 downto 0);
signal s_wb_master_dat : std_logic_vector(7 downto 0);
signal s_wb_slave_dat : std_logic_vector(7 downto 0);
signal s_wb_ack : std_logic;
--+ EFB signals
signal s_efb_irq : std_logic;
--+ Wishbone master signals
signal s_local_wen : std_logic;
signal s_local_ren : std_logic;
signal s_local_adr : std_logic_vector(7 downto 0);
signal s_local_read_data : std_logic_vector(7 downto 0);
signal s_local_write_data : std_logic_vector(7 downto 0);
signal s_local_ack : std_logic;
--+ RNG signals
signal s_rng_start : std_logic;
signal s_rng_wait : std_logic_vector(7 downto 0);
signal s_rng_run : std_logic_vector(7 downto 0);
signal s_rng_data_valid : std_logic;
signal s_rng_data : std_logic_vector(7 downto 0);
signal s_firo_run : std_logic;
signal s_firo_data : std_logic;
begin
--+ Oscillator instance
--+ It's generating our 26.6 MHz system lock
i_OSC : OSCH
generic map (
NOM_FREQ => "26.60"
)
port map (
STDBY => '0',
OSC => s_sys_clk,
SEDSTDBY => open
);
s_wb_clk <= s_sys_clk;
s_wb_rst <= not(s_sys_rst);
ResetP : process (s_sys_clk) is
variable v_clk_count : natural range 0 to 15 := 15;
begin
if(rising_edge(s_sys_clk)) then
if(v_clk_count = 0) then
s_sys_rst <= '1';
else
s_sys_rst <= '0';
v_clk_count := v_clk_count - 1;
end if;
end if;
end process ResetP;
--+ EFB SPI slave instance
i_EfbSpiSlave : EfbSpiSlave
port map (
wb_clk_i => s_wb_clk,
wb_rst_i => s_wb_rst,
wb_cyc_i => s_wb_cyc,
wb_stb_i => s_wb_stb,
wb_we_i => s_wb_we,
wb_adr_i => s_wb_adr,
wb_dat_i => s_wb_master_dat,
wb_dat_o => s_wb_slave_dat,
wb_ack_o => s_wb_ack,
spi_clk => SpiSclk_i,
spi_miso => SpiMiso_o,
spi_mosi => SpiMosi_i,
spi_scsn => SpiSte_i,
spi_irq => s_efb_irq
);
i_WishBoneMasterE : WishBoneMasterE
generic map (
G_ADR_WIDTH => 8,
G_DATA_WIDTH => 8
)
port map (
--+ wishbone system if
WbRst_i => s_wb_rst,
WbClk_i => s_wb_clk,
--+ wishbone outputs
WbCyc_o => s_wb_cyc,
WbStb_o => s_wb_stb,
WbWe_o => s_wb_we,
WbAdr_o => s_wb_adr,
WbDat_o => s_wb_master_dat,
--+ wishbone inputs
WbDat_i => s_wb_slave_dat,
WbAck_i => s_wb_ack,
WbErr_i => '0',
--+ local register if
LocalWen_i => s_local_wen,
LocalRen_i => s_local_ren,
LocalAdress_i => s_local_adr,
LocalData_i => s_local_write_data,
LocalData_o => s_local_read_data,
LocalAck_o => s_local_ack,
LocalError_o => open
);
i_RaspiFpgaCtrlE : RaspiFpgaCtrlE
port map (
--+ System if
Rst_n_i => s_sys_rst,
Clk_i => s_sys_clk,
--+ local register if
LocalWen_o => s_local_wen,
LocalRen_o => s_local_ren,
LocalAdress_o => s_local_adr,
LocalData_i => s_local_read_data,
LocalData_o => s_local_write_data,
LocalAck_i => s_local_ack,
LocalError_i => '0',
--+ EFB if
EfbSpiIrq_i => s_efb_irq,
--+ RNG if
RngStart_o => s_rng_start,
RngWait_o => s_rng_wait,
RngRun_o => s_rng_run,
RngDataValid_i => s_rng_data_valid,
RngData_i => s_rng_data
);
i_FiRoCtrlE : FiRoCtrlE
generic map (
EXTRACT => true
)
port map (
--+ system if
Clk_i => s_sys_clk,
Reset_i => s_sys_rst,
--+ ctrl/status
Start_i => s_rng_start,
Wait_i => s_rng_wait,
Run_i => s_rng_run,
--+ rnd data
DataValid_o => s_rng_data_valid,
Data_o => s_rng_data,
-- firo
Run_o => s_firo_run,
Data_i => s_firo_data
);
i_FiRoE : FiRoE
generic map (
IMP => "LUT",
TOGGLE => true
)
port map (
FiRo_o => s_firo_data,
Run_i => s_firo_run
);
RaspiIrq_o <= '0';
end architecture rtl;
| gpl-2.0 |
dimitdim/pineapple | strawberry/fpga/blk_mem_gen_v7_3/simulation/addr_gen.vhd | 101 | 4409 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/Instruction_streams_packages/i_fetch_test_stream_mul.vhd | 3 | 7087 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- All instructions are mul $2 $2 $2
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
(X"00421019_00421019_00421019_00421019", -- Loc 0C, 08, 04, 00
X"00421019_00421019_00421019_00421019", -- Loc 1C, 18, 14, 10
X"00421019_00421019_00421019_00421019", -- Loc 2C, 28, 24, 20
X"00421019_00421019_00421019_00421019", -- Loc 3C, 38, 34, 30
X"00421019_00421019_00421019_00421019", -- Loc 4C, 48, 44, 40
X"00421019_00421019_00421019_00421019", -- Loc 5C, 58, 54, 50
X"00421019_00421019_00421019_00421019", -- Loc 6C, 68, 64, 60
X"00421019_00421019_00421019_00421019", -- Loc 7C, 78, 74, 70
X"00421019_00421019_00421019_00421019", -- Loc 8C, 88, 84, 80
X"00421019_00421019_00421019_00421019", -- Loc 9C, 98, 94, 90
X"00421019_00421019_00421019_00421019", -- Loc AC, A8, A4, A0
X"00421019_00421019_00421019_00421019", -- Loc BC, B8, B4, B0
X"00421019_00421019_00421019_00421019", -- Loc CC, C8, C4, C0
X"00421019_00421019_00421019_00421019", -- Loc DC, D8, D4, D0
X"00421019_00421019_00421019_00421019", -- Loc EC, E8, E4, E0
X"00421019_00421019_00421019_00421019", -- Loc FC, F8, F4, F0
X"00421019_00421019_00421019_00421019", -- Loc 10C, 108, 104, 100
X"00421019_00421019_00421019_00421019", -- Loc 11C, 118, 114, 110
X"00421019_00421019_00421019_00421019", -- Loc 12C, 128, 124, 120
X"00421019_00421019_00421019_00421019", -- Loc 13C, 138, 134, 130
X"00421019_00421019_00421019_00421019", -- Loc 14C, 148, 144, 140
X"00421019_00421019_00421019_00421019", -- Loc 15C, 158, 154, 150
X"00421019_00421019_00421019_00421019", -- Loc 16C, 168, 164, 160
X"00421019_00421019_00421019_00421019", -- Loc 17C, 178, 174, 170
X"00421019_00421019_00421019_00421019", -- Loc 18C, 188, 184, 180
X"00421019_00421019_00421019_00421019", -- Loc 19C, 198, 194, 190
X"00421019_00421019_00421019_00421019", -- Loc 1AC, 1A8, 1A4, 1A0
X"00421019_00421019_00421019_00421019", -- Loc 1BC, 1B8, 1B4, 1B0
X"00421019_00421019_00421019_00421019", -- Loc 1CC, 1C8, 1C4, 1C0
X"00421019_00421019_00421019_00421019", -- Loc 1DC, 1D8, 1D4, 1D0
X"00421019_00421019_00421019_00421019", -- Loc 1EC, 1E8, 1E4, 1E0
X"00421019_00421019_00421019_00421019", -- Loc 1FC, 1F8, 1F4, 1F0
X"00421019_00421019_00421019_00421019", -- Loc 20C, 208, 204, 200
X"00421019_00421019_00421019_00421019", -- Loc 21C, 218, 214, 221
X"00421019_00421019_00421019_00421019", -- Loc 22C, 228, 224, 220
X"00421019_00421019_00421019_00421019", -- Loc 23C, 238, 234, 230
X"00421019_00421019_00421019_00421019", -- Loc 24C, 248, 244, 240
X"00421019_00421019_00421019_00421019", -- Loc 25C, 258, 254, 250
X"00421019_00421019_00421019_00421019", -- Loc 26C, 268, 264, 260
X"00421019_00421019_00421019_00421019", -- Loc 27C, 278, 274, 270
X"00421019_00421019_00421019_00421019", -- Loc 28C, 288, 284, 280
X"00421019_00421019_00421019_00421019", -- Loc 29C, 298, 294, 290
X"00421019_00421019_00421019_00421019", -- Loc 2AC, 2A8, 2A4, 2A0
X"00421019_00421019_00421019_00421019", -- Loc 2BC, 2B8, 2B4, 2B0
X"00421019_00421019_00421019_00421019", -- Loc 2CC, 2C8, 2C4, 2C0
X"00421019_00421019_00421019_00421019", -- Loc 2DC, 2D8, 2D4, 2D0
X"00421019_00421019_00421019_00421019", -- Loc 2EC, 2E8, 2E4, 2E0
X"00421019_00421019_00421019_00421019", -- Loc 2FC, 2F8, 2F4, 2F0
X"00421019_00421019_00421019_00421019", -- Loc 30C, 308, 304, 300
X"00421019_00421019_00421019_00421019", -- Loc 31C, 318, 314, 331
X"00421019_00421019_00421019_00421019", -- Loc 32C, 328, 324, 320
X"00421019_00421019_00421019_00421019", -- Loc 33C, 338, 334, 330
X"00421019_00421019_00421019_00421019", -- Loc 34C, 348, 344, 340
X"00421019_00421019_00421019_00421019", -- Loc 35C, 358, 354, 350
X"00421019_00421019_00421019_00421019", -- Loc 36C, 368, 364, 360
X"00421019_00421019_00421019_00421019", -- Loc 37C, 378, 374, 370
X"00421019_00421019_00421019_00421019", -- Loc 38C, 388, 384, 380
X"00421019_00421019_00421019_00421019", -- Loc 39C, 398, 394, 390
X"00421019_00421019_00421019_00421019", -- Loc 3AC, 3A8, 3A4, 3A0
X"00421019_00421019_00421019_00421019", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/GC_fifo/simulation/fg_tb_dgen.vhd | 36 | 4510 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/write_data_fifo/simulation/fg_tb_dgen.vhd | 36 | 4510 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/ssd_command_fifo/simulation/fg_tb_dgen.vhd | 36 | 4510 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/controller_command_fifo/simulation/fg_tb_dgen.vhd | 36 | 4510 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/ssd_command_fifo/simulation/fg_tb_dgen.vhd | 36 | 4510 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_sim/megatb/i_fetch_test_stream_add.vhd | 3 | 7087 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- All instructions are add $2 $2 $2
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
(X"00421020_00421020_00421020_00421020", -- Loc 0C, 08, 04, 00
X"00421020_00421020_00421020_00421020", -- Loc 1C, 18, 14, 10
X"00421020_00421020_00421020_00421020", -- Loc 2C, 28, 24, 20
X"00421020_00421020_00421020_00421020", -- Loc 3C, 38, 34, 30
X"00421020_00421020_00421020_00421020", -- Loc 4C, 48, 44, 40
X"00421020_00421020_00421020_00421020", -- Loc 5C, 58, 54, 50
X"00421020_00421020_00421020_00421020", -- Loc 6C, 68, 64, 60
X"00421020_00421020_00421020_00421020", -- Loc 7C, 78, 74, 70
X"00421020_00421020_00421020_00421020", -- Loc 8C, 88, 84, 80
X"00421020_00421020_00421020_00421020", -- Loc 9C, 98, 94, 90
X"00421020_00421020_00421020_00421020", -- Loc AC, A8, A4, A0
X"00421020_00421020_00421020_00421020", -- Loc BC, B8, B4, B0
X"00421020_00421020_00421020_00421020", -- Loc CC, C8, C4, C0
X"00421020_00421020_00421020_00421020", -- Loc DC, D8, D4, D0
X"00421020_00421020_00421020_00421020", -- Loc EC, E8, E4, E0
X"00421020_00421020_00421020_00421020", -- Loc FC, F8, F4, F0
X"00421020_00421020_00421020_00421020", -- Loc 10C, 108, 104, 100
X"00421020_00421020_00421020_00421020", -- Loc 11C, 118, 114, 110
X"00421020_00421020_00421020_00421020", -- Loc 12C, 128, 124, 120
X"00421020_00421020_00421020_00421020", -- Loc 13C, 138, 134, 130
X"00421020_00421020_00421020_00421020", -- Loc 14C, 148, 144, 140
X"00421020_00421020_00421020_00421020", -- Loc 15C, 158, 154, 150
X"00421020_00421020_00421020_00421020", -- Loc 16C, 168, 164, 160
X"00421020_00421020_00421020_00421020", -- Loc 17C, 178, 174, 170
X"00421020_00421020_00421020_00421020", -- Loc 18C, 188, 184, 180
X"00421020_00421020_00421020_00421020", -- Loc 19C, 198, 194, 190
X"00421020_00421020_00421020_00421020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00421020_00421020_00421020_00421020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00421020_00421020_00421020_00421020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00421020_00421020_00421020_00421020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00421020_00421020_00421020_00421020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00421020_00421020_00421020_00421020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00421020_00421020_00421020_00421020", -- Loc 20C, 208, 204, 200
X"00421020_00421020_00421020_00421020", -- Loc 21C, 218, 214, 221
X"00421020_00421020_00421020_00421020", -- Loc 22C, 228, 224, 220
X"00421020_00421020_00421020_00421020", -- Loc 23C, 238, 234, 230
X"00421020_00421020_00421020_00421020", -- Loc 24C, 248, 244, 240
X"00421020_00421020_00421020_00421020", -- Loc 25C, 258, 254, 250
X"00421020_00421020_00421020_00421020", -- Loc 26C, 268, 264, 260
X"00421020_00421020_00421020_00421020", -- Loc 27C, 278, 274, 270
X"00421020_00421020_00421020_00421020", -- Loc 28C, 288, 284, 280
X"00421020_00421020_00421020_00421020", -- Loc 29C, 298, 294, 290
X"00421020_00421020_00421020_00421020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00421020_00421020_00421020_00421020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00421020_00421020_00421020_00421020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00421020_00421020_00421020_00421020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00421020_00421020_00421020_00421020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00421020_00421020_00421020_00421020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00421020_00421020_00421020_00421020", -- Loc 30C, 308, 304, 300
X"00421020_00421020_00421020_00421020", -- Loc 31C, 318, 314, 331
X"00421020_00421020_00421020_00421020", -- Loc 32C, 328, 324, 320
X"00421020_00421020_00421020_00421020", -- Loc 33C, 338, 334, 330
X"00421020_00421020_00421020_00421020", -- Loc 34C, 348, 344, 340
X"00421020_00421020_00421020_00421020", -- Loc 35C, 358, 354, 350
X"00421020_00421020_00421020_00421020", -- Loc 36C, 368, 364, 360
X"00421020_00421020_00421020_00421020", -- Loc 37C, 378, 374, 370
X"00421020_00421020_00421020_00421020", -- Loc 38C, 388, 384, 380
X"00421020_00421020_00421020_00421020", -- Loc 39C, 398, 394, 390
X"00421020_00421020_00421020_00421020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00421020_00421020_00421020_00421020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/AddBuff_r2_NEW.vhd | 2 | 23639 | -- CHECKED AND MODIFIED BY PRASANJEET
-------------------------------------------
--UPDATED ON: 7/9/09
-------------------------------------------
-- CHECKED AND MODIFIED BY WALEED
-------------------------------------------
--UPDATED ON: 6/4/10
-------------------------------------------
-------------------------------------------------------------------------------
--
-- Design : Load/Store Address Buff
-- Project : Tomasulo Processor
-- Author : Rohit Goel
-- Company : University of Southern California
--
-------------------------------------------------------------------------------
--
-- File : AddBuff.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The Issue control controls the Issuque
-------------------------------------------------------------------------------
--library declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity AddBuff is
port (
-- Global Clk and Resetb Signals
Clk : in std_logic;
Resetb : in std_logic;
AddrBuffFull : out std_logic; --buffer full
AddrMatch0 : out std_logic;
AddrMatch1 : out std_logic;
AddrMatch2 : out std_logic;
AddrMatch3 : out std_logic;
AddrMatch4 : out std_logic;
AddrMatch5 : out std_logic;
AddrMatch6 : out std_logic;
AddrMatch7 : out std_logic;
AddrMatch0Num : out std_logic_vector (2 downto 0);
AddrMatch1Num : out std_logic_vector (2 downto 0);
AddrMatch2Num : out std_logic_vector (2 downto 0);
AddrMatch3Num : out std_logic_vector (2 downto 0);
AddrMatch4Num : out std_logic_vector (2 downto 0);
AddrMatch5Num : out std_logic_vector (2 downto 0);
AddrMatch6Num : out std_logic_vector (2 downto 0);
AddrMatch7Num : out std_logic_vector (2 downto 0);
ScanAddr0 : in std_logic_vector (31 downto 0); --scan address (address of entries in lsq)
ScanAddr1 : in std_logic_vector (31 downto 0);
ScanAddr2 : in std_logic_vector (31 downto 0);
ScanAddr3 : in std_logic_vector (31 downto 0);
ScanAddr4 : in std_logic_vector (31 downto 0); --scan address (address of entries in lsq)
ScanAddr5 : in std_logic_vector (31 downto 0);
ScanAddr6 : in std_logic_vector (31 downto 0);
ScanAddr7 : in std_logic_vector (31 downto 0);
LsqSwAddr : in std_logic_vector (36 downto 0); --ld/sw address
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector (4 downto 0);
Cdb_RobDepth : in std_logic_vector (4 downto 0);
StrAddr : in std_logic; -- control signal indicating to store address
SB_FlushSw : in std_logic; --flush store
SB_FlushSwTag : in std_logic_vector (1 downto 0); --flush store tag
SBTag_counter : in std_logic_vector (1 downto 0);
--Interface with ROB
Rob_CommitMemWrite : in std_logic
);
end AddBuff;
architecture behave of AddBuff is
type array_8_32 is array (0 to 7) of std_logic_vector(31 downto 0); --data
type array_8_6 is array (0 to 7) of std_logic_vector(4 downto 0); --ROBtag
type array_8_2 is array (0 to 7) of std_logic_vector(1 downto 0); --SBtag
type array_8_1 is array (0 to 7) of std_logic; --tagSelect
signal BuffAdd : array_8_32;
signal BuffRobTag : array_8_6;
signal BufValid : std_logic_vector (7 downto 0); --buffer valid
signal BufferDepth : array_8_6;
signal BuffSBTag : array_8_2;
signal BuffTagSel : array_8_1;
---Mod OAR: 24 Jul 09: Added one Flush
signal Flush : std_logic_vector ( 8 downto 0);
signal En : std_logic_vector ( 6 downto 0);
signal AddrMatch0NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch1NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch2NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch3NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch4NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch5NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch6NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch7NumTemp : std_logic_vector(2 downto 0);
begin
--***********************************************************************************************
-- The following 7 processes are used to perform associative search required for Memory Disambiguation.
-- Since we have 8 entries in the load/store issue queue (LSQ) then we need 8 processes one for each memory
-- address (ScanAddr). The associative search is combinational and is implemented for every memory address
-- in LSQ regardless whether the instruction in LSQ is Load or Store. However, we just need the results of the
-- associative search for Load instructions.
-- Task1: You are given the code completed for generating the number of matches for the first 7 addresses in
-- LSQ (ScanAddr0 to ScanAddr6). You are required to Add the code for the associative search of matches to
-- "ScanAddr7".
--***********************************************************************************************
process (ScanAddr0 ,BuffAdd ,BufValid)
variable Add0MatchTemp : std_logic_vector (2 downto 0);
begin
Add0MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr0 and BufValid(i) = '1') then --valid and address matched
Add0MatchTemp := unsigned(Add0MatchTemp) + 1; -- increment address match index
else
Add0MatchTemp := Add0MatchTemp;
end if;
end loop;
AddrMatch0NumTemp <= Add0MatchTemp;
end process;
process (ScanAddr1 ,BuffAdd,BufValid )
variable Add1MatchTemp : std_logic_vector (2 downto 0);
begin
Add1MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr1 and BufValid(i) = '1') then
Add1MatchTemp := unsigned(Add1MatchTemp) + 1;
else
Add1MatchTemp := Add1MatchTemp;
end if;
end loop;
AddrMatch1NumTemp <= Add1MatchTemp;
end process;
process (ScanAddr2 ,BuffAdd ,BufValid)
variable Add2MatchTemp : std_logic_vector (2 downto 0);
begin
Add2MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr2 and BufValid(i) = '1') then
Add2MatchTemp := unsigned(Add2MatchTemp) + 1;
else
Add2MatchTemp := Add2MatchTemp;
end if;
end loop;
AddrMatch2NumTemp <=Add2MatchTemp;
end process ;
process (ScanAddr3 ,BuffAdd ,BufValid)
variable Add3MatchTemp : std_logic_vector (2 downto 0);
begin
Add3MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr3 and BufValid(i) = '1') then
Add3MatchTemp := unsigned(Add3MatchTemp) + 1;
else
Add3MatchTemp := Add3MatchTemp;
end if;
end loop;
AddrMatch3NumTemp <= Add3MatchTemp;
end process ;
process (ScanAddr4 ,BuffAdd ,BufValid)
variable Add4MatchTemp : std_logic_vector (2 downto 0);
begin
Add4MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr4 and BufValid(i) = '1') then
Add4MatchTemp := unsigned(Add4MatchTemp) + 1;
else
Add4MatchTemp := Add4MatchTemp;
end if;
end loop;
AddrMatch4NumTemp <= Add4MatchTemp;
end process ;
process (ScanAddr5 ,BuffAdd ,BufValid)
variable Add5MatchTemp : std_logic_vector (2 downto 0);
begin
Add5MatchTemp := "000";
for i in 0 to 7 loop
if ( BuffAdd(i) = ScanAddr5 and BufValid(i) = '1' ) then
Add5MatchTemp := unsigned(Add5MatchTemp) + 1;
else
Add5MatchTemp := Add5MatchTemp;
end if;
end loop;
AddrMatch5NumTemp <= Add5MatchTemp;
end process;
process (ScanAddr6 ,BuffAdd ,BufValid)
variable Add6MatchTemp : std_logic_vector (2 downto 0);
begin
Add6MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr6 and BufValid(i) = '1') then
Add6MatchTemp := unsigned(Add6MatchTemp) + 1;
else
Add6MatchTemp := Add6MatchTemp;
end if;
end loop;
AddrMatch6NumTemp <= Add6MatchTemp;
end process;
process (ScanAddr7 ,BuffAdd ,BufValid)
variable Add7MatchTemp : std_logic_vector (2 downto 0);
begin
Add7MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr7 and BufValid(i) = '1') then
Add7MatchTemp := unsigned(Add7MatchTemp) + 1;
else
Add7MatchTemp := Add7MatchTemp;
end if;
end loop;
AddrMatch7NumTemp <= Add7MatchTemp;
end process;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- After we generate the internal Signals for the number of matches for each of the memory addresses
-- in LSQ (ScanAddr0 to ScanAddr7). We need to map the internal signals to the corresponding output ports
-- (AddrMatch0Num to AddrMatch7Match). At the same time we set the bit that indicates that there was at
-- least one match for each of the input addresses.
-- Task2: Add you code to map the matching results of ScanAddr7 to their respective output ports.
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
process (AddrMatch0NumTemp) --depending upon address match index
begin
AddrMatch0 <= '0';
AddrMatch0Num <= "000";
if (AddrMatch0NumTemp > "000") then
AddrMatch0 <= '1'; --just make a note that address is matched
AddrMatch0Num <= AddrMatch0NumTemp;
end if;
end process ;
process (AddrMatch1NumTemp)
begin
AddrMatch1 <= '0';
AddrMatch1Num <= "000";
if (AddrMatch1NumTemp > "000") then
AddrMatch1 <= '1';
AddrMatch1Num <= AddrMatch1NumTemp;
end if;
end process;
process (AddrMatch2NumTemp)
begin
AddrMatch2 <= '0';
AddrMatch2Num <= "000";
if ( AddrMatch2NumTemp > "000") then
AddrMatch2 <= '1';
AddrMatch2Num <= AddrMatch2NumTemp;
end if;
end process;
process (AddrMatch3NumTemp)
begin
AddrMatch3 <= '0';
AddrMatch3Num <= "000";
if (AddrMatch3NumTemp > "000") then
AddrMatch3 <= '1';
AddrMatch3Num <= AddrMatch3NumTemp;
end if;
end process;
process (AddrMatch4NumTemp)
begin
AddrMatch4 <= '0';
AddrMatch4Num <= "000";
if (AddrMatch4NumTemp > "000") then
AddrMatch4 <= '1';
AddrMatch4Num <= AddrMatch4NumTemp;
end if;
end process;
process (AddrMatch5NumTemp)
begin
AddrMatch5 <= '0';
AddrMatch5Num <= "000";
if (AddrMatch5NumTemp > "000") then
AddrMatch5 <= '1';
AddrMatch5Num <= AddrMatch5NumTemp;
end if;
end process;
process (AddrMatch6NumTemp)
begin
AddrMatch6 <= '0';
AddrMatch6Num <= "000";
if (AddrMatch6NumTemp > "000") then
AddrMatch6 <= '1';
AddrMatch6Num <= AddrMatch6NumTemp;
end if;
end process;
process (AddrMatch7NumTemp)
begin
AddrMatch7 <= '0';
AddrMatch7Num <= "000";
if (AddrMatch7NumTemp > "000") then
AddrMatch7 <= '1';
AddrMatch7Num <= AddrMatch7NumTemp;
end if;
end process;
--*************************************************************************************************************
-- This process is used to calculate Rob depth of all entries in address buffer to perform selective flushing in case of
-- branch misprediction. The Rob depth is the distance between the Rob entry of the instruction in the address buffer
-- and the Rob top pointer taking into consideration the fact that ROB is implemented as a circular buffer.
-- Task3: In this task we want to use the RobTag field of each address buffer entry (BuffRobTag array) to calculate
-- the Rob depth field of each entry (BufferDepth array).
--*************************************************************************************************************
process (BuffRobTag,Rob_TopPtr) --using buffer tag and rob pointer
begin
for i in 0 to 7 loop
BufferDepth(i) <= unsigned(BuffRobTag(i)) - unsigned(Rob_TopPtr);
end loop;
end process;
--********************************************************************************************************************
-- The value of the Depth you calculated in the previous process is used to decide whether the address buffer entry
-- must be flushed in case of branch misprediction or not. This of course depends on the Rob Depth of the mispredicted
-- branch and Rob Depth of the store instruction in the address buffer. When the branch Rob depth is smaller than the
-- Rob depth of address buffer entry then that entry is younger than the branch and hence must be flushed. This is known as
-- selective Flushing and is done once the branch instruction appears on Cdb and is mispredicted.
-- The following process is a very important process which takes care of generating the Flush signal of every
-- entry in the address buffer. There are two reasons for flushing address buffer entries:
-- 1) Selective flushing due to branch misprediction provided that the entry Rob depth is larger than that of the
-- mispredicted branch.
-- 2) When a store instruction writes to the cache and leaves the store buffer, we need to flush the corresponding
-- entry of that store in the address buffer. In this case need to use the SBTag to identify the address buffer
-- entry that must be flushed becasue the RobTag is released when the store instruction leaves the top of the
-- and enters the store buffer.
-- Task4: Write the code of the flushing process:
-- Hints: 1. Cdb_RobDepth in the sensitivity list is the Rob depth of the instruction that is currently on Cdb, so before decide
-- if you need to flush or not, you have to check Cdb_Flush input signal that indicates that the instruction on Cdb is
-- a mispredicted branch.
-- 2. You need to check the TagSel when you flush. if you are doing selective flushing and TagSel of one entry is set to 1
-- then there is no need to flush that entry because it belongs to a store instruction that has already left ROB and is
-- waiting in the store buffer to write to the cache. The same thing happen when you are flushing the entry of the store
-- which just finished writing to the cache, you need to check the TagSel, if it set to 0 then that entry belongs to a store
-- instruction which still in the ROB and hence it can NOT be the desired entry.
-- 3. There is only a single Flush bit per address buffer entry. This is enough because once a store instruction leaves ROB it
-- should never be flushed due to mis-prediction buffer but it needs to be flushed when the store leaves store buffer. This means
-- you can check both flush conditions mentioned above concurrently for each address buffer entry but at most one of the conditions
-- will set the Flush bit of that entry.
-- Flush(8) Special Case: Although we have 8 entries in address buffer and hence we just need 8-bit Flush signal (Flush[7:0]), we
-- one more additional bit namely (Flush[8]) to count for the case when a new store instruction is writing its address to the address
-- buffer at the same time when the Cdb_Flush signal becomes active. This case is already completed for you.
--********************************************************************************************************************
Flush(8) <= '1' when ((StrAddr = '1') AND (((unsigned(LsqSwAddr(36 downto 32))-unsigned(Rob_TopPtr))>Cdb_RobDepth)and Cdb_Flush = '1'))
else '0';
process (Cdb_Flush,Cdb_RobDepth,SB_FlushSw,SB_FlushSwTag,BufferDepth,BuffSBTag,BuffTagSel)
begin
for i in 0 to 7 loop
if (BufferDepth(i) > Cdb_RobDepth and Cdb_Flush = '1' and BuffTagSel(i) = '0') then
Flush(i) <= '1';
elsif (SB_FlushSw = '1' and SB_FlushSwTag = BuffSBTag(i) and BuffTagSel(i) = '1') then
Flush(i) <= '1';
else
Flush(i) <= '0';
end if;
end loop;
end process;
-- **************************************************************************************************
-- This process generates the shift enable signal that shifts all the entries in the address buffer.
-- As soon as you get a hole (empty entry) you shift all the upper entries down to fill it so that
-- A new entry is always written to the topmost location
-- **************************************************************************************************
process ( BufValid )
begin
if (BufValid(0) = '0') then
En(6 downto 0) <= "1111111"; --bottom is invalid(issued) so update all
elsif(BufValid(1) = '0') then
En(6 downto 0) <= "1111110";
elsif (BufValid(2) = '0' ) then
En(6 downto 0) <= "1111100";
elsif(BufValid(3) = '0') then
En(6 downto 0) <= "1111000";
elsif (BufValid(4) = '0' ) then
En(6 downto 0) <= "1110000";
elsif(BufValid(5) = '0') then
En(6 downto 0) <= "1100000";
elsif (BufValid(6) = '0' ) then
En(6 downto 0) <= "1000000";
else
En(6 downto 0) <= "0000000"; -- since except the top most others contain valid instruction so can't update, actually this allows the valid instruction to shift down
end if;
end process;
--if all entries are valid then address buffer full
AddrBuffFull <= Bufvalid(7) and BufValid(6) and Bufvalid(5) and Bufvalid(4) and BufValid(3)
and BufValid(2) and BufValid(1) and BufValid(0);
-- **************************************************************************************************
-- This is core clocked process used to update the address buffer entries. At Reset we set the Valid and the TagSel bits to '0'.
-- Since new store instructions write to the top most entry (entry(7)), we have a separate if statement for entry 7. For all other
-- entries (entry(6) to entry(0) we use a for loop.
-- Task5 is divided into two parts:
-- 1) You need to complete the last elsif condition for address buffer entry(7). This condition handles the communication
-- with the ROB. Basically you need to decide how should you update the different fields of address buffer entry(7) especially
-- SBTag field and TagSel field.
-- 2) You need to complete the else codition in for loop below. This else condition handle the case when no shift is required. How
-- would you update the different fields of the address buffer entries(6 to 0).
-- Hint: In Both parts give careful thinking on what you are going to write in SBTag and TagSel fields. You may need to include a nested
-- if statement.
-- **************************************************************************************************
process (Clk,Resetb)
begin
if (Resetb = '0') then
BufValid <= "00000000";
BuffTagSel <= "00000000";
elsif (Clk'event and Clk = '1') then
-- store the "sw" information always at the top
if (Flush(8) = '1') then ---if it's to be flushed don't update
BuffAdd(7) <= (others => '0');
BuffRobTag(7) <= (others => '0');
BufValid(7) <= '0';
BuffSBTag(7) <= (others => '0');
BuffTagSel(7) <= '0';
elsif (straddr = '1') then ---else put the incoming value on the top location.
BuffAdd(7) <= LsqSwAddr( 31 downto 0 );
BuffRobTag(7) <= LsqSwAddr( 36 downto 32 );
BufValid(7) <= '1';
BuffSBTag(7) <= (others => '0');
BuffTagSel(7) <= '0';
elsif (En(6) = '1') then ---else the next person is getting my values so I must go empty.
BuffAdd(7) <= (others => '0');
BuffRobTag(7) <= (others => '0');
BufValid(7) <= '0';
BuffSBTag(7) <= (others => '0');
BuffTagSel(7) <= '0';
elsif (Flush(7) = '1') then ---there is an instruction at the 7th location that is decided to be flushed. Mod25Jul09.
BuffAdd(7) <= (others => '0');
BuffRobTag(7) <= (others => '0');
BufValid(7) <= '0';
BuffSBTag(7) <= (others => '0');
BuffTagSel(7) <= '0';
elsif (Rob_CommitMemWrite = '1') then
if (BuffRobTag(7) = Rob_TopPtr and (BuffTagSel(7) = '0')) then
BuffSBTag(7) <= SBTag_counter;
BuffTagSel(7) <= '1';
end if;
end if;
for i in 0 to 6 loop --shift the others accordingly
if (Flush(i) = '1' and En(i) = '0') then
BuffAdd(i) <= (others => '0');
BuffRobTag(i) <= (others => '0');
BufValid(i) <= '0';
BuffSBTag(i) <= (others => '0');
BuffTagSel(i) <= '0';
else
if (En(i) = '1') then --shift update
BuffAdd(i) <= BuffAdd(i+1);
BuffRobTag(i) <= BuffRobTag(i+1);
BufValid(i) <= BufValid(i+1) and (not Flush(i+1)); --update , note the use of flush signal while updation
if ((Rob_CommitMemWrite = '1') and (BuffRobTag(i+1) = Rob_TopPtr) and (BuffTagSel(i+1) = '0'))then
BuffSBTag(i) <= SBTag_counter;
BuffTagSel(i) <= '1';
else
BuffSBTag(i) <= BuffSBTag(i+1);
BuffTagSel(i) <= BuffTagSel(i+1);
end if;
else
if (BuffRobTag(i) = Rob_TopPtr and (BuffTagSel(i) = '0') and (Rob_CommitMemWrite = '1')) then
BuffSBTag(i) <= SBTag_counter;
BuffTagSel(i) <= '1';
end if;
end if;
end if;
end loop;
end if;
end process;
end behave; | gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/TX_SEND_FIFO/example_design/TX_SEND_FIFO_top_wrapper.vhd | 1 | 18998 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: TX_SEND_FIFO_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity TX_SEND_FIFO_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end TX_SEND_FIFO_top_wrapper;
architecture xilinx of TX_SEND_FIFO_top_wrapper is
SIGNAL clk_i : std_logic;
component TX_SEND_FIFO_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : TX_SEND_FIFO_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_sim/megatb/inst_cache_dpram_r2_sim.vhd | 4 | 9310 | -------------------------------------------------------------------------------
--
-- Design : inst_cache_dpram (Dual Port RAM holding cache data)
-- In summer 2008, it was inst_cache_sprom (Single Port ROM holding the cache data)
-- Project : ee560 Tomosulo -- Instruction Cache Emulator
-- Author : Srinivas Vaduvatha , Gandhi Puvvada
-- Company : University of Southern California
-- Date last revised : 7/23/2008, 7/15/2009
-------------------------------------------------------------------------------
--
-- File : inst_cache_dpram_r2.vhd (produced by modifying Summer 2008 inst_cache_sprom_r1.vhd and data_mem_dp.vhd)
--
-------------------------------------------------------------------------------
--
-- Description : This BRAM is instantiated by the instr_cache module.
-- This holds the instructions.
-- In Summer 2008, it was a ROM (BRAM acting like a ROM) with inital
-- content (instruction stream) defined through a package called
-- instr_stream_pkg.
-- In Summer 2009, it is converted to a dual port RAM. The first port (Port a) is of read/write type
-- and it faciliatates downloading a file containing cache contents from a text file holding instructions
-- in hex notation, 4 instruction per line, with Instruction0 on the right-end of the line:
-- Instruction3_ Instruction2_Instruction1_Instruction0
-- Module features:
-- Data width & Address width - Generics
-- Port b: synchronous Read only (for the processor cache read operation)
-- Port a: synchronous Read/Write (for File I/O through Adept 2.0)
-- Infers BRAM resource in Xilinx FPGAs.
-- If the width / depth specified require more bits than in a single
-- BRAM, multiple BRAMs are automatically cascaded to form a larger
-- memory by the Xilinx XST. Memory has to be of (2**n) depth.
--
-------------------------------------------------------------------------------
-- libraries and use clauses
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
--synopsys translate_off
use work.instr_stream_pkg.all; -- instruction stream defining package
--synopsys translate_on
entity inst_cache_dpram is
generic (
DATA_WIDTH : integer := 128; --DATA_WIDTH_CONSTANT; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 --ADDR_WIDTH_CONSTANT -- defined as 6 in the instr_stream_pkg;
);
port (
clka : in std_logic;
addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
wea : in std_logic;
data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
ena : in std_logic;
clkb : in std_logic;
addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-- data_in_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- web : in std_logic;
data_out_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end inst_cache_dpram ;
architecture inferable of inst_cache_dpram is
-- signals declarations.
-- Note: A signal called "mem" of user defined type "mem_type" was declared
-- in a package called "instr_stream_pkg" refered in the use clause above.
-- It has lines similar to the following lines.
-- The initial content defines the stream of instructions.
-- -- type declarations
--type mem_type is array (0 to (2**ADDR_WIDTH)-1) of std_logic_vector((DATA_WIDTH-1) downto 0);
--*****************************************************************************************
-- This stream is used to generate the walking led pattern using memory mapped i/0
--*****************************************************************************************
--signal mem : mem_type
-- := (
-- X"AC180004_000CC01B_004C681B_0050601B", -- Loc 0C, 08, 04, 00
-- X"00000020_AC130004_AC120004_8DA90000", -- Loc 1C, 18, 14, 10 -- corrected
-- X"00000020_00000020_00000020_00000020", -- Loc 2C, 28, 24, 20
-- X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
-- X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
-- X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
-- X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
-- X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
-- X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
-- X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
-- X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
-- X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
-- X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
-- X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
-- X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
-- X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
-- X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
-- X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
-- X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
-- X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
-- X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
-- X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
-- X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
-- X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
-- X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
-- X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
-- X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
-- X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
-- X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
-- X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
-- X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
-- X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
-- X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
-- X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
-- X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
-- X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
-- X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
-- X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
-- X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
-- X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
-- X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
-- X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
-- X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
-- X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
-- X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
-- X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
-- X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
-- X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
-- X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
-- X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
-- X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
-- X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
-- X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
-- X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
-- X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
-- X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
-- X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
-- X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
-- X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
-- X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- -- the last 16 instructions are looping jump instructions
-- X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
-- X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
-- X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
-- X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
-- ) ;
begin
porta_oper : process (clka)
begin
if (clka = '1' and clka'event) then
if (wea = '1' and ena='1') then
mem(CONV_INTEGER(unsigned(addr_a))) <= data_in_a;
end if;
if( ena='1')then
data_out_a <= mem(CONV_INTEGER(unsigned(addr_a)));
end if;
end if;
end process;
portb_oper : process (clkb)
begin
if (clkb = '1' and clkb'event) then
-- if (web = '1') then
-- mem(CONV_INTEGER(addr_b)) := data_in_b;
-- end if;
data_out_b <= mem(CONV_INTEGER(unsigned(addr_b)));
end if;
end process;
end inferable ;
--- ===========================================================
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/RECV_REQ_QUEUE/example_design/RECV_REQ_QUEUE_top.vhd | 1 | 5002 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RECV_REQ_QUEUE_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RECV_REQ_QUEUE_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end RECV_REQ_QUEUE_top;
architecture xilinx of RECV_REQ_QUEUE_top is
SIGNAL clk_i : std_logic;
component RECV_REQ_QUEUE is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : RECV_REQ_QUEUE PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/RESPONSE_QUEUE/example_design/RESPONSE_QUEUE_top.vhd | 1 | 4798 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RESPONSE_QUEUE_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RESPONSE_QUEUE_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end RESPONSE_QUEUE_top;
architecture xilinx of RESPONSE_QUEUE_top is
SIGNAL clk_i : std_logic;
component RESPONSE_QUEUE is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : RESPONSE_QUEUE PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/RECV_REQ_QUEUE/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/TargetCmdFIFO/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/Finished_Cmd_FIFO/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/ssd_command_fifo/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/DMA_READ_QUEUE/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/pcie_command_send_fifo/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/RD_FLASH_PRE_FIFO/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/pcie_data_rec_fifo/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.