repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2092.vhd | 4 | 2650 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2092.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02092ent IS
END c07s02b04x00p20n01i02092ent;
ARCHITECTURE c07s02b04x00p20n01i02092arch OF c07s02b04x00p20n01i02092ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4_up is boolean_v (1 to 4);
SUBTYPE boolean_8_up is boolean_v (1 to 8);
SUBTYPE boolean_4_dwn is boolean_v (4 downto 1);
BEGIN
TESTING: PROCESS
variable l_operand : boolean_4_up := (true, true, false, false);
variable r_operand : boolean_4_dwn:= (false, false, true, true);
variable result : boolean_8_up;
BEGIN
result := l_operand & r_operand;
assert ( result (1) = true )
report "result (1) /= true" severity FAILURE;
assert ( result (4) = false )
report "result (4) /= false" severity FAILURE;
assert ( result (5) = false )
report "result (5) /= false" severity FAILURE;
assert ( result (8) = true )
report "result (8) /= true" severity FAILURE;
assert NOT((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***PASSED TEST: c07s02b04x00p20n01i02092"
severity NOTE;
assert ((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***FAILED TEST: c07s02b04x00p20n01i02092 - Concatenated array should be ascending and the left bound is that of the first operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02092arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1274.vhd | 4 | 1654 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1274.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01274ent IS
END c08s04b00x00p04n01i01274ent;
ARCHITECTURE c08s04b00x00p04n01i01274arch OF c08s04b00x00p04n01i01274ent IS
signal b : integer := 5;
BEGIN
TESTING: PROCESS
subtype a is integer range 1 to 10;
BEGIN
a := b;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01274 - Target of signal assignment statement is not a signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01274arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_21.vhd | 4 | 2002 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_21.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( clock : in std_logic;
reset_n : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity reg;
-- not in book
architecture gate_level of reg is
begin
store : process (clock, reset_n) is
begin
if reset_n = '0' or reset_n = 'L' then
data_out <= (others => '0') after t_pd;
elsif rising_edge(clock) then
data_out <= data_in after t_pd;
end if;
end process store;
end architecture gate_level;
-- end not in book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi.vhd | 4 | 10579 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxi.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
use work.dlx_types.all;
package dlx_instr is
subtype dlx_opcode is bit_vector(0 to 5);
subtype dlx_sp_func is bit_vector(0 to 5);
subtype dlx_fp_func is bit_vector(0 to 4);
subtype dlx_reg_addr is bit_vector(0 to 4);
subtype dlx_immed16 is bit_vector(0 to 15);
subtype dlx_immed26 is bit_vector(0 to 25);
constant op_special : dlx_opcode := B"000000";
constant op_fparith : dlx_opcode := B"000001";
constant op_j : dlx_opcode := B"000010";
constant op_jal : dlx_opcode := B"000011";
constant op_beqz : dlx_opcode := B"000100";
constant op_bnez : dlx_opcode := B"000101";
constant op_bfpt : dlx_opcode := B"000110";
constant op_bfpf : dlx_opcode := B"000111";
constant op_addi : dlx_opcode := B"001000";
constant op_addui : dlx_opcode := B"001001";
constant op_subi : dlx_opcode := B"001010";
constant op_subui : dlx_opcode := B"001011";
constant op_andi : dlx_opcode := B"001100";
constant op_ori : dlx_opcode := B"001101";
constant op_xori : dlx_opcode := B"001110";
constant op_lhi : dlx_opcode := B"001111";
constant op_rfe : dlx_opcode := B"010000";
constant op_trap : dlx_opcode := B"010001";
constant op_jr : dlx_opcode := B"010010";
constant op_jalr : dlx_opcode := B"010011";
constant op_slli : dlx_opcode := B"010100";
constant op_undef_15 : dlx_opcode := B"010101";
constant op_srli : dlx_opcode := B"010110";
constant op_srai : dlx_opcode := B"010111";
constant op_seqi : dlx_opcode := B"011000";
constant op_snei : dlx_opcode := B"011001";
constant op_slti : dlx_opcode := B"011010";
constant op_sgti : dlx_opcode := B"011011";
constant op_slei : dlx_opcode := B"011100";
constant op_sgei : dlx_opcode := B"011101";
constant op_undef_1E : dlx_opcode := B"011110";
constant op_undef_1F : dlx_opcode := B"011111";
constant op_lb : dlx_opcode := B"100000";
constant op_lh : dlx_opcode := B"100001";
constant op_undef_22 : dlx_opcode := B"100010";
constant op_lw : dlx_opcode := B"100011";
constant op_lbu : dlx_opcode := B"100100";
constant op_lhu : dlx_opcode := B"100101";
constant op_lf : dlx_opcode := B"100110";
constant op_ld : dlx_opcode := B"100111";
constant op_sb : dlx_opcode := B"101000";
constant op_sh : dlx_opcode := B"101001";
constant op_undef_2A : dlx_opcode := B"101010";
constant op_sw : dlx_opcode := B"101011";
constant op_undef_2C : dlx_opcode := B"101100";
constant op_undef_2D : dlx_opcode := B"101101";
constant op_sf : dlx_opcode := B"101110";
constant op_sd : dlx_opcode := B"101111";
constant op_sequi : dlx_opcode := B"110000";
constant op_sneui : dlx_opcode := B"110001";
constant op_sltui : dlx_opcode := B"110010";
constant op_sgtui : dlx_opcode := B"110011";
constant op_sleui : dlx_opcode := B"110100";
constant op_sgeui : dlx_opcode := B"110101";
constant op_undef_36 : dlx_opcode := B"110110";
constant op_undef_37 : dlx_opcode := B"110111";
constant op_undef_38 : dlx_opcode := B"111000";
constant op_undef_39 : dlx_opcode := B"111001";
constant op_undef_3A : dlx_opcode := B"111010";
constant op_undef_3B : dlx_opcode := B"111011";
constant op_undef_3C : dlx_opcode := B"111100";
constant op_undef_3D : dlx_opcode := B"111101";
constant op_undef_3E : dlx_opcode := B"111110";
constant op_undef_3F : dlx_opcode := B"111111";
constant sp_func_nop : dlx_sp_func := B"000000";
constant sp_func_undef_01 : dlx_sp_func := B"000001";
constant sp_func_undef_02 : dlx_sp_func := B"000010";
constant sp_func_undef_03 : dlx_sp_func := B"000011";
constant sp_func_sll : dlx_sp_func := B"000100";
constant sp_func_undef_05 : dlx_sp_func := B"000101";
constant sp_func_srl : dlx_sp_func := B"000110";
constant sp_func_sra : dlx_sp_func := B"000111";
constant sp_func_undef_08 : dlx_sp_func := B"001000";
constant sp_func_undef_09 : dlx_sp_func := B"001001";
constant sp_func_undef_0A : dlx_sp_func := B"001010";
constant sp_func_undef_0B : dlx_sp_func := B"001011";
constant sp_func_undef_0C : dlx_sp_func := B"001100";
constant sp_func_undef_0D : dlx_sp_func := B"001101";
constant sp_func_undef_0E : dlx_sp_func := B"001110";
constant sp_func_undef_0F : dlx_sp_func := B"001111";
constant sp_func_sequ : dlx_sp_func := B"010000";
constant sp_func_sneu : dlx_sp_func := B"010001";
constant sp_func_sltu : dlx_sp_func := B"010010";
constant sp_func_sgtu : dlx_sp_func := B"010011";
constant sp_func_sleu : dlx_sp_func := B"010100";
constant sp_func_sgeu : dlx_sp_func := B"010101";
constant sp_func_undef_16 : dlx_sp_func := B"010110";
constant sp_func_undef_17 : dlx_sp_func := B"010111";
constant sp_func_undef_18 : dlx_sp_func := B"011000";
constant sp_func_undef_19 : dlx_sp_func := B"011001";
constant sp_func_undef_1A : dlx_sp_func := B"011010";
constant sp_func_undef_1B : dlx_sp_func := B"011011";
constant sp_func_undef_1C : dlx_sp_func := B"011100";
constant sp_func_undef_1D : dlx_sp_func := B"011101";
constant sp_func_undef_1E : dlx_sp_func := B"011110";
constant sp_func_undef_1F : dlx_sp_func := B"011111";
constant sp_func_add : dlx_sp_func := B"100000";
constant sp_func_addu : dlx_sp_func := B"100001";
constant sp_func_sub : dlx_sp_func := B"100010";
constant sp_func_subu : dlx_sp_func := B"100011";
constant sp_func_and : dlx_sp_func := B"100100";
constant sp_func_or : dlx_sp_func := B"100101";
constant sp_func_xor : dlx_sp_func := B"100110";
constant sp_func_undef_27 : dlx_sp_func := B"100111";
constant sp_func_seq : dlx_sp_func := B"101000";
constant sp_func_sne : dlx_sp_func := B"101001";
constant sp_func_slt : dlx_sp_func := B"101010";
constant sp_func_sgt : dlx_sp_func := B"101011";
constant sp_func_sle : dlx_sp_func := B"101100";
constant sp_func_sge : dlx_sp_func := B"101101";
constant sp_func_undef_2E : dlx_sp_func := B"101110";
constant sp_func_undef_2F : dlx_sp_func := B"101111";
constant sp_func_movi2s : dlx_sp_func := B"110000";
constant sp_func_movs2i : dlx_sp_func := B"110001";
constant sp_func_movf : dlx_sp_func := B"110010";
constant sp_func_movd : dlx_sp_func := B"110011";
constant sp_func_movfp2i : dlx_sp_func := B"110100";
constant sp_func_movi2fp : dlx_sp_func := B"110101";
constant sp_func_undef_36 : dlx_sp_func := B"110110";
constant sp_func_undef_37 : dlx_sp_func := B"110111";
constant sp_func_undef_38 : dlx_sp_func := B"111000";
constant sp_func_undef_39 : dlx_sp_func := B"111001";
constant sp_func_undef_3A : dlx_sp_func := B"111010";
constant sp_func_undef_3B : dlx_sp_func := B"111011";
constant sp_func_undef_3C : dlx_sp_func := B"111100";
constant sp_func_undef_3D : dlx_sp_func := B"111101";
constant sp_func_undef_3E : dlx_sp_func := B"111110";
constant sp_func_undef_3F : dlx_sp_func := B"111111";
constant fp_func_addf : dlx_fp_func := B"00000";
constant fp_func_subf : dlx_fp_func := B"00001";
constant fp_func_multf : dlx_fp_func := B"00010";
constant fp_func_divf : dlx_fp_func := B"00011";
constant fp_func_addd : dlx_fp_func := B"00100";
constant fp_func_subd : dlx_fp_func := B"00101";
constant fp_func_multd : dlx_fp_func := B"00110";
constant fp_func_divd : dlx_fp_func := B"00111";
constant fp_func_cvtf2d : dlx_fp_func := B"01000";
constant fp_func_cvtf2i : dlx_fp_func := B"01001";
constant fp_func_cvtd2f : dlx_fp_func := B"01010";
constant fp_func_cvtd2i : dlx_fp_func := B"01011";
constant fp_func_cvti2f : dlx_fp_func := B"01100";
constant fp_func_cvti2d : dlx_fp_func := B"01101";
constant fp_func_mult : dlx_fp_func := B"01110";
constant fp_func_div : dlx_fp_func := B"01111";
constant fp_func_eqf : dlx_fp_func := B"10000";
constant fp_func_nef : dlx_fp_func := B"10001";
constant fp_func_ltf : dlx_fp_func := B"10010";
constant fp_func_gtf : dlx_fp_func := B"10011";
constant fp_func_lef : dlx_fp_func := B"10100";
constant fp_func_gef : dlx_fp_func := B"10101";
constant fp_func_multu : dlx_fp_func := B"10110";
constant fp_func_divu : dlx_fp_func := B"10111";
constant fp_func_eqd : dlx_fp_func := B"11000";
constant fp_func_ned : dlx_fp_func := B"11001";
constant fp_func_ltd : dlx_fp_func := B"11010";
constant fp_func_gtd : dlx_fp_func := B"11011";
constant fp_func_led : dlx_fp_func := B"11100";
constant fp_func_ged : dlx_fp_func := B"11101";
constant fp_func_undef_1E : dlx_fp_func := B"11110";
constant fp_func_undef_1F : dlx_fp_func := B"11111";
subtype dlx_opcode_num is natural range 0 to 63;
subtype dlx_sp_func_num is natural range 0 to 63;
subtype dlx_fp_func_num is natural range 0 to 31;
subtype instr_name is string(1 to 8);
type opcode_name_array is array (dlx_opcode_num) of instr_name;
type sp_func_name_array is array (dlx_sp_func_num) of instr_name;
type fp_func_name_array is array (dlx_fp_func_num) of instr_name;
constant opcode_names : opcode_name_array;
constant sp_func_names : sp_func_name_array;
constant fp_func_names : fp_func_name_array;
subtype reg_index is natural range 0 to 31;
constant link_reg : reg_index := 31;
procedure disassemble ( instr : dlx_bv_word;
disassembled_instr : out string; len : out positive );
end package dlx_instr;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc615.vhd | 4 | 2927 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc615.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:44 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:04 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:22 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00615ent IS
END c03s04b01x00p01n01i00615ent;
ARCHITECTURE c03s04b01x00p01n01i00615arch OF c03s04b01x00p01n01i00615ent IS
constant C4 : integer := 3;
type integer_vector is array (natural range <>) of integer;
subtype integer_vector_st is integer_vector(0 to 15);
type integer_vector_st_file is file of integer_vector_st;
constant C27 : integer_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : integer_vector_st_file open read_mode is "iofile.30";
variable v : integer_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00615"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00615 - File reading operation (integer_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00615arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2053.vhd | 4 | 1866 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2053.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02053ent IS
END c07s02b04x00p01n01i02053ent;
ARCHITECTURE c07s02b04x00p01n01i02053arch OF c07s02b04x00p01n01i02053ent IS
BEGIN
TESTING: PROCESS
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
variable RECV : DATE;
BEGIN
RECV := RECV + (DAY=>14, MONTH=>2, YEAR=>1988);
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02053 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02053arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket11/tb3.vhdl | 3 | 561 | entity tb3 is
end entity;
architecture arch of tb3 is
signal s: integer := 0;
begin
process is
begin
wait for 1 us;
s <= 1;
s <= reject 1 ns inertial 2 after 2 us;
assert s = 0;
wait on s;
report "s = " & integer'image(s);
assert s = 1 severity failure;
assert now = 1 us severity failure;
wait on s;
report "s = " & integer'image(s);
assert s = 2 severity failure;
assert now = 3 us severity failure;
wait;
end process;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd | 4 | 1555 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity DRAM_4M_by_4 is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM_4M_by_4;
architecture chip_function of DRAM_4M_by_4 is
begin
d <= (others => 'Z');
end architecture chip_function;
-- code from book
library chip_lib; use chip_lib.all;
configuration down_to_chips of memory_board is
for chip_level
for bank_array
for nibble_array
for a_DRAM : DRAM
use entity DRAM_4M_by_4(chip_function);
end for;
end for;
end for;
-- . . . -- configurations of other component instances
end for;
end configuration down_to_chips;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue44/costasloop.vhdl | 2 | 2198 | -- costasloop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity costasloop is
port(carrier: in signed(11 downto 0);
clk, reset: in std_logic;
op: out std_logic);
end costasloop;
architecture costasloop_arch of costasloop is
component nco is
port(clk, reset: in std_logic;
fword: in unsigned(5 downto 0);
op_sin: out signed(4 downto 0);
op_cos: out signed(4 downto 0));
end component;
component q_one_dot_fp_multiplier is
generic (a_word_size, b_word_size:integer);
port(a: in signed(a_word_size-1 downto 0);
b: in signed(b_word_size-1 downto 0);
mult_out: out signed(a_word_size + b_word_size -2 downto 0));
end component;
component lpf is
port(clk, reset: in std_logic;
x_in: in signed(15 downto 0);
y_out: out signed(19 downto 0));
end component;
component loopfilter is
port(clk, reset: in std_logic;
mult_error_op:in signed(38 downto 0);
f_desired: in unsigned(5 downto 0);
f_word_output: out unsigned(5 downto 0));
end component;
signal nco_input: unsigned(5 downto 0);
signal nco_sin, nco_cos: signed(4 downto 0);
signal mult_sin, mult_cos: signed(15 downto 0);
signal raw_op_sin, raw_op_cos: signed(19 downto 0);
signal mult_error_op: signed(38 downto 0);
begin
--NCO phase multiplier
N: nco port map(clk, reset, nco_input, nco_sin, nco_cos);
--Multiplier
M0: q_one_dot_fp_multiplier generic map(a_word_size=>nco_sin'length, b_word_size => carrier'length) port map(nco_sin, carrier, mult_sin);
M1: q_one_dot_fp_multiplier generic map(a_word_size=>nco_sin'length, b_word_size => carrier'length) port map(nco_cos, carrier, mult_cos);
--FIR Filter
L0: lpf port map(clk, reset, mult_sin, raw_op_sin);
L1: lpf port map(clk, reset, mult_cos, raw_op_cos);
--Extract output (Comparator)
COMPARATOR: op <= raw_op_sin(raw_op_sin'length -1); --Sign bit
--Error Multiplier
EM: q_one_dot_fp_multiplier generic map(a_word_size=>raw_op_sin'length, b_word_size => raw_op_cos'length) port map(raw_op_sin, raw_op_cos, mult_error_op);
--Loop Filter
--NCO mapping to error
LF: loopfilter port map(clk, reset, mult_error_op, to_unsigned(16, 6), nco_input);
end costasloop_arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1584.vhd | 4 | 1611 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1584.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p02n01i01584ent IS
END c08s11b00x00p02n01i01584ent;
ARCHITECTURE c08s11b00x00p02n01i01584arch OF c08s11b00x00p02n01i01584ent IS
BEGIN
TESTING: PROCESS
BEGIN
while i < 10 loop
exit
end loop;
assert FALSE
report "***FAILED TEST: c08s11b00x00p02n01i01584 - Missing semicolon in the loop statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p02n01i01584arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_04.vhd | 4 | 2356 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_ch_16_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_16_04 is
end entity ch_16_04;
----------------------------------------------------------------
architecture test of ch_16_04 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
-- code from book:
signal memory_data_bus : resolved_word bus;
disconnect memory_data_bus : resolved_word after 3 ns;
-- end of code from book
signal mem_sel, mem_write : boolean;
signal cache_data_bus : word;
begin
-- code from book:
mem_write_buffer : block (mem_sel and mem_write) is
begin
memory_data_bus <=
guarded reject 2 ns inertial cache_data_bus after 4 ns;
end block mem_write_buffer;
-- end of code from book
stimulus : process is
begin
cache_data_bus <= X"DDDDDDDD";
wait for 10 ns;
mem_sel <= true; mem_write <= true;
wait for 10 ns;
cache_data_bus <= X"AAAAAAAA";
wait for 10 ns;
mem_sel <= false; mem_write <= false;
wait for 10 ns;
cache_data_bus <= X"11111111";
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1616.vhd | 4 | 1709 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1616.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01616ent IS
END c08s12b00x00p03n01i01616ent;
ARCHITECTURE c08s12b00x00p03n01i01616arch OF c08s12b00x00p03n01i01616ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable j : boolean := true;
BEGIN
if j then return k;
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01616 - A return statement must be inside a subprogram body"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01616arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2444.vhd | 4 | 1778 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2444.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02444ent IS
type idx is range 0 to 15;
type aray is array (idx) of positive;
END c07s03b02x02p01n01i02444ent;
ARCHITECTURE c07s03b02x02p01n01i02444arch OF c07s03b02x02p01n01i02444ent IS
signal sig : aray;
BEGIN
TESTING: PROCESS
BEGIN
sig <= (others => 0);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02444 - An aggregate of a one-dimensional array type the expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02444arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc93.vhd | 4 | 1800 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc93.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p08n01i00093ent IS
END c04s03b02x00p08n01i00093ent;
ARCHITECTURE c04s03b02x00p08n01i00093arch OF c04s03b02x00p08n01i00093ent IS
procedure proc1 (x1 : integer; y1 :real; z1 : boolean) is
variable x12 : integer;
variable z12 : boolean;
begin
x12 := 12;
z12 := (x1 < 2);
z1 := z12;
y1 := y1 - 1.0;
x1 := x12;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x00p08n01i00093 - Object of mode in may not be updated."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p08n01i00093arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/top.vhd | 2 | 171765 | library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
cp_ok : out std_logic;
cp_en : in std_logic;
cp_rest : in std_logic;
cp_din : in std_logic_vector(63 downto 0);
cp_dout : out std_logic_vector(63 downto 0);
stdout_data : out std_logic_vector(7 downto 0);
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_data : in std_logic_vector(31 downto 0);
stdin_rdy : out std_logic;
stdin_ack : in std_logic
);
end top;
architecture augh of top is
-- Declaration of components
component output_split2 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component output_split3 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component sub_159 is
port (
gt : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end component;
component add_165 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component output_split1 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component output_split0 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component add_172 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_176 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_181 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_187 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_189 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(13 downto 0)
);
end component;
component add_191 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(30 downto 0)
);
end component;
component mul_192 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(10 downto 0)
);
end component;
component mul_193 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_198 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_199 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(13 downto 0)
);
end component;
component sub_209 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_212 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_213 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_214 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_215 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_216 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_217 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_218 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_219 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_220 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_223 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_227 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_157 is
port (
ge : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end component;
component add_163 is
port (
result : out std_logic_vector(15 downto 0);
in_a : in std_logic_vector(15 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component cmp_164 is
port (
ne : out std_logic;
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0)
);
end component;
component add_170 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_174 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_180 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component sub_186 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_190 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_196 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(10 downto 0)
);
end component;
component sub_200 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_206 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_210 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_171 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_177 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_179 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component mul_195 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_197 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_207 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_230 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_185 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_211 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_226 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_235 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_314 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component sub_160 is
port (
le : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end component;
component add_173 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_182 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_188 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_243 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_262 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component output_split4 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component output_split5 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component output_split6 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component output_split7 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component input_split0 is
port (
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(4 downto 0);
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(4 downto 0);
ra3_data : out std_logic_vector(31 downto 0);
ra3_addr : in std_logic_vector(4 downto 0);
clk : in std_logic;
wa2_data : in std_logic_vector(31 downto 0);
wa2_addr : in std_logic_vector(4 downto 0);
wa2_en : in std_logic
);
end component;
component add_194 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(29 downto 0)
);
end component;
component add_205 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_254 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_276 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component sub_284 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component input_split1 is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
wa0_en : in std_logic;
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(4 downto 0);
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(4 downto 0);
ra3_data : out std_logic_vector(31 downto 0);
ra3_addr : in std_logic_vector(4 downto 0);
clk : in std_logic
);
end component;
component add_166 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_168 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_178 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_183 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_332 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_341 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_357 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_365 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_368 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_369 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_370 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_377 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component cmp_398 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_400 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_404 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_406 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_408 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_410 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_412 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end component;
component sub_429 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_466 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_496 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_521 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_528 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component fsm_23 is
port (
clock : in std_logic;
reset : in std_logic;
in0 : in std_logic;
out181 : out std_logic;
out182 : out std_logic;
out183 : out std_logic;
out184 : out std_logic;
out185 : out std_logic;
out8 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out16 : out std_logic;
out18 : out std_logic;
out19 : out std_logic;
out20 : out std_logic;
out21 : out std_logic;
out22 : out std_logic;
in2 : in std_logic;
out23 : out std_logic;
out24 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
out27 : out std_logic;
out28 : out std_logic;
out29 : out std_logic;
out30 : out std_logic;
out31 : out std_logic;
out33 : out std_logic;
out35 : out std_logic;
out36 : out std_logic;
out38 : out std_logic;
out40 : out std_logic;
out42 : out std_logic;
in3 : in std_logic;
out44 : out std_logic;
out46 : out std_logic;
out48 : out std_logic;
out49 : out std_logic;
out50 : out std_logic;
out52 : out std_logic;
out54 : out std_logic;
out56 : out std_logic;
out57 : out std_logic;
out58 : out std_logic;
in4 : in std_logic;
out60 : out std_logic;
in5 : in std_logic;
out164 : out std_logic;
out165 : out std_logic;
out167 : out std_logic;
out168 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out174 : out std_logic;
out176 : out std_logic;
out178 : out std_logic;
out0 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
in1 : in std_logic;
out4 : out std_logic;
out90 : out std_logic;
out91 : out std_logic;
out97 : out std_logic;
out99 : out std_logic;
out101 : out std_logic;
in6 : in std_logic;
out103 : out std_logic;
out105 : out std_logic;
out106 : out std_logic;
out107 : out std_logic;
out108 : out std_logic;
out135 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
out138 : out std_logic;
in11 : in std_logic;
out140 : out std_logic;
out141 : out std_logic;
out142 : out std_logic;
out143 : out std_logic;
out145 : out std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out153 : out std_logic;
out154 : out std_logic;
out155 : out std_logic;
out156 : out std_logic;
out157 : out std_logic;
out158 : out std_logic;
out159 : out std_logic;
out160 : out std_logic;
out161 : out std_logic;
out162 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
out116 : out std_logic;
out118 : out std_logic;
out120 : out std_logic;
out121 : out std_logic;
out122 : out std_logic;
out123 : out std_logic;
out124 : out std_logic;
out125 : out std_logic;
out126 : out std_logic;
in7 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
in8 : in std_logic;
out131 : out std_logic;
in9 : in std_logic;
out132 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
in10 : in std_logic;
out186 : out std_logic;
out187 : out std_logic;
out190 : out std_logic;
out195 : out std_logic;
out197 : out std_logic;
out198 : out std_logic;
out199 : out std_logic;
out200 : out std_logic;
out201 : out std_logic;
out203 : out std_logic;
out204 : out std_logic;
out206 : out std_logic;
out207 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
out215 : out std_logic;
out217 : out std_logic;
out220 : out std_logic;
out221 : out std_logic;
out222 : out std_logic;
out223 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out226 : out std_logic;
out227 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out231 : out std_logic;
out232 : out std_logic;
out234 : out std_logic;
out235 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out243 : out std_logic;
out245 : out std_logic;
out248 : out std_logic;
out249 : out std_logic;
out250 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out254 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out257 : out std_logic;
out259 : out std_logic;
out260 : out std_logic;
out262 : out std_logic;
out263 : out std_logic;
out265 : out std_logic;
out266 : out std_logic;
out268 : out std_logic;
out269 : out std_logic;
out271 : out std_logic;
out273 : out std_logic;
out276 : out std_logic;
out277 : out std_logic;
out278 : out std_logic;
out279 : out std_logic;
out280 : out std_logic;
out281 : out std_logic;
out282 : out std_logic;
out283 : out std_logic;
out284 : out std_logic;
out285 : out std_logic;
out286 : out std_logic;
out287 : out std_logic;
out288 : out std_logic;
out289 : out std_logic;
out290 : out std_logic;
out291 : out std_logic;
out292 : out std_logic;
out293 : out std_logic;
out294 : out std_logic;
out295 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out298 : out std_logic;
out311 : out std_logic;
out312 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
out315 : out std_logic;
out316 : out std_logic;
out318 : out std_logic;
out321 : out std_logic;
out322 : out std_logic;
out323 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out327 : out std_logic;
out328 : out std_logic;
out329 : out std_logic;
out333 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out343 : out std_logic;
out344 : out std_logic;
out345 : out std_logic;
out346 : out std_logic;
out349 : out std_logic;
out350 : out std_logic;
out351 : out std_logic;
out352 : out std_logic;
out353 : out std_logic;
out354 : out std_logic;
out355 : out std_logic;
out357 : out std_logic;
out361 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out366 : out std_logic;
out367 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out382 : out std_logic;
out383 : out std_logic;
out385 : out std_logic;
out393 : out std_logic;
out394 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out398 : out std_logic;
out400 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out404 : out std_logic;
out406 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
out411 : out std_logic;
out412 : out std_logic;
out413 : out std_logic;
out414 : out std_logic;
out416 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out422 : out std_logic;
out423 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
out428 : out std_logic;
out429 : out std_logic;
out430 : out std_logic;
out431 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out435 : out std_logic;
out436 : out std_logic;
out437 : out std_logic;
out438 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
out443 : out std_logic;
out444 : out std_logic;
out445 : out std_logic;
out446 : out std_logic;
out447 : out std_logic;
out450 : out std_logic;
out451 : out std_logic;
out454 : out std_logic;
out455 : out std_logic;
out457 : out std_logic;
out458 : out std_logic;
out459 : out std_logic;
out460 : out std_logic;
out461 : out std_logic;
out462 : out std_logic;
out463 : out std_logic;
out464 : out std_logic;
out465 : out std_logic;
out466 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out469 : out std_logic;
out472 : out std_logic;
out475 : out std_logic;
out481 : out std_logic;
out482 : out std_logic;
out483 : out std_logic;
out484 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
out491 : out std_logic;
out495 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out499 : out std_logic;
out500 : out std_logic;
out501 : out std_logic;
out512 : out std_logic;
out513 : out std_logic;
out517 : out std_logic;
out518 : out std_logic;
out519 : out std_logic;
out521 : out std_logic;
out522 : out std_logic;
out524 : out std_logic;
out525 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out531 : out std_logic;
out540 : out std_logic;
out542 : out std_logic;
out544 : out std_logic;
out545 : out std_logic;
out554 : out std_logic;
out555 : out std_logic;
out559 : out std_logic;
out560 : out std_logic;
out561 : out std_logic;
out562 : out std_logic;
out563 : out std_logic;
out566 : out std_logic;
out567 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
out578 : out std_logic;
out580 : out std_logic;
out581 : out std_logic
);
end component;
component add_167 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_169 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_175 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_255 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component sub_362 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_376 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_420 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component sub_446 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_456 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_457 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_461 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_517 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_560 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_565 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_578 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component muxb_162 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end component;
component add_184 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component muxb_201 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end component;
component cmp_202 is
port (
ne : out std_logic;
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0)
);
end component;
component cmp_203 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end component;
component cmp_204 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end component;
component sub_208 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_236 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component muxb_263 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end component;
component muxb_265 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end component;
component add_277 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_295 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_296 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component sub_303 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_315 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component muxb_322 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end component;
component add_323 is
port (
result : out std_logic_vector(15 downto 0);
in_a : in std_logic_vector(15 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component cmp_324 is
port (
ne : out std_logic;
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0)
);
end component;
component cmp_325 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end component;
component mul_328 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_331 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_337 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_338 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_344 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_345 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_350 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_353 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_354 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_373 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component add_382 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_383 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_390 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_391 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component cmp_392 is
port (
ne : out std_logic;
in0 : in std_logic_vector(31 downto 0);
in1 : in std_logic_vector(31 downto 0)
);
end component;
component add_393 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component cmp_396 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_402 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_411 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end component;
component cmp_413 is
port (
ne : out std_logic;
in0 : in std_logic_vector(31 downto 0);
in1 : in std_logic_vector(31 downto 0)
);
end component;
component mul_416 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_419 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_430 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_437 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_442 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_445 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_447 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_448 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_449 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_460 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_469 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_474 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_477 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_478 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_483 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_484 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_487 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_488 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_489 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_492 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_495 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_499 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_502 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_503 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_508 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_511 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_516 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_520 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_524 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_527 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_531 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_534 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_537 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_540 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_543 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_544 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_547 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_552 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_553 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_556 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_559 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_561 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_562 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_563 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_564 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_566 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_567 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_570 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_573 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_574 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_577 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_579 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_580 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_585 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_586 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_589 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_592 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_593 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_594 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_595 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_596 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_599 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_600 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_601 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_602 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component mul_605 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
-- Declaration of signals
signal sig_clock : std_logic;
signal sig_reset : std_logic;
signal augh_test_9 : std_logic;
signal augh_test_11 : std_logic;
signal sig_start : std_logic;
signal test_cp_0_16 : std_logic;
signal test_cp_1_17 : std_logic;
signal memextrct_loop_sig_21 : std_logic;
signal psc_loop_sig_20 : std_logic;
signal memextrct_loop_sig_22 : std_logic;
signal sig_606 : std_logic_vector(30 downto 0);
signal sig_607 : std_logic_vector(19 downto 0);
signal sig_608 : std_logic_vector(26 downto 0);
signal sig_609 : std_logic_vector(31 downto 0);
signal sig_610 : std_logic_vector(31 downto 0);
signal sig_611 : std_logic_vector(31 downto 0);
signal sig_612 : std_logic_vector(31 downto 0);
signal sig_613 : std_logic_vector(31 downto 0);
signal sig_614 : std_logic_vector(31 downto 0);
signal sig_615 : std_logic_vector(31 downto 0);
signal sig_616 : std_logic_vector(31 downto 0);
signal sig_617 : std_logic_vector(31 downto 0);
signal sig_618 : std_logic_vector(31 downto 0);
signal sig_619 : std_logic_vector(31 downto 0);
signal sig_620 : std_logic_vector(31 downto 0);
signal sig_621 : std_logic_vector(30 downto 0);
signal sig_622 : std_logic_vector(31 downto 0);
signal sig_623 : std_logic_vector(30 downto 0);
signal sig_624 : std_logic_vector(31 downto 0);
signal sig_625 : std_logic_vector(31 downto 0);
signal sig_626 : std_logic_vector(31 downto 0);
signal sig_627 : std_logic_vector(31 downto 0);
signal sig_628 : std_logic_vector(31 downto 0);
signal sig_629 : std_logic_vector(31 downto 0);
signal sig_630 : std_logic_vector(31 downto 0);
signal sig_631 : std_logic_vector(30 downto 0);
signal sig_632 : std_logic_vector(30 downto 0);
signal sig_633 : std_logic_vector(31 downto 0);
signal sig_634 : std_logic_vector(31 downto 0);
signal sig_635 : std_logic_vector(30 downto 0);
signal sig_636 : std_logic_vector(31 downto 0);
signal sig_637 : std_logic_vector(31 downto 0);
signal sig_638 : std_logic_vector(31 downto 0);
signal sig_639 : std_logic_vector(31 downto 0);
signal sig_640 : std_logic_vector(30 downto 0);
signal sig_641 : std_logic_vector(30 downto 0);
signal sig_642 : std_logic_vector(31 downto 0);
signal sig_643 : std_logic_vector(31 downto 0);
signal sig_644 : std_logic_vector(30 downto 0);
signal sig_645 : std_logic_vector(31 downto 0);
signal sig_646 : std_logic_vector(30 downto 0);
signal sig_647 : std_logic_vector(31 downto 0);
signal sig_648 : std_logic_vector(31 downto 0);
signal sig_649 : std_logic_vector(31 downto 0);
signal sig_650 : std_logic_vector(31 downto 0);
signal sig_651 : std_logic_vector(31 downto 0);
signal sig_652 : std_logic_vector(31 downto 0);
signal sig_653 : std_logic_vector(31 downto 0);
signal sig_654 : std_logic_vector(31 downto 0);
signal sig_655 : std_logic_vector(31 downto 0);
signal sig_656 : std_logic_vector(31 downto 0);
signal sig_657 : std_logic_vector(31 downto 0);
signal sig_658 : std_logic_vector(31 downto 0);
signal sig_659 : std_logic_vector(30 downto 0);
signal sig_660 : std_logic_vector(31 downto 0);
signal sig_661 : std_logic_vector(30 downto 0);
signal sig_662 : std_logic_vector(31 downto 0);
signal sig_663 : std_logic_vector(31 downto 0);
signal sig_664 : std_logic_vector(31 downto 0);
signal sig_665 : std_logic_vector(31 downto 0);
signal sig_666 : std_logic_vector(31 downto 0);
signal sig_667 : std_logic_vector(31 downto 0);
signal sig_668 : std_logic_vector(31 downto 0);
signal sig_669 : std_logic_vector(31 downto 0);
signal sig_670 : std_logic_vector(26 downto 0);
signal sig_671 : std_logic_vector(30 downto 0);
signal sig_672 : std_logic;
signal sig_673 : std_logic;
signal sig_674 : std_logic;
signal sig_675 : std_logic_vector(31 downto 0);
signal sig_676 : std_logic_vector(31 downto 0);
signal sig_677 : std_logic_vector(31 downto 0);
signal sig_678 : std_logic_vector(30 downto 0);
signal sig_679 : std_logic_vector(31 downto 0);
signal sig_680 : std_logic_vector(31 downto 0);
signal sig_681 : std_logic_vector(31 downto 0);
signal sig_682 : std_logic_vector(30 downto 0);
signal sig_683 : std_logic_vector(31 downto 0);
signal sig_684 : std_logic_vector(31 downto 0);
signal sig_685 : std_logic_vector(31 downto 0);
signal sig_686 : std_logic_vector(31 downto 0);
signal sig_687 : std_logic_vector(31 downto 0);
signal sig_688 : std_logic_vector(31 downto 0);
signal sig_689 : std_logic_vector(31 downto 0);
signal sig_690 : std_logic;
signal sig_691 : std_logic_vector(15 downto 0);
signal sig_692 : std_logic;
signal sig_693 : std_logic_vector(19 downto 0);
signal sig_694 : std_logic_vector(31 downto 0);
signal sig_695 : std_logic_vector(19 downto 0);
signal sig_696 : std_logic_vector(26 downto 0);
signal sig_697 : std_logic_vector(19 downto 0);
signal sig_698 : std_logic;
signal sig_699 : std_logic;
signal sig_700 : std_logic_vector(19 downto 0);
signal sig_701 : std_logic_vector(31 downto 0);
signal sig_702 : std_logic;
signal sig_703 : std_logic;
signal sig_704 : std_logic_vector(31 downto 0);
signal sig_705 : std_logic;
signal sig_706 : std_logic_vector(31 downto 0);
signal sig_707 : std_logic_vector(31 downto 0);
signal sig_708 : std_logic_vector(31 downto 0);
signal sig_709 : std_logic_vector(31 downto 0);
signal sig_710 : std_logic_vector(31 downto 0);
signal sig_711 : std_logic_vector(31 downto 0);
signal sig_712 : std_logic_vector(30 downto 0);
signal sig_713 : std_logic_vector(31 downto 0);
signal sig_714 : std_logic_vector(19 downto 0);
signal sig_715 : std_logic_vector(31 downto 0);
signal sig_716 : std_logic_vector(31 downto 0);
signal sig_717 : std_logic_vector(19 downto 0);
signal sig_718 : std_logic_vector(26 downto 0);
signal sig_719 : std_logic_vector(26 downto 0);
signal sig_720 : std_logic_vector(26 downto 0);
signal sig_721 : std_logic;
signal sig_722 : std_logic;
signal sig_723 : std_logic;
signal sig_724 : std_logic;
signal sig_725 : std_logic;
signal sig_726 : std_logic;
signal sig_727 : std_logic;
signal sig_728 : std_logic;
signal sig_729 : std_logic;
signal sig_730 : std_logic;
signal sig_731 : std_logic;
signal sig_732 : std_logic;
signal sig_733 : std_logic;
signal sig_734 : std_logic;
signal sig_735 : std_logic;
signal sig_736 : std_logic;
signal sig_737 : std_logic;
signal sig_738 : std_logic;
signal sig_739 : std_logic;
signal sig_740 : std_logic;
signal sig_741 : std_logic;
signal sig_742 : std_logic;
signal sig_743 : std_logic;
signal sig_744 : std_logic;
signal sig_745 : std_logic;
signal sig_746 : std_logic;
signal sig_747 : std_logic;
signal sig_748 : std_logic;
signal sig_749 : std_logic;
signal sig_750 : std_logic;
signal sig_751 : std_logic;
signal sig_752 : std_logic;
signal sig_753 : std_logic;
signal sig_754 : std_logic;
signal sig_755 : std_logic;
signal sig_756 : std_logic;
signal sig_757 : std_logic;
signal sig_758 : std_logic;
signal sig_759 : std_logic;
signal sig_760 : std_logic;
signal sig_761 : std_logic;
signal sig_762 : std_logic;
signal sig_763 : std_logic;
signal sig_764 : std_logic;
signal sig_765 : std_logic;
signal sig_766 : std_logic;
signal sig_767 : std_logic;
signal sig_768 : std_logic;
signal sig_769 : std_logic;
signal sig_770 : std_logic;
signal sig_771 : std_logic;
signal sig_772 : std_logic;
signal sig_773 : std_logic;
signal sig_774 : std_logic;
signal sig_775 : std_logic;
signal sig_776 : std_logic;
signal sig_777 : std_logic;
signal sig_778 : std_logic;
signal sig_779 : std_logic;
signal sig_780 : std_logic;
signal sig_781 : std_logic;
signal sig_782 : std_logic;
signal sig_783 : std_logic;
signal sig_784 : std_logic;
signal sig_785 : std_logic;
signal sig_786 : std_logic;
signal sig_787 : std_logic;
signal sig_788 : std_logic;
signal sig_789 : std_logic;
signal sig_790 : std_logic;
signal sig_791 : std_logic;
signal sig_792 : std_logic;
signal sig_793 : std_logic;
signal sig_794 : std_logic;
signal sig_795 : std_logic;
signal sig_796 : std_logic;
signal sig_797 : std_logic;
signal sig_798 : std_logic;
signal sig_799 : std_logic;
signal sig_800 : std_logic;
signal sig_801 : std_logic;
signal sig_802 : std_logic;
signal sig_803 : std_logic;
signal sig_804 : std_logic;
signal sig_805 : std_logic;
signal sig_806 : std_logic;
signal sig_807 : std_logic;
signal sig_808 : std_logic;
signal sig_809 : std_logic;
signal sig_810 : std_logic;
signal sig_811 : std_logic;
signal sig_812 : std_logic;
signal sig_813 : std_logic;
signal sig_814 : std_logic;
signal sig_815 : std_logic;
signal sig_816 : std_logic;
signal sig_817 : std_logic;
signal sig_818 : std_logic;
signal sig_819 : std_logic;
signal sig_820 : std_logic;
signal sig_821 : std_logic;
signal sig_822 : std_logic;
signal sig_823 : std_logic;
signal sig_824 : std_logic;
signal sig_825 : std_logic;
signal sig_826 : std_logic;
signal sig_827 : std_logic;
signal sig_828 : std_logic;
signal sig_829 : std_logic;
signal sig_830 : std_logic;
signal sig_831 : std_logic;
signal sig_832 : std_logic;
signal sig_833 : std_logic;
signal sig_834 : std_logic;
signal sig_835 : std_logic;
signal sig_836 : std_logic;
signal sig_837 : std_logic;
signal sig_838 : std_logic;
signal sig_839 : std_logic;
signal sig_840 : std_logic;
signal sig_841 : std_logic;
signal sig_842 : std_logic;
signal sig_843 : std_logic;
signal sig_844 : std_logic;
signal sig_845 : std_logic;
signal sig_846 : std_logic;
signal sig_847 : std_logic;
signal sig_848 : std_logic;
signal sig_849 : std_logic;
signal sig_850 : std_logic;
signal sig_851 : std_logic;
signal sig_852 : std_logic;
signal sig_853 : std_logic;
signal sig_854 : std_logic;
signal sig_855 : std_logic;
signal sig_856 : std_logic;
signal sig_857 : std_logic;
signal sig_858 : std_logic;
signal sig_859 : std_logic;
signal sig_860 : std_logic;
signal sig_861 : std_logic;
signal sig_862 : std_logic;
signal sig_863 : std_logic;
signal sig_864 : std_logic;
signal sig_865 : std_logic;
signal sig_866 : std_logic;
signal sig_867 : std_logic;
signal sig_868 : std_logic;
signal sig_869 : std_logic;
signal sig_870 : std_logic;
signal sig_871 : std_logic;
signal sig_872 : std_logic;
signal sig_873 : std_logic;
signal sig_874 : std_logic;
signal sig_875 : std_logic;
signal sig_876 : std_logic;
signal sig_877 : std_logic;
signal sig_878 : std_logic;
signal sig_879 : std_logic;
signal sig_880 : std_logic;
signal sig_881 : std_logic;
signal sig_882 : std_logic;
signal sig_883 : std_logic;
signal sig_884 : std_logic;
signal sig_885 : std_logic;
signal sig_886 : std_logic;
signal sig_887 : std_logic;
signal sig_888 : std_logic;
signal sig_889 : std_logic;
signal sig_890 : std_logic;
signal sig_891 : std_logic;
signal sig_892 : std_logic;
signal sig_893 : std_logic;
signal sig_894 : std_logic;
signal sig_895 : std_logic;
signal sig_896 : std_logic;
signal sig_897 : std_logic;
signal sig_898 : std_logic;
signal sig_899 : std_logic;
signal sig_900 : std_logic;
signal sig_901 : std_logic;
signal sig_902 : std_logic;
signal sig_903 : std_logic;
signal sig_904 : std_logic;
signal sig_905 : std_logic;
signal sig_906 : std_logic;
signal sig_907 : std_logic;
signal sig_908 : std_logic;
signal sig_909 : std_logic;
signal sig_910 : std_logic;
signal sig_911 : std_logic;
signal sig_912 : std_logic;
signal sig_913 : std_logic;
signal sig_914 : std_logic;
signal sig_915 : std_logic;
signal sig_916 : std_logic;
signal sig_917 : std_logic;
signal sig_918 : std_logic;
signal sig_919 : std_logic;
signal sig_920 : std_logic;
signal sig_921 : std_logic;
signal sig_922 : std_logic;
signal sig_923 : std_logic;
signal sig_924 : std_logic;
signal sig_925 : std_logic;
signal sig_926 : std_logic;
signal sig_927 : std_logic;
signal sig_928 : std_logic;
signal sig_929 : std_logic;
signal sig_930 : std_logic;
signal sig_931 : std_logic;
signal sig_932 : std_logic;
signal sig_933 : std_logic;
signal sig_934 : std_logic;
signal sig_935 : std_logic;
signal sig_936 : std_logic;
signal sig_937 : std_logic;
signal sig_938 : std_logic;
signal sig_939 : std_logic;
signal sig_940 : std_logic;
signal sig_941 : std_logic;
signal sig_942 : std_logic;
signal sig_943 : std_logic;
signal sig_944 : std_logic;
signal sig_945 : std_logic;
signal sig_946 : std_logic;
signal sig_947 : std_logic;
signal sig_948 : std_logic;
signal sig_949 : std_logic;
signal sig_950 : std_logic;
signal sig_951 : std_logic;
signal sig_952 : std_logic;
signal sig_953 : std_logic;
signal sig_954 : std_logic;
signal sig_955 : std_logic;
signal sig_956 : std_logic;
signal sig_957 : std_logic;
signal sig_958 : std_logic;
signal sig_959 : std_logic;
signal sig_960 : std_logic;
signal sig_961 : std_logic;
signal sig_962 : std_logic;
signal sig_963 : std_logic;
signal sig_964 : std_logic;
signal sig_965 : std_logic;
signal sig_966 : std_logic;
signal sig_967 : std_logic;
signal sig_968 : std_logic;
signal sig_969 : std_logic;
signal sig_970 : std_logic;
signal sig_971 : std_logic;
signal sig_972 : std_logic;
signal sig_973 : std_logic;
signal sig_974 : std_logic;
signal sig_975 : std_logic;
signal sig_976 : std_logic;
signal sig_977 : std_logic;
signal sig_978 : std_logic;
signal sig_979 : std_logic;
signal sig_980 : std_logic;
signal sig_981 : std_logic;
signal sig_982 : std_logic;
signal sig_983 : std_logic;
signal sig_984 : std_logic;
signal sig_985 : std_logic;
signal sig_986 : std_logic;
signal sig_987 : std_logic;
signal sig_988 : std_logic;
signal sig_989 : std_logic;
signal sig_990 : std_logic;
signal sig_991 : std_logic;
signal sig_992 : std_logic;
signal sig_993 : std_logic;
signal sig_994 : std_logic;
signal sig_995 : std_logic;
signal sig_996 : std_logic;
signal sig_997 : std_logic;
signal sig_998 : std_logic;
signal sig_999 : std_logic;
signal sig_1000 : std_logic;
signal sig_1001 : std_logic;
signal sig_1002 : std_logic;
signal sig_1003 : std_logic;
signal sig_1004 : std_logic;
signal sig_1005 : std_logic;
signal sig_1006 : std_logic;
signal sig_1007 : std_logic;
signal sig_1008 : std_logic;
signal sig_1009 : std_logic;
signal sig_1010 : std_logic;
signal sig_1011 : std_logic;
signal sig_1012 : std_logic;
signal sig_1013 : std_logic;
signal sig_1014 : std_logic;
signal sig_1015 : std_logic;
signal sig_1016 : std_logic;
signal sig_1017 : std_logic;
signal sig_1018 : std_logic;
signal sig_1019 : std_logic;
signal sig_1020 : std_logic;
signal sig_1021 : std_logic;
signal sig_1022 : std_logic;
signal sig_1023 : std_logic;
signal sig_1024 : std_logic;
signal sig_1025 : std_logic;
signal sig_1026 : std_logic;
signal sig_1027 : std_logic;
signal sig_1028 : std_logic;
signal sig_1029 : std_logic;
signal sig_1030 : std_logic;
signal sig_1031 : std_logic;
signal sig_1032 : std_logic;
signal sig_1033 : std_logic;
signal sig_1034 : std_logic;
signal sig_1035 : std_logic;
signal sig_1036 : std_logic;
signal sig_1037 : std_logic;
signal sig_1038 : std_logic;
signal sig_1039 : std_logic;
signal sig_1040 : std_logic;
signal sig_1041 : std_logic;
signal sig_1042 : std_logic;
signal sig_1043 : std_logic;
signal sig_1044 : std_logic;
signal sig_1045 : std_logic;
signal sig_1046 : std_logic;
signal sig_1047 : std_logic;
signal sig_1048 : std_logic;
signal sig_1049 : std_logic;
signal sig_1050 : std_logic;
signal sig_1051 : std_logic;
signal sig_1052 : std_logic;
signal sig_1053 : std_logic;
signal sig_1054 : std_logic;
signal sig_1055 : std_logic;
signal sig_1056 : std_logic;
signal sig_1057 : std_logic;
signal sig_1058 : std_logic;
signal sig_1059 : std_logic_vector(31 downto 0);
signal sig_1060 : std_logic_vector(31 downto 0);
signal sig_1061 : std_logic_vector(31 downto 0);
signal sig_1062 : std_logic_vector(31 downto 0);
signal sig_1063 : std_logic_vector(31 downto 0);
signal sig_1064 : std_logic;
signal sig_1065 : std_logic;
signal sig_1066 : std_logic;
signal sig_1067 : std_logic;
signal sig_1068 : std_logic;
signal sig_1069 : std_logic;
signal sig_1070 : std_logic;
signal sig_1071 : std_logic_vector(31 downto 0);
signal sig_1072 : std_logic_vector(31 downto 0);
signal sig_1073 : std_logic_vector(31 downto 0);
signal sig_1074 : std_logic_vector(31 downto 0);
signal sig_1075 : std_logic_vector(31 downto 0);
signal sig_1076 : std_logic_vector(30 downto 0);
signal sig_1077 : std_logic_vector(31 downto 0);
signal sig_1078 : std_logic_vector(31 downto 0);
signal sig_1079 : std_logic_vector(31 downto 0);
signal sig_1080 : std_logic_vector(19 downto 0);
signal sig_1081 : std_logic_vector(19 downto 0);
signal sig_1082 : std_logic_vector(19 downto 0);
signal sig_1083 : std_logic_vector(31 downto 0);
signal sig_1084 : std_logic_vector(31 downto 0);
signal sig_1085 : std_logic_vector(31 downto 0);
signal sig_1086 : std_logic_vector(31 downto 0);
signal sig_1087 : std_logic_vector(31 downto 0);
signal sig_1088 : std_logic_vector(26 downto 0);
signal sig_1089 : std_logic_vector(26 downto 0);
signal sig_1090 : std_logic_vector(31 downto 0);
signal sig_1091 : std_logic_vector(29 downto 0);
signal sig_1092 : std_logic_vector(31 downto 0);
signal sig_1093 : std_logic_vector(31 downto 0);
signal sig_1094 : std_logic_vector(31 downto 0);
signal sig_1095 : std_logic_vector(31 downto 0);
signal sig_1096 : std_logic_vector(7 downto 0);
signal sig_1097 : std_logic_vector(7 downto 0);
signal sig_1098 : std_logic_vector(7 downto 0);
signal sig_1099 : std_logic_vector(7 downto 0);
signal sig_1100 : std_logic_vector(31 downto 0);
signal sig_1101 : std_logic_vector(31 downto 0);
signal sig_1102 : std_logic_vector(31 downto 0);
signal sig_1103 : std_logic_vector(31 downto 0);
signal sig_1104 : std_logic_vector(26 downto 0);
signal sig_1105 : std_logic_vector(31 downto 0);
signal sig_1106 : std_logic;
signal sig_1107 : std_logic_vector(26 downto 0);
signal sig_1108 : std_logic_vector(26 downto 0);
signal sig_1109 : std_logic_vector(31 downto 0);
signal sig_1110 : std_logic_vector(31 downto 0);
signal sig_1111 : std_logic_vector(31 downto 0);
signal sig_1112 : std_logic_vector(30 downto 0);
signal sig_1113 : std_logic_vector(31 downto 0);
signal sig_1114 : std_logic_vector(31 downto 0);
signal sig_1115 : std_logic_vector(31 downto 0);
signal sig_1116 : std_logic_vector(26 downto 0);
signal sig_1117 : std_logic_vector(26 downto 0);
signal sig_1118 : std_logic_vector(26 downto 0);
signal sig_1119 : std_logic_vector(31 downto 0);
signal sig_1120 : std_logic_vector(31 downto 0);
signal sig_1121 : std_logic_vector(31 downto 0);
signal sig_1122 : std_logic_vector(29 downto 0);
signal sig_1123 : std_logic_vector(31 downto 0);
signal sig_1124 : std_logic_vector(31 downto 0);
signal sig_1125 : std_logic_vector(19 downto 0);
signal sig_1126 : std_logic_vector(19 downto 0);
signal sig_1127 : std_logic_vector(19 downto 0);
signal sig_1128 : std_logic_vector(15 downto 0);
signal sig_1129 : std_logic_vector(31 downto 0);
signal sig_1130 : std_logic;
signal sig_1131 : std_logic_vector(31 downto 0);
signal sig_1132 : std_logic_vector(30 downto 0);
signal sig_1133 : std_logic_vector(31 downto 0);
signal sig_1134 : std_logic_vector(31 downto 0);
signal sig_1135 : std_logic_vector(31 downto 0);
signal sig_1136 : std_logic_vector(31 downto 0);
signal sig_1137 : std_logic_vector(31 downto 0);
signal sig_1138 : std_logic_vector(31 downto 0);
signal sig_1139 : std_logic_vector(31 downto 0);
signal sig_1140 : std_logic_vector(31 downto 0);
signal sig_1141 : std_logic_vector(31 downto 0);
signal sig_1142 : std_logic_vector(31 downto 0);
signal sig_1143 : std_logic_vector(30 downto 0);
signal sig_1144 : std_logic_vector(31 downto 0);
signal sig_1145 : std_logic_vector(31 downto 0);
signal sig_1146 : std_logic_vector(29 downto 0);
signal sig_1147 : std_logic_vector(30 downto 0);
signal sig_1148 : std_logic_vector(30 downto 0);
signal sig_1149 : std_logic_vector(31 downto 0);
signal sig_1150 : std_logic_vector(31 downto 0);
signal sig_1151 : std_logic_vector(19 downto 0);
signal sig_1152 : std_logic_vector(19 downto 0);
signal sig_1153 : std_logic_vector(7 downto 0);
signal sig_1154 : std_logic_vector(7 downto 0);
signal sig_1155 : std_logic_vector(26 downto 0);
signal sig_1156 : std_logic_vector(31 downto 0);
signal sig_1157 : std_logic;
signal sig_1158 : std_logic_vector(7 downto 0);
signal sig_1159 : std_logic_vector(7 downto 0);
signal sig_1160 : std_logic_vector(19 downto 0);
signal sig_1161 : std_logic_vector(31 downto 0);
signal sig_1162 : std_logic_vector(31 downto 0);
signal sig_1163 : std_logic_vector(19 downto 0);
signal sig_1164 : std_logic_vector(31 downto 0);
signal sig_1165 : std_logic_vector(19 downto 0);
signal sig_1166 : std_logic_vector(19 downto 0);
signal sig_1167 : std_logic_vector(19 downto 0);
signal sig_1168 : std_logic_vector(19 downto 0);
signal sig_1169 : std_logic_vector(19 downto 0);
signal sig_1170 : std_logic_vector(31 downto 0);
signal sig_1171 : std_logic_vector(19 downto 0);
signal sig_1172 : std_logic_vector(19 downto 0);
signal sig_1173 : std_logic_vector(19 downto 0);
signal sig_1174 : std_logic_vector(31 downto 0);
signal sig_1175 : std_logic_vector(31 downto 0);
signal sig_1176 : std_logic_vector(31 downto 0);
signal sig_1177 : std_logic_vector(31 downto 0);
signal sig_1178 : std_logic_vector(31 downto 0);
signal sig_1179 : std_logic_vector(19 downto 0);
signal sig_1180 : std_logic_vector(19 downto 0);
signal sig_1181 : std_logic_vector(19 downto 0);
signal sig_1182 : std_logic_vector(19 downto 0);
signal sig_1183 : std_logic_vector(19 downto 0);
-- Other inlined components
signal mux_66 : std_logic_vector(2 downto 0);
signal mux_30 : std_logic;
signal mux_32 : std_logic;
signal mux_33 : std_logic;
signal mux_34 : std_logic;
signal augh_main_k : std_logic_vector(31 downto 0) := (others => '0');
signal read32_ret0_10 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_58 : std_logic_vector(2 downto 0);
signal mux_59 : std_logic_vector(2 downto 0);
signal mux_60 : std_logic;
signal mux_61 : std_logic_vector(7 downto 0);
signal mux_62 : std_logic_vector(2 downto 0);
signal mux_63 : std_logic_vector(2 downto 0);
signal mux_64 : std_logic;
signal mux_65 : std_logic_vector(7 downto 0);
signal mux_35 : std_logic;
signal mux_36 : std_logic;
signal mux_37 : std_logic_vector(15 downto 0);
signal mux_38 : std_logic;
signal mux_39 : std_logic_vector(31 downto 0);
signal idct_2d_r : std_logic_vector(31 downto 0) := (others => '0');
signal mux_45 : std_logic_vector(4 downto 0);
signal mux_46 : std_logic_vector(4 downto 0);
signal mux_47 : std_logic_vector(4 downto 0);
signal mux_48 : std_logic_vector(4 downto 0);
signal mux_49 : std_logic_vector(4 downto 0);
signal mux_40 : std_logic_vector(4 downto 0);
signal mux_41 : std_logic_vector(4 downto 0);
signal mux_42 : std_logic;
signal mux_43 : std_logic_vector(4 downto 0);
signal mux_44 : std_logic_vector(4 downto 0);
signal write8_u8 : std_logic_vector(7 downto 0) := (others => '0');
signal mux_50 : std_logic_vector(31 downto 0);
signal mux_51 : std_logic_vector(4 downto 0);
signal mux_52 : std_logic;
signal mux_53 : std_logic_vector(7 downto 0);
signal mux_54 : std_logic_vector(2 downto 0);
signal mux_55 : std_logic_vector(2 downto 0);
signal mux_56 : std_logic;
signal mux_57 : std_logic_vector(7 downto 0);
signal idct_z3_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z3_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z3_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z3_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_88 : std_logic;
signal mux_67 : std_logic_vector(2 downto 0);
signal mux_68 : std_logic;
signal mux_69 : std_logic_vector(31 downto 0);
signal mux_71 : std_logic_vector(31 downto 0);
signal mux_73 : std_logic_vector(31 downto 0);
signal mux_75 : std_logic_vector(31 downto 0);
signal mux_77 : std_logic_vector(31 downto 0);
signal mux_79 : std_logic_vector(31 downto 0);
signal mux_81 : std_logic_vector(31 downto 0);
signal mux_83 : std_logic_vector(31 downto 0);
signal mux_85 : std_logic_vector(7 downto 0);
signal mux_86 : std_logic_vector(2 downto 0);
signal mux_87 : std_logic_vector(2 downto 0);
signal mux_28 : std_logic;
signal idct_z1_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_109 : std_logic_vector(31 downto 0);
signal mux_154 : std_logic;
signal mux_156 : std_logic_vector(7 downto 0);
signal idct_2d_yc_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_89 : std_logic_vector(7 downto 0);
signal mux_90 : std_logic_vector(2 downto 0);
signal mux_134 : std_logic;
signal mux_91 : std_logic_vector(2 downto 0);
signal mux_92 : std_logic;
signal mux_158 : std_logic_vector(7 downto 0);
signal mux_111 : std_logic_vector(31 downto 0);
signal mux_113 : std_logic_vector(31 downto 0);
signal mux_115 : std_logic_vector(31 downto 0);
signal mux_117 : std_logic_vector(31 downto 0);
signal mux_119 : std_logic_vector(31 downto 0);
signal mux_121 : std_logic_vector(31 downto 0);
signal mux_123 : std_logic_vector(31 downto 0);
signal or_224 : std_logic_vector(31 downto 0);
signal and_225 : std_logic_vector(31 downto 0);
signal or_231 : std_logic_vector(31 downto 0);
signal and_232 : std_logic_vector(31 downto 0);
signal or_250 : std_logic_vector(31 downto 0);
signal and_251 : std_logic_vector(31 downto 0);
signal or_260 : std_logic_vector(31 downto 0);
signal and_261 : std_logic_vector(31 downto 0);
signal or_282 : std_logic_vector(31 downto 0);
signal and_283 : std_logic_vector(31 downto 0);
signal or_285 : std_logic_vector(31 downto 0);
signal and_286 : std_logic_vector(31 downto 0);
signal or_289 : std_logic_vector(31 downto 0);
signal and_290 : std_logic_vector(31 downto 0);
signal or_291 : std_logic_vector(31 downto 0);
signal and_292 : std_logic_vector(31 downto 0);
signal or_297 : std_logic_vector(31 downto 0);
signal and_298 : std_logic_vector(31 downto 0);
signal or_299 : std_logic_vector(31 downto 0);
signal and_300 : std_logic_vector(31 downto 0);
signal or_320 : std_logic_vector(31 downto 0);
signal and_321 : std_logic_vector(31 downto 0);
signal or_326 : std_logic_vector(31 downto 0);
signal and_327 : std_logic_vector(31 downto 0);
signal or_333 : std_logic_vector(31 downto 0);
signal and_334 : std_logic_vector(31 downto 0);
signal or_363 : std_logic_vector(31 downto 0);
signal and_364 : std_logic_vector(31 downto 0);
signal and_403 : std_logic_vector(7 downto 0);
signal and_405 : std_logic_vector(7 downto 0);
signal and_407 : std_logic_vector(7 downto 0);
signal and_409 : std_logic_vector(7 downto 0);
signal and_415 : std_logic_vector(30 downto 0);
signal or_464 : std_logic_vector(31 downto 0);
signal and_465 : std_logic_vector(31 downto 0);
signal or_470 : std_logic_vector(31 downto 0);
signal and_471 : std_logic_vector(31 downto 0);
signal or_472 : std_logic_vector(31 downto 0);
signal and_473 : std_logic_vector(31 downto 0);
signal or_500 : std_logic_vector(31 downto 0);
signal and_501 : std_logic_vector(31 downto 0);
signal or_504 : std_logic_vector(31 downto 0);
signal and_505 : std_logic_vector(31 downto 0);
signal or_506 : std_logic_vector(31 downto 0);
signal and_507 : std_logic_vector(31 downto 0);
signal or_514 : std_logic_vector(31 downto 0);
signal and_515 : std_logic_vector(31 downto 0);
signal or_522 : std_logic_vector(31 downto 0);
signal and_523 : std_logic_vector(31 downto 0);
signal psc_loop_reg_13 : std_logic_vector(15 downto 0) := (others => '0');
signal cp_id_reg_14 : std_logic := '0';
signal cp_id_reg_stable_15 : std_logic := '0';
signal psc_stuff_reg_18 : std_logic_vector(23 downto 0) := (others => '0');
signal psc_stuff_reg_19 : std_logic_vector(62 downto 0) := "000000000000000000000000000000000000000000000000000000000000000";
signal mux_129 : std_logic_vector(31 downto 0);
signal mux_133 : std_logic_vector(7 downto 0);
signal mux_135 : std_logic_vector(31 downto 0);
signal mux_137 : std_logic_vector(7 downto 0);
signal mux_138 : std_logic_vector(2 downto 0);
signal mux_139 : std_logic_vector(2 downto 0);
signal mux_140 : std_logic;
signal mux_141 : std_logic_vector(7 downto 0);
signal mux_142 : std_logic_vector(2 downto 0);
signal mux_143 : std_logic_vector(2 downto 0);
signal mux_144 : std_logic;
signal mux_147 : std_logic;
signal mux_149 : std_logic_vector(31 downto 0);
signal mux_150 : std_logic;
signal mux_151 : std_logic;
signal mux_152 : std_logic_vector(63 downto 0);
signal mux_155 : std_logic;
signal or_221 : std_logic_vector(31 downto 0);
signal and_222 : std_logic_vector(31 downto 0);
signal or_233 : std_logic_vector(31 downto 0);
signal and_234 : std_logic_vector(31 downto 0);
signal or_237 : std_logic_vector(31 downto 0);
signal and_238 : std_logic_vector(31 downto 0);
signal or_252 : std_logic_vector(31 downto 0);
signal and_253 : std_logic_vector(31 downto 0);
signal or_256 : std_logic_vector(31 downto 0);
signal and_257 : std_logic_vector(31 downto 0);
signal or_268 : std_logic_vector(31 downto 0);
signal and_269 : std_logic_vector(31 downto 0);
signal or_270 : std_logic_vector(31 downto 0);
signal and_271 : std_logic_vector(31 downto 0);
signal or_274 : std_logic_vector(31 downto 0);
signal and_275 : std_logic_vector(31 downto 0);
signal or_278 : std_logic_vector(31 downto 0);
signal and_279 : std_logic_vector(31 downto 0);
signal or_310 : std_logic_vector(31 downto 0);
signal and_311 : std_logic_vector(31 downto 0);
signal or_316 : std_logic_vector(31 downto 0);
signal and_317 : std_logic_vector(31 downto 0);
signal or_358 : std_logic_vector(31 downto 0);
signal and_359 : std_logic_vector(31 downto 0);
signal or_366 : std_logic_vector(31 downto 0);
signal and_367 : std_logic_vector(31 downto 0);
signal or_374 : std_logic_vector(31 downto 0);
signal and_375 : std_logic_vector(31 downto 0);
signal or_417 : std_logic_vector(31 downto 0);
signal and_418 : std_logic_vector(31 downto 0);
signal or_421 : std_logic_vector(31 downto 0);
signal and_422 : std_logic_vector(31 downto 0);
signal or_435 : std_logic_vector(31 downto 0);
signal and_436 : std_logic_vector(31 downto 0);
signal or_452 : std_logic_vector(31 downto 0);
signal and_453 : std_logic_vector(31 downto 0);
signal and_494 : std_logic_vector(31 downto 0);
signal and_498 : std_logic_vector(31 downto 0);
signal or_509 : std_logic_vector(30 downto 0);
signal and_510 : std_logic_vector(30 downto 0);
signal or_550 : std_logic_vector(31 downto 0);
signal and_551 : std_logic_vector(31 downto 0);
signal or_581 : std_logic_vector(31 downto 0);
signal and_582 : std_logic_vector(31 downto 0);
signal or_583 : std_logic_vector(31 downto 0);
signal and_584 : std_logic_vector(31 downto 0);
signal or_587 : std_logic_vector(31 downto 0);
signal and_588 : std_logic_vector(31 downto 0);
signal and_161 : std_logic;
signal or_228 : std_logic_vector(31 downto 0);
signal and_229 : std_logic_vector(31 downto 0);
signal or_239 : std_logic_vector(31 downto 0);
signal and_240 : std_logic_vector(31 downto 0);
signal or_241 : std_logic_vector(31 downto 0);
signal and_242 : std_logic_vector(31 downto 0);
signal or_244 : std_logic_vector(31 downto 0);
signal and_245 : std_logic_vector(31 downto 0);
signal or_246 : std_logic_vector(31 downto 0);
signal and_247 : std_logic_vector(31 downto 0);
signal or_248 : std_logic_vector(31 downto 0);
signal and_249 : std_logic_vector(31 downto 0);
signal or_258 : std_logic_vector(31 downto 0);
signal and_259 : std_logic_vector(31 downto 0);
signal not_264 : std_logic;
signal or_266 : std_logic_vector(31 downto 0);
signal and_267 : std_logic_vector(31 downto 0);
signal or_272 : std_logic_vector(31 downto 0);
signal and_273 : std_logic_vector(31 downto 0);
signal or_280 : std_logic_vector(31 downto 0);
signal and_281 : std_logic_vector(31 downto 0);
signal or_287 : std_logic_vector(31 downto 0);
signal and_288 : std_logic_vector(31 downto 0);
signal or_293 : std_logic_vector(31 downto 0);
signal and_294 : std_logic_vector(31 downto 0);
signal or_301 : std_logic_vector(31 downto 0);
signal and_302 : std_logic_vector(31 downto 0);
signal or_304 : std_logic_vector(31 downto 0);
signal and_305 : std_logic_vector(31 downto 0);
signal or_306 : std_logic_vector(31 downto 0);
signal and_307 : std_logic_vector(31 downto 0);
signal or_308 : std_logic_vector(31 downto 0);
signal and_309 : std_logic_vector(31 downto 0);
signal or_312 : std_logic_vector(31 downto 0);
signal and_313 : std_logic_vector(31 downto 0);
signal or_318 : std_logic_vector(31 downto 0);
signal and_319 : std_logic_vector(31 downto 0);
signal or_329 : std_logic_vector(31 downto 0);
signal and_330 : std_logic_vector(31 downto 0);
signal or_335 : std_logic_vector(31 downto 0);
signal and_336 : std_logic_vector(31 downto 0);
signal or_339 : std_logic_vector(31 downto 0);
signal and_340 : std_logic_vector(31 downto 0);
signal or_342 : std_logic_vector(31 downto 0);
signal and_343 : std_logic_vector(31 downto 0);
signal or_346 : std_logic_vector(31 downto 0);
signal and_347 : std_logic_vector(31 downto 0);
signal or_348 : std_logic_vector(31 downto 0);
signal and_349 : std_logic_vector(31 downto 0);
signal or_351 : std_logic_vector(30 downto 0);
signal and_352 : std_logic_vector(30 downto 0);
signal or_355 : std_logic_vector(30 downto 0);
signal and_356 : std_logic_vector(30 downto 0);
signal or_360 : std_logic_vector(31 downto 0);
signal and_361 : std_logic_vector(31 downto 0);
signal or_371 : std_logic_vector(31 downto 0);
signal and_372 : std_logic_vector(31 downto 0);
signal or_378 : std_logic_vector(31 downto 0);
signal and_379 : std_logic_vector(31 downto 0);
signal or_380 : std_logic_vector(31 downto 0);
signal and_381 : std_logic_vector(31 downto 0);
signal or_384 : std_logic_vector(31 downto 0);
signal and_385 : std_logic_vector(31 downto 0);
signal or_386 : std_logic_vector(31 downto 0);
signal and_387 : std_logic_vector(31 downto 0);
signal or_388 : std_logic_vector(31 downto 0);
signal and_389 : std_logic_vector(31 downto 0);
signal or_394 : std_logic_vector(7 downto 0);
signal and_395 : std_logic_vector(7 downto 0);
signal and_397 : std_logic_vector(7 downto 0);
signal and_399 : std_logic_vector(7 downto 0);
signal and_401 : std_logic_vector(7 downto 0);
signal or_414 : std_logic_vector(30 downto 0);
signal or_423 : std_logic_vector(31 downto 0);
signal and_424 : std_logic_vector(31 downto 0);
signal or_425 : std_logic_vector(31 downto 0);
signal and_426 : std_logic_vector(31 downto 0);
signal or_427 : std_logic_vector(31 downto 0);
signal and_428 : std_logic_vector(31 downto 0);
signal or_431 : std_logic_vector(31 downto 0);
signal and_432 : std_logic_vector(31 downto 0);
signal or_433 : std_logic_vector(31 downto 0);
signal and_434 : std_logic_vector(31 downto 0);
signal or_438 : std_logic_vector(31 downto 0);
signal and_439 : std_logic_vector(31 downto 0);
signal or_440 : std_logic_vector(31 downto 0);
signal and_441 : std_logic_vector(31 downto 0);
signal or_443 : std_logic_vector(31 downto 0);
signal and_444 : std_logic_vector(31 downto 0);
signal or_450 : std_logic_vector(31 downto 0);
signal and_451 : std_logic_vector(31 downto 0);
signal or_454 : std_logic_vector(30 downto 0);
signal and_455 : std_logic_vector(30 downto 0);
signal or_458 : std_logic_vector(31 downto 0);
signal and_459 : std_logic_vector(31 downto 0);
signal or_462 : std_logic_vector(31 downto 0);
signal and_463 : std_logic_vector(31 downto 0);
signal or_467 : std_logic_vector(30 downto 0);
signal and_468 : std_logic_vector(30 downto 0);
signal or_475 : std_logic_vector(30 downto 0);
signal and_476 : std_logic_vector(30 downto 0);
signal or_479 : std_logic_vector(31 downto 0);
signal and_480 : std_logic_vector(31 downto 0);
signal or_481 : std_logic_vector(31 downto 0);
signal and_482 : std_logic_vector(31 downto 0);
signal or_485 : std_logic_vector(31 downto 0);
signal and_486 : std_logic_vector(31 downto 0);
signal or_490 : std_logic_vector(31 downto 0);
signal and_491 : std_logic_vector(31 downto 0);
signal or_493 : std_logic_vector(31 downto 0);
signal or_497 : std_logic_vector(31 downto 0);
signal or_512 : std_logic_vector(31 downto 0);
signal and_513 : std_logic_vector(31 downto 0);
signal or_518 : std_logic_vector(30 downto 0);
signal and_519 : std_logic_vector(30 downto 0);
signal or_525 : std_logic_vector(31 downto 0);
signal and_526 : std_logic_vector(31 downto 0);
signal or_529 : std_logic_vector(30 downto 0);
signal and_530 : std_logic_vector(30 downto 0);
signal or_532 : std_logic_vector(30 downto 0);
signal and_533 : std_logic_vector(30 downto 0);
signal or_535 : std_logic_vector(31 downto 0);
signal and_536 : std_logic_vector(31 downto 0);
signal or_538 : std_logic_vector(31 downto 0);
signal and_539 : std_logic_vector(31 downto 0);
signal or_541 : std_logic_vector(31 downto 0);
signal and_542 : std_logic_vector(31 downto 0);
signal or_545 : std_logic_vector(30 downto 0);
signal and_546 : std_logic_vector(30 downto 0);
signal or_548 : std_logic_vector(31 downto 0);
signal and_549 : std_logic_vector(31 downto 0);
signal or_554 : std_logic_vector(30 downto 0);
signal and_555 : std_logic_vector(30 downto 0);
signal or_557 : std_logic_vector(30 downto 0);
signal and_558 : std_logic_vector(30 downto 0);
signal or_568 : std_logic_vector(31 downto 0);
signal and_569 : std_logic_vector(31 downto 0);
signal or_571 : std_logic_vector(30 downto 0);
signal and_572 : std_logic_vector(30 downto 0);
signal or_575 : std_logic_vector(30 downto 0);
signal and_576 : std_logic_vector(30 downto 0);
signal or_590 : std_logic_vector(31 downto 0);
signal and_591 : std_logic_vector(31 downto 0);
signal or_597 : std_logic_vector(31 downto 0);
signal and_598 : std_logic_vector(31 downto 0);
signal or_603 : std_logic_vector(30 downto 0);
signal and_604 : std_logic_vector(30 downto 0);
-- This utility function is used for to generate concatenations of std_logic
-- Little utility function to ease concatenation of an std_logic
-- and explicitely return an std_logic_vector
function repeat(N: natural; B: std_logic) return std_logic_vector is
variable result: std_logic_vector(N-1 downto 0);
begin
result := (others => B);
return result;
end;
begin
-- Instantiation of components
output_split2_i : output_split2 port map (
wa0_data => mux_141,
wa0_addr => mux_142,
ra0_data => sig_1159,
ra0_addr => mux_143,
wa0_en => mux_144,
clk => sig_clock
);
output_split3_i : output_split3 port map (
wa0_data => mux_137,
wa0_addr => mux_138,
ra0_data => sig_1158,
ra0_addr => mux_139,
wa0_en => mux_140,
clk => sig_clock
);
sub_159_i : sub_159 port map (
gt => sig_1157,
result => sig_1156,
in_a => idct_2d_r,
in_b => "00000000000000000000000011111111",
sign => '1'
);
add_165_i : add_165 port map (
result => sig_1155,
in_a => idct_2d_yc_reg7(31 downto 5),
in_b => "000000000000000000000000001"
);
output_split1_i : output_split1 port map (
wa0_data => mux_89,
wa0_addr => mux_90,
ra0_data => sig_1154,
ra0_addr => mux_91,
wa0_en => mux_92,
clk => sig_clock
);
output_split0_i : output_split0 port map (
wa0_data => mux_85,
wa0_addr => mux_86,
ra0_data => sig_1153,
ra0_addr => mux_87,
wa0_en => mux_88,
clk => sig_clock
);
add_172_i : add_172 port map (
result => sig_1152,
in_a => sig_1183,
in_b => "00000000000000000001"
);
add_176_i : add_176 port map (
result => sig_1151,
in_a => sig_1182,
in_b => "00000000000000000001"
);
add_181_i : add_181 port map (
result => sig_1150,
in_a => idct_z2_reg0,
in_b => idct_z3_reg7
);
sub_187_i : sub_187 port map (
result => sig_1149,
in_a => idct_z2_reg1,
in_b => idct_z3_reg6
);
mul_189_i : mul_189 port map (
result => sig_1148,
in_a => idct_z2_reg4(30 downto 0),
in_b => "01000111000111"
);
add_191_i : add_191 port map (
result => sig_1147,
in_a => sig_1148,
in_b => sig_1123(31 downto 1)
);
mul_192_i : mul_192 port map (
result => sig_1146,
in_a => idct_z2_reg5(29 downto 0),
in_b => "01100011111"
);
mul_193_i : mul_193 port map (
result => sig_1145,
in_a => idct_z2_reg6,
in_b => "011111011000101"
);
mul_198_i : mul_198 port map (
result => sig_1144,
in_a => idct_z2_reg4,
in_b => "011010100110111"
);
mul_199_i : mul_199 port map (
result => sig_1143,
in_a => idct_z2_reg7(30 downto 0),
in_b => "01000111000111"
);
sub_209_i : sub_209 port map (
result => sig_1142,
in_a => idct_2d_yc_reg1,
in_b => idct_2d_yc_reg7
);
add_212_i : add_212 port map (
result => sig_1141,
in_a => idct_z1_reg1,
in_b => idct_z1_reg2
);
sub_213_i : sub_213 port map (
result => sig_1140,
in_a => idct_z1_reg1,
in_b => idct_z1_reg2
);
sub_214_i : sub_214 port map (
result => sig_1139,
in_a => idct_z1_reg0,
in_b => idct_z1_reg3
);
mul_215_i : mul_215 port map (
result => sig_1138,
in_a => idct_2d_yc_reg2,
in_b => "0101001110011111"
);
mul_216_i : mul_216 port map (
result => sig_1137,
in_a => idct_2d_yc_reg6,
in_b => "010001010100011"
);
sub_217_i : sub_217 port map (
result => sig_1136,
in_a => sig_1138,
in_b => sig_1137
);
mul_218_i : mul_218 port map (
result => sig_1135,
in_a => idct_2d_yc_reg2,
in_b => "010001010100011"
);
mul_219_i : mul_219 port map (
result => sig_1134,
in_a => idct_2d_yc_reg6,
in_b => "0101001110011111"
);
sub_220_i : sub_220 port map (
result => sig_1133,
in_a => sig_1135,
in_b => sig_1134
);
mul_223_i : mul_223 port map (
result => sig_1132,
in_a => idct_2d_yc_reg5(30 downto 0),
in_b => "010110101000001"
);
sub_227_i : sub_227 port map (
result => sig_1131,
in_a => idct_2d_yc_reg0,
in_b => idct_2d_yc_reg4
);
sub_157_i : sub_157 port map (
ge => sig_1130,
result => sig_1129,
in_a => idct_2d_r,
in_b => "00000000000000000000000000000000",
sign => '1'
);
add_163_i : add_163 port map (
result => sig_1128,
in_a => psc_loop_reg_13,
in_b => "0000000000000001"
);
cmp_164_i : cmp_164 port map (
ne => memextrct_loop_sig_21,
in0 => "0000000000011111",
in1 => psc_loop_reg_13
);
add_170_i : add_170 port map (
result => sig_1127,
in_a => sig_1181,
in_b => "00000000000000000001"
);
add_174_i : add_174 port map (
result => sig_1126,
in_a => sig_1180,
in_b => "00000000000000000001"
);
add_180_i : add_180 port map (
result => sig_1125,
in_a => sig_1179,
in_b => "00000000000000000001"
);
sub_186_i : sub_186 port map (
result => sig_1124,
in_a => idct_z2_reg2,
in_b => idct_z3_reg5
);
mul_190_i : mul_190 port map (
result => sig_1123,
in_a => idct_z2_reg7,
in_b => "011010100110111"
);
mul_196_i : mul_196 port map (
result => sig_1122,
in_a => idct_z2_reg6(29 downto 0),
in_b => "01100011111"
);
sub_200_i : sub_200 port map (
result => sig_1121,
in_a => sig_1144,
in_b => sig_1178
);
add_206_i : add_206 port map (
result => sig_1120,
in_a => idct_z1_reg4,
in_b => idct_z1_reg6
);
add_210_i : add_210 port map (
result => sig_1119,
in_a => idct_2d_yc_reg1,
in_b => idct_2d_yc_reg7
);
add_171_i : add_171 port map (
result => sig_1118,
in_a => idct_2d_yc_reg4(31 downto 5),
in_b => "000000000000000000000000001"
);
add_177_i : add_177 port map (
result => sig_1117,
in_a => idct_2d_yc_reg1(31 downto 5),
in_b => "000000000000000000000000001"
);
add_179_i : add_179 port map (
result => sig_1116,
in_a => idct_2d_yc_reg0(31 downto 5),
in_b => "000000000000000000000000001"
);
mul_195_i : mul_195 port map (
result => sig_1115,
in_a => idct_z2_reg5,
in_b => "011111011000101"
);
sub_197_i : sub_197 port map (
result => sig_1114,
in_a => sig_1115,
in_b => sig_1177
);
sub_207_i : sub_207 port map (
result => sig_1113,
in_a => idct_z1_reg7,
in_b => idct_z1_reg5
);
mul_230_i : mul_230 port map (
result => sig_1112,
in_a => idct_2d_yc_reg3(30 downto 0),
in_b => "010110101000001"
);
sub_185_i : sub_185 port map (
result => sig_1111,
in_a => idct_z2_reg3,
in_b => idct_z3_reg4
);
add_211_i : add_211 port map (
result => sig_1110,
in_a => idct_z1_reg0,
in_b => idct_z1_reg3
);
add_226_i : add_226 port map (
result => sig_1109,
in_a => idct_2d_yc_reg0,
in_b => idct_2d_yc_reg4
);
add_235_i : add_235 port map (
result => sig_1108,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_314_i : add_314 port map (
result => sig_1107,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
sub_160_i : sub_160 port map (
le => sig_1106,
result => sig_1105,
in_a => idct_2d_r,
in_b => "00000000000000000000000011111111",
sign => '1'
);
add_173_i : add_173 port map (
result => sig_1104,
in_a => idct_2d_yc_reg3(31 downto 5),
in_b => "000000000000000000000000001"
);
add_182_i : add_182 port map (
result => sig_1103,
in_a => idct_z2_reg1,
in_b => idct_z3_reg6
);
sub_188_i : sub_188 port map (
result => sig_1102,
in_a => idct_z2_reg0,
in_b => idct_z3_reg7
);
sub_243_i : sub_243 port map (
result => sig_1101,
in_a => sig_1115,
in_b => sig_1176
);
sub_262_i : sub_262 port map (
result => sig_1100,
in_a => sig_1115,
in_b => sig_1175
);
output_split4_i : output_split4 port map (
wa0_data => mux_65,
wa0_addr => mux_66,
ra0_data => sig_1099,
ra0_addr => mux_67,
wa0_en => mux_68,
clk => sig_clock
);
output_split5_i : output_split5 port map (
wa0_data => mux_61,
wa0_addr => mux_62,
ra0_data => sig_1098,
ra0_addr => mux_63,
wa0_en => mux_64,
clk => sig_clock
);
output_split6_i : output_split6 port map (
wa0_data => mux_57,
wa0_addr => mux_58,
ra0_data => sig_1097,
ra0_addr => mux_59,
wa0_en => mux_60,
clk => sig_clock
);
output_split7_i : output_split7 port map (
wa0_data => mux_53,
wa0_addr => mux_54,
ra0_data => sig_1096,
ra0_addr => mux_55,
wa0_en => mux_56,
clk => sig_clock
);
input_split0_i : input_split0 port map (
ra0_data => sig_1095,
ra0_addr => mux_46,
ra1_data => sig_1094,
ra1_addr => mux_47,
ra2_data => sig_1093,
ra2_addr => mux_48,
ra3_data => sig_1092,
ra3_addr => mux_49,
clk => sig_clock,
wa2_data => mux_50,
wa2_addr => mux_51,
wa2_en => mux_52
);
add_194_i : add_194 port map (
result => sig_1091,
in_a => sig_1146,
in_b => sig_1145(31 downto 2)
);
add_205_i : add_205 port map (
result => sig_1090,
in_a => idct_z1_reg7,
in_b => idct_z1_reg5
);
add_254_i : add_254 port map (
result => sig_1089,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_276_i : add_276 port map (
result => sig_1088,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
sub_284_i : sub_284 port map (
result => sig_1087,
in_a => sig_1115,
in_b => sig_1174
);
input_split1_i : input_split1 port map (
wa0_data => mux_39,
wa0_addr => mux_40,
ra0_data => sig_1086,
ra0_addr => mux_41,
wa0_en => mux_42,
ra1_data => sig_1085,
ra1_addr => mux_43,
ra2_data => sig_1084,
ra2_addr => mux_44,
ra3_data => sig_1083,
ra3_addr => mux_45,
clk => sig_clock
);
add_166_i : add_166 port map (
result => sig_1082,
in_a => sig_1173,
in_b => "00000000000000000001"
);
add_168_i : add_168 port map (
result => sig_1081,
in_a => sig_1172,
in_b => "00000000000000000001"
);
add_178_i : add_178 port map (
result => sig_1080,
in_a => sig_1171,
in_b => "00000000000000000001"
);
add_183_i : add_183 port map (
result => sig_1079,
in_a => idct_z2_reg2,
in_b => idct_z3_reg5
);
sub_332_i : sub_332 port map (
result => sig_1078,
in_a => sig_689,
in_b => sig_688
);
mul_341_i : mul_341 port map (
result => sig_1077,
in_a => or_339,
in_b => "0101001110011111"
);
mul_357_i : mul_357 port map (
result => sig_1076,
in_a => or_355,
in_b => "010110101000001"
);
mul_365_i : mul_365 port map (
result => sig_1075,
in_a => or_363,
in_b => "010001010100011"
);
mul_368_i : mul_368 port map (
result => sig_1074,
in_a => or_366,
in_b => "0101001110011111"
);
sub_369_i : sub_369 port map (
result => sig_1073,
in_a => sig_1075,
in_b => sig_1074
);
sub_370_i : sub_370 port map (
result => sig_1072,
in_a => sig_1115,
in_b => sig_1170
);
sub_377_i : sub_377 port map (
result => sig_1071,
in_a => sig_680,
in_b => sig_715
);
cmp_398_i : cmp_398 port map (
eq => sig_1070,
in0 => "110",
in1 => augh_main_k(2 downto 0)
);
cmp_400_i : cmp_400 port map (
eq => sig_1069,
in0 => "101",
in1 => augh_main_k(2 downto 0)
);
cmp_404_i : cmp_404 port map (
eq => sig_1068,
in0 => "011",
in1 => augh_main_k(2 downto 0)
);
cmp_406_i : cmp_406 port map (
eq => sig_1067,
in0 => "010",
in1 => augh_main_k(2 downto 0)
);
cmp_408_i : cmp_408 port map (
eq => sig_1066,
in0 => "001",
in1 => augh_main_k(2 downto 0)
);
cmp_410_i : cmp_410 port map (
eq => sig_1065,
in0 => "000",
in1 => augh_main_k(2 downto 0)
);
cmp_412_i : cmp_412 port map (
eq => sig_1064,
in0 => '0',
in1 => augh_main_k(0)
);
sub_429_i : sub_429 port map (
result => sig_1063,
in_a => or_421,
in_b => or_427
);
add_466_i : add_466 port map (
result => sig_1062,
in_a => or_462,
in_b => or_464
);
sub_496_i : sub_496 port map (
result => sig_1061,
in_a => sig_652,
in_b => sig_651
);
sub_521_i : sub_521 port map (
result => sig_1060,
in_a => or_438,
in_b => or_464
);
sub_528_i : sub_528 port map (
result => sig_1059,
in_a => sig_643,
in_b => sig_642
);
fsm_23_i : fsm_23 port map (
clock => sig_clock,
reset => sig_reset,
in0 => memextrct_loop_sig_21,
out181 => sig_1058,
out182 => sig_1057,
out183 => sig_1056,
out184 => sig_1055,
out185 => sig_1054,
out8 => sig_1053,
out13 => sig_1052,
out14 => sig_1051,
out16 => sig_1050,
out18 => sig_1049,
out19 => sig_1048,
out20 => sig_1047,
out21 => sig_1046,
out22 => sig_1045,
in2 => sig_start,
out23 => sig_1044,
out24 => sig_1043,
out25 => sig_1042,
out26 => sig_1041,
out27 => sig_1040,
out28 => sig_1039,
out29 => sig_1038,
out30 => sig_1037,
out31 => sig_1036,
out33 => sig_1035,
out35 => sig_1034,
out36 => sig_1033,
out38 => sig_1032,
out40 => sig_1031,
out42 => sig_1030,
in3 => memextrct_loop_sig_22,
out44 => sig_1029,
out46 => sig_1028,
out48 => sig_1027,
out49 => sig_1026,
out50 => sig_1025,
out52 => sig_1024,
out54 => sig_1023,
out56 => sig_1022,
out57 => sig_1021,
out58 => sig_1020,
in4 => test_cp_0_16,
out60 => sig_1019,
in5 => test_cp_1_17,
out164 => sig_1018,
out165 => sig_1017,
out167 => sig_1016,
out168 => sig_1015,
out170 => sig_1014,
out171 => sig_1013,
out173 => sig_1012,
out174 => sig_1011,
out176 => sig_1010,
out178 => sig_1009,
out0 => sig_1008,
out1 => sig_1007,
out2 => sig_1006,
in1 => cp_rest,
out4 => sig_1005,
out90 => sig_1004,
out91 => sig_1003,
out97 => sig_1002,
out99 => sig_1001,
out101 => sig_1000,
in6 => stdout_ack,
out103 => sig_999,
out105 => sig_998,
out106 => sig_997,
out107 => sig_996,
out108 => sig_995,
out135 => sig_994,
out136 => sig_993,
out137 => sig_992,
out138 => sig_991,
in11 => augh_test_9,
out140 => sig_990,
out141 => sig_989,
out142 => sig_988,
out143 => sig_987,
out145 => sig_986,
out146 => sig_985,
out148 => sig_984,
out150 => sig_983,
out153 => sig_982,
out154 => sig_981,
out155 => sig_980,
out156 => sig_979,
out157 => sig_978,
out158 => sig_977,
out159 => sig_976,
out160 => sig_975,
out161 => sig_974,
out162 => sig_973,
out111 => sig_972,
out112 => sig_971,
out114 => sig_970,
out116 => sig_969,
out118 => sig_968,
out120 => sig_967,
out121 => sig_966,
out122 => sig_965,
out123 => sig_964,
out124 => sig_963,
out125 => sig_962,
out126 => sig_961,
in7 => cp_en,
out129 => sig_960,
out130 => sig_959,
in8 => stdin_ack,
out131 => sig_958,
in9 => psc_loop_sig_20,
out132 => sig_957,
out133 => sig_956,
out134 => sig_955,
in10 => augh_test_11,
out186 => sig_954,
out187 => sig_953,
out190 => sig_952,
out195 => sig_951,
out197 => sig_950,
out198 => sig_949,
out199 => sig_948,
out200 => sig_947,
out201 => sig_946,
out203 => sig_945,
out204 => sig_944,
out206 => sig_943,
out207 => sig_942,
out209 => sig_941,
out210 => sig_940,
out212 => sig_939,
out213 => sig_938,
out215 => sig_937,
out217 => sig_936,
out220 => sig_935,
out221 => sig_934,
out222 => sig_933,
out223 => sig_932,
out224 => sig_931,
out225 => sig_930,
out226 => sig_929,
out227 => sig_928,
out228 => sig_927,
out229 => sig_926,
out231 => sig_925,
out232 => sig_924,
out234 => sig_923,
out235 => sig_922,
out237 => sig_921,
out238 => sig_920,
out240 => sig_919,
out241 => sig_918,
out243 => sig_917,
out245 => sig_916,
out248 => sig_915,
out249 => sig_914,
out250 => sig_913,
out251 => sig_912,
out252 => sig_911,
out253 => sig_910,
out254 => sig_909,
out255 => sig_908,
out256 => sig_907,
out257 => sig_906,
out259 => sig_905,
out260 => sig_904,
out262 => sig_903,
out263 => sig_902,
out265 => sig_901,
out266 => sig_900,
out268 => sig_899,
out269 => sig_898,
out271 => sig_897,
out273 => sig_896,
out276 => sig_895,
out277 => sig_894,
out278 => sig_893,
out279 => sig_892,
out280 => sig_891,
out281 => sig_890,
out282 => sig_889,
out283 => sig_888,
out284 => sig_887,
out285 => sig_886,
out286 => sig_885,
out287 => sig_884,
out288 => sig_883,
out289 => sig_882,
out290 => sig_881,
out291 => sig_880,
out292 => sig_879,
out293 => sig_878,
out294 => sig_877,
out295 => sig_876,
out296 => sig_875,
out297 => sig_874,
out298 => sig_873,
out311 => sig_872,
out312 => sig_871,
out313 => sig_870,
out314 => sig_869,
out315 => sig_868,
out316 => sig_867,
out318 => sig_866,
out321 => sig_865,
out322 => sig_864,
out323 => sig_863,
out324 => sig_862,
out325 => sig_861,
out326 => sig_860,
out327 => sig_859,
out328 => sig_858,
out329 => sig_857,
out333 => sig_856,
out341 => sig_855,
out342 => sig_854,
out343 => sig_853,
out344 => sig_852,
out345 => sig_851,
out346 => sig_850,
out349 => sig_849,
out350 => sig_848,
out351 => sig_847,
out352 => sig_846,
out353 => sig_845,
out354 => sig_844,
out355 => sig_843,
out357 => sig_842,
out361 => sig_841,
out362 => sig_840,
out363 => sig_839,
out364 => sig_838,
out366 => sig_837,
out367 => sig_836,
out371 => sig_835,
out372 => sig_834,
out373 => sig_833,
out382 => sig_832,
out383 => sig_831,
out385 => sig_830,
out393 => sig_829,
out394 => sig_828,
out395 => sig_827,
out396 => sig_826,
out398 => sig_825,
out400 => sig_824,
out401 => sig_823,
out402 => sig_822,
out404 => sig_821,
out406 => sig_820,
out407 => sig_819,
out408 => sig_818,
out409 => sig_817,
out410 => sig_816,
out411 => sig_815,
out412 => sig_814,
out413 => sig_813,
out414 => sig_812,
out416 => sig_811,
out417 => sig_810,
out418 => sig_809,
out419 => sig_808,
out422 => sig_807,
out423 => sig_806,
out425 => sig_805,
out426 => sig_804,
out428 => sig_803,
out429 => sig_802,
out430 => sig_801,
out431 => sig_800,
out433 => sig_799,
out434 => sig_798,
out435 => sig_797,
out436 => sig_796,
out437 => sig_795,
out438 => sig_794,
out440 => sig_793,
out441 => sig_792,
out443 => sig_791,
out444 => sig_790,
out445 => sig_789,
out446 => sig_788,
out447 => sig_787,
out450 => sig_786,
out451 => sig_785,
out454 => sig_784,
out455 => sig_783,
out457 => sig_782,
out458 => sig_781,
out459 => sig_780,
out460 => sig_779,
out461 => sig_778,
out462 => sig_777,
out463 => sig_776,
out464 => sig_775,
out465 => sig_774,
out466 => sig_773,
out467 => sig_772,
out468 => sig_771,
out469 => sig_770,
out472 => sig_769,
out475 => sig_768,
out481 => sig_767,
out482 => sig_766,
out483 => sig_765,
out484 => sig_764,
out487 => sig_763,
out488 => sig_762,
out491 => sig_761,
out495 => sig_760,
out496 => sig_759,
out497 => sig_758,
out498 => sig_757,
out499 => sig_756,
out500 => sig_755,
out501 => sig_754,
out512 => sig_753,
out513 => sig_752,
out517 => sig_751,
out518 => sig_750,
out519 => sig_749,
out521 => sig_748,
out522 => sig_747,
out524 => sig_746,
out525 => sig_745,
out526 => sig_744,
out527 => sig_743,
out528 => sig_742,
out531 => sig_741,
out540 => sig_740,
out542 => sig_739,
out544 => sig_738,
out545 => sig_737,
out554 => sig_736,
out555 => sig_735,
out559 => sig_734,
out560 => sig_733,
out561 => sig_732,
out562 => sig_731,
out563 => sig_730,
out566 => sig_729,
out567 => sig_728,
out570 => sig_727,
out572 => sig_726,
out575 => sig_725,
out577 => sig_724,
out578 => sig_723,
out580 => sig_722,
out581 => sig_721
);
add_167_i : add_167 port map (
result => sig_720,
in_a => idct_2d_yc_reg6(31 downto 5),
in_b => "000000000000000000000000001"
);
add_169_i : add_169 port map (
result => sig_719,
in_a => idct_2d_yc_reg5(31 downto 5),
in_b => "000000000000000000000000001"
);
add_175_i : add_175 port map (
result => sig_718,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_255_i : add_255 port map (
result => sig_717,
in_a => sig_1169,
in_b => "00000000000000000001"
);
sub_362_i : sub_362 port map (
result => sig_716,
in_a => or_358,
in_b => or_360
);
mul_376_i : mul_376 port map (
result => sig_715,
in_a => or_374,
in_b => "010001010100011"
);
add_420_i : add_420 port map (
result => sig_714,
in_a => sig_1168,
in_b => "00000000000000000001"
);
sub_446_i : sub_446 port map (
result => sig_713,
in_a => sig_667,
in_b => sig_666
);
mul_456_i : mul_456 port map (
result => sig_712,
in_a => or_454,
in_b => "010110101000001"
);
mul_457_i : mul_457 port map (
result => sig_711,
in_a => or_450,
in_b => "0101001110011111"
);
sub_461_i : sub_461 port map (
result => sig_710,
in_a => sig_711,
in_b => sig_662
);
sub_517_i : sub_517 port map (
result => sig_709,
in_a => or_512,
in_b => or_514
);
mul_560_i : mul_560 port map (
result => sig_708,
in_a => or_435,
in_b => "010001010100011"
);
mul_565_i : mul_565 port map (
result => sig_707,
in_a => or_363,
in_b => "0101001110011111"
);
mul_578_i : mul_578 port map (
result => sig_706,
in_a => or_431,
in_b => "010001010100011"
);
muxb_162_i : muxb_162 port map (
in_sel => cp_en,
out_data => sig_705,
in_data0 => '0',
in_data1 => '1'
);
add_184_i : add_184 port map (
result => sig_704,
in_a => idct_z2_reg3,
in_b => idct_z3_reg4
);
muxb_201_i : muxb_201 port map (
in_sel => cp_en,
out_data => sig_703,
in_data0 => '0',
in_data1 => '1'
);
cmp_202_i : cmp_202 port map (
ne => memextrct_loop_sig_22,
in0 => "0000000000000111",
in1 => psc_loop_reg_13
);
cmp_203_i : cmp_203 port map (
eq => test_cp_1_17,
in0 => '1',
in1 => cp_id_reg_stable_15
);
cmp_204_i : cmp_204 port map (
eq => sig_702,
in0 => '0',
in1 => cp_id_reg_stable_15
);
sub_208_i : sub_208 port map (
result => sig_701,
in_a => idct_z1_reg4,
in_b => idct_z1_reg6
);
add_236_i : add_236 port map (
result => sig_700,
in_a => sig_1167,
in_b => "00000000000000000001"
);
muxb_263_i : muxb_263 port map (
in_sel => not_264,
out_data => sig_699,
in_data0 => '0',
in_data1 => '1'
);
muxb_265_i : muxb_265 port map (
in_sel => not_264,
out_data => sig_698,
in_data0 => '0',
in_data1 => '1'
);
add_277_i : add_277 port map (
result => sig_697,
in_a => sig_1166,
in_b => "00000000000000000001"
);
add_295_i : add_295 port map (
result => sig_696,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_296_i : add_296 port map (
result => sig_695,
in_a => sig_1165,
in_b => "00000000000000000001"
);
sub_303_i : sub_303 port map (
result => sig_694,
in_a => sig_1115,
in_b => sig_1164
);
add_315_i : add_315 port map (
result => sig_693,
in_a => sig_1163,
in_b => "00000000000000000001"
);
muxb_322_i : muxb_322 port map (
in_sel => cp_en,
out_data => sig_692,
in_data0 => '0',
in_data1 => '1'
);
add_323_i : add_323 port map (
result => sig_691,
in_a => psc_loop_reg_13,
in_b => "0000000000000001"
);
cmp_324_i : cmp_324 port map (
ne => psc_loop_sig_20,
in0 => "0000000000000001",
in1 => psc_loop_reg_13
);
cmp_325_i : cmp_325 port map (
eq => sig_690,
in0 => '0',
in1 => cp_id_reg_stable_15
);
mul_328_i : mul_328 port map (
result => sig_689,
in_a => or_326,
in_b => "010001010100011"
);
mul_331_i : mul_331 port map (
result => sig_688,
in_a => or_329,
in_b => "0101001110011111"
);
sub_337_i : sub_337 port map (
result => sig_687,
in_a => or_333,
in_b => or_335
);
add_338_i : add_338 port map (
result => sig_686,
in_a => or_333,
in_b => or_297
);
mul_344_i : mul_344 port map (
result => sig_685,
in_a => or_342,
in_b => "010001010100011"
);
sub_345_i : sub_345 port map (
result => sig_684,
in_a => sig_1077,
in_b => sig_685
);
add_350_i : add_350 port map (
result => sig_683,
in_a => or_346,
in_b => or_348
);
mul_353_i : mul_353 port map (
result => sig_682,
in_a => or_351,
in_b => "010110101000001"
);
sub_354_i : sub_354 port map (
result => sig_681,
in_a => or_346,
in_b => or_348
);
mul_373_i : mul_373 port map (
result => sig_680,
in_a => or_371,
in_b => "0101001110011111"
);
add_382_i : add_382 port map (
result => sig_679,
in_a => or_378,
in_b => or_380
);
mul_383_i : mul_383 port map (
result => sig_678,
in_a => idct_2d_yc_reg3(30 downto 0),
in_b => "010110101000001"
);
add_390_i : add_390 port map (
result => sig_677,
in_a => or_386,
in_b => or_388
);
sub_391_i : sub_391 port map (
result => sig_676,
in_a => or_386,
in_b => or_388
);
cmp_392_i : cmp_392 port map (
ne => augh_test_11,
in0 => "00000000000000000000000000111111",
in1 => augh_main_k
);
add_393_i : add_393 port map (
result => sig_675,
in_a => augh_main_k,
in_b => "00000000000000000000000000000001"
);
cmp_396_i : cmp_396 port map (
eq => sig_674,
in0 => "111",
in1 => augh_main_k(2 downto 0)
);
cmp_402_i : cmp_402 port map (
eq => sig_673,
in0 => "100",
in1 => augh_main_k(2 downto 0)
);
cmp_411_i : cmp_411 port map (
eq => sig_672,
in0 => '1',
in1 => augh_main_k(0)
);
cmp_413_i : cmp_413 port map (
ne => augh_test_9,
in0 => "00000000000000000000000000111111",
in1 => augh_main_k
);
mul_416_i : mul_416 port map (
result => sig_671,
in_a => or_414,
in_b => "010110101000001"
);
add_419_i : add_419 port map (
result => sig_670,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_430_i : add_430 port map (
result => sig_669,
in_a => or_421,
in_b => or_427
);
sub_437_i : sub_437 port map (
result => sig_668,
in_a => sig_1115,
in_b => sig_1162
);
mul_442_i : mul_442 port map (
result => sig_667,
in_a => or_440,
in_b => "0101001110011111"
);
mul_445_i : mul_445 port map (
result => sig_666,
in_a => or_443,
in_b => "010001010100011"
);
mul_447_i : mul_447 port map (
result => sig_665,
in_a => or_440,
in_b => "010001010100011"
);
mul_448_i : mul_448 port map (
result => sig_664,
in_a => or_443,
in_b => "0101001110011111"
);
sub_449_i : sub_449 port map (
result => sig_663,
in_a => sig_665,
in_b => sig_664
);
mul_460_i : mul_460 port map (
result => sig_662,
in_a => or_458,
in_b => "010001010100011"
);
mul_469_i : mul_469 port map (
result => sig_661,
in_a => or_467,
in_b => "010110101000001"
);
add_474_i : add_474 port map (
result => sig_660,
in_a => or_470,
in_b => or_472
);
mul_477_i : mul_477 port map (
result => sig_659,
in_a => or_475,
in_b => "010110101000001"
);
sub_478_i : sub_478 port map (
result => sig_658,
in_a => or_470,
in_b => or_472
);
add_483_i : add_483 port map (
result => sig_657,
in_a => or_479,
in_b => or_481
);
sub_484_i : sub_484 port map (
result => sig_656,
in_a => or_479,
in_b => or_481
);
add_487_i : add_487 port map (
result => sig_655,
in_a => or_425,
in_b => or_485
);
sub_488_i : sub_488 port map (
result => sig_654,
in_a => or_425,
in_b => or_485
);
sub_489_i : sub_489 port map (
result => sig_653,
in_a => or_378,
in_b => or_285
);
mul_492_i : mul_492 port map (
result => sig_652,
in_a => or_490,
in_b => "010001010100011"
);
mul_495_i : mul_495 port map (
result => sig_651,
in_a => or_493,
in_b => "0101001110011111"
);
mul_499_i : mul_499 port map (
result => sig_650,
in_a => or_435,
in_b => "0101001110011111"
);
mul_502_i : mul_502 port map (
result => sig_649,
in_a => or_500,
in_b => "010001010100011"
);
sub_503_i : sub_503 port map (
result => sig_648,
in_a => sig_650,
in_b => sig_649
);
add_508_i : add_508 port map (
result => sig_647,
in_a => or_504,
in_b => or_506
);
mul_511_i : mul_511 port map (
result => sig_646,
in_a => or_509,
in_b => "010110101000001"
);
add_516_i : add_516 port map (
result => sig_645,
in_a => or_512,
in_b => or_514
);
mul_520_i : mul_520 port map (
result => sig_644,
in_a => or_518,
in_b => "010110101000001"
);
mul_524_i : mul_524 port map (
result => sig_643,
in_a => or_522,
in_b => "010001010100011"
);
mul_527_i : mul_527 port map (
result => sig_642,
in_a => or_525,
in_b => "0101001110011111"
);
mul_531_i : mul_531 port map (
result => sig_641,
in_a => or_529,
in_b => "010110101000001"
);
mul_534_i : mul_534 port map (
result => sig_640,
in_a => or_532,
in_b => "010110101000001"
);
add_537_i : add_537 port map (
result => sig_639,
in_a => or_497,
in_b => or_535
);
mul_540_i : mul_540 port map (
result => sig_638,
in_a => or_538,
in_b => "0101001110011111"
);
mul_543_i : mul_543 port map (
result => sig_637,
in_a => or_541,
in_b => "010001010100011"
);
sub_544_i : sub_544 port map (
result => sig_636,
in_a => sig_638,
in_b => sig_637
);
mul_547_i : mul_547 port map (
result => sig_635,
in_a => or_545,
in_b => "010110101000001"
);
add_552_i : add_552 port map (
result => sig_634,
in_a => or_548,
in_b => or_550
);
sub_553_i : sub_553 port map (
result => sig_633,
in_a => or_548,
in_b => or_550
);
mul_556_i : mul_556 port map (
result => sig_632,
in_a => or_554,
in_b => "010110101000001"
);
mul_559_i : mul_559 port map (
result => sig_631,
in_a => or_557,
in_b => "010110101000001"
);
mul_561_i : mul_561 port map (
result => sig_630,
in_a => or_500,
in_b => "0101001110011111"
);
sub_562_i : sub_562 port map (
result => sig_629,
in_a => sig_708,
in_b => sig_630
);
sub_563_i : sub_563 port map (
result => sig_628,
in_a => or_504,
in_b => or_506
);
add_564_i : add_564 port map (
result => sig_627,
in_a => or_358,
in_b => or_360
);
mul_566_i : mul_566 port map (
result => sig_626,
in_a => or_366,
in_b => "010001010100011"
);
sub_567_i : sub_567 port map (
result => sig_625,
in_a => sig_707,
in_b => sig_626
);
add_570_i : add_570 port map (
result => sig_624,
in_a => or_417,
in_b => or_568
);
mul_573_i : mul_573 port map (
result => sig_623,
in_a => or_571,
in_b => "010110101000001"
);
sub_574_i : sub_574 port map (
result => sig_622,
in_a => or_417,
in_b => or_568
);
mul_577_i : mul_577 port map (
result => sig_621,
in_a => or_575,
in_b => "010110101000001"
);
mul_579_i : mul_579 port map (
result => sig_620,
in_a => or_541,
in_b => "0101001110011111"
);
sub_580_i : sub_580 port map (
result => sig_619,
in_a => sig_706,
in_b => sig_620
);
sub_585_i : sub_585 port map (
result => sig_618,
in_a => or_581,
in_b => or_583
);
sub_586_i : sub_586 port map (
result => sig_617,
in_a => sig_1115,
in_b => sig_1161
);
mul_589_i : mul_589 port map (
result => sig_616,
in_a => or_587,
in_b => "0101001110011111"
);
mul_592_i : mul_592 port map (
result => sig_615,
in_a => or_590,
in_b => "010001010100011"
);
sub_593_i : sub_593 port map (
result => sig_614,
in_a => sig_616,
in_b => sig_615
);
mul_594_i : mul_594 port map (
result => sig_613,
in_a => or_587,
in_b => "010001010100011"
);
mul_595_i : mul_595 port map (
result => sig_612,
in_a => or_590,
in_b => "0101001110011111"
);
sub_596_i : sub_596 port map (
result => sig_611,
in_a => sig_613,
in_b => sig_612
);
sub_599_i : sub_599 port map (
result => sig_610,
in_a => or_423,
in_b => or_597
);
add_600_i : add_600 port map (
result => sig_609,
in_a => or_423,
in_b => or_597
);
add_601_i : add_601 port map (
result => sig_608,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_602_i : add_602 port map (
result => sig_607,
in_a => sig_1160,
in_b => "00000000000000000001"
);
mul_605_i : mul_605 port map (
result => sig_606,
in_a => or_603,
in_b => "010110101000001"
);
-- Behaviour of component 'mux_66' model 'mux'
mux_66 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_947) and "110") or
(repeat(3, sig_945) and "101") or
(repeat(3, sig_943) and "100") or
(repeat(3, sig_941) and "011") or
(repeat(3, sig_949) and "111") or
(repeat(3, sig_939) and "010") or
(repeat(3, sig_937) and "001");
-- Behaviour of component 'mux_30' model 'mux'
mux_30 <=
(sig_873 and cp_en);
-- Behaviour of component 'mux_32' model 'mux'
mux_32 <=
(sig_1002 and sig_702) or
(sig_872 and sig_690);
-- Behaviour of component 'mux_33' model 'mux'
mux_33 <=
(sig_1039 and cp_din(0)) or
(sig_954 and '1');
-- Behaviour of component 'mux_34' model 'mux'
mux_34 <=
(sig_1038 and cp_rest) or
(sig_953 and '1');
-- Behaviour of component 'mux_58' model 'mux'
mux_58 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_966) and "110") or
(repeat(3, sig_957) and "101") or
(repeat(3, sig_956) and "100") or
(repeat(3, sig_990) and "011") or
(repeat(3, sig_996) and "111") or
(repeat(3, sig_986) and "010") or
(repeat(3, sig_984) and "001");
-- Behaviour of component 'mux_59' model 'mux'
mux_59 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_60' model 'mux'
mux_60 <=
(sig_1004 and and_161) or
(sig_995 and '1');
-- Behaviour of component 'mux_61' model 'mux'
mux_61 <=
(repeat(8, sig_1003) and cp_din(23 downto 16)) or
(repeat(8, sig_977) and mux_156);
-- Behaviour of component 'mux_62' model 'mux'
mux_62 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_974) and "110") or
(repeat(3, sig_1018) and "101") or
(repeat(3, sig_1016) and "100") or
(repeat(3, sig_1014) and "011") or
(repeat(3, sig_976) and "111") or
(repeat(3, sig_1012) and "010") or
(repeat(3, sig_1010) and "001");
-- Behaviour of component 'mux_63' model 'mux'
mux_63 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_64' model 'mux'
mux_64 <=
(sig_1004 and and_161) or
(sig_975 and '1');
-- Behaviour of component 'mux_65' model 'mux'
mux_65 <=
(repeat(8, sig_1003) and cp_din(31 downto 24)) or
(repeat(8, sig_950) and mux_156);
-- Behaviour of component 'mux_35' model 'mux'
mux_35 <=
(sig_954 and '1') or
(sig_874 and augh_main_k(0));
-- Behaviour of component 'mux_36' model 'mux'
mux_36 <=
(sig_953 and '1') or
(sig_873 and cp_en);
-- Behaviour of component 'mux_37' model 'mux'
mux_37 <=
(repeat(16, sig_1052) and sig_1128) or
(repeat(16, sig_874) and sig_691);
-- Behaviour of component 'mux_38' model 'mux'
mux_38 <=
(sig_1051 and cp_en) or
(sig_1049 and '1');
-- Behaviour of component 'mux_39' model 'mux'
mux_39 <=
(repeat(32, sig_1005) and cp_din(31 downto 0)) or
(repeat(32, sig_884) and sig_704) or
(repeat(32, sig_880) and sig_1124) or
(repeat(32, sig_862) and sig_1103) or
(repeat(32, sig_859) and sig_1102) or
(repeat(32, sig_887) and (sig_1084(28 downto 0) & "000")) or
(repeat(32, sig_831) and read32_ret0_10) or
(repeat(32, sig_733) and (sig_1085(28 downto 0) & "000"));
-- Behaviour of component 'mux_45' model 'mux'
mux_45 <=
(repeat(5, sig_857) and "01101") or
(repeat(5, sig_754) and "11011") or
(repeat(5, sig_742) and "10111") or
(repeat(5, sig_737) and "10001") or
(repeat(5, sig_770) and "11111");
-- Behaviour of component 'mux_46' model 'mux'
mux_46 <=
(repeat(5, sig_867) and "01010") or
(repeat(5, sig_852) and "01111") or
(repeat(5, sig_843) and "11110") or
(repeat(5, sig_769) and "11010") or
(repeat(5, sig_761) and "11111") or
(repeat(5, sig_857) and "01011") or
(repeat(5, sig_755) and "10110") or
(repeat(5, sig_741) and "10011");
-- Behaviour of component 'mux_47' model 'mux'
mux_47 <=
(repeat(5, sig_867) and "01011") or
(repeat(5, sig_852) and "01110") or
(repeat(5, sig_843) and "11111") or
(repeat(5, sig_788) and "00001") or
(repeat(5, sig_770) and "11011") or
(repeat(5, sig_730) and "00111") or
(repeat(5, sig_857) and "01001") or
(repeat(5, sig_764) and "00110") or
(repeat(5, sig_742) and "10010") or
(repeat(5, sig_735) and "10000") or
(repeat(5, sig_762) and "00010") or
(repeat(5, sig_761) and "11101") or
(repeat(5, sig_755) and "10111") or
(repeat(5, sig_752) and "11001");
-- Behaviour of component 'mux_48' model 'mux'
mux_48 <=
(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
(repeat(5, sig_865) and "01101") or
(repeat(5, sig_844) and "11101") or
(repeat(5, sig_823) and "11000") or
(repeat(5, sig_818) and "10100") or
(repeat(5, sig_810) and "00100") or
(repeat(5, sig_804) and "10001") or
(repeat(5, sig_797) and "10101") or
(repeat(5, sig_785) and "11001") or
(repeat(5, sig_758) and "10000") or
(repeat(5, sig_731) and "00101") or
(repeat(5, sig_1017) and "11011") or
(repeat(5, sig_1015) and "10111") or
(repeat(5, sig_1013) and "10011") or
(repeat(5, sig_1011) and "01111") or
(repeat(5, sig_918) and "01110") or
(repeat(5, sig_916) and "01010") or
(repeat(5, sig_915) and "00110") or
(repeat(5, sig_973) and "11111") or
(repeat(5, sig_913) and "00010") or
(repeat(5, sig_891) and "01001") or
(repeat(5, sig_871) and "01100") or
(repeat(5, sig_1009) and "01011") or
(repeat(5, sig_922) and "10110") or
(repeat(5, sig_920) and "10010") or
(repeat(5, sig_1058) and "00111") or
(repeat(5, sig_1056) and "00011") or
(repeat(5, sig_926) and "11110") or
(repeat(5, sig_924) and "11010");
-- Behaviour of component 'mux_49' model 'mux'
mux_49 <=
(repeat(5, sig_866) and "01000") or
(repeat(5, sig_842) and "11100") or
(repeat(5, sig_787) and "00011") or
(repeat(5, sig_770) and "11000") or
(repeat(5, sig_755) and "10100") or
(repeat(5, sig_850) and "01101") or
(repeat(5, sig_752) and "11011") or
(repeat(5, sig_742) and "10001") or
(repeat(5, sig_735) and "10010");
-- Behaviour of component 'mux_40' model 'mux'
mux_40 <=
(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
(repeat(5, sig_794) and "11000") or
(repeat(5, sig_782) and "10100") or
(repeat(5, sig_781) and "11100") or
(repeat(5, sig_780) and "11110") or
(repeat(5, sig_776) and "11001") or
(repeat(5, sig_773) and "01001") or
(repeat(5, sig_771) and "10011") or
(repeat(5, sig_763) and "10001") or
(repeat(5, sig_760) and "11010") or
(repeat(5, sig_759) and "10101") or
(repeat(5, sig_751) and "10110") or
(repeat(5, sig_750) and "00111") or
(repeat(5, sig_748) and "01011") or
(repeat(5, sig_744) and "01110") or
(repeat(5, sig_736) and "01100") or
(repeat(5, sig_883) and "00101") or
(repeat(5, sig_879) and "00010") or
(repeat(5, sig_875) and "00110") or
(repeat(5, sig_863) and "01010") or
(repeat(5, sig_828) and "10000") or
(repeat(5, sig_827) and "01111") or
(repeat(5, sig_886) and "01101") or
(repeat(5, sig_824) and "11011") or
(repeat(5, sig_807) and "00001") or
(repeat(5, sig_803) and "11111") or
(repeat(5, sig_861) and "00100") or
(repeat(5, sig_845) and "10111") or
(repeat(5, sig_831) and augh_main_k(5 downto 1)) or
(repeat(5, sig_860) and "10010") or
(repeat(5, sig_858) and "00011") or
(repeat(5, sig_854) and "01000") or
(repeat(5, sig_849) and "11101");
-- Behaviour of component 'mux_41' model 'mux'
mux_41 <=
(repeat(5, sig_857) and "01110") or
(repeat(5, sig_754) and "11010") or
(repeat(5, sig_742) and "10110") or
(repeat(5, sig_737) and "10010") or
(repeat(5, sig_770) and "11110");
-- Behaviour of component 'mux_42' model 'mux'
mux_42 <=
(sig_1053 and and_161) or
(sig_830 and sig_672) or
(sig_885 and '1');
-- Behaviour of component 'mux_43' model 'mux'
mux_43 <=
(repeat(5, sig_857) and "01111") or
(repeat(5, sig_826) and "00001") or
(repeat(5, sig_808) and "01011") or
(repeat(5, sig_768) and "11100") or
(repeat(5, sig_754) and "11000") or
(repeat(5, sig_836) and "00111") or
(repeat(5, sig_749) and "00101") or
(repeat(5, sig_728) and "00011") or
(repeat(5, sig_747) and "00110") or
(repeat(5, sig_742) and "10100") or
(repeat(5, sig_740) and "00010") or
(repeat(5, sig_737) and "10011");
-- Behaviour of component 'mux_44' model 'mux'
mux_44 <=
(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
(repeat(5, sig_902) and "10101") or
(repeat(5, sig_900) and "10001") or
(repeat(5, sig_898) and "01101") or
(repeat(5, sig_896) and "01001") or
(repeat(5, sig_895) and "00101") or
(repeat(5, sig_893) and "00001") or
(repeat(5, sig_856) and "01100") or
(repeat(5, sig_838) and "10100") or
(repeat(5, sig_837) and "00100") or
(repeat(5, sig_829) and "10000") or
(repeat(5, sig_821) and "01000") or
(repeat(5, sig_800) and "11000") or
(repeat(5, sig_958) and "11011") or
(repeat(5, sig_991) and "10111") or
(repeat(5, sig_987) and "10011") or
(repeat(5, sig_985) and "01111") or
(repeat(5, sig_938) and "01110") or
(repeat(5, sig_936) and "01010") or
(repeat(5, sig_935) and "00110") or
(repeat(5, sig_961) and "11111") or
(repeat(5, sig_933) and "00010") or
(repeat(5, sig_906) and "11101") or
(repeat(5, sig_904) and "11001") or
(repeat(5, sig_983) and "01011") or
(repeat(5, sig_942) and "10110") or
(repeat(5, sig_940) and "10010") or
(repeat(5, sig_982) and "00111") or
(repeat(5, sig_980) and "00011") or
(repeat(5, sig_946) and "11110") or
(repeat(5, sig_944) and "11010");
-- Behaviour of component 'mux_50' model 'mux'
mux_50 <=
(repeat(32, sig_1005) and cp_din(63 downto 32)) or
(repeat(32, sig_882) and sig_1111) or
(repeat(32, sig_877) and sig_1079) or
(repeat(32, sig_869) and sig_1149) or
(repeat(32, sig_847) and sig_1150) or
(repeat(32, sig_890) and (sig_1093(28 downto 0) & "000")) or
(repeat(32, sig_831) and read32_ret0_10) or
(repeat(32, sig_777) and (sig_1094(28 downto 0) & "000")) or
(repeat(32, sig_766) and (sig_1092(28 downto 0) & "000"));
-- Behaviour of component 'mux_51' model 'mux'
mux_51 <=
(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
(repeat(5, sig_796) and "10101") or
(repeat(5, sig_795) and "10110") or
(repeat(5, sig_793) and "11111") or
(repeat(5, sig_790) and "11101") or
(repeat(5, sig_779) and "11010") or
(repeat(5, sig_778) and "01011") or
(repeat(5, sig_775) and "11001") or
(repeat(5, sig_767) and "11100") or
(repeat(5, sig_765) and "01000") or
(repeat(5, sig_756) and "10000") or
(repeat(5, sig_753) and "10011") or
(repeat(5, sig_746) and "10010") or
(repeat(5, sig_745) and "01010") or
(repeat(5, sig_729) and "11110") or
(repeat(5, sig_881) and "00110") or
(repeat(5, sig_878) and "01111") or
(repeat(5, sig_876) and "00101") or
(repeat(5, sig_870) and "01100") or
(repeat(5, sig_817) and "10100") or
(repeat(5, sig_813) and "00010") or
(repeat(5, sig_812) and "00001") or
(repeat(5, sig_889) and "01001") or
(repeat(5, sig_809) and "00100") or
(repeat(5, sig_799) and "10001") or
(repeat(5, sig_798) and "11011") or
(repeat(5, sig_868) and "00011") or
(repeat(5, sig_831) and augh_main_k(5 downto 1)) or
(repeat(5, sig_819) and "10111") or
(repeat(5, sig_864) and "01101") or
(repeat(5, sig_855) and "01110") or
(repeat(5, sig_853) and "00111") or
(repeat(5, sig_846) and "11000");
-- Behaviour of component 'mux_52' model 'mux'
mux_52 <=
(sig_1053 and and_161) or
(sig_830 and sig_1064) or
(sig_888 and '1');
-- Behaviour of component 'mux_53' model 'mux'
mux_53 <=
(repeat(8, sig_1008) and mux_156) or
(repeat(8, sig_1003) and cp_din(7 downto 0));
-- Behaviour of component 'mux_54' model 'mux'
mux_54 <=
(repeat(3, sig_1007) and "111") or
(repeat(3, sig_1045) and "101") or
(repeat(3, sig_1043) and "100") or
(repeat(3, sig_1041) and "011") or
(repeat(3, sig_1037) and "010") or
(repeat(3, sig_1048) and "110") or
(repeat(3, sig_1035) and "001") or
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0));
-- Behaviour of component 'mux_55' model 'mux'
mux_55 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_56' model 'mux'
mux_56 <=
(sig_1006 and '1') or
(sig_1004 and and_161);
-- Behaviour of component 'mux_57' model 'mux'
mux_57 <=
(repeat(8, sig_1003) and cp_din(15 downto 8)) or
(repeat(8, sig_997) and mux_156);
-- Behaviour of component 'mux_88' model 'mux'
mux_88 <=
(sig_1004 and and_161) or
(sig_839 and '1');
-- Behaviour of component 'mux_67' model 'mux'
mux_67 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_68' model 'mux'
mux_68 <=
(sig_1004 and and_161) or
(sig_948 and '1');
-- Behaviour of component 'mux_69' model 'mux'
mux_69 <=
(repeat(32, sig_1026) and sig_1102) or
(repeat(32, sig_974) and or_244) or
(repeat(32, sig_947) and or_266) or
(repeat(32, sig_927) and or_285) or
(repeat(32, sig_907) and or_304) or
(repeat(32, sig_966) and or_221) or
(repeat(32, sig_802) and or_378) or
(repeat(32, sig_727) and or_371) or
(repeat(32, sig_723) and or_470);
-- Behaviour of component 'mux_71' model 'mux'
mux_71 <=
(repeat(32, sig_1026) and sig_1149) or
(repeat(32, sig_1018) and or_246) or
(repeat(32, sig_945) and or_268) or
(repeat(32, sig_925) and or_287) or
(repeat(32, sig_905) and or_306) or
(repeat(32, sig_957) and or_224) or
(repeat(32, sig_801) and or_433) or
(repeat(32, sig_789) and or_438) or
(repeat(32, sig_786) and or_450);
-- Behaviour of component 'mux_73' model 'mux'
mux_73 <=
(repeat(32, sig_1026) and sig_1124) or
(repeat(32, sig_1016) and or_248) or
(repeat(32, sig_943) and or_270) or
(repeat(32, sig_923) and or_289) or
(repeat(32, sig_903) and or_308) or
(repeat(32, sig_956) and or_228) or
(repeat(32, sig_840) and or_384) or
(repeat(32, sig_792) and or_435) or
(repeat(32, sig_774) and or_452);
-- Behaviour of component 'mux_75' model 'mux'
mux_75 <=
(repeat(32, sig_1026) and sig_1111) or
(repeat(32, sig_1014) and or_250) or
(repeat(32, sig_941) and or_272) or
(repeat(32, sig_921) and or_291) or
(repeat(32, sig_901) and or_310) or
(repeat(32, sig_990) and or_231) or
(repeat(32, sig_825) and or_417) or
(repeat(32, sig_805) and or_431) or
(repeat(32, sig_757) and or_497);
-- Behaviour of component 'mux_77' model 'mux'
mux_77 <=
(repeat(32, sig_1026) and sig_704) or
(repeat(32, sig_1012) and or_252) or
(repeat(32, sig_939) and or_274) or
(repeat(32, sig_919) and or_293) or
(repeat(32, sig_899) and or_312) or
(repeat(32, sig_986) and or_233) or
(repeat(32, sig_806) and or_363) or
(repeat(32, sig_783) and or_346) or
(repeat(32, sig_743) and or_358);
-- Behaviour of component 'mux_79' model 'mux'
mux_79 <=
(repeat(32, sig_1026) and sig_1079) or
(repeat(32, sig_1010) and or_256) or
(repeat(32, sig_937) and or_278) or
(repeat(32, sig_917) and or_297) or
(repeat(32, sig_897) and or_316) or
(repeat(32, sig_984) and or_237) or
(repeat(32, sig_822) and or_421) or
(repeat(32, sig_738) and or_333) or
(repeat(32, sig_726) and or_326);
-- Behaviour of component 'mux_81' model 'mux'
mux_81 <=
(repeat(32, sig_1026) and sig_1103) or
(repeat(32, sig_1057) and or_258) or
(repeat(32, sig_934) and or_280) or
(repeat(32, sig_914) and or_299) or
(repeat(32, sig_894) and or_318) or
(repeat(32, sig_981) and or_239) or
(repeat(32, sig_784) and or_386) or
(repeat(32, sig_734) and or_479) or
(repeat(32, sig_724) and or_587);
-- Behaviour of component 'mux_83' model 'mux'
mux_83 <=
(repeat(32, sig_1026) and sig_1150) or
(repeat(32, sig_1055) and or_260) or
(repeat(32, sig_932) and or_282) or
(repeat(32, sig_912) and or_301) or
(repeat(32, sig_892) and or_320) or
(repeat(32, sig_979) and or_241) or
(repeat(32, sig_820) and or_423) or
(repeat(32, sig_811) and or_425) or
(repeat(32, sig_722) and or_440);
-- Behaviour of component 'mux_85' model 'mux'
mux_85 <=
(repeat(8, sig_1003) and cp_din(63 downto 56)) or
(repeat(8, sig_841) and mux_156);
-- Behaviour of component 'mux_86' model 'mux'
mux_86 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_825) and "011") or
(repeat(3, sig_822) and "001") or
(repeat(3, sig_801) and "101") or
(repeat(3, sig_840) and "100") or
(repeat(3, sig_783) and "010") or
(repeat(3, sig_725) and "111") or
(repeat(3, sig_723) and "110");
-- Behaviour of component 'mux_87' model 'mux'
mux_87 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_28' model 'mux'
mux_28 <=
(sig_873 and cp_en);
-- Behaviour of component 'mux_109' model 'mux'
mux_109 <=
(repeat(32, sig_972) and sig_1119) or
(repeat(32, sig_836) and sig_677) or
(repeat(32, sig_808) and sig_669) or
(repeat(32, sig_770) and sig_660) or
(repeat(32, sig_754) and sig_645) or
(repeat(32, sig_857) and sig_683) or
(repeat(32, sig_742) and sig_634) or
(repeat(32, sig_737) and sig_624) or
(repeat(32, sig_728) and sig_609);
-- Behaviour of component 'mux_154' model 'mux'
mux_154 <=
(sig_952 and sig_699);
-- Behaviour of component 'mux_156' model 'mux'
mux_156 <=
(repeat(8, sig_1130) and mux_158);
-- Behaviour of component 'mux_89' model 'mux'
mux_89 <=
(repeat(8, sig_1003) and cp_din(55 downto 48)) or
(repeat(8, sig_816) and mux_156);
-- Behaviour of component 'mux_90' model 'mux'
mux_90 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_806) and "010") or
(repeat(3, sig_805) and "011") or
(repeat(3, sig_792) and "100") or
(repeat(3, sig_786) and "101") or
(repeat(3, sig_815) and "111") or
(repeat(3, sig_727) and "110") or
(repeat(3, sig_726) and "001");
-- Behaviour of component 'mux_134' model 'mux'
mux_134 <=
(sig_873 and cp_en) or
(sig_832 and '1');
-- Behaviour of component 'mux_91' model 'mux'
mux_91 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_92' model 'mux'
mux_92 <=
(sig_1004 and and_161) or
(sig_814 and '1');
-- Behaviour of component 'mux_158' model 'mux'
mux_158 <=
(repeat(8, sig_1157) and "11111111") or
(repeat(8, sig_1106) and idct_2d_r(7 downto 0));
-- Behaviour of component 'mux_111' model 'mux'
mux_111 <=
(repeat(32, sig_960) and (sig_1132 & '0')) or
(repeat(32, sig_770) and (sig_659 & '0')) or
(repeat(32, sig_754) and (sig_644 & '0')) or
(repeat(32, sig_747) and (sig_640 & '0')) or
(repeat(32, sig_742) and (sig_632 & '0')) or
(repeat(32, sig_857) and (sig_1076 & '0')) or
(repeat(32, sig_740) and (sig_631 & '0')) or
(repeat(32, sig_737) and (sig_621 & '0')) or
(repeat(32, sig_721) and (sig_606 & '0'));
-- Behaviour of component 'mux_113' model 'mux'
mux_113 <=
(repeat(32, sig_989) and (sig_1112 & '0')) or
(repeat(32, sig_843) and (sig_678 & '0')) or
(repeat(32, sig_826) and (sig_671 & '0')) or
(repeat(32, sig_772) and (sig_712 & '0')) or
(repeat(32, sig_770) and (sig_661 & '0')) or
(repeat(32, sig_857) and (sig_682 & '0')) or
(repeat(32, sig_754) and (sig_646 & '0')) or
(repeat(32, sig_749) and (sig_641 & '0')) or
(repeat(32, sig_742) and (sig_635 & '0')) or
(repeat(32, sig_737) and (sig_623 & '0'));
-- Behaviour of component 'mux_115' model 'mux'
mux_115 <=
(repeat(32, sig_972) and sig_1142) or
(repeat(32, sig_836) and sig_676) or
(repeat(32, sig_808) and sig_1063) or
(repeat(32, sig_770) and sig_658) or
(repeat(32, sig_754) and sig_709) or
(repeat(32, sig_857) and sig_681) or
(repeat(32, sig_742) and sig_633) or
(repeat(32, sig_737) and sig_622) or
(repeat(32, sig_728) and sig_610);
-- Behaviour of component 'mux_117' model 'mux'
mux_117 <=
(repeat(32, sig_965) and sig_1136) or
(repeat(32, sig_843) and sig_1071) or
(repeat(32, sig_787) and sig_713) or
(repeat(32, sig_770) and sig_710) or
(repeat(32, sig_754) and sig_648) or
(repeat(32, sig_857) and sig_684) or
(repeat(32, sig_742) and sig_636) or
(repeat(32, sig_737) and sig_625) or
(repeat(32, sig_730) and sig_614);
-- Behaviour of component 'mux_119' model 'mux'
mux_119 <=
(repeat(32, sig_963) and sig_1133) or
(repeat(32, sig_851) and sig_1073) or
(repeat(32, sig_787) and sig_663) or
(repeat(32, sig_761) and sig_1061) or
(repeat(32, sig_752) and sig_1059) or
(repeat(32, sig_867) and sig_1078) or
(repeat(32, sig_739) and sig_629) or
(repeat(32, sig_735) and sig_619) or
(repeat(32, sig_730) and sig_611);
-- Behaviour of component 'mux_121' model 'mux'
mux_121 <=
(repeat(32, sig_993) and sig_1131) or
(repeat(32, sig_851) and sig_716) or
(repeat(32, sig_764) and sig_656) or
(repeat(32, sig_762) and sig_654) or
(repeat(32, sig_761) and sig_653) or
(repeat(32, sig_867) and sig_687) or
(repeat(32, sig_752) and sig_1060) or
(repeat(32, sig_739) and sig_628) or
(repeat(32, sig_735) and sig_618);
-- Behaviour of component 'mux_123' model 'mux'
mux_123 <=
(repeat(32, sig_955) and sig_1109) or
(repeat(32, sig_843) and sig_679) or
(repeat(32, sig_770) and sig_1062) or
(repeat(32, sig_764) and sig_657) or
(repeat(32, sig_762) and sig_655) or
(repeat(32, sig_857) and sig_686) or
(repeat(32, sig_754) and sig_647) or
(repeat(32, sig_742) and sig_639) or
(repeat(32, sig_737) and sig_627);
-- Behaviour of component 'or_224' model 'or'
or_224 <=
and_225;
-- Behaviour of component 'and_225' model 'and'
and_225 <=
sig_1084;
-- Behaviour of component 'or_231' model 'or'
or_231 <=
and_232;
-- Behaviour of component 'and_232' model 'and'
and_232 <=
sig_1084;
-- Behaviour of component 'or_250' model 'or'
or_250 <=
and_251;
-- Behaviour of component 'and_251' model 'and'
and_251 <=
sig_1093;
-- Behaviour of component 'or_260' model 'or'
or_260 <=
and_261;
-- Behaviour of component 'and_261' model 'and'
and_261 <=
sig_1093;
-- Behaviour of component 'or_282' model 'or'
or_282 <=
and_283;
-- Behaviour of component 'and_283' model 'and'
and_283 <=
sig_1084;
-- Behaviour of component 'or_285' model 'or'
or_285 <=
and_286;
-- Behaviour of component 'and_286' model 'and'
and_286 <=
sig_1093;
-- Behaviour of component 'or_289' model 'or'
or_289 <=
and_290;
-- Behaviour of component 'and_290' model 'and'
and_290 <=
sig_1093;
-- Behaviour of component 'or_291' model 'or'
or_291 <=
and_292;
-- Behaviour of component 'and_292' model 'and'
and_292 <=
sig_1093;
-- Behaviour of component 'or_297' model 'or'
or_297 <=
and_298;
-- Behaviour of component 'and_298' model 'and'
and_298 <=
sig_1093;
-- Behaviour of component 'or_299' model 'or'
or_299 <=
and_300;
-- Behaviour of component 'and_300' model 'and'
and_300 <=
sig_1093;
-- Behaviour of component 'or_320' model 'or'
or_320 <=
and_321;
-- Behaviour of component 'and_321' model 'and'
and_321 <=
sig_1084;
-- Behaviour of component 'or_326' model 'or'
or_326 <=
and_327;
-- Behaviour of component 'and_327' model 'and'
and_327 <=
sig_1093;
-- Behaviour of component 'or_333' model 'or'
or_333 <=
and_334;
-- Behaviour of component 'and_334' model 'and'
and_334 <=
sig_1092;
-- Behaviour of component 'or_363' model 'or'
or_363 <=
and_364;
-- Behaviour of component 'and_364' model 'and'
and_364 <=
sig_1092;
-- Behaviour of component 'and_403' model 'and'
and_403 <=
sig_1158 and
repeat(8, sig_1068);
-- Behaviour of component 'and_405' model 'and'
and_405 <=
sig_1159 and
repeat(8, sig_1067);
-- Behaviour of component 'and_407' model 'and'
and_407 <=
sig_1154 and
repeat(8, sig_1066);
-- Behaviour of component 'and_409' model 'and'
and_409 <=
sig_1153 and
repeat(8, sig_1065);
-- Behaviour of component 'and_415' model 'and'
and_415 <=
sig_1085(30 downto 0);
-- Behaviour of component 'or_464' model 'or'
or_464 <=
and_465;
-- Behaviour of component 'and_465' model 'and'
and_465 <=
sig_1095;
-- Behaviour of component 'or_470' model 'or'
or_470 <=
and_471;
-- Behaviour of component 'and_471' model 'and'
and_471 <=
sig_1085;
-- Behaviour of component 'or_472' model 'or'
or_472 <=
and_473;
-- Behaviour of component 'and_473' model 'and'
and_473 <=
sig_1083;
-- Behaviour of component 'or_500' model 'or'
or_500 <=
and_501;
-- Behaviour of component 'and_501' model 'and'
and_501 <=
sig_1094;
-- Behaviour of component 'or_504' model 'or'
or_504 <=
and_505;
-- Behaviour of component 'and_505' model 'and'
and_505 <=
sig_1092;
-- Behaviour of component 'or_506' model 'or'
or_506 <=
and_507;
-- Behaviour of component 'and_507' model 'and'
and_507 <=
sig_1095;
-- Behaviour of component 'or_514' model 'or'
or_514 <=
and_515;
-- Behaviour of component 'and_515' model 'and'
and_515 <=
sig_1083;
-- Behaviour of component 'or_522' model 'or'
or_522 <=
and_523;
-- Behaviour of component 'and_523' model 'and'
and_523 <=
sig_1094;
-- Behaviour of component 'mux_129' model 'mux'
mux_129 <=
(repeat(32, sig_1021) and sig_1114) or
(repeat(32, sig_1054) and sig_1100) or
(repeat(32, sig_931) and sig_1087) or
(repeat(32, sig_911) and sig_694) or
(repeat(32, sig_848) and sig_1072) or
(repeat(32, sig_978) and sig_1101) or
(repeat(32, sig_791) and sig_668) or
(repeat(32, sig_732) and sig_617);
-- Behaviour of component 'mux_133' model 'mux'
mux_133 <=
(repeat(8, sig_874) and cp_din(39 downto 32)) or
(repeat(8, sig_833) and or_394);
-- Behaviour of component 'mux_135' model 'mux'
mux_135 <=
(repeat(32, sig_1047) and (repeat(5, sig_1082(19)) & sig_1082 & sig_1155(7 downto 1))) or
(repeat(32, sig_1042) and (repeat(5, sig_1127(19)) & sig_1127 & sig_719(7 downto 1))) or
(repeat(32, sig_1040) and (repeat(5, sig_1152(19)) & sig_1152 & sig_1118(7 downto 1))) or
(repeat(32, sig_1036) and (repeat(5, sig_1126(19)) & sig_1126 & sig_1104(7 downto 1))) or
(repeat(32, sig_1035) and (repeat(5, sig_1151(19)) & sig_1151 & sig_718(7 downto 1))) or
(repeat(32, sig_822) and (repeat(5, sig_714(19)) & sig_714 & sig_670(7 downto 1))) or
(repeat(32, sig_726) and (repeat(5, sig_607(19)) & sig_607 & sig_608(7 downto 1))) or
(repeat(32, sig_1044) and (repeat(5, sig_1081(19)) & sig_1081 & sig_720(7 downto 1))) or
(repeat(32, sig_1034) and (repeat(5, sig_1080(19)) & sig_1080 & sig_1117(7 downto 1))) or
(repeat(32, sig_917) and (repeat(5, sig_695(19)) & sig_695 & sig_696(7 downto 1))) or
(repeat(32, sig_897) and (repeat(5, sig_693(19)) & sig_693 & sig_1107(7 downto 1))) or
(repeat(32, sig_1033) and (repeat(5, sig_1125(19)) & sig_1125 & sig_1116(7 downto 1))) or
(repeat(32, sig_984) and (repeat(5, sig_700(19)) & sig_700 & sig_1108(7 downto 1))) or
(repeat(32, sig_1010) and (repeat(5, sig_717(19)) & sig_717 & sig_1089(7 downto 1))) or
(repeat(32, sig_937) and (repeat(5, sig_697(19)) & sig_697 & sig_1088(7 downto 1)));
-- Behaviour of component 'mux_137' model 'mux'
mux_137 <=
(repeat(8, sig_1003) and cp_din(39 downto 32)) or
(repeat(8, sig_930) and mux_156);
-- Behaviour of component 'mux_138' model 'mux'
mux_138 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_927) and "110") or
(repeat(3, sig_925) and "101") or
(repeat(3, sig_923) and "100") or
(repeat(3, sig_921) and "011") or
(repeat(3, sig_929) and "111") or
(repeat(3, sig_919) and "010") or
(repeat(3, sig_917) and "001");
-- Behaviour of component 'mux_139' model 'mux'
mux_139 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_140' model 'mux'
mux_140 <=
(sig_1004 and and_161) or
(sig_928 and '1');
-- Behaviour of component 'mux_141' model 'mux'
mux_141 <=
(repeat(8, sig_1003) and cp_din(47 downto 40)) or
(repeat(8, sig_910) and mux_156);
-- Behaviour of component 'mux_142' model 'mux'
mux_142 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_907) and "110") or
(repeat(3, sig_905) and "101") or
(repeat(3, sig_903) and "100") or
(repeat(3, sig_901) and "011") or
(repeat(3, sig_909) and "111") or
(repeat(3, sig_899) and "010") or
(repeat(3, sig_897) and "001");
-- Behaviour of component 'mux_143' model 'mux'
mux_143 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_144' model 'mux'
mux_144 <=
(sig_1004 and and_161) or
(sig_908 and '1');
-- Behaviour of component 'mux_147' model 'mux'
mux_147 <=
(sig_951 and not_264);
-- Behaviour of component 'mux_149' model 'mux'
mux_149 <=
(repeat(32, sig_874) and cp_din(31 downto 0)) or
(repeat(32, sig_835) and sig_675);
-- Behaviour of component 'mux_150' model 'mux'
mux_150 <=
(sig_873 and cp_en) or
(sig_834 and '1');
-- Behaviour of component 'mux_151' model 'mux'
mux_151 <=
(sig_1005 and sig_705) or
(sig_1003 and sig_703) or
(sig_874 and sig_692) or
(sig_1050 and '1');
-- Behaviour of component 'mux_152' model 'mux'
mux_152 <=
(repeat(64, sig_1005) and (sig_1093 & sig_1084)) or
(repeat(64, sig_874) and (psc_stuff_reg_19 & cp_id_reg_14)) or
(repeat(64, sig_1003) and (sig_1153 & sig_1154 & sig_1159 & sig_1158 & sig_1099 & sig_1098 & sig_1097 & sig_1096));
-- Behaviour of component 'mux_155' model 'mux'
mux_155 <=
(sig_951 and sig_698);
-- Behaviour of component 'or_221' model 'or'
or_221 <=
and_222;
-- Behaviour of component 'and_222' model 'and'
and_222 <=
sig_1084;
-- Behaviour of component 'or_233' model 'or'
or_233 <=
and_234;
-- Behaviour of component 'and_234' model 'and'
and_234 <=
sig_1084;
-- Behaviour of component 'or_237' model 'or'
or_237 <=
and_238;
-- Behaviour of component 'and_238' model 'and'
and_238 <=
sig_1084;
-- Behaviour of component 'or_252' model 'or'
or_252 <=
and_253;
-- Behaviour of component 'and_253' model 'and'
and_253 <=
sig_1093;
-- Behaviour of component 'or_256' model 'or'
or_256 <=
and_257;
-- Behaviour of component 'and_257' model 'and'
and_257 <=
sig_1093;
-- Behaviour of component 'or_268' model 'or'
or_268 <=
and_269;
-- Behaviour of component 'and_269' model 'and'
and_269 <=
sig_1084;
-- Behaviour of component 'or_270' model 'or'
or_270 <=
and_271;
-- Behaviour of component 'and_271' model 'and'
and_271 <=
sig_1084;
-- Behaviour of component 'or_274' model 'or'
or_274 <=
and_275;
-- Behaviour of component 'and_275' model 'and'
and_275 <=
sig_1084;
-- Behaviour of component 'or_278' model 'or'
or_278 <=
and_279;
-- Behaviour of component 'and_279' model 'and'
and_279 <=
sig_1084;
-- Behaviour of component 'or_310' model 'or'
or_310 <=
and_311;
-- Behaviour of component 'and_311' model 'and'
and_311 <=
sig_1084;
-- Behaviour of component 'or_316' model 'or'
or_316 <=
and_317;
-- Behaviour of component 'and_317' model 'and'
and_317 <=
sig_1084;
-- Behaviour of component 'or_358' model 'or'
or_358 <=
and_359;
-- Behaviour of component 'and_359' model 'and'
and_359 <=
sig_1093;
-- Behaviour of component 'or_366' model 'or'
or_366 <=
and_367;
-- Behaviour of component 'and_367' model 'and'
and_367 <=
sig_1095;
-- Behaviour of component 'or_374' model 'or'
or_374 <=
and_375;
-- Behaviour of component 'and_375' model 'and'
and_375 <=
sig_1094;
-- Behaviour of component 'or_417' model 'or'
or_417 <=
and_418;
-- Behaviour of component 'and_418' model 'and'
and_418 <=
sig_1084;
-- Behaviour of component 'or_421' model 'or'
or_421 <=
and_422;
-- Behaviour of component 'and_422' model 'and'
and_422 <=
sig_1084;
-- Behaviour of component 'or_435' model 'or'
or_435 <=
and_436;
-- Behaviour of component 'and_436' model 'and'
and_436 <=
sig_1093;
-- Behaviour of component 'or_452' model 'or'
or_452 <=
and_453;
-- Behaviour of component 'and_453' model 'and'
and_453 <=
sig_1093;
-- Behaviour of component 'and_494' model 'and'
and_494 <=
sig_1095;
-- Behaviour of component 'and_498' model 'and'
and_498 <=
sig_1093;
-- Behaviour of component 'or_509' model 'or'
or_509 <=
and_510;
-- Behaviour of component 'and_510' model 'and'
and_510 <=
sig_1084(30 downto 0);
-- Behaviour of component 'or_550' model 'or'
or_550 <=
and_551;
-- Behaviour of component 'and_551' model 'and'
and_551 <=
sig_1083;
-- Behaviour of component 'or_581' model 'or'
or_581 <=
and_582;
-- Behaviour of component 'and_582' model 'and'
and_582 <=
sig_1094;
-- Behaviour of component 'or_583' model 'or'
or_583 <=
and_584;
-- Behaviour of component 'and_584' model 'and'
and_584 <=
sig_1092;
-- Behaviour of component 'or_587' model 'or'
or_587 <=
and_588;
-- Behaviour of component 'and_588' model 'and'
and_588 <=
sig_1093;
-- Behaviour of component 'and_161' model 'and'
and_161 <=
cp_en and
cp_rest;
-- Behaviour of component 'or_228' model 'or'
or_228 <=
and_229;
-- Behaviour of component 'and_229' model 'and'
and_229 <=
sig_1084;
-- Behaviour of component 'or_239' model 'or'
or_239 <=
and_240;
-- Behaviour of component 'and_240' model 'and'
and_240 <=
sig_1084;
-- Behaviour of component 'or_241' model 'or'
or_241 <=
and_242;
-- Behaviour of component 'and_242' model 'and'
and_242 <=
sig_1084;
-- Behaviour of component 'or_244' model 'or'
or_244 <=
and_245;
-- Behaviour of component 'and_245' model 'and'
and_245 <=
sig_1093;
-- Behaviour of component 'or_246' model 'or'
or_246 <=
and_247;
-- Behaviour of component 'and_247' model 'and'
and_247 <=
sig_1093;
-- Behaviour of component 'or_248' model 'or'
or_248 <=
and_249;
-- Behaviour of component 'and_249' model 'and'
and_249 <=
sig_1093;
-- Behaviour of component 'or_258' model 'or'
or_258 <=
and_259;
-- Behaviour of component 'and_259' model 'and'
and_259 <=
sig_1093;
-- Behaviour of component 'not_264' model 'not'
not_264 <= not (
cp_en
);
-- Behaviour of component 'or_266' model 'or'
or_266 <=
and_267;
-- Behaviour of component 'and_267' model 'and'
and_267 <=
sig_1084;
-- Behaviour of component 'or_272' model 'or'
or_272 <=
and_273;
-- Behaviour of component 'and_273' model 'and'
and_273 <=
sig_1084;
-- Behaviour of component 'or_280' model 'or'
or_280 <=
and_281;
-- Behaviour of component 'and_281' model 'and'
and_281 <=
sig_1084;
-- Behaviour of component 'or_287' model 'or'
or_287 <=
and_288;
-- Behaviour of component 'and_288' model 'and'
and_288 <=
sig_1093;
-- Behaviour of component 'or_293' model 'or'
or_293 <=
and_294;
-- Behaviour of component 'and_294' model 'and'
and_294 <=
sig_1093;
-- Behaviour of component 'or_301' model 'or'
or_301 <=
and_302;
-- Behaviour of component 'and_302' model 'and'
and_302 <=
sig_1093;
-- Behaviour of component 'or_304' model 'or'
or_304 <=
and_305;
-- Behaviour of component 'and_305' model 'and'
and_305 <=
sig_1084;
-- Behaviour of component 'or_306' model 'or'
or_306 <=
and_307;
-- Behaviour of component 'and_307' model 'and'
and_307 <=
sig_1084;
-- Behaviour of component 'or_308' model 'or'
or_308 <=
and_309;
-- Behaviour of component 'and_309' model 'and'
and_309 <=
sig_1084;
-- Behaviour of component 'or_312' model 'or'
or_312 <=
and_313;
-- Behaviour of component 'and_313' model 'and'
and_313 <=
sig_1084;
-- Behaviour of component 'or_318' model 'or'
or_318 <=
and_319;
-- Behaviour of component 'and_319' model 'and'
and_319 <=
sig_1084;
-- Behaviour of component 'or_329' model 'or'
or_329 <=
and_330;
-- Behaviour of component 'and_330' model 'and'
and_330 <=
sig_1094;
-- Behaviour of component 'or_335' model 'or'
or_335 <=
and_336;
-- Behaviour of component 'and_336' model 'and'
and_336 <=
sig_1095;
-- Behaviour of component 'or_339' model 'or'
or_339 <=
and_340;
-- Behaviour of component 'and_340' model 'and'
and_340 <=
sig_1094;
-- Behaviour of component 'or_342' model 'or'
or_342 <=
and_343;
-- Behaviour of component 'and_343' model 'and'
and_343 <=
sig_1095;
-- Behaviour of component 'or_346' model 'or'
or_346 <=
and_347;
-- Behaviour of component 'and_347' model 'and'
and_347 <=
sig_1084;
-- Behaviour of component 'or_348' model 'or'
or_348 <=
and_349;
-- Behaviour of component 'and_349' model 'and'
and_349 <=
sig_1085;
-- Behaviour of component 'or_351' model 'or'
or_351 <=
and_352;
-- Behaviour of component 'and_352' model 'and'
and_352 <=
sig_1083(30 downto 0);
-- Behaviour of component 'or_355' model 'or'
or_355 <=
and_356;
-- Behaviour of component 'and_356' model 'and'
and_356 <=
sig_1086(30 downto 0);
-- Behaviour of component 'or_360' model 'or'
or_360 <=
and_361;
-- Behaviour of component 'and_361' model 'and'
and_361 <=
sig_1094;
-- Behaviour of component 'or_371' model 'or'
or_371 <=
and_372;
-- Behaviour of component 'and_372' model 'and'
and_372 <=
sig_1093;
-- Behaviour of component 'or_378' model 'or'
or_378 <=
and_379;
-- Behaviour of component 'and_379' model 'and'
and_379 <=
sig_1092;
-- Behaviour of component 'or_380' model 'or'
or_380 <=
and_381;
-- Behaviour of component 'and_381' model 'and'
and_381 <=
sig_1095;
-- Behaviour of component 'or_384' model 'or'
or_384 <=
and_385;
-- Behaviour of component 'and_385' model 'and'
and_385 <=
sig_1084;
-- Behaviour of component 'or_386' model 'or'
or_386 <=
and_387;
-- Behaviour of component 'and_387' model 'and'
and_387 <=
sig_1084;
-- Behaviour of component 'or_388' model 'or'
or_388 <=
and_389;
-- Behaviour of component 'and_389' model 'and'
and_389 <=
sig_1085;
-- Behaviour of component 'or_394' model 'or'
or_394 <=
and_395 or
and_399 or
and_401 or
and_403 or
and_405 or
and_397 or
and_407 or
and_409;
-- Behaviour of component 'and_395' model 'and'
and_395 <=
sig_1096 and
repeat(8, sig_674);
-- Behaviour of component 'and_397' model 'and'
and_397 <=
sig_1097 and
repeat(8, sig_1070);
-- Behaviour of component 'and_399' model 'and'
and_399 <=
sig_1098 and
repeat(8, sig_1069);
-- Behaviour of component 'and_401' model 'and'
and_401 <=
sig_1099 and
repeat(8, sig_673);
-- Behaviour of component 'or_414' model 'or'
or_414 <=
and_415;
-- Behaviour of component 'or_423' model 'or'
or_423 <=
and_424;
-- Behaviour of component 'and_424' model 'and'
and_424 <=
sig_1084;
-- Behaviour of component 'or_425' model 'or'
or_425 <=
and_426;
-- Behaviour of component 'and_426' model 'and'
and_426 <=
sig_1093;
-- Behaviour of component 'or_427' model 'or'
or_427 <=
and_428;
-- Behaviour of component 'and_428' model 'and'
and_428 <=
sig_1085;
-- Behaviour of component 'or_431' model 'or'
or_431 <=
and_432;
-- Behaviour of component 'and_432' model 'and'
and_432 <=
sig_1093;
-- Behaviour of component 'or_433' model 'or'
or_433 <=
and_434;
-- Behaviour of component 'and_434' model 'and'
and_434 <=
sig_1084;
-- Behaviour of component 'or_438' model 'or'
or_438 <=
and_439;
-- Behaviour of component 'and_439' model 'and'
and_439 <=
sig_1093;
-- Behaviour of component 'or_440' model 'or'
or_440 <=
and_441;
-- Behaviour of component 'and_441' model 'and'
and_441 <=
sig_1094;
-- Behaviour of component 'or_443' model 'or'
or_443 <=
and_444;
-- Behaviour of component 'and_444' model 'and'
and_444 <=
sig_1092;
-- Behaviour of component 'or_450' model 'or'
or_450 <=
and_451;
-- Behaviour of component 'and_451' model 'and'
and_451 <=
sig_1093;
-- Behaviour of component 'or_454' model 'or'
or_454 <=
and_455;
-- Behaviour of component 'and_455' model 'and'
and_455 <=
sig_1084(30 downto 0);
-- Behaviour of component 'or_458' model 'or'
or_458 <=
and_459;
-- Behaviour of component 'and_459' model 'and'
and_459 <=
sig_1094;
-- Behaviour of component 'or_462' model 'or'
or_462 <=
and_463;
-- Behaviour of component 'and_463' model 'and'
and_463 <=
sig_1092;
-- Behaviour of component 'or_467' model 'or'
or_467 <=
and_468;
-- Behaviour of component 'and_468' model 'and'
and_468 <=
sig_1084(30 downto 0);
-- Behaviour of component 'or_475' model 'or'
or_475 <=
and_476;
-- Behaviour of component 'and_476' model 'and'
and_476 <=
sig_1086(30 downto 0);
-- Behaviour of component 'or_479' model 'or'
or_479 <=
and_480;
-- Behaviour of component 'and_480' model 'and'
and_480 <=
sig_1093;
-- Behaviour of component 'or_481' model 'or'
or_481 <=
and_482;
-- Behaviour of component 'and_482' model 'and'
and_482 <=
sig_1094;
-- Behaviour of component 'or_485' model 'or'
or_485 <=
and_486;
-- Behaviour of component 'and_486' model 'and'
and_486 <=
sig_1094;
-- Behaviour of component 'or_490' model 'or'
or_490 <=
and_491;
-- Behaviour of component 'and_491' model 'and'
and_491 <=
sig_1094;
-- Behaviour of component 'or_493' model 'or'
or_493 <=
and_494;
-- Behaviour of component 'or_497' model 'or'
or_497 <=
and_498;
-- Behaviour of component 'or_512' model 'or'
or_512 <=
and_513;
-- Behaviour of component 'and_513' model 'and'
and_513 <=
sig_1085;
-- Behaviour of component 'or_518' model 'or'
or_518 <=
and_519;
-- Behaviour of component 'and_519' model 'and'
and_519 <=
sig_1086(30 downto 0);
-- Behaviour of component 'or_525' model 'or'
or_525 <=
and_526;
-- Behaviour of component 'and_526' model 'and'
and_526 <=
sig_1092;
-- Behaviour of component 'or_529' model 'or'
or_529 <=
and_530;
-- Behaviour of component 'and_530' model 'and'
and_530 <=
sig_1085(30 downto 0);
-- Behaviour of component 'or_532' model 'or'
or_532 <=
and_533;
-- Behaviour of component 'and_533' model 'and'
and_533 <=
sig_1085(30 downto 0);
-- Behaviour of component 'or_535' model 'or'
or_535 <=
and_536;
-- Behaviour of component 'and_536' model 'and'
and_536 <=
sig_1094;
-- Behaviour of component 'or_538' model 'or'
or_538 <=
and_539;
-- Behaviour of component 'and_539' model 'and'
and_539 <=
sig_1092;
-- Behaviour of component 'or_541' model 'or'
or_541 <=
and_542;
-- Behaviour of component 'and_542' model 'and'
and_542 <=
sig_1095;
-- Behaviour of component 'or_545' model 'or'
or_545 <=
and_546;
-- Behaviour of component 'and_546' model 'and'
and_546 <=
sig_1084(30 downto 0);
-- Behaviour of component 'or_548' model 'or'
or_548 <=
and_549;
-- Behaviour of component 'and_549' model 'and'
and_549 <=
sig_1085;
-- Behaviour of component 'or_554' model 'or'
or_554 <=
and_555;
-- Behaviour of component 'and_555' model 'and'
and_555 <=
sig_1086(30 downto 0);
-- Behaviour of component 'or_557' model 'or'
or_557 <=
and_558;
-- Behaviour of component 'and_558' model 'and'
and_558 <=
sig_1085(30 downto 0);
-- Behaviour of component 'or_568' model 'or'
or_568 <=
and_569;
-- Behaviour of component 'and_569' model 'and'
and_569 <=
sig_1085;
-- Behaviour of component 'or_571' model 'or'
or_571 <=
and_572;
-- Behaviour of component 'and_572' model 'and'
and_572 <=
sig_1083(30 downto 0);
-- Behaviour of component 'or_575' model 'or'
or_575 <=
and_576;
-- Behaviour of component 'and_576' model 'and'
and_576 <=
sig_1086(30 downto 0);
-- Behaviour of component 'or_590' model 'or'
or_590 <=
and_591;
-- Behaviour of component 'and_591' model 'and'
and_591 <=
sig_1094;
-- Behaviour of component 'or_597' model 'or'
or_597 <=
and_598;
-- Behaviour of component 'and_598' model 'and'
and_598 <=
sig_1085;
-- Behaviour of component 'or_603' model 'or'
or_603 <=
and_604;
-- Behaviour of component 'and_604' model 'and'
and_604 <=
sig_1084(30 downto 0);
-- Behaviour of all components of model 'reg'
-- Registers with clock = sig_clock and reset = sig_reset active '1'
process(sig_clock, sig_reset)
begin
if sig_reset = '1' then
psc_stuff_reg_19 <= "000000000000000000000000000000000000000000000000000000000000000";
else
if rising_edge(sig_clock) then
if mux_28 = '1' then
psc_stuff_reg_19 <= psc_stuff_reg_18 & write8_u8 & augh_main_k(31 downto 1);
end if;
end if;
end if;
end process;
-- Registers with clock = sig_clock and no reset
process(sig_clock)
begin
if rising_edge(sig_clock) then
if mux_30 = '1' then
psc_stuff_reg_18 <= cp_din(63 downto 40);
end if;
if mux_34 = '1' then
cp_id_reg_stable_15 <= mux_33;
end if;
if mux_36 = '1' then
cp_id_reg_14 <= mux_35;
end if;
if mux_38 = '1' then
psc_loop_reg_13 <= mux_37;
end if;
if sig_1024 = '1' then
idct_2d_yc_reg7 <= mux_69;
end if;
if sig_1025 = '1' then
idct_2d_yc_reg6 <= mux_71;
end if;
if sig_1027 = '1' then
idct_2d_yc_reg5 <= mux_73;
end if;
if sig_1028 = '1' then
idct_2d_yc_reg4 <= mux_75;
end if;
if sig_1029 = '1' then
idct_2d_yc_reg3 <= mux_77;
end if;
if sig_1030 = '1' then
idct_2d_yc_reg2 <= mux_79;
end if;
if sig_1031 = '1' then
idct_2d_yc_reg1 <= mux_81;
end if;
if sig_1032 = '1' then
idct_2d_yc_reg0 <= mux_83;
end if;
if sig_1001 = '1' then
idct_z2_reg7 <= sig_1090;
end if;
if sig_998 = '1' then
idct_z2_reg6 <= sig_701;
end if;
if sig_999 = '1' then
idct_z2_reg5 <= sig_1113;
end if;
if sig_1000 = '1' then
idct_z2_reg4 <= sig_1120;
end if;
if sig_967 = '1' then
idct_z2_reg3 <= sig_1139;
end if;
if sig_968 = '1' then
idct_z2_reg2 <= sig_1140;
end if;
if sig_969 = '1' then
idct_z2_reg1 <= sig_1141;
end if;
if sig_970 = '1' then
idct_z2_reg0 <= sig_1110;
end if;
if sig_971 = '1' then
idct_z1_reg7 <= mux_109;
end if;
if sig_959 = '1' then
idct_z1_reg6 <= mux_111;
end if;
if sig_988 = '1' then
idct_z1_reg5 <= mux_113;
end if;
if sig_971 = '1' then
idct_z1_reg4 <= mux_115;
end if;
if sig_964 = '1' then
idct_z1_reg3 <= mux_117;
end if;
if sig_962 = '1' then
idct_z1_reg2 <= mux_119;
end if;
if sig_992 = '1' then
idct_z1_reg1 <= mux_121;
end if;
if sig_994 = '1' then
idct_z1_reg0 <= mux_123;
end if;
if sig_1023 = '1' then
idct_z3_reg7 <= sig_1147 & idct_z2_reg7(0);
end if;
if sig_1022 = '1' then
idct_z3_reg6 <= sig_1091 & idct_z2_reg6(1 downto 0);
end if;
if sig_1020 = '1' then
idct_z3_reg5 <= mux_129;
end if;
if sig_1019 = '1' then
idct_z3_reg4 <= sig_1121;
end if;
if mux_134 = '1' then
write8_u8 <= mux_133;
end if;
if sig_1046 = '1' then
idct_2d_r <= mux_135;
end if;
if mux_147 = '1' then
read32_ret0_10 <= stdin_data;
end if;
if mux_150 = '1' then
augh_main_k <= mux_149;
end if;
end if;
end process;
-- Remaining signal assignments
-- Those who are not assigned by component instantiation
sig_clock <= clock;
sig_reset <= reset;
sig_start <= start;
test_cp_0_16 <= mux_32;
sig_1160 <= sig_608(26) & sig_608(26 downto 8);
sig_1161 <= sig_1122 & "00";
sig_1162 <= sig_1122 & "00";
sig_1163 <= sig_1107(26) & sig_1107(26 downto 8);
sig_1164 <= sig_1122 & "00";
sig_1165 <= sig_696(26) & sig_696(26 downto 8);
sig_1166 <= sig_1088(26) & sig_1088(26 downto 8);
sig_1167 <= sig_1108(26) & sig_1108(26 downto 8);
sig_1168 <= sig_670(26) & sig_670(26 downto 8);
sig_1169 <= sig_1089(26) & sig_1089(26 downto 8);
sig_1170 <= sig_1122 & "00";
sig_1171 <= sig_1117(26) & sig_1117(26 downto 8);
sig_1172 <= sig_720(26) & sig_720(26 downto 8);
sig_1173 <= sig_1155(26) & sig_1155(26 downto 8);
sig_1174 <= sig_1122 & "00";
sig_1175 <= sig_1122 & "00";
sig_1176 <= sig_1122 & "00";
sig_1177 <= sig_1122 & "00";
sig_1178 <= sig_1143 & '0';
sig_1179 <= sig_1116(26) & sig_1116(26 downto 8);
sig_1180 <= sig_1104(26) & sig_1104(26 downto 8);
sig_1181 <= sig_719(26) & sig_719(26 downto 8);
sig_1182 <= sig_718(26) & sig_718(26 downto 8);
sig_1183 <= sig_1118(26) & sig_1118(26 downto 8);
-- Remaining top-level ports assignments
-- Those who are not assigned by component instantiation
cp_ok <= mux_151;
cp_dout <= mux_152;
stdout_data <= write8_u8;
stdout_rdy <= mux_154;
stdin_rdy <= mux_155;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3128.vhd | 4 | 2967 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3128.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x02p12n01i03128ent_a IS
generic ( g1 : integer := 3 );
END c05s02b01x02p12n01i03128ent_a;
ARCHITECTURE c05s02b01x02p12n01i03128arch_a OF c05s02b01x02p12n01i03128ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert g1 /= 2 report "g1 = 2" severity FAILURE;
assert g1 /= 3 report "g1 = 3" severity FAILURE;
assert g1 = 4 report "g1 /= 4" severity FAILURE;
assert g1 /= 5 report "g1 = 5" severity FAILURE;
assert g1 /= 6 report "g1 = 6" severity FAILURE;
assert NOT( g1 /= 2 and
g1 /= 3 and
g1 = 4 and
g1 /= 5 and
g1 /= 6 )
report "***PASSED TEST: c05s02b01x02p12n01i03128"
severity NOTE;
assert ( g1 /= 2 and
g1 /= 3 and
g1 = 4 and
g1 /= 5 and
g1 /= 6 )
report "***FAILED TEST: c05s02b01x02p12n01i03128 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x02p12n01i03128arch_a;
ENTITY c05s02b01x02p12n01i03128ent IS
END c05s02b01x02p12n01i03128ent;
ARCHITECTURE c05s02b01x02p12n01i03128arch OF c05s02b01x02p12n01i03128ent IS
BEGIN
labeled : block
component ic_socket
generic ( g1 : integer := 2 );
end component;
for instance : ic_socket use entity work.c05s02b01x02p12n01i03128ent_a (c05s02b01x02p12n01i03128arch_a)
generic map ( g1 => g1 + g1 );
begin
instance : ic_socket ;
end block;
END c05s02b01x02p12n01i03128arch;
configuration c05s02b01x02p12n01i03128cfg of c05s02b01x02p12n01i03128ent is
for c05s02b01x02p12n01i03128arch
end for;
end c05s02b01x02p12n01i03128cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/flipflop.vhd | 4 | 1296 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity flipflop is
generic ( Tsetup : delay_length );
port ( clk, d : in bit; q : out bit );
end entity flipflop;
-- code from book
architecture behavior of flipflop is
begin
timing_check : process (clk) is
begin
if clk = '1' then
assert d'last_event >= Tsetup
report "set up violation detected in " & timing_check'path_name
severity error;
end if;
end process timing_check;
-- . . . -- functionality
end architecture behavior;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_19.vhd | 4 | 3762 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_05_19 is
end entity fg_05_19;
architecture test of fg_05_19 is
constant scheduling_delay : delay_length := 5 ns;
subtype request_type is natural range 0 to 20;
type server_status_type is (ready, busy);
signal first_priority_request,
first_normal_request,
reset_request : request_type := 0;
signal functional_request, equivalent_request : request_type;
signal priority_waiting : boolean := false;
signal server_status : server_status_type := busy;
begin
functional_scheduler : block is
port ( request : out request_type );
port map ( request => functional_request );
begin
-- code from book
scheduler :
request <= first_priority_request after scheduling_delay
when priority_waiting and server_status = ready else
first_normal_request after scheduling_delay
when not priority_waiting and server_status = ready else
unaffected
when server_status = busy else
reset_request after scheduling_delay;
-- end code from book
end block functional_scheduler;
--------------------------------------------------
equivalent_scheduler : block is
port ( request : out request_type );
port map ( request => equivalent_request );
begin
-- code from book
scheduler : process is
begin
if priority_waiting and server_status = ready then
request <= first_priority_request after scheduling_delay;
elsif not priority_waiting and server_status = ready then
request <= first_normal_request after scheduling_delay;
elsif server_status = busy then
null;
else
request <= reset_request after scheduling_delay;
end if;
wait on first_priority_request, priority_waiting, server_status,
first_normal_request, reset_request;
end process scheduler;
-- end code from book
end block equivalent_scheduler;
--------------------------------------------------
stimulus : process is
begin
first_priority_request <= 10; wait for 20 ns;
first_normal_request <= 5; wait for 20 ns;
server_status <= ready; wait for 20 ns;
server_status <= busy; wait for 20 ns;
priority_waiting <= true; wait for 20 ns;
server_status <= ready; wait for 20 ns;
first_normal_request <= 7; wait for 20 ns;
first_priority_request <= 12; wait for 20 ns;
wait;
end process stimulus;
verifier :
assert functional_request = equivalent_request
report "Functional and equivalent models give different results";
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1178.vhd | 4 | 1593 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1178.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p01n02i01178ent IS
END c08s00b00x00p01n02i01178ent;
ARCHITECTURE c08s00b00x00p01n02i01178arch OF c08s00b00x00p01n02i01178ent IS
BEGIN
TESTING: PROCESS
BEGIN
case TRUE is
when TRUE =>
when FALSE =>
end case;
assert FALSE
report "***PASSED TEST: c08s00b00x00p01n02i01178"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s00b00x00p01n02i01178arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_11.vhd | 4 | 1800 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_11.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_05_11 is
end entity ch_05_11;
----------------------------------------------------------------
architecture test of ch_05_11 is
signal line_in, line_out : bit := '0';
begin
-- code from book:
transmission_line : process (line_in) is
begin
line_out <= transport line_in after 500 ps;
end process transmission_line;
-- end of code from book
----------------
stimulus : process is
begin
line_in <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps,
'1' after 8000 ps,
'0' after 8200 ps,
'1' after 8300 ps,
'0' after 8400 ps;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3119.vhd | 4 | 2902 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3119.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p05n01i03119ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p05n01i03119ent_a;
ARCHITECTURE c05s02b01x01p05n01i03119arch_a OF c05s02b01x01p05n01i03119ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p05n01i03119arch_a;
configuration c05s02b01x01p05n01i03119cfg_a of c05s02b01x01p05n01i03119ent_a is
for c05s02b01x01p05n01i03119arch_a
end for;
end c05s02b01x01p05n01i03119cfg_a;
--
ENTITY c05s02b01x01p05n01i03119ent IS
END c05s02b01x01p05n01i03119ent;
ARCHITECTURE c05s02b01x01p05n01i03119arch OF c05s02b01x01p05n01i03119ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p05n01i03119"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p05n01i03119 - Use a configuration that is fully bound test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p05n01i03119arch;
configuration c05s02b01x01p05n01i03119cfg of c05s02b01x01p05n01i03119ent is
for c05s02b01x01p05n01i03119arch
for all : virtual use configuration work.c05s02b01x01p05n01i03119cfg_a;
end for;
end for;
end c05s02b01x01p05n01i03119cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket50/ent2.vhdl | 3 | 327 | entity ent is
end entity;
package pkg1 is
function cond return boolean;
end pkg1;
package pkg2 is
function cond return boolean;
end pkg2;
use work.pkg1.all;
use work.pkg2.all;
architecture a of ent is
type enum_t is (cond);
begin
main : process
begin
if cond then
end if;
end process;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc179.vhd | 4 | 1853 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc179.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p02n01i00179ent IS
attribute attr : INTEGER;
END c04s04b00x00p02n01i00179ent;
ARCHITECTURE c04s04b00x00p02n01i00179arch OF c04s04b00x00p02n01i00179ent IS
constant C : INTEGER := 1;
attribute attr of C : CONSTANT is 40;
constant D : INTEGER := C'attr;
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( C = 1 and D = 40 )
report "***PASSED TEST: c04s04b00x00p02n01i00179"
severity NOTE;
assert ( C = 1 and D = 40 )
report "***FAILED TEST: c04s04b00x00p02n01i00179 - User-defined attribute test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p02n01i00179arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1084.vhd | 4 | 1887 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1084.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01084ent IS
END c06s05b00x00p02n01i01084ent;
ARCHITECTURE c06s05b00x00p02n01i01084arch OF c06s05b00x00p02n01i01084ent IS
BEGIN
TESTING: PROCESS
type FIVE is range 1 to 5;
type A51 is array (FIVE) of BOOLEAN;
type A53 is array (FIVE) of A51;
variable V51: A51 ;
variable V53: A53 ;
BEGIN
V51(2 downto 1, 3 to 4) := V51(2 downto 1, 3 to 4);
-- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
assert FALSE
report "***FAILED TEST: c06s05b00x00p02n01i01084 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01084arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_11.vhd | 4 | 1495 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_11.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_11 is
end entity ch_03_11;
architecture test of ch_03_11 is
signal sensitivity_list : bit := '0';
begin
-- code from book:
-- make "sensitivity_list" roman italic
control_section : process ( sensitivity_list ) is
begin
null;
end process control_section;
-- end of code from book
stimulus : process is
begin
sensitivity_list <= '1' after 10 ns, '0' after 20 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_diff.vhd | 4 | 1775 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity lead_lag_diff is
port ( signal clk : in std_logic; -- clock
quantity input : in real;
quantity output : out real );
end entity lead_lag_diff;
----------------------------------------------------------------
architecture bhv of lead_lag_diff is
constant k : real := 400.0; -- normalize gain
signal z_out : real := 0.0;
begin
proc : process (clk)
variable zi_dly1 : real := 0.0; -- input delayed 1 clk cycle
variable zo_dly1 : real := 0.0; -- output delayed 1 clk cycle
variable z_new : real := 0.0; -- new output value this clk cycle
begin
zo_dly1 := z_out; -- store previous output value
z_new := 0.6163507 * input - 0.6144184 * zi_dly1 + 0.2307692 * zo_dly1;
zi_dly1 := input; -- store previous input value
z_out <= z_new;
end process;
output == k * z_out'ramp(100.0e-9); -- ensure continuous transitions on output
end bhv;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc733.vhd | 4 | 2637 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc733.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x00p05n01i00733ent_a is
generic (
constant gc1 : integer;
gc2 : natural;
constant gc3 : positive
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x00p05n01i00733ent_a;
architecture arch of c01s01b01x00p05n01i00733ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
ENTITY c01s01b01x00p05n01i00733ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x00p05n01i00733ent;
ARCHITECTURE c01s01b01x00p05n01i00733arch OF c01s01b01x00p05n01i00733ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
variable dgc2 : natural;
signal dgc3 : positive
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x00p05n01i00733ent_a
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (3,3,3)
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p05n01i00733 - Variable and signal declaration can not be in local generic clause in component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p05n01i00733arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_23.vhd | 4 | 4342 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_23.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity nor_gate is
generic ( width : positive;
Tpd01, Tpd10 : delay_length );
port ( input : in std_logic_vector(0 to width - 1);
output : out std_logic );
end entity nor_gate;
architecture primitive of nor_gate is
function max ( a, b : delay_length ) return delay_length is
begin
if a > b then
return a;
else
return b;
end if;
end function max;
begin
reducer : process (input) is
variable result : std_logic;
begin
result := '0';
for index in input'range loop
result := result or input(index);
end loop;
if not result = '1' then
output <= not result after Tpd01;
elsif not result = '0' then
output <= not result after Tpd10;
else
output <= not result after max(Tpd01, Tpd10);
end if;
end process reducer;
end architecture primitive;
library ieee; use ieee.std_logic_1164.all;
library cell_lib;
entity interlock_control is
end entity interlock_control;
-- code from book
architecture detailed_timing of interlock_control is
component nor_gate is
generic ( input_width : positive );
port ( input : in std_logic_vector(0 to input_width - 1);
output : out std_logic );
end component nor_gate;
for ex_interlock_gate : nor_gate
use entity cell_lib.nor_gate(primitive)
generic map ( width => input_width,
Tpd01 => 250 ps, Tpd10 => 200 ps ); -- estimates
-- . . .
-- not in book
signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
-- end not in book
begin
ex_interlock_gate : component nor_gate
generic map ( input_width => 2 )
port map ( input(0) => reg_access_hazard,
input(1) => load_hazard,
output => stall_ex_n);
-- . . .
-- not in book
reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;
load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
'0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
'0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
'0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;
-- end not in book
end architecture detailed_timing;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1197.vhd | 4 | 1784 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1197.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01197ent IS
END c08s01b00x00p05n01i01197ent;
ARCHITECTURE c08s01b00x00p05n01i01197arch OF c08s01b00x00p05n01i01197ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait on k until (k=5);
assert NOT( k=5 )
report "***PASSED TEST: c08s01b00x00p05n01i01197"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s01b00x00p05n01i01197 - In the wait statement, the reserved word 'until' is followed by a boolean statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01197arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd | 4 | 2393 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity receiver is
end entity receiver;
-- code from book
architecture behavioral of receiver is
-- . . . -- type declarations, etc
-- not in book
subtype packet_index_range is integer range 1 to 8;
type packet_array is array (packet_index_range) of bit;
-- end not in book
signal recovered_data : bit;
signal recovered_clock : bit;
-- . . .
procedure receive_packet ( signal rx_data : in bit;
signal rx_clock : in bit;
data_buffer : out packet_array ) is
begin
for index in packet_index_range loop
wait until rx_clock = '1';
data_buffer(index) := rx_data;
end loop;
end procedure receive_packet;
begin
packet_assembler : process is
variable packet : packet_array;
begin
-- . . .
receive_packet ( recovered_data, recovered_clock, packet );
-- . . .
end process packet_assembler;
-- . . .
-- not in book
data_generator : recovered_data <= '1' after 5 ns,
'0' after 15 ns,
'1' after 25 ns,
'0' after 35 ns,
'0' after 45 ns,
'1' after 55 ns,
'0' after 65 ns,
'1' after 75 ns;
clock_generator : process is
begin
recovered_clock <= '0' after 2 ns, '1' after 10 ns;
wait for 10 ns;
end process clock_generator;
-- end not in book
end architecture behavioral;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc443.vhd | 4 | 3307 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc443.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00443ent IS
END c03s02b01x01p19n01i00443ent;
ARCHITECTURE c03s02b01x01p19n01i00443arch OF c03s02b01x01p19n01i00443ent IS
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_st is severity_level_vector(0 to 15);
constant C1 : severity_level := note;
constant C70 : severity_level_vector_st :=(others => C1);
function complex_scalar(s : severity_level_vector_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return severity_level_vector_st is
begin
return C70;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : severity_level_vector_st;
signal S2 : severity_level_vector_st;
signal S3 : severity_level_vector_st := C70;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C70) and (S2 = C70))
report "***PASSED TEST: c03s02b01x01p19n01i00443"
severity NOTE;
assert ((S1 = C70) and (S2 = C70))
report "***FAILED TEST: c03s02b01x01p19n01i00443 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00443arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug019/PoC/tb/common/my_config_ML505.vhdl | 2 | 1808 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML505"; -- ML505 - Xilinx Virtex 5 reference design board: XC5VLX50T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
package body my_config is
end package body;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1114.vhd | 4 | 2048 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1114.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01114ent IS
END c06s05b00x00p03n01i01114ent;
ARCHITECTURE c06s05b00x00p03n01i01114arch OF c06s05b00x00p03n01i01114ent IS
BEGIN
TESTING: PROCESS
type FIVE is range 1 to 5;
type A1B is array (FIVE range <>) of BOOLEAN;
subtype A1 is A1B(FIVE);
type A2B is array (FIVE range <>, FIVE range <>) of A1;
subtype A2 is A2B(FIVE, FIVE);
variable V1: A1;
variable V2: A2;
BEGIN
V1(2 to 4) := V2(1 to 3); -- ERROR: prefix of a slice name
-- cannot be a multi-dimensional
-- array object
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01114 - Prefix of a slice number must be a one-dimensional array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01114arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3014.vhd | 4 | 1992 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3014.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c11s01b00x00p08n03i03014ent is
procedure test;
end c11s01b00x00p08n03i03014ent;
package body c11s01b00x00p08n03i03014ent is
procedure test is
begin
assert false
report "Duplicate primary unit name allowed in same library -- test fails."
severity note ;
end test;
end c11s01b00x00p08n03i03014ent;
use work.c11s01b00x00p08n03i03014ent.all;
ENTITY c11s01b00x00p08n03i03014ent IS
END c11s01b00x00p08n03i03014ent;
ARCHITECTURE c11s01b00x00p08n03i03014arch OF c11s01b00x00p08n03i03014ent IS
BEGIN
c11s01b00x00p08n03i03014ent.test;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c11s01b00x00p08n03i03014d - Duplicate primary unit name is not allowed in same library."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s01b00x00p08n03i03014arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/perf02/mul_148.vhd | 3 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_148 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_148;
architecture augh of mul_148 is
signal tmp_res : signed(64 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(63 downto 0));
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2214.vhd | 4 | 1899 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2214.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02214ent IS
END c07s02b06x00p01n01i02214ent;
ARCHITECTURE c07s02b06x00p01n01i02214arch OF c07s02b06x00p01n01i02214ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
-- Local declarations.
variable LOGICV : LOGIC_SWITCH := '0';
variable k : integer;
BEGIN
k := LOGICV rem '0';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02214 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02214arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd | 4 | 2232 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_adc is
end tb_adc;
architecture tb_adc of tb_adc is
-- Component declarations
-- Signal declarations
signal clk_in : bit;
signal clk_in_tmp : std_logic;
signal dig_out1, dig_out2 : bit;
terminal sine_in : electrical;
quantity gain : real;
begin
-- Signal assignments
clk_in <= To_bit(clk_in_tmp); -- convert std_logic to bit
-- Component instances
v1 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 5.0
)
port map(
pos => sine_in,
neg => ELECTRICAL_REF
);
adc25 : entity work.adc(struct)
port map(
gain => gain,
a => sine_in,
d_out => dig_out1,
clk => clk_in
);
adc26 : entity work.adc(ideal)
port map(
gain => gain,
a => sine_in,
d_out => dig_out2,
clk => clk_in
);
clock1 : entity work.clock_duty(ideal)
generic map(
on_time => 1 ms,
off_time => 0.5 ms
)
port map(
CLOCK_OUT => clk_in_tmp
);
src1 : entity work.src_constant(ideal)
generic map(
level => 1.0
)
port map(
output => gain
);
end tb_adc;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_type.vhdl | 4 | 1776 | entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
begin -- only
process
variable x : std_logic;
begin -- process
assert std_logic'pos('U') = 0 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('X') = 1 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('0') = 2 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('1') = 3 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('Z') = 4 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('W') = 5 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('L') = 6 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('H') = 7 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('-') = 8 report "TEST FAILED" severity FAILURE;
assert x'left = 'U' report "TEST FAILED" severity FAILURE;
assert x'right = '-' report "TEST FAILED" severity FAILURE;
assert x'high = '-' report "TEST FAILED" severity FAILURE;
assert x'low = 'U' report "TEST FAILED" severity FAILURE;
assert x'ascending = true report "TEST FAILED" severity FAILURE;
assert std_logic'image('U') = "'U'" report "TEST FAILED" severity FAILURE;
assert std_logic'value("'U'") = 'U' report "TEST FAILED" severity FAILURE;
assert std_logic'val(0) = 'U' report "TEST FAILED" severity FAILURE;
assert std_logic'succ('U') = 'X' report "TEST FAILED" severity FAILURE;
assert std_logic'pred('-') = 'H' report "TEST FAILED" severity FAILURE;
assert std_logic'leftof('-') = 'H' report "TEST FAILED" severity FAILURE;
assert std_logic'rightof('U') = 'X' report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity note;
wait;
end process;
end only;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1389.vhd | 4 | 1901 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1389.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n02i01389ent IS
END c08s05b00x00p04n02i01389ent;
ARCHITECTURE c08s05b00x00p04n02i01389arch OF c08s05b00x00p04n02i01389ent IS
subtype C2 is BIT_VECTOR(1 to 2);
BEGIN
TESTING: PROCESS
variable S1 : BIT;
variable T1 : BIT;
variable BIT2 : C2 := B"11";
BEGIN
(S1, T1) := BIT2;
assert NOT((S1 = '1') and (T1 = '1'))
report "***PASSED TEST: c08s05b00x00p04n02i01389"
severity NOTE;
assert ((S1 = '1') and (T1 = '1'))
report "***FAILED TEST: c08s05b00x00p04n02i01389 - Base types of the expression on the right hand side is the same as the base type of the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n02i01389arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc24.vhd | 4 | 2460 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc24.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p10n01i00024ent IS
END c04s02b00x00p10n01i00024ent;
ARCHITECTURE c04s02b00x00p10n01i00024arch OF c04s02b00x00p10n01i00024ent IS
BEGIN
TESTING: PROCESS
-- Define an ascending subtype.
subtype ASC is INTEGER range 0 to 1;
-- Define a descending subtype.
subtype DES is INTEGER range 1 to 0;
-- Define a 'previous value' variable.
variable PREV : INTEGER;
variable k : integer := 0;
variable l : integer := 0;
BEGIN
-- Test the direction of the ascending range.
PREV := -1;
for I in ASC loop
if (I > PREV) then
PREV := I;
else
k := 1;
end if;
end loop;
-- Test the direction of the descending range.
PREV := 2;
for I in DES loop
if (I < PREV) then
PREV := I;
else
l := 1;
end if;
end loop;
assert NOT( k=0 and l=0 )
report "***PASSED TEST:c04s02b00x00p10n01i00024"
severity NOTE;
assert ( k=0 and l=0 )
report "***FAILED TEST: c04s02b00x00p10n01i00024 - The direction of a discrete subtype indication is the same as the direction of the range constraint that appears as the constraint of the subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p10n01i00024arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1713.vhd | 4 | 1783 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1713.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p10n01i01713ent IS
port (signal max : in natural);
type word is array (natural range <>) of bit;
subtype mem_array is word (0 to 7);
END c09s02b00x00p10n01i01713ent;
ARCHITECTURE c09s02b00x00p10n01i01713arch OF c09s02b00x00p10n01i01713ent IS
signal idx : natural;
signal mem : mem_array;
BEGIN
TESTING: PROCESS(mem_array'(others => '1'))
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p10n01i01713 - Process sensitivity list can not be a qualified aggregate."
severity ERROR;
END PROCESS TESTING;
END c09s02b00x00p10n01i01713arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2004.vhd | 4 | 2057 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2004.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p08n02i02004ent IS
END c07s02b02x00p08n02i02004ent;
ARCHITECTURE c07s02b02x00p08n02i02004arch OF c07s02b02x00p08n02i02004ent IS
BEGIN
TESTING: PROCESS
type array_x is array (positive range <>) of integer;
subtype array_three is array_x (1 to 6) ;
subtype array_four is array_x (6 downto 1) ;
variable x : array_four := (1,2,3,4,5,6);
variable y : array_three := (1,2,3,4,5,6);
BEGIN
assert NOT(x=y)
report "***PASSED TEST: c07s02b02x00p08n02i02004"
severity NOTE;
assert ( x=y )
report "***FAILED TEST: c07s02b02x00p08n02i02004 - Two composite values of the same type are equal if and only if for each element of the left operand there is a matching element of the right operand and vice versa."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p08n02i02004arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc466.vhd | 4 | 3392 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc466.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00466ent IS
END c03s02b01x01p19n01i00466ent;
ARCHITECTURE c03s02b01x01p19n01i00466arch OF c03s02b01x01p19n01i00466ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type integer_vector is array (natural range <>) of integer;
subtype integer_vector_range is integer_vector(hi_to_low_range);
constant C66: integer_vector_range := (others => 3);
function complex_scalar(s : integer_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_vector_range;
signal S2 : integer_vector_range;
signal S3 : integer_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00466"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00466 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00466arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/sub_243.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_243 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_243;
architecture augh of sub_243 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | libraries/vital95/vital_timing.vhdl | 6 | 46973 | -------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug052/tb_simple.vhdl | 2 | 249 | entity tb_simple is
package pkg1 is
constant c : natural := 5;
end pkg1;
end tb_simple;
architecture behav of tb_simple is
begin
assert pkg1.c = 5 severity failure;
assert pkg1.c /= 5 report "value is correct" severity note;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1867.vhd | 4 | 1992 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1867.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01867ent IS
END c07s01b00x00p08n01i01867ent;
ARCHITECTURE c07s01b00x00p08n01i01867arch OF c07s01b00x00p08n01i01867ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal s_int : small_int;
signal bool : boolean;
BEGIN
with c07s01b00x00p08n01i01867arch select --body name illegal here
obus <= (0 => 1, others => 0) after 5 ns when true;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01867 - Architecture body names are not permitted as primaries in a selected signal expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01867arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3125.vhd | 4 | 2373 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3125.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x02p08n01i03125ent_a IS
generic ( message : string );
END c05s02b01x02p08n01i03125ent_a;
ARCHITECTURE c05s02b01x02p08n01i03125arch_a OF c05s02b01x02p08n01i03125ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( message = "Hello there..." )
report "***PASSED TEST: c05s02b01x02p08n01i03125"
severity NOTE;
assert ( message = "Hello there..." )
report "***FAILED TEST: c05s02b01x02p08n01i03125 - Generic maps work does not work properly with unconstrained generic elements."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x02p08n01i03125arch_a;
ENTITY c05s02b01x02p08n01i03125ent IS
END c05s02b01x02p08n01i03125ent;
ARCHITECTURE c05s02b01x02p08n01i03125arch OF c05s02b01x02p08n01i03125ent IS
component ic_socket
generic ( message : string );
end component;
BEGIN
u1 : ic_socket generic map ("Hello there...");
END c05s02b01x02p08n01i03125arch;
configuration c05s02b01x02p08n01i03125cfg of c05s02b01x02p08n01i03125ent is
for c05s02b01x02p08n01i03125arch
for u1 : ic_socket use entity work.c05s02b01x02p08n01i03125ent_a(c05s02b01x02p08n01i03125arch_a);
end for;
end for;
end c05s02b01x02p08n01i03125cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2133.vhd | 4 | 2378 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2133.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02133ent IS
END c07s02b04x00p21n01i02133ent;
ARCHITECTURE c07s02b04x00p21n01i02133arch OF c07s02b04x00p21n01i02133ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_5 is record_v (1 to 5);
SUBTYPE record_4 is record_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : record_5;
variable l_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
variable r_operand : simple_record := (12,34);
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result = ((12,34),(56,78),(12,34),(56,78),(12,34)))
report "***PASSED TEST: c07s02b04x00p21n01i02133"
severity NOTE;
assert ( result = ((12,34),(56,78),(12,34),(56,78),(12,34)))
report "***FAILED TEST: c07s02b04x00p21n01i02133 - Concatenation of element and RECORD array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02133arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_02.vhd | 4 | 1882 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_tb_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_04_02 is
end entity test_bench_04_02;
----------------------------------------------------------------
architecture test_and_multiple_behavioral of test_bench_04_02 is
-- code from book:
signal count_value : bit_vector(7 downto 0);
signal terminal_count : bit;
-- end of code from book
begin
-- code from book:
tc_gate : entity work.and_multiple(behavioral)
port map ( i => count_value, y => terminal_count);
-- end of code from book
stumulus : process is
begin
wait for 10 ns;
count_value <= "10000000"; wait for 10 ns;
count_value <= "11111110"; wait for 10 ns;
count_value <= "01111111"; wait for 10 ns;
count_value <= "11111111"; wait for 10 ns;
count_value <= "00000000"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_and_multiple_behavioral;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1548.vhd | 4 | 3397 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1548.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01548ent IS
END c08s09b00x00p10n01i01548ent;
ARCHITECTURE c08s09b00x00p10n01i01548arch OF c08s09b00x00p10n01i01548ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type COLORS is (RED, GREEN, BLUE);
variable k : integer := 0;
BEGIN
-- None of these loops should EVER execute any of their statements.
for I in INTEGER'HIGH to 0 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'HIGH to INTEGER'HIGH-1 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'LOW downto 0 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'LOW downto INTEGER'LOW + 1 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'HIGH to COLORS'LOW loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'HIGH to COLORS'PRED( COLORS'HIGH ) loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'LOW downto COLORS'HIGH loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'LOW downto COLORS'SUCC( COLORS'LOW ) loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p10n01i01548"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p10n01i01548 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01548arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd | 4 | 1551 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity std_logic_to_analog is
port ( d : in std_logic;
terminal a : electrical );
end entity std_logic_to_analog;
----------------------------------------------------------------
architecture ideal of std_logic_to_analog is
constant v_low : real := 0.0;
constant v_high : real := 5.0;
constant v_unknown : real := 2.0;
signal v_in : real := 0.0;
quantity v_out across i_out through a to electrical_ref;
begin
v_in <= v_high when d = '1' or d = 'H' else
v_low when d = '0' or d = 'L' else
v_unknown;
v_out == v_in'slew(2.0e+9, -1.0e+9);
end architecture ideal;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1771.vhd | 4 | 1832 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1771.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b02x00p11n01i01771ent IS
END c09s05b02x00p11n01i01771ent;
ARCHITECTURE c09s05b02x00p11n01i01771arch OF c09s05b02x00p11n01i01771ent IS
type x is (Jan,Feb,Mar);
signal y : x;
signal Month_Num : integer;
BEGIN
with y select
Month_num <= transport 1 when Jan,
2 when Feb,
3 when others, -- Failure_here
-- choice 'others' is not last.
4 when Mar;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b02x00p11n01i01771 - Choice of others should be the last alternative."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b02x00p11n01i01771arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc422.vhd | 4 | 3293 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc422.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00422ent IS
END c03s02b01x01p19n01i00422ent;
ARCHITECTURE c03s02b01x01p19n01i00422arch OF c03s02b01x01p19n01i00422ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
constant C1 : boolean_cons_vectorofvector := (others => (others => true));
function complex_scalar(s : boolean_cons_vectorofvector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_cons_vectorofvector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_cons_vectorofvector;
signal S2 : boolean_cons_vectorofvector;
signal S3 : boolean_cons_vectorofvector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00422"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00422 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00422arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/integer-record-aggregate-init.vhdl | 4 | 527 | entity test is
end test;
architecture only of test is
begin -- only
p: process
type integerRecord is record
foo : integer;
bar : integer;
end record;
variable myRecord : integerRecord;
begin -- process p
myRecord := ( 0, 1 );
assert myRecord.foo = 0 report "TEST FAILED - 0" severity FAILURE;
assert myRecord.bar = 1 report "TEST FAILED - 1" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket18/psl_test_working.vhd | 3 | 1000 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_working is
end entity psl_test_working;
architecture test of psl_test_working is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_WORKING test case";
report "==================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- this one works:
-- psl assert always (s_write -> not(s_read));
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3024.vhd | 4 | 1831 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3024.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c11s03b00x00p02n01i03024pkg is
type T is (one,two);
end c11s03b00x00p02n01i03024pkg;
ENTITY c11s03b00x00p02n01i03024ent IS
END c11s03b00x00p02n01i03024ent;
ARCHITECTURE c11s03b00x00p02n01i03024arch OF c11s03b00x00p02n01i03024ent IS
signal S : boolean;
BEGIN
TESTING: PROCESS
BEGIN
S <= TRUE;
wait for 3 ns;
assert NOT( S = TRUE )
report "***PASSED TEST: c11s03b00x00p02n01i03024"
severity NOTE;
assert ( S = TRUE )
report "***FAILED TEST: c11s03b00x00p02n01i03024 - A context clause can contain zero context item."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s03b00x00p02n01i03024arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc633.vhd | 4 | 2809 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc633.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:48 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:12 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:27 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00633ent IS
END c03s04b01x00p01n01i00633ent;
ARCHITECTURE c03s04b01x00p01n01i00633arch OF c03s04b01x00p01n01i00633ent IS
type four_value is ('Z','0','1','X');
subtype binary is four_value range '0' to '1';
type binary_file is file of binary;
constant C38 : binary := '0';
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : binary_file open read_mode is "iofile.38";
variable v : binary;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00633"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00633 - File reading operation (binary file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00633arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/sub_221.vhd | 2 | 1730 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_221 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_221;
architecture augh of sub_221 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
gt <= not(tmp_le);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2447.vhd | 4 | 1790 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2447.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p02n02i02447ent IS
END c07s03b02x02p02n02i02447ent;
ARCHITECTURE c07s03b02x02p02n02i02447arch OF c07s03b02x02p02n02i02447ent IS
BEGIN
TESTING: PROCESS
type t16 is array (1 to 1) of integer;
variable v16 : t16;
BEGIN
v16 := (1 to 0 => 16, 1 => 12); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s03b02x02p02n02i02447 - Named association of an array aggregate can have a choice that is a null range only if the aggregate includes a single element association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p02n02i02447arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2063.vhd | 4 | 1883 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2063.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02063ent IS
END c07s02b04x00p01n02i02063ent;
ARCHITECTURE c07s02b04x00p01n02i02063arch OF c07s02b04x00p01n02i02063ent IS
signal S1 : Integer;
signal S2 : Integer;
signal S3 : BIT_VECTOR(0 to 7);
BEGIN
TESTING: PROCESS
variable V1,V2 : Integer := 10;
variable V3,V4 : BIT_VECTOR(0 to 3) := "0101" ;
BEGIN
S3 <= V3&V4;
wait for 1 ns;
assert NOT(S3 = "01010101")
report "***PASSED TEST: c07s02b04x00p01n02i02063"
severity NOTE;
assert (S3 = "01010101")
report "***FAILED TEST: c07s02b04x00p01n02i02063 - Operands must be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02063arch;
| gpl-2.0 |
emogenet/ghdl | libraries/ieee2008/numeric_std_unsigned-body.vhdl | 4 | 18848 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD_UNSIGNED package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type STD_ULOGIC_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the STD_ULOGIC_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
package body NUMERIC_STD_UNSIGNED is
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function "?>" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?> UNSIGNED(R);
end function "?>";
-- Id: C.51
function "?>" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?> UNSIGNED(R);
end function "?>";
-- Id: C.53
function "?>" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?> R;
end function "?>";
--============================================================================
-- Id: C.55
function "?<" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?< UNSIGNED(R);
end function "?<";
-- Id: C.57
function "?<" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?< UNSIGNED(R);
end function "?<";
-- Id: C.59
function "?<" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?< R;
end function "?<";
--============================================================================
-- Id: C.61
function "?<=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.63
function "?<=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.65
function "?<=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?<= R;
end function "?<=";
--============================================================================
-- Id: C.67
function "?>=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.69
function "?>=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.71
function "?>=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?>= R;
end function "?>=";
--============================================================================
-- Id: C.73
function "?=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?= UNSIGNED(R);
end function "?=";
-- Id: C.75
function "?=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?= UNSIGNED(R);
end function "?=";
-- Id: C.77
function "?=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?= R;
end function "?=";
--============================================================================
-- Id: C.79
function "?/=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.81
function "?/=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.83
function "?/=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?/= R;
end function "?/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdLogicVector;
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdULogicVector;
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdLogicVector;
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdULogicVector;
end package body NUMERIC_STD_UNSIGNED;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/add_430.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_430 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_430;
architecture augh of add_430 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2617.vhd | 4 | 1680 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2617.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02617ent IS
END c13s03b01x00p02n01i02617ent;
ARCHITECTURE c13s03b01x00p02n01i02617arch OF c13s03b01x00p02n01i02617ent IS
BEGIN
TESTING: PROCESS
variable k(k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02617 - Identifier can not contain '('."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02617arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3104.vhd | 4 | 1807 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3104.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p16n02i03104ent IS
port (PT:BOOLEAN);
attribute AT1 : integer;
attribute AT1 of ch0501_P01602_02_ent : entity is 1.2; -- Failure_here
--ERROR: Specification expression is not the same type as attribute declaration
END c05s01b00x00p16n02i03104ent;
ARCHITECTURE c05s01b00x00p16n02i03104arch OF c05s01b00x00p16n02i03104ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p16n02i03104 - Specification expression is not of the same type as attribute specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p16n02i03104arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2755.vhd | 4 | 1621 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2755.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p03n01i02755ent IS
END c13s07b00x00p03n01i02755ent;
ARCHITECTURE c13s07b00x00p03n01i02755arch OF c13s07b00x00p03n01i02755ent IS
BEGIN
TESTING: PROCESS
variable bit_str : bit_vector (1 to 8) := b"0101 0101";
BEGIN
assert FALSE
report "***FAILED TEST: c13s07b00x00p03n01i02755 - Spaces are not allowed in bit string."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p03n01i02755arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1453.vhd | 4 | 1696 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1453.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p01n01i01453ent IS
END c08s07b00x00p01n01i01453ent;
ARCHITECTURE c08s07b00x00p01n01i01453arch OF c08s07b00x00p01n01i01453ent IS
BEGIN
transmit: process
variable s := 10;
begin
if s + 10 then -- failure_here condition not boolean.
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p01n01i01453 - Expression of IF statement must be of type BOOLEAN"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p01n01i01453arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc263.vhd | 4 | 1659 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc263.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00263ent IS
END c03s01b02x00p08n01i00263ent;
ARCHITECTURE c03s01b02x00p08n01i00263arch OF c03s01b02x00p08n01i00263ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER := INTEGER'HIGH / 2 + 1;
BEGIN
V := V + V; -- operation should overflow
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00263 - Number is out of integer bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00263arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc598.vhd | 4 | 2080 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc598.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00598ent IS
END c03s04b01x00p01n01i00598ent;
ARCHITECTURE c03s04b01x00p01n01i00598arch OF c03s04b01x00p01n01i00598ent IS
type time_cons_vector is array (15 downto 0) of time;
type time_cons_vector_file is file of time_cons_vector;
constant C19 : time_cons_vector := (others => 3 ns);
BEGIN
TESTING: PROCESS
file filein : time_cons_vector_file open write_mode is "iofile.32";
BEGIN
for i in 1 to 100 loop
write(filein, C19);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00598 - The output file will be verified by test s010246.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00598arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1048.vhd | 4 | 1834 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1048.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01048ent IS
END c06s04b00x00p03n01i01048ent;
ARCHITECTURE c06s04b00x00p03n01i01048arch OF c06s04b00x00p03n01i01048ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type ONE is range 1 to 1;
type A2 is array (ONE) of BOOLEAN;
variable V1: BOOLEAN;
BEGIN
V1 := A2'(1=>TRUE)(1);
-- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01048 - Prefix of an indexed name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01048arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1404.vhd | 4 | 1710 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1404.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p06n01i01404ent IS
END c08s05b00x00p06n01i01404ent;
ARCHITECTURE c08s05b00x00p06n01i01404arch OF c08s05b00x00p06n01i01404ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER range 1 to 10;
BEGIN
V := 1;
V := V - 1; -- scalar variable subtype check error
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c08s05b00x00p06n01i01404 - Scalar variable subtype check test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p06n01i01404arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2812.vhd | 4 | 1602 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2812.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity NAND is
end NAND;
ENTITY c13s09b00x00p99n01i02812ent IS
END c13s09b00x00p99n01i02812ent;
ARCHITECTURE c13s09b00x00p99n01i02812arch OF c13s09b00x00p99n01i02812ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02812 - Reserved word NAND can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02812arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1029.vhd | 4 | 2272 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1029.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01029ent IS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type A2 is array (THREE, THREE) of BOOLEAN;
type A3 is array (THREE) of A1;
type R1 is record
RE1: A1;
end record;
type R2 is record
RE2: A2;
end record;
type R3 is record
RE3: A3;
end record;
END c06s04b00x00p02n01i01029ent;
ARCHITECTURE c06s04b00x00p02n01i01029arch OF c06s04b00x00p02n01i01029ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
variable V1: R1 ; -- := (RE1=>(others=>TRUE));
variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));
variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
BEGIN
V := V2.RE2(2, 3);
assert NOT( V=false )
report "***PASSED TEST: c06s04b00x00p02n01i01029"
severity NOTE;
assert ( V=false )
report "***FAILED TEST: c06s04b00x00p02n01i01029 - The prefix of an indexed name can be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01029arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc323.vhd | 4 | 1894 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc323.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p04n01i00323ent IS
END c03s02b01x00p04n01i00323ent;
ARCHITECTURE c03s02b01x00p04n01i00323arch OF c03s02b01x00p04n01i00323ent IS
type bit_vctor is array (14 downto 7) of bit;
BEGIN
TESTING: PROCESS
variable k : bit_vctor;
BEGIN
k(14 downto 7) :="11110000";
assert NOT(k(14 downto 7)="11110000")
report "***PASSED TEST: c03s02b01x00p04n01i00323"
severity NOTE;
assert ( k(14 downto 7)="11110000" )
report "***FAILED TEST: c03s02b01x00p04n01i00323 - In the constrainted array definition, the reserved word array is followed by an index constraint and the reserved word if."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p04n01i00323arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/sub_503.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_503 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_503;
architecture augh of sub_503 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1947.vhd | 4 | 16579 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1947.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01947pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- -----------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01947pkg.all;
ENTITY c07s02b01x00p01n02i01947ent IS
END c07s02b01x00p01n02i01947ent;
ARCHITECTURE c07s02b01x00p01n02i01947arch OF c07s02b01x00p01n02i01947ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT NAND_C_csa1_1 : t_csa1_1 := ( '0', '1', '1', '1' );
CONSTANT NAND_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT NAND_C_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, TRUE );
CONSTANT NAND_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, TRUE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT NAND_C_csa1_3 : t_csa1_3 := ( '0', '1', '1', '1' );
CONSTANT NAND_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT NAND_C_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, TRUE );
CONSTANT NAND_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, TRUE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL NAND_S_csa1_1 : t_csa1_1 := ( '0', '1', '1', '1' );
SIGNAL NAND_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL NAND_S_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, TRUE );
SIGNAL NAND_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, TRUE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL NAND_S_csa1_3 : t_csa1_3 := ( '0', '1', '1', '1' );
SIGNAL NAND_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL NAND_S_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, TRUE );
SIGNAL NAND_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, TRUE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE NAND_V_csa1_1 : t_csa1_1 := ( '0', '1', '1', '1' );
VARIABLE NAND_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE NAND_V_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, TRUE );
VARIABLE NAND_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, TRUE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE NAND_V_csa1_3 : t_csa1_3 := ( '0', '1', '1', '1' );
VARIABLE NAND_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE NAND_V_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, TRUE );
VARIABLE NAND_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, TRUE );
BEGIN
--
-- Test NANDoperator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test NANDoperator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test NANDoperator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1 and
( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2 and
( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3 and
( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4 and
( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1 and
( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2 and
( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3 and
( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4 and
( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1 and
( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2 and
( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3 and
( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4 and
( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1 and
( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2 and
( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3 and
( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4 and
( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1 and
( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2 and
( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3 and
( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4 and
( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1 and
( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2 and
( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3 and
( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01947"
severity NOTE;
assert ( ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1 and
( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2 and
( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3 and
( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4 and
( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1 and
( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2 and
( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3 and
( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4 and
( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1 and
( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2 and
( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3 and
( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4 and
( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1 and
( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2 and
( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3 and
( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4 and
( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1 and
( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2 and
( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3 and
( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4 and
( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1 and
( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2 and
( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3 and
( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01947 - Logical operator NAND for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01947arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2817.vhd | 4 | 1602 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2817.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity NULL is
end NULL;
ENTITY c13s09b00x00p99n01i02817ent IS
END c13s09b00x00p99n01i02817ent;
ARCHITECTURE c13s09b00x00p99n01i02817arch OF c13s09b00x00p99n01i02817ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02817 - Reserved word NULL can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02817arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1565.vhd | 4 | 1776 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1565.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01565ent IS
END c08s10b00x00p03n01i01565ent;
ARCHITECTURE c08s10b00x00p03n01i01565arch OF c08s10b00x00p03n01i01565ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for i in 1 to 10 loop
next when i = 3;
k := k + 1;
end loop;
assert NOT( k=9 )
report "***PASSED TEST: c08s10b00x00p03n01i01565"
severity NOTE;
assert ( k=9 )
report "***FAILED TEST: c08s10b00x00p03n01i01565 - A NEXT statement must be inside a loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01565arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/multiple_opamp.vhd | 4 | 1660 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity multiple_opamp is
generic ( size : positive;
gains : real_vector );
port ( terminal inputs, outputs : electrical_vector(1 to size) );
end entity multiple_opamp;
----------------------------------------------------------------
architecture ideal of multiple_opamp is
quantity v_in across i_in through inputs to electrical_ref;
quantity v_out across outputs to electrical_ref;
alias gains_alias : real_vector(1 to size) is gains;
begin
assert gains'length = size
report "gains vector size differs from input/output size";
amplify : procedural is
begin
for index in 1 to size loop
v_out(index) := v_in(index) * gains_alias(index);
end loop;
end procedural amplify;
end architecture ideal;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-event-attribute.vhdl | 3 | 704 | entity test is
end test;
architecture only of test is
signal s : bit;
begin
s <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
p: process
begin
wait for 1 ns;
assert not(s'event) report "TEST FAILED - 'event active" severity failure;
wait for 25 ns;
-- s <= '1';
-- wait for 0 ns;
assert s = '0' report "TEST FAILED - s has not changed to 0 yet!" severity failure;
--wait for 10 ns;
wait for 4 ns;
assert s = '1' report "TEST FAILED - s has not changed to 1 yet!" severity failure;
assert (s'event) report "TEST FAILED - 'event not tripped" severity failure;
report "TEST PASSED";
wait;
end process;
end architecture only;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2854.vhd | 4 | 2294 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2854.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p03n01i02854ent IS
END c13s10b00x00p03n01i02854ent;
ARCHITECTURE c13s10b00x00p03n01i02854arch OF c13s10b00x00p03n01i02854ent IS
constant one : integer := 16:E:E1;
constant two : integer := 16#E#E1;
constant three : integer := 16#FF#;
constant four : integer := 16:FF:;
constant five : integer := 2#1110_0000#;
constant six : integer := 2:1110_0000:;
constant seven : integer := 8#776#;
constant eight : integer := 8:776:;
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( one=two and
three=four and
five=six and
seven=eight )
report "***PASSED TEST: c13s10b00x00p03n01i02854"
severity NOTE;
assert ( one=two and
three=four and
five=six and
seven=eight )
report "***FAILED TEST: c13s10b00x00p03n01i02854 - Colon(:) can replace the sharp character(#) in based literal definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p03n01i02854arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3016.vhd | 4 | 1887 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3016.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library WORK, STD;
use STD.STANDARD.all; -- No_failure_here
ENTITY c11s02b00x00p05n02i03016ent IS
END c11s02b00x00p05n02i03016ent;
ARCHITECTURE c11s02b00x00p05n02i03016arch OF c11s02b00x00p05n02i03016ent IS
signal BV : BIT_VECTOR(0 to 7);
BEGIN
TESTING: PROCESS
BEGIN
BV <= "01010111" after 5 ns;
wait for 10 ns;
assert NOT( BV = "01010111" )
report "***PASSED TEST: c11s02b00x00p05n02i03016"
severity NOTE;
assert ( BV = "01010111" )
report "***FAILED TEST: c11s02b00x00p05n02i03016 - Library clause should appear as part of a context clause at the beginning of a design unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s02b00x00p05n02i03016arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1627.vhd | 4 | 1657 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1627.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01627ent IS
END c08s12b00x00p03n01i01627ent;
ARCHITECTURE c08s12b00x00p03n01i01627arch OF c08s12b00x00p03n01i01627ent IS
BEGIN
TESTING: PROCESS
BEGIN
return true; -- illegal in a process statement
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01627 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01627arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2480.vhd | 4 | 1933 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2480.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p13n04i02480ent IS
END c07s03b02x02p13n04i02480ent;
ARCHITECTURE c07s03b02x02p13n04i02480arch OF c07s03b02x02p13n04i02480ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CA_UP is UNCONSTRAINED_ARRAY (1 to 10);
subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
BEGIN
TESTING: PROCESS
BEGIN
assert NOT((CA_DOWN'RIGHT = 1) and (CA_UP'RIGHT = 10))
report "***PASSED TEST: c07s03b02x02p13n04i02480"
severity NOTE;
assert ((CA_DOWN'RIGHT = 1) and (CA_UP'RIGHT = 10))
report "***FAILED TEST: c07s03b02x02p13n04i02480 - Rightmost bounds INCORRECT for positional aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p13n04i02480arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1875.vhd | 4 | 1786 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1875.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01875ent IS
END c07s01b00x00p08n01i01875ent;
ARCHITECTURE c07s01b00x00p08n01i01875arch OF c07s01b00x00p08n01i01875ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
variable car : small_int;
BEGIN
car := c07s01b00x00p08n01i01875arch; --architecture body name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01875 - Architecture body names are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01875arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc105.vhd | 4 | 1666 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc105.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00105ent IS
port ( signal S : out bit) ;
END c04s03b02x00p29n06i00105ent;
ARCHITECTURE c04s03b02x00p29n06i00105arch OF c04s03b02x00p29n06i00105ent IS
BEGIN
TESTING: PROCESS
BEGIN
if (S'ACTIVE) then -- Failure_here
end if;
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n06i00105 - The attribute ACTIVE of a signal of mode out cannot be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00105arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2626.vhd | 4 | 1680 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2626.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02626ent IS
END c13s03b01x00p02n01i02626ent;
ARCHITECTURE c13s03b01x00p02n01i02626arch OF c13s03b01x00p02n01i02626ent IS
BEGIN
TESTING: PROCESS
variable k[k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02626 - Identifier can not contain '['."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02626arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug022/test.vhdl | 2 | 468 | entity test is
end entity test;
entity internal is
end entity internal;
architecture arch of internal is begin
end architecture arch;
entity internal_bis is
end entity internal_bis;
architecture arch of internal_bis is begin
end architecture arch;
architecture first of test is begin
test_instantiation : entity work.internal;
end architecture first;
architecture second of test is begin
test_instantiation : entity work.internal_bis;
end architecture second;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3033.vhd | 4 | 2647 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3033.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b01x00p01n02i03033ent IS
END c12s02b01x00p01n02i03033ent;
ARCHITECTURE c12s02b01x00p01n02i03033arch OF c12s02b01x00p01n02i03033ent IS
subtype subi is integer range 1 to 10;
signal s1,s2,s3 : subi;
BEGIN
bl1: block
generic (gi : subi);
generic map (gi => 1);
port (s11 : OUT subi);
port map (s11 => s1);
begin
assert (gi=1)
report "Generic GI did not take on the correct low value of 1"
severity failure;
s11 <= gi;
end block;
bl2: block
generic (gi : subi);
generic map (gi => 5);
port (s22 : OUT subi);
port map (s22 => s2);
begin
assert (gi=5)
report "Generic GI did not take on the correct middle value of 5"
severity failure;
s22 <= gi;
end block;
bl3: block
generic (gi : subi);
generic map (gi => 10);
port (s33 : OUT subi);
port map (s33 => s3);
begin
assert (gi=10)
report "Generic GI did not take on the correct high value of 10"
severity failure;
s33 <= gi;
end block;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( s1 = 1 and s2 = 5 and s3 = 10 )
report "***PASSED TEST: c12s02b01x00p01n02i03033"
severity NOTE;
assert ( s1 = 1 and s2 = 5 and s3 = 10 )
report "***FAILED TEST: c12s02b01x00p01n02i03033 - Generic constants does not conform to their subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s02b01x00p01n02i03033arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1079.vhd | 4 | 2028 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1079.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n02i01079ent IS
END c06s05b00x00p01n02i01079ent;
ARCHITECTURE c06s05b00x00p01n02i01079arch OF c06s05b00x00p01n02i01079ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL v_slice : bit_vector_8 := B"1010_1100";
procedure subprogram ( signal v : out bit_vector_4 ) is
begin
v <= B"0101" after 10 ns;
end ;
BEGIN
TESTING: PROCESS
BEGIN
subprogram ( v_slice ( 0 to 3 ) );
wait for 11 ns;
assert NOT(v_slice = B"0101_1100")
report "***PASSED TEST: c06s05b00x00p01n02i01079"
severity NOTE;
assert (v_slice = B"0101_1100")
report "***FAILED TEST: c06s05b00x00p01n02i01079 - A slice of a signal should still be a signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n02i01079arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_06.vhd | 4 | 2210 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_06.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_06 is
end entity fg_a_06;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_06 is
-- code from book
constant terminal_count : integer := 2**6 - 1;
subtype counter_range is integer range 0 to terminal_count;
signal count : counter_range;
-- . . .
-- end code from book
signal clk, reset : std_ulogic;
begin
-- code from book
counter6 : process (reset, clk)
begin
if reset = '0' then
count <= 0;
elsif rising_edge(clk) then
if count < terminal_count then
count <= count + 1;
else
count <= 0;
end if;
end if;
end process counter6;
-- end code from book
stimulus : process is
begin
reset <= '1'; clk <= '0'; wait for 10 ns;
clk <= '1', '0' after 10 ns; wait for 20 ns;
clk <= '1', '0' after 10 ns; wait for 20 ns;
clk <= '1', '0' after 10 ns; wait for 20 ns;
reset <= '0', '1' after 30 ns;
clk <= '1' after 10 ns, '0' after 20 ns;
wait for 40 ns;
for i in 1 to terminal_count + 10 loop
clk <= '1', '0' after 10 ns;
wait for 20 ns;
end loop;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue150/concat2.vhdl | 2 | 434 | library ieee;
use ieee.std_logic_1164.all;
entity concat is
port (a: in std_ulogic_vector (3 downto 0);
b: in std_ulogic_vector (3 downto 0);
q1: out std_ulogic_vector (7 downto 0);
q2: out std_ulogic_vector (7 downto 0);
q3: out std_ulogic_vector (7 downto 0));
end concat;
architecture rtl of concat is
begin
as_q1: q1 <= "0000" & b;
as_q2: q2 <= a & "0000";
as_q3: q3 <= a & b;
end rtl;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_01.vhd | 4 | 1879 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_tb_01_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_01_01 is
end entity test_bench_01_01;
architecture test_reg4_behav of test_bench_01_01 is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)
port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
stimulus : process is
begin
wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1010"); wait for 20 ns;
en <= '1'; wait for 20 ns;
clk <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0101"); wait for 20 ns;
clk <= '0'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0000"); wait for 20 ns;
en <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1111"); wait for 20 ns;
wait;
end process stimulus;
end architecture test_reg4_behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc223.vhd | 4 | 1810 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc223.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00223ent IS
END c03s01b01x00p07n01i00223ent;
ARCHITECTURE c03s01b01x00p07n01i00223arch OF c03s01b01x00p07n01i00223ent IS
type ENUM1 is (FF, GG);
type ENUM2 is (GG, HH);
type ENUM3 is (FALSE);
type ENUM4 is ('A', 'Z');
BEGIN
TESTING: PROCESS
BEGIN
if (FALSE = FALSE) then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c03s01b01x00p07n01i00223"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c03s01b01x00p07n01i00223 - Literal cannot be determined."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00223arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd | 4 | 1393 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed;
use ieee_proposed.electrical_systems.all, ieee_proposed.mechanical_systems.all;
entity safety_switch is
port ( terminal neutral : electrical;
terminal relay_actuator : translational );
end entity safety_switch;
-- code from book
library ieee_proposed;
use ieee_proposed.electrical_systems.all, ieee_proposed.mechanical_systems.all;
architecture basic of safety_switch is
quantity neutral_potential across neutral to ground;
quantity relay_position across relay_actuator to anchor;
-- ...
begin
-- ...
end architecture basic;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc836.vhd | 4 | 1985 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc836.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b01x00p02n01i00836ent IS
END c01s03b01x00p02n01i00836ent;
ARCHITECTURE c01s03b01x00p02n01i00836arch OF c01s03b01x00p02n01i00836ent IS
BEGIN
DE : block
signal S1 : BOOLEAN;
begin
S1 <= true;
end block DE;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b01x00p02n01i00836 - Binding indications are not allowed in a configuration of a block."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p02n01i00836arch;
configuration c01s03b01x00p02n01i00836cfg of c01s03b01x00p02n01i00836ent is
for c01s03b01x00p02n01i00836arch
for DE use -- Failure_here : binding indications are not allowed in a
-- configuration of a block
entity work.entity0 open;
end for;
end c01s03b01x00p02n01i00836cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2443.vhd | 4 | 1724 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2443.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02443ent IS
type idx is range 0 to 15;
type aray is array (idx) of positive;
END c07s03b02x02p01n01i02443ent;
ARCHITECTURE c07s03b02x02p01n01i02443arch OF c07s03b02x02p01n01i02443ent IS
signal sig : aray := (others => 0);
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02443 - The expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02443arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc694.vhd | 4 | 2119 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc694.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:05 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00694ent IS
END c03s04b01x00p23n01i00694ent;
ARCHITECTURE c03s04b01x00p23n01i00694arch OF c03s04b01x00p23n01i00694ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of REAL;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.54";
-- Declare a variable.
constant CON : REAL := 1.0;
variable VAR : REAL := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00694 - The output file will tested by test file s010420.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00694arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/capacitor.vhd | 4 | 1453 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
generic ( cap : capacitance;
r_esr : resistance := 0.0;
v_ic : voltage := real'low );
port ( terminal p1, p2 : electrical );
end entity capacitor;
----------------------------------------------------------------
architecture esr of capacitor is
quantity v across i through p1 to p2;
quantity vc : voltage; -- Internal voltage across capacitor
begin
if domain = quiescent_domain and v_ic /= real'low use
vc == v_ic;
i == 0.0;
else
vc == v - (i * r_esr);
i == cap * vc'dot;
end use;
end architecture esr;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc916.vhd | 4 | 1863 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc916.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s03b00x00p10n01i00916pkg is
constant x : integer := 2;
end c10s03b00x00p10n01i00916pkg;
ENTITY c10s03b00x00p10n01i00916ent IS
END c10s03b00x00p10n01i00916ent;
ARCHITECTURE c10s03b00x00p10n01i00916arch OF c10s03b00x00p10n01i00916ent IS
-- selected use of package element
use work.c10s03b00x00p10n01i00916pkg.x;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( x=2 )
report "***PASSED TEST: c10s03b00x00p10n01i00916"
severity NOTE;
assert ( x=2 )
report "***FAILED TEST: c10s03b00x00p10n01i00916 - A declaration ina package can be made visible by selection."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p10n01i00916arch;
| gpl-2.0 |
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